]> git.sur5r.net Git - freertos/commitdiff
Rename STM32Cube to GCC for STM32L4 Discovery projects as GCC is
authorgaurav-aws <gaurav-aws@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 1 Jan 2020 00:35:42 +0000 (00:35 +0000)
committergaurav-aws <gaurav-aws@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 1 Jan 2020 00:35:42 +0000 (00:35 +0000)
the compiler used.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2788 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

222 files changed:
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Config/FreeRTOSConfig.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.cproject [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.project [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/STM32L475VGTX_FLASH.ld [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/startup_stm32l475vgtx.s [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/syscalls.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewd [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewp [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.eww [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/memfault_handler.s [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/startup_stm32l475xx.s [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/stm32l475xx_flash.icf [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/EventRecorderStub.scvd [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.sct [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvoptx [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvprojx [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/memfault_handler.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/startup_stm32l475xx.s [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/main.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/stm32l4xx_hal_conf.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/stm32l4xx_it.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/main.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_hal_msp.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_it.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/system_stm32l4xx.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_armcc.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_armclang.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_compiler.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_gcc.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_version.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_armv8mbl.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_armv8mml.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm0.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm0plus.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm1.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm23.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm3.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm33.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm4.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm7.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_sc000.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_sc300.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/mpu_armv7.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/mpu_armv8.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/tz_context.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c [new file with mode: 0644]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Config/FreeRTOSConfig.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewd [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewp [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.eww [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/memfault_handler.s [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/startup_stm32l475xx.s [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/stm32l475xx_flash.icf [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/EventRecorderStub.scvd [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.sct [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvoptx [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvprojx [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/memfault_handler.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/startup_stm32l475xx.s [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/.cproject [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/.project [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/STM32L475VGTX_FLASH.ld [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/memfault_handler.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/startup_stm32l475vgtx.s [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/syscalls.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/sysmem.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/main.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/stm32l4xx_hal_conf.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/stm32l4xx_it.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/main.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_hal_msp.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_it.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/system_stm32l4xx.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_armcc.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_armclang.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_compiler.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_gcc.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_version.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_armv8mbl.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_armv8mml.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm0.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm0plus.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm1.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm23.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm3.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm33.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm4.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm7.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_sc000.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_sc300.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/mpu_armv7.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/mpu_armv8.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/tz_context.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c [deleted file]
FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c [deleted file]

diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Config/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..c8f6553
--- /dev/null
@@ -0,0 +1,164 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html\r
+ *----------------------------------------------------------*/\r
+\r
+/* The MPU version of port.c includes and excludes functions depending on the\r
+settings within this file.  Therefore, to ensure all the functions in port.c\r
+build, this configuration file has all options turned on. */\r
+\r
+#define configUSE_PREEMPTION                                   1\r
+#define configTICK_RATE_HZ                                             ( 1000 )\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION        1\r
+#define configUSE_QUEUE_SETS                                   1\r
+#define configUSE_IDLE_HOOK                                            0\r
+#define configUSE_TICK_HOOK                                            0\r
+#define configCPU_CLOCK_HZ                                             48000000\r
+#define configMAX_PRIORITIES                                   ( 5 )\r
+#define configMINIMAL_STACK_SIZE                               ( ( unsigned short ) 256 )\r
+#define configTOTAL_HEAP_SIZE                                  ( ( size_t ) ( 16 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                                        ( 10 )\r
+#define configUSE_TRACE_FACILITY                               1\r
+#define configUSE_16_BIT_TICKS                                 0\r
+#define configIDLE_SHOULD_YIELD                                        1\r
+#define configUSE_MUTEXES                                              1\r
+#define configQUEUE_REGISTRY_SIZE                              5\r
+#define configCHECK_FOR_STACK_OVERFLOW                 2\r
+#define configUSE_RECURSIVE_MUTEXES                            1\r
+#define configUSE_MALLOC_FAILED_HOOK                   1\r
+#define configUSE_APPLICATION_TASK_TAG                 1\r
+#define configUSE_COUNTING_SEMAPHORES                  1\r
+#define configUSE_TICKLESS_IDLE                                        0\r
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS        2\r
+\r
+/* This demo shows the MPU being used without any dynamic memory allocation. */\r
+#define configSUPPORT_STATIC_ALLOCATION                        1\r
+#define configSUPPORT_DYNAMIC_ALLOCATION               1\r
+\r
+/* Run time stats gathering definitions. */\r
+#define configGENERATE_RUN_TIME_STATS                  1\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+#define portGET_RUN_TIME_COUNTER_VALUE()               0\r
+\r
+/* This demo makes use of one or more example stats formatting functions.  These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form.  See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES                                  0\r
+#define configMAX_CO_ROUTINE_PRIORITIES                ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS                                               1\r
+#define configTIMER_TASK_PRIORITY                              ( 2 )\r
+#define configTIMER_QUEUE_LENGTH                               5\r
+#define configTIMER_TASK_STACK_DEPTH                   ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet                               1\r
+#define INCLUDE_uxTaskPriorityGet                              1\r
+#define INCLUDE_vTaskDelete                                            1\r
+#define INCLUDE_vTaskCleanUpResources                  1\r
+#define INCLUDE_vTaskSuspend                                   1\r
+#define INCLUDE_vTaskDelayUntil                                        1\r
+#define INCLUDE_vTaskDelay                                             1\r
+#define INCLUDE_eTaskGetState                                  1\r
+#define INCLUDE_xTimerPendFunctionCall                 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder               1\r
+#define INCLUDE_xTaskGetHandle                                 1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle              1\r
+#define INCLUDE_xTaskGetIdleTaskHandle                 1\r
+#define INCLUDE_xTaskAbortDelay                                        1\r
+#define INCLUDE_xTaskGetSchedulerState                 1\r
+#define INCLUDE_xTaskGetIdleTaskHandle                 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark    1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+       /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+       #define configPRIO_BITS                                         __NVIC_PRIO_BITS\r
+#else\r
+       #define configPRIO_BITS                                         4       /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY                        0xf\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY   5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself.  These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY                                        ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY                   ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define xPortPendSVHandler                     PendSV_Handler\r
+#define vPortSVCHandler                        SVC_Handler\r
+#define xPortSysTickHandler            SysTick_Handler\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x )                      if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Ensure that system calls can only be made from kernel code. */\r
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY            1\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.c
new file mode 100644 (file)
index 0000000..81d6f5f
--- /dev/null
@@ -0,0 +1,117 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* App includes. */\r
+#include "app_main.h"\r
+\r
+/* Demo includes. */\r
+#include "mpu_demo.h"\r
+\r
+void app_main( void )\r
+{\r
+       /* Start the MPU demo. */\r
+       vStartMPUDemo();\r
+\r
+       /* Start the scheduler. */\r
+       vTaskStartScheduler();\r
+\r
+       /* Should not get here. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+       /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this\r
+       function will automatically get called if a task overflows its stack. */\r
+       ( void ) pxTask;\r
+       ( void ) pcTaskName;\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will\r
+       be called automatically if a call to pvPortMalloc() fails.  pvPortMalloc()\r
+       is called automatically when a task, queue or semaphore is created. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is\r
+used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Idle task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xIdleTaskTCB;\r
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
+\r
+       /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
+       state will be stored. */\r
+       *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+       /* Pass out the array that will be used as the Idle task's stack. */\r
+       *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+       /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+       Note that, as the array is necessarily of type StackType_t,\r
+       configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+       *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Timer task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xTimerTaskTCB;\r
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
+\r
+       /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+       task's state will be stored. */\r
+       *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+       /* Pass out the array that will be used as the Timer task's stack. */\r
+       *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+       /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+       Note that, as the array is necessarily of type StackType_t,\r
+       configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+       *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.h
new file mode 100644 (file)
index 0000000..64210fc
--- /dev/null
@@ -0,0 +1,36 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __APP_MAIN_H__\r
+#define __APP_MAIN_H__\r
+\r
+/**\r
+ * @brief Main app entry point.\r
+ */\r
+void app_main( void );\r
+\r
+#endif /* __APP_MAIN_H__ */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.c
new file mode 100644 (file)
index 0000000..039439a
--- /dev/null
@@ -0,0 +1,301 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/** ARMv7 MPU Details:\r
+ *\r
+ * - ARMv7 MPU requires that the size of a MPU region is a power of 2.\r
+ * - Smallest supported region size is 32 bytes.\r
+ * - Start address of a region must be aligned to an integer multiple of the\r
+ *   region size. For example, if the region size is 4 KB(0x1000), the starting\r
+ *   address must be N x 0x1000, where N is an integer.\r
+ */\r
+\r
+/**\r
+ * @brief Size of the shared memory region.\r
+ */\r
+#define SHARED_MEMORY_SIZE 32\r
+\r
+/**\r
+ * @brief Memory region shared between two tasks.\r
+ */\r
+static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) );\r
+\r
+/**\r
+ * @brief Memory region used to track Memory Fault intentionally caused by the\r
+ * RO Access task.\r
+ *\r
+ * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal\r
+ * memory. Illegal memory access causes Memory Fault and the fault handler\r
+ * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We\r
+ * recover gracefully from an expected fault by jumping to the next instruction.\r
+ *\r
+ * @note We are declaring a region of 32 bytes even though we need only one.\r
+ * The reason is that the smallest supported MPU region size is 32 bytes.\r
+ */\r
+static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 };\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Implements the task which has Read Only access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvROAccessTask( void * pvParameters );\r
+\r
+/**\r
+ * @brief Implements the task which has Read Write access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvRWAccessTask( void * pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvROAccessTask( void * pvParameters )\r
+{\r
+uint8_t ucVal;\r
+\r
+       /* Unused parameters. */\r
+       ( void ) pvParameters;\r
+\r
+       for( ; ; )\r
+       {\r
+               /* This task has RO access to ucSharedMemory and therefore it can read\r
+                * it but cannot modify it. */\r
+               ucVal = ucSharedMemory[ 0 ];\r
+\r
+               /* Silent compiler warnings about unused variables. */\r
+               ( void ) ucVal;\r
+\r
+               /* Since this task has Read Only access to the ucSharedMemory region,\r
+                * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]\r
+                * to 1 to tell the Memory Fault Handler that this is an expected fault.\r
+                * The handler will recover from this fault gracefully by jumping to the\r
+                * next instruction. */\r
+               ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+               /* Illegal access to generate Memory Fault. */\r
+               ucSharedMemory[ 0 ] = 0;\r
+\r
+               /* Ensure that the above line did generate MemFault and the fault\r
+                * handler did clear the  ucROTaskFaultTracker[ 0 ]. */\r
+               configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+\r
+               #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
+               {\r
+                       /* Generate an SVC to raise the privilege. Since privilege\r
+                        * escalation is only allowed from kernel code, this request must\r
+                        * get rejected and the task must remain unprivileged. As a result,\r
+                        * trying to write to ucSharedMemory will still result in Memory\r
+                        * Fault. */\r
+                       portRAISE_PRIVILEGE();\r
+\r
+                       /* Set ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault\r
+                        * Handler that this is an expected fault. The handler will then be\r
+                        * able to recover from this fault gracefully by jumping to the\r
+                        * next instruction.*/\r
+                       ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+                       /* The following must still result in Memory Fault since the task\r
+                        * is still running unprivileged. */\r
+                       ucSharedMemory[ 0 ] = 0;\r
+\r
+                       /* Ensure that the above line did generate MemFault and the fault\r
+                        * handler did clear the  ucROTaskFaultTracker[ 0 ]. */\r
+                       configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+               }\r
+               #else\r
+               {\r
+                       /* Generate an SVC to raise the privilege. Since\r
+                        * configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not enabled, the\r
+                        * task will be able to escalate privilege. */\r
+                       portRAISE_PRIVILEGE();\r
+\r
+                       /* At this point, the task is running privileged. The following\r
+                        * access must not result in Memory Fault. If something goes\r
+                        * wrong and we do get a fault, the execution will stop in fault\r
+                        * handler as ucROTaskFaultTracker[ 0 ] is not set (i.e.\r
+                        * un-expected fault). */\r
+                       ucSharedMemory[ 0 ] = 0;\r
+\r
+                       /* Lower down the privilege. */\r
+                       portSWITCH_TO_USER_MODE();\r
+\r
+                       /* Now the task is running unprivileged and therefore an attempt to\r
+                        * write to ucSharedMemory will result in a Memory Fault. Set\r
+                        * ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault Handler\r
+                        * that this is an expected fault. The handler will then be able to\r
+                        * recover from this fault gracefully by jumping to the next\r
+                        * instruction.*/\r
+                       ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+                       /* The following must result in Memory Fault since the task is now\r
+                        * running unprivileged. */\r
+                       ucSharedMemory[ 0 ] = 0;\r
+\r
+                       /* Ensure that the above line did generate MemFault and the fault\r
+                        * handler did clear the  ucROTaskFaultTracker[ 0 ]. */\r
+                       configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+               }\r
+               #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
+\r
+               /* Wait for a second. */\r
+               vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRWAccessTask( void * pvParameters )\r
+{\r
+       /* Unused parameters. */\r
+       ( void ) pvParameters;\r
+\r
+       for( ; ; )\r
+       {\r
+               /* This task has RW access to ucSharedMemory and therefore can write to\r
+                * it. */\r
+               ucSharedMemory[ 0 ] = 0;\r
+\r
+               /* Wait for a second. */\r
+               vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartMPUDemo( void )\r
+{\r
+/**\r
+ * Since stack of a task is protected using MPU, it must satisfy MPU\r
+ * requirements as mentioned at the top of this file.\r
+ */\r
+static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
+static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
+TaskParameters_t xROAccessTaskParameters =\r
+{\r
+       .pvTaskCode             = prvROAccessTask,\r
+       .pcName                 = "ROAccess",\r
+       .usStackDepth   = configMINIMAL_STACK_SIZE,\r
+       .pvParameters   = NULL,\r
+       .uxPriority             = tskIDLE_PRIORITY,\r
+       .puxStackBuffer = xROAccessTaskStack,\r
+       .xRegions               =       {\r
+                                                       { ucSharedMemory,                                       SHARED_MEMORY_SIZE,     portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER    },\r
+                                                       { ( void * ) ucROTaskFaultTracker,      SHARED_MEMORY_SIZE,     portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER                                                                },\r
+                                                       { 0,                                                            0,                                      0                                                                                                                                                                               },\r
+                                               }\r
+};\r
+TaskParameters_t xRWAccessTaskParameters =\r
+{\r
+       .pvTaskCode             = prvRWAccessTask,\r
+       .pcName                 = "RWAccess",\r
+       .usStackDepth   = configMINIMAL_STACK_SIZE,\r
+       .pvParameters   = NULL,\r
+       .uxPriority             = tskIDLE_PRIORITY,\r
+       .puxStackBuffer = xRWAccessTaskStack,\r
+       .xRegions               =       {\r
+                                                       { ucSharedMemory,       SHARED_MEMORY_SIZE,     portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER},\r
+                                                       { 0,                            0,                                      0                                                                                                               },\r
+                                                       { 0,                            0,                                      0                                                                                                               },\r
+                                               }\r
+};\r
+\r
+       /* Create an unprivileged task with RO access to ucSharedMemory. */\r
+       xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );\r
+\r
+       /* Create an unprivileged task with RW access to ucSharedMemory. */\r
+       xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )\r
+{\r
+uint32_t ulPC;\r
+uint16_t usOffendingInstruction;\r
+\r
+       /* Is this an expected fault? */\r
+       if( ucROTaskFaultTracker[ 0 ] == 1 )\r
+       {\r
+               /* Read program counter. */\r
+               ulPC = pulFaultStackAddress[ 6 ];\r
+\r
+               /* Read the offending instruction. */\r
+               usOffendingInstruction = *( uint16_t * )ulPC;\r
+\r
+               /* From ARM docs:\r
+                * If the value of bits[15:11] of the halfword being decoded is one of\r
+                * the following, the halfword is the first halfword of a 32-bit\r
+                * instruction:\r
+                * - 0b11101.\r
+                * - 0b11110.\r
+                * - 0b11111.\r
+                * Otherwise, the halfword is a 16-bit instruction.\r
+                */\r
+\r
+               /* Extract bits[15:11] of the offending instruction. */\r
+               usOffendingInstruction = usOffendingInstruction & 0xF800;\r
+               usOffendingInstruction = ( usOffendingInstruction >> 11 );\r
+\r
+               /* Determine if the offending instruction is a 32-bit instruction or\r
+                * a 16-bit instruction. */\r
+               if( usOffendingInstruction == 0x001F ||\r
+                       usOffendingInstruction == 0x001E ||\r
+                       usOffendingInstruction == 0x001D )\r
+               {\r
+                       /* Since the offending instruction is a 32-bit instruction,\r
+                        * increment the program counter by 4 to move to the next\r
+                        * instruction. */\r
+                       ulPC += 4;\r
+               }\r
+               else\r
+               {\r
+                       /* Since the offending instruction is a 16-bit instruction,\r
+                        * increment the program counter by 2 to move to the next\r
+                        * instruction. */\r
+                       ulPC += 2;\r
+               }\r
+\r
+               /* Save the new program counter on the stack. */\r
+               pulFaultStackAddress[ 6 ] = ulPC;\r
+\r
+               /* Mark the fault as handled. */\r
+               ucROTaskFaultTracker[ 0 ] = 0;\r
+       }\r
+       else\r
+       {\r
+               /* This is an unexpected fault - loop forever. */\r
+               for( ; ; )\r
+               {\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.h
new file mode 100644 (file)
index 0000000..e624027
--- /dev/null
@@ -0,0 +1,45 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __MPU_DEMO_H__\r
+#define __MPU_DEMO_H__\r
+\r
+/**\r
+ * @brief Creates all the tasks for MPU demo.\r
+ *\r
+ * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access\r
+ * to a shared memory region while the other has Read Write access. The task\r
+ * with Read Only access then tries to write to the shared memory which results\r
+ * in a Memory fault. The fault handler examines that it is the fault generated\r
+ * by the task with Read Only access and if so, it recovers from the fault\r
+ * greacefully by moving the Program Counter to the next instruction to the one\r
+ * which generated the fault. If any other memory access violation occurs, the\r
+ * fault handler will get stuck in an inifinite loop.\r
+ */\r
+void vStartMPUDemo( void );\r
+\r
+#endif /* __MPU_DEMO_H__ */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.cproject b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.cproject
new file mode 100644 (file)
index 0000000..7b75704
--- /dev/null
@@ -0,0 +1,218 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+       <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+               <cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567" moduleId="org.eclipse.cdt.core.settings" name="Debug">\r
+                               <externalSettings/>\r
+                               <extensions>\r
+                                       <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                               </extensions>\r
+                       </storageModule>\r
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+                               <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">\r
+                                       <folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567." name="/" resourcePath="">\r
+                                               <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.151851129" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">\r
+                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1653744095" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1681944964" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.8945483" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32L475VGTx" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1577664432" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1898127558" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.2108997886" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.2001329861" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1091286848" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="B-L475E-IOT01A1" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1037532678" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || B-L475E-IOT01A1 || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/CMSIS/Device/ST/STM32L4xx/Include | ../Drivers/STM32L4xx_HAL_Driver/Inc | ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy ||  ||  || USE_HAL_DRIVER | STM32L475xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>\r
+                                                       <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.426124029" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>\r
+                                                       <builder buildPath="${workspace_loc:/MPUDemo}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.2128934708" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.593503556" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1563011769" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>\r
+                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1415168970" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1478257368" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1219427263" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1995035483" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>\r
+                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.894694479" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">\r
+                                                                       <listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>\r
+                                                                       <listOptionValue builtIn="false" value="DEBUG"/>\r
+                                                                       <listOptionValue builtIn="false" value="STM32L475xx"/>\r
+                                                               </option>\r
+                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1719315783" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">\r
+                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/CMSIS/Include"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Core/Inc"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../Config"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../Demo"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../../../Source/include"/>\r
+                                                                       <listOptionValue builtIn="false" value="../../../../../Source/portable/GCC/ARM_CM4_MPU"/>\r
+                                                               </option>\r
+                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1633770288" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.427031050" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.308658656" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1955283688" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.909277324" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1282618698" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
+                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.422722354" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">\r
+                                                                       <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+                                                                       <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+                                                               </inputType>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.422475117" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.1092153668" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1299869734" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.2094239253" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1582287773" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.670067362" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1387142483" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1905141019" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.475038865" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1528425390" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>\r
+                                               </toolChain>\r
+                                       </folderInfo>\r
+                                       <folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567.19817946" name="/" resourcePath="Startup">\r
+                                               <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1794512592" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug" unusedChildren="">\r
+                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1653744095.169975929" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1653744095"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1681944964.946377599" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1681944964"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.8945483.262684702" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.8945483"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1577664432.427235401" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1577664432"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1898127558.560835881" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1898127558"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.2108997886.140706480" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.2108997886"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.2001329861.1331183223" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.2001329861"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1091286848.1020682886" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1091286848"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1037532678.1618834064" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1037532678"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.692231107" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.593503556"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.245264136" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1478257368"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.763839302" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.427031050"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.2022161589" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.909277324"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.778888425" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.422475117"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.728912733" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1299869734"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1521916125" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.2094239253"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.171635900" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1582287773"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.510896173" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.670067362"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1631939929" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1387142483"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1716690007" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1905141019"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.302624683" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.475038865"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1335461923" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1528425390"/>\r
+                                               </toolChain>\r
+                                       </folderInfo>\r
+                                       <sourceEntries>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Config"/>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Demo"/>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FreeRTOS"/>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>\r
+                                       </sourceEntries>\r
+                               </configuration>\r
+                       </storageModule>\r
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+               </cconfiguration>\r
+               <cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181" moduleId="org.eclipse.cdt.core.settings" name="Release">\r
+                               <externalSettings/>\r
+                               <extensions>\r
+                                       <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                               </extensions>\r
+                       </storageModule>\r
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+                               <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">\r
+                                       <folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181." name="/" resourcePath="">\r
+                                               <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1940388223" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">\r
+                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1164105596" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.969849987" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1143746181" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32L475VGTx" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1546095951" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.990303221" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.1809067860" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1254746839" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.204372413" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="B-L475E-IOT01A1" valueType="string"/>\r
+                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1344132037" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || B-L475E-IOT01A1 || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/CMSIS/Device/ST/STM32L4xx/Include | ../Drivers/STM32L4xx_HAL_Driver/Inc | ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy ||  ||  || USE_HAL_DRIVER | STM32L475xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>\r
+                                                       <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.605687567" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>\r
+                                                       <builder buildPath="${workspace_loc:/MPUDemo}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.924159257" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1457338997" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.625237364" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>\r
+                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.2042536896" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.236149066" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.883085407" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.895688238" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.o3" valueType="enumerated"/>\r
+                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1094376630" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">\r
+                                                                       <listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>\r
+                                                                       <listOptionValue builtIn="false" value="STM32L475xx"/>\r
+                                                               </option>\r
+                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1390012251" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">\r
+                                                                       <listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>\r
+                                                                       <listOptionValue builtIn="false" value="../Core/Inc"/>\r
+                                                                       <listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L4xx/Include"/>\r
+                                                                       <listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc"/>\r
+                                                                       <listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy"/>\r
+                                                               </option>\r
+                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.879588113" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1264350081" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.441749113" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.214554399" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.o3" valueType="enumerated"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.799737946" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1204679986" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
+                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.346247509" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">\r
+                                                                       <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+                                                                       <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+                                                               </inputType>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.504797300" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">\r
+                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.351476792" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
+                                                       </tool>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1580405798" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1682675601" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1606608792" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1519571618" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.516527531" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1259742608" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1453134435" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>\r
+                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1610429959" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>\r
+                                               </toolChain>\r
+                                       </folderInfo>\r
+                                       <sourceEntries>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>\r
+                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>\r
+                                       </sourceEntries>\r
+                               </configuration>\r
+                       </storageModule>\r
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+               </cconfiguration>\r
+       </storageModule>\r
+       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+               <project id="MPUDemo.null.551361165" name="MPUDemo"/>\r
+       </storageModule>\r
+       <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>\r
+       <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>\r
+       <storageModule moduleId="scannerConfiguration">\r
+               <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+               <scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1478257368;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1633770288">\r
+                       <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>\r
+               </scannerConfigBuildInfo>\r
+               <scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.236149066;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.879588113">\r
+                       <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>\r
+               </scannerConfigBuildInfo>\r
+       </storageModule>\r
+       <storageModule moduleId="refreshScope" versionNumber="2">\r
+               <configuration configurationName="Debug">\r
+                       <resource resourceType="PROJECT" workspacePath="/MPUDemo"/>\r
+               </configuration>\r
+               <configuration configurationName="Release">\r
+                       <resource resourceType="PROJECT" workspacePath="/MPUDemo"/>\r
+               </configuration>\r
+       </storageModule>\r
+</cproject>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.project
new file mode 100644 (file)
index 0000000..6f28b16
--- /dev/null
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>MPUDemo</name>\r
+       <comment></comment>\r
+       <projects>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+                       <triggers>clean,full,incremental,</triggers>\r
+                       <arguments>\r
+                       </arguments>\r
+               </buildCommand>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+                       <triggers>full,incremental,</triggers>\r
+                       <arguments>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>\r
+               <nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+               <nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature</nature>\r
+               <nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>\r
+               <nature>com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature</nature>\r
+               <nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>\r
+               <nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+       </natures>\r
+       <linkedResources>\r
+               <link>\r
+                       <name>Config</name>\r
+                       <type>2</type>\r
+                       <locationURI>PARENT-2-PROJECT_LOC/Config</locationURI>\r
+               </link>\r
+               <link>\r
+                       <name>Core</name>\r
+                       <type>2</type>\r
+                       <locationURI>PARENT-2-PROJECT_LOC/ST_Code/Core</locationURI>\r
+               </link>\r
+               <link>\r
+                       <name>Demo</name>\r
+                       <type>2</type>\r
+                       <locationURI>PARENT-2-PROJECT_LOC/Demo</locationURI>\r
+               </link>\r
+               <link>\r
+                       <name>Drivers</name>\r
+                       <type>2</type>\r
+                       <locationURI>PARENT-2-PROJECT_LOC/ST_Code/Drivers</locationURI>\r
+               </link>\r
+               <link>\r
+                       <name>FreeRTOS</name>\r
+                       <type>2</type>\r
+                       <locationURI>PARENT-4-PROJECT_LOC/Source</locationURI>\r
+               </link>\r
+       </linkedResources>\r
+       <filteredResources>\r
+               <filter>\r
+                       <id>1576807148309</id>\r
+                       <name>FreeRTOS/portable</name>\r
+                       <type>9</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-GCC</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1576807148309</id>\r
+                       <name>FreeRTOS/portable</name>\r
+                       <type>9</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-MemMang</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1576807148325</id>\r
+                       <name>FreeRTOS/portable</name>\r
+                       <type>9</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-Common</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1576807182461</id>\r
+                       <name>FreeRTOS/portable/GCC</name>\r
+                       <type>9</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-ARM_CM4_MPU</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1576807232013</id>\r
+                       <name>FreeRTOS/portable/MemMang</name>\r
+                       <type>5</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-heap_4.c</arguments>\r
+                       </matcher>\r
+               </filter>\r
+       </filteredResources>\r
+</projectDescription>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/STM32L475VGTX_FLASH.ld b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/STM32L475VGTX_FLASH.ld
new file mode 100644 (file)
index 0000000..6d41308
--- /dev/null
@@ -0,0 +1,249 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author             : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for B-L475E-IOT01A1 Board embedding STM32L475VGTx Device from STM32L4 series
+**                      1024Kbytes FLASH
+**                      96Kbytes RAM
+**                      32Kbytes RAM2
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);   /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;       /* required amount of heap  */
+_Min_Stack_Size = 0x400 ;      /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM  (xrw)   : ORIGIN = 0x20000000,  LENGTH = 96K
+  RAM2 (xrw)   : ORIGIN = 0x10000000,  LENGTH = 32K
+  FLASH        (rx)    : ORIGIN = 0x8000000,   LENGTH = 1024K
+}
+
+/* Initial 32K Flash is used to store kernel functions and
+ * initial 512 bytes of RAM is used to store kernel data. */
+__privileged_functions_region_size__  = 32K;
+__privileged_data_region_size__       = 512;
+
+__FLASH_segment_start__               = ORIGIN( FLASH );
+__FLASH_segment_end__                 = __FLASH_segment_start__ + LENGTH( FLASH );
+
+__SRAM_segment_start__                = ORIGIN( RAM );
+__SRAM_segment_end__                  = __SRAM_segment_start__ + LENGTH( RAM );
+
+__privileged_functions_start__        = __FLASH_segment_start__;
+__privileged_functions_end__          = __FLASH_segment_start__ + __privileged_functions_region_size__;
+
+__privileged_data_start__             = __SRAM_segment_start__;
+__privileged_data_end__               = __SRAM_segment_start__ + __privileged_data_region_size__;
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code and FreeRTOS kernel code are placed into privileged
+   * flash. */
+  .privileged_functions :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code. */
+    . = ALIGN(4);
+    *(privileged_functions)
+    . = ALIGN(4);
+    FILL(0xDEAD);
+    /* Ensure that non-privileged code is placed after the region reserved for
+     * privileged kernel code. */
+    /* Note that dot (.) actually refers to the byte offset from the start of
+     * the current section (.privileged_functions in this case). As a result,
+     * setting dot (.) to a value sets the size of the section. */
+    . = __privileged_functions_region_size__;
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    /* Place the FreeRTOS System Calls first in the unprivileged region. */
+    . = ALIGN(4);
+    __syscalls_flash_start__ = .;
+    *(freertos_system_calls)
+    __syscalls_flash_end__ = .;
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.privileged_data);
+
+  /* FreeRTOS kernel data. */
+  .privileged_data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* Create a global symbol at data start. */
+    *(privileged_data)
+    . = ALIGN(4);
+    FILL(0xDEAD);
+    /* Ensure that non-privileged data is placed after the region reserved for
+     * privileged kernel data. */
+    /* Note that dot (.) actually refers to the byte offset from the start of
+     * the current section (.privileged_data in this case). As a result, setting
+     * dot (.) to a value sets the size of the section. */
+    . = __privileged_data_region_size__;
+  } >RAM AT> FLASH
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c
new file mode 100644 (file)
index 0000000..f0e1b92
--- /dev/null
@@ -0,0 +1,48 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/**\r
+ * @brief Mem fault handler.\r
+ */\r
+void MemManage_Handler( void ) __attribute__ (( naked ));\r
+/*-----------------------------------------------------------*/\r
+\r
+void MemManage_Handler( void )\r
+{\r
+       __asm volatile\r
+       (\r
+               " tst lr, #4                                                                            \n"\r
+               " ite eq                                                                                        \n"\r
+               " mrseq r0, msp                                                                         \n"\r
+               " mrsne r0, psp                                                                         \n"\r
+               " ldr r1, handler_address_const                                         \n"\r
+               " bx r1                                                                                         \n"\r
+               "                                                                                                       \n"\r
+               " handler_address_const: .word vHandleMemoryFault       \n"\r
+       );\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/startup_stm32l475vgtx.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/startup_stm32l475vgtx.s
new file mode 100644 (file)
index 0000000..9e2b0ff
--- /dev/null
@@ -0,0 +1,505 @@
+/**\r
+  ******************************************************************************\r
+  * @file      startup_stm32l475xx.s\r
+  * @author    MCD Application Team\r
+  * @brief     STM32L475xx devices vector table for GCC toolchain.\r
+  *            This module performs:\r
+  *                - Set the initial SP\r
+  *                - Set the initial PC == Reset_Handler,\r
+  *                - Set the vector table entries with the exceptions ISR address,\r
+  *                - Configure the clock system  \r
+  *                - Branches to main in the C library (which eventually\r
+  *                  calls main()).\r
+  *            After Reset the Cortex-M4 processor is in Thread mode,\r
+  *            priority is Privileged, and the Stack is set to Main.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+  .syntax unified\r
+       .cpu cortex-m4\r
+       .fpu softvfp\r
+       .thumb\r
+\r
+.global        g_pfnVectors\r
+.global        Default_Handler\r
+\r
+/* start address for the initialization values of the .data section.\r
+defined in linker script */\r
+.word  _sidata\r
+/* start address for the .data section. defined in linker script */\r
+.word  _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word  _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word  _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word  _ebss\r
+\r
+.equ  BootRAM,        0xF1E0F85F\r
+/**\r
+ * @brief  This is the code that gets called when the processor first\r
+ *          starts execution following a reset event. Only the absolutely\r
+ *          necessary set is performed, after which the application\r
+ *          supplied main() routine is called.\r
+ * @param  None\r
+ * @retval : None\r
+*/\r
+\r
+    .section   .text.Reset_Handler\r
+       .weak   Reset_Handler\r
+       .type   Reset_Handler, %function\r
+Reset_Handler:\r
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */\r
+\r
+/* Copy the data segment initializers from flash to SRAM */\r
+  movs r1, #0\r
+  b    LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+       ldr     r3, =_sidata\r
+       ldr     r3, [r3, r1]\r
+       str     r3, [r0, r1]\r
+       adds    r1, r1, #4\r
+\r
+LoopCopyDataInit:\r
+       ldr     r0, =_sdata\r
+       ldr     r3, =_edata\r
+       adds    r2, r0, r1\r
+       cmp     r2, r3\r
+       bcc     CopyDataInit\r
+       ldr     r2, =_sbss\r
+       b       LoopFillZerobss\r
+/* Zero fill the bss segment. */\r
+FillZerobss:\r
+       movs    r3, #0\r
+       str     r3, [r2], #4\r
+\r
+LoopFillZerobss:\r
+       ldr     r3, = _ebss\r
+       cmp     r2, r3\r
+       bcc     FillZerobss\r
+\r
+/* Call the clock system intitialization function.*/\r
+    bl  SystemInit\r
+/* Call static constructors */\r
+    bl __libc_init_array\r
+/* Call the application's entry point.*/\r
+       bl      main\r
+\r
+LoopForever:\r
+    b LoopForever\r
+    \r
+.size  Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief  This is the code that gets called when the processor receives an\r
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving\r
+ *         the system state for examination by a debugger.\r
+ *\r
+ * @param  None\r
+ * @retval : None\r
+*/\r
+    .section   .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+       b       Infinite_Loop\r
+       .size   Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+******************************************************************************/\r
+       .section        .isr_vector,"a",%progbits\r
+       .type   g_pfnVectors, %object\r
+       .size   g_pfnVectors, .-g_pfnVectors\r
+\r
+\r
+g_pfnVectors:\r
+       .word   _estack\r
+       .word   Reset_Handler\r
+       .word   NMI_Handler\r
+       .word   HardFault_Handler\r
+       .word   MemManage_Handler\r
+       .word   BusFault_Handler\r
+       .word   UsageFault_Handler\r
+       .word   0\r
+       .word   0\r
+       .word   0\r
+       .word   0\r
+       .word   SVC_Handler\r
+       .word   DebugMon_Handler\r
+       .word   0\r
+       .word   PendSV_Handler\r
+       .word   SysTick_Handler\r
+       .word   WWDG_IRQHandler\r
+       .word   PVD_PVM_IRQHandler\r
+       .word   TAMP_STAMP_IRQHandler\r
+       .word   RTC_WKUP_IRQHandler\r
+       .word   FLASH_IRQHandler\r
+       .word   RCC_IRQHandler\r
+       .word   EXTI0_IRQHandler\r
+       .word   EXTI1_IRQHandler\r
+       .word   EXTI2_IRQHandler\r
+       .word   EXTI3_IRQHandler\r
+       .word   EXTI4_IRQHandler\r
+       .word   DMA1_Channel1_IRQHandler\r
+       .word   DMA1_Channel2_IRQHandler\r
+       .word   DMA1_Channel3_IRQHandler\r
+       .word   DMA1_Channel4_IRQHandler\r
+       .word   DMA1_Channel5_IRQHandler\r
+       .word   DMA1_Channel6_IRQHandler\r
+       .word   DMA1_Channel7_IRQHandler\r
+       .word   ADC1_2_IRQHandler\r
+       .word   CAN1_TX_IRQHandler\r
+       .word   CAN1_RX0_IRQHandler\r
+       .word   CAN1_RX1_IRQHandler\r
+       .word   CAN1_SCE_IRQHandler\r
+       .word   EXTI9_5_IRQHandler\r
+       .word   TIM1_BRK_TIM15_IRQHandler\r
+       .word   TIM1_UP_TIM16_IRQHandler\r
+       .word   TIM1_TRG_COM_TIM17_IRQHandler\r
+       .word   TIM1_CC_IRQHandler\r
+       .word   TIM2_IRQHandler\r
+       .word   TIM3_IRQHandler\r
+       .word   TIM4_IRQHandler\r
+       .word   I2C1_EV_IRQHandler\r
+       .word   I2C1_ER_IRQHandler\r
+       .word   I2C2_EV_IRQHandler\r
+       .word   I2C2_ER_IRQHandler\r
+       .word   SPI1_IRQHandler\r
+       .word   SPI2_IRQHandler\r
+       .word   USART1_IRQHandler\r
+       .word   USART2_IRQHandler\r
+       .word   USART3_IRQHandler\r
+       .word   EXTI15_10_IRQHandler\r
+       .word   RTC_Alarm_IRQHandler\r
+       .word   DFSDM1_FLT3_IRQHandler\r
+       .word   TIM8_BRK_IRQHandler\r
+       .word   TIM8_UP_IRQHandler\r
+       .word   TIM8_TRG_COM_IRQHandler\r
+       .word   TIM8_CC_IRQHandler\r
+       .word   ADC3_IRQHandler\r
+       .word   FMC_IRQHandler\r
+       .word   SDMMC1_IRQHandler\r
+       .word   TIM5_IRQHandler\r
+       .word   SPI3_IRQHandler\r
+       .word   UART4_IRQHandler\r
+       .word   UART5_IRQHandler\r
+       .word   TIM6_DAC_IRQHandler\r
+       .word   TIM7_IRQHandler\r
+       .word   DMA2_Channel1_IRQHandler\r
+       .word   DMA2_Channel2_IRQHandler\r
+       .word   DMA2_Channel3_IRQHandler\r
+       .word   DMA2_Channel4_IRQHandler\r
+       .word   DMA2_Channel5_IRQHandler\r
+       .word   DFSDM1_FLT0_IRQHandler\r
+       .word   DFSDM1_FLT1_IRQHandler\r
+       .word   DFSDM1_FLT2_IRQHandler\r
+       .word   COMP_IRQHandler\r
+       .word   LPTIM1_IRQHandler\r
+       .word   LPTIM2_IRQHandler\r
+       .word   OTG_FS_IRQHandler\r
+       .word   DMA2_Channel6_IRQHandler\r
+       .word   DMA2_Channel7_IRQHandler\r
+       .word   LPUART1_IRQHandler\r
+       .word   QUADSPI_IRQHandler\r
+       .word   I2C3_EV_IRQHandler\r
+       .word   I2C3_ER_IRQHandler\r
+       .word   SAI1_IRQHandler\r
+       .word   SAI2_IRQHandler\r
+       .word   SWPMI1_IRQHandler\r
+       .word   TSC_IRQHandler\r
+       .word 0\r
+       .word 0\r
+       .word   RNG_IRQHandler\r
+       .word   FPU_IRQHandler\r
+\r
+\r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler.\r
+* As they are weak aliases, any function with the same name will override\r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+\r
+  .weak        NMI_Handler\r
+       .thumb_set NMI_Handler,Default_Handler\r
+\r
+  .weak        HardFault_Handler\r
+       .thumb_set HardFault_Handler,Default_Handler\r
+\r
+  .weak        MemManage_Handler\r
+       .thumb_set MemManage_Handler,Default_Handler\r
+\r
+  .weak        BusFault_Handler\r
+       .thumb_set BusFault_Handler,Default_Handler\r
+\r
+       .weak   UsageFault_Handler\r
+       .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+       .weak   SVC_Handler\r
+       .thumb_set SVC_Handler,Default_Handler\r
+\r
+       .weak   DebugMon_Handler\r
+       .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+       .weak   PendSV_Handler\r
+       .thumb_set PendSV_Handler,Default_Handler\r
+\r
+       .weak   SysTick_Handler\r
+       .thumb_set SysTick_Handler,Default_Handler\r
+\r
+       .weak   WWDG_IRQHandler\r
+       .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+       .weak   PVD_PVM_IRQHandler\r
+       .thumb_set PVD_PVM_IRQHandler,Default_Handler\r
+\r
+       .weak   TAMP_STAMP_IRQHandler\r
+       .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r
+\r
+       .weak   RTC_WKUP_IRQHandler\r
+       .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
+\r
+       .weak   FLASH_IRQHandler\r
+       .thumb_set FLASH_IRQHandler,Default_Handler\r
+\r
+       .weak   RCC_IRQHandler\r
+       .thumb_set RCC_IRQHandler,Default_Handler\r
+\r
+       .weak   EXTI0_IRQHandler\r
+       .thumb_set EXTI0_IRQHandler,Default_Handler\r
+\r
+       .weak   EXTI1_IRQHandler\r
+       .thumb_set EXTI1_IRQHandler,Default_Handler\r
+\r
+       .weak   EXTI2_IRQHandler\r
+       .thumb_set EXTI2_IRQHandler,Default_Handler\r
+\r
+       .weak   EXTI3_IRQHandler\r
+       .thumb_set EXTI3_IRQHandler,Default_Handler\r
+\r
+       .weak   EXTI4_IRQHandler\r
+       .thumb_set EXTI4_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA1_Channel1_IRQHandler\r
+       .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA1_Channel2_IRQHandler\r
+       .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA1_Channel3_IRQHandler\r
+       .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA1_Channel4_IRQHandler\r
+       .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA1_Channel5_IRQHandler\r
+       .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA1_Channel6_IRQHandler\r
+       .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA1_Channel7_IRQHandler\r
+       .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
+\r
+       .weak   ADC1_2_IRQHandler\r
+       .thumb_set ADC1_2_IRQHandler,Default_Handler\r
+\r
+       .weak   CAN1_TX_IRQHandler\r
+       .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
+\r
+       .weak   CAN1_RX0_IRQHandler\r
+       .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
+\r
+       .weak   CAN1_RX1_IRQHandler\r
+       .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+\r
+       .weak   CAN1_SCE_IRQHandler\r
+       .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+\r
+       .weak   EXTI9_5_IRQHandler\r
+       .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM1_BRK_TIM15_IRQHandler\r
+       .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM1_UP_TIM16_IRQHandler\r
+       .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM1_TRG_COM_TIM17_IRQHandler\r
+       .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM1_CC_IRQHandler\r
+       .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM2_IRQHandler\r
+       .thumb_set TIM2_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM3_IRQHandler\r
+       .thumb_set TIM3_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM4_IRQHandler\r
+       .thumb_set TIM4_IRQHandler,Default_Handler\r
+\r
+       .weak   I2C1_EV_IRQHandler\r
+       .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+\r
+       .weak   I2C1_ER_IRQHandler\r
+       .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+\r
+       .weak   I2C2_EV_IRQHandler\r
+       .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+\r
+       .weak   I2C2_ER_IRQHandler\r
+       .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+\r
+       .weak   SPI1_IRQHandler\r
+       .thumb_set SPI1_IRQHandler,Default_Handler\r
+\r
+       .weak   SPI2_IRQHandler\r
+       .thumb_set SPI2_IRQHandler,Default_Handler\r
+\r
+       .weak   USART1_IRQHandler\r
+       .thumb_set USART1_IRQHandler,Default_Handler\r
+\r
+       .weak   USART2_IRQHandler\r
+       .thumb_set USART2_IRQHandler,Default_Handler\r
+\r
+       .weak   USART3_IRQHandler\r
+       .thumb_set USART3_IRQHandler,Default_Handler\r
+\r
+       .weak   EXTI15_10_IRQHandler\r
+       .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+\r
+       .weak   RTC_Alarm_IRQHandler\r
+       .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
+\r
+       .weak   DFSDM1_FLT3_IRQHandler\r
+       .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM8_BRK_IRQHandler\r
+       .thumb_set TIM8_BRK_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM8_UP_IRQHandler\r
+       .thumb_set TIM8_UP_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM8_TRG_COM_IRQHandler\r
+       .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM8_CC_IRQHandler\r
+       .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
+\r
+       .weak   ADC3_IRQHandler\r
+       .thumb_set ADC3_IRQHandler,Default_Handler\r
+\r
+       .weak   FMC_IRQHandler\r
+       .thumb_set FMC_IRQHandler,Default_Handler\r
+\r
+       .weak   SDMMC1_IRQHandler\r
+       .thumb_set SDMMC1_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM5_IRQHandler\r
+       .thumb_set TIM5_IRQHandler,Default_Handler\r
+\r
+       .weak   SPI3_IRQHandler\r
+       .thumb_set SPI3_IRQHandler,Default_Handler\r
+\r
+       .weak   UART4_IRQHandler\r
+       .thumb_set UART4_IRQHandler,Default_Handler\r
+\r
+       .weak   UART5_IRQHandler\r
+       .thumb_set UART5_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM6_DAC_IRQHandler\r
+       .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r
+\r
+       .weak   TIM7_IRQHandler\r
+       .thumb_set TIM7_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA2_Channel1_IRQHandler\r
+       .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA2_Channel2_IRQHandler\r
+       .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA2_Channel3_IRQHandler\r
+       .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA2_Channel4_IRQHandler\r
+       .thumb_set DMA2_Channel4_IRQHandler,Default_Handler\r
+\r
+       .weak   DMA2_Channel5_IRQHandler\r
+       .thumb_set DMA2_Channel5_IRQHandler,Default_Handler\r
+\r
+       .weak   DFSDM1_FLT0_IRQHandler\r
+       .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler       \r
+       \r
+       .weak   DFSDM1_FLT1_IRQHandler\r
+       .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler       \r
+       \r
+       .weak   DFSDM1_FLT2_IRQHandler\r
+       .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler       \r
+       \r
+       .weak   COMP_IRQHandler\r
+       .thumb_set COMP_IRQHandler,Default_Handler\r
+       \r
+       .weak   LPTIM1_IRQHandler\r
+       .thumb_set LPTIM1_IRQHandler,Default_Handler\r
+       \r
+       .weak   LPTIM2_IRQHandler\r
+       .thumb_set LPTIM2_IRQHandler,Default_Handler    \r
+       \r
+       .weak   OTG_FS_IRQHandler\r
+       .thumb_set OTG_FS_IRQHandler,Default_Handler    \r
+       \r
+       .weak   DMA2_Channel6_IRQHandler\r
+       .thumb_set DMA2_Channel6_IRQHandler,Default_Handler     \r
+       \r
+       .weak   DMA2_Channel7_IRQHandler\r
+       .thumb_set DMA2_Channel7_IRQHandler,Default_Handler     \r
+       \r
+       .weak   LPUART1_IRQHandler\r
+       .thumb_set LPUART1_IRQHandler,Default_Handler   \r
+       \r
+       .weak   QUADSPI_IRQHandler\r
+       .thumb_set QUADSPI_IRQHandler,Default_Handler   \r
+       \r
+       .weak   I2C3_EV_IRQHandler\r
+       .thumb_set I2C3_EV_IRQHandler,Default_Handler   \r
+       \r
+       .weak   I2C3_ER_IRQHandler\r
+       .thumb_set I2C3_ER_IRQHandler,Default_Handler   \r
+       \r
+       .weak   SAI1_IRQHandler\r
+       .thumb_set SAI1_IRQHandler,Default_Handler\r
+       \r
+       .weak   SAI2_IRQHandler\r
+       .thumb_set SAI2_IRQHandler,Default_Handler\r
+       \r
+       .weak   SWPMI1_IRQHandler\r
+       .thumb_set SWPMI1_IRQHandler,Default_Handler\r
+       \r
+       .weak   TSC_IRQHandler\r
+       .thumb_set TSC_IRQHandler,Default_Handler\r
+       \r
+       .weak   RNG_IRQHandler\r
+       .thumb_set RNG_IRQHandler,Default_Handler\r
+       \r
+       .weak   FPU_IRQHandler\r
+       .thumb_set FPU_IRQHandler,Default_Handler\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/syscalls.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/syscalls.c
new file mode 100644 (file)
index 0000000..9f32dad
--- /dev/null
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author         : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+**                       For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+       return 1;
+}
+
+int _kill(int pid, int sig)
+{
+       errno = EINVAL;
+       return -1;
+}
+
+void _exit (int status)
+{
+       _kill(status, -1);
+       while (1) {}            /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+       int DataIdx;
+
+       for (DataIdx = 0; DataIdx < len; DataIdx++)
+       {
+               *ptr++ = __io_getchar();
+       }
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+       int DataIdx;
+
+       for (DataIdx = 0; DataIdx < len; DataIdx++)
+       {
+               __io_putchar(*ptr++);
+       }
+       return len;
+}
+
+int _close(int file)
+{
+       return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+       st->st_mode = S_IFCHR;
+       return 0;
+}
+
+int _isatty(int file)
+{
+       return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+       return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+       /* Pretend like we always fail */
+       return -1;
+}
+
+int _wait(int *status)
+{
+       errno = ECHILD;
+       return -1;
+}
+
+int _unlink(char *name)
+{
+       errno = ENOENT;
+       return -1;
+}
+
+int _times(struct tms *buf)
+{
+       return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+       st->st_mode = S_IFCHR;
+       return 0;
+}
+
+int _link(char *old, char *new)
+{
+       errno = EMLINK;
+       return -1;
+}
+
+int _fork(void)
+{
+       errno = EAGAIN;
+       return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+       errno = ENOMEM;
+       return -1;
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c
new file mode 100644 (file)
index 0000000..e5e1bc2
--- /dev/null
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author         : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+**                       For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <errno.h>
+#include <stdio.h>
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+       extern char end asm("end");
+       static char *heap_end;
+       char *prev_heap_end;
+
+       if (heap_end == 0)
+               heap_end = &end;
+
+       prev_heap_end = heap_end;
+       if (heap_end + incr > stack_ptr)
+       {
+               errno = ENOMEM;
+               return (caddr_t) -1;
+       }
+
+       heap_end += incr;
+
+       return (caddr_t) prev_heap_end;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewd
new file mode 100644 (file)
index 0000000..f9ec12d
--- /dev/null
@@ -0,0 +1,1419 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<project>\r
+       <fileVersion>3</fileVersion>\r
+       <configuration>\r
+               <name>MPUDemo</name>\r
+               <toolchain>\r
+                       <name>ARM</name>\r
+               </toolchain>\r
+               <debug>1</debug>\r
+               <settings>\r
+                       <name>C-SPY</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>29</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>CInput</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CEndian</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CProcessor</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCVariant</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>MacOverride</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>MacFile</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>MemOverride</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>MemFile</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>RunToEnable</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RunToName</name>\r
+                                       <state>main</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CExtraOptionsCheck</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CExtraOptions</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CFpuProcessor</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDDFArgumentProducer</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDownloadSuppressDownload</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDownloadVerifyAll</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCProductVersion</name>\r
+                                       <state>7.10.3.6927</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDynDriverList</name>\r
+                                       <state>STLINK_ID</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCLastSavedByProductVersion</name>\r
+                                       <state>8.20.1.14181</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>UseFlashLoader</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CLowLevel</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCBE8Slave</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>MacFile2</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CDevice</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>FlashLoadersV3</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesSuppressCheck1</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesPath1</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesSuppressCheck2</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesPath2</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesSuppressCheck3</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesPath3</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OverrideDefFlashBoard</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesOffset1</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesOffset2</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesOffset3</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesUse1</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesUse2</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCImagesUse3</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDeviceConfigMacroFile</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDebuggerExtraOption</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCAllMTBOptions</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCMulticoreNrOfCores</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCMulticoreMaster</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCMulticorePort</name>\r
+                                       <state>53461</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCMulticoreWorkspace</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCMulticoreSlaveProject</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCMulticoreSlaveConfiguration</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDownloadExtraImage</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCAttachSlave</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>MassEraseBeforeFlashing</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>ARMSIM_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>1</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>OCSimDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCSimEnablePSP</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCSimPspOverrideConfig</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCSimPspConfigFile</name>\r
+                                       <state />\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>CADI_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>0</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>CCadiMemory</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>Fast Model</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCADILogFileCheck</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCADILogFileEditB</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>CMSISDAP_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>4</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>CatchSFERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCIarProbeScriptFile</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPResetList</name>\r
+                                       <version>1</version>\r
+                                       <state>10</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPHWResetDuration</name>\r
+                                       <state>300</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPHWResetDelay</name>\r
+                                       <state>200</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPDoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPLogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPInterfaceRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPInterfaceCmdLine</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPMultiTargetEnable</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPMultiTarget</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPJtagSpeedList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPBreakpointRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+                                       <state>_call_main</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchReset</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchUndef</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchSWI</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchData</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchPrefetch</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchIRQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchFIQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchCORERESET</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchMMERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchNOCPERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchCHKERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchSTATERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchBUSERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchINTERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchHARDERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchDummy</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPMultiCPUEnable</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPMultiCPUNumber</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCProbeCfgOverride</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCProbeConfig</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPProbeConfigRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CMSISDAPSelectedCPUBehaviour</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>ICpuName</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCJetEmuParams</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCMSISDAPUsbSerialNo</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCMSISDAPUsbSerialNoSelect</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>GDBSERVER_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>0</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>TCPIP</name>\r
+                                       <state>aaa.bbb.ccc.ddd</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>DoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>LogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJTagBreakpointRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJTagDoUpdateBreakpoints</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJTagUpdateBreakpoints</name>\r
+                                       <state>_call_main</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>IJET_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>8</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>CatchSFERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCIarProbeScriptFile</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetResetList</name>\r
+                                       <version>1</version>\r
+                                       <state>10</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetHWResetDuration</name>\r
+                                       <state>300</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetHWResetDelay</name>\r
+                                       <state>200</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetPowerFromProbe</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetPowerRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetDoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetLogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetInterfaceRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetInterfaceCmdLine</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetMultiTargetEnable</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetMultiTarget</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetScanChainNonARMDevices</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetIRLength</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetJtagSpeedList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetProtocolRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetSwoPin</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetCpuClockEdit</name>\r
+                                       <state>72.0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetSwoPrescalerList</name>\r
+                                       <version>1</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetBreakpointRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetRestoreBreakpointsCheck</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetUpdateBreakpointsEdit</name>\r
+                                       <state>_call_main</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchReset</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchUndef</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchSWI</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchData</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchPrefetch</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchIRQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>RDICatchFIQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchCORERESET</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchMMERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchNOCPERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchCHKERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchSTATERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchBUSERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchINTERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchHARDERR</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CatchDummy</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCProbeCfgOverride</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCProbeConfig</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetProbeConfigRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetMultiCPUEnable</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetMultiCPUNumber</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetSelectedCPUBehaviour</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>ICpuName</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCJetEmuParams</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetPreferETB</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetTraceSettingsList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>IjetTraceSizeList</name>\r
+                                       <version>0</version>\r
+                                       <state>4</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>FlashBoardPathSlave</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCIjetUsbSerialNo</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCIjetUsbSerialNoSelect</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>JLINK_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>16</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>CCCatchSFERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>JLinkSpeed</name>\r
+                                       <state>1000</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkDoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkLogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkHWResetDelay</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>JLinkInitialSpeed</name>\r
+                                       <state>1000</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCDoJlinkMultiTarget</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCScanChainNonARMDevices</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkMultiTarget</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkIRLength</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkCommRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkTCPIP</name>\r
+                                       <state>aaa.bbb.ccc.ddd</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkSpeedRadioV2</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCUSBDevice</name>\r
+                                       <version>1</version>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCRDICatchReset</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCRDICatchUndef</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCRDICatchSWI</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCRDICatchData</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCRDICatchPrefetch</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCRDICatchIRQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCRDICatchFIQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkBreakpointRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkDoUpdateBreakpoints</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkUpdateBreakpoints</name>\r
+                                       <state>_call_main</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkInterfaceRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkResetList</name>\r
+                                       <version>6</version>\r
+                                       <state>7</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkInterfaceCmdLine</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchCORERESET</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchMMERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchNOCPERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchCHRERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchSTATERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchBUSERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchINTERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchHARDERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCatchDummy</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCJLinkScriptFile</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkUsbSerialNo</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCTcpIpAlt</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJLinkTcpIpSerialNo</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCpuClockEdit</name>\r
+                                       <state>72.0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSwoClockAuto</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSwoClockEdit</name>\r
+                                       <state>2000</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCJLinkTraceSource</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCJLinkTraceSourceDummy</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCJLinkDeviceName</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>LMIFTDI_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>2</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>LmiftdiSpeed</name>\r
+                                       <state>500</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCLmiftdiDoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCLmiftdiLogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCLmiFtdiInterfaceRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCLmiFtdiInterfaceCmdLine</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>PEMICRO_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>3</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCJPEMicroShowSettings</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>DoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>LogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>STLINK_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>4</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkInterfaceRadio</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkInterfaceCmdLine</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkResetList</name>\r
+                                       <version>3</version>\r
+                                       <state>4</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCCpuClockEdit</name>\r
+                                       <state>80.0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSwoClockAuto</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSwoClockEdit</name>\r
+                                       <state>2000</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>DoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>LogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkDoUpdateBreakpoints</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkUpdateBreakpoints</name>\r
+                                       <state>_call_main</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchCORERESET</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchMMERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchNOCPERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchCHRERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchSTATERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchBUSERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchINTERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchSFERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchHARDERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkCatchDummy</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkUsbSerialNo</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkUsbSerialNoSelect</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkJtagSpeedList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkDAPNumber</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCSTLinkDebugAccessPortRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>THIRDPARTY_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>0</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>CThirdPartyDriverDll</name>\r
+                                       <state>###Uninitialized###</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CThirdPartyLogFileCheck</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CThirdPartyLogFileEditB</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>TIFET_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>1</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetResetList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetInterfaceRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetInterfaceCmdLine</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetTargetVccTypeDefault</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetTargetVoltage</name>\r
+                                       <state>###Uninitialized###</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetVCCDefault</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetTargetSettlingtime</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetRadioJtagSpeedType</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetConnection</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetUsbComPort</name>\r
+                                       <state>Automatic</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetAllowAccessToBSL</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetDoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetLogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCMSPFetRadioEraseFlash</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <settings>\r
+                       <name>XDS100_ID</name>\r
+                       <archiveVersion>2</archiveVersion>\r
+                       <data>\r
+                               <version>6</version>\r
+                               <wantNonLocal>1</wantNonLocal>\r
+                               <debug>1</debug>\r
+                               <option>\r
+                                       <name>OCDriverInfo</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>TIPackageOverride</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>TIPackage</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>BoardFile</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>DoLogfile</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>LogFile</name>\r
+                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100BreakpointRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100DoUpdateBreakpoints</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100UpdateBreakpoints</name>\r
+                                       <state>_call_main</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchReset</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchUndef</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchSWI</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchData</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchPrefetch</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchIRQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchFIQ</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchCORERESET</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchMMERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchNOCPERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchCHRERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchSTATERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchBUSERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchINTERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchSFERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchHARDERR</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CatchDummy</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100CpuClockEdit</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100SwoClockAuto</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100SwoClockEdit</name>\r
+                                       <state>1000</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100HWResetDelay</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100ResetList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100UsbSerialNo</name>\r
+                                       <state />\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100UsbSerialNoSelect</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100JtagSpeedList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100InterfaceRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100InterfaceCmdLine</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100ProbeList</name>\r
+                                       <version>0</version>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100SWOPortRadio</name>\r
+                                       <state>0</state>\r
+                               </option>\r
+                               <option>\r
+                                       <name>CCXds100SWOPort</name>\r
+                                       <state>1</state>\r
+                               </option>\r
+                       </data>\r
+               </settings>\r
+               <debuggerPlugins>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+                               <loadFlag>1</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+                       <plugin>\r
+                               <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+                               <loadFlag>0</loadFlag>\r
+                       </plugin>\r
+               </debuggerPlugins>\r
+       </configuration>\r
+</project>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewp
new file mode 100644 (file)
index 0000000..7344028
--- /dev/null
@@ -0,0 +1,1212 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<project>\r
+    <fileVersion>3</fileVersion>\r
+    <configuration>\r
+        <name>MPUDemo</name>\r
+        <toolchain>\r
+            <name>ARM</name>\r
+        </toolchain>\r
+        <debug>1</debug>\r
+        <settings>\r
+            <name>General</name>\r
+            <archiveVersion>3</archiveVersion>\r
+            <data>\r
+                <version>31</version>\r
+                <wantNonLocal>1</wantNonLocal>\r
+                <debug>1</debug>\r
+                <option>\r
+                    <name>ExePath</name>\r
+                    <state>Debug/Objects</state>\r
+                </option>\r
+                <option>\r
+                    <name>ObjPath</name>\r
+                    <state>Debug/Objects</state>\r
+                </option>\r
+                <option>\r
+                    <name>ListPath</name>\r
+                    <state>Debug/Listings</state>\r
+                </option>\r
+                <option>\r
+                    <name>GEndianMode</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>Input description</name>\r
+                    <state>Full formatting, with multibyte support.</state>\r
+                </option>\r
+                <option>\r
+                    <name>Output description</name>\r
+                    <state>Full formatting, with multibyte support.</state>\r
+                </option>\r
+                <option>\r
+                    <name>GOutputBinary</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGCoreOrChip</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>GRuntimeLibSelect</name>\r
+                    <version>0</version>\r
+                    <state>2</state>\r
+                </option>\r
+                <option>\r
+                    <name>GRuntimeLibSelectSlave</name>\r
+                    <version>0</version>\r
+                    <state>2</state>\r
+                </option>\r
+                <option>\r
+                    <name>RTDescription</name>\r
+                    <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGProductVersion</name>\r
+                    <state>4.41A</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGLastSavedByProductVersion</name>\r
+                    <state>8.30.2.18207</state>\r
+                </option>\r
+                <option>\r
+                    <name>GeneralEnableMisra</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>GeneralMisraVerbose</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGChipSelectEditMenu</name>\r
+                    <state>STM32L475VG ST STM32L475VG</state>\r
+                </option>\r
+                <option>\r
+                    <name>GenLowLevelInterface</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>GEndianModeBE</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGBufferedTerminalOutput</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>GenStdoutInterface</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>GeneralMisraRules98</name>\r
+                    <version>0</version>\r
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+                </option>\r
+                <option>\r
+                    <name>GeneralMisraVer</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>GeneralMisraRules04</name>\r
+                    <version>0</version>\r
+                    <state>011111111111111110111111111111011111111111111011110100111111111111111111111111111111111111111111101111111111111011111111111111111111111111111</state>\r
+                </option>\r
+                <option>\r
+                    <name>RTConfigPath2</name>\r
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>\r
+                </option>\r
+                <option>\r
+                    <name>GBECoreSlave</name>\r
+                    <version>26</version>\r
+                    <state>39</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGUseCmsis</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGUseCmsisDspLib</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>GRuntimeLibThreads</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CoreVariant</name>\r
+                    <version>26</version>\r
+                    <state>39</state>\r
+                </option>\r
+                <option>\r
+                    <name>GFPUDeviceSlave</name>\r
+                    <state>STM32L475VG ST STM32L475VG</state>\r
+                </option>\r
+                <option>\r
+                    <name>FPU2</name>\r
+                    <version>0</version>\r
+                    <state>4</state>\r
+                </option>\r
+                <option>\r
+                    <name>NrRegs</name>\r
+                    <version>0</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>NEON</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>GFPUCoreSlave2</name>\r
+                    <version>26</version>\r
+                    <state>39</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGCMSISPackSelectDevice</name>\r
+                </option>\r
+                <option>\r
+                    <name>OgLibHeap</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGLibAdditionalLocale</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGPrintfVariant</name>\r
+                    <version>0</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGPrintfMultibyteSupport</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGScanfVariant</name>\r
+                    <version>0</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OGScanfMultibyteSupport</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>GenLocaleTags</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>GenLocaleDisplayOnly</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>DSPExtension</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>TrustZone</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>TrustZoneModes</name>\r
+                    <version>0</version>\r
+                    <state>0</state>\r
+                </option>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>ICCARM</name>\r
+            <archiveVersion>2</archiveVersion>\r
+            <data>\r
+                <version>34</version>\r
+                <wantNonLocal>1</wantNonLocal>\r
+                <debug>1</debug>\r
+                <option>\r
+                    <name>CCOptimizationNoSizeConstraints</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCDefines</name>\r
+                    <state>USE_HAL_DRIVER</state>\r
+                    <state>STM32L475xx</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCPreprocFile</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCPreprocComments</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCPreprocLine</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCListCFile</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCListCMnemonics</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCListCMessages</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCListAssFile</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCListAssSource</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCEnableRemarks</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCDiagSuppress</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>CCDiagRemark</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>CCDiagWarning</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>CCDiagError</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>CCObjPrefix</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCAllowList</name>\r
+                    <version>1</version>\r
+                    <state>00000000</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCDebugInfo</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IEndianMode</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IProcessor</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IExtraOptionsCheck</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IExtraOptions</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>CCLangConformance</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCSignedPlainChar</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCRequirePrototypes</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCDiagWarnAreErr</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCCompilerRuntimeInfo</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IFpuProcessor</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OutputFile</name>\r
+                    <state>$FILE_BNAME$.o</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCLibConfigHeader</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>PreInclude</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>CompilerMisraOverride</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCIncludePath2</name>\r
+                    <state>$PROJ_DIR$/../../ST_Code/Core/Inc</state>\r
+                    <state>$PROJ_DIR$/../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc</state>\r
+                    <state>$PROJ_DIR$/../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy</state>\r
+                    <state>$PROJ_DIR$/../../ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include</state>\r
+                    <state>$PROJ_DIR$/../../ST_Code/Drivers/CMSIS/Include</state>\r
+                    <state>$PROJ_DIR$/../../Config</state>\r
+                    <state>$PROJ_DIR$/../../Demo</state>\r
+                    <state>$PROJ_DIR$/../../../../Source/include</state>\r
+                    <state>$PROJ_DIR$/../../../../Source/portable/IAR/ARM_CM4F_MPU</state>\r
+                    <state>$PROJ_DIR$/../../../../Source/portable/IAR/ARM_CM4F_MPU</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCStdIncCheck</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCCodeSection</name>\r
+                    <state>.text</state>\r
+                </option>\r
+                <option>\r
+                    <name>IProcessorMode2</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCOptLevel</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCOptStrategy</name>\r
+                    <version>0</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCOptLevelSlave</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CompilerMisraRules98</name>\r
+                    <version>0</version>\r
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+                </option>\r
+                <option>\r
+                    <name>CompilerMisraRules04</name>\r
+                    <version>0</version>\r
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCPosIndRopi</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCPosIndRwpi</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCPosIndNoDynInit</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccLang</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccCDialect</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccAllowVLA</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccStaticDestr</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccCppInlineSemantics</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccCmsis</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccFloatSemantics</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCNoLiteralPool</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCOptStrategySlave</name>\r
+                    <version>0</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCGuardCalls</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCEncSource</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCEncOutput</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCEncOutputBom</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CCEncInput</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccExceptions2</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IccRTTI2</name>\r
+                    <state>0</state>\r
+                </option>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>AARM</name>\r
+            <archiveVersion>2</archiveVersion>\r
+            <data>\r
+                <version>10</version>\r
+                <wantNonLocal>1</wantNonLocal>\r
+                <debug>1</debug>\r
+                <option>\r
+                    <name>AObjPrefix</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>AEndian</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>ACaseSensitivity</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>MacroChars</name>\r
+                    <version>0</version>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AWarnEnable</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AWarnWhat</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AWarnOne</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>AWarnRange1</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>AWarnRange2</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>ADebug</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>AltRegisterNames</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>ADefines</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>AList</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AListHeader</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>AListing</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>Includes</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>MacDefs</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>MacExps</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>MacExec</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>OnlyAssed</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>MultiLine</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>PageLengthCheck</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>PageLength</name>\r
+                    <state>80</state>\r
+                </option>\r
+                <option>\r
+                    <name>TabSpacing</name>\r
+                    <state>8</state>\r
+                </option>\r
+                <option>\r
+                    <name>AXRef</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AXRefDefines</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AXRefInternal</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AXRefDual</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AProcessor</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>AFpuProcessor</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>AOutputFile</name>\r
+                    <state>$FILE_BNAME$.o</state>\r
+                </option>\r
+                <option>\r
+                    <name>ALimitErrorsCheck</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>ALimitErrorsEdit</name>\r
+                    <state>100</state>\r
+                </option>\r
+                <option>\r
+                    <name>AIgnoreStdInclude</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AUserIncludes</name>\r
+                    <state>$PROJ_DIR$\..\..\Config</state>\r
+                </option>\r
+                <option>\r
+                    <name>AExtraOptionsCheckV2</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>AExtraOptionsV2</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>AsmNoLiteralPool</name>\r
+                    <state>0</state>\r
+                </option>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>OBJCOPY</name>\r
+            <archiveVersion>0</archiveVersion>\r
+            <data>\r
+                <version>1</version>\r
+                <wantNonLocal>1</wantNonLocal>\r
+                <debug>1</debug>\r
+                <option>\r
+                    <name>OOCOutputFormat</name>\r
+                    <version>3</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OCOutputOverride</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OOCOutputFile</name>\r
+                    <state>MPUDemo.hex</state>\r
+                </option>\r
+                <option>\r
+                    <name>OOCCommandLineProducer</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>OOCObjCopyEnable</name>\r
+                    <state>1</state>\r
+                </option>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>CUSTOM</name>\r
+            <archiveVersion>3</archiveVersion>\r
+            <data>\r
+                <extensions></extensions>\r
+                <cmdline></cmdline>\r
+                <hasPrio>0</hasPrio>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>BICOMP</name>\r
+            <archiveVersion>0</archiveVersion>\r
+            <data />\r
+        </settings>\r
+        <settings>\r
+            <name>BUILDACTION</name>\r
+            <archiveVersion>1</archiveVersion>\r
+            <data>\r
+                <prebuild></prebuild>\r
+                <postbuild></postbuild>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>ILINK</name>\r
+            <archiveVersion>0</archiveVersion>\r
+            <data>\r
+                <version>21</version>\r
+                <wantNonLocal>1</wantNonLocal>\r
+                <debug>1</debug>\r
+                <option>\r
+                    <name>IlinkLibIOConfig</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>XLinkMisraHandler</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkInputFileSlave</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOutputFile</name>\r
+                    <state>MPUDemo.out</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkDebugInfoEnable</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkKeepSymbols</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkRawBinaryFile</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkRawBinarySymbol</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkRawBinarySegment</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkRawBinaryAlign</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkDefines</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkConfigDefines</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkMapFile</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogFile</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogInitialization</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogModule</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogSection</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogVeneer</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkIcfOverride</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkIcfFile</name>\r
+                    <state>$PROJ_DIR$/stm32l475xx_flash.icf</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkIcfFileSlave</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkEnableRemarks</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkSuppressDiags</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkTreatAsRem</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkTreatAsWarn</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkTreatAsErr</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkWarningsAreErrors</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkUseExtraOptions</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkExtraOptions</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLowLevelInterfaceSlave</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkAutoLibEnable</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkAdditionalLibs</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOverrideProgramEntryLabel</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkProgramEntryLabelSelect</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkProgramEntryLabel</name>\r
+                    <state>__iar_program_start</state>\r
+                </option>\r
+                <option>\r
+                    <name>DoFill</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>FillerByte</name>\r
+                    <state>0xFF</state>\r
+                </option>\r
+                <option>\r
+                    <name>FillerStart</name>\r
+                    <state>0x0</state>\r
+                </option>\r
+                <option>\r
+                    <name>FillerEnd</name>\r
+                    <state>0x0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcSize</name>\r
+                    <version>0</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcAlign</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcPoly</name>\r
+                    <state>0x11021</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcCompl</name>\r
+                    <version>0</version>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcBitOrder</name>\r
+                    <version>0</version>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcInitialValue</name>\r
+                    <state>0x0</state>\r
+                </option>\r
+                <option>\r
+                    <name>DoCrc</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkBE8Slave</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkBufferedTerminalOutput</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkStdoutInterfaceSlave</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcFullSize</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkIElfToolPostProcess</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogAutoLibSelect</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogRedirSymbols</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogUnusedFragments</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkCrcReverseByteOrder</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkCrcUseAsInput</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOptInline</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOptExceptionsAllow</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOptExceptionsForce</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkCmsis</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOptMergeDuplSections</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOptUseVfe</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkOptForceVfe</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkStackAnalysisEnable</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkStackControlFile</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkStackCallGraphFile</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcAlgorithm</name>\r
+                    <version>1</version>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>CrcUnitSize</name>\r
+                    <version>0</version>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkThreadsSlave</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLogCallGraph</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkIcfFile_AltDefault</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkEncInput</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkEncOutput</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkEncOutputBom</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkHeapSelect</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkLocaleSelect</name>\r
+                    <state>1</state>\r
+                </option>\r
+                <option>\r
+                    <name>IlinkTrustzoneImportLibraryOut</name>\r
+                    <state>MPUDemo_import_lib.o</state>\r
+                </option>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>IARCHIVE</name>\r
+            <archiveVersion>0</archiveVersion>\r
+            <data>\r
+                <version>0</version>\r
+                <wantNonLocal>1</wantNonLocal>\r
+                <debug>1</debug>\r
+                <option>\r
+                    <name>IarchiveInputs</name>\r
+                    <state></state>\r
+                </option>\r
+                <option>\r
+                    <name>IarchiveOverride</name>\r
+                    <state>0</state>\r
+                </option>\r
+                <option>\r
+                    <name>IarchiveOutput</name>\r
+                    <state>###Unitialized###</state>\r
+                </option>\r
+            </data>\r
+        </settings>\r
+        <settings>\r
+            <name>BILINK</name>\r
+            <archiveVersion>0</archiveVersion>\r
+            <data />\r
+        </settings>\r
+    </configuration>\r
+    <group>\r
+        <name>Config</name>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\Config\FreeRTOSConfig.h</name>\r
+        </file>\r
+    </group>\r
+    <group>\r
+        <name>Demo</name>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\Demo\app_main.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\Demo\app_main.h</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\Demo\mpu_demo.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\Demo\mpu_demo.h</name>\r
+        </file>\r
+    </group>\r
+    <group>\r
+        <name>FreeRTOS</name>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\croutine.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\event_groups.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_4.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\list.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\portable\Common\mpu_wrappers.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\port.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\portasm.s</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\portmacro.h</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\queue.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\stream_buffer.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\tasks.c</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\..\..\..\..\Source\timers.c</name>\r
+        </file>\r
+    </group>\r
+    <group>\r
+        <name>ST_Code</name>\r
+        <group>\r
+            <name>Core</name>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\main.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_hal_msp.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_hal_timebase_tim.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_it.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\system_stm32l4xx.c</name>\r
+            </file>\r
+        </group>\r
+        <group>\r
+            <name>STM32L4xx_HAL_Driver</name>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c</name>\r
+            </file>\r
+            <file>\r
+                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c</name>\r
+            </file>\r
+        </group>\r
+    </group>\r
+    <group>\r
+        <name>Startup</name>\r
+        <file>\r
+            <name>$PROJ_DIR$\memfault_handler.s</name>\r
+        </file>\r
+        <file>\r
+            <name>$PROJ_DIR$\startup_stm32l475xx.s</name>\r
+        </file>\r
+    </group>\r
+</project>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.eww b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.eww
new file mode 100644 (file)
index 0000000..5fcd4a0
--- /dev/null
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\MPUDemo.ewp</path>\r
+  </project>\r
+  <batchBuild />\r
+</workspace>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/memfault_handler.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/memfault_handler.s
new file mode 100644 (file)
index 0000000..4e7b3af
--- /dev/null
@@ -0,0 +1,43 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+       EXTERN vHandleMemoryFault\r
+       PUBLIC MemManage_Handler\r
+\r
+       SECTION .text:CODE:NOROOT(2)\r
+       THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+MemManage_Handler:\r
+       tst lr, #4\r
+       ite eq\r
+       mrseq r0, msp\r
+       mrsne r0, psp\r
+       b vHandleMemoryFault\r
+/*-----------------------------------------------------------*/\r
+\r
+       END\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/startup_stm32l475xx.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/startup_stm32l475xx.s
new file mode 100644 (file)
index 0000000..ca1cd67
--- /dev/null
@@ -0,0 +1,630 @@
+;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************\r
+;* File Name          : startup_stm32l475xx.s\r
+;* Author             : MCD Application Team\r
+;* Description        : STM32L475xx Ultra Low Power Devices vector\r
+;*                      This module performs:\r
+;*                      - Set the initial SP\r
+;*                      - Set the initial PC == _iar_program_start,\r
+;*                      - Set the vector table entries with the exceptions ISR\r
+;*                        address.\r
+;*                      - Branches to main in the C library (which eventually\r
+;*                        calls main()).\r
+;*                      After Reset the Cortex-M4 processor is in Thread mode,\r
+;*                      priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;*\r
+;* Redistribution and use in source and binary forms, with or without modification,\r
+;* are permitted provided that the following conditions are met:\r
+;*   1. Redistributions of source code must retain the above copyright notice,\r
+;*      this list of conditions and the following disclaimer.\r
+;*   2. Redistributions in binary form must reproduce the above copyright notice,\r
+;*      this list of conditions and the following disclaimer in the documentation\r
+;*      and/or other materials provided with the distribution.\r
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors\r
+;*      may be used to endorse or promote products derived from this software\r
+;*      without specific prior written permission.\r
+;*\r
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+;*\r
+;*******************************************************************************\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+        MODULE  ?cstartup\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+        EXTERN  SystemInit\r
+        PUBLIC  __vector_table\r
+\r
+        DATA\r
+__vector_table\r
+        DCD     sfe(CSTACK)\r
+        DCD     Reset_Handler             ; Reset Handler\r
+\r
+        DCD     NMI_Handler               ; NMI Handler\r
+        DCD     HardFault_Handler         ; Hard Fault Handler\r
+        DCD     MemManage_Handler         ; MPU Fault Handler\r
+        DCD     BusFault_Handler          ; Bus Fault Handler\r
+        DCD     UsageFault_Handler        ; Usage Fault Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     SVC_Handler               ; SVCall Handler\r
+        DCD     DebugMon_Handler          ; Debug Monitor Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     PendSV_Handler            ; PendSV Handler\r
+        DCD     SysTick_Handler           ; SysTick Handler\r
+\r
+         ; External Interrupts\r
+        DCD     WWDG_IRQHandler                   ; Window WatchDog\r
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection\r
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line\r
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line\r
+        DCD     FLASH_IRQHandler                  ; FLASH\r
+        DCD     RCC_IRQHandler                    ; RCC\r
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0\r
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1\r
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2\r
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3\r
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4\r
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1\r
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2\r
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3\r
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4\r
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5\r
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6\r
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7\r
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2\r
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX\r
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0\r
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1\r
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE\r
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s\r
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15\r
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16\r
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17\r
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare\r
+        DCD     TIM2_IRQHandler                   ; TIM2\r
+        DCD     TIM3_IRQHandler                   ; TIM3\r
+        DCD     TIM4_IRQHandler                   ; TIM4\r
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event\r
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error\r
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event\r
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error\r
+        DCD     SPI1_IRQHandler                   ; SPI1\r
+        DCD     SPI2_IRQHandler                   ; SPI2\r
+        DCD     USART1_IRQHandler                 ; USART1\r
+        DCD     USART2_IRQHandler                 ; USART2\r
+        DCD     USART3_IRQHandler                 ; USART3\r
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]\r
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line\r
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt\r
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt\r
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt\r
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt\r
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt\r
+        DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt\r
+        DCD     FMC_IRQHandler                    ; FMC\r
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1\r
+        DCD     TIM5_IRQHandler                   ; TIM5\r
+        DCD     SPI3_IRQHandler                   ; SPI3\r
+        DCD     UART4_IRQHandler                  ; UART4\r
+        DCD     UART5_IRQHandler                  ; UART5\r
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors\r
+        DCD     TIM7_IRQHandler                   ; TIM7\r
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1\r
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2\r
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3\r
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4\r
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5\r
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt\r
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt\r
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt\r
+        DCD     COMP_IRQHandler                   ; COMP Interrupt\r
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt\r
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt\r
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS\r
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6\r
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7\r
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt\r
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt\r
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event\r
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error\r
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt\r
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt\r
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt\r
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt\r
+        DCD     0                                 ; Reserved        \r
+        DCD     0                                 ; Reserved        \r
+        DCD     RNG_IRQHandler                    ; RNG global interrupt\r
+        DCD     FPU_IRQHandler                    ; FPU\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+        PUBWEAK Reset_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(2)\r
+Reset_Handler\r
+        LDR     R0, =SystemInit\r
+        BLX     R0\r
+        LDR     R0, =__iar_program_start\r
+        BX      R0\r
+\r
+        PUBWEAK NMI_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+NMI_Handler\r
+        B NMI_Handler\r
+\r
+        PUBWEAK HardFault_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+HardFault_Handler\r
+        B HardFault_Handler\r
+\r
+        PUBWEAK MemManage_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+MemManage_Handler\r
+        B MemManage_Handler\r
+\r
+        PUBWEAK BusFault_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+BusFault_Handler\r
+        B BusFault_Handler\r
+\r
+        PUBWEAK UsageFault_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+UsageFault_Handler\r
+        B UsageFault_Handler\r
+\r
+        PUBWEAK SVC_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SVC_Handler\r
+        B SVC_Handler\r
+\r
+        PUBWEAK DebugMon_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DebugMon_Handler\r
+        B DebugMon_Handler\r
+\r
+        PUBWEAK PendSV_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+PendSV_Handler\r
+        B PendSV_Handler\r
+\r
+        PUBWEAK SysTick_Handler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SysTick_Handler\r
+        B SysTick_Handler\r
+\r
+        PUBWEAK WWDG_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+WWDG_IRQHandler\r
+        B WWDG_IRQHandler\r
+\r
+        PUBWEAK PVD_PVM_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+PVD_PVM_IRQHandler\r
+        B PVD_PVM_IRQHandler\r
+\r
+        PUBWEAK TAMP_STAMP_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TAMP_STAMP_IRQHandler\r
+        B TAMP_STAMP_IRQHandler\r
+\r
+        PUBWEAK RTC_WKUP_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+RTC_WKUP_IRQHandler\r
+        B RTC_WKUP_IRQHandler\r
+\r
+        PUBWEAK FLASH_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+FLASH_IRQHandler\r
+        B FLASH_IRQHandler\r
+\r
+        PUBWEAK RCC_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+RCC_IRQHandler\r
+        B RCC_IRQHandler\r
+\r
+        PUBWEAK EXTI0_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI0_IRQHandler\r
+        B EXTI0_IRQHandler\r
+\r
+        PUBWEAK EXTI1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI1_IRQHandler\r
+        B EXTI1_IRQHandler\r
+\r
+        PUBWEAK EXTI2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI2_IRQHandler\r
+        B EXTI2_IRQHandler\r
+\r
+        PUBWEAK EXTI3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI3_IRQHandler\r
+        B EXTI3_IRQHandler\r
+\r
+        PUBWEAK EXTI4_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI4_IRQHandler\r
+        B EXTI4_IRQHandler\r
+\r
+        PUBWEAK DMA1_Channel1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+        B DMA1_Channel1_IRQHandler\r
+\r
+        PUBWEAK DMA1_Channel2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel2_IRQHandler\r
+        B DMA1_Channel2_IRQHandler\r
+\r
+        PUBWEAK DMA1_Channel3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel3_IRQHandler\r
+        B DMA1_Channel3_IRQHandler\r
+\r
+        PUBWEAK DMA1_Channel4_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel4_IRQHandler\r
+        B DMA1_Channel4_IRQHandler\r
+\r
+        PUBWEAK DMA1_Channel5_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel5_IRQHandler\r
+        B DMA1_Channel5_IRQHandler\r
+\r
+        PUBWEAK DMA1_Channel6_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel6_IRQHandler\r
+        B DMA1_Channel6_IRQHandler\r
+\r
+        PUBWEAK DMA1_Channel7_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel7_IRQHandler\r
+        B DMA1_Channel7_IRQHandler\r
+\r
+        PUBWEAK ADC1_2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC1_2_IRQHandler\r
+        B ADC1_2_IRQHandler\r
+\r
+        PUBWEAK CAN1_TX_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_TX_IRQHandler\r
+        B CAN1_TX_IRQHandler\r
+\r
+        PUBWEAK CAN1_RX0_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_RX0_IRQHandler\r
+        B CAN1_RX0_IRQHandler\r
+\r
+        PUBWEAK CAN1_RX1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_RX1_IRQHandler\r
+        B CAN1_RX1_IRQHandler\r
+\r
+        PUBWEAK CAN1_SCE_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_SCE_IRQHandler\r
+        B CAN1_SCE_IRQHandler\r
+\r
+        PUBWEAK EXTI9_5_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI9_5_IRQHandler\r
+        B EXTI9_5_IRQHandler\r
+\r
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_BRK_TIM15_IRQHandler\r
+        B TIM1_BRK_TIM15_IRQHandler\r
+\r
+        PUBWEAK TIM1_UP_TIM16_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_UP_TIM16_IRQHandler\r
+        B TIM1_UP_TIM16_IRQHandler\r
+\r
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_TRG_COM_TIM17_IRQHandler\r
+        B TIM1_TRG_COM_TIM17_IRQHandler\r
+\r
+        PUBWEAK TIM1_CC_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_CC_IRQHandler\r
+        B TIM1_CC_IRQHandler\r
+\r
+        PUBWEAK TIM2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM2_IRQHandler\r
+        B TIM2_IRQHandler\r
+\r
+        PUBWEAK TIM3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM3_IRQHandler\r
+        B TIM3_IRQHandler\r
+\r
+        PUBWEAK TIM4_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM4_IRQHandler\r
+        B TIM4_IRQHandler\r
+\r
+        PUBWEAK I2C1_EV_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C1_EV_IRQHandler\r
+        B I2C1_EV_IRQHandler\r
+\r
+        PUBWEAK I2C1_ER_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C1_ER_IRQHandler\r
+        B I2C1_ER_IRQHandler\r
+\r
+        PUBWEAK I2C2_EV_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C2_EV_IRQHandler\r
+        B I2C2_EV_IRQHandler\r
+\r
+        PUBWEAK I2C2_ER_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C2_ER_IRQHandler\r
+        B I2C2_ER_IRQHandler\r
+\r
+        PUBWEAK SPI1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI1_IRQHandler\r
+        B SPI1_IRQHandler\r
+\r
+        PUBWEAK SPI2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI2_IRQHandler\r
+        B SPI2_IRQHandler\r
+\r
+        PUBWEAK USART1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART1_IRQHandler\r
+        B USART1_IRQHandler\r
+\r
+        PUBWEAK USART2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART2_IRQHandler\r
+        B USART2_IRQHandler\r
+\r
+        PUBWEAK USART3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART3_IRQHandler\r
+        B USART3_IRQHandler\r
+\r
+        PUBWEAK EXTI15_10_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI15_10_IRQHandler\r
+        B EXTI15_10_IRQHandler\r
+\r
+        PUBWEAK RTC_Alarm_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+RTC_Alarm_IRQHandler\r
+        B RTC_Alarm_IRQHandler\r
+\r
+        PUBWEAK DFSDM1_FLT3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT3_IRQHandler\r
+        B DFSDM1_FLT3_IRQHandler\r
+\r
+        PUBWEAK TIM8_BRK_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_BRK_IRQHandler\r
+        B TIM8_BRK_IRQHandler\r
+\r
+        PUBWEAK TIM8_UP_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_UP_IRQHandler\r
+        B TIM8_UP_IRQHandler\r
+\r
+        PUBWEAK TIM8_TRG_COM_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_TRG_COM_IRQHandler\r
+        B TIM8_TRG_COM_IRQHandler\r
+\r
+        PUBWEAK TIM8_CC_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_CC_IRQHandler\r
+        B TIM8_CC_IRQHandler\r
+\r
+        PUBWEAK ADC3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC3_IRQHandler\r
+        B ADC3_IRQHandler\r
+\r
+        PUBWEAK FMC_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+FMC_IRQHandler\r
+        B FMC_IRQHandler\r
+\r
+        PUBWEAK SDMMC1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SDMMC1_IRQHandler\r
+        B SDMMC1_IRQHandler\r
+\r
+        PUBWEAK TIM5_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM5_IRQHandler\r
+        B TIM5_IRQHandler\r
+\r
+        PUBWEAK SPI3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI3_IRQHandler\r
+        B SPI3_IRQHandler\r
+\r
+        PUBWEAK UART4_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART4_IRQHandler\r
+        B UART4_IRQHandler\r
+\r
+        PUBWEAK UART5_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART5_IRQHandler\r
+        B UART5_IRQHandler\r
+\r
+        PUBWEAK TIM6_DAC_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM6_DAC_IRQHandler\r
+        B TIM6_DAC_IRQHandler\r
+\r
+        PUBWEAK TIM7_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM7_IRQHandler\r
+        B TIM7_IRQHandler\r
+\r
+        PUBWEAK DMA2_Channel1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel1_IRQHandler\r
+        B DMA2_Channel1_IRQHandler\r
+\r
+        PUBWEAK DMA2_Channel2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel2_IRQHandler\r
+        B DMA2_Channel2_IRQHandler\r
+\r
+        PUBWEAK DMA2_Channel3_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel3_IRQHandler\r
+        B DMA2_Channel3_IRQHandler\r
+\r
+        PUBWEAK DMA2_Channel4_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel4_IRQHandler\r
+        B DMA2_Channel4_IRQHandler\r
+\r
+        PUBWEAK DMA2_Channel5_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel5_IRQHandler\r
+        B DMA2_Channel5_IRQHandler\r
+\r
+        PUBWEAK DFSDM1_FLT0_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT0_IRQHandler\r
+        B DFSDM1_FLT0_IRQHandler\r
+\r
+        PUBWEAK DFSDM1_FLT1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT1_IRQHandler\r
+        B DFSDM1_FLT1_IRQHandler\r
+\r
+        PUBWEAK DFSDM1_FLT2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT2_IRQHandler\r
+        B DFSDM1_FLT2_IRQHandler\r
+\r
+        PUBWEAK COMP_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+COMP_IRQHandler\r
+        B COMP_IRQHandler\r
+\r
+        PUBWEAK LPTIM1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+LPTIM1_IRQHandler\r
+        B LPTIM1_IRQHandler\r
+\r
+        PUBWEAK LPTIM2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+LPTIM2_IRQHandler\r
+        B LPTIM2_IRQHandler\r
+\r
+        PUBWEAK OTG_FS_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+OTG_FS_IRQHandler\r
+        B OTG_FS_IRQHandler\r
+\r
+        PUBWEAK DMA2_Channel6_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel6_IRQHandler\r
+        B DMA2_Channel6_IRQHandler\r
+\r
+        PUBWEAK DMA2_Channel7_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel7_IRQHandler\r
+        B DMA2_Channel7_IRQHandler\r
+\r
+        PUBWEAK LPUART1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+LPUART1_IRQHandler\r
+        B LPUART1_IRQHandler\r
+\r
+        PUBWEAK QUADSPI_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+QUADSPI_IRQHandler\r
+        B QUADSPI_IRQHandler\r
+\r
+        PUBWEAK I2C3_EV_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C3_EV_IRQHandler\r
+        B I2C3_EV_IRQHandler\r
+\r
+        PUBWEAK I2C3_ER_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C3_ER_IRQHandler\r
+        B I2C3_ER_IRQHandler\r
+\r
+        PUBWEAK SAI1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SAI1_IRQHandler\r
+        B SAI1_IRQHandler\r
+\r
+       PUBWEAK SAI2_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SAI2_IRQHandler\r
+        B SAI2_IRQHandler\r
+\r
+        PUBWEAK SWPMI1_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+SWPMI1_IRQHandler\r
+        B SWPMI1_IRQHandler\r
+\r
+       PUBWEAK TSC_IRQHandler\r
+       SECTION .text:CODE:NOROOT:REORDER(1)\r
+TSC_IRQHandler\r
+       B TSC_IRQHandler\r
+\r
+        PUBWEAK RNG_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+RNG_IRQHandler\r
+        B RNG_IRQHandler\r
+\r
+        PUBWEAK FPU_IRQHandler\r
+        SECTION .text:CODE:NOROOT:REORDER(1)\r
+FPU_IRQHandler\r
+        B FPU_IRQHandler\r
+\r
+        END\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/stm32l475xx_flash.icf b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/stm32l475xx_flash.icf
new file mode 100644 (file)
index 0000000..90a1e1e
--- /dev/null
@@ -0,0 +1,96 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;\r
+define symbol __ICFEDIT_region_ROM_end__      = 0x080FFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__      = 0x20017FFF;\r
+\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+/* Flash Organization\r
+ *  1. Privileged Code:\r
+ *      Start   : 0x08000000\r
+ *      End     : 0x08007FFF\r
+ *      Size    : 32 Kbytes\r
+ *  2. System calls:\r
+ *      Start   : 0x08008000\r
+ *      End     : 0x08008FFF\r
+ *      Size    : 4 Kbytes\r
+ *  3. Unprivileged Code:\r
+ *      Start   : 0x08009000\r
+ *      End     : 0x080FFFFF\r
+ *      Size    : 988 Kbytes\r
+ */\r
+define symbol __reigon_ROM_privileged_start__   = __ICFEDIT_region_ROM_start__;\r
+define symbol __reigon_ROM_privileged_end__     = 0x08007FFF;\r
+define symbol __reigon_ROM_system_calls_start__ = 0x08008000;\r
+define symbol __reigon_ROM_system_calls_end__   = 0x08008FFF;\r
+define symbol __reigon_ROM_unprivileged_start__ = 0x08009000;\r
+define symbol __reigon_ROM_unprivileged_end__   = __ICFEDIT_region_ROM_end__;\r
+\r
+/* RAM Organization\r
+ *  1. Privileged Data:\r
+ *      Start   : 0x20000000\r
+ *      End     : 0x200003FF\r
+ *      Size    : 1 Kbytes\r
+ *  2. Unprivileged Data:\r
+ *      Start   : 0x20000400\r
+ *      End     : 0x20017FFF\r
+ *      Size    : 95 Kbytes\r
+ */\r
+define symbol __region_RAM_privileged_start__   = __ICFEDIT_region_RAM_start__;\r
+define symbol __region_RAM_privileged_end__     = 0x200003FF;\r
+define symbol __region_RAM_unprivileged_start__ = 0x20000400;\r
+define symbol __region_RAM_unprivileged_end__   = __ICFEDIT_region_RAM_end__;\r
+define symbol __region_SRAM2_start__            = 0x10000000;\r
+define symbol __region_SRAM2_end__              = 0x10007FFF;\r
+\r
+/* Memory regions. */\r
+define memory mem with size = 4G;\r
+define region ROM_region_privileged     = mem:[from __reigon_ROM_privileged_start__ to __reigon_ROM_privileged_end__];\r
+define region ROM_region_system_calls   = mem:[from __reigon_ROM_system_calls_start__ to __reigon_ROM_system_calls_end__];\r
+define region ROM_region_unprivileged   = mem:[from __reigon_ROM_unprivileged_start__ to __reigon_ROM_unprivileged_end__];\r
+define region RAM_region_privileged     = mem:[from __region_RAM_privileged_start__   to __region_RAM_privileged_end__];\r
+define region RAM_region_unprivileged   = mem:[from __region_RAM_unprivileged_start__   to __region_RAM_unprivileged_end__];\r
+define region SRAM2_region              = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];\r
+\r
+/* Stack and Heap. */\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+/* Initialization. */\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+\r
+/* Exported symbols. */\r
+define exported symbol __FLASH_segment_start__          = __ICFEDIT_region_ROM_start__;\r
+define exported symbol __FLASH_segment_end__            = __ICFEDIT_region_ROM_end__;\r
+define exported symbol __SRAM_segment_start__           = __ICFEDIT_region_RAM_start__;\r
+define exported symbol __SRAM_segment_end__             = __ICFEDIT_region_RAM_end__;\r
+\r
+define exported symbol __privileged_functions_start__   = __reigon_ROM_privileged_start__;\r
+define exported symbol __privileged_functions_end__     = __reigon_ROM_privileged_end__;\r
+define exported symbol __privileged_data_start__        = __region_RAM_privileged_start__;\r
+define exported symbol __privileged_data_end__          = __region_RAM_privileged_end__;\r
+\r
+define exported symbol __syscalls_flash_start__         = __reigon_ROM_system_calls_start__;\r
+define exported symbol __syscalls_flash_end__           = __reigon_ROM_system_calls_end__;\r
+\r
+/* Placements. */\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region_privileged      { readonly section privileged_functions };\r
+place in ROM_region_system_calls    { readonly section freertos_system_calls };\r
+place in ROM_region_unprivileged    { readonly };\r
+\r
+place in RAM_region_privileged      { readwrite section privileged_data };\r
+place in RAM_region_unprivileged    { readwrite,\r
+                                      block CSTACK, block HEAP }; \r
+place in SRAM2_region               { };\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/EventRecorderStub.scvd b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/EventRecorderStub.scvd
new file mode 100644 (file)
index 0000000..0fb3ee5
--- /dev/null
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>\r
+\r
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">\r
+\r
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->\r
+  <events>\r
+  </events>\r
+\r
+</component_viewer>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.sct b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.sct
new file mode 100644 (file)
index 0000000..891bc1b
--- /dev/null
@@ -0,0 +1,45 @@
+; Flash Layout\r
+;\r
+;  ---------------------\r
+; |   Privileged Code   |\r
+;  ---------------------\r
+; |  Unprivileged Code  |\r
+;  ---------------------\r
+;\r
+; RAM Layout\r
+;\r
+;  ---------------------\r
+; |   Privileged Data   |\r
+;  ---------------------\r
+; |  Unprivileged Data  |\r
+;  ---------------------\r
+\r
+LR_APP 0x08000000 0x100000 ; load region size_region\r
+{\r
+    ER_IROM_PRIVILEGED 0x08000000\r
+    {\r
+        *.o (RESET, +First)\r
+        *(InRoot$$Sections)\r
+        *(privileged_functions)\r
+    }\r
+\r
+    ER_IROM_FREERTOS_SYSTEM_CALLS 0x08008000 FIXED\r
+    {\r
+        *(freertos_system_calls)\r
+    }\r
+\r
+    ER_IROM_UNPRIVILEGED +0\r
+    {\r
+        .ANY (+RO)\r
+    }\r
+\r
+    RW_IRAM_PRIVILEGED 0x20000000\r
+    {\r
+        *(privileged_data)\r
+    }\r
+\r
+    RW_IRAM_UNPRIVILEGED 0x20000400\r
+    {\r
+        .ANY (+RW +ZI)\r
+    }\r
+}\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvoptx
new file mode 100644 (file)
index 0000000..6cdaf39
--- /dev/null
@@ -0,0 +1,856 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>MPUDemo</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>80000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath></ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>18</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>1</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>5</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMRTXEVENTFLAGS</Key>
+          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=2981,231,3458,546,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32L475VGTx$CMSIS\Flash\STM32L4xx_1024.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ST-LINKIII-KEIL_SWO</Key>
+          <Name>-U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L475VGTx$CMSIS\Flash\STM32L4xx_1024.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Startup</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>startup_stm32l475xx.s</PathWithFileName>
+      <FilenameWithoutPath>startup_stm32l475xx.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\memfault_handler.c</PathWithFileName>
+      <FilenameWithoutPath>memfault_handler.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>FreeRTOS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/croutine.c</PathWithFileName>
+      <FilenameWithoutPath>croutine.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/event_groups.c</PathWithFileName>
+      <FilenameWithoutPath>event_groups.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/list.c</PathWithFileName>
+      <FilenameWithoutPath>list.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/queue.c</PathWithFileName>
+      <FilenameWithoutPath>queue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/stream_buffer.c</PathWithFileName>
+      <FilenameWithoutPath>stream_buffer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/tasks.c</PathWithFileName>
+      <FilenameWithoutPath>tasks.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/timers.c</PathWithFileName>
+      <FilenameWithoutPath>timers.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/portable/Common/mpu_wrappers.c</PathWithFileName>
+      <FilenameWithoutPath>mpu_wrappers.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/portable/GCC/ARM_CM4_MPU/port.c</PathWithFileName>
+      <FilenameWithoutPath>port.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/portable/GCC/ARM_CM4_MPU/portmacro.h</PathWithFileName>
+      <FilenameWithoutPath>portmacro.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../../../Source/portable/MemMang/heap_4.c</PathWithFileName>
+      <FilenameWithoutPath>heap_4.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Config</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../Config/FreeRTOSConfig.h</PathWithFileName>
+      <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Demo</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../Demo/app_main.c</PathWithFileName>
+      <FilenameWithoutPath>app_main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../Demo/app_main.h</PathWithFileName>
+      <FilenameWithoutPath>app_main.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../Demo/mpu_demo.c</PathWithFileName>
+      <FilenameWithoutPath>mpu_demo.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../Demo/mpu_demo.h</PathWithFileName>
+      <FilenameWithoutPath>mpu_demo.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Core</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Core/Src/main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>20</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Core/Src/stm32l4xx_it.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_it.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>21</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Core/Src/stm32l4xx_hal_msp.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_msp.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>22</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_timebase_tim.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Drivers/STM32L4xx_HAL_Driver</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>23</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_dfsdm.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>24</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_i2c.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_i2c_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_qspi.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>27</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_spi.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>28</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_spi_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>29</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_tim.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>30</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_tim_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>31</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_uart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>32</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_uart_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>33</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_pcd.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>34</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_pcd_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>35</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_ll_usb.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>36</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>37</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_rcc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>38</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_rcc_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>39</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_flash.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>40</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_flash_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>41</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_flash_ramfunc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>42</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>43</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_dma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>44</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_dma_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>45</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_pwr.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>46</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_pwr_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>47</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_cortex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>48</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c</PathWithFileName>
+      <FilenameWithoutPath>stm32l4xx_hal_exti.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Drivers/CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>49</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../../ST_Code/Core/Src/system_stm32l4xx.c</PathWithFileName>
+      <FilenameWithoutPath>system_stm32l4xx.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvprojx
new file mode 100644 (file)
index 0000000..b69de9d
--- /dev/null
@@ -0,0 +1,733 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>MPUDemo</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32L475VGTx</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32L4xx_DFP.2.2.0</PackID>
+          <PackURL>http://www.keil.com/pack</PackURL>
+          <Cpu>IRAM(0x20000000-0x20017FFF) IRAM2(0x10000000-0x10007FFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId></DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32L475VGTx$CMSIS\SVD\STM32L4x5.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>Debug\</OutputDirectory>
+          <OutputName>MPUDemo</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath></ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4107</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x18000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x18000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_HAL_DRIVER,STM32L475xx</Define>
+              <Undefine></Undefine>
+              <IncludePath>../../ST_Code/Core/Inc;../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc;../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy;../../ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include;../../ST_Code/Drivers/CMSIS/Include;../../Config;../../Demo;../../../../Source/include;../../../../Source/portable/GCC/ARM_CM4_MPU</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>MPUDemo.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Startup</GroupName>
+          <Files>
+            <File>
+              <FileName>startup_stm32l475xx.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>startup_stm32l475xx.s</FilePath>
+            </File>
+            <File>
+              <FileName>memfault_handler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\memfault_handler.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FreeRTOS</GroupName>
+          <Files>
+            <File>
+              <FileName>croutine.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/croutine.c</FilePath>
+            </File>
+            <File>
+              <FileName>event_groups.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/event_groups.c</FilePath>
+            </File>
+            <File>
+              <FileName>list.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/list.c</FilePath>
+            </File>
+            <File>
+              <FileName>queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>stream_buffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/stream_buffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>tasks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/tasks.c</FilePath>
+            </File>
+            <File>
+              <FileName>timers.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/timers.c</FilePath>
+            </File>
+            <File>
+              <FileName>mpu_wrappers.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/portable/Common/mpu_wrappers.c</FilePath>
+            </File>
+            <File>
+              <FileName>port.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/portable/GCC/ARM_CM4_MPU/port.c</FilePath>
+            </File>
+            <File>
+              <FileName>portmacro.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>../../../../Source/portable/GCC/ARM_CM4_MPU/portmacro.h</FilePath>
+            </File>
+            <File>
+              <FileName>heap_4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../../../Source/portable/MemMang/heap_4.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Config</GroupName>
+          <Files>
+            <File>
+              <FileName>FreeRTOSConfig.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>../../Config/FreeRTOSConfig.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Demo</GroupName>
+          <Files>
+            <File>
+              <FileName>app_main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../Demo/app_main.c</FilePath>
+            </File>
+            <File>
+              <FileName>app_main.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>../../Demo/app_main.h</FilePath>
+            </File>
+            <File>
+              <FileName>mpu_demo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../Demo/mpu_demo.c</FilePath>
+            </File>
+            <File>
+              <FileName>mpu_demo.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>../../Demo/mpu_demo.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Core</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Core/Src/main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Core/Src/stm32l4xx_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_msp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Core/Src/stm32l4xx_hal_msp.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_timebase_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers/STM32L4xx_HAL_Driver</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32l4xx_hal_dfsdm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_i2c_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_qspi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_spi_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_tim_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_uart_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_pcd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_pcd_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_ll_usb.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>2</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>1</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_rcc_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_flash_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_flash_ramfunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_dma_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_pwr_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_cortex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l4xx_hal_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers/CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32l4xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../ST_Code/Core/Src/system_stm32l4xx.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+        <targetInfos>
+          <targetInfo name="MPUDemo"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/memfault_handler.c
new file mode 100644 (file)
index 0000000..59efcd7
--- /dev/null
@@ -0,0 +1,69 @@
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base;\r
+extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit;\r
+\r
+/* Memory map needed for MPU setup. Must must match the one defined in\r
+ * the scatter-loading file (MPUDemo.sct). */\r
+const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x08000000;\r
+const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x08100000;\r
+const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000;\r
+const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20018000;\r
+\r
+const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x08000000;\r
+const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x08008000;\r
+const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000;\r
+const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20000400;\r
+\r
+const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base );\r
+const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Mem fault handler.\r
+ */\r
+void MemManage_Handler( void ) __attribute__ (( naked ));\r
+/*-----------------------------------------------------------*/\r
+\r
+void MemManage_Handler( void )\r
+{\r
+       __asm volatile\r
+       (\r
+               " tst lr, #4                                                                            \n"\r
+               " ite eq                                                                                        \n"\r
+               " mrseq r0, msp                                                                         \n"\r
+               " mrsne r0, psp                                                                         \n"\r
+               " ldr r1, handler_address_const                                         \n"\r
+               " bx r1                                                                                         \n"\r
+               "                                                                                                       \n"\r
+               " handler_address_const: .word vHandleMemoryFault       \n"\r
+       );\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/startup_stm32l475xx.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/startup_stm32l475xx.s
new file mode 100644 (file)
index 0000000..18a4ee1
--- /dev/null
@@ -0,0 +1,435 @@
+;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************\r
+;* File Name          : startup_stm32l475xx.s\r
+;* Author             : MCD Application Team\r
+;* Description        : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain.\r
+;*                      This module performs:\r
+;*                      - Set the initial SP\r
+;*                      - Set the initial PC == Reset_Handler\r
+;*                      - Set the vector table entries with the exceptions ISR address\r
+;*                      - Branches to __main in the C library (which eventually\r
+;*                        calls main()).\r
+;*                      After Reset the Cortex-M4 processor is in Thread mode,\r
+;*                      priority is Privileged, and the Stack is set to Main.\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+;*******************************************************************************\r
+;*\r
+;* Redistribution and use in source and binary forms, with or without modification,\r
+;* are permitted provided that the following conditions are met:\r
+;*   1. Redistributions of source code must retain the above copyright notice,\r
+;*      this list of conditions and the following disclaimer.\r
+;*   2. Redistributions in binary form must reproduce the above copyright notice,\r
+;*      this list of conditions and the following disclaimer in the documentation\r
+;*      and/or other materials provided with the distribution.\r
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors\r
+;*      may be used to endorse or promote products derived from this software\r
+;*      without specific prior written permission.\r
+;*\r
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+;*\r
+;*******************************************************************************\r
+;\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size             EQU     0x400\r
+\r
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem       SPACE   Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size      EQU     0x200\r
+\r
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem        SPACE   Heap_Size\r
+__heap_limit\r
+\r
+                PRESERVE8\r
+                THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+                AREA    RESET, DATA, READONLY\r
+                EXPORT  __Vectors\r
+                EXPORT  __Vectors_End\r
+                EXPORT  __Vectors_Size\r
+\r
+__Vectors       DCD     __initial_sp               ; Top of Stack\r
+                DCD     Reset_Handler              ; Reset Handler\r
+                DCD     NMI_Handler                ; NMI Handler\r
+                DCD     HardFault_Handler          ; Hard Fault Handler\r
+                DCD     MemManage_Handler          ; MPU Fault Handler\r
+                DCD     BusFault_Handler           ; Bus Fault Handler\r
+                DCD     UsageFault_Handler         ; Usage Fault Handler\r
+                DCD     0                          ; Reserved\r
+                DCD     0                          ; Reserved\r
+                DCD     0                          ; Reserved\r
+                DCD     0                          ; Reserved\r
+                DCD     SVC_Handler                ; SVCall Handler\r
+                DCD     DebugMon_Handler           ; Debug Monitor Handler\r
+                DCD     0                          ; Reserved\r
+                DCD     PendSV_Handler             ; PendSV Handler\r
+                DCD     SysTick_Handler            ; SysTick Handler\r
+\r
+                ; External Interrupts\r
+                DCD     WWDG_IRQHandler                   ; Window WatchDog\r
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection\r
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line\r
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line\r
+                DCD     FLASH_IRQHandler                  ; FLASH\r
+                DCD     RCC_IRQHandler                    ; RCC\r
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0\r
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1\r
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2\r
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3\r
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4\r
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1\r
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2\r
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3\r
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4\r
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5\r
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6\r
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7\r
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2\r
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX\r
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0\r
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1\r
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE\r
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s\r
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15\r
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16\r
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17\r
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare\r
+                DCD     TIM2_IRQHandler                   ; TIM2\r
+                DCD     TIM3_IRQHandler                   ; TIM3\r
+                DCD     TIM4_IRQHandler                   ; TIM4\r
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event\r
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error\r
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event\r
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error\r
+                DCD     SPI1_IRQHandler                   ; SPI1\r
+                DCD     SPI2_IRQHandler                   ; SPI2\r
+                DCD     USART1_IRQHandler                 ; USART1\r
+                DCD     USART2_IRQHandler                 ; USART2\r
+                DCD     USART3_IRQHandler                 ; USART3\r
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]\r
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line\r
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt\r
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt\r
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt\r
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt\r
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt\r
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt\r
+                DCD     FMC_IRQHandler                    ; FMC\r
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1\r
+                DCD     TIM5_IRQHandler                   ; TIM5\r
+                DCD     SPI3_IRQHandler                   ; SPI3\r
+                DCD     UART4_IRQHandler                  ; UART4\r
+                DCD     UART5_IRQHandler                  ; UART5\r
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors\r
+                DCD     TIM7_IRQHandler                   ; TIM7\r
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1\r
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2\r
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3\r
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4\r
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5\r
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt\r
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt\r
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt\r
+                DCD     COMP_IRQHandler                   ; COMP Interrupt\r
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt\r
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt\r
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS\r
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6\r
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7\r
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt\r
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt\r
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event\r
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error\r
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt\r
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt\r
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt\r
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt\r
+                DCD     0                                 ; Reserved                \r
+                DCD     0                                 ; Reserved                \r
+                DCD     RNG_IRQHandler                    ; RNG global interrupt\r
+                DCD     FPU_IRQHandler                    ; FPU\r
+\r
+__Vectors_End\r
+\r
+__Vectors_Size  EQU  __Vectors_End - __Vectors\r
+\r
+                AREA    |.text|, CODE, READONLY\r
+\r
+; Reset handler\r
+Reset_Handler    PROC\r
+                 EXPORT  Reset_Handler             [WEAK]\r
+        IMPORT  SystemInit\r
+        IMPORT  __main\r
+\r
+                 LDR     R0, =SystemInit\r
+                 BLX     R0\r
+                 LDR     R0, =__main\r
+                 BX      R0\r
+                 ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler     PROC\r
+                EXPORT  NMI_Handler                [WEAK]\r
+                B       .\r
+                ENDP\r
+HardFault_Handler\\r
+                PROC\r
+                EXPORT  HardFault_Handler          [WEAK]\r
+                B       .\r
+                ENDP\r
+MemManage_Handler\\r
+                PROC\r
+                EXPORT  MemManage_Handler          [WEAK]\r
+                B       .\r
+                ENDP\r
+BusFault_Handler\\r
+                PROC\r
+                EXPORT  BusFault_Handler           [WEAK]\r
+                B       .\r
+                ENDP\r
+UsageFault_Handler\\r
+                PROC\r
+                EXPORT  UsageFault_Handler         [WEAK]\r
+                B       .\r
+                ENDP\r
+SVC_Handler     PROC\r
+                EXPORT  SVC_Handler                [WEAK]\r
+                B       .\r
+                ENDP\r
+DebugMon_Handler\\r
+                PROC\r
+                EXPORT  DebugMon_Handler           [WEAK]\r
+                B       .\r
+                ENDP\r
+PendSV_Handler  PROC\r
+                EXPORT  PendSV_Handler             [WEAK]\r
+                B       .\r
+                ENDP\r
+SysTick_Handler PROC\r
+                EXPORT  SysTick_Handler            [WEAK]\r
+                B       .\r
+                ENDP\r
+\r
+Default_Handler PROC\r
+\r
+        EXPORT     WWDG_IRQHandler                   [WEAK]\r
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]\r
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]\r
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]\r
+        EXPORT     FLASH_IRQHandler                  [WEAK]\r
+        EXPORT     RCC_IRQHandler                    [WEAK]\r
+        EXPORT     EXTI0_IRQHandler                  [WEAK]\r
+        EXPORT     EXTI1_IRQHandler                  [WEAK]\r
+        EXPORT     EXTI2_IRQHandler                  [WEAK]\r
+        EXPORT     EXTI3_IRQHandler                  [WEAK]\r
+        EXPORT     EXTI4_IRQHandler                  [WEAK]\r
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]\r
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]\r
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]\r
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]\r
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]\r
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]\r
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]\r
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]\r
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]\r
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]\r
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]\r
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]\r
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]\r
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]\r
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]\r
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]\r
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]\r
+        EXPORT     TIM2_IRQHandler                   [WEAK]\r
+        EXPORT     TIM3_IRQHandler                   [WEAK]\r
+        EXPORT     TIM4_IRQHandler                   [WEAK]\r
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]\r
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]\r
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]\r
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]\r
+        EXPORT     SPI1_IRQHandler                   [WEAK]\r
+        EXPORT     SPI2_IRQHandler                   [WEAK]\r
+        EXPORT     USART1_IRQHandler                 [WEAK]\r
+        EXPORT     USART2_IRQHandler                 [WEAK]\r
+        EXPORT     USART3_IRQHandler                 [WEAK]\r
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]\r
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]\r
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]\r
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]\r
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]\r
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]\r
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]\r
+        EXPORT     ADC3_IRQHandler                   [WEAK]\r
+        EXPORT     FMC_IRQHandler                    [WEAK]\r
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]\r
+        EXPORT     TIM5_IRQHandler                   [WEAK]\r
+        EXPORT     SPI3_IRQHandler                   [WEAK]\r
+        EXPORT     UART4_IRQHandler                  [WEAK]\r
+        EXPORT     UART5_IRQHandler                  [WEAK]\r
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]\r
+        EXPORT     TIM7_IRQHandler                   [WEAK]\r
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]\r
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]\r
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]\r
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]\r
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]\r
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]\r
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]\r
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]\r
+        EXPORT     COMP_IRQHandler                   [WEAK]\r
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]\r
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]\r
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]\r
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]\r
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]\r
+        EXPORT     LPUART1_IRQHandler                [WEAK]\r
+        EXPORT     QUADSPI_IRQHandler                [WEAK]\r
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]\r
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]\r
+        EXPORT     SAI1_IRQHandler                   [WEAK]\r
+        EXPORT     SAI2_IRQHandler                   [WEAK]\r
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]\r
+        EXPORT     TSC_IRQHandler                    [WEAK]\r
+        EXPORT     RNG_IRQHandler                    [WEAK]\r
+        EXPORT     FPU_IRQHandler                    [WEAK]\r
+\r
+WWDG_IRQHandler\r
+PVD_PVM_IRQHandler\r
+TAMP_STAMP_IRQHandler\r
+RTC_WKUP_IRQHandler\r
+FLASH_IRQHandler\r
+RCC_IRQHandler\r
+EXTI0_IRQHandler\r
+EXTI1_IRQHandler\r
+EXTI2_IRQHandler\r
+EXTI3_IRQHandler\r
+EXTI4_IRQHandler\r
+DMA1_Channel1_IRQHandler\r
+DMA1_Channel2_IRQHandler\r
+DMA1_Channel3_IRQHandler\r
+DMA1_Channel4_IRQHandler\r
+DMA1_Channel5_IRQHandler\r
+DMA1_Channel6_IRQHandler\r
+DMA1_Channel7_IRQHandler\r
+ADC1_2_IRQHandler\r
+CAN1_TX_IRQHandler\r
+CAN1_RX0_IRQHandler\r
+CAN1_RX1_IRQHandler\r
+CAN1_SCE_IRQHandler\r
+EXTI9_5_IRQHandler\r
+TIM1_BRK_TIM15_IRQHandler\r
+TIM1_UP_TIM16_IRQHandler\r
+TIM1_TRG_COM_TIM17_IRQHandler\r
+TIM1_CC_IRQHandler\r
+TIM2_IRQHandler\r
+TIM3_IRQHandler\r
+TIM4_IRQHandler\r
+I2C1_EV_IRQHandler\r
+I2C1_ER_IRQHandler\r
+I2C2_EV_IRQHandler\r
+I2C2_ER_IRQHandler\r
+SPI1_IRQHandler\r
+SPI2_IRQHandler\r
+USART1_IRQHandler\r
+USART2_IRQHandler\r
+USART3_IRQHandler\r
+EXTI15_10_IRQHandler\r
+RTC_Alarm_IRQHandler\r
+DFSDM1_FLT3_IRQHandler\r
+TIM8_BRK_IRQHandler\r
+TIM8_UP_IRQHandler\r
+TIM8_TRG_COM_IRQHandler\r
+TIM8_CC_IRQHandler\r
+ADC3_IRQHandler\r
+FMC_IRQHandler\r
+SDMMC1_IRQHandler\r
+TIM5_IRQHandler\r
+SPI3_IRQHandler\r
+UART4_IRQHandler\r
+UART5_IRQHandler\r
+TIM6_DAC_IRQHandler\r
+TIM7_IRQHandler\r
+DMA2_Channel1_IRQHandler\r
+DMA2_Channel2_IRQHandler\r
+DMA2_Channel3_IRQHandler\r
+DMA2_Channel4_IRQHandler\r
+DMA2_Channel5_IRQHandler\r
+DFSDM1_FLT0_IRQHandler\r
+DFSDM1_FLT1_IRQHandler\r
+DFSDM1_FLT2_IRQHandler\r
+COMP_IRQHandler\r
+LPTIM1_IRQHandler\r
+LPTIM2_IRQHandler\r
+OTG_FS_IRQHandler\r
+DMA2_Channel6_IRQHandler\r
+DMA2_Channel7_IRQHandler\r
+LPUART1_IRQHandler\r
+QUADSPI_IRQHandler\r
+I2C3_EV_IRQHandler\r
+I2C3_ER_IRQHandler\r
+SAI1_IRQHandler\r
+SAI2_IRQHandler\r
+SWPMI1_IRQHandler\r
+TSC_IRQHandler\r
+RNG_IRQHandler\r
+FPU_IRQHandler\r
+\r
+                B       .\r
+\r
+                ENDP\r
+\r
+                ALIGN\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+                 IF      :DEF:__MICROLIB\r
+\r
+                 EXPORT  __initial_sp\r
+                 EXPORT  __heap_base\r
+                 EXPORT  __heap_limit\r
+\r
+                 ELSE\r
+\r
+                 IMPORT  __use_two_region_memory\r
+                 EXPORT  __user_initial_stackheap\r
+\r
+__user_initial_stackheap\r
+\r
+                 LDR     R0, =  Heap_Mem\r
+                 LDR     R1, =(Stack_Mem + Stack_Size)\r
+                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
+                 LDR     R3, = Stack_Mem\r
+                 BX      LR\r
+\r
+                 ALIGN\r
+\r
+                 ENDIF\r
+\r
+                 END\r
+\r
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/main.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/main.h
new file mode 100644 (file)
index 0000000..28f22d8
--- /dev/null
@@ -0,0 +1,236 @@
+/* USER CODE BEGIN Header */\r
+/**\r
+  ******************************************************************************\r
+  * @file           : main.h\r
+  * @brief          : Header for main.c file.\r
+  *                   This file contains the common defines of the application.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+/* USER CODE END Header */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MAIN_H\r
+#define __MAIN_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* USER CODE BEGIN ET */\r
+\r
+/* USER CODE END ET */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* USER CODE BEGIN EC */\r
+\r
+/* USER CODE END EC */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* USER CODE BEGIN EM */\r
+\r
+/* USER CODE END EM */\r
+\r
+/* Exported functions prototypes ---------------------------------------------*/\r
+void Error_Handler(void);\r
+\r
+/* USER CODE BEGIN EFP */\r
+\r
+/* USER CODE END EFP */\r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+#define M24SR64_Y_RF_DISABLE_Pin GPIO_PIN_2\r
+#define M24SR64_Y_RF_DISABLE_GPIO_Port GPIOE\r
+#define USB_OTG_FS_OVRCR_EXTI3_Pin GPIO_PIN_3\r
+#define USB_OTG_FS_OVRCR_EXTI3_GPIO_Port GPIOE\r
+#define M24SR64_Y_GPO_Pin GPIO_PIN_4\r
+#define M24SR64_Y_GPO_GPIO_Port GPIOE\r
+#define SPSGRF_915_GPIO3_EXTI5_Pin GPIO_PIN_5\r
+#define SPSGRF_915_GPIO3_EXTI5_GPIO_Port GPIOE\r
+#define SPSGRF_915_GPIO3_EXTI5_EXTI_IRQn EXTI9_5_IRQn\r
+#define SPBTLE_RF_IRQ_EXTI6_Pin GPIO_PIN_6\r
+#define SPBTLE_RF_IRQ_EXTI6_GPIO_Port GPIOE\r
+#define SPBTLE_RF_IRQ_EXTI6_EXTI_IRQn EXTI9_5_IRQn\r
+#define BUTTON_EXTI13_Pin GPIO_PIN_13\r
+#define BUTTON_EXTI13_GPIO_Port GPIOC\r
+#define BUTTON_EXTI13_EXTI_IRQn EXTI15_10_IRQn\r
+#define ARD_A5_Pin GPIO_PIN_0\r
+#define ARD_A5_GPIO_Port GPIOC\r
+#define ARD_A4_Pin GPIO_PIN_1\r
+#define ARD_A4_GPIO_Port GPIOC\r
+#define ARD_A3_Pin GPIO_PIN_2\r
+#define ARD_A3_GPIO_Port GPIOC\r
+#define ARD_A2_Pin GPIO_PIN_3\r
+#define ARD_A2_GPIO_Port GPIOC\r
+#define ARD_D1_Pin GPIO_PIN_0\r
+#define ARD_D1_GPIO_Port GPIOA\r
+#define ARD_D0_Pin GPIO_PIN_1\r
+#define ARD_D0_GPIO_Port GPIOA\r
+#define ARD_D10_Pin GPIO_PIN_2\r
+#define ARD_D10_GPIO_Port GPIOA\r
+#define ARD_D4_Pin GPIO_PIN_3\r
+#define ARD_D4_GPIO_Port GPIOA\r
+#define ARD_D7_Pin GPIO_PIN_4\r
+#define ARD_D7_GPIO_Port GPIOA\r
+#define ARD_D13_Pin GPIO_PIN_5\r
+#define ARD_D13_GPIO_Port GPIOA\r
+#define ARD_D12_Pin GPIO_PIN_6\r
+#define ARD_D12_GPIO_Port GPIOA\r
+#define ARD_D11_Pin GPIO_PIN_7\r
+#define ARD_D11_GPIO_Port GPIOA\r
+#define ARD_A1_Pin GPIO_PIN_4\r
+#define ARD_A1_GPIO_Port GPIOC\r
+#define ARD_A0_Pin GPIO_PIN_5\r
+#define ARD_A0_GPIO_Port GPIOC\r
+#define ARD_D3_Pin GPIO_PIN_0\r
+#define ARD_D3_GPIO_Port GPIOB\r
+#define ARD_D6_Pin GPIO_PIN_1\r
+#define ARD_D6_GPIO_Port GPIOB\r
+#define ARD_D8_Pin GPIO_PIN_2\r
+#define ARD_D8_GPIO_Port GPIOB\r
+#define DFSDM1_DATIN2_Pin GPIO_PIN_7\r
+#define DFSDM1_DATIN2_GPIO_Port GPIOE\r
+#define ISM43362_RST_Pin GPIO_PIN_8\r
+#define ISM43362_RST_GPIO_Port GPIOE\r
+#define DFSDM1_CKOUT_Pin GPIO_PIN_9\r
+#define DFSDM1_CKOUT_GPIO_Port GPIOE\r
+#define QUADSPI_CLK_Pin GPIO_PIN_10\r
+#define QUADSPI_CLK_GPIO_Port GPIOE\r
+#define QUADSPI_NCS_Pin GPIO_PIN_11\r
+#define QUADSPI_NCS_GPIO_Port GPIOE\r
+#define OQUADSPI_BK1_IO0_Pin GPIO_PIN_12\r
+#define OQUADSPI_BK1_IO0_GPIO_Port GPIOE\r
+#define QUADSPI_BK1_IO1_Pin GPIO_PIN_13\r
+#define QUADSPI_BK1_IO1_GPIO_Port GPIOE\r
+#define QUAD_SPI_BK1_IO2_Pin GPIO_PIN_14\r
+#define QUAD_SPI_BK1_IO2_GPIO_Port GPIOE\r
+#define QUAD_SPI_BK1_IO3_Pin GPIO_PIN_15\r
+#define QUAD_SPI_BK1_IO3_GPIO_Port GPIOE\r
+#define INTERNAL_I2C2_SCL_Pin GPIO_PIN_10\r
+#define INTERNAL_I2C2_SCL_GPIO_Port GPIOB\r
+#define INTERNAL_I2C2_SDA_Pin GPIO_PIN_11\r
+#define INTERNAL_I2C2_SDA_GPIO_Port GPIOB\r
+#define ISM43362_BOOT0_Pin GPIO_PIN_12\r
+#define ISM43362_BOOT0_GPIO_Port GPIOB\r
+#define ISM43362_WAKEUP_Pin GPIO_PIN_13\r
+#define ISM43362_WAKEUP_GPIO_Port GPIOB\r
+#define LED2_Pin GPIO_PIN_14\r
+#define LED2_GPIO_Port GPIOB\r
+#define SPSGRF_915_SDN_Pin GPIO_PIN_15\r
+#define SPSGRF_915_SDN_GPIO_Port GPIOB\r
+#define INTERNAL_UART3_TX_Pin GPIO_PIN_8\r
+#define INTERNAL_UART3_TX_GPIO_Port GPIOD\r
+#define INTERNAL_UART3_RX_Pin GPIO_PIN_9\r
+#define INTERNAL_UART3_RX_GPIO_Port GPIOD\r
+#define LPS22HB_INT_DRDY_EXTI0_Pin GPIO_PIN_10\r
+#define LPS22HB_INT_DRDY_EXTI0_GPIO_Port GPIOD\r
+#define LPS22HB_INT_DRDY_EXTI0_EXTI_IRQn EXTI15_10_IRQn\r
+#define LSM6DSL_INT1_EXTI11_Pin GPIO_PIN_11\r
+#define LSM6DSL_INT1_EXTI11_GPIO_Port GPIOD\r
+#define LSM6DSL_INT1_EXTI11_EXTI_IRQn EXTI15_10_IRQn\r
+#define USB_OTG_FS_PWR_EN_Pin GPIO_PIN_12\r
+#define USB_OTG_FS_PWR_EN_GPIO_Port GPIOD\r
+#define SPBTLE_RF_SPI3_CSN_Pin GPIO_PIN_13\r
+#define SPBTLE_RF_SPI3_CSN_GPIO_Port GPIOD\r
+#define ARD_D2_Pin GPIO_PIN_14\r
+#define ARD_D2_GPIO_Port GPIOD\r
+#define ARD_D2_EXTI_IRQn EXTI15_10_IRQn\r
+#define HTS221_DRDY_EXTI15_Pin GPIO_PIN_15\r
+#define HTS221_DRDY_EXTI15_GPIO_Port GPIOD\r
+#define HTS221_DRDY_EXTI15_EXTI_IRQn EXTI15_10_IRQn\r
+#define VL53L0X_XSHUT_Pin GPIO_PIN_6\r
+#define VL53L0X_XSHUT_GPIO_Port GPIOC\r
+#define VL53L0X_GPIO1_EXTI7_Pin GPIO_PIN_7\r
+#define VL53L0X_GPIO1_EXTI7_GPIO_Port GPIOC\r
+#define VL53L0X_GPIO1_EXTI7_EXTI_IRQn EXTI9_5_IRQn\r
+#define LSM3MDL_DRDY_EXTI8_Pin GPIO_PIN_8\r
+#define LSM3MDL_DRDY_EXTI8_GPIO_Port GPIOC\r
+#define LSM3MDL_DRDY_EXTI8_EXTI_IRQn EXTI9_5_IRQn\r
+#define LED3_WIFI__LED4_BLE_Pin GPIO_PIN_9\r
+#define LED3_WIFI__LED4_BLE_GPIO_Port GPIOC\r
+#define SPBTLE_RF_RST_Pin GPIO_PIN_8\r
+#define SPBTLE_RF_RST_GPIO_Port GPIOA\r
+#define USB_OTG_FS_VBUS_Pin GPIO_PIN_9\r
+#define USB_OTG_FS_VBUS_GPIO_Port GPIOA\r
+#define USB_OTG_FS_ID_Pin GPIO_PIN_10\r
+#define USB_OTG_FS_ID_GPIO_Port GPIOA\r
+#define USB_OTG_FS_DM_Pin GPIO_PIN_11\r
+#define USB_OTG_FS_DM_GPIO_Port GPIOA\r
+#define USB_OTG_FS_DP_Pin GPIO_PIN_12\r
+#define USB_OTG_FS_DP_GPIO_Port GPIOA\r
+#define SYS_JTMS_SWDIO_Pin GPIO_PIN_13\r
+#define SYS_JTMS_SWDIO_GPIO_Port GPIOA\r
+#define SYS_JTCK_SWCLK_Pin GPIO_PIN_14\r
+#define SYS_JTCK_SWCLK_GPIO_Port GPIOA\r
+#define ARD_D9_Pin GPIO_PIN_15\r
+#define ARD_D9_GPIO_Port GPIOA\r
+#define INTERNAL_SPI3_SCK_Pin GPIO_PIN_10\r
+#define INTERNAL_SPI3_SCK_GPIO_Port GPIOC\r
+#define INTERNAL_SPI3_MISO_Pin GPIO_PIN_11\r
+#define INTERNAL_SPI3_MISO_GPIO_Port GPIOC\r
+#define INTERNAL_SPI3_MOSI_Pin GPIO_PIN_12\r
+#define INTERNAL_SPI3_MOSI_GPIO_Port GPIOC\r
+#define PMOD_RESET_Pin GPIO_PIN_0\r
+#define PMOD_RESET_GPIO_Port GPIOD\r
+#define PMOD_SPI2_SCK_Pin GPIO_PIN_1\r
+#define PMOD_SPI2_SCK_GPIO_Port GPIOD\r
+#define PMOD_IRQ_EXTI12_Pin GPIO_PIN_2\r
+#define PMOD_IRQ_EXTI12_GPIO_Port GPIOD\r
+#define PMOD_UART2_CTS_Pin GPIO_PIN_3\r
+#define PMOD_UART2_CTS_GPIO_Port GPIOD\r
+#define PMOD_UART2_RTS_Pin GPIO_PIN_4\r
+#define PMOD_UART2_RTS_GPIO_Port GPIOD\r
+#define PMOD_UART2_TX_Pin GPIO_PIN_5\r
+#define PMOD_UART2_TX_GPIO_Port GPIOD\r
+#define PMOD_UART2_RX_Pin GPIO_PIN_6\r
+#define PMOD_UART2_RX_GPIO_Port GPIOD\r
+#define STSAFE_A100_RESET_Pin GPIO_PIN_7\r
+#define STSAFE_A100_RESET_GPIO_Port GPIOD\r
+#define SYS_JTD0_SWO_Pin GPIO_PIN_3\r
+#define SYS_JTD0_SWO_GPIO_Port GPIOB\r
+#define ARD_D5_Pin GPIO_PIN_4\r
+#define ARD_D5_GPIO_Port GPIOB\r
+#define SPSGRF_915_SPI3_CSN_Pin GPIO_PIN_5\r
+#define SPSGRF_915_SPI3_CSN_GPIO_Port GPIOB\r
+#define ST_LINK_UART1_TX_Pin GPIO_PIN_6\r
+#define ST_LINK_UART1_TX_GPIO_Port GPIOB\r
+#define ST_LINK_UART1_RX_Pin GPIO_PIN_7\r
+#define ST_LINK_UART1_RX_GPIO_Port GPIOB\r
+#define ARD_D15_Pin GPIO_PIN_8\r
+#define ARD_D15_GPIO_Port GPIOB\r
+#define ARD_D14_Pin GPIO_PIN_9\r
+#define ARD_D14_GPIO_Port GPIOB\r
+#define ISM43362_SPI3_CSN_Pin GPIO_PIN_0\r
+#define ISM43362_SPI3_CSN_GPIO_Port GPIOE\r
+#define ISM43362_DRDY_EXTI1_Pin GPIO_PIN_1\r
+#define ISM43362_DRDY_EXTI1_GPIO_Port GPIOE\r
+/* USER CODE BEGIN Private defines */\r
+\r
+/* USER CODE END Private defines */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MAIN_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/stm32l4xx_hal_conf.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/stm32l4xx_hal_conf.h
new file mode 100644 (file)
index 0000000..25b2a0d
--- /dev/null
@@ -0,0 +1,440 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_conf.h\r
+  * @brief   HAL configuration file.             \r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>\r
+  *\r
+  * Redistribution and use in source and binary forms, with or without modification,\r
+  * are permitted provided that the following conditions are met:\r
+  *   1. Redistributions of source code must retain the above copyright notice,\r
+  *      this list of conditions and the following disclaimer.\r
+  *   2. Redistributions in binary form must reproduce the above copyright notice,\r
+  *      this list of conditions and the following disclaimer in the documentation\r
+  *      and/or other materials provided with the distribution.\r
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
+  *      may be used to endorse or promote products derived from this software\r
+  *      without specific prior written permission.\r
+  *\r
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+  *\r
+  ******************************************************************************\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_CONF_H\r
+#define __STM32L4xx_HAL_CONF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* ########################## Module Selection ############################## */\r
+/**\r
+  * @brief This is the list of modules to be used in the HAL driver \r
+  */\r
+\r
+#define HAL_MODULE_ENABLED  \r
+/*#define HAL_ADC_MODULE_ENABLED   */\r
+/*#define HAL_CRYP_MODULE_ENABLED   */\r
+/*#define HAL_CAN_MODULE_ENABLED   */\r
+/*#define HAL_COMP_MODULE_ENABLED   */\r
+/*#define HAL_CRC_MODULE_ENABLED   */\r
+/*#define HAL_CRYP_MODULE_ENABLED   */\r
+/*#define HAL_DAC_MODULE_ENABLED   */\r
+/*#define HAL_DCMI_MODULE_ENABLED   */\r
+/*#define HAL_DMA2D_MODULE_ENABLED   */\r
+#define HAL_DFSDM_MODULE_ENABLED\r
+/*#define HAL_DSI_MODULE_ENABLED   */\r
+/*#define HAL_FIREWALL_MODULE_ENABLED   */\r
+/*#define HAL_GFXMMU_MODULE_ENABLED   */\r
+/*#define HAL_HCD_MODULE_ENABLED   */\r
+/*#define HAL_HASH_MODULE_ENABLED   */\r
+/*#define HAL_I2S_MODULE_ENABLED   */\r
+/*#define HAL_IRDA_MODULE_ENABLED   */\r
+/*#define HAL_IWDG_MODULE_ENABLED   */\r
+/*#define HAL_LTDC_MODULE_ENABLED   */\r
+/*#define HAL_LCD_MODULE_ENABLED   */\r
+/*#define HAL_LPTIM_MODULE_ENABLED   */\r
+/*#define HAL_MMC_MODULE_ENABLED   */\r
+/*#define HAL_NAND_MODULE_ENABLED   */\r
+/*#define HAL_NOR_MODULE_ENABLED   */\r
+/*#define HAL_OPAMP_MODULE_ENABLED   */\r
+/*#define HAL_OSPI_MODULE_ENABLED   */\r
+/*#define HAL_OSPI_MODULE_ENABLED   */\r
+#define HAL_PCD_MODULE_ENABLED\r
+/*#define HAL_QSPI_MODULE_ENABLED   */\r
+#define HAL_QSPI_MODULE_ENABLED\r
+/*#define HAL_RNG_MODULE_ENABLED   */\r
+/*#define HAL_RTC_MODULE_ENABLED   */\r
+/*#define HAL_SAI_MODULE_ENABLED   */\r
+/*#define HAL_SD_MODULE_ENABLED   */\r
+/*#define HAL_SMBUS_MODULE_ENABLED   */\r
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */\r
+#define HAL_SPI_MODULE_ENABLED\r
+/*#define HAL_SRAM_MODULE_ENABLED   */\r
+/*#define HAL_SWPMI_MODULE_ENABLED   */\r
+#define HAL_TIM_MODULE_ENABLED\r
+/*#define HAL_TSC_MODULE_ENABLED   */\r
+#define HAL_UART_MODULE_ENABLED\r
+/*#define HAL_USART_MODULE_ENABLED   */\r
+/*#define HAL_WWDG_MODULE_ENABLED   */\r
+/*#define HAL_EXTI_MODULE_ENABLED   */\r
+#define HAL_GPIO_MODULE_ENABLED\r
+#define HAL_EXTI_MODULE_ENABLED \r
+#define HAL_I2C_MODULE_ENABLED\r
+#define HAL_DMA_MODULE_ENABLED\r
+#define HAL_RCC_MODULE_ENABLED\r
+#define HAL_FLASH_MODULE_ENABLED\r
+#define HAL_PWR_MODULE_ENABLED\r
+#define HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* ########################## Oscillator Values adaptation ####################*/\r
+/**\r
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
+  *        This value is used by the RCC HAL module to compute the system frequency\r
+  *        (when HSE is used as system clock source, directly or through the PLL).  \r
+  */\r
+#if !defined  (HSE_VALUE) \r
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined  (HSE_STARTUP_TIMEOUT)\r
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+  * @brief Internal Multiple Speed oscillator (MSI) default value.\r
+  *        This value is the default MSI range value after Reset.\r
+  */\r
+#if !defined  (MSI_VALUE)\r
+  #define MSI_VALUE    ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* MSI_VALUE */\r
+/**\r
+  * @brief Internal High Speed oscillator (HSI) value.\r
+  *        This value is used by the RCC HAL module to compute the system frequency\r
+  *        (when HSI is used as system clock source, directly or through the PLL). \r
+  */\r
+#if !defined  (HSI_VALUE)\r
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.\r
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to\r
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.\r
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency\r
+  *        which is subject to manufacturing process variations.\r
+  */\r
+#if !defined  (HSI48_VALUE) \r
+ #define HSI48_VALUE   ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.\r
+                                              The real value my vary depending on manufacturing process variations.*/\r
+#endif /* HSI48_VALUE */\r
+\r
+/**\r
+  * @brief Internal Low Speed oscillator (LSI) value.\r
+  */\r
+#if !defined  (LSI_VALUE) \r
+ #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/\r
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz\r
+                                             The real value may vary depending on the variations\r
+                                             in voltage and temperature.*/\r
+\r
+/**\r
+  * @brief External Low Speed oscillator (LSE) value.\r
+  *        This value is used by the UART, RTC HAL module to compute the system frequency\r
+  */\r
+#if !defined  (LSE_VALUE)\r
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/\r
+#endif /* LSE_VALUE */\r
+\r
+#if !defined  (LSE_STARTUP_TIMEOUT)\r
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+  * @brief External clock source for SAI1 peripheral\r
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source \r
+  *        frequency.\r
+  */\r
+#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)\r
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/\r
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */\r
+\r
+/**\r
+  * @brief External clock source for SAI2 peripheral\r
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source \r
+  *        frequency.\r
+  */\r
+#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)\r
+  #define EXTERNAL_SAI2_CLOCK_VALUE    ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/\r
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */\r
+\r
+/* Tip: To avoid modifying this file each time you need to use different HSE,\r
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */\r
+\r
+/* ########################### System Configuration ######################### */\r
+/**\r
+  * @brief This is the HAL system configuration section\r
+  */     \r
+  \r
+#define  VDD_VALUE                                       ((uint32_t)3300U) /*!< Value of VDD in mv */           \r
+#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */            \r
+#define  USE_RTOS                     0U     \r
+#define  PREFETCH_ENABLE              0U\r
+#define  INSTRUCTION_CACHE_ENABLE     1U\r
+#define  DATA_CACHE_ENABLE            1U\r
+\r
+/* ########################## Assert Selection ############################## */\r
+/**\r
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
+  *        HAL drivers code\r
+  */\r
+/* #define USE_FULL_ASSERT    1U */\r
+\r
+/* ################## SPI peripheral configuration ########################## */\r
+\r
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\r
+ * Activated: CRC code is present inside driver\r
+ * Deactivated: CRC code cleaned from driver\r
+ */\r
+\r
+#define USE_SPI_CRC                   0U\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/**\r
+  * @brief Include module's header file\r
+  */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_rcc.h"\r
+  #include "stm32l4xx_hal_rcc_ex.h"\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_EXTI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_exti.h"\r
+#endif /* HAL_EXTI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_gpio.h"\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_dma.h"\r
+  #include "stm32l4xx_hal_dma_ex.h"\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DFSDM_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_dfsdm.h"\r
+#endif /* HAL_DFSDM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_cortex.h"\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_adc.h"\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CAN_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_can.h"\r
+#endif /* HAL_CAN_MODULE_ENABLED */\r
+\r
+#ifdef HAL_COMP_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_comp.h"\r
+#endif /* HAL_COMP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_crc.h"\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_cryp.h"\r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_dac.h"\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_dcmi.h"\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_dma2d.h"\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DSI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_dsi.h"\r
+#endif /* HAL_DSI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FIREWALL_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_firewall.h"\r
+#endif /* HAL_FIREWALL_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_flash.h"\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_hash.h"\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_sram.h"\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_MMC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_mmc.h"\r
+#endif /* HAL_MMC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_nor.h"\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_nand.h"\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_i2c.h"\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_iwdg.h"\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LCD_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_lcd.h"\r
+#endif /* HAL_LCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_lptim.h"\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_ltdc.h"\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_OPAMP_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_opamp.h"\r
+#endif /* HAL_OPAMP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_OSPI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_ospi.h"\r
+#endif /* HAL_OSPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_pwr.h"\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_qspi.h"\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_rng.h"\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_rtc.h"\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_sai.h"\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_sd.h"\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMBUS_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_smbus.h"\r
+#endif /* HAL_SMBUS_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_spi.h"\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SWPMI_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_swpmi.h"\r
+#endif /* HAL_SWPMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_tim.h"\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TSC_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_tsc.h"\r
+#endif /* HAL_TSC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_uart.h"\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_usart.h"\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_irda.h"\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_smartcard.h"\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_wwdg.h"\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_pcd.h"\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_hcd.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GFXMMU_MODULE_ENABLED\r
+  #include "stm32l4xx_hal_gfxmmu.h"\r
+#endif /* HAL_GFXMMU_MODULE_ENABLED */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef  USE_FULL_ASSERT\r
+/**\r
+  * @brief  The assert_param macro is used for function's parameters check.\r
+  * @param  expr: If expr is false, it calls assert_failed function\r
+  *         which reports the name of the source file and the source\r
+  *         line number of the call that failed.\r
+  *         If expr is true, it returns no value.\r
+  * @retval None\r
+  */\r
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+  void assert_failed(char *file, uint32_t line);\r
+#else\r
+  #define assert_param(expr) ((void)0U)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_CONF_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/stm32l4xx_it.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Inc/stm32l4xx_it.h
new file mode 100644 (file)
index 0000000..832f37a
--- /dev/null
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */\r
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_it.h\r
+  * @brief   This file contains the headers of the interrupt handlers.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+ ******************************************************************************\r
+  */\r
+/* USER CODE END Header */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_IT_H\r
+#define __STM32L4xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* USER CODE BEGIN ET */\r
+\r
+/* USER CODE END ET */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* USER CODE BEGIN EC */\r
+\r
+/* USER CODE END EC */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* USER CODE BEGIN EM */\r
+\r
+/* USER CODE END EM */\r
+\r
+/* Exported functions prototypes ---------------------------------------------*/\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void DebugMon_Handler(void);\r
+void EXTI9_5_IRQHandler(void);\r
+void EXTI15_10_IRQHandler(void);\r
+void TIM6_DAC_IRQHandler(void);\r
+/* USER CODE BEGIN EFP */\r
+\r
+/* USER CODE END EFP */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_IT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/main.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/main.c
new file mode 100644 (file)
index 0000000..cfeb512
--- /dev/null
@@ -0,0 +1,710 @@
+/* USER CODE BEGIN Header */\r
+/**\r
+  ******************************************************************************\r
+  * @file           : main.c\r
+  * @brief          : Main program body\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+#include "app_main.h"\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN PTD */\r
+\r
+/* USER CODE END PTD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN PD */\r
+/* USER CODE END PD */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN PM */\r
+\r
+/* USER CODE END PM */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+DFSDM_Channel_HandleTypeDef hdfsdm1_channel1;\r
+\r
+I2C_HandleTypeDef hi2c2;\r
+\r
+QSPI_HandleTypeDef hqspi;\r
+\r
+SPI_HandleTypeDef hspi3;\r
+\r
+UART_HandleTypeDef huart1;\r
+UART_HandleTypeDef huart3;\r
+\r
+PCD_HandleTypeDef hpcd_USB_OTG_FS;\r
+\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+void SystemClock_Config(void);\r
+static void MX_GPIO_Init(void);\r
+static void MX_DFSDM1_Init(void);\r
+static void MX_I2C2_Init(void);\r
+static void MX_QUADSPI_Init(void);\r
+static void MX_SPI3_Init(void);\r
+static void MX_USART1_UART_Init(void);\r
+static void MX_USART3_UART_Init(void);\r
+static void MX_USB_OTG_FS_PCD_Init(void);\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* Private user code ---------------------------------------------------------*/\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+\r
+/**\r
+  * @brief  The application entry point.\r
+  * @retval int\r
+  */\r
+int main(void)\r
+{\r
+  /* USER CODE BEGIN 1 */\r
+\r
+  /* USER CODE END 1 */\r
+  \r
+\r
+  /* MCU Configuration--------------------------------------------------------*/\r
+\r
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\r
+  HAL_Init();\r
+\r
+  /* USER CODE BEGIN Init */\r
+\r
+  /* USER CODE END Init */\r
+\r
+  /* Configure the system clock */\r
+  SystemClock_Config();\r
+\r
+  /* USER CODE BEGIN SysInit */\r
+\r
+  /* USER CODE END SysInit */\r
+\r
+  /* Initialize all configured peripherals */\r
+  MX_GPIO_Init();\r
+  MX_DFSDM1_Init();\r
+  MX_I2C2_Init();\r
+  MX_QUADSPI_Init();\r
+  MX_SPI3_Init();\r
+  MX_USART1_UART_Init();\r
+  MX_USART3_UART_Init();\r
+  MX_USB_OTG_FS_PCD_Init();\r
+  /* USER CODE BEGIN 2 */\r
+  /* Call our entry point. */\r
+  app_main();\r
+  /* USER CODE END 2 */\r
+\r
+  /* Infinite loop */\r
+  /* USER CODE BEGIN WHILE */\r
+  while (1)\r
+  {\r
+    /* USER CODE END WHILE */\r
+\r
+    /* USER CODE BEGIN 3 */\r
+  }\r
+  /* USER CODE END 3 */\r
+}\r
+\r
+/**\r
+  * @brief System Clock Configuration\r
+  * @retval None\r
+  */\r
+void SystemClock_Config(void)\r
+{\r
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};\r
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};\r
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};\r
+\r
+  /** Configure LSE Drive Capability \r
+  */\r
+  HAL_PWR_EnableBkUpAccess();\r
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);\r
+  /** Initializes the CPU, AHB and APB busses clocks \r
+  */\r
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;\r
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;\r
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;\r
+  RCC_OscInitStruct.MSICalibrationValue = 0;\r
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;\r
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;\r
+  RCC_OscInitStruct.PLL.PLLM = 1;\r
+  RCC_OscInitStruct.PLL.PLLN = 40;\r
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;\r
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;\r
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;\r
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /** Initializes the CPU, AHB and APB busses clocks \r
+  */\r
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\r
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;\r
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;\r
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;\r
+\r
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART3\r
+                              |RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_DFSDM1\r
+                              |RCC_PERIPHCLK_USB;\r
+  PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;\r
+  PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;\r
+  PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;\r
+  PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;\r
+  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;\r
+  PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;\r
+  PeriphClkInit.PLLSAI1.PLLSAI1M = 1;\r
+  PeriphClkInit.PLLSAI1.PLLSAI1N = 24;\r
+  PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;\r
+  PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;\r
+  PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;\r
+  PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;\r
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /** Configure the main internal regulator output voltage \r
+  */\r
+  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /** Enable MSI Auto calibration \r
+  */\r
+  HAL_RCCEx_EnableMSIPLLMode();\r
+}\r
+\r
+/**\r
+  * @brief DFSDM1 Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_DFSDM1_Init(void)\r
+{\r
+\r
+  /* USER CODE BEGIN DFSDM1_Init 0 */\r
+\r
+  /* USER CODE END DFSDM1_Init 0 */\r
+\r
+  /* USER CODE BEGIN DFSDM1_Init 1 */\r
+\r
+  /* USER CODE END DFSDM1_Init 1 */\r
+  hdfsdm1_channel1.Instance = DFSDM1_Channel1;\r
+  hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;\r
+  hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;\r
+  hdfsdm1_channel1.Init.OutputClock.Divider = 2;\r
+  hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;\r
+  hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;\r
+  hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;\r
+  hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;\r
+  hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;\r
+  hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;\r
+  hdfsdm1_channel1.Init.Awd.Oversampling = 1;\r
+  hdfsdm1_channel1.Init.Offset = 0;\r
+  hdfsdm1_channel1.Init.RightBitShift = 0x00;\r
+  if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /* USER CODE BEGIN DFSDM1_Init 2 */\r
+\r
+  /* USER CODE END DFSDM1_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+  * @brief I2C2 Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_I2C2_Init(void)\r
+{\r
+\r
+  /* USER CODE BEGIN I2C2_Init 0 */\r
+\r
+  /* USER CODE END I2C2_Init 0 */\r
+\r
+  /* USER CODE BEGIN I2C2_Init 1 */\r
+\r
+  /* USER CODE END I2C2_Init 1 */\r
+  hi2c2.Instance = I2C2;\r
+  hi2c2.Init.Timing = 0x10909CEC;\r
+  hi2c2.Init.OwnAddress1 = 0;\r
+  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;\r
+  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;\r
+  hi2c2.Init.OwnAddress2 = 0;\r
+  hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;\r
+  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;\r
+  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;\r
+  if (HAL_I2C_Init(&hi2c2) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /** Configure Analogue filter \r
+  */\r
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /** Configure Digital filter \r
+  */\r
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /* USER CODE BEGIN I2C2_Init 2 */\r
+\r
+  /* USER CODE END I2C2_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+  * @brief QUADSPI Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_QUADSPI_Init(void)\r
+{\r
+\r
+  /* USER CODE BEGIN QUADSPI_Init 0 */\r
+\r
+  /* USER CODE END QUADSPI_Init 0 */\r
+\r
+  /* USER CODE BEGIN QUADSPI_Init 1 */\r
+\r
+  /* USER CODE END QUADSPI_Init 1 */\r
+  /* QUADSPI parameter configuration*/\r
+  hqspi.Instance = QUADSPI;\r
+  hqspi.Init.ClockPrescaler = 255;\r
+  hqspi.Init.FifoThreshold = 1;\r
+  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE;\r
+  hqspi.Init.FlashSize = 1;\r
+  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;\r
+  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;\r
+  if (HAL_QSPI_Init(&hqspi) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /* USER CODE BEGIN QUADSPI_Init 2 */\r
+\r
+  /* USER CODE END QUADSPI_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+  * @brief SPI3 Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_SPI3_Init(void)\r
+{\r
+\r
+  /* USER CODE BEGIN SPI3_Init 0 */\r
+\r
+  /* USER CODE END SPI3_Init 0 */\r
+\r
+  /* USER CODE BEGIN SPI3_Init 1 */\r
+\r
+  /* USER CODE END SPI3_Init 1 */\r
+  /* SPI3 parameter configuration*/\r
+  hspi3.Instance = SPI3;\r
+  hspi3.Init.Mode = SPI_MODE_MASTER;\r
+  hspi3.Init.Direction = SPI_DIRECTION_2LINES;\r
+  hspi3.Init.DataSize = SPI_DATASIZE_4BIT;\r
+  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;\r
+  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;\r
+  hspi3.Init.NSS = SPI_NSS_SOFT;\r
+  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\r
+  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;\r
+  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;\r
+  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
+  hspi3.Init.CRCPolynomial = 7;\r
+  hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;\r
+  hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;\r
+  if (HAL_SPI_Init(&hspi3) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /* USER CODE BEGIN SPI3_Init 2 */\r
+\r
+  /* USER CODE END SPI3_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+  * @brief USART1 Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_USART1_UART_Init(void)\r
+{\r
+\r
+  /* USER CODE BEGIN USART1_Init 0 */\r
+\r
+  /* USER CODE END USART1_Init 0 */\r
+\r
+  /* USER CODE BEGIN USART1_Init 1 */\r
+\r
+  /* USER CODE END USART1_Init 1 */\r
+  huart1.Instance = USART1;\r
+  huart1.Init.BaudRate = 115200;\r
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;\r
+  huart1.Init.StopBits = UART_STOPBITS_1;\r
+  huart1.Init.Parity = UART_PARITY_NONE;\r
+  huart1.Init.Mode = UART_MODE_TX_RX;\r
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;\r
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;\r
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;\r
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;\r
+  if (HAL_UART_Init(&huart1) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /* USER CODE BEGIN USART1_Init 2 */\r
+\r
+  /* USER CODE END USART1_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+  * @brief USART3 Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_USART3_UART_Init(void)\r
+{\r
+\r
+  /* USER CODE BEGIN USART3_Init 0 */\r
+\r
+  /* USER CODE END USART3_Init 0 */\r
+\r
+  /* USER CODE BEGIN USART3_Init 1 */\r
+\r
+  /* USER CODE END USART3_Init 1 */\r
+  huart3.Instance = USART3;\r
+  huart3.Init.BaudRate = 115200;\r
+  huart3.Init.WordLength = UART_WORDLENGTH_8B;\r
+  huart3.Init.StopBits = UART_STOPBITS_1;\r
+  huart3.Init.Parity = UART_PARITY_NONE;\r
+  huart3.Init.Mode = UART_MODE_TX_RX;\r
+  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;\r
+  huart3.Init.OverSampling = UART_OVERSAMPLING_16;\r
+  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;\r
+  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;\r
+  if (HAL_UART_Init(&huart3) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /* USER CODE BEGIN USART3_Init 2 */\r
+\r
+  /* USER CODE END USART3_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+  * @brief USB_OTG_FS Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_USB_OTG_FS_PCD_Init(void)\r
+{\r
+\r
+  /* USER CODE BEGIN USB_OTG_FS_Init 0 */\r
+\r
+  /* USER CODE END USB_OTG_FS_Init 0 */\r
+\r
+  /* USER CODE BEGIN USB_OTG_FS_Init 1 */\r
+\r
+  /* USER CODE END USB_OTG_FS_Init 1 */\r
+  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;\r
+  hpcd_USB_OTG_FS.Init.dev_endpoints = 6;\r
+  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;\r
+  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;\r
+  hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;\r
+  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;\r
+  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;\r
+  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;\r
+  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;\r
+  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;\r
+  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)\r
+  {\r
+    Error_Handler();\r
+  }\r
+  /* USER CODE BEGIN USB_OTG_FS_Init 2 */\r
+\r
+  /* USER CODE END USB_OTG_FS_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+  * @brief GPIO Initialization Function\r
+  * @param None\r
+  * @retval None\r
+  */\r
+static void MX_GPIO_Init(void)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+\r
+  /* GPIO Ports Clock Enable */\r
+  __HAL_RCC_GPIOE_CLK_ENABLE();\r
+  __HAL_RCC_GPIOC_CLK_ENABLE();\r
+  __HAL_RCC_GPIOA_CLK_ENABLE();\r
+  __HAL_RCC_GPIOB_CLK_ENABLE();\r
+  __HAL_RCC_GPIOD_CLK_ENABLE();\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET);\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin \r
+                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET);\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);\r
+\r
+  /*Configure GPIO pin Output Level */\r
+  HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);\r
+\r
+  /*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */\r
+  GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */\r
+  GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pin : BUTTON_EXTI13_Pin */\r
+  GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin \r
+                           ARD_A1_Pin ARD_A0_Pin */\r
+  GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin \r
+                          |ARD_A1_Pin|ARD_A0_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+  GPIO_InitStruct.Alternate = GPIO_AF8_UART4;\r
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : ARD_D10_Pin SPBTLE_RF_RST_Pin ARD_D9_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pin : ARD_D4_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D4_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+  GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;\r
+  HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pin : ARD_D7_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D7_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : ARD_D13_Pin ARD_D12_Pin ARD_D11_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin|ARD_D11_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+  GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\r
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pin : ARD_D3_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D3_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pin : ARD_D6_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D6_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin \r
+                           SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin \r
+                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin \r
+                           PMOD_IRQ_EXTI12_Pin */\r
+  GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin \r
+                          |PMOD_IRQ_EXTI12_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */\r
+  GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */\r
+  GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */\r
+  GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pin : PMOD_SPI2_SCK_Pin */\r
+  GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+  GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;\r
+  HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */\r
+  GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+  GPIO_InitStruct.Alternate = GPIO_AF7_USART2;\r
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
+\r
+  /*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */\r
+  GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\r
+  GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+  GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;\r
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
+\r
+  /* EXTI interrupt init*/\r
+  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);\r
+  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);\r
+\r
+  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);\r
+  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);\r
+\r
+}\r
+\r
+/* USER CODE BEGIN 4 */\r
+\r
+/* USER CODE END 4 */\r
+\r
+/**\r
+  * @brief  Period elapsed callback in non blocking mode\r
+  * @note   This function is called  when TIM6 interrupt took place, inside\r
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment\r
+  * a global variable "uwTick" used as application time base.\r
+  * @param  htim : TIM handle\r
+  * @retval None\r
+  */\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* USER CODE BEGIN Callback 0 */\r
+\r
+  /* USER CODE END Callback 0 */\r
+  if (htim->Instance == TIM6) {\r
+    HAL_IncTick();\r
+  }\r
+  /* USER CODE BEGIN Callback 1 */\r
+\r
+  /* USER CODE END Callback 1 */\r
+}\r
+\r
+/**\r
+  * @brief  This function is executed in case of error occurrence.\r
+  * @retval None\r
+  */\r
+void Error_Handler(void)\r
+{\r
+  /* USER CODE BEGIN Error_Handler_Debug */\r
+  /* User can add his own implementation to report the HAL error return state */\r
+\r
+  /* USER CODE END Error_Handler_Debug */\r
+}\r
+\r
+#ifdef  USE_FULL_ASSERT\r
+/**\r
+  * @brief  Reports the name of the source file and the source line number\r
+  *         where the assert_param error has occurred.\r
+  * @param  file: pointer to the source file name\r
+  * @param  line: assert_param error line source number\r
+  * @retval None\r
+  */\r
+void assert_failed(char *file, uint32_t line)\r
+{ \r
+  /* USER CODE BEGIN 6 */\r
+  /* User can add his own implementation to report the file name and line number,\r
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
+  /* USER CODE END 6 */\r
+}\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_hal_msp.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_hal_msp.c
new file mode 100644 (file)
index 0000000..a8cea7a
--- /dev/null
@@ -0,0 +1,562 @@
+/* USER CODE BEGIN Header */\r
+/**\r
+  ******************************************************************************\r
+  * File Name          : stm32l4xx_hal_msp.c\r
+  * Description        : This file provides code for the MSP Initialization \r
+  *                      and de-Initialization codes.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN TD */\r
+\r
+/* USER CODE END TD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN Define */\r
\r
+/* USER CODE END Define */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN Macro */\r
+\r
+/* USER CODE END Macro */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* External functions --------------------------------------------------------*/\r
+/* USER CODE BEGIN ExternalFunctions */\r
+\r
+/* USER CODE END ExternalFunctions */\r
+\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+/**\r
+  * Initializes the Global MSP.\r
+  */\r
+void HAL_MspInit(void)\r
+{\r
+  /* USER CODE BEGIN MspInit 0 */\r
+\r
+  /* USER CODE END MspInit 0 */\r
+\r
+  __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+  __HAL_RCC_PWR_CLK_ENABLE();\r
+\r
+  /* System interrupt init*/\r
+\r
+  /* USER CODE BEGIN MspInit 1 */\r
+\r
+  /* USER CODE END MspInit 1 */\r
+}\r
+\r
+static uint32_t DFSDM1_Init = 0;\r
+/**\r
+* @brief DFSDM_Channel MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param hdfsdm_channel: DFSDM_Channel handle pointer\r
+* @retval None\r
+*/\r
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+  if(DFSDM1_Init == 0)\r
+  {\r
+  /* USER CODE BEGIN DFSDM1_MspInit 0 */\r
+\r
+  /* USER CODE END DFSDM1_MspInit 0 */\r
+    /* Peripheral clock enable */\r
+    __HAL_RCC_DFSDM1_CLK_ENABLE();\r
+  \r
+    __HAL_RCC_GPIOE_CLK_ENABLE();\r
+    /**DFSDM1 GPIO Configuration    \r
+    PE7     ------> DFSDM1_DATIN2\r
+    PE9     ------> DFSDM1_CKOUT \r
+    */\r
+    GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+    GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;\r
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
+\r
+  /* USER CODE BEGIN DFSDM1_MspInit 1 */\r
+\r
+  /* USER CODE END DFSDM1_MspInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief DFSDM_Channel MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param hdfsdm_channel: DFSDM_Channel handle pointer\r
+* @retval None\r
+*/\r
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)\r
+{\r
+  DFSDM1_Init-- ;\r
+  if(DFSDM1_Init == 0)\r
+    {\r
+  /* USER CODE BEGIN DFSDM1_MspDeInit 0 */\r
+\r
+  /* USER CODE END DFSDM1_MspDeInit 0 */\r
+    /* Peripheral clock disable */\r
+    __HAL_RCC_DFSDM1_CLK_DISABLE();\r
+  \r
+    /**DFSDM1 GPIO Configuration    \r
+    PE7     ------> DFSDM1_DATIN2\r
+    PE9     ------> DFSDM1_CKOUT \r
+    */\r
+    HAL_GPIO_DeInit(GPIOE, DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin);\r
+\r
+  /* USER CODE BEGIN DFSDM1_MspDeInit 1 */\r
+\r
+  /* USER CODE END DFSDM1_MspDeInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief I2C MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param hi2c: I2C handle pointer\r
+* @retval None\r
+*/\r
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+  if(hi2c->Instance==I2C2)\r
+  {\r
+  /* USER CODE BEGIN I2C2_MspInit 0 */\r
+\r
+  /* USER CODE END I2C2_MspInit 0 */\r
+  \r
+    __HAL_RCC_GPIOB_CLK_ENABLE();\r
+    /**I2C2 GPIO Configuration    \r
+    PB10     ------> I2C2_SCL\r
+    PB11     ------> I2C2_SDA \r
+    */\r
+    GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\r
+    GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;\r
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
+\r
+    /* Peripheral clock enable */\r
+    __HAL_RCC_I2C2_CLK_ENABLE();\r
+  /* USER CODE BEGIN I2C2_MspInit 1 */\r
+\r
+  /* USER CODE END I2C2_MspInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief I2C MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param hi2c: I2C handle pointer\r
+* @retval None\r
+*/\r
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)\r
+{\r
+  if(hi2c->Instance==I2C2)\r
+  {\r
+  /* USER CODE BEGIN I2C2_MspDeInit 0 */\r
+\r
+  /* USER CODE END I2C2_MspDeInit 0 */\r
+    /* Peripheral clock disable */\r
+    __HAL_RCC_I2C2_CLK_DISABLE();\r
+  \r
+    /**I2C2 GPIO Configuration    \r
+    PB10     ------> I2C2_SCL\r
+    PB11     ------> I2C2_SDA \r
+    */\r
+    HAL_GPIO_DeInit(GPIOB, INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin);\r
+\r
+  /* USER CODE BEGIN I2C2_MspDeInit 1 */\r
+\r
+  /* USER CODE END I2C2_MspDeInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief QSPI MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param hqspi: QSPI handle pointer\r
+* @retval None\r
+*/\r
+void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+  if(hqspi->Instance==QUADSPI)\r
+  {\r
+  /* USER CODE BEGIN QUADSPI_MspInit 0 */\r
+\r
+  /* USER CODE END QUADSPI_MspInit 0 */\r
+    /* Peripheral clock enable */\r
+    __HAL_RCC_QSPI_CLK_ENABLE();\r
+  \r
+    __HAL_RCC_GPIOE_CLK_ENABLE();\r
+    /**QUADSPI GPIO Configuration    \r
+    PE10     ------> QUADSPI_CLK\r
+    PE11     ------> QUADSPI_NCS\r
+    PE12     ------> QUADSPI_BK1_IO0\r
+    PE13     ------> QUADSPI_BK1_IO1\r
+    PE14     ------> QUADSPI_BK1_IO2\r
+    PE15     ------> QUADSPI_BK1_IO3 \r
+    */\r
+    GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin \r
+                          |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;\r
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
+\r
+  /* USER CODE BEGIN QUADSPI_MspInit 1 */\r
+\r
+  /* USER CODE END QUADSPI_MspInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief QSPI MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param hqspi: QSPI handle pointer\r
+* @retval None\r
+*/\r
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)\r
+{\r
+  if(hqspi->Instance==QUADSPI)\r
+  {\r
+  /* USER CODE BEGIN QUADSPI_MspDeInit 0 */\r
+\r
+  /* USER CODE END QUADSPI_MspDeInit 0 */\r
+    /* Peripheral clock disable */\r
+    __HAL_RCC_QSPI_CLK_DISABLE();\r
+  \r
+    /**QUADSPI GPIO Configuration    \r
+    PE10     ------> QUADSPI_CLK\r
+    PE11     ------> QUADSPI_NCS\r
+    PE12     ------> QUADSPI_BK1_IO0\r
+    PE13     ------> QUADSPI_BK1_IO1\r
+    PE14     ------> QUADSPI_BK1_IO2\r
+    PE15     ------> QUADSPI_BK1_IO3 \r
+    */\r
+    HAL_GPIO_DeInit(GPIOE, QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin \r
+                          |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin);\r
+\r
+  /* USER CODE BEGIN QUADSPI_MspDeInit 1 */\r
+\r
+  /* USER CODE END QUADSPI_MspDeInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief SPI MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param hspi: SPI handle pointer\r
+* @retval None\r
+*/\r
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+  if(hspi->Instance==SPI3)\r
+  {\r
+  /* USER CODE BEGIN SPI3_MspInit 0 */\r
+\r
+  /* USER CODE END SPI3_MspInit 0 */\r
+    /* Peripheral clock enable */\r
+    __HAL_RCC_SPI3_CLK_ENABLE();\r
+  \r
+    __HAL_RCC_GPIOC_CLK_ENABLE();\r
+    /**SPI3 GPIO Configuration    \r
+    PC10     ------> SPI3_SCK\r
+    PC11     ------> SPI3_MISO\r
+    PC12     ------> SPI3_MOSI \r
+    */\r
+    GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;\r
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
+\r
+  /* USER CODE BEGIN SPI3_MspInit 1 */\r
+\r
+  /* USER CODE END SPI3_MspInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief SPI MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param hspi: SPI handle pointer\r
+* @retval None\r
+*/\r
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)\r
+{\r
+  if(hspi->Instance==SPI3)\r
+  {\r
+  /* USER CODE BEGIN SPI3_MspDeInit 0 */\r
+\r
+  /* USER CODE END SPI3_MspDeInit 0 */\r
+    /* Peripheral clock disable */\r
+    __HAL_RCC_SPI3_CLK_DISABLE();\r
+  \r
+    /**SPI3 GPIO Configuration    \r
+    PC10     ------> SPI3_SCK\r
+    PC11     ------> SPI3_MISO\r
+    PC12     ------> SPI3_MOSI \r
+    */\r
+    HAL_GPIO_DeInit(GPIOC, INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin);\r
+\r
+  /* USER CODE BEGIN SPI3_MspDeInit 1 */\r
+\r
+  /* USER CODE END SPI3_MspDeInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief UART MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param huart: UART handle pointer\r
+* @retval None\r
+*/\r
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+  if(huart->Instance==USART1)\r
+  {\r
+  /* USER CODE BEGIN USART1_MspInit 0 */\r
+\r
+  /* USER CODE END USART1_MspInit 0 */\r
+    /* Peripheral clock enable */\r
+    __HAL_RCC_USART1_CLK_ENABLE();\r
+  \r
+    __HAL_RCC_GPIOB_CLK_ENABLE();\r
+    /**USART1 GPIO Configuration    \r
+    PB6     ------> USART1_TX\r
+    PB7     ------> USART1_RX \r
+    */\r
+    GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;\r
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
+\r
+  /* USER CODE BEGIN USART1_MspInit 1 */\r
+\r
+  /* USER CODE END USART1_MspInit 1 */\r
+  }\r
+  else if(huart->Instance==USART3)\r
+  {\r
+  /* USER CODE BEGIN USART3_MspInit 0 */\r
+\r
+  /* USER CODE END USART3_MspInit 0 */\r
+    /* Peripheral clock enable */\r
+    __HAL_RCC_USART3_CLK_ENABLE();\r
+  \r
+    __HAL_RCC_GPIOD_CLK_ENABLE();\r
+    /**USART3 GPIO Configuration    \r
+    PD8     ------> USART3_TX\r
+    PD9     ------> USART3_RX \r
+    */\r
+    GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;\r
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
+\r
+  /* USER CODE BEGIN USART3_MspInit 1 */\r
+\r
+  /* USER CODE END USART3_MspInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief UART MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param huart: UART handle pointer\r
+* @retval None\r
+*/\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)\r
+{\r
+  if(huart->Instance==USART1)\r
+  {\r
+  /* USER CODE BEGIN USART1_MspDeInit 0 */\r
+\r
+  /* USER CODE END USART1_MspDeInit 0 */\r
+    /* Peripheral clock disable */\r
+    __HAL_RCC_USART1_CLK_DISABLE();\r
+  \r
+    /**USART1 GPIO Configuration    \r
+    PB6     ------> USART1_TX\r
+    PB7     ------> USART1_RX \r
+    */\r
+    HAL_GPIO_DeInit(GPIOB, ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin);\r
+\r
+  /* USER CODE BEGIN USART1_MspDeInit 1 */\r
+\r
+  /* USER CODE END USART1_MspDeInit 1 */\r
+  }\r
+  else if(huart->Instance==USART3)\r
+  {\r
+  /* USER CODE BEGIN USART3_MspDeInit 0 */\r
+\r
+  /* USER CODE END USART3_MspDeInit 0 */\r
+    /* Peripheral clock disable */\r
+    __HAL_RCC_USART3_CLK_DISABLE();\r
+  \r
+    /**USART3 GPIO Configuration    \r
+    PD8     ------> USART3_TX\r
+    PD9     ------> USART3_RX \r
+    */\r
+    HAL_GPIO_DeInit(GPIOD, INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin);\r
+\r
+  /* USER CODE BEGIN USART3_MspDeInit 1 */\r
+\r
+  /* USER CODE END USART3_MspDeInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief PCD MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param hpcd: PCD handle pointer\r
+* @retval None\r
+*/\r
+void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+  if(hpcd->Instance==USB_OTG_FS)\r
+  {\r
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */\r
+\r
+  /* USER CODE END USB_OTG_FS_MspInit 0 */\r
+  \r
+    __HAL_RCC_GPIOA_CLK_ENABLE();\r
+    /**USB_OTG_FS GPIO Configuration    \r
+    PA9     ------> USB_OTG_FS_VBUS\r
+    PA10     ------> USB_OTG_FS_ID\r
+    PA11     ------> USB_OTG_FS_DM\r
+    PA12     ------> USB_OTG_FS_DP \r
+    */\r
+    GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r
+    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+    HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);\r
+\r
+    GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;\r
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;\r
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
+\r
+    /* Peripheral clock enable */\r
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r
+\r
+    /* Enable VDDUSB */\r
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
+    {\r
+      __HAL_RCC_PWR_CLK_ENABLE();\r
+      HAL_PWREx_EnableVddUSB();\r
+      __HAL_RCC_PWR_CLK_DISABLE();\r
+    }\r
+    else\r
+    {\r
+      HAL_PWREx_EnableVddUSB();\r
+    }\r
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */\r
+\r
+  /* USER CODE END USB_OTG_FS_MspInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/**\r
+* @brief PCD MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param hpcd: PCD handle pointer\r
+* @retval None\r
+*/\r
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)\r
+{\r
+  if(hpcd->Instance==USB_OTG_FS)\r
+  {\r
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */\r
+\r
+  /* USER CODE END USB_OTG_FS_MspDeInit 0 */\r
+    /* Peripheral clock disable */\r
+    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();\r
+  \r
+    /**USB_OTG_FS GPIO Configuration    \r
+    PA9     ------> USB_OTG_FS_VBUS\r
+    PA10     ------> USB_OTG_FS_ID\r
+    PA11     ------> USB_OTG_FS_DM\r
+    PA12     ------> USB_OTG_FS_DP \r
+    */\r
+    HAL_GPIO_DeInit(GPIOA, USB_OTG_FS_VBUS_Pin|USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin);\r
+\r
+    /* Disable VDDUSB */\r
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
+    {\r
+      __HAL_RCC_PWR_CLK_ENABLE();\r
+      HAL_PWREx_DisableVddUSB();\r
+      __HAL_RCC_PWR_CLK_DISABLE();\r
+    }\r
+    else\r
+    {\r
+      HAL_PWREx_DisableVddUSB();\r
+    }\r
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */\r
+\r
+  /* USER CODE END USB_OTG_FS_MspDeInit 1 */\r
+  }\r
+\r
+}\r
+\r
+/* USER CODE BEGIN 1 */\r
+\r
+/* USER CODE END 1 */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c
new file mode 100644 (file)
index 0000000..47f531b
--- /dev/null
@@ -0,0 +1,114 @@
+/* USER CODE BEGIN Header */\r
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_timebase_TIM.c \r
+  * @brief   HAL time base based on the hardware TIM.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+#include "stm32l4xx_hal_tim.h"\r
\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+TIM_HandleTypeDef        htim6; \r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+  * @brief  This function configures the TIM6 as a time base source. \r
+  *         The time source is configured  to have 1ms time base with a dedicated \r
+  *         Tick interrupt priority. \r
+  * @note   This function is called  automatically at the beginning of program after\r
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). \r
+  * @param  TickPriority: Tick interrupt priority.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+  RCC_ClkInitTypeDef    clkconfig;\r
+  uint32_t              uwTimclock = 0;\r
+  uint32_t              uwPrescalerValue = 0;\r
+  uint32_t              pFLatency;\r
+  \r
+  /*Configure the TIM6 IRQ priority */\r
+  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0); \r
+  \r
+  /* Enable the TIM6 global Interrupt */\r
+  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); \r
+  \r
+  /* Enable TIM6 clock */\r
+  __HAL_RCC_TIM6_CLK_ENABLE();\r
+  \r
+  /* Get clock configuration */\r
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);\r
+  \r
+  /* Compute TIM6 clock */\r
+  uwTimclock = HAL_RCC_GetPCLK1Freq();\r
+   \r
+  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */\r
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);\r
+  \r
+  /* Initialize TIM6 */\r
+  htim6.Instance = TIM6;\r
+  \r
+  /* Initialize TIMx peripheral as follow:\r
+  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.\r
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.\r
+  + ClockDivision = 0\r
+  + Counter direction = Up\r
+  */\r
+  htim6.Init.Period = (1000000 / 1000) - 1;\r
+  htim6.Init.Prescaler = uwPrescalerValue;\r
+  htim6.Init.ClockDivision = 0;\r
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;\r
+  if(HAL_TIM_Base_Init(&htim6) == HAL_OK)\r
+  {\r
+    /* Start the TIM time Base generation in interrupt mode */\r
+    return HAL_TIM_Base_Start_IT(&htim6);\r
+  }\r
+  \r
+  /* Return function status */\r
+  return HAL_ERROR;\r
+}\r
+\r
+/**\r
+  * @brief  Suspend Tick increment.\r
+  * @note   Disable the tick increment by disabling TIM6 update interrupt.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void HAL_SuspendTick(void)\r
+{\r
+  /* Disable TIM6 update Interrupt */\r
+  __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);                                                  \r
+}\r
+\r
+/**\r
+  * @brief  Resume Tick increment.\r
+  * @note   Enable the tick increment by Enabling TIM6 update interrupt.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void HAL_ResumeTick(void)\r
+{\r
+  /* Enable TIM6 Update interrupt */\r
+  __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_it.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/stm32l4xx_it.c
new file mode 100644 (file)
index 0000000..f707420
--- /dev/null
@@ -0,0 +1,200 @@
+/* USER CODE BEGIN Header */\r
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_it.c\r
+  * @brief   Interrupt Service Routines.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+#include "stm32l4xx_it.h"\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN TD */\r
+\r
+/* USER CODE END TD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN PD */\r
\r
+/* USER CODE END PD */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN PM */\r
+\r
+/* USER CODE END PM */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* Private user code ---------------------------------------------------------*/\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+\r
+/* External variables --------------------------------------------------------*/\r
+extern TIM_HandleTypeDef htim6;\r
+\r
+/* USER CODE BEGIN EV */\r
+\r
+/* USER CODE END EV */\r
+\r
+/******************************************************************************/\r
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */ \r
+/******************************************************************************/\r
+/**\r
+  * @brief This function handles Non maskable interrupt.\r
+  */\r
+void NMI_Handler(void)\r
+{\r
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */\r
+\r
+  /* USER CODE END NonMaskableInt_IRQn 0 */\r
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */\r
+\r
+  /* USER CODE END NonMaskableInt_IRQn 1 */\r
+}\r
+\r
+/**\r
+  * @brief This function handles Hard fault interrupt.\r
+  */\r
+void HardFault_Handler(void)\r
+{\r
+  /* USER CODE BEGIN HardFault_IRQn 0 */\r
+\r
+  /* USER CODE END HardFault_IRQn 0 */\r
+  while (1)\r
+  {\r
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */\r
+    /* USER CODE END W1_HardFault_IRQn 0 */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief This function handles Prefetch fault, memory access fault.\r
+  */\r
+void BusFault_Handler(void)\r
+{\r
+  /* USER CODE BEGIN BusFault_IRQn 0 */\r
+\r
+  /* USER CODE END BusFault_IRQn 0 */\r
+  while (1)\r
+  {\r
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */\r
+    /* USER CODE END W1_BusFault_IRQn 0 */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief This function handles Undefined instruction or illegal state.\r
+  */\r
+void UsageFault_Handler(void)\r
+{\r
+  /* USER CODE BEGIN UsageFault_IRQn 0 */\r
+\r
+  /* USER CODE END UsageFault_IRQn 0 */\r
+  while (1)\r
+  {\r
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */\r
+    /* USER CODE END W1_UsageFault_IRQn 0 */\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief This function handles Debug monitor.\r
+  */\r
+void DebugMon_Handler(void)\r
+{\r
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */\r
+\r
+  /* USER CODE END DebugMonitor_IRQn 0 */\r
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */\r
+\r
+  /* USER CODE END DebugMonitor_IRQn 1 */\r
+}\r
+\r
+\r
+/******************************************************************************/\r
+/* STM32L4xx Peripheral Interrupt Handlers                                    */\r
+/* Add here the Interrupt Handlers for the used peripherals.                  */\r
+/* For the available peripheral interrupt handler names,                      */\r
+/* please refer to the startup file (startup_stm32l4xx.s).                    */\r
+/******************************************************************************/\r
+\r
+/**\r
+  * @brief This function handles EXTI line[9:5] interrupts.\r
+  */\r
+void EXTI9_5_IRQHandler(void)\r
+{\r
+  /* USER CODE BEGIN EXTI9_5_IRQn 0 */\r
+\r
+  /* USER CODE END EXTI9_5_IRQn 0 */\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);\r
+  /* USER CODE BEGIN EXTI9_5_IRQn 1 */\r
+\r
+  /* USER CODE END EXTI9_5_IRQn 1 */\r
+}\r
+\r
+/**\r
+  * @brief This function handles EXTI line[15:10] interrupts.\r
+  */\r
+void EXTI15_10_IRQHandler(void)\r
+{\r
+  /* USER CODE BEGIN EXTI15_10_IRQn 0 */\r
+\r
+  /* USER CODE END EXTI15_10_IRQn 0 */\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);\r
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);\r
+  /* USER CODE BEGIN EXTI15_10_IRQn 1 */\r
+\r
+  /* USER CODE END EXTI15_10_IRQn 1 */\r
+}\r
+\r
+/**\r
+  * @brief This function handles TIM6 global interrupt, DAC channel1 and channel2 underrun error interrupts.\r
+  */\r
+void TIM6_DAC_IRQHandler(void)\r
+{\r
+  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */\r
+\r
+  /* USER CODE END TIM6_DAC_IRQn 0 */\r
+  HAL_TIM_IRQHandler(&htim6);\r
+  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */\r
+\r
+  /* USER CODE END TIM6_DAC_IRQn 1 */\r
+}\r
+\r
+/* USER CODE BEGIN 1 */\r
+\r
+/* USER CODE END 1 */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/system_stm32l4xx.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Core/Src/system_stm32l4xx.c
new file mode 100644 (file)
index 0000000..1db59ec
--- /dev/null
@@ -0,0 +1,337 @@
+/**\r
+  ******************************************************************************\r
+  * @file    system_stm32l4xx.c\r
+  * @author  MCD Application Team\r
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File\r
+  *\r
+  *   This file provides two functions and one global variable to be called from\r
+  *   user application:\r
+  *      - SystemInit(): This function is called at startup just after reset and\r
+  *                      before branch to main program. This call is made inside\r
+  *                      the "startup_stm32l4xx.s" file.\r
+  *\r
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+  *                                  by the user application to setup the SysTick\r
+  *                                  timer or configure other parameters.\r
+  *\r
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+  *                                 be called whenever the core clock is changed\r
+  *                                 during program execution.\r
+  *\r
+  *   After each device reset the MSI (4 MHz) is used as system clock source.\r
+  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to\r
+  *   configure the system clock before to branch to main program.\r
+  *\r
+  *   This file configures the system clock as follows:\r
+  *=============================================================================\r
+  *-----------------------------------------------------------------------------\r
+  *        System Clock source                    | MSI\r
+  *-----------------------------------------------------------------------------\r
+  *        SYSCLK(Hz)                             | 4000000\r
+  *-----------------------------------------------------------------------------\r
+  *        HCLK(Hz)                               | 4000000\r
+  *-----------------------------------------------------------------------------\r
+  *        AHB Prescaler                          | 1\r
+  *-----------------------------------------------------------------------------\r
+  *        APB1 Prescaler                         | 1\r
+  *-----------------------------------------------------------------------------\r
+  *        APB2 Prescaler                         | 1\r
+  *-----------------------------------------------------------------------------\r
+  *        PLL_M                                  | 1\r
+  *-----------------------------------------------------------------------------\r
+  *        PLL_N                                  | 8\r
+  *-----------------------------------------------------------------------------\r
+  *        PLL_P                                  | 7\r
+  *-----------------------------------------------------------------------------\r
+  *        PLL_Q                                  | 2\r
+  *-----------------------------------------------------------------------------\r
+  *        PLL_R                                  | 2\r
+  *-----------------------------------------------------------------------------\r
+  *        PLLSAI1_P                              | NA\r
+  *-----------------------------------------------------------------------------\r
+  *        PLLSAI1_Q                              | NA\r
+  *-----------------------------------------------------------------------------\r
+  *        PLLSAI1_R                              | NA\r
+  *-----------------------------------------------------------------------------\r
+  *        PLLSAI2_P                              | NA\r
+  *-----------------------------------------------------------------------------\r
+  *        PLLSAI2_Q                              | NA\r
+  *-----------------------------------------------------------------------------\r
+  *        PLLSAI2_R                              | NA\r
+  *-----------------------------------------------------------------------------\r
+  *        Require 48MHz for USB OTG FS,          | Disabled\r
+  *        SDIO and RNG clock                     |\r
+  *-----------------------------------------------------------------------------\r
+  *=============================================================================\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l4xx_system\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Includes\r
+  * @{\r
+  */\r
+\r
+#include "stm32l4xx.h"\r
+\r
+#if !defined  (HSE_VALUE)\r
+  #define HSE_VALUE    8000000U  /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined  (MSI_VALUE)\r
+  #define MSI_VALUE    4000000U  /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* MSI_VALUE */\r
+\r
+#if !defined  (HSI_VALUE)\r
+  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+     Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.\r
+                                   This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Variables\r
+  * @{\r
+  */\r
+  /* The SystemCoreClock variable is updated in three ways:\r
+      1) by calling CMSIS function SystemCoreClockUpdate()\r
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
+         Note: If you use this function to configure the system clock; then there\r
+               is no need to call the 2 first functions listed above, since SystemCoreClock\r
+               variable is updated automatically.\r
+  */\r
+  uint32_t SystemCoreClock = 4000000U;\r
+\r
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};\r
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};\r
+  const uint32_t MSIRangeTable[12] = {100000U,   200000U,   400000U,   800000U,  1000000U,  2000000U, \\r
+                                      4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Setup the microcontroller system.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+\r
+void SystemInit(void)\r
+{\r
+  /* FPU settings ------------------------------------------------------------*/\r
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\r
+  #endif\r
+\r
+  /* Reset the RCC clock configuration to the default reset state ------------*/\r
+  /* Set MSION bit */\r
+  RCC->CR |= RCC_CR_MSION;\r
+\r
+  /* Reset CFGR register */\r
+  RCC->CFGR = 0x00000000U;\r
+\r
+  /* Reset HSEON, CSSON , HSION, and PLLON bits */\r
+  RCC->CR &= 0xEAF6FFFFU;\r
+\r
+  /* Reset PLLCFGR register */\r
+  RCC->PLLCFGR = 0x00001000U;\r
+\r
+  /* Reset HSEBYP bit */\r
+  RCC->CR &= 0xFFFBFFFFU;\r
+\r
+  /* Disable all interrupts */\r
+  RCC->CIER = 0x00000000U;\r
+\r
+  /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.\r
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can\r
+  *         be used by the user application to setup the SysTick timer or configure\r
+  *         other parameters.\r
+  *\r
+  * @note   Each time the core clock (HCLK) changes, this function must be called\r
+  *         to update SystemCoreClock variable value. Otherwise, any configuration\r
+  *         based on this variable will be incorrect.\r
+  *\r
+  * @note   - The system frequency computed by this function is not the real\r
+  *           frequency in the chip. It is calculated based on the predefined\r
+  *           constant and the selected clock source:\r
+  *\r
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)\r
+  *\r
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)\r
+  *\r
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)\r
+  *\r
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)\r
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.\r
+  *\r
+  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
+  *             4 MHz) but the real value may vary depending on the variations\r
+  *             in voltage and temperature.\r
+  *\r
+  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
+  *              16 MHz) but the real value may vary depending on the variations\r
+  *              in voltage and temperature.\r
+  *\r
+  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+  *              frequency of the crystal used. Otherwise, this function may\r
+  *              have wrong result.\r
+  *\r
+  *         - The result of this function could be not correct when using fractional\r
+  *           value for HSE crystal.\r
+  *\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+  uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;\r
+\r
+  /* Get MSI Range frequency--------------------------------------------------*/\r
+  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)\r
+  { /* MSISRANGE from RCC_CSR applies */\r
+    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;\r
+  }\r
+  else\r
+  { /* MSIRANGE from RCC_CR applies */\r
+    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;\r
+  }\r
+  /*MSI frequency range in HZ*/\r
+  msirange = MSIRangeTable[msirange];\r
+\r
+  /* Get SYSCLK source -------------------------------------------------------*/\r
+  switch (RCC->CFGR & RCC_CFGR_SWS)\r
+  {\r
+    case 0x00:  /* MSI used as system clock source */\r
+      SystemCoreClock = msirange;\r
+      break;\r
+\r
+    case 0x04:  /* HSI used as system clock source */\r
+      SystemCoreClock = HSI_VALUE;\r
+      break;\r
+\r
+    case 0x08:  /* HSE used as system clock source */\r
+      SystemCoreClock = HSE_VALUE;\r
+      break;\r
+\r
+    case 0x0C:  /* PLL used as system clock  source */\r
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN\r
+         SYSCLK = PLL_VCO / PLLR\r
+         */\r
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;\r
+\r
+      switch (pllsource)\r
+      {\r
+        case 0x02:  /* HSI used as PLL clock source */\r
+          pllvco = (HSI_VALUE / pllm);\r
+          break;\r
+\r
+        case 0x03:  /* HSE used as PLL clock source */\r
+          pllvco = (HSE_VALUE / pllm);\r
+          break;\r
+\r
+        default:    /* MSI used as PLL clock source */\r
+          pllvco = (msirange / pllm);\r
+          break;\r
+      }\r
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);\r
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;\r
+      SystemCoreClock = pllvco/pllr;\r
+      break;\r
+\r
+    default:\r
+      SystemCoreClock = msirange;\r
+      break;\r
+  }\r
+  /* Compute HCLK clock frequency --------------------------------------------*/\r
+  /* Get HCLK prescaler */\r
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];\r
+  /* HCLK clock frequency */\r
+  SystemCoreClock >>= tmp;\r
+}\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h
new file mode 100644 (file)
index 0000000..cc1a05a
--- /dev/null
@@ -0,0 +1,18327 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l475xx.h\r
+  * @author  MCD Application Team\r
+  * @brief   CMSIS STM32L475xx Device Peripheral Access Layer Header File.\r
+  *\r
+  *          This file contains:\r
+  *           - Data structures and the address mapping for all peripherals\r
+  *           - Peripheral's registers declarations and bits definition\r
+  *           - Macros to access peripheral\92s registers hardware\r
+  *\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS_Device\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l475xx\r
+  * @{\r
+  */\r
+\r
+#ifndef __STM32L475xx_H\r
+#define __STM32L475xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+   */\r
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */\r
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */\r
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\r
+#define __FPU_PRESENT             1       /*!< FPU present                                   */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Peripheral_interrupt_number_definition\r
+  * @{\r
+  */\r
+\r
+/**\r
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device\r
+ *        in @ref Library_configuration_section\r
+ */\r
+typedef enum\r
+{\r
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\r
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */\r
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */\r
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\r
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\r
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\r
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\r
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\r
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\r
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\r
+/******  STM32 specific Interrupt Numbers **********************************************************************/\r
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\r
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */\r
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\r
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\r
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\r
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\r
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\r
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\r
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\r
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\r
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\r
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */\r
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */\r
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */\r
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */\r
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */\r
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */\r
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */\r
+  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */\r
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\r
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\r
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\r
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\r
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\r
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */\r
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */\r
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */\r
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\r
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\r
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\r
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\r
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\r
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\r
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\r
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\r
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\r
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\r
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\r
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\r
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\r
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\r
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\r
+  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */\r
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */\r
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */\r
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */\r
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\r
+  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */\r
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\r
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\r
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\r
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\r
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\r
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\r
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\r
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\r
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */\r
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */\r
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */\r
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */\r
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */\r
+  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */\r
+  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */\r
+  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */\r
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */\r
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */\r
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */\r
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\r
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */\r
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */\r
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */\r
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */\r
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\r
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\r
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */\r
+  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */\r
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */\r
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */\r
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */\r
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */\r
+} IRQn_Type;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */\r
+#include "system_stm32l4xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Analog to Digital Converter\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */\r
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */\r
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */\r
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */\r
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */\r
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */\r
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */\r
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */\r
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */\r
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */\r
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */\r
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */\r
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */\r
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */\r
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */\r
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */\r
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */\r
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */\r
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */\r
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */\r
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */\r
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */\r
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */\r
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */\r
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */\r
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */\r
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */\r
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */\r
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */\r
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */\r
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */\r
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */\r
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */\r
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */\r
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */\r
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */\r
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */\r
+\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */\r
+  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */\r
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */\r
+  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Controller Area Network TxMailBox\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\r
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/**\r
+  * @brief Controller Area Network FIFOMailBox\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\r
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/**\r
+  * @brief Controller Area Network FilterRegister\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/**\r
+  * @brief Controller Area Network\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\r
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\r
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\r
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\r
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\r
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\r
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\r
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\r
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\r
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\r
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\r
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\r
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\r
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\r
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\r
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\r
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\r
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\r
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\r
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\r
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\r
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\r
+} CAN_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Comparator\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */\r
+} COMP_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\r
+} COMP_Common_TypeDef;\r
+\r
+/**\r
+  * @brief CRC calculation unit\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */\r
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\r
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */\r
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */\r
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */\r
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */\r
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\r
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\r
+} CRC_TypeDef;\r
+\r
+/**\r
+  * @brief Digital to Analog Converter\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */\r
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */\r
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\r
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\r
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\r
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\r
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\r
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\r
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\r
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */\r
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */\r
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */\r
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */\r
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */\r
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */\r
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */\r
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */\r
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */\r
+} DAC_TypeDef;\r
+\r
+/**\r
+  * @brief DFSDM module registers\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */\r
+  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */\r
+  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\r
+  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\r
+  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\r
+  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */\r
+  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */\r
+  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */\r
+  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\r
+  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\r
+  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\r
+  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\r
+  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\r
+  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\r
+  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */\r
+} DFSDM_Filter_TypeDef;\r
+\r
+/**\r
+  * @brief DFSDM channel configuration registers\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\r
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\r
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and\r
+                                  short circuit detector register,                  Address offset: 0x08 */\r
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\r
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */\r
+} DFSDM_Channel_TypeDef;\r
+\r
+/**\r
+  * @brief Debug MCU\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */\r
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */\r
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */\r
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */\r
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */\r
+} DBGMCU_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief DMA Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */\r
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */\r
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */\r
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */\r
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */\r
+} DMA_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */\r
+} DMA_Request_TypeDef;\r
+\r
+/* Legacy define */\r
+#define DMA_request_TypeDef  DMA_Request_TypeDef\r
+\r
+\r
+/**\r
+  * @brief External Interrupt/Event Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */\r
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */\r
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */\r
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */\r
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */\r
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */\r
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */\r
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */\r
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */\r
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */\r
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */\r
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */\r
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */\r
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */\r
+} EXTI_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Firewall\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */\r
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */\r
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */\r
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */\r
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */\r
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */\r
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */\r
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */\r
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */\r
+} FIREWALL_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief FLASH Registers\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */\r
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */\r
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */\r
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */\r
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */\r
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */\r
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */\r
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */\r
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */\r
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */\r
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */\r
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */\r
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */\r
+       uint32_t RESERVED2[4];     /*!< Reserved2,                           Address offset: 0x34-0x40 */\r
+  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */\r
+  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */\r
+  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */\r
+  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */\r
+} FLASH_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Flexible Memory Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r
+} FMC_Bank1_TypeDef;\r
+\r
+/**\r
+  * @brief Flexible Memory Controller Bank1E\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/**\r
+  * @brief Flexible Memory Controller Bank3\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */\r
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */\r
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */\r
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */\r
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+\r
+/**\r
+  * @brief General Purpose I/O\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */\r
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */\r
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */\r
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\r
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */\r
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */\r
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */\r
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */\r
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\r
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */\r
+  __IO uint32_t ASCR;        /*!< GPIO analog switch control register,   Address offset: 0x2C     */\r
+\r
+} GPIO_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Inter-integrated Circuit Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */\r
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */\r
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */\r
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */\r
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */\r
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */\r
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */\r
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */\r
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */\r
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */\r
+} I2C_TypeDef;\r
+\r
+/**\r
+  * @brief Independent WATCHDOG\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */\r
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */\r
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */\r
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+/**\r
+  * @brief LPTIMER\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\r
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\r
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\r
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */\r
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */\r
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */\r
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\r
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */\r
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */\r
+} LPTIM_TypeDef;\r
+\r
+/**\r
+  * @brief Operational Amplifier (OPAMP)\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */\r
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */\r
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */\r
+} OPAMP_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */\r
+} OPAMP_Common_TypeDef;\r
+\r
+/**\r
+  * @brief Power Control\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */\r
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */\r
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */\r
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */\r
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */\r
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */\r
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */\r
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */\r
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */\r
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */\r
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */\r
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */\r
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */\r
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */\r
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */\r
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */\r
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */\r
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */\r
+  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */\r
+  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */\r
+  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */\r
+  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */\r
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */\r
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */\r
+} PWR_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief QUAD Serial Peripheral Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */\r
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\r
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */\r
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\r
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\r
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\r
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */\r
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\r
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */\r
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\r
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\r
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\r
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\r
+} QUADSPI_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Reset and Clock Control\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */\r
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */\r
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */\r
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */\r
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */\r
+  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */\r
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */\r
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */\r
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */\r
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */\r
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */\r
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */\r
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */\r
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */\r
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */\r
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */\r
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */\r
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */\r
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */\r
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */\r
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */\r
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */\r
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */\r
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */\r
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */\r
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */\r
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */\r
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */\r
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */\r
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */\r
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */\r
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */\r
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */\r
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */\r
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */\r
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */\r
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */\r
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */\r
+} RCC_TypeDef;\r
+\r
+/**\r
+  * @brief Real-Time Clock\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */\r
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */\r
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */\r
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */\r
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */\r
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\r
+       uint32_t reserved;    /*!< Reserved  */\r
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */\r
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */\r
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */\r
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */\r
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */\r
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */\r
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */\r
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\r
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */\r
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */\r
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\r
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\r
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */\r
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */\r
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */\r
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */\r
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */\r
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */\r
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */\r
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */\r
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */\r
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */\r
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */\r
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */\r
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */\r
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */\r
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */\r
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */\r
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */\r
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */\r
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */\r
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */\r
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */\r
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */\r
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */\r
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */\r
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */\r
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */\r
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */\r
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */\r
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */\r
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */\r
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */\r
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */\r
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+/**\r
+  * @brief Serial Audio Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */\r
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */\r
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */\r
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\r
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */\r
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */\r
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Secure digital input/output Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */\r
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */\r
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */\r
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */\r
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */\r
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */\r
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */\r
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */\r
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */\r
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */\r
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */\r
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */\r
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */\r
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */\r
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */\r
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */\r
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */\r
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */\r
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */\r
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */\r
+} SDMMC_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Serial Peripheral Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */\r
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */\r
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */\r
+  __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */\r
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */\r
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */\r
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */\r
+} SPI_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Single Wire Protocol Master Interface SPWMI\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */\r
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */\r
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */\r
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */\r
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */\r
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */\r
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */\r
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */\r
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */\r
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */\r
+} SWPMI_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief System configuration controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\r
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */\r
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */\r
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */\r
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */\r
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */\r
+} SYSCFG_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief TIM\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */\r
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */\r
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */\r
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */\r
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */\r
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */\r
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */\r
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */\r
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */\r
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */\r
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */\r
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */\r
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */\r
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */\r
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */\r
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */\r
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */\r
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */\r
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */\r
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */\r
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */\r
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\r
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */\r
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */\r
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */\r
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */\r
+} TIM_TypeDef;\r
+\r
+\r
+/**\r
+  * @brief Touch Sensing Controller (TSC)\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */\r
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */\r
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */\r
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */\r
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */\r
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */\r
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */\r
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */\r
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */\r
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */\r
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */\r
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */\r
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */\r
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */\r
+} TSC_TypeDef;\r
+\r
+/**\r
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */\r
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */\r
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */\r
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */\r
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\r
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */\r
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */\r
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */\r
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */\r
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */\r
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\r
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */\r
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */\r
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */\r
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */\r
+} USART_TypeDef;\r
+\r
+/**\r
+  * @brief VREFBUF\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */\r
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */\r
+} VREFBUF_TypeDef;\r
+\r
+/**\r
+  * @brief Window WATCHDOG\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */\r
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */\r
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/**\r
+  * @brief RNG\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\r
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\r
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+  * @brief USB_OTG_Core_register\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/\r
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/\r
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/\r
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/\r
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/\r
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/\r
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/\r
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/\r
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/\r
+  __IO uint32_t GRXFSIZ;              /*!<  Receive FIFO Size Register                   024h*/\r
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/\r
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/\r
+  uint32_t Reserved30[2];             /*!<  Reserved                                     030h*/\r
+  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register                  038h*/\r
+  __IO uint32_t CID;                  /*!<  User ID Register                             03Ch*/\r
+  __IO uint32_t GSNPSID;              /*!<  USB_OTG core ID                              040h*/\r
+  __IO uint32_t GHWCFG1;              /*!<  User HW config1                              044h*/\r
+  __IO uint32_t GHWCFG2;              /*!<  User HW config2                              048h*/\r
+  __IO uint32_t GHWCFG3;              /*!<  User HW config3                              04Ch*/\r
+  uint32_t  Reserved6;                /*!<  Reserved                                     050h*/\r
+  __IO uint32_t GLPMCFG;              /*!<  LPM Register                                 054h*/\r
+  __IO uint32_t GPWRDN;               /*!<  Power Down Register                          058h*/\r
+  __IO uint32_t GDFIFOCFG;            /*!<  DFIFO Software Config Register               05Ch*/\r
+   __IO uint32_t GADPCTL;             /*!<  ADP Timer, Control and Status Register       060h*/\r
+    uint32_t  Reserved43[39];         /*!<  Reserved                                064h-0FFh*/\r
+  __IO uint32_t HPTXFSIZ;             /*!<  Host Periodic Tx FIFO Size Reg               100h*/\r
+  __IO uint32_t DIEPTXF[0x0F];        /*!<  dev Periodic Transmit FIFO */\r
+} USB_OTG_GlobalTypeDef;\r
+\r
+/**\r
+  * @brief USB_OTG_device_Registers\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/\r
+  __IO uint32_t DCTL;        /* dev Control Register         804h*/\r
+  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/\r
+  uint32_t Reserved0C;       /* Reserved                     80Ch*/\r
+  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/\r
+  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/\r
+  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/\r
+  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/\r
+  uint32_t Reserved20;       /* Reserved                     820h*/\r
+  uint32_t Reserved24;       /* Reserved                     824h*/\r
+  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/\r
+  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/\r
+  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/\r
+  __IO uint32_t DIEPEMPMSK;  /* dev empty msk                834h*/\r
+  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/\r
+  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/\r
+  uint32_t Reserved40;       /* Reserved                     840h*/\r
+  __IO uint32_t DINEP1MSK;   /* dedicated EP mask            844h*/\r
+  uint32_t  Reserved44[15];  /* Reserved                 848-880h*/\r
+  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk             884h*/\r
+} USB_OTG_DeviceTypeDef;\r
+\r
+/**\r
+  * @brief USB_OTG_IN_Endpoint-Specific_Register\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/\r
+  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/\r
+  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/\r
+  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/\r
+  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/\r
+  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/\r
+  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/\r
+  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/\r
+} USB_OTG_INEndpointTypeDef;\r
+\r
+/**\r
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/\r
+  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/\r
+  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/\r
+  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/\r
+  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/\r
+  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/\r
+  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/\r
+} USB_OTG_OUTEndpointTypeDef;\r
+\r
+/**\r
+  * @brief USB_OTG_Host_Mode_Register_Structures\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/\r
+  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/\r
+  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/\r
+  uint32_t Reserved40C;      /* Reserved                       40Ch*/\r
+  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/\r
+  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/\r
+  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/\r
+} USB_OTG_HostTypeDef;\r
+\r
+/**\r
+  * @brief USB_OTG_Host_Channel_Specific_Registers\r
+  */\r
+typedef struct\r
+{\r
+  __IO uint32_t HCCHAR;\r
+  __IO uint32_t HCSPLT;\r
+  __IO uint32_t HCINT;\r
+  __IO uint32_t HCINTMSK;\r
+  __IO uint32_t HCTSIZ;\r
+  __IO uint32_t HCDMA;\r
+  uint32_t Reserved[2];\r
+} USB_OTG_HostChannelTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Peripheral_memory_map\r
+  * @{\r
+  */\r
+#define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 1 MB) base address */\r
+#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */\r
+#define SRAM2_BASE            (0x10000000UL) /*!< SRAM2(32 KB) base address */\r
+#define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */\r
+#define FMC_BASE              (0x60000000UL) /*!< FMC base address */\r
+#define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */\r
+\r
+#define FMC_R_BASE            (0xA0000000UL) /*!< FMC  control registers base address */\r
+#define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */\r
+#define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */\r
+#define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */\r
+\r
+/* Legacy defines */\r
+#define SRAM_BASE             SRAM1_BASE\r
+#define SRAM_BB_BASE          SRAM1_BB_BASE\r
+\r
+#define SRAM1_SIZE_MAX        (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */\r
+#define SRAM2_SIZE            (0x00008000UL) /*!< SRAM2 size (32 KBytes) */\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE        PERIPH_BASE\r
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\r
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\r
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)\r
+\r
+#define FMC_BANK1             FMC_BASE\r
+#define FMC_BANK1_1           FMC_BANK1\r
+#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000UL)\r
+#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000UL)\r
+#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000UL)\r
+#define FMC_BANK3             (FMC_BASE  + 0x20000000UL)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\r
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\r
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\r
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\r
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\r
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\r
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\r
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\r
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\r
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\r
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\r
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\r
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\r
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)\r
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)\r
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\r
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\r
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\r
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\r
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\r
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)\r
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)\r
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)\r
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)\r
+#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810UL)\r
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)\r
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)\r
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800UL)\r
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)\r
+\r
+\r
+/*!< APB2 peripherals */\r
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)\r
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)\r
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)\r
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)\r
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)\r
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)\r
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800UL)\r
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)\r
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\r
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)\r
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)\r
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)\r
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)\r
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)\r
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)\r
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)\r
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)\r
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800UL)\r
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x0004UL)\r
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x0024UL)\r
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000UL)\r
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x0000UL)\r
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x0020UL)\r
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x0040UL)\r
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x0060UL)\r
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x0080UL)\r
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0x00A0UL)\r
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0x00C0UL)\r
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0x00E0UL)\r
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x0100UL)\r
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x0180UL)\r
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x0200UL)\r
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x0280UL)\r
+\r
+/*!< AHB1 peripherals */\r
+#define DMA1_BASE             (AHB1PERIPH_BASE)\r
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)\r
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)\r
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)\r
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\r
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)\r
+\r
+\r
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)\r
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)\r
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)\r
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)\r
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)\r
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)\r
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)\r
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)\r
+\r
+\r
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)\r
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)\r
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)\r
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)\r
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)\r
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)\r
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)\r
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)\r
+\r
+\r
+/*!< AHB2 peripherals */\r
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)\r
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)\r
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)\r
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)\r
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)\r
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)\r
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)\r
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)\r
+\r
+#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000UL)\r
+\r
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)\r
+#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100UL)\r
+#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200UL)\r
+#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300UL)\r
+\r
+\r
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)\r
+\r
+\r
+/*!< FMC Banks registers base  address */\r
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)\r
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)\r
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE           (0xE0042000UL)\r
+\r
+/*!< USB registers base address */\r
+#define USB_OTG_FS_PERIPH_BASE               (0x50000000UL)\r
+\r
+#define USB_OTG_GLOBAL_BASE                  (0x00000000UL)\r
+#define USB_OTG_DEVICE_BASE                  (0x00000800UL)\r
+#define USB_OTG_IN_ENDPOINT_BASE             (0x00000900UL)\r
+#define USB_OTG_OUT_ENDPOINT_BASE            (0x00000B00UL)\r
+#define USB_OTG_EP_REG_SIZE                  (0x00000020UL)\r
+#define USB_OTG_HOST_BASE                    (0x00000400UL)\r
+#define USB_OTG_HOST_PORT_BASE               (0x00000440UL)\r
+#define USB_OTG_HOST_CHANNEL_BASE            (0x00000500UL)\r
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x00000020UL)\r
+#define USB_OTG_PCGCCTL_BASE                 (0x00000E00UL)\r
+#define USB_OTG_FIFO_BASE                    (0x00001000UL)\r
+#define USB_OTG_FIFO_SIZE                    (0x00001000UL)\r
+\r
+\r
+#define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */\r
+#define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */\r
+#define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Peripheral_declaration\r
+  * @{\r
+  */\r
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\r
+#define USART2              ((USART_TypeDef *) USART2_BASE)\r
+#define USART3              ((USART_TypeDef *) USART3_BASE)\r
+#define UART4               ((USART_TypeDef *) UART4_BASE)\r
+#define UART5               ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\r
+#define CAN                 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\r
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)\r
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)\r
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)\r
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)\r
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)\r
+#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)\r
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\r
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)\r
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)\r
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)\r
+\r
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)\r
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)\r
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)\r
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)\r
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)\r
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)\r
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\r
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\r
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1              ((USART_TypeDef *) USART1_BASE)\r
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)\r
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\r
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\r
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)\r
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\r
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\r
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\r
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\r
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\r
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\r
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\r
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\r
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\r
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\r
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\r
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\r
+/* Aliases to keep compatibility after DFSDM renaming */\r
+#define DFSDM_Channel0      DFSDM1_Channel0\r
+#define DFSDM_Channel1      DFSDM1_Channel1\r
+#define DFSDM_Channel2      DFSDM1_Channel2\r
+#define DFSDM_Channel3      DFSDM1_Channel3\r
+#define DFSDM_Channel4      DFSDM1_Channel4\r
+#define DFSDM_Channel5      DFSDM1_Channel5\r
+#define DFSDM_Channel6      DFSDM1_Channel6\r
+#define DFSDM_Channel7      DFSDM1_Channel7\r
+#define DFSDM_Filter0       DFSDM1_Filter0\r
+#define DFSDM_Filter1       DFSDM1_Filter1\r
+#define DFSDM_Filter2       DFSDM1_Filter2\r
+#define DFSDM_Filter3       DFSDM1_Filter3\r
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\r
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)\r
+\r
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\r
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\r
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)\r
+\r
+\r
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)\r
+\r
+\r
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\r
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\r
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\r
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\r
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\r
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)\r
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)\r
+#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)\r
+\r
+\r
+#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+\r
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
+\r
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Exported_constants\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup Peripheral_Registers_Bits_Definition\r
+  * @{\r
+  */\r
+\r
+/******************************************************************************/\r
+/*                         Peripheral Registers_Bits_Definition               */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Analog to Digital Converter                         */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)\r
+ */\r
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\r
+\r
+/********************  Bit definition for ADC_ISR register  *******************/\r
+#define ADC_ISR_ADRDY_Pos              (0U)\r
+#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */\r
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */\r
+#define ADC_ISR_EOSMP_Pos              (1U)\r
+#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */\r
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */\r
+#define ADC_ISR_EOC_Pos                (2U)\r
+#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */\r
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */\r
+#define ADC_ISR_EOS_Pos                (3U)\r
+#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */\r
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */\r
+#define ADC_ISR_OVR_Pos                (4U)\r
+#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */\r
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */\r
+#define ADC_ISR_JEOC_Pos               (5U)\r
+#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */\r
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */\r
+#define ADC_ISR_JEOS_Pos               (6U)\r
+#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */\r
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */\r
+#define ADC_ISR_AWD1_Pos               (7U)\r
+#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */\r
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */\r
+#define ADC_ISR_AWD2_Pos               (8U)\r
+#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */\r
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */\r
+#define ADC_ISR_AWD3_Pos               (9U)\r
+#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */\r
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */\r
+#define ADC_ISR_JQOVF_Pos              (10U)\r
+#define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */\r
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */\r
+\r
+/********************  Bit definition for ADC_IER register  *******************/\r
+#define ADC_IER_ADRDYIE_Pos            (0U)\r
+#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */\r
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */\r
+#define ADC_IER_EOSMPIE_Pos            (1U)\r
+#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */\r
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */\r
+#define ADC_IER_EOCIE_Pos              (2U)\r
+#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */\r
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */\r
+#define ADC_IER_EOSIE_Pos              (3U)\r
+#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */\r
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */\r
+#define ADC_IER_OVRIE_Pos              (4U)\r
+#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */\r
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */\r
+#define ADC_IER_JEOCIE_Pos             (5U)\r
+#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */\r
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */\r
+#define ADC_IER_JEOSIE_Pos             (6U)\r
+#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */\r
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */\r
+#define ADC_IER_AWD1IE_Pos             (7U)\r
+#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */\r
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */\r
+#define ADC_IER_AWD2IE_Pos             (8U)\r
+#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */\r
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */\r
+#define ADC_IER_AWD3IE_Pos             (9U)\r
+#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */\r
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */\r
+#define ADC_IER_JQOVFIE_Pos            (10U)\r
+#define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */\r
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */\r
+\r
+/* Legacy defines */\r
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)\r
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)\r
+#define ADC_IER_EOC             (ADC_IER_EOCIE)\r
+#define ADC_IER_EOS             (ADC_IER_EOSIE)\r
+#define ADC_IER_OVR             (ADC_IER_OVRIE)\r
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)\r
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)\r
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)\r
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)\r
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)\r
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)\r
+\r
+/********************  Bit definition for ADC_CR register  ********************/\r
+#define ADC_CR_ADEN_Pos                (0U)\r
+#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */\r
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */\r
+#define ADC_CR_ADDIS_Pos               (1U)\r
+#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */\r
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */\r
+#define ADC_CR_ADSTART_Pos             (2U)\r
+#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */\r
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */\r
+#define ADC_CR_JADSTART_Pos            (3U)\r
+#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */\r
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */\r
+#define ADC_CR_ADSTP_Pos               (4U)\r
+#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */\r
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */\r
+#define ADC_CR_JADSTP_Pos              (5U)\r
+#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */\r
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */\r
+#define ADC_CR_ADVREGEN_Pos            (28U)\r
+#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */\r
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */\r
+#define ADC_CR_DEEPPWD_Pos             (29U)\r
+#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */\r
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */\r
+#define ADC_CR_ADCALDIF_Pos            (30U)\r
+#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */\r
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */\r
+#define ADC_CR_ADCAL_Pos               (31U)\r
+#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */\r
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */\r
+\r
+/********************  Bit definition for ADC_CFGR register  ******************/\r
+#define ADC_CFGR_DMAEN_Pos             (0U)\r
+#define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */\r
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */\r
+#define ADC_CFGR_DMACFG_Pos            (1U)\r
+#define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */\r
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */\r
+\r
+#define ADC_CFGR_RES_Pos               (3U)\r
+#define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */\r
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */\r
+#define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */\r
+#define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */\r
+\r
+#define ADC_CFGR_ALIGN_Pos             (5U)\r
+#define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00000020 */\r
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */\r
+\r
+#define ADC_CFGR_EXTSEL_Pos            (6U)\r
+#define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x000003C0 */\r
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */\r
+#define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */\r
+#define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */\r
+#define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */\r
+#define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000200 */\r
+\r
+#define ADC_CFGR_EXTEN_Pos             (10U)\r
+#define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */\r
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */\r
+#define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */\r
+#define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */\r
+\r
+#define ADC_CFGR_OVRMOD_Pos            (12U)\r
+#define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */\r
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */\r
+#define ADC_CFGR_CONT_Pos              (13U)\r
+#define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */\r
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */\r
+#define ADC_CFGR_AUTDLY_Pos            (14U)\r
+#define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */\r
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */\r
+\r
+#define ADC_CFGR_DISCEN_Pos            (16U)\r
+#define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */\r
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */\r
+\r
+#define ADC_CFGR_DISCNUM_Pos           (17U)\r
+#define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */\r
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */\r
+#define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */\r
+#define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */\r
+#define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */\r
+\r
+#define ADC_CFGR_JDISCEN_Pos           (20U)\r
+#define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */\r
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */\r
+#define ADC_CFGR_JQM_Pos               (21U)\r
+#define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */\r
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */\r
+#define ADC_CFGR_AWD1SGL_Pos           (22U)\r
+#define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */\r
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\r
+#define ADC_CFGR_AWD1EN_Pos            (23U)\r
+#define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */\r
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */\r
+#define ADC_CFGR_JAWD1EN_Pos           (24U)\r
+#define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */\r
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */\r
+#define ADC_CFGR_JAUTO_Pos             (25U)\r
+#define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */\r
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */\r
+\r
+#define ADC_CFGR_AWD1CH_Pos            (26U)\r
+#define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */\r
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */\r
+#define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */\r
+#define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */\r
+#define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */\r
+#define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */\r
+#define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */\r
+\r
+#define ADC_CFGR_JQDIS_Pos             (31U)\r
+#define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */\r
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */\r
+\r
+/********************  Bit definition for ADC_CFGR2 register  *****************/\r
+#define ADC_CFGR2_ROVSE_Pos            (0U)\r
+#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */\r
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */\r
+#define ADC_CFGR2_JOVSE_Pos            (1U)\r
+#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */\r
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */\r
+\r
+#define ADC_CFGR2_OVSR_Pos             (2U)\r
+#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */\r
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */\r
+#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */\r
+#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */\r
+#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */\r
+\r
+#define ADC_CFGR2_OVSS_Pos             (5U)\r
+#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */\r
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */\r
+#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */\r
+#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */\r
+#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */\r
+#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */\r
+\r
+#define ADC_CFGR2_TROVS_Pos            (9U)\r
+#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */\r
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */\r
+#define ADC_CFGR2_ROVSM_Pos            (10U)\r
+#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */\r
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */\r
+\r
+/********************  Bit definition for ADC_SMPR1 register  *****************/\r
+#define ADC_SMPR1_SMP0_Pos             (0U)\r
+#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */\r
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */\r
+#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */\r
+#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */\r
+#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */\r
+\r
+#define ADC_SMPR1_SMP1_Pos             (3U)\r
+#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */\r
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */\r
+#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */\r
+#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */\r
+#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */\r
+\r
+#define ADC_SMPR1_SMP2_Pos             (6U)\r
+#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */\r
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */\r
+#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */\r
+#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */\r
+#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */\r
+\r
+#define ADC_SMPR1_SMP3_Pos             (9U)\r
+#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */\r
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */\r
+#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */\r
+#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */\r
+#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */\r
+\r
+#define ADC_SMPR1_SMP4_Pos             (12U)\r
+#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */\r
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */\r
+#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */\r
+#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */\r
+#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */\r
+\r
+#define ADC_SMPR1_SMP5_Pos             (15U)\r
+#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */\r
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */\r
+#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */\r
+#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */\r
+#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */\r
+\r
+#define ADC_SMPR1_SMP6_Pos             (18U)\r
+#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */\r
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */\r
+#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */\r
+#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */\r
+#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */\r
+\r
+#define ADC_SMPR1_SMP7_Pos             (21U)\r
+#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */\r
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */\r
+#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */\r
+#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */\r
+#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */\r
+\r
+#define ADC_SMPR1_SMP8_Pos             (24U)\r
+#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */\r
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */\r
+#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */\r
+#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */\r
+#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */\r
+\r
+#define ADC_SMPR1_SMP9_Pos             (27U)\r
+#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */\r
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */\r
+#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */\r
+#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */\r
+#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */\r
+\r
+/********************  Bit definition for ADC_SMPR2 register  *****************/\r
+#define ADC_SMPR2_SMP10_Pos            (0U)\r
+#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */\r
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */\r
+#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */\r
+#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */\r
+#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */\r
+\r
+#define ADC_SMPR2_SMP11_Pos            (3U)\r
+#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */\r
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */\r
+#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */\r
+#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */\r
+#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */\r
+\r
+#define ADC_SMPR2_SMP12_Pos            (6U)\r
+#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */\r
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */\r
+#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */\r
+#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */\r
+#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */\r
+\r
+#define ADC_SMPR2_SMP13_Pos            (9U)\r
+#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */\r
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */\r
+#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */\r
+#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */\r
+#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */\r
+\r
+#define ADC_SMPR2_SMP14_Pos            (12U)\r
+#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */\r
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */\r
+#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */\r
+#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */\r
+#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */\r
+\r
+#define ADC_SMPR2_SMP15_Pos            (15U)\r
+#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */\r
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */\r
+#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */\r
+#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */\r
+#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */\r
+\r
+#define ADC_SMPR2_SMP16_Pos            (18U)\r
+#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */\r
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */\r
+#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */\r
+#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */\r
+#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */\r
+\r
+#define ADC_SMPR2_SMP17_Pos            (21U)\r
+#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */\r
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */\r
+#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */\r
+#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */\r
+#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */\r
+\r
+#define ADC_SMPR2_SMP18_Pos            (24U)\r
+#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */\r
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */\r
+#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */\r
+#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */\r
+#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */\r
+\r
+/********************  Bit definition for ADC_TR1 register  *******************/\r
+#define ADC_TR1_LT1_Pos                (0U)\r
+#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */\r
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */\r
+#define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */\r
+#define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */\r
+#define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */\r
+#define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */\r
+#define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */\r
+#define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */\r
+#define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */\r
+#define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */\r
+#define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */\r
+#define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */\r
+#define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */\r
+#define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */\r
+\r
+#define ADC_TR1_HT1_Pos                (16U)\r
+#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */\r
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */\r
+#define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */\r
+#define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */\r
+#define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */\r
+#define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */\r
+#define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */\r
+#define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */\r
+#define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */\r
+#define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */\r
+#define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */\r
+#define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */\r
+#define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */\r
+#define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */\r
+\r
+/********************  Bit definition for ADC_TR2 register  *******************/\r
+#define ADC_TR2_LT2_Pos                (0U)\r
+#define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */\r
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */\r
+#define ADC_TR2_LT2_0                  (0x01UL << ADC_TR2_LT2_Pos)             /*!< 0x00000001 */\r
+#define ADC_TR2_LT2_1                  (0x02UL << ADC_TR2_LT2_Pos)             /*!< 0x00000002 */\r
+#define ADC_TR2_LT2_2                  (0x04UL << ADC_TR2_LT2_Pos)             /*!< 0x00000004 */\r
+#define ADC_TR2_LT2_3                  (0x08UL << ADC_TR2_LT2_Pos)             /*!< 0x00000008 */\r
+#define ADC_TR2_LT2_4                  (0x10UL << ADC_TR2_LT2_Pos)             /*!< 0x00000010 */\r
+#define ADC_TR2_LT2_5                  (0x20UL << ADC_TR2_LT2_Pos)             /*!< 0x00000020 */\r
+#define ADC_TR2_LT2_6                  (0x40UL << ADC_TR2_LT2_Pos)             /*!< 0x00000040 */\r
+#define ADC_TR2_LT2_7                  (0x80UL << ADC_TR2_LT2_Pos)             /*!< 0x00000080 */\r
+\r
+#define ADC_TR2_HT2_Pos                (16U)\r
+#define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */\r
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */\r
+#define ADC_TR2_HT2_0                  (0x01UL << ADC_TR2_HT2_Pos)             /*!< 0x00010000 */\r
+#define ADC_TR2_HT2_1                  (0x02UL << ADC_TR2_HT2_Pos)             /*!< 0x00020000 */\r
+#define ADC_TR2_HT2_2                  (0x04UL << ADC_TR2_HT2_Pos)             /*!< 0x00040000 */\r
+#define ADC_TR2_HT2_3                  (0x08UL << ADC_TR2_HT2_Pos)             /*!< 0x00080000 */\r
+#define ADC_TR2_HT2_4                  (0x10UL << ADC_TR2_HT2_Pos)             /*!< 0x00100000 */\r
+#define ADC_TR2_HT2_5                  (0x20UL << ADC_TR2_HT2_Pos)             /*!< 0x00200000 */\r
+#define ADC_TR2_HT2_6                  (0x40UL << ADC_TR2_HT2_Pos)             /*!< 0x00400000 */\r
+#define ADC_TR2_HT2_7                  (0x80UL << ADC_TR2_HT2_Pos)             /*!< 0x00800000 */\r
+\r
+/********************  Bit definition for ADC_TR3 register  *******************/\r
+#define ADC_TR3_LT3_Pos                (0U)\r
+#define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */\r
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */\r
+#define ADC_TR3_LT3_0                  (0x01UL << ADC_TR3_LT3_Pos)             /*!< 0x00000001 */\r
+#define ADC_TR3_LT3_1                  (0x02UL << ADC_TR3_LT3_Pos)             /*!< 0x00000002 */\r
+#define ADC_TR3_LT3_2                  (0x04UL << ADC_TR3_LT3_Pos)             /*!< 0x00000004 */\r
+#define ADC_TR3_LT3_3                  (0x08UL << ADC_TR3_LT3_Pos)             /*!< 0x00000008 */\r
+#define ADC_TR3_LT3_4                  (0x10UL << ADC_TR3_LT3_Pos)             /*!< 0x00000010 */\r
+#define ADC_TR3_LT3_5                  (0x20UL << ADC_TR3_LT3_Pos)             /*!< 0x00000020 */\r
+#define ADC_TR3_LT3_6                  (0x40UL << ADC_TR3_LT3_Pos)             /*!< 0x00000040 */\r
+#define ADC_TR3_LT3_7                  (0x80UL << ADC_TR3_LT3_Pos)             /*!< 0x00000080 */\r
+\r
+#define ADC_TR3_HT3_Pos                (16U)\r
+#define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */\r
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */\r
+#define ADC_TR3_HT3_0                  (0x01UL << ADC_TR3_HT3_Pos)             /*!< 0x00010000 */\r
+#define ADC_TR3_HT3_1                  (0x02UL << ADC_TR3_HT3_Pos)             /*!< 0x00020000 */\r
+#define ADC_TR3_HT3_2                  (0x04UL << ADC_TR3_HT3_Pos)             /*!< 0x00040000 */\r
+#define ADC_TR3_HT3_3                  (0x08UL << ADC_TR3_HT3_Pos)             /*!< 0x00080000 */\r
+#define ADC_TR3_HT3_4                  (0x10UL << ADC_TR3_HT3_Pos)             /*!< 0x00100000 */\r
+#define ADC_TR3_HT3_5                  (0x20UL << ADC_TR3_HT3_Pos)             /*!< 0x00200000 */\r
+#define ADC_TR3_HT3_6                  (0x40UL << ADC_TR3_HT3_Pos)             /*!< 0x00400000 */\r
+#define ADC_TR3_HT3_7                  (0x80UL << ADC_TR3_HT3_Pos)             /*!< 0x00800000 */\r
+\r
+/********************  Bit definition for ADC_SQR1 register  ******************/\r
+#define ADC_SQR1_L_Pos                 (0U)\r
+#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */\r
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */\r
+#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */\r
+#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */\r
+#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */\r
+#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */\r
+\r
+#define ADC_SQR1_SQ1_Pos               (6U)\r
+#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */\r
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */\r
+#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */\r
+#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */\r
+#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */\r
+#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */\r
+#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */\r
+\r
+#define ADC_SQR1_SQ2_Pos               (12U)\r
+#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */\r
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */\r
+#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */\r
+#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */\r
+#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */\r
+#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */\r
+#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */\r
+\r
+#define ADC_SQR1_SQ3_Pos               (18U)\r
+#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */\r
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */\r
+#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */\r
+#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */\r
+#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */\r
+#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */\r
+#define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */\r
+\r
+#define ADC_SQR1_SQ4_Pos               (24U)\r
+#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */\r
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */\r
+#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */\r
+#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */\r
+#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */\r
+#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */\r
+#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */\r
+\r
+/********************  Bit definition for ADC_SQR2 register  ******************/\r
+#define ADC_SQR2_SQ5_Pos               (0U)\r
+#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */\r
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */\r
+#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */\r
+#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */\r
+#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */\r
+#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */\r
+#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */\r
+\r
+#define ADC_SQR2_SQ6_Pos               (6U)\r
+#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */\r
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */\r
+#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */\r
+#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */\r
+#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */\r
+#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */\r
+#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */\r
+\r
+#define ADC_SQR2_SQ7_Pos               (12U)\r
+#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */\r
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */\r
+#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */\r
+#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */\r
+#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */\r
+#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */\r
+#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */\r
+\r
+#define ADC_SQR2_SQ8_Pos               (18U)\r
+#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */\r
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */\r
+#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */\r
+#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */\r
+#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */\r
+#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */\r
+#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */\r
+\r
+#define ADC_SQR2_SQ9_Pos               (24U)\r
+#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */\r
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */\r
+#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */\r
+#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */\r
+#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */\r
+#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */\r
+#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */\r
+\r
+/********************  Bit definition for ADC_SQR3 register  ******************/\r
+#define ADC_SQR3_SQ10_Pos              (0U)\r
+#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */\r
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */\r
+#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */\r
+#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */\r
+#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */\r
+#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */\r
+#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */\r
+\r
+#define ADC_SQR3_SQ11_Pos              (6U)\r
+#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */\r
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */\r
+#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */\r
+#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */\r
+#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */\r
+#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */\r
+#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */\r
+\r
+#define ADC_SQR3_SQ12_Pos              (12U)\r
+#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */\r
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */\r
+#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */\r
+#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */\r
+#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */\r
+#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */\r
+#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */\r
+\r
+#define ADC_SQR3_SQ13_Pos              (18U)\r
+#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */\r
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */\r
+#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */\r
+#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */\r
+#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */\r
+#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */\r
+#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */\r
+\r
+#define ADC_SQR3_SQ14_Pos              (24U)\r
+#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */\r
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */\r
+#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */\r
+#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */\r
+#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */\r
+#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */\r
+#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */\r
+\r
+/********************  Bit definition for ADC_SQR4 register  ******************/\r
+#define ADC_SQR4_SQ15_Pos              (0U)\r
+#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */\r
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */\r
+#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */\r
+#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */\r
+#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */\r
+#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */\r
+#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */\r
+\r
+#define ADC_SQR4_SQ16_Pos              (6U)\r
+#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */\r
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */\r
+#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */\r
+#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */\r
+#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */\r
+#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */\r
+#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */\r
+\r
+/********************  Bit definition for ADC_DR register  ********************/\r
+#define ADC_DR_RDATA_Pos               (0U)\r
+#define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */\r
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */\r
+#define ADC_DR_RDATA_0                 (0x0001UL << ADC_DR_RDATA_Pos)          /*!< 0x00000001 */\r
+#define ADC_DR_RDATA_1                 (0x0002UL << ADC_DR_RDATA_Pos)          /*!< 0x00000002 */\r
+#define ADC_DR_RDATA_2                 (0x0004UL << ADC_DR_RDATA_Pos)          /*!< 0x00000004 */\r
+#define ADC_DR_RDATA_3                 (0x0008UL << ADC_DR_RDATA_Pos)          /*!< 0x00000008 */\r
+#define ADC_DR_RDATA_4                 (0x0010UL << ADC_DR_RDATA_Pos)          /*!< 0x00000010 */\r
+#define ADC_DR_RDATA_5                 (0x0020UL << ADC_DR_RDATA_Pos)          /*!< 0x00000020 */\r
+#define ADC_DR_RDATA_6                 (0x0040UL << ADC_DR_RDATA_Pos)          /*!< 0x00000040 */\r
+#define ADC_DR_RDATA_7                 (0x0080UL << ADC_DR_RDATA_Pos)          /*!< 0x00000080 */\r
+#define ADC_DR_RDATA_8                 (0x0100UL << ADC_DR_RDATA_Pos)          /*!< 0x00000100 */\r
+#define ADC_DR_RDATA_9                 (0x0200UL << ADC_DR_RDATA_Pos)          /*!< 0x00000200 */\r
+#define ADC_DR_RDATA_10                (0x0400UL << ADC_DR_RDATA_Pos)          /*!< 0x00000400 */\r
+#define ADC_DR_RDATA_11                (0x0800UL << ADC_DR_RDATA_Pos)          /*!< 0x00000800 */\r
+#define ADC_DR_RDATA_12                (0x1000UL << ADC_DR_RDATA_Pos)          /*!< 0x00001000 */\r
+#define ADC_DR_RDATA_13                (0x2000UL << ADC_DR_RDATA_Pos)          /*!< 0x00002000 */\r
+#define ADC_DR_RDATA_14                (0x4000UL << ADC_DR_RDATA_Pos)          /*!< 0x00004000 */\r
+#define ADC_DR_RDATA_15                (0x8000UL << ADC_DR_RDATA_Pos)          /*!< 0x00008000 */\r
+\r
+/********************  Bit definition for ADC_JSQR register  ******************/\r
+#define ADC_JSQR_JL_Pos                (0U)\r
+#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */\r
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */\r
+#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */\r
+#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */\r
+\r
+#define ADC_JSQR_JEXTSEL_Pos           (2U)\r
+#define ADC_JSQR_JEXTSEL_Msk           (0xFUL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x0000003C */\r
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */\r
+#define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */\r
+#define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */\r
+#define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */\r
+#define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */\r
+\r
+#define ADC_JSQR_JEXTEN_Pos            (6U)\r
+#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x000000C0 */\r
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */\r
+#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000040 */\r
+#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */\r
+\r
+#define ADC_JSQR_JSQ1_Pos              (8U)\r
+#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001F00 */\r
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */\r
+#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000100 */\r
+#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */\r
+#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */\r
+#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */\r
+#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */\r
+\r
+#define ADC_JSQR_JSQ2_Pos              (14U)\r
+#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */\r
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */\r
+#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */\r
+#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */\r
+#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */\r
+#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */\r
+#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */\r
+\r
+#define ADC_JSQR_JSQ3_Pos              (20U)\r
+#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01F00000 */\r
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */\r
+#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00100000 */\r
+#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */\r
+#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */\r
+#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */\r
+#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */\r
+\r
+#define ADC_JSQR_JSQ4_Pos              (26U)\r
+#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0x7C000000 */\r
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */\r
+#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x04000000 */\r
+#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */\r
+#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */\r
+#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */\r
+#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */\r
+\r
+/********************  Bit definition for ADC_OFR1 register  ******************/\r
+#define ADC_OFR1_OFFSET1_Pos           (0U)\r
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */\r
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */\r
+#define ADC_OFR1_OFFSET1_0             (0x001UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000001 */\r
+#define ADC_OFR1_OFFSET1_1             (0x002UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000002 */\r
+#define ADC_OFR1_OFFSET1_2             (0x004UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000004 */\r
+#define ADC_OFR1_OFFSET1_3             (0x008UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000008 */\r
+#define ADC_OFR1_OFFSET1_4             (0x010UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000010 */\r
+#define ADC_OFR1_OFFSET1_5             (0x020UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000020 */\r
+#define ADC_OFR1_OFFSET1_6             (0x040UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000040 */\r
+#define ADC_OFR1_OFFSET1_7             (0x080UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000080 */\r
+#define ADC_OFR1_OFFSET1_8             (0x100UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000100 */\r
+#define ADC_OFR1_OFFSET1_9             (0x200UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000200 */\r
+#define ADC_OFR1_OFFSET1_10            (0x400UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000400 */\r
+#define ADC_OFR1_OFFSET1_11            (0x800UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000800 */\r
+\r
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)\r
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */\r
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */\r
+#define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */\r
+#define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */\r
+#define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */\r
+#define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */\r
+#define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */\r
+\r
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)\r
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */\r
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */\r
+\r
+/********************  Bit definition for ADC_OFR2 register  ******************/\r
+#define ADC_OFR2_OFFSET2_Pos           (0U)\r
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */\r
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */\r
+#define ADC_OFR2_OFFSET2_0             (0x001UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000001 */\r
+#define ADC_OFR2_OFFSET2_1             (0x002UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000002 */\r
+#define ADC_OFR2_OFFSET2_2             (0x004UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000004 */\r
+#define ADC_OFR2_OFFSET2_3             (0x008UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000008 */\r
+#define ADC_OFR2_OFFSET2_4             (0x010UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000010 */\r
+#define ADC_OFR2_OFFSET2_5             (0x020UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000020 */\r
+#define ADC_OFR2_OFFSET2_6             (0x040UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000040 */\r
+#define ADC_OFR2_OFFSET2_7             (0x080UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000080 */\r
+#define ADC_OFR2_OFFSET2_8             (0x100UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000100 */\r
+#define ADC_OFR2_OFFSET2_9             (0x200UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000200 */\r
+#define ADC_OFR2_OFFSET2_10            (0x400UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000400 */\r
+#define ADC_OFR2_OFFSET2_11            (0x800UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000800 */\r
+\r
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)\r
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */\r
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */\r
+#define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */\r
+#define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */\r
+#define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */\r
+#define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */\r
+#define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */\r
+\r
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)\r
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */\r
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */\r
+\r
+/********************  Bit definition for ADC_OFR3 register  ******************/\r
+#define ADC_OFR3_OFFSET3_Pos           (0U)\r
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */\r
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */\r
+#define ADC_OFR3_OFFSET3_0             (0x001UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000001 */\r
+#define ADC_OFR3_OFFSET3_1             (0x002UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000002 */\r
+#define ADC_OFR3_OFFSET3_2             (0x004UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000004 */\r
+#define ADC_OFR3_OFFSET3_3             (0x008UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000008 */\r
+#define ADC_OFR3_OFFSET3_4             (0x010UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000010 */\r
+#define ADC_OFR3_OFFSET3_5             (0x020UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000020 */\r
+#define ADC_OFR3_OFFSET3_6             (0x040UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000040 */\r
+#define ADC_OFR3_OFFSET3_7             (0x080UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000080 */\r
+#define ADC_OFR3_OFFSET3_8             (0x100UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000100 */\r
+#define ADC_OFR3_OFFSET3_9             (0x200UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000200 */\r
+#define ADC_OFR3_OFFSET3_10            (0x400UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000400 */\r
+#define ADC_OFR3_OFFSET3_11            (0x800UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000800 */\r
+\r
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)\r
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */\r
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */\r
+#define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */\r
+#define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */\r
+#define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */\r
+#define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */\r
+#define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */\r
+\r
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)\r
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */\r
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */\r
+\r
+/********************  Bit definition for ADC_OFR4 register  ******************/\r
+#define ADC_OFR4_OFFSET4_Pos           (0U)\r
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */\r
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */\r
+#define ADC_OFR4_OFFSET4_0             (0x001UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000001 */\r
+#define ADC_OFR4_OFFSET4_1             (0x002UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000002 */\r
+#define ADC_OFR4_OFFSET4_2             (0x004UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000004 */\r
+#define ADC_OFR4_OFFSET4_3             (0x008UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000008 */\r
+#define ADC_OFR4_OFFSET4_4             (0x010UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000010 */\r
+#define ADC_OFR4_OFFSET4_5             (0x020UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000020 */\r
+#define ADC_OFR4_OFFSET4_6             (0x040UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000040 */\r
+#define ADC_OFR4_OFFSET4_7             (0x080UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000080 */\r
+#define ADC_OFR4_OFFSET4_8             (0x100UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000100 */\r
+#define ADC_OFR4_OFFSET4_9             (0x200UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000200 */\r
+#define ADC_OFR4_OFFSET4_10            (0x400UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000400 */\r
+#define ADC_OFR4_OFFSET4_11            (0x800UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000800 */\r
+\r
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)\r
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */\r
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */\r
+#define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */\r
+#define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */\r
+#define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */\r
+#define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */\r
+#define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */\r
+\r
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)\r
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */\r
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */\r
+\r
+/********************  Bit definition for ADC_JDR1 register  ******************/\r
+#define ADC_JDR1_JDATA_Pos             (0U)\r
+#define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */\r
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */\r
+#define ADC_JDR1_JDATA_0               (0x0001UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000001 */\r
+#define ADC_JDR1_JDATA_1               (0x0002UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000002 */\r
+#define ADC_JDR1_JDATA_2               (0x0004UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000004 */\r
+#define ADC_JDR1_JDATA_3               (0x0008UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000008 */\r
+#define ADC_JDR1_JDATA_4               (0x0010UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000010 */\r
+#define ADC_JDR1_JDATA_5               (0x0020UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000020 */\r
+#define ADC_JDR1_JDATA_6               (0x0040UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000040 */\r
+#define ADC_JDR1_JDATA_7               (0x0080UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000080 */\r
+#define ADC_JDR1_JDATA_8               (0x0100UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000100 */\r
+#define ADC_JDR1_JDATA_9               (0x0200UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000200 */\r
+#define ADC_JDR1_JDATA_10              (0x0400UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000400 */\r
+#define ADC_JDR1_JDATA_11              (0x0800UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000800 */\r
+#define ADC_JDR1_JDATA_12              (0x1000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00001000 */\r
+#define ADC_JDR1_JDATA_13              (0x2000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00002000 */\r
+#define ADC_JDR1_JDATA_14              (0x4000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00004000 */\r
+#define ADC_JDR1_JDATA_15              (0x8000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00008000 */\r
+\r
+/********************  Bit definition for ADC_JDR2 register  ******************/\r
+#define ADC_JDR2_JDATA_Pos             (0U)\r
+#define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */\r
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */\r
+#define ADC_JDR2_JDATA_0               (0x0001UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000001 */\r
+#define ADC_JDR2_JDATA_1               (0x0002UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000002 */\r
+#define ADC_JDR2_JDATA_2               (0x0004UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000004 */\r
+#define ADC_JDR2_JDATA_3               (0x0008UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000008 */\r
+#define ADC_JDR2_JDATA_4               (0x0010UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000010 */\r
+#define ADC_JDR2_JDATA_5               (0x0020UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000020 */\r
+#define ADC_JDR2_JDATA_6               (0x0040UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000040 */\r
+#define ADC_JDR2_JDATA_7               (0x0080UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000080 */\r
+#define ADC_JDR2_JDATA_8               (0x0100UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000100 */\r
+#define ADC_JDR2_JDATA_9               (0x0200UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000200 */\r
+#define ADC_JDR2_JDATA_10              (0x0400UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000400 */\r
+#define ADC_JDR2_JDATA_11              (0x0800UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000800 */\r
+#define ADC_JDR2_JDATA_12              (0x1000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00001000 */\r
+#define ADC_JDR2_JDATA_13              (0x2000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00002000 */\r
+#define ADC_JDR2_JDATA_14              (0x4000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00004000 */\r
+#define ADC_JDR2_JDATA_15              (0x8000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00008000 */\r
+\r
+/********************  Bit definition for ADC_JDR3 register  ******************/\r
+#define ADC_JDR3_JDATA_Pos             (0U)\r
+#define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */\r
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */\r
+#define ADC_JDR3_JDATA_0               (0x0001UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000001 */\r
+#define ADC_JDR3_JDATA_1               (0x0002UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000002 */\r
+#define ADC_JDR3_JDATA_2               (0x0004UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000004 */\r
+#define ADC_JDR3_JDATA_3               (0x0008UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000008 */\r
+#define ADC_JDR3_JDATA_4               (0x0010UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000010 */\r
+#define ADC_JDR3_JDATA_5               (0x0020UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000020 */\r
+#define ADC_JDR3_JDATA_6               (0x0040UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000040 */\r
+#define ADC_JDR3_JDATA_7               (0x0080UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000080 */\r
+#define ADC_JDR3_JDATA_8               (0x0100UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000100 */\r
+#define ADC_JDR3_JDATA_9               (0x0200UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000200 */\r
+#define ADC_JDR3_JDATA_10              (0x0400UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000400 */\r
+#define ADC_JDR3_JDATA_11              (0x0800UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000800 */\r
+#define ADC_JDR3_JDATA_12              (0x1000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00001000 */\r
+#define ADC_JDR3_JDATA_13              (0x2000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00002000 */\r
+#define ADC_JDR3_JDATA_14              (0x4000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00004000 */\r
+#define ADC_JDR3_JDATA_15              (0x8000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00008000 */\r
+\r
+/********************  Bit definition for ADC_JDR4 register  ******************/\r
+#define ADC_JDR4_JDATA_Pos             (0U)\r
+#define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */\r
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */\r
+#define ADC_JDR4_JDATA_0               (0x0001UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000001 */\r
+#define ADC_JDR4_JDATA_1               (0x0002UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000002 */\r
+#define ADC_JDR4_JDATA_2               (0x0004UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000004 */\r
+#define ADC_JDR4_JDATA_3               (0x0008UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000008 */\r
+#define ADC_JDR4_JDATA_4               (0x0010UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000010 */\r
+#define ADC_JDR4_JDATA_5               (0x0020UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000020 */\r
+#define ADC_JDR4_JDATA_6               (0x0040UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000040 */\r
+#define ADC_JDR4_JDATA_7               (0x0080UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000080 */\r
+#define ADC_JDR4_JDATA_8               (0x0100UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000100 */\r
+#define ADC_JDR4_JDATA_9               (0x0200UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000200 */\r
+#define ADC_JDR4_JDATA_10              (0x0400UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000400 */\r
+#define ADC_JDR4_JDATA_11              (0x0800UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000800 */\r
+#define ADC_JDR4_JDATA_12              (0x1000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00001000 */\r
+#define ADC_JDR4_JDATA_13              (0x2000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00002000 */\r
+#define ADC_JDR4_JDATA_14              (0x4000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00004000 */\r
+#define ADC_JDR4_JDATA_15              (0x8000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00008000 */\r
+\r
+/********************  Bit definition for ADC_AWD2CR register  ****************/\r
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)\r
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */\r
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */\r
+#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */\r
+#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */\r
+#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */\r
+#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */\r
+#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */\r
+#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */\r
+#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */\r
+#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */\r
+#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */\r
+#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */\r
+#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */\r
+#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */\r
+#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */\r
+#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */\r
+#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */\r
+#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */\r
+#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */\r
+#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */\r
+#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */\r
+\r
+/********************  Bit definition for ADC_AWD3CR register  ****************/\r
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)\r
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */\r
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */\r
+#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */\r
+#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */\r
+#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */\r
+#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */\r
+#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */\r
+#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */\r
+#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */\r
+#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */\r
+#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */\r
+#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */\r
+#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */\r
+#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */\r
+#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */\r
+#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */\r
+#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */\r
+#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */\r
+#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */\r
+#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */\r
+#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */\r
+\r
+/********************  Bit definition for ADC_DIFSEL register  ****************/\r
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)\r
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */\r
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */\r
+#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */\r
+#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */\r
+#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */\r
+#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */\r
+#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */\r
+#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */\r
+#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */\r
+#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */\r
+#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */\r
+#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */\r
+#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */\r
+#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */\r
+#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */\r
+#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */\r
+#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */\r
+#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */\r
+#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */\r
+#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */\r
+#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */\r
+\r
+/********************  Bit definition for ADC_CALFACT register  ***************/\r
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)\r
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */\r
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */\r
+#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */\r
+#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */\r
+#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */\r
+#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */\r
+#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */\r
+#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */\r
+#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */\r
+\r
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)\r
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */\r
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */\r
+#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */\r
+#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */\r
+#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */\r
+#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */\r
+#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */\r
+#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */\r
+#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */\r
+\r
+/*************************  ADC Common registers  *****************************/\r
+/********************  Bit definition for ADC_CSR register  *******************/\r
+#define ADC_CSR_ADRDY_MST_Pos          (0U)\r
+#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */\r
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */\r
+#define ADC_CSR_EOSMP_MST_Pos          (1U)\r
+#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */\r
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */\r
+#define ADC_CSR_EOC_MST_Pos            (2U)\r
+#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */\r
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */\r
+#define ADC_CSR_EOS_MST_Pos            (3U)\r
+#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */\r
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */\r
+#define ADC_CSR_OVR_MST_Pos            (4U)\r
+#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */\r
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */\r
+#define ADC_CSR_JEOC_MST_Pos           (5U)\r
+#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */\r
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */\r
+#define ADC_CSR_JEOS_MST_Pos           (6U)\r
+#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */\r
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */\r
+#define ADC_CSR_AWD1_MST_Pos           (7U)\r
+#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */\r
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */\r
+#define ADC_CSR_AWD2_MST_Pos           (8U)\r
+#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */\r
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */\r
+#define ADC_CSR_AWD3_MST_Pos           (9U)\r
+#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */\r
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */\r
+#define ADC_CSR_JQOVF_MST_Pos          (10U)\r
+#define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */\r
+#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */\r
+\r
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)\r
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */\r
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */\r
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)\r
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */\r
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */\r
+#define ADC_CSR_EOC_SLV_Pos            (18U)\r
+#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */\r
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */\r
+#define ADC_CSR_EOS_SLV_Pos            (19U)\r
+#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */\r
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */\r
+#define ADC_CSR_OVR_SLV_Pos            (20U)\r
+#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */\r
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */\r
+#define ADC_CSR_JEOC_SLV_Pos           (21U)\r
+#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */\r
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */\r
+#define ADC_CSR_JEOS_SLV_Pos           (22U)\r
+#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */\r
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */\r
+#define ADC_CSR_AWD1_SLV_Pos           (23U)\r
+#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */\r
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */\r
+#define ADC_CSR_AWD2_SLV_Pos           (24U)\r
+#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */\r
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */\r
+#define ADC_CSR_AWD3_SLV_Pos           (25U)\r
+#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */\r
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */\r
+#define ADC_CSR_JQOVF_SLV_Pos          (26U)\r
+#define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */\r
+#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */\r
+\r
+/********************  Bit definition for ADC_CCR register  *******************/\r
+#define ADC_CCR_DUAL_Pos               (0U)\r
+#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */\r
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */\r
+#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */\r
+#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */\r
+#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */\r
+#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */\r
+#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */\r
+\r
+#define ADC_CCR_DELAY_Pos              (8U)\r
+#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */\r
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */\r
+#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */\r
+#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */\r
+#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */\r
+#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */\r
+\r
+#define ADC_CCR_DMACFG_Pos             (13U)\r
+#define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */\r
+#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */\r
+\r
+#define ADC_CCR_MDMA_Pos               (14U)\r
+#define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */\r
+#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */\r
+#define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */\r
+#define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */\r
+\r
+#define ADC_CCR_CKMODE_Pos             (16U)\r
+#define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */\r
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */\r
+#define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */\r
+#define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */\r
+\r
+#define ADC_CCR_PRESC_Pos              (18U)\r
+#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */\r
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */\r
+#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */\r
+#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */\r
+#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */\r
+#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */\r
+\r
+#define ADC_CCR_VREFEN_Pos             (22U)\r
+#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */\r
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */\r
+#define ADC_CCR_TSEN_Pos               (23U)\r
+#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */\r
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */\r
+#define ADC_CCR_VBATEN_Pos             (24U)\r
+#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */\r
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */\r
+\r
+/********************  Bit definition for ADC_CDR register  *******************/\r
+#define ADC_CDR_RDATA_MST_Pos          (0U)\r
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */\r
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */\r
+#define ADC_CDR_RDATA_MST_0            (0x0001UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000001 */\r
+#define ADC_CDR_RDATA_MST_1            (0x0002UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000002 */\r
+#define ADC_CDR_RDATA_MST_2            (0x0004UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000004 */\r
+#define ADC_CDR_RDATA_MST_3            (0x0008UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000008 */\r
+#define ADC_CDR_RDATA_MST_4            (0x0010UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000010 */\r
+#define ADC_CDR_RDATA_MST_5            (0x0020UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000020 */\r
+#define ADC_CDR_RDATA_MST_6            (0x0040UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000040 */\r
+#define ADC_CDR_RDATA_MST_7            (0x0080UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000080 */\r
+#define ADC_CDR_RDATA_MST_8            (0x0100UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000100 */\r
+#define ADC_CDR_RDATA_MST_9            (0x0200UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000200 */\r
+#define ADC_CDR_RDATA_MST_10           (0x0400UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000400 */\r
+#define ADC_CDR_RDATA_MST_11           (0x0800UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000800 */\r
+#define ADC_CDR_RDATA_MST_12           (0x1000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00001000 */\r
+#define ADC_CDR_RDATA_MST_13           (0x2000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00002000 */\r
+#define ADC_CDR_RDATA_MST_14           (0x4000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00004000 */\r
+#define ADC_CDR_RDATA_MST_15           (0x8000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00008000 */\r
+\r
+#define ADC_CDR_RDATA_SLV_Pos          (16U)\r
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */\r
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */\r
+#define ADC_CDR_RDATA_SLV_0            (0x0001UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00010000 */\r
+#define ADC_CDR_RDATA_SLV_1            (0x0002UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00020000 */\r
+#define ADC_CDR_RDATA_SLV_2            (0x0004UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00040000 */\r
+#define ADC_CDR_RDATA_SLV_3            (0x0008UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00080000 */\r
+#define ADC_CDR_RDATA_SLV_4            (0x0010UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00100000 */\r
+#define ADC_CDR_RDATA_SLV_5            (0x0020UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00200000 */\r
+#define ADC_CDR_RDATA_SLV_6            (0x0040UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00400000 */\r
+#define ADC_CDR_RDATA_SLV_7            (0x0080UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00800000 */\r
+#define ADC_CDR_RDATA_SLV_8            (0x0100UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x01000000 */\r
+#define ADC_CDR_RDATA_SLV_9            (0x0200UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x02000000 */\r
+#define ADC_CDR_RDATA_SLV_10           (0x0400UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x04000000 */\r
+#define ADC_CDR_RDATA_SLV_11           (0x0800UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x08000000 */\r
+#define ADC_CDR_RDATA_SLV_12           (0x1000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x10000000 */\r
+#define ADC_CDR_RDATA_SLV_13           (0x2000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x20000000 */\r
+#define ADC_CDR_RDATA_SLV_14           (0x4000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x40000000 */\r
+#define ADC_CDR_RDATA_SLV_15           (0x8000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x80000000 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         Controller Area Network                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/*******************  Bit definition for CAN_MCR register  ********************/\r
+#define CAN_MCR_INRQ_Pos       (0U)\r
+#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                     /*!< 0x00000001 */\r
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP_Pos      (1U)\r
+#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                    /*!< 0x00000002 */\r
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP_Pos       (2U)\r
+#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                     /*!< 0x00000004 */\r
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM_Pos       (3U)\r
+#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                     /*!< 0x00000008 */\r
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART_Pos       (4U)\r
+#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                     /*!< 0x00000010 */\r
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM_Pos       (5U)\r
+#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                     /*!< 0x00000020 */\r
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM_Pos       (6U)\r
+#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                     /*!< 0x00000040 */\r
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM_Pos       (7U)\r
+#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                     /*!< 0x00000080 */\r
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET_Pos      (15U)\r
+#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                    /*!< 0x00008000 */\r
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\r
+\r
+/*******************  Bit definition for CAN_MSR register  ********************/\r
+#define CAN_MSR_INAK_Pos       (0U)\r
+#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                     /*!< 0x00000001 */\r
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK_Pos       (1U)\r
+#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                     /*!< 0x00000002 */\r
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI_Pos       (2U)\r
+#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                     /*!< 0x00000004 */\r
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI_Pos       (3U)\r
+#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                     /*!< 0x00000008 */\r
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI_Pos      (4U)\r
+#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                    /*!< 0x00000010 */\r
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM_Pos        (8U)\r
+#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                      /*!< 0x00000100 */\r
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\r
+#define CAN_MSR_RXM_Pos        (9U)\r
+#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                      /*!< 0x00000200 */\r
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\r
+#define CAN_MSR_SAMP_Pos       (10U)\r
+#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                     /*!< 0x00000400 */\r
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\r
+#define CAN_MSR_RX_Pos         (11U)\r
+#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                       /*!< 0x00000800 */\r
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\r
+\r
+/*******************  Bit definition for CAN_TSR register  ********************/\r
+#define CAN_TSR_RQCP0_Pos      (0U)\r
+#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0_Pos      (1U)\r
+#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                    /*!< 0x00000002 */\r
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0_Pos      (2U)\r
+#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                    /*!< 0x00000004 */\r
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0_Pos      (3U)\r
+#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                    /*!< 0x00000008 */\r
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0_Pos      (7U)\r
+#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                    /*!< 0x00000080 */\r
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1_Pos      (8U)\r
+#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                    /*!< 0x00000100 */\r
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1_Pos      (9U)\r
+#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                    /*!< 0x00000200 */\r
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1_Pos      (10U)\r
+#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                    /*!< 0x00000400 */\r
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1_Pos      (11U)\r
+#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                    /*!< 0x00000800 */\r
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1_Pos      (15U)\r
+#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                    /*!< 0x00008000 */\r
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2_Pos      (16U)\r
+#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                    /*!< 0x00010000 */\r
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2_Pos      (17U)\r
+#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                    /*!< 0x00020000 */\r
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2_Pos      (18U)\r
+#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                    /*!< 0x00040000 */\r
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2_Pos      (19U)\r
+#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                    /*!< 0x00080000 */\r
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2_Pos      (23U)\r
+#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                    /*!< 0x00800000 */\r
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE_Pos       (24U)\r
+#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                     /*!< 0x03000000 */\r
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME_Pos        (26U)\r
+#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                      /*!< 0x1C000000 */\r
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0_Pos       (26U)\r
+#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                     /*!< 0x04000000 */\r
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1_Pos       (27U)\r
+#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                     /*!< 0x08000000 */\r
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2_Pos       (28U)\r
+#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                     /*!< 0x10000000 */\r
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW_Pos        (29U)\r
+#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                      /*!< 0xE0000000 */\r
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0_Pos       (29U)\r
+#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                     /*!< 0x20000000 */\r
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1_Pos       (30U)\r
+#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                     /*!< 0x40000000 */\r
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2_Pos       (31U)\r
+#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                     /*!< 0x80000000 */\r
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/*******************  Bit definition for CAN_RF0R register  *******************/\r
+#define CAN_RF0R_FMP0_Pos      (0U)\r
+#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                    /*!< 0x00000003 */\r
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0_Pos     (3U)\r
+#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                   /*!< 0x00000008 */\r
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0_Pos     (4U)\r
+#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                   /*!< 0x00000010 */\r
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0_Pos     (5U)\r
+#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                   /*!< 0x00000020 */\r
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/*******************  Bit definition for CAN_RF1R register  *******************/\r
+#define CAN_RF1R_FMP1_Pos      (0U)\r
+#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                    /*!< 0x00000003 */\r
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1_Pos     (3U)\r
+#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                   /*!< 0x00000008 */\r
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1_Pos     (4U)\r
+#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                   /*!< 0x00000010 */\r
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1_Pos     (5U)\r
+#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                   /*!< 0x00000020 */\r
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/********************  Bit definition for CAN_IER register  *******************/\r
+#define CAN_IER_TMEIE_Pos      (0U)\r
+#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                    /*!< 0x00000001 */\r
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0_Pos     (1U)\r
+#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                   /*!< 0x00000002 */\r
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0_Pos      (2U)\r
+#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                    /*!< 0x00000004 */\r
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0_Pos     (3U)\r
+#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                   /*!< 0x00000008 */\r
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1_Pos     (4U)\r
+#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                   /*!< 0x00000010 */\r
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1_Pos      (5U)\r
+#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                    /*!< 0x00000020 */\r
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1_Pos     (6U)\r
+#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                   /*!< 0x00000040 */\r
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE_Pos      (8U)\r
+#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                    /*!< 0x00000100 */\r
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE_Pos      (9U)\r
+#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                    /*!< 0x00000200 */\r
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE_Pos      (10U)\r
+#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                    /*!< 0x00000400 */\r
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE_Pos      (11U)\r
+#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                    /*!< 0x00000800 */\r
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE_Pos      (15U)\r
+#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                    /*!< 0x00008000 */\r
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE_Pos      (16U)\r
+#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                    /*!< 0x00010000 */\r
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE_Pos      (17U)\r
+#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                    /*!< 0x00020000 */\r
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\r
+\r
+/********************  Bit definition for CAN_ESR register  *******************/\r
+#define CAN_ESR_EWGF_Pos       (0U)\r
+#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                     /*!< 0x00000001 */\r
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF_Pos       (1U)\r
+#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                     /*!< 0x00000002 */\r
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF_Pos       (2U)\r
+#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                     /*!< 0x00000004 */\r
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC_Pos        (4U)\r
+#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000070 */\r
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000010 */\r
+#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000020 */\r
+#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000040 */\r
+\r
+#define CAN_ESR_TEC_Pos        (16U)\r
+#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                     /*!< 0x00FF0000 */\r
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC_Pos        (24U)\r
+#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                     /*!< 0xFF000000 */\r
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\r
+\r
+/*******************  Bit definition for CAN_BTR register  ********************/\r
+#define CAN_BTR_BRP_Pos        (0U)\r
+#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                    /*!< 0x000003FF */\r
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1_Pos        (16U)\r
+#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                      /*!< 0x000F0000 */\r
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\r
+#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                      /*!< 0x00010000 */\r
+#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                      /*!< 0x00020000 */\r
+#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                      /*!< 0x00040000 */\r
+#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                      /*!< 0x00080000 */\r
+#define CAN_BTR_TS2_Pos        (20U)\r
+#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                      /*!< 0x00700000 */\r
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\r
+#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                      /*!< 0x00100000 */\r
+#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                      /*!< 0x00200000 */\r
+#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                      /*!< 0x00400000 */\r
+#define CAN_BTR_SJW_Pos        (24U)\r
+#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                      /*!< 0x03000000 */\r
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                      /*!< 0x01000000 */\r
+#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                      /*!< 0x02000000 */\r
+#define CAN_BTR_LBKM_Pos       (30U)\r
+#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                     /*!< 0x40000000 */\r
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM_Pos       (31U)\r
+#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                     /*!< 0x80000000 */\r
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/******************  Bit definition for CAN_TI0R register  ********************/\r
+#define CAN_TI0R_TXRQ_Pos      (0U)\r
+#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                    /*!< 0x00000001 */\r
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR_Pos       (1U)\r
+#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                     /*!< 0x00000002 */\r
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE_Pos       (2U)\r
+#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                     /*!< 0x00000004 */\r
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID_Pos      (3U)\r
+#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                /*!< 0x001FFFF8 */\r
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\r
+#define CAN_TI0R_STID_Pos      (21U)\r
+#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                  /*!< 0xFFE00000 */\r
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************  Bit definition for CAN_TDT0R register  *******************/\r
+#define CAN_TDT0R_DLC_Pos      (0U)\r
+#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                    /*!< 0x0000000F */\r
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT_Pos      (8U)\r
+#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                    /*!< 0x00000100 */\r
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME_Pos     (16U)\r
+#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                /*!< 0xFFFF0000 */\r
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\r
+\r
+/******************  Bit definition for CAN_TDL0R register  *******************/\r
+#define CAN_TDL0R_DATA0_Pos    (0U)\r
+#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                 /*!< 0x000000FF */\r
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1_Pos    (8U)\r
+#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2_Pos    (16U)\r
+#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3_Pos    (24U)\r
+#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\r
+\r
+/******************  Bit definition for CAN_TDH0R register  *******************/\r
+#define CAN_TDH0R_DATA4_Pos    (0U)\r
+#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                 /*!< 0x000000FF */\r
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5_Pos    (8U)\r
+#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6_Pos    (16U)\r
+#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7_Pos    (24U)\r
+#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_TI1R register  *******************/\r
+#define CAN_TI1R_TXRQ_Pos      (0U)\r
+#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                    /*!< 0x00000001 */\r
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR_Pos       (1U)\r
+#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                     /*!< 0x00000002 */\r
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE_Pos       (2U)\r
+#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                     /*!< 0x00000004 */\r
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID_Pos      (3U)\r
+#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                /*!< 0x001FFFF8 */\r
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\r
+#define CAN_TI1R_STID_Pos      (21U)\r
+#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                  /*!< 0xFFE00000 */\r
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_TDT1R register  ******************/\r
+#define CAN_TDT1R_DLC_Pos      (0U)\r
+#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                    /*!< 0x0000000F */\r
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT_Pos      (8U)\r
+#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                    /*!< 0x00000100 */\r
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME_Pos     (16U)\r
+#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                /*!< 0xFFFF0000 */\r
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_TDL1R register  ******************/\r
+#define CAN_TDL1R_DATA0_Pos    (0U)\r
+#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                 /*!< 0x000000FF */\r
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1_Pos    (8U)\r
+#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2_Pos    (16U)\r
+#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3_Pos    (24U)\r
+#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_TDH1R register  ******************/\r
+#define CAN_TDH1R_DATA4_Pos    (0U)\r
+#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                 /*!< 0x000000FF */\r
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5_Pos    (8U)\r
+#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6_Pos    (16U)\r
+#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7_Pos    (24U)\r
+#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_TI2R register  *******************/\r
+#define CAN_TI2R_TXRQ_Pos      (0U)\r
+#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                    /*!< 0x00000001 */\r
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR_Pos       (1U)\r
+#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                     /*!< 0x00000002 */\r
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE_Pos       (2U)\r
+#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                     /*!< 0x00000004 */\r
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID_Pos      (3U)\r
+#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                /*!< 0x001FFFF8 */\r
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\r
+#define CAN_TI2R_STID_Pos      (21U)\r
+#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                  /*!< 0xFFE00000 */\r
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_TDT2R register  ******************/\r
+#define CAN_TDT2R_DLC_Pos      (0U)\r
+#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                    /*!< 0x0000000F */\r
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT_Pos      (8U)\r
+#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                    /*!< 0x00000100 */\r
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME_Pos     (16U)\r
+#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                /*!< 0xFFFF0000 */\r
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_TDL2R register  ******************/\r
+#define CAN_TDL2R_DATA0_Pos    (0U)\r
+#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                 /*!< 0x000000FF */\r
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1_Pos    (8U)\r
+#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2_Pos    (16U)\r
+#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3_Pos    (24U)\r
+#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_TDH2R register  ******************/\r
+#define CAN_TDH2R_DATA4_Pos    (0U)\r
+#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                 /*!< 0x000000FF */\r
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5_Pos    (8U)\r
+#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6_Pos    (16U)\r
+#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7_Pos    (24U)\r
+#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_RI0R register  *******************/\r
+#define CAN_RI0R_RTR_Pos       (1U)\r
+#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                     /*!< 0x00000002 */\r
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE_Pos       (2U)\r
+#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                     /*!< 0x00000004 */\r
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID_Pos      (3U)\r
+#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                /*!< 0x001FFFF8 */\r
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\r
+#define CAN_RI0R_STID_Pos      (21U)\r
+#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                  /*!< 0xFFE00000 */\r
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_RDT0R register  ******************/\r
+#define CAN_RDT0R_DLC_Pos      (0U)\r
+#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                    /*!< 0x0000000F */\r
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI_Pos      (8U)\r
+#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                   /*!< 0x0000FF00 */\r
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME_Pos     (16U)\r
+#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                /*!< 0xFFFF0000 */\r
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_RDL0R register  ******************/\r
+#define CAN_RDL0R_DATA0_Pos    (0U)\r
+#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                 /*!< 0x000000FF */\r
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1_Pos    (8U)\r
+#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2_Pos    (16U)\r
+#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3_Pos    (24U)\r
+#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_RDH0R register  ******************/\r
+#define CAN_RDH0R_DATA4_Pos    (0U)\r
+#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                 /*!< 0x000000FF */\r
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5_Pos    (8U)\r
+#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6_Pos    (16U)\r
+#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7_Pos    (24U)\r
+#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_RI1R register  *******************/\r
+#define CAN_RI1R_RTR_Pos       (1U)\r
+#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                     /*!< 0x00000002 */\r
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE_Pos       (2U)\r
+#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                     /*!< 0x00000004 */\r
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID_Pos      (3U)\r
+#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                /*!< 0x001FFFF8 */\r
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\r
+#define CAN_RI1R_STID_Pos      (21U)\r
+#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                  /*!< 0xFFE00000 */\r
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_RDT1R register  ******************/\r
+#define CAN_RDT1R_DLC_Pos      (0U)\r
+#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                    /*!< 0x0000000F */\r
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI_Pos      (8U)\r
+#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                   /*!< 0x0000FF00 */\r
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME_Pos     (16U)\r
+#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                /*!< 0xFFFF0000 */\r
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_RDL1R register  ******************/\r
+#define CAN_RDL1R_DATA0_Pos    (0U)\r
+#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                 /*!< 0x000000FF */\r
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1_Pos    (8U)\r
+#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2_Pos    (16U)\r
+#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3_Pos    (24U)\r
+#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_RDH1R register  ******************/\r
+#define CAN_RDH1R_DATA4_Pos    (0U)\r
+#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                 /*!< 0x000000FF */\r
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5_Pos    (8U)\r
+#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6_Pos    (16U)\r
+#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7_Pos    (24U)\r
+#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                 /*!< 0xFF000000 */\r
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/*******************  Bit definition for CAN_FMR register  ********************/\r
+#define CAN_FMR_FINIT_Pos      (0U)\r
+#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                    /*!< 0x00000001 */\r
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\r
+\r
+/*******************  Bit definition for CAN_FM1R register  *******************/\r
+#define CAN_FM1R_FBM_Pos       (0U)\r
+#define CAN_FM1R_FBM_Msk       (0x3FFFUL << CAN_FM1R_FBM_Pos)                  /*!< 0x00003FFF */\r
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0_Pos      (0U)\r
+#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1_Pos      (1U)\r
+#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2_Pos      (2U)\r
+#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3_Pos      (3U)\r
+#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4_Pos      (4U)\r
+#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5_Pos      (5U)\r
+#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6_Pos      (6U)\r
+#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7_Pos      (7U)\r
+#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8_Pos      (8U)\r
+#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9_Pos      (9U)\r
+#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10_Pos     (10U)\r
+#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11_Pos     (11U)\r
+#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12_Pos     (12U)\r
+#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13_Pos     (13U)\r
+#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\r
+\r
+/*******************  Bit definition for CAN_FS1R register  *******************/\r
+#define CAN_FS1R_FSC_Pos       (0U)\r
+#define CAN_FS1R_FSC_Msk       (0x3FFFUL << CAN_FS1R_FSC_Pos)                  /*!< 0x00003FFF */\r
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0_Pos      (0U)\r
+#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1_Pos      (1U)\r
+#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2_Pos      (2U)\r
+#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3_Pos      (3U)\r
+#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4_Pos      (4U)\r
+#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5_Pos      (5U)\r
+#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6_Pos      (6U)\r
+#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7_Pos      (7U)\r
+#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8_Pos      (8U)\r
+#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9_Pos      (9U)\r
+#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10_Pos     (10U)\r
+#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11_Pos     (11U)\r
+#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12_Pos     (12U)\r
+#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13_Pos     (13U)\r
+#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\r
+\r
+/******************  Bit definition for CAN_FFA1R register  *******************/\r
+#define CAN_FFA1R_FFA_Pos      (0U)\r
+#define CAN_FFA1R_FFA_Msk      (0x3FFFUL << CAN_FFA1R_FFA_Pos)                 /*!< 0x00003FFF */\r
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0_Pos     (0U)\r
+#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                   /*!< 0x00000001 */\r
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1_Pos     (1U)\r
+#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                   /*!< 0x00000002 */\r
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2_Pos     (2U)\r
+#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                   /*!< 0x00000004 */\r
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3_Pos     (3U)\r
+#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                   /*!< 0x00000008 */\r
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4_Pos     (4U)\r
+#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                   /*!< 0x00000010 */\r
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5_Pos     (5U)\r
+#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                   /*!< 0x00000020 */\r
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6_Pos     (6U)\r
+#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                   /*!< 0x00000040 */\r
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7_Pos     (7U)\r
+#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                   /*!< 0x00000080 */\r
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8_Pos     (8U)\r
+#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                   /*!< 0x00000100 */\r
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9_Pos     (9U)\r
+#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                   /*!< 0x00000200 */\r
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10_Pos    (10U)\r
+#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                  /*!< 0x00000400 */\r
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11_Pos    (11U)\r
+#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                  /*!< 0x00000800 */\r
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12_Pos    (12U)\r
+#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                  /*!< 0x00001000 */\r
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13_Pos    (13U)\r
+#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                  /*!< 0x00002000 */\r
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/*******************  Bit definition for CAN_FA1R register  *******************/\r
+#define CAN_FA1R_FACT_Pos      (0U)\r
+#define CAN_FA1R_FACT_Msk      (0x3FFFUL << CAN_FA1R_FACT_Pos)                 /*!< 0x00003FFF */\r
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\r
+#define CAN_FA1R_FACT0_Pos     (0U)\r
+#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                   /*!< 0x00000001 */\r
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1_Pos     (1U)\r
+#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                   /*!< 0x00000002 */\r
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2_Pos     (2U)\r
+#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                   /*!< 0x00000004 */\r
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3_Pos     (3U)\r
+#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                   /*!< 0x00000008 */\r
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4_Pos     (4U)\r
+#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                   /*!< 0x00000010 */\r
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5_Pos     (5U)\r
+#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                   /*!< 0x00000020 */\r
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6_Pos     (6U)\r
+#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                   /*!< 0x00000040 */\r
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7_Pos     (7U)\r
+#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                   /*!< 0x00000080 */\r
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8_Pos     (8U)\r
+#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                   /*!< 0x00000100 */\r
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9_Pos     (9U)\r
+#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                   /*!< 0x00000200 */\r
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10_Pos    (10U)\r
+#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                  /*!< 0x00000400 */\r
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11_Pos    (11U)\r
+#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                  /*!< 0x00000800 */\r
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12_Pos    (12U)\r
+#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                  /*!< 0x00001000 */\r
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13_Pos    (13U)\r
+#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                  /*!< 0x00002000 */\r
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */\r
+\r
+/*******************  Bit definition for CAN_F0R1 register  *******************/\r
+#define CAN_F0R1_FB0_Pos       (0U)\r
+#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1_Pos       (1U)\r
+#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2_Pos       (2U)\r
+#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3_Pos       (3U)\r
+#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4_Pos       (4U)\r
+#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5_Pos       (5U)\r
+#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6_Pos       (6U)\r
+#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7_Pos       (7U)\r
+#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8_Pos       (8U)\r
+#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9_Pos       (9U)\r
+#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10_Pos      (10U)\r
+#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11_Pos      (11U)\r
+#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12_Pos      (12U)\r
+#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13_Pos      (13U)\r
+#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14_Pos      (14U)\r
+#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15_Pos      (15U)\r
+#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16_Pos      (16U)\r
+#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17_Pos      (17U)\r
+#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18_Pos      (18U)\r
+#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19_Pos      (19U)\r
+#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20_Pos      (20U)\r
+#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21_Pos      (21U)\r
+#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22_Pos      (22U)\r
+#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23_Pos      (23U)\r
+#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24_Pos      (24U)\r
+#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25_Pos      (25U)\r
+#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26_Pos      (26U)\r
+#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27_Pos      (27U)\r
+#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28_Pos      (28U)\r
+#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29_Pos      (29U)\r
+#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30_Pos      (30U)\r
+#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31_Pos      (31U)\r
+#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F1R1 register  *******************/\r
+#define CAN_F1R1_FB0_Pos       (0U)\r
+#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1_Pos       (1U)\r
+#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2_Pos       (2U)\r
+#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3_Pos       (3U)\r
+#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4_Pos       (4U)\r
+#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5_Pos       (5U)\r
+#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6_Pos       (6U)\r
+#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7_Pos       (7U)\r
+#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8_Pos       (8U)\r
+#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9_Pos       (9U)\r
+#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10_Pos      (10U)\r
+#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11_Pos      (11U)\r
+#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12_Pos      (12U)\r
+#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13_Pos      (13U)\r
+#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14_Pos      (14U)\r
+#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15_Pos      (15U)\r
+#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16_Pos      (16U)\r
+#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17_Pos      (17U)\r
+#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18_Pos      (18U)\r
+#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19_Pos      (19U)\r
+#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20_Pos      (20U)\r
+#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21_Pos      (21U)\r
+#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22_Pos      (22U)\r
+#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23_Pos      (23U)\r
+#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24_Pos      (24U)\r
+#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25_Pos      (25U)\r
+#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26_Pos      (26U)\r
+#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27_Pos      (27U)\r
+#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28_Pos      (28U)\r
+#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29_Pos      (29U)\r
+#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30_Pos      (30U)\r
+#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31_Pos      (31U)\r
+#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F2R1 register  *******************/\r
+#define CAN_F2R1_FB0_Pos       (0U)\r
+#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1_Pos       (1U)\r
+#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2_Pos       (2U)\r
+#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3_Pos       (3U)\r
+#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4_Pos       (4U)\r
+#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5_Pos       (5U)\r
+#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6_Pos       (6U)\r
+#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7_Pos       (7U)\r
+#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8_Pos       (8U)\r
+#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9_Pos       (9U)\r
+#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10_Pos      (10U)\r
+#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11_Pos      (11U)\r
+#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12_Pos      (12U)\r
+#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13_Pos      (13U)\r
+#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14_Pos      (14U)\r
+#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15_Pos      (15U)\r
+#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16_Pos      (16U)\r
+#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17_Pos      (17U)\r
+#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18_Pos      (18U)\r
+#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19_Pos      (19U)\r
+#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20_Pos      (20U)\r
+#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21_Pos      (21U)\r
+#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22_Pos      (22U)\r
+#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23_Pos      (23U)\r
+#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24_Pos      (24U)\r
+#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25_Pos      (25U)\r
+#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26_Pos      (26U)\r
+#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27_Pos      (27U)\r
+#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28_Pos      (28U)\r
+#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29_Pos      (29U)\r
+#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30_Pos      (30U)\r
+#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31_Pos      (31U)\r
+#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F3R1 register  *******************/\r
+#define CAN_F3R1_FB0_Pos       (0U)\r
+#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1_Pos       (1U)\r
+#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2_Pos       (2U)\r
+#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3_Pos       (3U)\r
+#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4_Pos       (4U)\r
+#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5_Pos       (5U)\r
+#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6_Pos       (6U)\r
+#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7_Pos       (7U)\r
+#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8_Pos       (8U)\r
+#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9_Pos       (9U)\r
+#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10_Pos      (10U)\r
+#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11_Pos      (11U)\r
+#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12_Pos      (12U)\r
+#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13_Pos      (13U)\r
+#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14_Pos      (14U)\r
+#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15_Pos      (15U)\r
+#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16_Pos      (16U)\r
+#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17_Pos      (17U)\r
+#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18_Pos      (18U)\r
+#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19_Pos      (19U)\r
+#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20_Pos      (20U)\r
+#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21_Pos      (21U)\r
+#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22_Pos      (22U)\r
+#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23_Pos      (23U)\r
+#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24_Pos      (24U)\r
+#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25_Pos      (25U)\r
+#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26_Pos      (26U)\r
+#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27_Pos      (27U)\r
+#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28_Pos      (28U)\r
+#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29_Pos      (29U)\r
+#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30_Pos      (30U)\r
+#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31_Pos      (31U)\r
+#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F4R1 register  *******************/\r
+#define CAN_F4R1_FB0_Pos       (0U)\r
+#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1_Pos       (1U)\r
+#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2_Pos       (2U)\r
+#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3_Pos       (3U)\r
+#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4_Pos       (4U)\r
+#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5_Pos       (5U)\r
+#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6_Pos       (6U)\r
+#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7_Pos       (7U)\r
+#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8_Pos       (8U)\r
+#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9_Pos       (9U)\r
+#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10_Pos      (10U)\r
+#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11_Pos      (11U)\r
+#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12_Pos      (12U)\r
+#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13_Pos      (13U)\r
+#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14_Pos      (14U)\r
+#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15_Pos      (15U)\r
+#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16_Pos      (16U)\r
+#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17_Pos      (17U)\r
+#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18_Pos      (18U)\r
+#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19_Pos      (19U)\r
+#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20_Pos      (20U)\r
+#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21_Pos      (21U)\r
+#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22_Pos      (22U)\r
+#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23_Pos      (23U)\r
+#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24_Pos      (24U)\r
+#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25_Pos      (25U)\r
+#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26_Pos      (26U)\r
+#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27_Pos      (27U)\r
+#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28_Pos      (28U)\r
+#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29_Pos      (29U)\r
+#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30_Pos      (30U)\r
+#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31_Pos      (31U)\r
+#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F5R1 register  *******************/\r
+#define CAN_F5R1_FB0_Pos       (0U)\r
+#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1_Pos       (1U)\r
+#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2_Pos       (2U)\r
+#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3_Pos       (3U)\r
+#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4_Pos       (4U)\r
+#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5_Pos       (5U)\r
+#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6_Pos       (6U)\r
+#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7_Pos       (7U)\r
+#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8_Pos       (8U)\r
+#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9_Pos       (9U)\r
+#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10_Pos      (10U)\r
+#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11_Pos      (11U)\r
+#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12_Pos      (12U)\r
+#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13_Pos      (13U)\r
+#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14_Pos      (14U)\r
+#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15_Pos      (15U)\r
+#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16_Pos      (16U)\r
+#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17_Pos      (17U)\r
+#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18_Pos      (18U)\r
+#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19_Pos      (19U)\r
+#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20_Pos      (20U)\r
+#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21_Pos      (21U)\r
+#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22_Pos      (22U)\r
+#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23_Pos      (23U)\r
+#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24_Pos      (24U)\r
+#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25_Pos      (25U)\r
+#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26_Pos      (26U)\r
+#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27_Pos      (27U)\r
+#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28_Pos      (28U)\r
+#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29_Pos      (29U)\r
+#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30_Pos      (30U)\r
+#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31_Pos      (31U)\r
+#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F6R1 register  *******************/\r
+#define CAN_F6R1_FB0_Pos       (0U)\r
+#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1_Pos       (1U)\r
+#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2_Pos       (2U)\r
+#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3_Pos       (3U)\r
+#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4_Pos       (4U)\r
+#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5_Pos       (5U)\r
+#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6_Pos       (6U)\r
+#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7_Pos       (7U)\r
+#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8_Pos       (8U)\r
+#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9_Pos       (9U)\r
+#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10_Pos      (10U)\r
+#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11_Pos      (11U)\r
+#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12_Pos      (12U)\r
+#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13_Pos      (13U)\r
+#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14_Pos      (14U)\r
+#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15_Pos      (15U)\r
+#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16_Pos      (16U)\r
+#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17_Pos      (17U)\r
+#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18_Pos      (18U)\r
+#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19_Pos      (19U)\r
+#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20_Pos      (20U)\r
+#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21_Pos      (21U)\r
+#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22_Pos      (22U)\r
+#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23_Pos      (23U)\r
+#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24_Pos      (24U)\r
+#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25_Pos      (25U)\r
+#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26_Pos      (26U)\r
+#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27_Pos      (27U)\r
+#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28_Pos      (28U)\r
+#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29_Pos      (29U)\r
+#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30_Pos      (30U)\r
+#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31_Pos      (31U)\r
+#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F7R1 register  *******************/\r
+#define CAN_F7R1_FB0_Pos       (0U)\r
+#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1_Pos       (1U)\r
+#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2_Pos       (2U)\r
+#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3_Pos       (3U)\r
+#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4_Pos       (4U)\r
+#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5_Pos       (5U)\r
+#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6_Pos       (6U)\r
+#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7_Pos       (7U)\r
+#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8_Pos       (8U)\r
+#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9_Pos       (9U)\r
+#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10_Pos      (10U)\r
+#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11_Pos      (11U)\r
+#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12_Pos      (12U)\r
+#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13_Pos      (13U)\r
+#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14_Pos      (14U)\r
+#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15_Pos      (15U)\r
+#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16_Pos      (16U)\r
+#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17_Pos      (17U)\r
+#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18_Pos      (18U)\r
+#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19_Pos      (19U)\r
+#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20_Pos      (20U)\r
+#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21_Pos      (21U)\r
+#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22_Pos      (22U)\r
+#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23_Pos      (23U)\r
+#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24_Pos      (24U)\r
+#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25_Pos      (25U)\r
+#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26_Pos      (26U)\r
+#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27_Pos      (27U)\r
+#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28_Pos      (28U)\r
+#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29_Pos      (29U)\r
+#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30_Pos      (30U)\r
+#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31_Pos      (31U)\r
+#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F8R1 register  *******************/\r
+#define CAN_F8R1_FB0_Pos       (0U)\r
+#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1_Pos       (1U)\r
+#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2_Pos       (2U)\r
+#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3_Pos       (3U)\r
+#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4_Pos       (4U)\r
+#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5_Pos       (5U)\r
+#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6_Pos       (6U)\r
+#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7_Pos       (7U)\r
+#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8_Pos       (8U)\r
+#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9_Pos       (9U)\r
+#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10_Pos      (10U)\r
+#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11_Pos      (11U)\r
+#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12_Pos      (12U)\r
+#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13_Pos      (13U)\r
+#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14_Pos      (14U)\r
+#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15_Pos      (15U)\r
+#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16_Pos      (16U)\r
+#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17_Pos      (17U)\r
+#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18_Pos      (18U)\r
+#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19_Pos      (19U)\r
+#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20_Pos      (20U)\r
+#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21_Pos      (21U)\r
+#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22_Pos      (22U)\r
+#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23_Pos      (23U)\r
+#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24_Pos      (24U)\r
+#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25_Pos      (25U)\r
+#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26_Pos      (26U)\r
+#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27_Pos      (27U)\r
+#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28_Pos      (28U)\r
+#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29_Pos      (29U)\r
+#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30_Pos      (30U)\r
+#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31_Pos      (31U)\r
+#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F9R1 register  *******************/\r
+#define CAN_F9R1_FB0_Pos       (0U)\r
+#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1_Pos       (1U)\r
+#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2_Pos       (2U)\r
+#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3_Pos       (3U)\r
+#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4_Pos       (4U)\r
+#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5_Pos       (5U)\r
+#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6_Pos       (6U)\r
+#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7_Pos       (7U)\r
+#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8_Pos       (8U)\r
+#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9_Pos       (9U)\r
+#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10_Pos      (10U)\r
+#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11_Pos      (11U)\r
+#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12_Pos      (12U)\r
+#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13_Pos      (13U)\r
+#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14_Pos      (14U)\r
+#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15_Pos      (15U)\r
+#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16_Pos      (16U)\r
+#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17_Pos      (17U)\r
+#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18_Pos      (18U)\r
+#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19_Pos      (19U)\r
+#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20_Pos      (20U)\r
+#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21_Pos      (21U)\r
+#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22_Pos      (22U)\r
+#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23_Pos      (23U)\r
+#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24_Pos      (24U)\r
+#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25_Pos      (25U)\r
+#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26_Pos      (26U)\r
+#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27_Pos      (27U)\r
+#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28_Pos      (28U)\r
+#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29_Pos      (29U)\r
+#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30_Pos      (30U)\r
+#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31_Pos      (31U)\r
+#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F10R1 register  ******************/\r
+#define CAN_F10R1_FB0_Pos      (0U)\r
+#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1_Pos      (1U)\r
+#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2_Pos      (2U)\r
+#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3_Pos      (3U)\r
+#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4_Pos      (4U)\r
+#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5_Pos      (5U)\r
+#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6_Pos      (6U)\r
+#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7_Pos      (7U)\r
+#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8_Pos      (8U)\r
+#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9_Pos      (9U)\r
+#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10_Pos     (10U)\r
+#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11_Pos     (11U)\r
+#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12_Pos     (12U)\r
+#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13_Pos     (13U)\r
+#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14_Pos     (14U)\r
+#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15_Pos     (15U)\r
+#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16_Pos     (16U)\r
+#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17_Pos     (17U)\r
+#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18_Pos     (18U)\r
+#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19_Pos     (19U)\r
+#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20_Pos     (20U)\r
+#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21_Pos     (21U)\r
+#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22_Pos     (22U)\r
+#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23_Pos     (23U)\r
+#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24_Pos     (24U)\r
+#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25_Pos     (25U)\r
+#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26_Pos     (26U)\r
+#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27_Pos     (27U)\r
+#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28_Pos     (28U)\r
+#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29_Pos     (29U)\r
+#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30_Pos     (30U)\r
+#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31_Pos     (31U)\r
+#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F11R1 register  ******************/\r
+#define CAN_F11R1_FB0_Pos      (0U)\r
+#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1_Pos      (1U)\r
+#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2_Pos      (2U)\r
+#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3_Pos      (3U)\r
+#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4_Pos      (4U)\r
+#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5_Pos      (5U)\r
+#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6_Pos      (6U)\r
+#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7_Pos      (7U)\r
+#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8_Pos      (8U)\r
+#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9_Pos      (9U)\r
+#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10_Pos     (10U)\r
+#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11_Pos     (11U)\r
+#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12_Pos     (12U)\r
+#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13_Pos     (13U)\r
+#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14_Pos     (14U)\r
+#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15_Pos     (15U)\r
+#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16_Pos     (16U)\r
+#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17_Pos     (17U)\r
+#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18_Pos     (18U)\r
+#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19_Pos     (19U)\r
+#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20_Pos     (20U)\r
+#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21_Pos     (21U)\r
+#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22_Pos     (22U)\r
+#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23_Pos     (23U)\r
+#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24_Pos     (24U)\r
+#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25_Pos     (25U)\r
+#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26_Pos     (26U)\r
+#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27_Pos     (27U)\r
+#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28_Pos     (28U)\r
+#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29_Pos     (29U)\r
+#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30_Pos     (30U)\r
+#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31_Pos     (31U)\r
+#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F12R1 register  ******************/\r
+#define CAN_F12R1_FB0_Pos      (0U)\r
+#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1_Pos      (1U)\r
+#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2_Pos      (2U)\r
+#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3_Pos      (3U)\r
+#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4_Pos      (4U)\r
+#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5_Pos      (5U)\r
+#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6_Pos      (6U)\r
+#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7_Pos      (7U)\r
+#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8_Pos      (8U)\r
+#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9_Pos      (9U)\r
+#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10_Pos     (10U)\r
+#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11_Pos     (11U)\r
+#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12_Pos     (12U)\r
+#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13_Pos     (13U)\r
+#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14_Pos     (14U)\r
+#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15_Pos     (15U)\r
+#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16_Pos     (16U)\r
+#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17_Pos     (17U)\r
+#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18_Pos     (18U)\r
+#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19_Pos     (19U)\r
+#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20_Pos     (20U)\r
+#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21_Pos     (21U)\r
+#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22_Pos     (22U)\r
+#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23_Pos     (23U)\r
+#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24_Pos     (24U)\r
+#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25_Pos     (25U)\r
+#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26_Pos     (26U)\r
+#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27_Pos     (27U)\r
+#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28_Pos     (28U)\r
+#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29_Pos     (29U)\r
+#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30_Pos     (30U)\r
+#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31_Pos     (31U)\r
+#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F13R1 register  ******************/\r
+#define CAN_F13R1_FB0_Pos      (0U)\r
+#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1_Pos      (1U)\r
+#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2_Pos      (2U)\r
+#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3_Pos      (3U)\r
+#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4_Pos      (4U)\r
+#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5_Pos      (5U)\r
+#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6_Pos      (6U)\r
+#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7_Pos      (7U)\r
+#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8_Pos      (8U)\r
+#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9_Pos      (9U)\r
+#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10_Pos     (10U)\r
+#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11_Pos     (11U)\r
+#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12_Pos     (12U)\r
+#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13_Pos     (13U)\r
+#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14_Pos     (14U)\r
+#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15_Pos     (15U)\r
+#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16_Pos     (16U)\r
+#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17_Pos     (17U)\r
+#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18_Pos     (18U)\r
+#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19_Pos     (19U)\r
+#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20_Pos     (20U)\r
+#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21_Pos     (21U)\r
+#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22_Pos     (22U)\r
+#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23_Pos     (23U)\r
+#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24_Pos     (24U)\r
+#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25_Pos     (25U)\r
+#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26_Pos     (26U)\r
+#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27_Pos     (27U)\r
+#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28_Pos     (28U)\r
+#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29_Pos     (29U)\r
+#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30_Pos     (30U)\r
+#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31_Pos     (31U)\r
+#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F0R2 register  *******************/\r
+#define CAN_F0R2_FB0_Pos       (0U)\r
+#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1_Pos       (1U)\r
+#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2_Pos       (2U)\r
+#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3_Pos       (3U)\r
+#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4_Pos       (4U)\r
+#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5_Pos       (5U)\r
+#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6_Pos       (6U)\r
+#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7_Pos       (7U)\r
+#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8_Pos       (8U)\r
+#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9_Pos       (9U)\r
+#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10_Pos      (10U)\r
+#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11_Pos      (11U)\r
+#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12_Pos      (12U)\r
+#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13_Pos      (13U)\r
+#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14_Pos      (14U)\r
+#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15_Pos      (15U)\r
+#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16_Pos      (16U)\r
+#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17_Pos      (17U)\r
+#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18_Pos      (18U)\r
+#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19_Pos      (19U)\r
+#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20_Pos      (20U)\r
+#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21_Pos      (21U)\r
+#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22_Pos      (22U)\r
+#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23_Pos      (23U)\r
+#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24_Pos      (24U)\r
+#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25_Pos      (25U)\r
+#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26_Pos      (26U)\r
+#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27_Pos      (27U)\r
+#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28_Pos      (28U)\r
+#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29_Pos      (29U)\r
+#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30_Pos      (30U)\r
+#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31_Pos      (31U)\r
+#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F1R2 register  *******************/\r
+#define CAN_F1R2_FB0_Pos       (0U)\r
+#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1_Pos       (1U)\r
+#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2_Pos       (2U)\r
+#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3_Pos       (3U)\r
+#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4_Pos       (4U)\r
+#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5_Pos       (5U)\r
+#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6_Pos       (6U)\r
+#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7_Pos       (7U)\r
+#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8_Pos       (8U)\r
+#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9_Pos       (9U)\r
+#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10_Pos      (10U)\r
+#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11_Pos      (11U)\r
+#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12_Pos      (12U)\r
+#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13_Pos      (13U)\r
+#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14_Pos      (14U)\r
+#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15_Pos      (15U)\r
+#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16_Pos      (16U)\r
+#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17_Pos      (17U)\r
+#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18_Pos      (18U)\r
+#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19_Pos      (19U)\r
+#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20_Pos      (20U)\r
+#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21_Pos      (21U)\r
+#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22_Pos      (22U)\r
+#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23_Pos      (23U)\r
+#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24_Pos      (24U)\r
+#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25_Pos      (25U)\r
+#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26_Pos      (26U)\r
+#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27_Pos      (27U)\r
+#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28_Pos      (28U)\r
+#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29_Pos      (29U)\r
+#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30_Pos      (30U)\r
+#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31_Pos      (31U)\r
+#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F2R2 register  *******************/\r
+#define CAN_F2R2_FB0_Pos       (0U)\r
+#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1_Pos       (1U)\r
+#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2_Pos       (2U)\r
+#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3_Pos       (3U)\r
+#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4_Pos       (4U)\r
+#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5_Pos       (5U)\r
+#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6_Pos       (6U)\r
+#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7_Pos       (7U)\r
+#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8_Pos       (8U)\r
+#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9_Pos       (9U)\r
+#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10_Pos      (10U)\r
+#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11_Pos      (11U)\r
+#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12_Pos      (12U)\r
+#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13_Pos      (13U)\r
+#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14_Pos      (14U)\r
+#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15_Pos      (15U)\r
+#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16_Pos      (16U)\r
+#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17_Pos      (17U)\r
+#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18_Pos      (18U)\r
+#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19_Pos      (19U)\r
+#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20_Pos      (20U)\r
+#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21_Pos      (21U)\r
+#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22_Pos      (22U)\r
+#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23_Pos      (23U)\r
+#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24_Pos      (24U)\r
+#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25_Pos      (25U)\r
+#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26_Pos      (26U)\r
+#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27_Pos      (27U)\r
+#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28_Pos      (28U)\r
+#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29_Pos      (29U)\r
+#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30_Pos      (30U)\r
+#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31_Pos      (31U)\r
+#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F3R2 register  *******************/\r
+#define CAN_F3R2_FB0_Pos       (0U)\r
+#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1_Pos       (1U)\r
+#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2_Pos       (2U)\r
+#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3_Pos       (3U)\r
+#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4_Pos       (4U)\r
+#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5_Pos       (5U)\r
+#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6_Pos       (6U)\r
+#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7_Pos       (7U)\r
+#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8_Pos       (8U)\r
+#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9_Pos       (9U)\r
+#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10_Pos      (10U)\r
+#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11_Pos      (11U)\r
+#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12_Pos      (12U)\r
+#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13_Pos      (13U)\r
+#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14_Pos      (14U)\r
+#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15_Pos      (15U)\r
+#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16_Pos      (16U)\r
+#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17_Pos      (17U)\r
+#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18_Pos      (18U)\r
+#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19_Pos      (19U)\r
+#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20_Pos      (20U)\r
+#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21_Pos      (21U)\r
+#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22_Pos      (22U)\r
+#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23_Pos      (23U)\r
+#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24_Pos      (24U)\r
+#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25_Pos      (25U)\r
+#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26_Pos      (26U)\r
+#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27_Pos      (27U)\r
+#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28_Pos      (28U)\r
+#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29_Pos      (29U)\r
+#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30_Pos      (30U)\r
+#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31_Pos      (31U)\r
+#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F4R2 register  *******************/\r
+#define CAN_F4R2_FB0_Pos       (0U)\r
+#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1_Pos       (1U)\r
+#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2_Pos       (2U)\r
+#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3_Pos       (3U)\r
+#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4_Pos       (4U)\r
+#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5_Pos       (5U)\r
+#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6_Pos       (6U)\r
+#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7_Pos       (7U)\r
+#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8_Pos       (8U)\r
+#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9_Pos       (9U)\r
+#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10_Pos      (10U)\r
+#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11_Pos      (11U)\r
+#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12_Pos      (12U)\r
+#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13_Pos      (13U)\r
+#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14_Pos      (14U)\r
+#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15_Pos      (15U)\r
+#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16_Pos      (16U)\r
+#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17_Pos      (17U)\r
+#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18_Pos      (18U)\r
+#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19_Pos      (19U)\r
+#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20_Pos      (20U)\r
+#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21_Pos      (21U)\r
+#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22_Pos      (22U)\r
+#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23_Pos      (23U)\r
+#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24_Pos      (24U)\r
+#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25_Pos      (25U)\r
+#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26_Pos      (26U)\r
+#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27_Pos      (27U)\r
+#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28_Pos      (28U)\r
+#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29_Pos      (29U)\r
+#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30_Pos      (30U)\r
+#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31_Pos      (31U)\r
+#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F5R2 register  *******************/\r
+#define CAN_F5R2_FB0_Pos       (0U)\r
+#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1_Pos       (1U)\r
+#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2_Pos       (2U)\r
+#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3_Pos       (3U)\r
+#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4_Pos       (4U)\r
+#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5_Pos       (5U)\r
+#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6_Pos       (6U)\r
+#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7_Pos       (7U)\r
+#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8_Pos       (8U)\r
+#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9_Pos       (9U)\r
+#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10_Pos      (10U)\r
+#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11_Pos      (11U)\r
+#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12_Pos      (12U)\r
+#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13_Pos      (13U)\r
+#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14_Pos      (14U)\r
+#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15_Pos      (15U)\r
+#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16_Pos      (16U)\r
+#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17_Pos      (17U)\r
+#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18_Pos      (18U)\r
+#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19_Pos      (19U)\r
+#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20_Pos      (20U)\r
+#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21_Pos      (21U)\r
+#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22_Pos      (22U)\r
+#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23_Pos      (23U)\r
+#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24_Pos      (24U)\r
+#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25_Pos      (25U)\r
+#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26_Pos      (26U)\r
+#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27_Pos      (27U)\r
+#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28_Pos      (28U)\r
+#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29_Pos      (29U)\r
+#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30_Pos      (30U)\r
+#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31_Pos      (31U)\r
+#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F6R2 register  *******************/\r
+#define CAN_F6R2_FB0_Pos       (0U)\r
+#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1_Pos       (1U)\r
+#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2_Pos       (2U)\r
+#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3_Pos       (3U)\r
+#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4_Pos       (4U)\r
+#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5_Pos       (5U)\r
+#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6_Pos       (6U)\r
+#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7_Pos       (7U)\r
+#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8_Pos       (8U)\r
+#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9_Pos       (9U)\r
+#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10_Pos      (10U)\r
+#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11_Pos      (11U)\r
+#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12_Pos      (12U)\r
+#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13_Pos      (13U)\r
+#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14_Pos      (14U)\r
+#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15_Pos      (15U)\r
+#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16_Pos      (16U)\r
+#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17_Pos      (17U)\r
+#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18_Pos      (18U)\r
+#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19_Pos      (19U)\r
+#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20_Pos      (20U)\r
+#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21_Pos      (21U)\r
+#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22_Pos      (22U)\r
+#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23_Pos      (23U)\r
+#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24_Pos      (24U)\r
+#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25_Pos      (25U)\r
+#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26_Pos      (26U)\r
+#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27_Pos      (27U)\r
+#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28_Pos      (28U)\r
+#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29_Pos      (29U)\r
+#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30_Pos      (30U)\r
+#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31_Pos      (31U)\r
+#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F7R2 register  *******************/\r
+#define CAN_F7R2_FB0_Pos       (0U)\r
+#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1_Pos       (1U)\r
+#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2_Pos       (2U)\r
+#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3_Pos       (3U)\r
+#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4_Pos       (4U)\r
+#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5_Pos       (5U)\r
+#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6_Pos       (6U)\r
+#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7_Pos       (7U)\r
+#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8_Pos       (8U)\r
+#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9_Pos       (9U)\r
+#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10_Pos      (10U)\r
+#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11_Pos      (11U)\r
+#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12_Pos      (12U)\r
+#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13_Pos      (13U)\r
+#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14_Pos      (14U)\r
+#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15_Pos      (15U)\r
+#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16_Pos      (16U)\r
+#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17_Pos      (17U)\r
+#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18_Pos      (18U)\r
+#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19_Pos      (19U)\r
+#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20_Pos      (20U)\r
+#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21_Pos      (21U)\r
+#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22_Pos      (22U)\r
+#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23_Pos      (23U)\r
+#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24_Pos      (24U)\r
+#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25_Pos      (25U)\r
+#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26_Pos      (26U)\r
+#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27_Pos      (27U)\r
+#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28_Pos      (28U)\r
+#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29_Pos      (29U)\r
+#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30_Pos      (30U)\r
+#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31_Pos      (31U)\r
+#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F8R2 register  *******************/\r
+#define CAN_F8R2_FB0_Pos       (0U)\r
+#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1_Pos       (1U)\r
+#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2_Pos       (2U)\r
+#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3_Pos       (3U)\r
+#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4_Pos       (4U)\r
+#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5_Pos       (5U)\r
+#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6_Pos       (6U)\r
+#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7_Pos       (7U)\r
+#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8_Pos       (8U)\r
+#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9_Pos       (9U)\r
+#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10_Pos      (10U)\r
+#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11_Pos      (11U)\r
+#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12_Pos      (12U)\r
+#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13_Pos      (13U)\r
+#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14_Pos      (14U)\r
+#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15_Pos      (15U)\r
+#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16_Pos      (16U)\r
+#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17_Pos      (17U)\r
+#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18_Pos      (18U)\r
+#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19_Pos      (19U)\r
+#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20_Pos      (20U)\r
+#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21_Pos      (21U)\r
+#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22_Pos      (22U)\r
+#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23_Pos      (23U)\r
+#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24_Pos      (24U)\r
+#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25_Pos      (25U)\r
+#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26_Pos      (26U)\r
+#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27_Pos      (27U)\r
+#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28_Pos      (28U)\r
+#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29_Pos      (29U)\r
+#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30_Pos      (30U)\r
+#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31_Pos      (31U)\r
+#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F9R2 register  *******************/\r
+#define CAN_F9R2_FB0_Pos       (0U)\r
+#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                     /*!< 0x00000001 */\r
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1_Pos       (1U)\r
+#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                     /*!< 0x00000002 */\r
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2_Pos       (2U)\r
+#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                     /*!< 0x00000004 */\r
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3_Pos       (3U)\r
+#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                     /*!< 0x00000008 */\r
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4_Pos       (4U)\r
+#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                     /*!< 0x00000010 */\r
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5_Pos       (5U)\r
+#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                     /*!< 0x00000020 */\r
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6_Pos       (6U)\r
+#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                     /*!< 0x00000040 */\r
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7_Pos       (7U)\r
+#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                     /*!< 0x00000080 */\r
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8_Pos       (8U)\r
+#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                     /*!< 0x00000100 */\r
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9_Pos       (9U)\r
+#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                     /*!< 0x00000200 */\r
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10_Pos      (10U)\r
+#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                    /*!< 0x00000400 */\r
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11_Pos      (11U)\r
+#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                    /*!< 0x00000800 */\r
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12_Pos      (12U)\r
+#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                    /*!< 0x00001000 */\r
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13_Pos      (13U)\r
+#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                    /*!< 0x00002000 */\r
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14_Pos      (14U)\r
+#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                    /*!< 0x00004000 */\r
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15_Pos      (15U)\r
+#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                    /*!< 0x00008000 */\r
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16_Pos      (16U)\r
+#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                    /*!< 0x00010000 */\r
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17_Pos      (17U)\r
+#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                    /*!< 0x00020000 */\r
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18_Pos      (18U)\r
+#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                    /*!< 0x00040000 */\r
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19_Pos      (19U)\r
+#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                    /*!< 0x00080000 */\r
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20_Pos      (20U)\r
+#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                    /*!< 0x00100000 */\r
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21_Pos      (21U)\r
+#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                    /*!< 0x00200000 */\r
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22_Pos      (22U)\r
+#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                    /*!< 0x00400000 */\r
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23_Pos      (23U)\r
+#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                    /*!< 0x00800000 */\r
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24_Pos      (24U)\r
+#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                    /*!< 0x01000000 */\r
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25_Pos      (25U)\r
+#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                    /*!< 0x02000000 */\r
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26_Pos      (26U)\r
+#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                    /*!< 0x04000000 */\r
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27_Pos      (27U)\r
+#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                    /*!< 0x08000000 */\r
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28_Pos      (28U)\r
+#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                    /*!< 0x10000000 */\r
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29_Pos      (29U)\r
+#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                    /*!< 0x20000000 */\r
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30_Pos      (30U)\r
+#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                    /*!< 0x40000000 */\r
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31_Pos      (31U)\r
+#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                    /*!< 0x80000000 */\r
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F10R2 register  ******************/\r
+#define CAN_F10R2_FB0_Pos      (0U)\r
+#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1_Pos      (1U)\r
+#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2_Pos      (2U)\r
+#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3_Pos      (3U)\r
+#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4_Pos      (4U)\r
+#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5_Pos      (5U)\r
+#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6_Pos      (6U)\r
+#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7_Pos      (7U)\r
+#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8_Pos      (8U)\r
+#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9_Pos      (9U)\r
+#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10_Pos     (10U)\r
+#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11_Pos     (11U)\r
+#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12_Pos     (12U)\r
+#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13_Pos     (13U)\r
+#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14_Pos     (14U)\r
+#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15_Pos     (15U)\r
+#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16_Pos     (16U)\r
+#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17_Pos     (17U)\r
+#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18_Pos     (18U)\r
+#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19_Pos     (19U)\r
+#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20_Pos     (20U)\r
+#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21_Pos     (21U)\r
+#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22_Pos     (22U)\r
+#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23_Pos     (23U)\r
+#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24_Pos     (24U)\r
+#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25_Pos     (25U)\r
+#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26_Pos     (26U)\r
+#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27_Pos     (27U)\r
+#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28_Pos     (28U)\r
+#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29_Pos     (29U)\r
+#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30_Pos     (30U)\r
+#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31_Pos     (31U)\r
+#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F11R2 register  ******************/\r
+#define CAN_F11R2_FB0_Pos      (0U)\r
+#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1_Pos      (1U)\r
+#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2_Pos      (2U)\r
+#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3_Pos      (3U)\r
+#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4_Pos      (4U)\r
+#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5_Pos      (5U)\r
+#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6_Pos      (6U)\r
+#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7_Pos      (7U)\r
+#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8_Pos      (8U)\r
+#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9_Pos      (9U)\r
+#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10_Pos     (10U)\r
+#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11_Pos     (11U)\r
+#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12_Pos     (12U)\r
+#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13_Pos     (13U)\r
+#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14_Pos     (14U)\r
+#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15_Pos     (15U)\r
+#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16_Pos     (16U)\r
+#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17_Pos     (17U)\r
+#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18_Pos     (18U)\r
+#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19_Pos     (19U)\r
+#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20_Pos     (20U)\r
+#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21_Pos     (21U)\r
+#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22_Pos     (22U)\r
+#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23_Pos     (23U)\r
+#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24_Pos     (24U)\r
+#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25_Pos     (25U)\r
+#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26_Pos     (26U)\r
+#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27_Pos     (27U)\r
+#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28_Pos     (28U)\r
+#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29_Pos     (29U)\r
+#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30_Pos     (30U)\r
+#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31_Pos     (31U)\r
+#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F12R2 register  ******************/\r
+#define CAN_F12R2_FB0_Pos      (0U)\r
+#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1_Pos      (1U)\r
+#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2_Pos      (2U)\r
+#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3_Pos      (3U)\r
+#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4_Pos      (4U)\r
+#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5_Pos      (5U)\r
+#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6_Pos      (6U)\r
+#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7_Pos      (7U)\r
+#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8_Pos      (8U)\r
+#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9_Pos      (9U)\r
+#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10_Pos     (10U)\r
+#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11_Pos     (11U)\r
+#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12_Pos     (12U)\r
+#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13_Pos     (13U)\r
+#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14_Pos     (14U)\r
+#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15_Pos     (15U)\r
+#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16_Pos     (16U)\r
+#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17_Pos     (17U)\r
+#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18_Pos     (18U)\r
+#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19_Pos     (19U)\r
+#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20_Pos     (20U)\r
+#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21_Pos     (21U)\r
+#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22_Pos     (22U)\r
+#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23_Pos     (23U)\r
+#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24_Pos     (24U)\r
+#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25_Pos     (25U)\r
+#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26_Pos     (26U)\r
+#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27_Pos     (27U)\r
+#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28_Pos     (28U)\r
+#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29_Pos     (29U)\r
+#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30_Pos     (30U)\r
+#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31_Pos     (31U)\r
+#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F13R2 register  ******************/\r
+#define CAN_F13R2_FB0_Pos      (0U)\r
+#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                    /*!< 0x00000001 */\r
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1_Pos      (1U)\r
+#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                    /*!< 0x00000002 */\r
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2_Pos      (2U)\r
+#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                    /*!< 0x00000004 */\r
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3_Pos      (3U)\r
+#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                    /*!< 0x00000008 */\r
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4_Pos      (4U)\r
+#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                    /*!< 0x00000010 */\r
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5_Pos      (5U)\r
+#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                    /*!< 0x00000020 */\r
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6_Pos      (6U)\r
+#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                    /*!< 0x00000040 */\r
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7_Pos      (7U)\r
+#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                    /*!< 0x00000080 */\r
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8_Pos      (8U)\r
+#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                    /*!< 0x00000100 */\r
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9_Pos      (9U)\r
+#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                    /*!< 0x00000200 */\r
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10_Pos     (10U)\r
+#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                   /*!< 0x00000400 */\r
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11_Pos     (11U)\r
+#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                   /*!< 0x00000800 */\r
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12_Pos     (12U)\r
+#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                   /*!< 0x00001000 */\r
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13_Pos     (13U)\r
+#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                   /*!< 0x00002000 */\r
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14_Pos     (14U)\r
+#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                   /*!< 0x00004000 */\r
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15_Pos     (15U)\r
+#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                   /*!< 0x00008000 */\r
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16_Pos     (16U)\r
+#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                   /*!< 0x00010000 */\r
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17_Pos     (17U)\r
+#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                   /*!< 0x00020000 */\r
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18_Pos     (18U)\r
+#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                   /*!< 0x00040000 */\r
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19_Pos     (19U)\r
+#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                   /*!< 0x00080000 */\r
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20_Pos     (20U)\r
+#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                   /*!< 0x00100000 */\r
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21_Pos     (21U)\r
+#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                   /*!< 0x00200000 */\r
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22_Pos     (22U)\r
+#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                   /*!< 0x00400000 */\r
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23_Pos     (23U)\r
+#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                   /*!< 0x00800000 */\r
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24_Pos     (24U)\r
+#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                   /*!< 0x01000000 */\r
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25_Pos     (25U)\r
+#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                   /*!< 0x02000000 */\r
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26_Pos     (26U)\r
+#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                   /*!< 0x04000000 */\r
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27_Pos     (27U)\r
+#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                   /*!< 0x08000000 */\r
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28_Pos     (28U)\r
+#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                   /*!< 0x10000000 */\r
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29_Pos     (29U)\r
+#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                   /*!< 0x20000000 */\r
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30_Pos     (30U)\r
+#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                   /*!< 0x40000000 */\r
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31_Pos     (31U)\r
+#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                   /*!< 0x80000000 */\r
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          CRC calculation unit                              */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for CRC_DR register  *********************/\r
+#define CRC_DR_DR_Pos            (0U)\r
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */\r
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */\r
+\r
+/*******************  Bit definition for CRC_IDR register  ********************/\r
+#define CRC_IDR_IDR_Pos          (0U)\r
+#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */\r
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */\r
+\r
+/********************  Bit definition for CRC_CR register  ********************/\r
+#define CRC_CR_RESET_Pos         (0U)\r
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */\r
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_POLYSIZE_Pos      (3U)\r
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */\r
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */\r
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */\r
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */\r
+#define CRC_CR_REV_IN_Pos        (5U)\r
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */\r
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */\r
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */\r
+#define CRC_CR_REV_OUT_Pos       (7U)\r
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */\r
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/*******************  Bit definition for CRC_INIT register  *******************/\r
+#define CRC_INIT_INIT_Pos        (0U)\r
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */\r
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */\r
+\r
+/*******************  Bit definition for CRC_POL register  ********************/\r
+#define CRC_POL_POL_Pos          (0U)\r
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */\r
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      Digital to Analog Converter                           */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)\r
+ */\r
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */\r
+\r
+/********************  Bit definition for DAC_CR register  ********************/\r
+#define DAC_CR_EN1_Pos              (0U)\r
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */\r
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\r
+#define DAC_CR_TEN1_Pos             (2U)\r
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000004 */\r
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1_Pos            (3U)\r
+#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000038 */\r
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */\r
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */\r
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */\r
+\r
+#define DAC_CR_WAVE1_Pos            (6U)\r
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */\r
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */\r
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */\r
+\r
+#define DAC_CR_MAMP1_Pos            (8U)\r
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */\r
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */\r
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */\r
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */\r
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */\r
+\r
+#define DAC_CR_DMAEN1_Pos           (12U)\r
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */\r
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1_Pos        (13U)\r
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */\r
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/\r
+#define DAC_CR_CEN1_Pos             (14U)\r
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */\r
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/\r
+\r
+#define DAC_CR_EN2_Pos              (16U)\r
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */\r
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\r
+#define DAC_CR_TEN2_Pos             (18U)\r
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00040000 */\r
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2_Pos            (19U)\r
+#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                /*!< 0x00380000 */\r
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */\r
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */\r
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */\r
+\r
+#define DAC_CR_WAVE2_Pos            (22U)\r
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */\r
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */\r
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */\r
+\r
+#define DAC_CR_MAMP2_Pos            (24U)\r
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */\r
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */\r
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */\r
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */\r
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */\r
+\r
+#define DAC_CR_DMAEN2_Pos           (28U)\r
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */\r
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\r
+#define DAC_CR_DMAUDRIE2_Pos        (29U)\r
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */\r
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/\r
+#define DAC_CR_CEN2_Pos             (30U)\r
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */\r
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/\r
+\r
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\r
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */\r
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\r
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */\r
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\r
+\r
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\r
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */\r
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\r
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8R1 register  ******************/\r
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\r
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */\r
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\r
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */\r
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\r
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8R2 register  ******************/\r
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\r
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */\r
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12RD register  ******************/\r
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\r
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */\r
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\r
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */\r
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12LD register  ******************/\r
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\r
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\r
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */\r
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8RD register  ******************/\r
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\r
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */\r
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\r
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */\r
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/*******************  Bit definition for DAC_DOR1 register  *******************/\r
+#define DAC_DOR1_DACC1DOR_Pos       (0U)\r
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */\r
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\r
+\r
+/*******************  Bit definition for DAC_DOR2 register  *******************/\r
+#define DAC_DOR2_DACC2DOR_Pos       (0U)\r
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */\r
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\r
+\r
+/********************  Bit definition for DAC_SR register  ********************/\r
+#define DAC_SR_DMAUDR1_Pos          (13U)\r
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */\r
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_CAL_FLAG1_Pos        (14U)\r
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */\r
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */\r
+#define DAC_SR_BWST1_Pos            (15U)\r
+#define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */\r
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */\r
+\r
+#define DAC_SR_DMAUDR2_Pos          (29U)\r
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */\r
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\r
+#define DAC_SR_CAL_FLAG2_Pos        (30U)\r
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */\r
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */\r
+#define DAC_SR_BWST2_Pos            (31U)\r
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */\r
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */\r
+\r
+/*******************  Bit definition for DAC_CCR register  ********************/\r
+#define DAC_CCR_OTRIM1_Pos          (0U)\r
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */\r
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */\r
+#define DAC_CCR_OTRIM2_Pos          (16U)\r
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */\r
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */\r
+\r
+/*******************  Bit definition for DAC_MCR register  *******************/\r
+#define DAC_MCR_MODE1_Pos           (0U)\r
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */\r
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */\r
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */\r
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */\r
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */\r
+\r
+#define DAC_MCR_MODE2_Pos           (16U)\r
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */\r
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */\r
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */\r
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */\r
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */\r
+\r
+/******************  Bit definition for DAC_SHSR1 register  ******************/\r
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)\r
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */\r
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */\r
+\r
+/******************  Bit definition for DAC_SHSR2 register  ******************/\r
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)\r
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */\r
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */\r
+\r
+/******************  Bit definition for DAC_SHHR register  ******************/\r
+#define DAC_SHHR_THOLD1_Pos         (0U)\r
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */\r
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */\r
+#define DAC_SHHR_THOLD2_Pos         (16U)\r
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */\r
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */\r
+\r
+/******************  Bit definition for DAC_SHRR register  ******************/\r
+#define DAC_SHRR_TREFRESH1_Pos      (0U)\r
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */\r
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */\r
+#define DAC_SHRR_TREFRESH2_Pos      (16U)\r
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */\r
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                 Digital Filter for Sigma Delta Modulators                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/****************   DFSDM channel configuration registers  ********************/\r
+\r
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\r
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\r
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */\r
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\r
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\r
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */\r
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\r
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\r
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\r
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\r
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */\r
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\r
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x00008000 */\r
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x00004000 */\r
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\r
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */\r
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\r
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00002000 */\r
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00001000 */\r
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\r
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */\r
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\r
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\r
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */\r
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\r
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\r
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */\r
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\r
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */\r
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\r
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */\r
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x00000008 */\r
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x00000004 */\r
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)\r
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */\r
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\r
+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000002 */\r
+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000001 */\r
+\r
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\r
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\r
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\r
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\r
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */\r
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\r
+\r
+/****************  Bit definition for DFSDM_CHAWSCDR register *****************/\r
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\r
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */\r
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\r
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00800000 */\r
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00400000 */\r
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\r
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */\r
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\r
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\r
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */\r
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\r
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\r
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */\r
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\r
+\r
+/****************  Bit definition for DFSDM_CHWDATR register *******************/\r
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)\r
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */\r
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\r
+\r
+/****************  Bit definition for DFSDM_CHDATINR register *****************/\r
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\r
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\r
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\r
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\r
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\r
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\r
+\r
+/************************   DFSDM module registers  ****************************/\r
+\r
+/*****************  Bit definition for DFSDM_FLTCR1 register *******************/\r
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\r
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */\r
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\r
+#define DFSDM_FLTCR1_FAST_Pos           (29U)\r
+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */\r
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\r
+#define DFSDM_FLTCR1_RCH_Pos            (24U)\r
+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */\r
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\r
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\r
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */\r
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\r
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\r
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */\r
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\r
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)\r
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */\r
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\r
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\r
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */\r
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\r
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\r
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */\r
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\r
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00004000 */\r
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00002000 */\r
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\r
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000700 */\r
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */\r
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */\r
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */\r
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */\r
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\r
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */\r
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\r
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\r
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */\r
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\r
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\r
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */\r
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\r
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\r
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */\r
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\r
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)\r
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */\r
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\r
+\r
+/*****************  Bit definition for DFSDM_FLTCR2 register *******************/\r
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\r
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */\r
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\r
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)\r
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */\r
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\r
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\r
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */\r
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\r
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\r
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */\r
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\r
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\r
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */\r
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\r
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\r
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */\r
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\r
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */\r
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\r
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */\r
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\r
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\r
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */\r
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\r
+\r
+/*****************  Bit definition for DFSDM_FLTISR register *******************/\r
+#define DFSDM_FLTISR_SCDF_Pos           (24U)\r
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */\r
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\r
+#define DFSDM_FLTISR_CKABF_Pos          (16U)\r
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */\r
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\r
+#define DFSDM_FLTISR_RCIP_Pos           (14U)\r
+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */\r
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\r
+#define DFSDM_FLTISR_JCIP_Pos           (13U)\r
+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */\r
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\r
+#define DFSDM_FLTISR_AWDF_Pos           (4U)\r
+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */\r
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\r
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)\r
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */\r
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\r
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)\r
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */\r
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\r
+#define DFSDM_FLTISR_REOCF_Pos          (1U)\r
+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */\r
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\r
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)\r
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */\r
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\r
+\r
+/*****************  Bit definition for DFSDM_FLTICR register *******************/\r
+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)\r
+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */\r
+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCDF[7:0] Clear the short circuit detector flag */\r
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\r
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */\r
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\r
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\r
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */\r
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\r
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\r
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */\r
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\r
+\r
+/****************  Bit definition for DFSDM_FLTJCHGR register ******************/\r
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\r
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */\r
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\r
+\r
+/*****************  Bit definition for DFSDM_FLTFCR register *******************/\r
+#define DFSDM_FLTFCR_FORD_Pos           (29U)\r
+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */\r
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\r
+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x80000000 */\r
+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x40000000 */\r
+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x20000000 */\r
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)\r
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */\r
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\r
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)\r
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */\r
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\r
+\r
+/***************  Bit definition for DFSDM_FLTJDATAR register *****************/\r
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\r
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\r
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\r
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\r
+\r
+/***************  Bit definition for DFSDM_FLTRDATAR register *****************/\r
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\r
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\r
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\r
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */\r
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\r
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\r
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\r
+\r
+/***************  Bit definition for DFSDM_FLTAWHTR register ******************/\r
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\r
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\r
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\r
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */\r
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\r
+\r
+/***************  Bit definition for DFSDM_FLTAWLTR register ******************/\r
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\r
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */\r
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\r
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */\r
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\r
+\r
+/***************  Bit definition for DFSDM_FLTAWSR register *******************/\r
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\r
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */\r
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\r
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\r
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */\r
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\r
+\r
+/***************  Bit definition for DFSDM_FLTAWCFR register ******************/\r
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\r
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\r
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\r
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\r
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\r
+\r
+/***************  Bit definition for DFSDM_FLTEXMAX register ******************/\r
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\r
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\r
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\r
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */\r
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\r
+\r
+/***************  Bit definition for DFSDM_FLTEXMIN register ******************/\r
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\r
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\r
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\r
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */\r
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\r
+\r
+/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/\r
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\r
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\r
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                           DMA Controller (DMA)                             */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for DMA_ISR register  ********************/\r
+#define DMA_ISR_GIF1_Pos       (0U)\r
+#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */\r
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */\r
+#define DMA_ISR_TCIF1_Pos      (1U)\r
+#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */\r
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */\r
+#define DMA_ISR_HTIF1_Pos      (2U)\r
+#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */\r
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */\r
+#define DMA_ISR_TEIF1_Pos      (3U)\r
+#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */\r
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */\r
+#define DMA_ISR_GIF2_Pos       (4U)\r
+#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */\r
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */\r
+#define DMA_ISR_TCIF2_Pos      (5U)\r
+#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */\r
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */\r
+#define DMA_ISR_HTIF2_Pos      (6U)\r
+#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */\r
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */\r
+#define DMA_ISR_TEIF2_Pos      (7U)\r
+#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */\r
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */\r
+#define DMA_ISR_GIF3_Pos       (8U)\r
+#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */\r
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */\r
+#define DMA_ISR_TCIF3_Pos      (9U)\r
+#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */\r
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */\r
+#define DMA_ISR_HTIF3_Pos      (10U)\r
+#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */\r
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */\r
+#define DMA_ISR_TEIF3_Pos      (11U)\r
+#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */\r
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */\r
+#define DMA_ISR_GIF4_Pos       (12U)\r
+#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */\r
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */\r
+#define DMA_ISR_TCIF4_Pos      (13U)\r
+#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */\r
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */\r
+#define DMA_ISR_HTIF4_Pos      (14U)\r
+#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */\r
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */\r
+#define DMA_ISR_TEIF4_Pos      (15U)\r
+#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */\r
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */\r
+#define DMA_ISR_GIF5_Pos       (16U)\r
+#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */\r
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */\r
+#define DMA_ISR_TCIF5_Pos      (17U)\r
+#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */\r
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */\r
+#define DMA_ISR_HTIF5_Pos      (18U)\r
+#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */\r
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */\r
+#define DMA_ISR_TEIF5_Pos      (19U)\r
+#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */\r
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */\r
+#define DMA_ISR_GIF6_Pos       (20U)\r
+#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */\r
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */\r
+#define DMA_ISR_TCIF6_Pos      (21U)\r
+#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */\r
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */\r
+#define DMA_ISR_HTIF6_Pos      (22U)\r
+#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */\r
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */\r
+#define DMA_ISR_TEIF6_Pos      (23U)\r
+#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */\r
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */\r
+#define DMA_ISR_GIF7_Pos       (24U)\r
+#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */\r
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */\r
+#define DMA_ISR_TCIF7_Pos      (25U)\r
+#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */\r
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */\r
+#define DMA_ISR_HTIF7_Pos      (26U)\r
+#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */\r
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */\r
+#define DMA_ISR_TEIF7_Pos      (27U)\r
+#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */\r
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */\r
+\r
+/*******************  Bit definition for DMA_IFCR register  *******************/\r
+#define DMA_IFCR_CGIF1_Pos     (0U)\r
+#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */\r
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */\r
+#define DMA_IFCR_CTCIF1_Pos    (1U)\r
+#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */\r
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF1_Pos    (2U)\r
+#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */\r
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF1_Pos    (3U)\r
+#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */\r
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */\r
+#define DMA_IFCR_CGIF2_Pos     (4U)\r
+#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */\r
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF2_Pos    (5U)\r
+#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */\r
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF2_Pos    (6U)\r
+#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */\r
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF2_Pos    (7U)\r
+#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */\r
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */\r
+#define DMA_IFCR_CGIF3_Pos     (8U)\r
+#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */\r
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF3_Pos    (9U)\r
+#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */\r
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF3_Pos    (10U)\r
+#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */\r
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF3_Pos    (11U)\r
+#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */\r
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */\r
+#define DMA_IFCR_CGIF4_Pos     (12U)\r
+#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */\r
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF4_Pos    (13U)\r
+#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */\r
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF4_Pos    (14U)\r
+#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */\r
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF4_Pos    (15U)\r
+#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */\r
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */\r
+#define DMA_IFCR_CGIF5_Pos     (16U)\r
+#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */\r
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF5_Pos    (17U)\r
+#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */\r
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF5_Pos    (18U)\r
+#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */\r
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF5_Pos    (19U)\r
+#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */\r
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */\r
+#define DMA_IFCR_CGIF6_Pos     (20U)\r
+#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */\r
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF6_Pos    (21U)\r
+#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */\r
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF6_Pos    (22U)\r
+#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */\r
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF6_Pos    (23U)\r
+#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */\r
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */\r
+#define DMA_IFCR_CGIF7_Pos     (24U)\r
+#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */\r
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF7_Pos    (25U)\r
+#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */\r
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF7_Pos    (26U)\r
+#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */\r
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF7_Pos    (27U)\r
+#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */\r
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */\r
+\r
+/*******************  Bit definition for DMA_CCR register  ********************/\r
+#define DMA_CCR_EN_Pos         (0U)\r
+#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */\r
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */\r
+#define DMA_CCR_TCIE_Pos       (1U)\r
+#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */\r
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */\r
+#define DMA_CCR_HTIE_Pos       (2U)\r
+#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */\r
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */\r
+#define DMA_CCR_TEIE_Pos       (3U)\r
+#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */\r
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */\r
+#define DMA_CCR_DIR_Pos        (4U)\r
+#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */\r
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */\r
+#define DMA_CCR_CIRC_Pos       (5U)\r
+#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */\r
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */\r
+#define DMA_CCR_PINC_Pos       (6U)\r
+#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */\r
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */\r
+#define DMA_CCR_MINC_Pos       (7U)\r
+#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */\r
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */\r
+\r
+#define DMA_CCR_PSIZE_Pos      (8U)\r
+#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */\r
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */\r
+#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */\r
+#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */\r
+\r
+#define DMA_CCR_MSIZE_Pos      (10U)\r
+#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */\r
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */\r
+#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */\r
+#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */\r
+\r
+#define DMA_CCR_PL_Pos         (12U)\r
+#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */\r
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/\r
+#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */\r
+#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */\r
+\r
+#define DMA_CCR_MEM2MEM_Pos    (14U)\r
+#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */\r
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */\r
+\r
+/******************  Bit definition for DMA_CNDTR register  *******************/\r
+#define DMA_CNDTR_NDT_Pos      (0U)\r
+#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */\r
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */\r
+\r
+/******************  Bit definition for DMA_CPAR register  ********************/\r
+#define DMA_CPAR_PA_Pos        (0U)\r
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */\r
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */\r
+\r
+/******************  Bit definition for DMA_CMAR register  ********************/\r
+#define DMA_CMAR_MA_Pos        (0U)\r
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */\r
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */\r
+\r
+\r
+/*******************  Bit definition for DMA_CSELR register  *******************/\r
+#define DMA_CSELR_C1S_Pos      (0U)\r
+#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                    /*!< 0x0000000F */\r
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */\r
+#define DMA_CSELR_C2S_Pos      (4U)\r
+#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                    /*!< 0x000000F0 */\r
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */\r
+#define DMA_CSELR_C3S_Pos      (8U)\r
+#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                    /*!< 0x00000F00 */\r
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */\r
+#define DMA_CSELR_C4S_Pos      (12U)\r
+#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                    /*!< 0x0000F000 */\r
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */\r
+#define DMA_CSELR_C5S_Pos      (16U)\r
+#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                    /*!< 0x000F0000 */\r
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */\r
+#define DMA_CSELR_C6S_Pos      (20U)\r
+#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                    /*!< 0x00F00000 */\r
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */\r
+#define DMA_CSELR_C7S_Pos      (24U)\r
+#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                    /*!< 0x0F000000 */\r
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                    External Interrupt/Event Controller                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for EXTI_IMR1 register  ******************/\r
+#define EXTI_IMR1_IM0_Pos        (0U)\r
+#define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */\r
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR1_IM1_Pos        (1U)\r
+#define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */\r
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR1_IM2_Pos        (2U)\r
+#define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */\r
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR1_IM3_Pos        (3U)\r
+#define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */\r
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR1_IM4_Pos        (4U)\r
+#define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */\r
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR1_IM5_Pos        (5U)\r
+#define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */\r
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR1_IM6_Pos        (6U)\r
+#define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */\r
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR1_IM7_Pos        (7U)\r
+#define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */\r
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR1_IM8_Pos        (8U)\r
+#define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */\r
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR1_IM9_Pos        (9U)\r
+#define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */\r
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR1_IM10_Pos       (10U)\r
+#define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */\r
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR1_IM11_Pos       (11U)\r
+#define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */\r
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR1_IM12_Pos       (12U)\r
+#define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */\r
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR1_IM13_Pos       (13U)\r
+#define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */\r
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR1_IM14_Pos       (14U)\r
+#define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */\r
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR1_IM15_Pos       (15U)\r
+#define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */\r
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR1_IM16_Pos       (16U)\r
+#define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */\r
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR1_IM17_Pos       (17U)\r
+#define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */\r
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR1_IM18_Pos       (18U)\r
+#define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */\r
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR1_IM19_Pos       (19U)\r
+#define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */\r
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR1_IM20_Pos       (20U)\r
+#define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */\r
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR1_IM21_Pos       (21U)\r
+#define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */\r
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR1_IM22_Pos       (22U)\r
+#define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */\r
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR1_IM23_Pos       (23U)\r
+#define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */\r
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */\r
+#define EXTI_IMR1_IM24_Pos       (24U)\r
+#define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */\r
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */\r
+#define EXTI_IMR1_IM25_Pos       (25U)\r
+#define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */\r
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */\r
+#define EXTI_IMR1_IM26_Pos       (26U)\r
+#define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */\r
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */\r
+#define EXTI_IMR1_IM27_Pos       (27U)\r
+#define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */\r
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */\r
+#define EXTI_IMR1_IM28_Pos       (28U)\r
+#define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */\r
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */\r
+#define EXTI_IMR1_IM29_Pos       (29U)\r
+#define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */\r
+#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */\r
+#define EXTI_IMR1_IM30_Pos       (30U)\r
+#define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */\r
+#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */\r
+#define EXTI_IMR1_IM31_Pos       (31U)\r
+#define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */\r
+#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */\r
+#define EXTI_IMR1_IM_Pos         (0U)\r
+#define EXTI_IMR1_IM_Msk         (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0xFFFFFFFF */\r
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */\r
+\r
+/*******************  Bit definition for EXTI_EMR1 register  ******************/\r
+#define EXTI_EMR1_EM0_Pos        (0U)\r
+#define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */\r
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */\r
+#define EXTI_EMR1_EM1_Pos        (1U)\r
+#define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */\r
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */\r
+#define EXTI_EMR1_EM2_Pos        (2U)\r
+#define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */\r
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */\r
+#define EXTI_EMR1_EM3_Pos        (3U)\r
+#define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */\r
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */\r
+#define EXTI_EMR1_EM4_Pos        (4U)\r
+#define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */\r
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */\r
+#define EXTI_EMR1_EM5_Pos        (5U)\r
+#define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */\r
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */\r
+#define EXTI_EMR1_EM6_Pos        (6U)\r
+#define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */\r
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */\r
+#define EXTI_EMR1_EM7_Pos        (7U)\r
+#define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */\r
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */\r
+#define EXTI_EMR1_EM8_Pos        (8U)\r
+#define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */\r
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */\r
+#define EXTI_EMR1_EM9_Pos        (9U)\r
+#define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */\r
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */\r
+#define EXTI_EMR1_EM10_Pos       (10U)\r
+#define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */\r
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */\r
+#define EXTI_EMR1_EM11_Pos       (11U)\r
+#define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */\r
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */\r
+#define EXTI_EMR1_EM12_Pos       (12U)\r
+#define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */\r
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */\r
+#define EXTI_EMR1_EM13_Pos       (13U)\r
+#define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */\r
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */\r
+#define EXTI_EMR1_EM14_Pos       (14U)\r
+#define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */\r
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */\r
+#define EXTI_EMR1_EM15_Pos       (15U)\r
+#define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */\r
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */\r
+#define EXTI_EMR1_EM16_Pos       (16U)\r
+#define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */\r
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */\r
+#define EXTI_EMR1_EM17_Pos       (17U)\r
+#define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */\r
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */\r
+#define EXTI_EMR1_EM18_Pos       (18U)\r
+#define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */\r
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */\r
+#define EXTI_EMR1_EM19_Pos       (19U)\r
+#define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */\r
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */\r
+#define EXTI_EMR1_EM20_Pos       (20U)\r
+#define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */\r
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */\r
+#define EXTI_EMR1_EM21_Pos       (21U)\r
+#define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */\r
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */\r
+#define EXTI_EMR1_EM22_Pos       (22U)\r
+#define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */\r
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */\r
+#define EXTI_EMR1_EM23_Pos       (23U)\r
+#define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */\r
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */\r
+#define EXTI_EMR1_EM24_Pos       (24U)\r
+#define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */\r
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */\r
+#define EXTI_EMR1_EM25_Pos       (25U)\r
+#define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */\r
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */\r
+#define EXTI_EMR1_EM26_Pos       (26U)\r
+#define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */\r
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */\r
+#define EXTI_EMR1_EM27_Pos       (27U)\r
+#define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */\r
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */\r
+#define EXTI_EMR1_EM28_Pos       (28U)\r
+#define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */\r
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */\r
+#define EXTI_EMR1_EM29_Pos       (29U)\r
+#define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */\r
+#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */\r
+#define EXTI_EMR1_EM30_Pos       (30U)\r
+#define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */\r
+#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */\r
+#define EXTI_EMR1_EM31_Pos       (31U)\r
+#define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */\r
+#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */\r
+\r
+/******************  Bit definition for EXTI_RTSR1 register  ******************/\r
+#define EXTI_RTSR1_RT0_Pos       (0U)\r
+#define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */\r
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR1_RT1_Pos       (1U)\r
+#define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */\r
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR1_RT2_Pos       (2U)\r
+#define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */\r
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR1_RT3_Pos       (3U)\r
+#define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */\r
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR1_RT4_Pos       (4U)\r
+#define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */\r
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR1_RT5_Pos       (5U)\r
+#define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */\r
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR1_RT6_Pos       (6U)\r
+#define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */\r
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR1_RT7_Pos       (7U)\r
+#define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */\r
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR1_RT8_Pos       (8U)\r
+#define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */\r
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR1_RT9_Pos       (9U)\r
+#define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */\r
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR1_RT10_Pos      (10U)\r
+#define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */\r
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR1_RT11_Pos      (11U)\r
+#define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */\r
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR1_RT12_Pos      (12U)\r
+#define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */\r
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR1_RT13_Pos      (13U)\r
+#define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */\r
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR1_RT14_Pos      (14U)\r
+#define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */\r
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR1_RT15_Pos      (15U)\r
+#define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */\r
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR1_RT16_Pos      (16U)\r
+#define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */\r
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR1_RT18_Pos      (18U)\r
+#define EXTI_RTSR1_RT18_Msk      (0x1UL << EXTI_RTSR1_RT18_Pos)                /*!< 0x00040000 */\r
+#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR1_RT19_Pos      (19U)\r
+#define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */\r
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR1_RT20_Pos      (20U)\r
+#define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */\r
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR1_RT21_Pos      (21U)\r
+#define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */\r
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR1_RT22_Pos      (22U)\r
+#define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */\r
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\r
+\r
+/******************  Bit definition for EXTI_FTSR1 register  ******************/\r
+#define EXTI_FTSR1_FT0_Pos       (0U)\r
+#define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */\r
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR1_FT1_Pos       (1U)\r
+#define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */\r
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR1_FT2_Pos       (2U)\r
+#define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */\r
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR1_FT3_Pos       (3U)\r
+#define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */\r
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR1_FT4_Pos       (4U)\r
+#define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */\r
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR1_FT5_Pos       (5U)\r
+#define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */\r
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR1_FT6_Pos       (6U)\r
+#define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */\r
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR1_FT7_Pos       (7U)\r
+#define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */\r
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR1_FT8_Pos       (8U)\r
+#define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */\r
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR1_FT9_Pos       (9U)\r
+#define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */\r
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR1_FT10_Pos      (10U)\r
+#define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */\r
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR1_FT11_Pos      (11U)\r
+#define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */\r
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR1_FT12_Pos      (12U)\r
+#define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */\r
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR1_FT13_Pos      (13U)\r
+#define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */\r
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR1_FT14_Pos      (14U)\r
+#define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */\r
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR1_FT15_Pos      (15U)\r
+#define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */\r
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR1_FT16_Pos      (16U)\r
+#define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */\r
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR1_FT18_Pos      (18U)\r
+#define EXTI_FTSR1_FT18_Msk      (0x1UL << EXTI_FTSR1_FT18_Pos)                /*!< 0x00040000 */\r
+#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR1_FT19_Pos      (19U)\r
+#define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */\r
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR1_FT20_Pos      (20U)\r
+#define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */\r
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR1_FT21_Pos      (21U)\r
+#define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */\r
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR1_FT22_Pos      (22U)\r
+#define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */\r
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\r
+\r
+/******************  Bit definition for EXTI_SWIER1 register  *****************/\r
+#define EXTI_SWIER1_SWI0_Pos     (0U)\r
+#define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */\r
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER1_SWI1_Pos     (1U)\r
+#define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */\r
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER1_SWI2_Pos     (2U)\r
+#define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */\r
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER1_SWI3_Pos     (3U)\r
+#define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */\r
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER1_SWI4_Pos     (4U)\r
+#define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */\r
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER1_SWI5_Pos     (5U)\r
+#define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */\r
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER1_SWI6_Pos     (6U)\r
+#define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */\r
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER1_SWI7_Pos     (7U)\r
+#define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */\r
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER1_SWI8_Pos     (8U)\r
+#define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */\r
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER1_SWI9_Pos     (9U)\r
+#define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */\r
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER1_SWI10_Pos    (10U)\r
+#define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */\r
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER1_SWI11_Pos    (11U)\r
+#define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */\r
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER1_SWI12_Pos    (12U)\r
+#define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */\r
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER1_SWI13_Pos    (13U)\r
+#define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */\r
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER1_SWI14_Pos    (14U)\r
+#define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */\r
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER1_SWI15_Pos    (15U)\r
+#define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */\r
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER1_SWI16_Pos    (16U)\r
+#define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */\r
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER1_SWI18_Pos    (18U)\r
+#define EXTI_SWIER1_SWI18_Msk    (0x1UL << EXTI_SWIER1_SWI18_Pos)              /*!< 0x00040000 */\r
+#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER1_SWI19_Pos    (19U)\r
+#define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */\r
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER1_SWI20_Pos    (20U)\r
+#define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */\r
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER1_SWI21_Pos    (21U)\r
+#define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */\r
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER1_SWI22_Pos    (22U)\r
+#define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */\r
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */\r
+\r
+/*******************  Bit definition for EXTI_PR1 register  *******************/\r
+#define EXTI_PR1_PIF0_Pos        (0U)\r
+#define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */\r
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */\r
+#define EXTI_PR1_PIF1_Pos        (1U)\r
+#define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */\r
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */\r
+#define EXTI_PR1_PIF2_Pos        (2U)\r
+#define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */\r
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */\r
+#define EXTI_PR1_PIF3_Pos        (3U)\r
+#define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */\r
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */\r
+#define EXTI_PR1_PIF4_Pos        (4U)\r
+#define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */\r
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */\r
+#define EXTI_PR1_PIF5_Pos        (5U)\r
+#define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */\r
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */\r
+#define EXTI_PR1_PIF6_Pos        (6U)\r
+#define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */\r
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */\r
+#define EXTI_PR1_PIF7_Pos        (7U)\r
+#define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */\r
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */\r
+#define EXTI_PR1_PIF8_Pos        (8U)\r
+#define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */\r
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */\r
+#define EXTI_PR1_PIF9_Pos        (9U)\r
+#define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */\r
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */\r
+#define EXTI_PR1_PIF10_Pos       (10U)\r
+#define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */\r
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */\r
+#define EXTI_PR1_PIF11_Pos       (11U)\r
+#define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */\r
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */\r
+#define EXTI_PR1_PIF12_Pos       (12U)\r
+#define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */\r
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */\r
+#define EXTI_PR1_PIF13_Pos       (13U)\r
+#define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */\r
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */\r
+#define EXTI_PR1_PIF14_Pos       (14U)\r
+#define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */\r
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */\r
+#define EXTI_PR1_PIF15_Pos       (15U)\r
+#define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */\r
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */\r
+#define EXTI_PR1_PIF16_Pos       (16U)\r
+#define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */\r
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */\r
+#define EXTI_PR1_PIF18_Pos       (18U)\r
+#define EXTI_PR1_PIF18_Msk       (0x1UL << EXTI_PR1_PIF18_Pos)                 /*!< 0x00040000 */\r
+#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */\r
+#define EXTI_PR1_PIF19_Pos       (19U)\r
+#define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */\r
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */\r
+#define EXTI_PR1_PIF20_Pos       (20U)\r
+#define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */\r
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */\r
+#define EXTI_PR1_PIF21_Pos       (21U)\r
+#define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */\r
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */\r
+#define EXTI_PR1_PIF22_Pos       (22U)\r
+#define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */\r
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */\r
+\r
+/*******************  Bit definition for EXTI_IMR2 register  ******************/\r
+#define EXTI_IMR2_IM32_Pos       (0U)\r
+#define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */\r
+#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */\r
+#define EXTI_IMR2_IM33_Pos       (1U)\r
+#define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */\r
+#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */\r
+#define EXTI_IMR2_IM34_Pos       (2U)\r
+#define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */\r
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */\r
+#define EXTI_IMR2_IM35_Pos       (3U)\r
+#define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */\r
+#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */\r
+#define EXTI_IMR2_IM36_Pos       (4U)\r
+#define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */\r
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */\r
+#define EXTI_IMR2_IM37_Pos       (5U)\r
+#define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */\r
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */\r
+#define EXTI_IMR2_IM38_Pos       (6U)\r
+#define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */\r
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */\r
+#define EXTI_IMR2_IM_Pos         (0U)\r
+#define EXTI_IMR2_IM_Msk         (0x7FUL << EXTI_IMR2_IM_Pos)                  /*!< 0x0000007F */\r
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */\r
+\r
+/*******************  Bit definition for EXTI_EMR2 register  ******************/\r
+#define EXTI_EMR2_EM32_Pos       (0U)\r
+#define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */\r
+#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */\r
+#define EXTI_EMR2_EM33_Pos       (1U)\r
+#define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */\r
+#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */\r
+#define EXTI_EMR2_EM34_Pos       (2U)\r
+#define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */\r
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */\r
+#define EXTI_EMR2_EM35_Pos       (3U)\r
+#define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */\r
+#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */\r
+#define EXTI_EMR2_EM36_Pos       (4U)\r
+#define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */\r
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */\r
+#define EXTI_EMR2_EM37_Pos       (5U)\r
+#define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */\r
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */\r
+#define EXTI_EMR2_EM38_Pos       (6U)\r
+#define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */\r
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */\r
+#define EXTI_EMR2_EM_Pos         (0U)\r
+#define EXTI_EMR2_EM_Msk         (0x7FUL << EXTI_EMR2_EM_Pos)                  /*!< 0x0000007F */\r
+#define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */\r
+\r
+/******************  Bit definition for EXTI_RTSR2 register  ******************/\r
+#define EXTI_RTSR2_RT35_Pos      (3U)\r
+#define EXTI_RTSR2_RT35_Msk      (0x1UL << EXTI_RTSR2_RT35_Pos)                /*!< 0x00000008 */\r
+#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */\r
+#define EXTI_RTSR2_RT36_Pos      (4U)\r
+#define EXTI_RTSR2_RT36_Msk      (0x1UL << EXTI_RTSR2_RT36_Pos)                /*!< 0x00000010 */\r
+#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */\r
+#define EXTI_RTSR2_RT37_Pos      (5U)\r
+#define EXTI_RTSR2_RT37_Msk      (0x1UL << EXTI_RTSR2_RT37_Pos)                /*!< 0x00000020 */\r
+#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */\r
+#define EXTI_RTSR2_RT38_Pos      (6U)\r
+#define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */\r
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */\r
+\r
+/******************  Bit definition for EXTI_FTSR2 register  ******************/\r
+#define EXTI_FTSR2_FT35_Pos      (3U)\r
+#define EXTI_FTSR2_FT35_Msk      (0x1UL << EXTI_FTSR2_FT35_Pos)                /*!< 0x00000008 */\r
+#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */\r
+#define EXTI_FTSR2_FT36_Pos      (4U)\r
+#define EXTI_FTSR2_FT36_Msk      (0x1UL << EXTI_FTSR2_FT36_Pos)                /*!< 0x00000010 */\r
+#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */\r
+#define EXTI_FTSR2_FT37_Pos      (5U)\r
+#define EXTI_FTSR2_FT37_Msk      (0x1UL << EXTI_FTSR2_FT37_Pos)                /*!< 0x00000020 */\r
+#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */\r
+#define EXTI_FTSR2_FT38_Pos      (6U)\r
+#define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */\r
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */\r
+\r
+/******************  Bit definition for EXTI_SWIER2 register  *****************/\r
+#define EXTI_SWIER2_SWI35_Pos    (3U)\r
+#define EXTI_SWIER2_SWI35_Msk    (0x1UL << EXTI_SWIER2_SWI35_Pos)              /*!< 0x00000008 */\r
+#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */\r
+#define EXTI_SWIER2_SWI36_Pos    (4U)\r
+#define EXTI_SWIER2_SWI36_Msk    (0x1UL << EXTI_SWIER2_SWI36_Pos)              /*!< 0x00000010 */\r
+#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */\r
+#define EXTI_SWIER2_SWI37_Pos    (5U)\r
+#define EXTI_SWIER2_SWI37_Msk    (0x1UL << EXTI_SWIER2_SWI37_Pos)              /*!< 0x00000020 */\r
+#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */\r
+#define EXTI_SWIER2_SWI38_Pos    (6U)\r
+#define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */\r
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */\r
+\r
+/*******************  Bit definition for EXTI_PR2 register  *******************/\r
+#define EXTI_PR2_PIF35_Pos       (3U)\r
+#define EXTI_PR2_PIF35_Msk       (0x1UL << EXTI_PR2_PIF35_Pos)                 /*!< 0x00000008 */\r
+#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */\r
+#define EXTI_PR2_PIF36_Pos       (4U)\r
+#define EXTI_PR2_PIF36_Msk       (0x1UL << EXTI_PR2_PIF36_Pos)                 /*!< 0x00000010 */\r
+#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */\r
+#define EXTI_PR2_PIF37_Pos       (5U)\r
+#define EXTI_PR2_PIF37_Msk       (0x1UL << EXTI_PR2_PIF37_Pos)                 /*!< 0x00000020 */\r
+#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */\r
+#define EXTI_PR2_PIF38_Pos       (6U)\r
+#define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */\r
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    FLASH                                   */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bits definition for FLASH_ACR register  *****************/\r
+#define FLASH_ACR_LATENCY_Pos             (0U)\r
+#define FLASH_ACR_LATENCY_Msk             (0x7UL << FLASH_ACR_LATENCY_Pos)     /*!< 0x00000007 */\r
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk\r
+#define FLASH_ACR_LATENCY_0WS             (0x00000000UL)\r
+#define FLASH_ACR_LATENCY_1WS             (0x00000001UL)\r
+#define FLASH_ACR_LATENCY_2WS             (0x00000002UL)\r
+#define FLASH_ACR_LATENCY_3WS             (0x00000003UL)\r
+#define FLASH_ACR_LATENCY_4WS             (0x00000004UL)\r
+#define FLASH_ACR_PRFTEN_Pos              (8U)\r
+#define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */\r
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk\r
+#define FLASH_ACR_ICEN_Pos                (9U)\r
+#define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */\r
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk\r
+#define FLASH_ACR_DCEN_Pos                (10U)\r
+#define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */\r
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk\r
+#define FLASH_ACR_ICRST_Pos               (11U)\r
+#define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */\r
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk\r
+#define FLASH_ACR_DCRST_Pos               (12U)\r
+#define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */\r
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk\r
+#define FLASH_ACR_RUN_PD_Pos              (13U)\r
+#define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */\r
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */\r
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)\r
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */\r
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */\r
+\r
+/*******************  Bits definition for FLASH_SR register  ******************/\r
+#define FLASH_SR_EOP_Pos                  (0U)\r
+#define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */\r
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk\r
+#define FLASH_SR_OPERR_Pos                (1U)\r
+#define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */\r
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk\r
+#define FLASH_SR_PROGERR_Pos              (3U)\r
+#define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */\r
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk\r
+#define FLASH_SR_WRPERR_Pos               (4U)\r
+#define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */\r
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk\r
+#define FLASH_SR_PGAERR_Pos               (5U)\r
+#define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */\r
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk\r
+#define FLASH_SR_SIZERR_Pos               (6U)\r
+#define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */\r
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk\r
+#define FLASH_SR_PGSERR_Pos               (7U)\r
+#define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */\r
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk\r
+#define FLASH_SR_MISERR_Pos               (8U)\r
+#define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */\r
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk\r
+#define FLASH_SR_FASTERR_Pos              (9U)\r
+#define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */\r
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk\r
+#define FLASH_SR_RDERR_Pos                (14U)\r
+#define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */\r
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk\r
+#define FLASH_SR_OPTVERR_Pos              (15U)\r
+#define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */\r
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk\r
+#define FLASH_SR_BSY_Pos                  (16U)\r
+#define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */\r
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk\r
+\r
+/*******************  Bits definition for FLASH_CR register  ******************/\r
+#define FLASH_CR_PG_Pos                   (0U)\r
+#define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */\r
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk\r
+#define FLASH_CR_PER_Pos                  (1U)\r
+#define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */\r
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk\r
+#define FLASH_CR_MER1_Pos                 (2U)\r
+#define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */\r
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk\r
+#define FLASH_CR_PNB_Pos                  (3U)\r
+#define FLASH_CR_PNB_Msk                  (0xFFUL << FLASH_CR_PNB_Pos)         /*!< 0x000007F8 */\r
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk\r
+#define FLASH_CR_BKER_Pos                 (11U)\r
+#define FLASH_CR_BKER_Msk                 (0x1UL << FLASH_CR_BKER_Pos)         /*!< 0x00000800 */\r
+#define FLASH_CR_BKER                     FLASH_CR_BKER_Msk\r
+#define FLASH_CR_MER2_Pos                 (15U)\r
+#define FLASH_CR_MER2_Msk                 (0x1UL << FLASH_CR_MER2_Pos)         /*!< 0x00008000 */\r
+#define FLASH_CR_MER2                     FLASH_CR_MER2_Msk\r
+#define FLASH_CR_STRT_Pos                 (16U)\r
+#define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */\r
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk\r
+#define FLASH_CR_OPTSTRT_Pos              (17U)\r
+#define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */\r
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk\r
+#define FLASH_CR_FSTPG_Pos                (18U)\r
+#define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */\r
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk\r
+#define FLASH_CR_EOPIE_Pos                (24U)\r
+#define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */\r
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk\r
+#define FLASH_CR_ERRIE_Pos                (25U)\r
+#define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */\r
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk\r
+#define FLASH_CR_RDERRIE_Pos              (26U)\r
+#define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */\r
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk\r
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)\r
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */\r
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk\r
+#define FLASH_CR_OPTLOCK_Pos              (30U)\r
+#define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */\r
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk\r
+#define FLASH_CR_LOCK_Pos                 (31U)\r
+#define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */\r
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk\r
+\r
+/*******************  Bits definition for FLASH_ECCR register  ***************/\r
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)\r
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */\r
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk\r
+#define FLASH_ECCR_BK_ECC_Pos             (19U)\r
+#define FLASH_ECCR_BK_ECC_Msk             (0x1UL << FLASH_ECCR_BK_ECC_Pos)     /*!< 0x00080000 */\r
+#define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk\r
+#define FLASH_ECCR_SYSF_ECC_Pos           (20U)\r
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00100000 */\r
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk\r
+#define FLASH_ECCR_ECCIE_Pos              (24U)\r
+#define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */\r
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk\r
+#define FLASH_ECCR_ECCC_Pos               (30U)\r
+#define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */\r
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk\r
+#define FLASH_ECCR_ECCD_Pos               (31U)\r
+#define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */\r
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk\r
+\r
+/*******************  Bits definition for FLASH_OPTR register  ***************/\r
+#define FLASH_OPTR_RDP_Pos                (0U)\r
+#define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */\r
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk\r
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)\r
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */\r
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk\r
+#define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */\r
+#define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */\r
+#define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */\r
+#define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */\r
+#define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */\r
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)\r
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */\r
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk\r
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)\r
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */\r
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk\r
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)\r
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */\r
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk\r
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)\r
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */\r
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk\r
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)\r
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */\r
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk\r
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)\r
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */\r
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk\r
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)\r
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */\r
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk\r
+#define FLASH_OPTR_BFB2_Pos               (20U)\r
+#define FLASH_OPTR_BFB2_Msk               (0x1UL << FLASH_OPTR_BFB2_Pos)       /*!< 0x00100000 */\r
+#define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk\r
+#define FLASH_OPTR_DUALBANK_Pos           (21U)\r
+#define FLASH_OPTR_DUALBANK_Msk           (0x1UL << FLASH_OPTR_DUALBANK_Pos)   /*!< 0x00200000 */\r
+#define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk\r
+#define FLASH_OPTR_nBOOT1_Pos             (23U)\r
+#define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */\r
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk\r
+#define FLASH_OPTR_SRAM2_PE_Pos           (24U)\r
+#define FLASH_OPTR_SRAM2_PE_Msk           (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)   /*!< 0x01000000 */\r
+#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk\r
+#define FLASH_OPTR_SRAM2_RST_Pos          (25U)\r
+#define FLASH_OPTR_SRAM2_RST_Msk          (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)  /*!< 0x02000000 */\r
+#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk\r
+\r
+/******************  Bits definition for FLASH_PCROP1SR register  **********/\r
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)\r
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk\r
+\r
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/\r
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)\r
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk\r
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)\r
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */\r
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk\r
+\r
+/******************  Bits definition for FLASH_WRP1AR register  ***************/\r
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)\r
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */\r
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk\r
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)\r
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos)  /*!< 0x00FF0000 */\r
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk\r
+\r
+/******************  Bits definition for FLASH_WRPB1R register  ***************/\r
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)\r
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */\r
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk\r
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)\r
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos)  /*!< 0x00FF0000 */\r
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk\r
+\r
+/******************  Bits definition for FLASH_PCROP2SR register  **********/\r
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)\r
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk\r
+\r
+/******************  Bits definition for FLASH_PCROP2ER register  ***********/\r
+#define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)\r
+#define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFUL << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk\r
+\r
+/******************  Bits definition for FLASH_WRP2AR register  ***************/\r
+#define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)\r
+#define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFUL << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */\r
+#define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk\r
+#define FLASH_WRP2AR_WRP2A_END_Pos        (16U)\r
+#define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFUL << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */\r
+#define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk\r
+\r
+/******************  Bits definition for FLASH_WRP2BR register  ***************/\r
+#define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)\r
+#define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFUL << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */\r
+#define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk\r
+#define FLASH_WRP2BR_WRP2B_END_Pos        (16U)\r
+#define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFUL << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */\r
+#define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          Flexible Memory Controller                        */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for FMC_BCR1 register  *******************/\r
+#define FMC_BCR1_CCLKEN_Pos        (20U)\r
+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\r
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */\r
+\r
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/\r
+#define FMC_BCRx_MBKEN_Pos         (0U)\r
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */\r
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r
+#define FMC_BCRx_MUXEN_Pos         (1U)\r
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */\r
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r
+\r
+#define FMC_BCRx_MTYP_Pos          (2U)\r
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */\r
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */\r
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */\r
+\r
+#define FMC_BCRx_MWID_Pos          (4U)\r
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */\r
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */\r
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */\r
+\r
+#define FMC_BCRx_FACCEN_Pos        (6U)\r
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */\r
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */\r
+#define FMC_BCRx_BURSTEN_Pos       (8U)\r
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */\r
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */\r
+#define FMC_BCRx_WAITPOL_Pos       (9U)\r
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */\r
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r
+#define FMC_BCRx_WAITCFG_Pos       (11U)\r
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */\r
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */\r
+#define FMC_BCRx_WREN_Pos          (12U)\r
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */\r
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */\r
+#define FMC_BCRx_WAITEN_Pos        (13U)\r
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */\r
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */\r
+#define FMC_BCRx_EXTMOD_Pos        (14U)\r
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */\r
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */\r
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)\r
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */\r
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r
+\r
+#define FMC_BCRx_CPSIZE_Pos        (16U)\r
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */\r
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */\r
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */\r
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */\r
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */\r
+\r
+#define FMC_BCRx_CBURSTRW_Pos      (19U)\r
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */\r
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */\r
+\r
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/\r
+#define FMC_BTRx_ADDSET_Pos        (0U)\r
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */\r
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */\r
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */\r
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */\r
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */\r
+\r
+#define FMC_BTRx_ADDHLD_Pos        (4U)\r
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */\r
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\r
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */\r
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */\r
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */\r
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */\r
+\r
+#define FMC_BTRx_DATAST_Pos        (8U)\r
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */\r
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */\r
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */\r
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */\r
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */\r
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */\r
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */\r
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */\r
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */\r
+\r
+#define FMC_BTRx_BUSTURN_Pos       (16U)\r
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */\r
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */\r
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */\r
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */\r
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */\r
+\r
+#define FMC_BTRx_CLKDIV_Pos        (20U)\r
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */\r
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */\r
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */\r
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */\r
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */\r
+\r
+#define FMC_BTRx_DATLAT_Pos        (24U)\r
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */\r
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */\r
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */\r
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */\r
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */\r
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */\r
+\r
+#define FMC_BTRx_ACCMOD_Pos        (28U)\r
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */\r
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */\r
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */\r
+\r
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/\r
+#define FMC_BWTRx_ADDSET_Pos       (0U)\r
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */\r
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */\r
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */\r
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */\r
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */\r
+\r
+#define FMC_BWTRx_ADDHLD_Pos       (4U)\r
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */\r
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */\r
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */\r
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */\r
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */\r
+\r
+#define FMC_BWTRx_DATAST_Pos       (8U)\r
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */\r
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */\r
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */\r
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */\r
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */\r
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */\r
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */\r
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */\r
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */\r
+\r
+#define FMC_BWTRx_BUSTURN_Pos      (16U)\r
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */\r
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */\r
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */\r
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */\r
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */\r
+\r
+#define FMC_BWTRx_ACCMOD_Pos       (28U)\r
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */\r
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */\r
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */\r
+\r
+/******************  Bit definition for FMC_PCR register  ********************/\r
+#define FMC_PCR_PWAITEN_Pos        (1U)\r
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */\r
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */\r
+#define FMC_PCR_PBKEN_Pos          (2U)\r
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */\r
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */\r
+#define FMC_PCR_PTYP_Pos           (3U)\r
+#define FMC_PCR_PTYP_Msk           (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */\r
+#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */\r
+\r
+#define FMC_PCR_PWID_Pos           (4U)\r
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */\r
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */\r
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */\r
+\r
+#define FMC_PCR_ECCEN_Pos          (6U)\r
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */\r
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */\r
+\r
+#define FMC_PCR_TCLR_Pos           (9U)\r
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */\r
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */\r
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */\r
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */\r
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */\r
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */\r
+\r
+#define FMC_PCR_TAR_Pos            (13U)\r
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */\r
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */\r
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */\r
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */\r
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */\r
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */\r
+\r
+#define FMC_PCR_ECCPS_Pos          (17U)\r
+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */\r
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */\r
+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */\r
+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */\r
+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */\r
+\r
+/*******************  Bit definition for FMC_SR register  ********************/\r
+#define FMC_SR_IRS_Pos             (0U)\r
+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */\r
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */\r
+#define FMC_SR_ILS_Pos             (1U)\r
+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */\r
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */\r
+#define FMC_SR_IFS_Pos             (2U)\r
+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */\r
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */\r
+#define FMC_SR_IREN_Pos            (3U)\r
+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */\r
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */\r
+#define FMC_SR_ILEN_Pos            (4U)\r
+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */\r
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */\r
+#define FMC_SR_IFEN_Pos            (5U)\r
+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */\r
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR_FEMPT_Pos           (6U)\r
+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */\r
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */\r
+\r
+/******************  Bit definition for FMC_PMEM register  ******************/\r
+#define FMC_PMEM_MEMSET_Pos        (0U)\r
+#define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */\r
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */\r
+#define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */\r
+#define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */\r
+#define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */\r
+#define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */\r
+#define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */\r
+#define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */\r
+#define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */\r
+#define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */\r
+\r
+#define FMC_PMEM_MEMWAIT_Pos       (8U)\r
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */\r
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */\r
+#define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */\r
+#define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */\r
+#define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */\r
+#define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */\r
+#define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */\r
+#define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */\r
+#define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */\r
+#define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */\r
+\r
+#define FMC_PMEM_MEMHOLD_Pos       (16U)\r
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */\r
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */\r
+#define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */\r
+#define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */\r
+#define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */\r
+#define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */\r
+#define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */\r
+#define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */\r
+#define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */\r
+#define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */\r
+\r
+#define FMC_PMEM_MEMHIZ_Pos        (24U)\r
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */\r
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */\r
+#define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */\r
+#define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */\r
+#define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */\r
+#define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */\r
+#define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */\r
+#define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */\r
+#define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */\r
+#define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */\r
+\r
+/******************  Bit definition for FMC_PATT register  *******************/\r
+#define FMC_PATT_ATTSET_Pos        (0U)\r
+#define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */\r
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */\r
+#define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */\r
+#define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */\r
+#define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */\r
+#define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */\r
+#define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */\r
+#define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */\r
+#define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */\r
+#define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */\r
+\r
+#define FMC_PATT_ATTWAIT_Pos       (8U)\r
+#define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */\r
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */\r
+#define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */\r
+#define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */\r
+#define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */\r
+#define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */\r
+#define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */\r
+#define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */\r
+#define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */\r
+#define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */\r
+\r
+#define FMC_PATT_ATTHOLD_Pos       (16U)\r
+#define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */\r
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */\r
+#define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */\r
+#define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */\r
+#define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */\r
+#define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */\r
+#define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */\r
+#define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */\r
+#define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */\r
+#define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */\r
+\r
+#define FMC_PATT_ATTHIZ_Pos        (24U)\r
+#define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */\r
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */\r
+#define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */\r
+#define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */\r
+#define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */\r
+#define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */\r
+#define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */\r
+#define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */\r
+#define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */\r
+#define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */\r
+\r
+/******************  Bit definition for FMC_ECCR register  *******************/\r
+#define FMC_ECCR_ECC_Pos           (0U)\r
+#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)          /*!< 0xFFFFFFFF */\r
+#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                       General Purpose IOs (GPIO)                           */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bits definition for GPIO_MODER register  *****************/\r
+#define GPIO_MODER_MODE0_Pos           (0U)\r
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */\r
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk\r
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */\r
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */\r
+#define GPIO_MODER_MODE1_Pos           (2U)\r
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */\r
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk\r
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */\r
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */\r
+#define GPIO_MODER_MODE2_Pos           (4U)\r
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */\r
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk\r
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */\r
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */\r
+#define GPIO_MODER_MODE3_Pos           (6U)\r
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */\r
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk\r
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */\r
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */\r
+#define GPIO_MODER_MODE4_Pos           (8U)\r
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */\r
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk\r
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */\r
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */\r
+#define GPIO_MODER_MODE5_Pos           (10U)\r
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */\r
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk\r
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */\r
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */\r
+#define GPIO_MODER_MODE6_Pos           (12U)\r
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */\r
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk\r
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */\r
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */\r
+#define GPIO_MODER_MODE7_Pos           (14U)\r
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */\r
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk\r
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */\r
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */\r
+#define GPIO_MODER_MODE8_Pos           (16U)\r
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */\r
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk\r
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */\r
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */\r
+#define GPIO_MODER_MODE9_Pos           (18U)\r
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */\r
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk\r
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */\r
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */\r
+#define GPIO_MODER_MODE10_Pos          (20U)\r
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */\r
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk\r
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */\r
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */\r
+#define GPIO_MODER_MODE11_Pos          (22U)\r
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */\r
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk\r
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */\r
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */\r
+#define GPIO_MODER_MODE12_Pos          (24U)\r
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */\r
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk\r
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */\r
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */\r
+#define GPIO_MODER_MODE13_Pos          (26U)\r
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */\r
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk\r
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */\r
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */\r
+#define GPIO_MODER_MODE14_Pos          (28U)\r
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */\r
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk\r
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */\r
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */\r
+#define GPIO_MODER_MODE15_Pos          (30U)\r
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */\r
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk\r
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */\r
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */\r
+\r
+/* Legacy defines */\r
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0\r
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0\r
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1\r
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1\r
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0\r
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1\r
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2\r
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0\r
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1\r
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3\r
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0\r
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1\r
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4\r
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0\r
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1\r
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5\r
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0\r
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1\r
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6\r
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0\r
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1\r
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7\r
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0\r
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1\r
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8\r
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0\r
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1\r
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9\r
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0\r
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1\r
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10\r
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0\r
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1\r
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11\r
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0\r
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1\r
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12\r
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0\r
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1\r
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13\r
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0\r
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1\r
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14\r
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0\r
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1\r
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15\r
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0\r
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1\r
+\r
+/******************  Bits definition for GPIO_OTYPER register  ****************/\r
+#define GPIO_OTYPER_OT0_Pos            (0U)\r
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */\r
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk\r
+#define GPIO_OTYPER_OT1_Pos            (1U)\r
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */\r
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk\r
+#define GPIO_OTYPER_OT2_Pos            (2U)\r
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */\r
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk\r
+#define GPIO_OTYPER_OT3_Pos            (3U)\r
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */\r
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk\r
+#define GPIO_OTYPER_OT4_Pos            (4U)\r
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */\r
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk\r
+#define GPIO_OTYPER_OT5_Pos            (5U)\r
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */\r
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk\r
+#define GPIO_OTYPER_OT6_Pos            (6U)\r
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */\r
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk\r
+#define GPIO_OTYPER_OT7_Pos            (7U)\r
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */\r
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk\r
+#define GPIO_OTYPER_OT8_Pos            (8U)\r
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */\r
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk\r
+#define GPIO_OTYPER_OT9_Pos            (9U)\r
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */\r
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk\r
+#define GPIO_OTYPER_OT10_Pos           (10U)\r
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */\r
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk\r
+#define GPIO_OTYPER_OT11_Pos           (11U)\r
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */\r
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk\r
+#define GPIO_OTYPER_OT12_Pos           (12U)\r
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */\r
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk\r
+#define GPIO_OTYPER_OT13_Pos           (13U)\r
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */\r
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk\r
+#define GPIO_OTYPER_OT14_Pos           (14U)\r
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */\r
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk\r
+#define GPIO_OTYPER_OT15_Pos           (15U)\r
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */\r
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk\r
+\r
+/* Legacy defines */\r
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0\r
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1\r
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2\r
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3\r
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4\r
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5\r
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6\r
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7\r
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8\r
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9\r
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10\r
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11\r
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12\r
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13\r
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14\r
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15\r
+\r
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/\r
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)\r
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */\r
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk\r
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */\r
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */\r
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)\r
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */\r
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk\r
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */\r
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */\r
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)\r
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */\r
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk\r
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */\r
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */\r
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)\r
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */\r
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk\r
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */\r
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */\r
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)\r
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */\r
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk\r
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */\r
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */\r
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)\r
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */\r
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk\r
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */\r
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */\r
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)\r
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */\r
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk\r
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */\r
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */\r
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)\r
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */\r
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk\r
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */\r
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */\r
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)\r
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */\r
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk\r
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */\r
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */\r
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)\r
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */\r
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk\r
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */\r
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */\r
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)\r
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */\r
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk\r
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */\r
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */\r
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)\r
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */\r
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk\r
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */\r
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */\r
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)\r
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */\r
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk\r
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */\r
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */\r
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)\r
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */\r
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk\r
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */\r
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */\r
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)\r
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */\r
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk\r
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */\r
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */\r
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)\r
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */\r
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk\r
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */\r
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */\r
+\r
+/* Legacy defines */\r
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0\r
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0\r
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1\r
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1\r
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0\r
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1\r
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2\r
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0\r
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1\r
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3\r
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0\r
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1\r
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4\r
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0\r
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1\r
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5\r
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0\r
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1\r
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6\r
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0\r
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1\r
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7\r
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0\r
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1\r
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8\r
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0\r
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1\r
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9\r
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0\r
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1\r
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10\r
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0\r
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1\r
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11\r
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0\r
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1\r
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12\r
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0\r
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1\r
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13\r
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0\r
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1\r
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14\r
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0\r
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1\r
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15\r
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0\r
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1\r
+\r
+/******************  Bits definition for GPIO_PUPDR register  *****************/\r
+#define GPIO_PUPDR_PUPD0_Pos           (0U)\r
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */\r
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk\r
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */\r
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */\r
+#define GPIO_PUPDR_PUPD1_Pos           (2U)\r
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */\r
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk\r
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */\r
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */\r
+#define GPIO_PUPDR_PUPD2_Pos           (4U)\r
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */\r
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk\r
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */\r
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */\r
+#define GPIO_PUPDR_PUPD3_Pos           (6U)\r
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */\r
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk\r
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */\r
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */\r
+#define GPIO_PUPDR_PUPD4_Pos           (8U)\r
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */\r
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk\r
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */\r
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */\r
+#define GPIO_PUPDR_PUPD5_Pos           (10U)\r
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */\r
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk\r
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */\r
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */\r
+#define GPIO_PUPDR_PUPD6_Pos           (12U)\r
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */\r
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk\r
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */\r
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */\r
+#define GPIO_PUPDR_PUPD7_Pos           (14U)\r
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */\r
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk\r
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */\r
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */\r
+#define GPIO_PUPDR_PUPD8_Pos           (16U)\r
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */\r
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk\r
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */\r
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */\r
+#define GPIO_PUPDR_PUPD9_Pos           (18U)\r
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */\r
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk\r
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */\r
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */\r
+#define GPIO_PUPDR_PUPD10_Pos          (20U)\r
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */\r
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk\r
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */\r
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */\r
+#define GPIO_PUPDR_PUPD11_Pos          (22U)\r
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */\r
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk\r
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */\r
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */\r
+#define GPIO_PUPDR_PUPD12_Pos          (24U)\r
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */\r
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk\r
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */\r
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */\r
+#define GPIO_PUPDR_PUPD13_Pos          (26U)\r
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */\r
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk\r
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */\r
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */\r
+#define GPIO_PUPDR_PUPD14_Pos          (28U)\r
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */\r
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk\r
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */\r
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */\r
+#define GPIO_PUPDR_PUPD15_Pos          (30U)\r
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */\r
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk\r
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */\r
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */\r
+\r
+/* Legacy defines */\r
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0\r
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0\r
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1\r
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1\r
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0\r
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1\r
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2\r
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0\r
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1\r
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3\r
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0\r
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1\r
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4\r
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0\r
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1\r
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5\r
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0\r
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1\r
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6\r
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0\r
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1\r
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7\r
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0\r
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1\r
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8\r
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0\r
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1\r
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9\r
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0\r
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1\r
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10\r
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0\r
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1\r
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11\r
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0\r
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1\r
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12\r
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0\r
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1\r
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13\r
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0\r
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1\r
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14\r
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0\r
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1\r
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15\r
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0\r
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1\r
+\r
+/******************  Bits definition for GPIO_IDR register  *******************/\r
+#define GPIO_IDR_ID0_Pos               (0U)\r
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */\r
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk\r
+#define GPIO_IDR_ID1_Pos               (1U)\r
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */\r
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk\r
+#define GPIO_IDR_ID2_Pos               (2U)\r
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */\r
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk\r
+#define GPIO_IDR_ID3_Pos               (3U)\r
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */\r
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk\r
+#define GPIO_IDR_ID4_Pos               (4U)\r
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */\r
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk\r
+#define GPIO_IDR_ID5_Pos               (5U)\r
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */\r
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk\r
+#define GPIO_IDR_ID6_Pos               (6U)\r
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */\r
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk\r
+#define GPIO_IDR_ID7_Pos               (7U)\r
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */\r
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk\r
+#define GPIO_IDR_ID8_Pos               (8U)\r
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */\r
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk\r
+#define GPIO_IDR_ID9_Pos               (9U)\r
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */\r
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk\r
+#define GPIO_IDR_ID10_Pos              (10U)\r
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */\r
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk\r
+#define GPIO_IDR_ID11_Pos              (11U)\r
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */\r
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk\r
+#define GPIO_IDR_ID12_Pos              (12U)\r
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */\r
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk\r
+#define GPIO_IDR_ID13_Pos              (13U)\r
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */\r
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk\r
+#define GPIO_IDR_ID14_Pos              (14U)\r
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */\r
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk\r
+#define GPIO_IDR_ID15_Pos              (15U)\r
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */\r
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk\r
+\r
+/* Legacy defines */\r
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0\r
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1\r
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2\r
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3\r
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4\r
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5\r
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6\r
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7\r
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8\r
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9\r
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10\r
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11\r
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12\r
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13\r
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14\r
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15\r
+\r
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0\r
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1\r
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2\r
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3\r
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4\r
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5\r
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6\r
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7\r
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8\r
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9\r
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10\r
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11\r
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12\r
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13\r
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14\r
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15\r
+\r
+/******************  Bits definition for GPIO_ODR register  *******************/\r
+#define GPIO_ODR_OD0_Pos               (0U)\r
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */\r
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk\r
+#define GPIO_ODR_OD1_Pos               (1U)\r
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */\r
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk\r
+#define GPIO_ODR_OD2_Pos               (2U)\r
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */\r
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk\r
+#define GPIO_ODR_OD3_Pos               (3U)\r
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */\r
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk\r
+#define GPIO_ODR_OD4_Pos               (4U)\r
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */\r
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk\r
+#define GPIO_ODR_OD5_Pos               (5U)\r
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */\r
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk\r
+#define GPIO_ODR_OD6_Pos               (6U)\r
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */\r
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk\r
+#define GPIO_ODR_OD7_Pos               (7U)\r
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */\r
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk\r
+#define GPIO_ODR_OD8_Pos               (8U)\r
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */\r
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk\r
+#define GPIO_ODR_OD9_Pos               (9U)\r
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */\r
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk\r
+#define GPIO_ODR_OD10_Pos              (10U)\r
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */\r
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk\r
+#define GPIO_ODR_OD11_Pos              (11U)\r
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */\r
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk\r
+#define GPIO_ODR_OD12_Pos              (12U)\r
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */\r
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk\r
+#define GPIO_ODR_OD13_Pos              (13U)\r
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */\r
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk\r
+#define GPIO_ODR_OD14_Pos              (14U)\r
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */\r
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk\r
+#define GPIO_ODR_OD15_Pos              (15U)\r
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */\r
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk\r
+\r
+/* Legacy defines */\r
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0\r
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1\r
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2\r
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3\r
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4\r
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5\r
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6\r
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7\r
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8\r
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9\r
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10\r
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11\r
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12\r
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13\r
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14\r
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15\r
+\r
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0\r
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1\r
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2\r
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3\r
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4\r
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5\r
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6\r
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7\r
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8\r
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9\r
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10\r
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11\r
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12\r
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13\r
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14\r
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15\r
+\r
+/******************  Bits definition for GPIO_BSRR register  ******************/\r
+#define GPIO_BSRR_BS0_Pos              (0U)\r
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */\r
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk\r
+#define GPIO_BSRR_BS1_Pos              (1U)\r
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */\r
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk\r
+#define GPIO_BSRR_BS2_Pos              (2U)\r
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */\r
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk\r
+#define GPIO_BSRR_BS3_Pos              (3U)\r
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */\r
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk\r
+#define GPIO_BSRR_BS4_Pos              (4U)\r
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */\r
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk\r
+#define GPIO_BSRR_BS5_Pos              (5U)\r
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */\r
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk\r
+#define GPIO_BSRR_BS6_Pos              (6U)\r
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */\r
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk\r
+#define GPIO_BSRR_BS7_Pos              (7U)\r
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */\r
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk\r
+#define GPIO_BSRR_BS8_Pos              (8U)\r
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */\r
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk\r
+#define GPIO_BSRR_BS9_Pos              (9U)\r
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */\r
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk\r
+#define GPIO_BSRR_BS10_Pos             (10U)\r
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */\r
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk\r
+#define GPIO_BSRR_BS11_Pos             (11U)\r
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */\r
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk\r
+#define GPIO_BSRR_BS12_Pos             (12U)\r
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */\r
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk\r
+#define GPIO_BSRR_BS13_Pos             (13U)\r
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */\r
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk\r
+#define GPIO_BSRR_BS14_Pos             (14U)\r
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */\r
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk\r
+#define GPIO_BSRR_BS15_Pos             (15U)\r
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */\r
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk\r
+#define GPIO_BSRR_BR0_Pos              (16U)\r
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */\r
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk\r
+#define GPIO_BSRR_BR1_Pos              (17U)\r
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */\r
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk\r
+#define GPIO_BSRR_BR2_Pos              (18U)\r
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */\r
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk\r
+#define GPIO_BSRR_BR3_Pos              (19U)\r
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */\r
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk\r
+#define GPIO_BSRR_BR4_Pos              (20U)\r
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */\r
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk\r
+#define GPIO_BSRR_BR5_Pos              (21U)\r
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */\r
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk\r
+#define GPIO_BSRR_BR6_Pos              (22U)\r
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */\r
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk\r
+#define GPIO_BSRR_BR7_Pos              (23U)\r
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */\r
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk\r
+#define GPIO_BSRR_BR8_Pos              (24U)\r
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */\r
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk\r
+#define GPIO_BSRR_BR9_Pos              (25U)\r
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */\r
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk\r
+#define GPIO_BSRR_BR10_Pos             (26U)\r
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */\r
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk\r
+#define GPIO_BSRR_BR11_Pos             (27U)\r
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */\r
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk\r
+#define GPIO_BSRR_BR12_Pos             (28U)\r
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */\r
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk\r
+#define GPIO_BSRR_BR13_Pos             (29U)\r
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */\r
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk\r
+#define GPIO_BSRR_BR14_Pos             (30U)\r
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */\r
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk\r
+#define GPIO_BSRR_BR15_Pos             (31U)\r
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */\r
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk\r
+\r
+/* Legacy defines */\r
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0\r
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1\r
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2\r
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3\r
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4\r
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5\r
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6\r
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7\r
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8\r
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9\r
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10\r
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11\r
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12\r
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13\r
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14\r
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15\r
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0\r
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1\r
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2\r
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3\r
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4\r
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5\r
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6\r
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7\r
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8\r
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9\r
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10\r
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11\r
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12\r
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13\r
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14\r
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15\r
+\r
+/****************** Bit definition for GPIO_LCKR register *********************/\r
+#define GPIO_LCKR_LCK0_Pos             (0U)\r
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */\r
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk\r
+#define GPIO_LCKR_LCK1_Pos             (1U)\r
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */\r
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk\r
+#define GPIO_LCKR_LCK2_Pos             (2U)\r
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */\r
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk\r
+#define GPIO_LCKR_LCK3_Pos             (3U)\r
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */\r
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk\r
+#define GPIO_LCKR_LCK4_Pos             (4U)\r
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */\r
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk\r
+#define GPIO_LCKR_LCK5_Pos             (5U)\r
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */\r
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk\r
+#define GPIO_LCKR_LCK6_Pos             (6U)\r
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */\r
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk\r
+#define GPIO_LCKR_LCK7_Pos             (7U)\r
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */\r
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk\r
+#define GPIO_LCKR_LCK8_Pos             (8U)\r
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */\r
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk\r
+#define GPIO_LCKR_LCK9_Pos             (9U)\r
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */\r
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk\r
+#define GPIO_LCKR_LCK10_Pos            (10U)\r
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */\r
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk\r
+#define GPIO_LCKR_LCK11_Pos            (11U)\r
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */\r
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk\r
+#define GPIO_LCKR_LCK12_Pos            (12U)\r
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */\r
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk\r
+#define GPIO_LCKR_LCK13_Pos            (13U)\r
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */\r
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk\r
+#define GPIO_LCKR_LCK14_Pos            (14U)\r
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */\r
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk\r
+#define GPIO_LCKR_LCK15_Pos            (15U)\r
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */\r
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk\r
+#define GPIO_LCKR_LCKK_Pos             (16U)\r
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */\r
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk\r
+\r
+/****************** Bit definition for GPIO_AFRL register *********************/\r
+#define GPIO_AFRL_AFSEL0_Pos           (0U)\r
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */\r
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk\r
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */\r
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */\r
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */\r
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */\r
+#define GPIO_AFRL_AFSEL1_Pos           (4U)\r
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */\r
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk\r
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */\r
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */\r
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */\r
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */\r
+#define GPIO_AFRL_AFSEL2_Pos           (8U)\r
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */\r
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk\r
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */\r
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */\r
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */\r
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */\r
+#define GPIO_AFRL_AFSEL3_Pos           (12U)\r
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */\r
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk\r
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */\r
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */\r
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */\r
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */\r
+#define GPIO_AFRL_AFSEL4_Pos           (16U)\r
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */\r
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk\r
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */\r
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */\r
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */\r
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */\r
+#define GPIO_AFRL_AFSEL5_Pos           (20U)\r
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */\r
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk\r
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */\r
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */\r
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */\r
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */\r
+#define GPIO_AFRL_AFSEL6_Pos           (24U)\r
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */\r
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk\r
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */\r
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */\r
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */\r
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */\r
+#define GPIO_AFRL_AFSEL7_Pos           (28U)\r
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */\r
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk\r
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */\r
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */\r
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */\r
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */\r
+\r
+/* Legacy defines */\r
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\r
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\r
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\r
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\r
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\r
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\r
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\r
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\r
+\r
+/****************** Bit definition for GPIO_AFRH register *********************/\r
+#define GPIO_AFRH_AFSEL8_Pos           (0U)\r
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */\r
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk\r
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */\r
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */\r
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */\r
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */\r
+#define GPIO_AFRH_AFSEL9_Pos           (4U)\r
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */\r
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk\r
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */\r
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */\r
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */\r
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */\r
+#define GPIO_AFRH_AFSEL10_Pos          (8U)\r
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */\r
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk\r
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */\r
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */\r
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */\r
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */\r
+#define GPIO_AFRH_AFSEL11_Pos          (12U)\r
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */\r
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk\r
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */\r
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */\r
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */\r
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */\r
+#define GPIO_AFRH_AFSEL12_Pos          (16U)\r
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */\r
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk\r
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */\r
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */\r
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */\r
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */\r
+#define GPIO_AFRH_AFSEL13_Pos          (20U)\r
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */\r
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk\r
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */\r
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */\r
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */\r
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */\r
+#define GPIO_AFRH_AFSEL14_Pos          (24U)\r
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */\r
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk\r
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */\r
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */\r
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */\r
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */\r
+#define GPIO_AFRH_AFSEL15_Pos          (28U)\r
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */\r
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk\r
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */\r
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */\r
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */\r
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */\r
+\r
+/* Legacy defines */\r
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\r
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\r
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\r
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\r
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\r
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\r
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\r
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\r
+\r
+/******************  Bits definition for GPIO_BRR register  ******************/\r
+#define GPIO_BRR_BR0_Pos               (0U)\r
+#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */\r
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk\r
+#define GPIO_BRR_BR1_Pos               (1U)\r
+#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */\r
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk\r
+#define GPIO_BRR_BR2_Pos               (2U)\r
+#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */\r
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk\r
+#define GPIO_BRR_BR3_Pos               (3U)\r
+#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */\r
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk\r
+#define GPIO_BRR_BR4_Pos               (4U)\r
+#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */\r
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk\r
+#define GPIO_BRR_BR5_Pos               (5U)\r
+#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */\r
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk\r
+#define GPIO_BRR_BR6_Pos               (6U)\r
+#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */\r
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk\r
+#define GPIO_BRR_BR7_Pos               (7U)\r
+#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */\r
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk\r
+#define GPIO_BRR_BR8_Pos               (8U)\r
+#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */\r
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk\r
+#define GPIO_BRR_BR9_Pos               (9U)\r
+#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */\r
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk\r
+#define GPIO_BRR_BR10_Pos              (10U)\r
+#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */\r
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk\r
+#define GPIO_BRR_BR11_Pos              (11U)\r
+#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */\r
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk\r
+#define GPIO_BRR_BR12_Pos              (12U)\r
+#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */\r
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk\r
+#define GPIO_BRR_BR13_Pos              (13U)\r
+#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */\r
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk\r
+#define GPIO_BRR_BR14_Pos              (14U)\r
+#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */\r
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk\r
+#define GPIO_BRR_BR15_Pos              (15U)\r
+#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */\r
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk\r
+\r
+/* Legacy defines */\r
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0\r
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1\r
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2\r
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3\r
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4\r
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5\r
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6\r
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7\r
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8\r
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9\r
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10\r
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11\r
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12\r
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13\r
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14\r
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15\r
+\r
+\r
+/******************  Bits definition for GPIO_ASCR register  *******************/\r
+#define GPIO_ASCR_ASC0_Pos             (0U)\r
+#define GPIO_ASCR_ASC0_Msk             (0x1UL << GPIO_ASCR_ASC0_Pos)           /*!< 0x00000001 */\r
+#define GPIO_ASCR_ASC0                 GPIO_ASCR_ASC0_Msk\r
+#define GPIO_ASCR_ASC1_Pos             (1U)\r
+#define GPIO_ASCR_ASC1_Msk             (0x1UL << GPIO_ASCR_ASC1_Pos)           /*!< 0x00000002 */\r
+#define GPIO_ASCR_ASC1                 GPIO_ASCR_ASC1_Msk\r
+#define GPIO_ASCR_ASC2_Pos             (2U)\r
+#define GPIO_ASCR_ASC2_Msk             (0x1UL << GPIO_ASCR_ASC2_Pos)           /*!< 0x00000004 */\r
+#define GPIO_ASCR_ASC2                 GPIO_ASCR_ASC2_Msk\r
+#define GPIO_ASCR_ASC3_Pos             (3U)\r
+#define GPIO_ASCR_ASC3_Msk             (0x1UL << GPIO_ASCR_ASC3_Pos)           /*!< 0x00000008 */\r
+#define GPIO_ASCR_ASC3                 GPIO_ASCR_ASC3_Msk\r
+#define GPIO_ASCR_ASC4_Pos             (4U)\r
+#define GPIO_ASCR_ASC4_Msk             (0x1UL << GPIO_ASCR_ASC4_Pos)           /*!< 0x00000010 */\r
+#define GPIO_ASCR_ASC4                 GPIO_ASCR_ASC4_Msk\r
+#define GPIO_ASCR_ASC5_Pos             (5U)\r
+#define GPIO_ASCR_ASC5_Msk             (0x1UL << GPIO_ASCR_ASC5_Pos)           /*!< 0x00000020 */\r
+#define GPIO_ASCR_ASC5                 GPIO_ASCR_ASC5_Msk\r
+#define GPIO_ASCR_ASC6_Pos             (6U)\r
+#define GPIO_ASCR_ASC6_Msk             (0x1UL << GPIO_ASCR_ASC6_Pos)           /*!< 0x00000040 */\r
+#define GPIO_ASCR_ASC6                 GPIO_ASCR_ASC6_Msk\r
+#define GPIO_ASCR_ASC7_Pos             (7U)\r
+#define GPIO_ASCR_ASC7_Msk             (0x1UL << GPIO_ASCR_ASC7_Pos)           /*!< 0x00000080 */\r
+#define GPIO_ASCR_ASC7                 GPIO_ASCR_ASC7_Msk\r
+#define GPIO_ASCR_ASC8_Pos             (8U)\r
+#define GPIO_ASCR_ASC8_Msk             (0x1UL << GPIO_ASCR_ASC8_Pos)           /*!< 0x00000100 */\r
+#define GPIO_ASCR_ASC8                 GPIO_ASCR_ASC8_Msk\r
+#define GPIO_ASCR_ASC9_Pos             (9U)\r
+#define GPIO_ASCR_ASC9_Msk             (0x1UL << GPIO_ASCR_ASC9_Pos)           /*!< 0x00000200 */\r
+#define GPIO_ASCR_ASC9                 GPIO_ASCR_ASC9_Msk\r
+#define GPIO_ASCR_ASC10_Pos            (10U)\r
+#define GPIO_ASCR_ASC10_Msk            (0x1UL << GPIO_ASCR_ASC10_Pos)          /*!< 0x00000400 */\r
+#define GPIO_ASCR_ASC10                GPIO_ASCR_ASC10_Msk\r
+#define GPIO_ASCR_ASC11_Pos            (11U)\r
+#define GPIO_ASCR_ASC11_Msk            (0x1UL << GPIO_ASCR_ASC11_Pos)          /*!< 0x00000800 */\r
+#define GPIO_ASCR_ASC11                GPIO_ASCR_ASC11_Msk\r
+#define GPIO_ASCR_ASC12_Pos            (12U)\r
+#define GPIO_ASCR_ASC12_Msk            (0x1UL << GPIO_ASCR_ASC12_Pos)          /*!< 0x00001000 */\r
+#define GPIO_ASCR_ASC12                GPIO_ASCR_ASC12_Msk\r
+#define GPIO_ASCR_ASC13_Pos            (13U)\r
+#define GPIO_ASCR_ASC13_Msk            (0x1UL << GPIO_ASCR_ASC13_Pos)          /*!< 0x00002000 */\r
+#define GPIO_ASCR_ASC13                GPIO_ASCR_ASC13_Msk\r
+#define GPIO_ASCR_ASC14_Pos            (14U)\r
+#define GPIO_ASCR_ASC14_Msk            (0x1UL << GPIO_ASCR_ASC14_Pos)          /*!< 0x00004000 */\r
+#define GPIO_ASCR_ASC14                GPIO_ASCR_ASC14_Msk\r
+#define GPIO_ASCR_ASC15_Pos            (15U)\r
+#define GPIO_ASCR_ASC15_Msk            (0x1UL << GPIO_ASCR_ASC15_Pos)          /*!< 0x00008000 */\r
+#define GPIO_ASCR_ASC15                GPIO_ASCR_ASC15_Msk\r
+\r
+/* Legacy defines */\r
+#define GPIO_ASCR_EN_0                      GPIO_ASCR_ASC0\r
+#define GPIO_ASCR_EN_1                      GPIO_ASCR_ASC1\r
+#define GPIO_ASCR_EN_2                      GPIO_ASCR_ASC2\r
+#define GPIO_ASCR_EN_3                      GPIO_ASCR_ASC3\r
+#define GPIO_ASCR_EN_4                      GPIO_ASCR_ASC4\r
+#define GPIO_ASCR_EN_5                      GPIO_ASCR_ASC5\r
+#define GPIO_ASCR_EN_6                      GPIO_ASCR_ASC6\r
+#define GPIO_ASCR_EN_7                      GPIO_ASCR_ASC7\r
+#define GPIO_ASCR_EN_8                      GPIO_ASCR_ASC8\r
+#define GPIO_ASCR_EN_9                      GPIO_ASCR_ASC9\r
+#define GPIO_ASCR_EN_10                     GPIO_ASCR_ASC10\r
+#define GPIO_ASCR_EN_11                     GPIO_ASCR_ASC11\r
+#define GPIO_ASCR_EN_12                     GPIO_ASCR_ASC12\r
+#define GPIO_ASCR_EN_13                     GPIO_ASCR_ASC13\r
+#define GPIO_ASCR_EN_14                     GPIO_ASCR_ASC14\r
+#define GPIO_ASCR_EN_15                     GPIO_ASCR_ASC15\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      Inter-integrated Circuit Interface (I2C)              */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for I2C_CR1 register  *******************/\r
+#define I2C_CR1_PE_Pos               (0U)\r
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */\r
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */\r
+#define I2C_CR1_TXIE_Pos             (1U)\r
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */\r
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */\r
+#define I2C_CR1_RXIE_Pos             (2U)\r
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */\r
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */\r
+#define I2C_CR1_ADDRIE_Pos           (3U)\r
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */\r
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */\r
+#define I2C_CR1_NACKIE_Pos           (4U)\r
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */\r
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */\r
+#define I2C_CR1_STOPIE_Pos           (5U)\r
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */\r
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */\r
+#define I2C_CR1_TCIE_Pos             (6U)\r
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */\r
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */\r
+#define I2C_CR1_ERRIE_Pos            (7U)\r
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */\r
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */\r
+#define I2C_CR1_DNF_Pos              (8U)\r
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */\r
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */\r
+#define I2C_CR1_ANFOFF_Pos           (12U)\r
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */\r
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */\r
+#define I2C_CR1_SWRST_Pos            (13U)\r
+#define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */\r
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */\r
+#define I2C_CR1_TXDMAEN_Pos          (14U)\r
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */\r
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */\r
+#define I2C_CR1_RXDMAEN_Pos          (15U)\r
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */\r
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */\r
+#define I2C_CR1_SBC_Pos              (16U)\r
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */\r
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */\r
+#define I2C_CR1_NOSTRETCH_Pos        (17U)\r
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */\r
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */\r
+#define I2C_CR1_WUPEN_Pos            (18U)\r
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */\r
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */\r
+#define I2C_CR1_GCEN_Pos             (19U)\r
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */\r
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */\r
+#define I2C_CR1_SMBHEN_Pos           (20U)\r
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */\r
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */\r
+#define I2C_CR1_SMBDEN_Pos           (21U)\r
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */\r
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN_Pos          (22U)\r
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */\r
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */\r
+#define I2C_CR1_PECEN_Pos            (23U)\r
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */\r
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */\r
+\r
+/******************  Bit definition for I2C_CR2 register  ********************/\r
+#define I2C_CR2_SADD_Pos             (0U)\r
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */\r
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */\r
+#define I2C_CR2_RD_WRN_Pos           (10U)\r
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */\r
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */\r
+#define I2C_CR2_ADD10_Pos            (11U)\r
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */\r
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */\r
+#define I2C_CR2_HEAD10R_Pos          (12U)\r
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */\r
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START_Pos            (13U)\r
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */\r
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */\r
+#define I2C_CR2_STOP_Pos             (14U)\r
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */\r
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */\r
+#define I2C_CR2_NACK_Pos             (15U)\r
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */\r
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */\r
+#define I2C_CR2_NBYTES_Pos           (16U)\r
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */\r
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */\r
+#define I2C_CR2_RELOAD_Pos           (24U)\r
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */\r
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */\r
+#define I2C_CR2_AUTOEND_Pos          (25U)\r
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */\r
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */\r
+#define I2C_CR2_PECBYTE_Pos          (26U)\r
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */\r
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */\r
+\r
+/*******************  Bit definition for I2C_OAR1 register  ******************/\r
+#define I2C_OAR1_OA1_Pos             (0U)\r
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */\r
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */\r
+#define I2C_OAR1_OA1MODE_Pos         (10U)\r
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */\r
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN_Pos           (15U)\r
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */\r
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */\r
+\r
+/*******************  Bit definition for I2C_OAR2 register  ******************/\r
+#define I2C_OAR2_OA2_Pos             (1U)\r
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */\r
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */\r
+#define I2C_OAR2_OA2MSK_Pos          (8U)\r
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */\r
+#define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */\r
+#define I2C_OAR2_OA2MASK01_Pos       (8U)\r
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */\r
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */\r
+#define I2C_OAR2_OA2MASK02_Pos       (9U)\r
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */\r
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r
+#define I2C_OAR2_OA2MASK03_Pos       (8U)\r
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */\r
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r
+#define I2C_OAR2_OA2MASK04_Pos       (10U)\r
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */\r
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r
+#define I2C_OAR2_OA2MASK05_Pos       (8U)\r
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */\r
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r
+#define I2C_OAR2_OA2MASK06_Pos       (9U)\r
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */\r
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */\r
+#define I2C_OAR2_OA2MASK07_Pos       (8U)\r
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */\r
+#define I2C_OAR2_OA2EN_Pos           (15U)\r
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */\r
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */\r
+\r
+/*******************  Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL_Pos         (0U)\r
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */\r
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */\r
+#define I2C_TIMINGR_SCLH_Pos         (8U)\r
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */\r
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL_Pos       (16U)\r
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */\r
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */\r
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)\r
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */\r
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */\r
+#define I2C_TIMINGR_PRESC_Pos        (28U)\r
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */\r
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\r
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */\r
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */\r
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)\r
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */\r
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */\r
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\r
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */\r
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */\r
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\r
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */\r
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */\r
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)\r
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */\r
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\r
+\r
+/******************  Bit definition for I2C_ISR register  *********************/\r
+#define I2C_ISR_TXE_Pos              (0U)\r
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */\r
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */\r
+#define I2C_ISR_TXIS_Pos             (1U)\r
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */\r
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */\r
+#define I2C_ISR_RXNE_Pos             (2U)\r
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */\r
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR_Pos             (3U)\r
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */\r
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */\r
+#define I2C_ISR_NACKF_Pos            (4U)\r
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */\r
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */\r
+#define I2C_ISR_STOPF_Pos            (5U)\r
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */\r
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */\r
+#define I2C_ISR_TC_Pos               (6U)\r
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */\r
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR_Pos              (7U)\r
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */\r
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */\r
+#define I2C_ISR_BERR_Pos             (8U)\r
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */\r
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */\r
+#define I2C_ISR_ARLO_Pos             (9U)\r
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */\r
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */\r
+#define I2C_ISR_OVR_Pos              (10U)\r
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */\r
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */\r
+#define I2C_ISR_PECERR_Pos           (11U)\r
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */\r
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */\r
+#define I2C_ISR_TIMEOUT_Pos          (12U)\r
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */\r
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */\r
+#define I2C_ISR_ALERT_Pos            (13U)\r
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */\r
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */\r
+#define I2C_ISR_BUSY_Pos             (15U)\r
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */\r
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */\r
+#define I2C_ISR_DIR_Pos              (16U)\r
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */\r
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE_Pos          (17U)\r
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */\r
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\r
+\r
+/******************  Bit definition for I2C_ICR register  *********************/\r
+#define I2C_ICR_ADDRCF_Pos           (3U)\r
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */\r
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */\r
+#define I2C_ICR_NACKCF_Pos           (4U)\r
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */\r
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */\r
+#define I2C_ICR_STOPCF_Pos           (5U)\r
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */\r
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */\r
+#define I2C_ICR_BERRCF_Pos           (8U)\r
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */\r
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */\r
+#define I2C_ICR_ARLOCF_Pos           (9U)\r
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */\r
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF_Pos            (10U)\r
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */\r
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF_Pos            (11U)\r
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */\r
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */\r
+#define I2C_ICR_TIMOUTCF_Pos         (12U)\r
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */\r
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */\r
+#define I2C_ICR_ALERTCF_Pos          (13U)\r
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */\r
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */\r
+\r
+/******************  Bit definition for I2C_PECR register  *********************/\r
+#define I2C_PECR_PEC_Pos             (0U)\r
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */\r
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */\r
+\r
+/******************  Bit definition for I2C_RXDR register  *********************/\r
+#define I2C_RXDR_RXDATA_Pos          (0U)\r
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */\r
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */\r
+\r
+/******************  Bit definition for I2C_TXDR register  *********************/\r
+#define I2C_TXDR_TXDATA_Pos          (0U)\r
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */\r
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                           Independent WATCHDOG                             */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for IWDG_KR register  ********************/\r
+#define IWDG_KR_KEY_Pos      (0U)\r
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */\r
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\r
+\r
+/*******************  Bit definition for IWDG_PR register  ********************/\r
+#define IWDG_PR_PR_Pos       (0U)\r
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */\r
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\r
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */\r
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */\r
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */\r
+\r
+/*******************  Bit definition for IWDG_RLR register  *******************/\r
+#define IWDG_RLR_RL_Pos      (0U)\r
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */\r
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\r
+\r
+/*******************  Bit definition for IWDG_SR register  ********************/\r
+#define IWDG_SR_PVU_Pos      (0U)\r
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */\r
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU_Pos      (1U)\r
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */\r
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU_Pos      (2U)\r
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */\r
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\r
+\r
+/*******************  Bit definition for IWDG_KR register  ********************/\r
+#define IWDG_WINR_WIN_Pos    (0U)\r
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */\r
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                     Firewall                               */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */\r
+#define FW_CSSA_ADD_Pos      (8U)\r
+#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                     /*!< 0x00FFFF00 */\r
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */\r
+#define FW_CSL_LENG_Pos      (8U)\r
+#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                     /*!< 0x003FFF00 */\r
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */\r
+#define FW_NVDSSA_ADD_Pos    (8U)\r
+#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                   /*!< 0x00FFFF00 */\r
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */\r
+#define FW_NVDSL_LENG_Pos    (8U)\r
+#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                   /*!< 0x003FFF00 */\r
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */\r
+#define FW_VDSSA_ADD_Pos     (6U)\r
+#define FW_VDSSA_ADD_Msk     (0x7FFUL << FW_VDSSA_ADD_Pos)                     /*!< 0x0001FFC0 */\r
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */\r
+#define FW_VDSL_LENG_Pos     (6U)\r
+#define FW_VDSL_LENG_Msk     (0x7FFUL << FW_VDSL_LENG_Pos)                     /*!< 0x0001FFC0 */\r
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */\r
+\r
+/**************************Bit definition for CR register *********************/\r
+#define FW_CR_FPA_Pos        (0U)\r
+#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                          /*!< 0x00000001 */\r
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/\r
+#define FW_CR_VDS_Pos        (1U)\r
+#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                          /*!< 0x00000002 */\r
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/\r
+#define FW_CR_VDE_Pos        (2U)\r
+#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                          /*!< 0x00000004 */\r
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                             Power Control                                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for PWR_CR1 register  ********************/\r
+\r
+#define PWR_CR1_LPR_Pos              (14U)\r
+#define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */\r
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */\r
+#define PWR_CR1_VOS_Pos              (9U)\r
+#define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */\r
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */\r
+#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */\r
+#define PWR_CR1_DBP_Pos              (8U)\r
+#define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */\r
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */\r
+#define PWR_CR1_LPMS_Pos             (0U)\r
+#define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */\r
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */\r
+#define PWR_CR1_LPMS_STOP0           (0x00000000UL)                            /*!< Stop 0 mode */\r
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)\r
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */\r
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */\r
+#define PWR_CR1_LPMS_STOP2_Pos       (1U)\r
+#define PWR_CR1_LPMS_STOP2_Msk       (0x1UL << PWR_CR1_LPMS_STOP2_Pos)         /*!< 0x00000002 */\r
+#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */\r
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)\r
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */\r
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */\r
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)\r
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */\r
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */\r
+\r
+\r
+/********************  Bit definition for PWR_CR2 register  ********************/\r
+#define PWR_CR2_USV_Pos              (10U)\r
+#define PWR_CR2_USV_Msk              (0x1UL << PWR_CR2_USV_Pos)                /*!< 0x00000400 */\r
+#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */\r
+#define PWR_CR2_IOSV_Pos             (9U)\r
+#define PWR_CR2_IOSV_Msk             (0x1UL << PWR_CR2_IOSV_Pos)               /*!< 0x00000200 */\r
+#define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */\r
+/*!< PVME  Peripheral Voltage Monitor Enable */\r
+#define PWR_CR2_PVME_Pos             (4U)\r
+#define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */\r
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */\r
+#define PWR_CR2_PVME4_Pos            (7U)\r
+#define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */\r
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */\r
+#define PWR_CR2_PVME3_Pos            (6U)\r
+#define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */\r
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */\r
+#define PWR_CR2_PVME2_Pos            (5U)\r
+#define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */\r
+#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */\r
+#define PWR_CR2_PVME1_Pos            (4U)\r
+#define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */\r
+#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */\r
+/*!< PVD level configuration */\r
+#define PWR_CR2_PLS_Pos              (1U)\r
+#define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */\r
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */\r
+#define PWR_CR2_PLS_LEV0             (0x00000000UL)                            /*!< PVD level 0 */\r
+#define PWR_CR2_PLS_LEV1_Pos         (1U)\r
+#define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */\r
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */\r
+#define PWR_CR2_PLS_LEV2_Pos         (2U)\r
+#define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */\r
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */\r
+#define PWR_CR2_PLS_LEV3_Pos         (1U)\r
+#define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */\r
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */\r
+#define PWR_CR2_PLS_LEV4_Pos         (3U)\r
+#define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */\r
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */\r
+#define PWR_CR2_PLS_LEV5_Pos         (1U)\r
+#define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */\r
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */\r
+#define PWR_CR2_PLS_LEV6_Pos         (2U)\r
+#define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */\r
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */\r
+#define PWR_CR2_PLS_LEV7_Pos         (1U)\r
+#define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */\r
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */\r
+#define PWR_CR2_PVDE_Pos             (0U)\r
+#define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */\r
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */\r
+\r
+/********************  Bit definition for PWR_CR3 register  ********************/\r
+#define PWR_CR3_EIWUL_Pos            (15U)\r
+#define PWR_CR3_EIWUL_Msk            (0x1UL << PWR_CR3_EIWUL_Pos)              /*!< 0x00008000 */\r
+#define PWR_CR3_EIWUL                PWR_CR3_EIWUL_Msk                         /*!< Enable Internal Wake-up line */\r
+#define PWR_CR3_APC_Pos              (10U)\r
+#define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */\r
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */\r
+#define PWR_CR3_RRS_Pos              (8U)\r
+#define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */\r
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */\r
+#define PWR_CR3_EWUP5_Pos            (4U)\r
+#define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */\r
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */\r
+#define PWR_CR3_EWUP4_Pos            (3U)\r
+#define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */\r
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */\r
+#define PWR_CR3_EWUP3_Pos            (2U)\r
+#define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */\r
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */\r
+#define PWR_CR3_EWUP2_Pos            (1U)\r
+#define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */\r
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */\r
+#define PWR_CR3_EWUP1_Pos            (0U)\r
+#define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */\r
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */\r
+#define PWR_CR3_EWUP_Pos             (0U)\r
+#define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */\r
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */\r
+\r
+/* Legacy defines */\r
+#define PWR_CR3_EIWF_Pos             PWR_CR3_EIWUL_Pos\r
+#define PWR_CR3_EIWF_Msk             PWR_CR3_EIWUL_Msk\r
+#define PWR_CR3_EIWF                 PWR_CR3_EIWUL\r
+\r
+\r
+/********************  Bit definition for PWR_CR4 register  ********************/\r
+#define PWR_CR4_VBRS_Pos             (9U)\r
+#define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */\r
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */\r
+#define PWR_CR4_VBE_Pos              (8U)\r
+#define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */\r
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */\r
+#define PWR_CR4_WP5_Pos              (4U)\r
+#define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */\r
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */\r
+#define PWR_CR4_WP4_Pos              (3U)\r
+#define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */\r
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */\r
+#define PWR_CR4_WP3_Pos              (2U)\r
+#define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */\r
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */\r
+#define PWR_CR4_WP2_Pos              (1U)\r
+#define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */\r
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */\r
+#define PWR_CR4_WP1_Pos              (0U)\r
+#define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */\r
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */\r
+\r
+/********************  Bit definition for PWR_SR1 register  ********************/\r
+#define PWR_SR1_WUFI_Pos             (15U)\r
+#define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */\r
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */\r
+#define PWR_SR1_SBF_Pos              (8U)\r
+#define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */\r
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */\r
+#define PWR_SR1_WUF_Pos              (0U)\r
+#define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */\r
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */\r
+#define PWR_SR1_WUF5_Pos             (4U)\r
+#define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */\r
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */\r
+#define PWR_SR1_WUF4_Pos             (3U)\r
+#define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */\r
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */\r
+#define PWR_SR1_WUF3_Pos             (2U)\r
+#define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */\r
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */\r
+#define PWR_SR1_WUF2_Pos             (1U)\r
+#define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */\r
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */\r
+#define PWR_SR1_WUF1_Pos             (0U)\r
+#define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */\r
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */\r
+\r
+/********************  Bit definition for PWR_SR2 register  ********************/\r
+#define PWR_SR2_PVMO4_Pos            (15U)\r
+#define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */\r
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */\r
+#define PWR_SR2_PVMO3_Pos            (14U)\r
+#define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */\r
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */\r
+#define PWR_SR2_PVMO2_Pos            (13U)\r
+#define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */\r
+#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */\r
+#define PWR_SR2_PVMO1_Pos            (12U)\r
+#define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */\r
+#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */\r
+#define PWR_SR2_PVDO_Pos             (11U)\r
+#define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */\r
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */\r
+#define PWR_SR2_VOSF_Pos             (10U)\r
+#define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */\r
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */\r
+#define PWR_SR2_REGLPF_Pos           (9U)\r
+#define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */\r
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */\r
+#define PWR_SR2_REGLPS_Pos           (8U)\r
+#define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */\r
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */\r
+\r
+/********************  Bit definition for PWR_SCR register  ********************/\r
+#define PWR_SCR_CSBF_Pos             (8U)\r
+#define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */\r
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */\r
+#define PWR_SCR_CWUF_Pos             (0U)\r
+#define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */\r
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */\r
+#define PWR_SCR_CWUF5_Pos            (4U)\r
+#define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */\r
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */\r
+#define PWR_SCR_CWUF4_Pos            (3U)\r
+#define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */\r
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */\r
+#define PWR_SCR_CWUF3_Pos            (2U)\r
+#define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */\r
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */\r
+#define PWR_SCR_CWUF2_Pos            (1U)\r
+#define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */\r
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */\r
+#define PWR_SCR_CWUF1_Pos            (0U)\r
+#define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */\r
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */\r
+\r
+/********************  Bit definition for PWR_PUCRA register  ********************/\r
+#define PWR_PUCRA_PA15_Pos           (15U)\r
+#define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */\r
+#define PWR_PUCRA_PA13_Pos           (13U)\r
+#define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */\r
+#define PWR_PUCRA_PA12_Pos           (12U)\r
+#define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */\r
+#define PWR_PUCRA_PA11_Pos           (11U)\r
+#define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */\r
+#define PWR_PUCRA_PA10_Pos           (10U)\r
+#define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */\r
+#define PWR_PUCRA_PA9_Pos            (9U)\r
+#define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */\r
+#define PWR_PUCRA_PA8_Pos            (8U)\r
+#define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */\r
+#define PWR_PUCRA_PA7_Pos            (7U)\r
+#define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */\r
+#define PWR_PUCRA_PA6_Pos            (6U)\r
+#define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */\r
+#define PWR_PUCRA_PA5_Pos            (5U)\r
+#define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */\r
+#define PWR_PUCRA_PA4_Pos            (4U)\r
+#define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */\r
+#define PWR_PUCRA_PA3_Pos            (3U)\r
+#define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */\r
+#define PWR_PUCRA_PA2_Pos            (2U)\r
+#define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */\r
+#define PWR_PUCRA_PA1_Pos            (1U)\r
+#define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */\r
+#define PWR_PUCRA_PA0_Pos            (0U)\r
+#define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRA register  ********************/\r
+#define PWR_PDCRA_PA14_Pos           (14U)\r
+#define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */\r
+#define PWR_PDCRA_PA12_Pos           (12U)\r
+#define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */\r
+#define PWR_PDCRA_PA11_Pos           (11U)\r
+#define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */\r
+#define PWR_PDCRA_PA10_Pos           (10U)\r
+#define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */\r
+#define PWR_PDCRA_PA9_Pos            (9U)\r
+#define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */\r
+#define PWR_PDCRA_PA8_Pos            (8U)\r
+#define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */\r
+#define PWR_PDCRA_PA7_Pos            (7U)\r
+#define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */\r
+#define PWR_PDCRA_PA6_Pos            (6U)\r
+#define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */\r
+#define PWR_PDCRA_PA5_Pos            (5U)\r
+#define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */\r
+#define PWR_PDCRA_PA4_Pos            (4U)\r
+#define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */\r
+#define PWR_PDCRA_PA3_Pos            (3U)\r
+#define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */\r
+#define PWR_PDCRA_PA2_Pos            (2U)\r
+#define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */\r
+#define PWR_PDCRA_PA1_Pos            (1U)\r
+#define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */\r
+#define PWR_PDCRA_PA0_Pos            (0U)\r
+#define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */\r
+\r
+/********************  Bit definition for PWR_PUCRB register  ********************/\r
+#define PWR_PUCRB_PB15_Pos           (15U)\r
+#define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */\r
+#define PWR_PUCRB_PB14_Pos           (14U)\r
+#define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */\r
+#define PWR_PUCRB_PB13_Pos           (13U)\r
+#define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */\r
+#define PWR_PUCRB_PB12_Pos           (12U)\r
+#define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */\r
+#define PWR_PUCRB_PB11_Pos           (11U)\r
+#define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */\r
+#define PWR_PUCRB_PB10_Pos           (10U)\r
+#define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */\r
+#define PWR_PUCRB_PB9_Pos            (9U)\r
+#define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */\r
+#define PWR_PUCRB_PB8_Pos            (8U)\r
+#define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */\r
+#define PWR_PUCRB_PB7_Pos            (7U)\r
+#define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */\r
+#define PWR_PUCRB_PB6_Pos            (6U)\r
+#define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */\r
+#define PWR_PUCRB_PB5_Pos            (5U)\r
+#define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */\r
+#define PWR_PUCRB_PB4_Pos            (4U)\r
+#define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */\r
+#define PWR_PUCRB_PB3_Pos            (3U)\r
+#define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */\r
+#define PWR_PUCRB_PB2_Pos            (2U)\r
+#define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */\r
+#define PWR_PUCRB_PB1_Pos            (1U)\r
+#define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */\r
+#define PWR_PUCRB_PB0_Pos            (0U)\r
+#define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRB register  ********************/\r
+#define PWR_PDCRB_PB15_Pos           (15U)\r
+#define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */\r
+#define PWR_PDCRB_PB14_Pos           (14U)\r
+#define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */\r
+#define PWR_PDCRB_PB13_Pos           (13U)\r
+#define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */\r
+#define PWR_PDCRB_PB12_Pos           (12U)\r
+#define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */\r
+#define PWR_PDCRB_PB11_Pos           (11U)\r
+#define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */\r
+#define PWR_PDCRB_PB10_Pos           (10U)\r
+#define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */\r
+#define PWR_PDCRB_PB9_Pos            (9U)\r
+#define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */\r
+#define PWR_PDCRB_PB8_Pos            (8U)\r
+#define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */\r
+#define PWR_PDCRB_PB7_Pos            (7U)\r
+#define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */\r
+#define PWR_PDCRB_PB6_Pos            (6U)\r
+#define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */\r
+#define PWR_PDCRB_PB5_Pos            (5U)\r
+#define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */\r
+#define PWR_PDCRB_PB3_Pos            (3U)\r
+#define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */\r
+#define PWR_PDCRB_PB2_Pos            (2U)\r
+#define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */\r
+#define PWR_PDCRB_PB1_Pos            (1U)\r
+#define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */\r
+#define PWR_PDCRB_PB0_Pos            (0U)\r
+#define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */\r
+\r
+/********************  Bit definition for PWR_PUCRC register  ********************/\r
+#define PWR_PUCRC_PC15_Pos           (15U)\r
+#define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */\r
+#define PWR_PUCRC_PC14_Pos           (14U)\r
+#define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */\r
+#define PWR_PUCRC_PC13_Pos           (13U)\r
+#define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */\r
+#define PWR_PUCRC_PC12_Pos           (12U)\r
+#define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */\r
+#define PWR_PUCRC_PC11_Pos           (11U)\r
+#define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */\r
+#define PWR_PUCRC_PC10_Pos           (10U)\r
+#define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */\r
+#define PWR_PUCRC_PC9_Pos            (9U)\r
+#define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */\r
+#define PWR_PUCRC_PC8_Pos            (8U)\r
+#define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */\r
+#define PWR_PUCRC_PC7_Pos            (7U)\r
+#define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */\r
+#define PWR_PUCRC_PC6_Pos            (6U)\r
+#define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */\r
+#define PWR_PUCRC_PC5_Pos            (5U)\r
+#define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */\r
+#define PWR_PUCRC_PC4_Pos            (4U)\r
+#define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */\r
+#define PWR_PUCRC_PC3_Pos            (3U)\r
+#define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */\r
+#define PWR_PUCRC_PC2_Pos            (2U)\r
+#define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */\r
+#define PWR_PUCRC_PC1_Pos            (1U)\r
+#define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */\r
+#define PWR_PUCRC_PC0_Pos            (0U)\r
+#define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRC register  ********************/\r
+#define PWR_PDCRC_PC15_Pos           (15U)\r
+#define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */\r
+#define PWR_PDCRC_PC14_Pos           (14U)\r
+#define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */\r
+#define PWR_PDCRC_PC13_Pos           (13U)\r
+#define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */\r
+#define PWR_PDCRC_PC12_Pos           (12U)\r
+#define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */\r
+#define PWR_PDCRC_PC11_Pos           (11U)\r
+#define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */\r
+#define PWR_PDCRC_PC10_Pos           (10U)\r
+#define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */\r
+#define PWR_PDCRC_PC9_Pos            (9U)\r
+#define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */\r
+#define PWR_PDCRC_PC8_Pos            (8U)\r
+#define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */\r
+#define PWR_PDCRC_PC7_Pos            (7U)\r
+#define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */\r
+#define PWR_PDCRC_PC6_Pos            (6U)\r
+#define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */\r
+#define PWR_PDCRC_PC5_Pos            (5U)\r
+#define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */\r
+#define PWR_PDCRC_PC4_Pos            (4U)\r
+#define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */\r
+#define PWR_PDCRC_PC3_Pos            (3U)\r
+#define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */\r
+#define PWR_PDCRC_PC2_Pos            (2U)\r
+#define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */\r
+#define PWR_PDCRC_PC1_Pos            (1U)\r
+#define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */\r
+#define PWR_PDCRC_PC0_Pos            (0U)\r
+#define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */\r
+\r
+/********************  Bit definition for PWR_PUCRD register  ********************/\r
+#define PWR_PUCRD_PD15_Pos           (15U)\r
+#define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */\r
+#define PWR_PUCRD_PD14_Pos           (14U)\r
+#define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */\r
+#define PWR_PUCRD_PD13_Pos           (13U)\r
+#define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */\r
+#define PWR_PUCRD_PD12_Pos           (12U)\r
+#define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */\r
+#define PWR_PUCRD_PD11_Pos           (11U)\r
+#define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */\r
+#define PWR_PUCRD_PD10_Pos           (10U)\r
+#define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */\r
+#define PWR_PUCRD_PD9_Pos            (9U)\r
+#define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */\r
+#define PWR_PUCRD_PD8_Pos            (8U)\r
+#define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */\r
+#define PWR_PUCRD_PD7_Pos            (7U)\r
+#define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */\r
+#define PWR_PUCRD_PD6_Pos            (6U)\r
+#define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */\r
+#define PWR_PUCRD_PD5_Pos            (5U)\r
+#define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */\r
+#define PWR_PUCRD_PD4_Pos            (4U)\r
+#define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */\r
+#define PWR_PUCRD_PD3_Pos            (3U)\r
+#define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */\r
+#define PWR_PUCRD_PD2_Pos            (2U)\r
+#define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */\r
+#define PWR_PUCRD_PD1_Pos            (1U)\r
+#define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */\r
+#define PWR_PUCRD_PD0_Pos            (0U)\r
+#define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRD register  ********************/\r
+#define PWR_PDCRD_PD15_Pos           (15U)\r
+#define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */\r
+#define PWR_PDCRD_PD14_Pos           (14U)\r
+#define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */\r
+#define PWR_PDCRD_PD13_Pos           (13U)\r
+#define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */\r
+#define PWR_PDCRD_PD12_Pos           (12U)\r
+#define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */\r
+#define PWR_PDCRD_PD11_Pos           (11U)\r
+#define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */\r
+#define PWR_PDCRD_PD10_Pos           (10U)\r
+#define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */\r
+#define PWR_PDCRD_PD9_Pos            (9U)\r
+#define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */\r
+#define PWR_PDCRD_PD8_Pos            (8U)\r
+#define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */\r
+#define PWR_PDCRD_PD7_Pos            (7U)\r
+#define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */\r
+#define PWR_PDCRD_PD6_Pos            (6U)\r
+#define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */\r
+#define PWR_PDCRD_PD5_Pos            (5U)\r
+#define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */\r
+#define PWR_PDCRD_PD4_Pos            (4U)\r
+#define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */\r
+#define PWR_PDCRD_PD3_Pos            (3U)\r
+#define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */\r
+#define PWR_PDCRD_PD2_Pos            (2U)\r
+#define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */\r
+#define PWR_PDCRD_PD1_Pos            (1U)\r
+#define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */\r
+#define PWR_PDCRD_PD0_Pos            (0U)\r
+#define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */\r
+\r
+/********************  Bit definition for PWR_PUCRE register  ********************/\r
+#define PWR_PUCRE_PE15_Pos           (15U)\r
+#define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */\r
+#define PWR_PUCRE_PE14_Pos           (14U)\r
+#define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */\r
+#define PWR_PUCRE_PE13_Pos           (13U)\r
+#define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */\r
+#define PWR_PUCRE_PE12_Pos           (12U)\r
+#define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */\r
+#define PWR_PUCRE_PE11_Pos           (11U)\r
+#define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */\r
+#define PWR_PUCRE_PE10_Pos           (10U)\r
+#define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */\r
+#define PWR_PUCRE_PE9_Pos            (9U)\r
+#define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */\r
+#define PWR_PUCRE_PE8_Pos            (8U)\r
+#define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */\r
+#define PWR_PUCRE_PE7_Pos            (7U)\r
+#define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */\r
+#define PWR_PUCRE_PE6_Pos            (6U)\r
+#define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */\r
+#define PWR_PUCRE_PE5_Pos            (5U)\r
+#define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */\r
+#define PWR_PUCRE_PE4_Pos            (4U)\r
+#define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */\r
+#define PWR_PUCRE_PE3_Pos            (3U)\r
+#define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */\r
+#define PWR_PUCRE_PE2_Pos            (2U)\r
+#define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */\r
+#define PWR_PUCRE_PE1_Pos            (1U)\r
+#define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */\r
+#define PWR_PUCRE_PE0_Pos            (0U)\r
+#define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRE register  ********************/\r
+#define PWR_PDCRE_PE15_Pos           (15U)\r
+#define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */\r
+#define PWR_PDCRE_PE14_Pos           (14U)\r
+#define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */\r
+#define PWR_PDCRE_PE13_Pos           (13U)\r
+#define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */\r
+#define PWR_PDCRE_PE12_Pos           (12U)\r
+#define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */\r
+#define PWR_PDCRE_PE11_Pos           (11U)\r
+#define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */\r
+#define PWR_PDCRE_PE10_Pos           (10U)\r
+#define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */\r
+#define PWR_PDCRE_PE9_Pos            (9U)\r
+#define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */\r
+#define PWR_PDCRE_PE8_Pos            (8U)\r
+#define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */\r
+#define PWR_PDCRE_PE7_Pos            (7U)\r
+#define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */\r
+#define PWR_PDCRE_PE6_Pos            (6U)\r
+#define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */\r
+#define PWR_PDCRE_PE5_Pos            (5U)\r
+#define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */\r
+#define PWR_PDCRE_PE4_Pos            (4U)\r
+#define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */\r
+#define PWR_PDCRE_PE3_Pos            (3U)\r
+#define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */\r
+#define PWR_PDCRE_PE2_Pos            (2U)\r
+#define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */\r
+#define PWR_PDCRE_PE1_Pos            (1U)\r
+#define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */\r
+#define PWR_PDCRE_PE0_Pos            (0U)\r
+#define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */\r
+\r
+/********************  Bit definition for PWR_PUCRF register  ********************/\r
+#define PWR_PUCRF_PF15_Pos           (15U)\r
+#define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */\r
+#define PWR_PUCRF_PF14_Pos           (14U)\r
+#define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */\r
+#define PWR_PUCRF_PF13_Pos           (13U)\r
+#define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */\r
+#define PWR_PUCRF_PF12_Pos           (12U)\r
+#define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */\r
+#define PWR_PUCRF_PF11_Pos           (11U)\r
+#define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */\r
+#define PWR_PUCRF_PF10_Pos           (10U)\r
+#define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */\r
+#define PWR_PUCRF_PF9_Pos            (9U)\r
+#define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */\r
+#define PWR_PUCRF_PF8_Pos            (8U)\r
+#define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */\r
+#define PWR_PUCRF_PF7_Pos            (7U)\r
+#define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */\r
+#define PWR_PUCRF_PF6_Pos            (6U)\r
+#define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */\r
+#define PWR_PUCRF_PF5_Pos            (5U)\r
+#define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */\r
+#define PWR_PUCRF_PF4_Pos            (4U)\r
+#define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */\r
+#define PWR_PUCRF_PF3_Pos            (3U)\r
+#define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */\r
+#define PWR_PUCRF_PF2_Pos            (2U)\r
+#define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */\r
+#define PWR_PUCRF_PF1_Pos            (1U)\r
+#define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */\r
+#define PWR_PUCRF_PF0_Pos            (0U)\r
+#define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRF register  ********************/\r
+#define PWR_PDCRF_PF15_Pos           (15U)\r
+#define PWR_PDCRF_PF15_Msk           (0x1UL << PWR_PDCRF_PF15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */\r
+#define PWR_PDCRF_PF14_Pos           (14U)\r
+#define PWR_PDCRF_PF14_Msk           (0x1UL << PWR_PDCRF_PF14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */\r
+#define PWR_PDCRF_PF13_Pos           (13U)\r
+#define PWR_PDCRF_PF13_Msk           (0x1UL << PWR_PDCRF_PF13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */\r
+#define PWR_PDCRF_PF12_Pos           (12U)\r
+#define PWR_PDCRF_PF12_Msk           (0x1UL << PWR_PDCRF_PF12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */\r
+#define PWR_PDCRF_PF11_Pos           (11U)\r
+#define PWR_PDCRF_PF11_Msk           (0x1UL << PWR_PDCRF_PF11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */\r
+#define PWR_PDCRF_PF10_Pos           (10U)\r
+#define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */\r
+#define PWR_PDCRF_PF9_Pos            (9U)\r
+#define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */\r
+#define PWR_PDCRF_PF8_Pos            (8U)\r
+#define PWR_PDCRF_PF8_Msk            (0x1UL << PWR_PDCRF_PF8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */\r
+#define PWR_PDCRF_PF7_Pos            (7U)\r
+#define PWR_PDCRF_PF7_Msk            (0x1UL << PWR_PDCRF_PF7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */\r
+#define PWR_PDCRF_PF6_Pos            (6U)\r
+#define PWR_PDCRF_PF6_Msk            (0x1UL << PWR_PDCRF_PF6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */\r
+#define PWR_PDCRF_PF5_Pos            (5U)\r
+#define PWR_PDCRF_PF5_Msk            (0x1UL << PWR_PDCRF_PF5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */\r
+#define PWR_PDCRF_PF4_Pos            (4U)\r
+#define PWR_PDCRF_PF4_Msk            (0x1UL << PWR_PDCRF_PF4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */\r
+#define PWR_PDCRF_PF3_Pos            (3U)\r
+#define PWR_PDCRF_PF3_Msk            (0x1UL << PWR_PDCRF_PF3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */\r
+#define PWR_PDCRF_PF2_Pos            (2U)\r
+#define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */\r
+#define PWR_PDCRF_PF1_Pos            (1U)\r
+#define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */\r
+#define PWR_PDCRF_PF0_Pos            (0U)\r
+#define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */\r
+\r
+/********************  Bit definition for PWR_PUCRG register  ********************/\r
+#define PWR_PUCRG_PG15_Pos           (15U)\r
+#define PWR_PUCRG_PG15_Msk           (0x1UL << PWR_PUCRG_PG15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */\r
+#define PWR_PUCRG_PG14_Pos           (14U)\r
+#define PWR_PUCRG_PG14_Msk           (0x1UL << PWR_PUCRG_PG14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */\r
+#define PWR_PUCRG_PG13_Pos           (13U)\r
+#define PWR_PUCRG_PG13_Msk           (0x1UL << PWR_PUCRG_PG13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */\r
+#define PWR_PUCRG_PG12_Pos           (12U)\r
+#define PWR_PUCRG_PG12_Msk           (0x1UL << PWR_PUCRG_PG12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */\r
+#define PWR_PUCRG_PG11_Pos           (11U)\r
+#define PWR_PUCRG_PG11_Msk           (0x1UL << PWR_PUCRG_PG11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */\r
+#define PWR_PUCRG_PG10_Pos           (10U)\r
+#define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */\r
+#define PWR_PUCRG_PG9_Pos            (9U)\r
+#define PWR_PUCRG_PG9_Msk            (0x1UL << PWR_PUCRG_PG9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */\r
+#define PWR_PUCRG_PG8_Pos            (8U)\r
+#define PWR_PUCRG_PG8_Msk            (0x1UL << PWR_PUCRG_PG8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */\r
+#define PWR_PUCRG_PG7_Pos            (7U)\r
+#define PWR_PUCRG_PG7_Msk            (0x1UL << PWR_PUCRG_PG7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */\r
+#define PWR_PUCRG_PG6_Pos            (6U)\r
+#define PWR_PUCRG_PG6_Msk            (0x1UL << PWR_PUCRG_PG6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */\r
+#define PWR_PUCRG_PG5_Pos            (5U)\r
+#define PWR_PUCRG_PG5_Msk            (0x1UL << PWR_PUCRG_PG5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */\r
+#define PWR_PUCRG_PG4_Pos            (4U)\r
+#define PWR_PUCRG_PG4_Msk            (0x1UL << PWR_PUCRG_PG4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */\r
+#define PWR_PUCRG_PG3_Pos            (3U)\r
+#define PWR_PUCRG_PG3_Msk            (0x1UL << PWR_PUCRG_PG3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */\r
+#define PWR_PUCRG_PG2_Pos            (2U)\r
+#define PWR_PUCRG_PG2_Msk            (0x1UL << PWR_PUCRG_PG2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */\r
+#define PWR_PUCRG_PG1_Pos            (1U)\r
+#define PWR_PUCRG_PG1_Msk            (0x1UL << PWR_PUCRG_PG1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */\r
+#define PWR_PUCRG_PG0_Pos            (0U)\r
+#define PWR_PUCRG_PG0_Msk            (0x1UL << PWR_PUCRG_PG0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRG register  ********************/\r
+#define PWR_PDCRG_PG15_Pos           (15U)\r
+#define PWR_PDCRG_PG15_Msk           (0x1UL << PWR_PDCRG_PG15_Pos)             /*!< 0x00008000 */\r
+#define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */\r
+#define PWR_PDCRG_PG14_Pos           (14U)\r
+#define PWR_PDCRG_PG14_Msk           (0x1UL << PWR_PDCRG_PG14_Pos)             /*!< 0x00004000 */\r
+#define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */\r
+#define PWR_PDCRG_PG13_Pos           (13U)\r
+#define PWR_PDCRG_PG13_Msk           (0x1UL << PWR_PDCRG_PG13_Pos)             /*!< 0x00002000 */\r
+#define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */\r
+#define PWR_PDCRG_PG12_Pos           (12U)\r
+#define PWR_PDCRG_PG12_Msk           (0x1UL << PWR_PDCRG_PG12_Pos)             /*!< 0x00001000 */\r
+#define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */\r
+#define PWR_PDCRG_PG11_Pos           (11U)\r
+#define PWR_PDCRG_PG11_Msk           (0x1UL << PWR_PDCRG_PG11_Pos)             /*!< 0x00000800 */\r
+#define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */\r
+#define PWR_PDCRG_PG10_Pos           (10U)\r
+#define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */\r
+#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */\r
+#define PWR_PDCRG_PG9_Pos            (9U)\r
+#define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */\r
+#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */\r
+#define PWR_PDCRG_PG8_Pos            (8U)\r
+#define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */\r
+#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */\r
+#define PWR_PDCRG_PG7_Pos            (7U)\r
+#define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */\r
+#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */\r
+#define PWR_PDCRG_PG6_Pos            (6U)\r
+#define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */\r
+#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */\r
+#define PWR_PDCRG_PG5_Pos            (5U)\r
+#define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */\r
+#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */\r
+#define PWR_PDCRG_PG4_Pos            (4U)\r
+#define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */\r
+#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */\r
+#define PWR_PDCRG_PG3_Pos            (3U)\r
+#define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */\r
+#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */\r
+#define PWR_PDCRG_PG2_Pos            (2U)\r
+#define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */\r
+#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */\r
+#define PWR_PDCRG_PG1_Pos            (1U)\r
+#define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */\r
+#define PWR_PDCRG_PG0_Pos            (0U)\r
+#define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */\r
+\r
+/********************  Bit definition for PWR_PUCRH register  ********************/\r
+#define PWR_PUCRH_PH1_Pos            (1U)\r
+#define PWR_PUCRH_PH1_Msk            (0x1UL << PWR_PUCRH_PH1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */\r
+#define PWR_PUCRH_PH0_Pos            (0U)\r
+#define PWR_PUCRH_PH0_Msk            (0x1UL << PWR_PUCRH_PH0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */\r
+\r
+/********************  Bit definition for PWR_PDCRH register  ********************/\r
+#define PWR_PDCRH_PH1_Pos            (1U)\r
+#define PWR_PDCRH_PH1_Msk            (0x1UL << PWR_PDCRH_PH1_Pos)              /*!< 0x00000002 */\r
+#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */\r
+#define PWR_PDCRH_PH0_Pos            (0U)\r
+#define PWR_PDCRH_PH0_Msk            (0x1UL << PWR_PDCRH_PH0_Pos)              /*!< 0x00000001 */\r
+#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         Reset and Clock Control                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*\r
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)\r
+*/\r
+#define RCC_PLLSAI1_SUPPORT\r
+#define RCC_PLLP_SUPPORT\r
+#define RCC_PLLSAI2_SUPPORT\r
+\r
+/********************  Bit definition for RCC_CR register  ********************/\r
+#define RCC_CR_MSION_Pos                     (0U)\r
+#define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */\r
+#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */\r
+#define RCC_CR_MSIRDY_Pos                    (1U)\r
+#define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */\r
+#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */\r
+#define RCC_CR_MSIPLLEN_Pos                  (2U)\r
+#define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */\r
+#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */\r
+#define RCC_CR_MSIRGSEL_Pos                  (3U)\r
+#define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */\r
+#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */\r
+\r
+/*!< MSIRANGE configuration : 12 frequency ranges available */\r
+#define RCC_CR_MSIRANGE_Pos                  (4U)\r
+#define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */\r
+#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */\r
+#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */\r
+#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */\r
+#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */\r
+#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */\r
+#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */\r
+#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */\r
+#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */\r
+#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */\r
+#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */\r
+#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */\r
+#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */\r
+#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */\r
+\r
+#define RCC_CR_HSION_Pos                     (8U)\r
+#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */\r
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */\r
+#define RCC_CR_HSIKERON_Pos                  (9U)\r
+#define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */\r
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */\r
+#define RCC_CR_HSIRDY_Pos                    (10U)\r
+#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */\r
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */\r
+#define RCC_CR_HSIASFS_Pos                   (11U)\r
+#define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */\r
+#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */\r
+\r
+#define RCC_CR_HSEON_Pos                     (16U)\r
+#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */\r
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */\r
+#define RCC_CR_HSERDY_Pos                    (17U)\r
+#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */\r
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */\r
+#define RCC_CR_HSEBYP_Pos                    (18U)\r
+#define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */\r
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */\r
+#define RCC_CR_CSSON_Pos                     (19U)\r
+#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */\r
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */\r
+\r
+#define RCC_CR_PLLON_Pos                     (24U)\r
+#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */\r
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */\r
+#define RCC_CR_PLLRDY_Pos                    (25U)\r
+#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */\r
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */\r
+#define RCC_CR_PLLSAI1ON_Pos                 (26U)\r
+#define RCC_CR_PLLSAI1ON_Msk                 (0x1UL << RCC_CR_PLLSAI1ON_Pos)   /*!< 0x04000000 */\r
+#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */\r
+#define RCC_CR_PLLSAI1RDY_Pos                (27U)\r
+#define RCC_CR_PLLSAI1RDY_Msk                (0x1UL << RCC_CR_PLLSAI1RDY_Pos)  /*!< 0x08000000 */\r
+#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */\r
+#define RCC_CR_PLLSAI2ON_Pos                 (28U)\r
+#define RCC_CR_PLLSAI2ON_Msk                 (0x1UL << RCC_CR_PLLSAI2ON_Pos)   /*!< 0x10000000 */\r
+#define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */\r
+#define RCC_CR_PLLSAI2RDY_Pos                (29U)\r
+#define RCC_CR_PLLSAI2RDY_Msk                (0x1UL << RCC_CR_PLLSAI2RDY_Pos)  /*!< 0x20000000 */\r
+#define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */\r
+\r
+/********************  Bit definition for RCC_ICSCR register  ***************/\r
+/*!< MSICAL configuration */\r
+#define RCC_ICSCR_MSICAL_Pos                 (0U)\r
+#define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */\r
+#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */\r
+#define RCC_ICSCR_MSICAL_0                   (0x01UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000001 */\r
+#define RCC_ICSCR_MSICAL_1                   (0x02UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000002 */\r
+#define RCC_ICSCR_MSICAL_2                   (0x04UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000004 */\r
+#define RCC_ICSCR_MSICAL_3                   (0x08UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000008 */\r
+#define RCC_ICSCR_MSICAL_4                   (0x10UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000010 */\r
+#define RCC_ICSCR_MSICAL_5                   (0x20UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000020 */\r
+#define RCC_ICSCR_MSICAL_6                   (0x40UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000040 */\r
+#define RCC_ICSCR_MSICAL_7                   (0x80UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000080 */\r
+\r
+/*!< MSITRIM configuration */\r
+#define RCC_ICSCR_MSITRIM_Pos                (8U)\r
+#define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */\r
+#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */\r
+#define RCC_ICSCR_MSITRIM_0                  (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */\r
+#define RCC_ICSCR_MSITRIM_1                  (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */\r
+#define RCC_ICSCR_MSITRIM_2                  (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */\r
+#define RCC_ICSCR_MSITRIM_3                  (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */\r
+#define RCC_ICSCR_MSITRIM_4                  (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */\r
+#define RCC_ICSCR_MSITRIM_5                  (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */\r
+#define RCC_ICSCR_MSITRIM_6                  (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */\r
+#define RCC_ICSCR_MSITRIM_7                  (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */\r
+\r
+/*!< HSICAL configuration */\r
+#define RCC_ICSCR_HSICAL_Pos                 (16U)\r
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */\r
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */\r
+#define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */\r
+#define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */\r
+#define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */\r
+#define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */\r
+#define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */\r
+#define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */\r
+#define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */\r
+#define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */\r
+\r
+/*!< HSITRIM configuration */\r
+#define RCC_ICSCR_HSITRIM_Pos                (24U)\r
+#define RCC_ICSCR_HSITRIM_Msk                (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */\r
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */\r
+#define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */\r
+#define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */\r
+#define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */\r
+#define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */\r
+#define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */\r
+\r
+/********************  Bit definition for RCC_CFGR register  ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_Pos                      (0U)\r
+#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */\r
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */\r
+#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */\r
+\r
+#define RCC_CFGR_SW_MSI                      (0x00000000UL)                    /*!< MSI oscillator selection as system clock */\r
+#define RCC_CFGR_SW_HSI                      (0x00000001UL)                    /*!< HSI16 oscillator selection as system clock */\r
+#define RCC_CFGR_SW_HSE                      (0x00000002UL)                    /*!< HSE oscillator selection as system clock */\r
+#define RCC_CFGR_SW_PLL                      (0x00000003UL)                    /*!< PLL selection as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_Pos                     (2U)\r
+#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */\r
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */\r
+#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */\r
+\r
+#define RCC_CFGR_SWS_MSI                     (0x00000000UL)                    /*!< MSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSI                     (0x00000004UL)                    /*!< HSI16 oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE                     (0x00000008UL)                    /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL                     (0x0000000CUL)                    /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE_Pos                    (4U)\r
+#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */\r
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */\r
+#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */\r
+#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */\r
+#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000UL)                    /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080UL)                    /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090UL)                    /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0UL)                    /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0UL)                    /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0UL)                    /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0UL)                    /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0UL)                    /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0UL)                    /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1_Pos                   (8U)\r
+#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */\r
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */\r
+#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */\r
+#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400UL)                    /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500UL)                    /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600UL)                    /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700UL)                    /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2_Pos                   (11U)\r
+#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */\r
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */\r
+#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */\r
+#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000UL)                    /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800UL)                    /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000UL)                    /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800UL)                    /*!< HCLK divided by 16 */\r
+\r
+#define RCC_CFGR_STOPWUCK_Pos                (15U)\r
+#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */\r
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */\r
+\r
+/*!< MCOSEL configuration */\r
+#define RCC_CFGR_MCOSEL_Pos                  (24U)\r
+#define RCC_CFGR_MCOSEL_Msk                  (0x7UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x07000000 */\r
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [2:0] bits (Clock output selection) */\r
+#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */\r
+#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */\r
+#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */\r
+\r
+#define RCC_CFGR_MCOPRE_Pos                  (28U)\r
+#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */\r
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */\r
+#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */\r
+#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */\r
+#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */\r
+\r
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000UL)                    /*!< MCO is divided by 1 */\r
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000UL)                    /*!< MCO is divided by 2 */\r
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000UL)                    /*!< MCO is divided by 4 */\r
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000UL)                    /*!< MCO is divided by 8 */\r
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000UL)                    /*!< MCO is divided by 16 */\r
+\r
+/* Legacy aliases */\r
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE\r
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1\r
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2\r
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4\r
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8\r
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16\r
+\r
+/********************  Bit definition for RCC_PLLCFGR register  ***************/\r
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)\r
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */\r
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk\r
+\r
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)\r
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */\r
+#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */\r
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)\r
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */\r
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */\r
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)\r
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */\r
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */\r
+\r
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)\r
+#define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000070 */\r
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk\r
+#define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */\r
+#define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */\r
+#define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */\r
+\r
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)\r
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */\r
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk\r
+#define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */\r
+#define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */\r
+#define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */\r
+#define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */\r
+#define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */\r
+#define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */\r
+#define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */\r
+\r
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)\r
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk\r
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)\r
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */\r
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk\r
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)\r
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */\r
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk\r
+\r
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)\r
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */\r
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk\r
+#define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */\r
+#define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */\r
+\r
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)\r
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk\r
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)\r
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */\r
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk\r
+#define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */\r
+#define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */\r
+\r
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */\r
+\r
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)\r
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk\r
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)\r
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk\r
+\r
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)\r
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk\r
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)\r
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk\r
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */\r
+\r
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)\r
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk\r
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)\r
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk\r
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */\r
+\r
+/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FUL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */\r
+\r
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)\r
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk\r
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)\r
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk\r
+\r
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)\r
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk\r
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)\r
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk\r
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */\r
+\r
+/********************  Bit definition for RCC_CIER register  ******************/\r
+#define RCC_CIER_LSIRDYIE_Pos                (0U)\r
+#define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */\r
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk\r
+#define RCC_CIER_LSERDYIE_Pos                (1U)\r
+#define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */\r
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk\r
+#define RCC_CIER_MSIRDYIE_Pos                (2U)\r
+#define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)  /*!< 0x00000004 */\r
+#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk\r
+#define RCC_CIER_HSIRDYIE_Pos                (3U)\r
+#define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */\r
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk\r
+#define RCC_CIER_HSERDYIE_Pos                (4U)\r
+#define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */\r
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk\r
+#define RCC_CIER_PLLRDYIE_Pos                (5U)\r
+#define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */\r
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk\r
+#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)\r
+#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */\r
+#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk\r
+#define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)\r
+#define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1UL << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */\r
+#define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk\r
+#define RCC_CIER_LSECSSIE_Pos                (9U)\r
+#define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */\r
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk\r
+\r
+/********************  Bit definition for RCC_CIFR register  ******************/\r
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)\r
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */\r
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk\r
+#define RCC_CIFR_LSERDYF_Pos                 (1U)\r
+#define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */\r
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk\r
+#define RCC_CIFR_MSIRDYF_Pos                 (2U)\r
+#define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */\r
+#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk\r
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)\r
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */\r
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk\r
+#define RCC_CIFR_HSERDYF_Pos                 (4U)\r
+#define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */\r
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk\r
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)\r
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */\r
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk\r
+#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)\r
+#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */\r
+#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk\r
+#define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)\r
+#define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1UL << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */\r
+#define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk\r
+#define RCC_CIFR_CSSF_Pos                    (8U)\r
+#define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */\r
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk\r
+#define RCC_CIFR_LSECSSF_Pos                 (9U)\r
+#define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */\r
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk\r
+\r
+/********************  Bit definition for RCC_CICR register  ******************/\r
+#define RCC_CICR_LSIRDYC_Pos                 (0U)\r
+#define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */\r
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk\r
+#define RCC_CICR_LSERDYC_Pos                 (1U)\r
+#define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */\r
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk\r
+#define RCC_CICR_MSIRDYC_Pos                 (2U)\r
+#define RCC_CICR_MSIRDYC_Msk                 (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */\r
+#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk\r
+#define RCC_CICR_HSIRDYC_Pos                 (3U)\r
+#define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */\r
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk\r
+#define RCC_CICR_HSERDYC_Pos                 (4U)\r
+#define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */\r
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk\r
+#define RCC_CICR_PLLRDYC_Pos                 (5U)\r
+#define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */\r
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk\r
+#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)\r
+#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */\r
+#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk\r
+#define RCC_CICR_PLLSAI2RDYC_Pos             (7U)\r
+#define RCC_CICR_PLLSAI2RDYC_Msk             (0x1UL << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */\r
+#define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk\r
+#define RCC_CICR_CSSC_Pos                    (8U)\r
+#define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */\r
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk\r
+#define RCC_CICR_LSECSSC_Pos                 (9U)\r
+#define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */\r
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk\r
+\r
+/********************  Bit definition for RCC_AHB1RSTR register  **************/\r
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)\r
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk\r
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)\r
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk\r
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)\r
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk\r
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)\r
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk\r
+#define RCC_AHB1RSTR_TSCRST_Pos              (16U)\r
+#define RCC_AHB1RSTR_TSCRST_Msk              (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk\r
+\r
+/********************  Bit definition for RCC_AHB2RSTR register  **************/\r
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)\r
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk\r
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)\r
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk\r
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)\r
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk\r
+#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)\r
+#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk\r
+#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)\r
+#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk\r
+#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)\r
+#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk\r
+#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)\r
+#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk\r
+#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)\r
+#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk\r
+#define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)\r
+#define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk\r
+#define RCC_AHB2RSTR_ADCRST_Pos              (13U)\r
+#define RCC_AHB2RSTR_ADCRST_Msk              (0x1UL << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */\r
+#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk\r
+#define RCC_AHB2RSTR_RNGRST_Pos              (18U)\r
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */\r
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk\r
+\r
+/********************  Bit definition for RCC_AHB3RSTR register  **************/\r
+#define RCC_AHB3RSTR_FMCRST_Pos              (0U)\r
+#define RCC_AHB3RSTR_FMCRST_Msk              (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk\r
+#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)\r
+#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk\r
+\r
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/\r
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)\r
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk\r
+#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)\r
+#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk\r
+#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)\r
+#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk\r
+#define RCC_APB1RSTR1_TIM5RST_Pos            (3U)\r
+#define RCC_APB1RSTR1_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk\r
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)\r
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk\r
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)\r
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk\r
+#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)\r
+#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk\r
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)\r
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk\r
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)\r
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk\r
+#define RCC_APB1RSTR1_USART3RST_Pos          (18U)\r
+#define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk\r
+#define RCC_APB1RSTR1_UART4RST_Pos           (19U)\r
+#define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk\r
+#define RCC_APB1RSTR1_UART5RST_Pos           (20U)\r
+#define RCC_APB1RSTR1_UART5RST_Msk           (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk\r
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)\r
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk\r
+#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)\r
+#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk\r
+#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)\r
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk\r
+#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)\r
+#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk\r
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)\r
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk\r
+#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)\r
+#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk\r
+#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)\r
+#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk\r
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)\r
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk\r
+\r
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/\r
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)\r
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk\r
+#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)\r
+#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk\r
+#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)\r
+#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk\r
+\r
+/********************  Bit definition for RCC_APB2RSTR register  **************/\r
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)\r
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk\r
+#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)\r
+#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */\r
+#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk\r
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)\r
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk\r
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)\r
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk\r
+#define RCC_APB2RSTR_TIM8RST_Pos             (13U)\r
+#define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk\r
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)\r
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk\r
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)\r
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk\r
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)\r
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk\r
+#define RCC_APB2RSTR_TIM17RST_Pos            (18U)\r
+#define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk\r
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)\r
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk\r
+#define RCC_APB2RSTR_SAI2RST_Pos             (22U)\r
+#define RCC_APB2RSTR_SAI2RST_Msk             (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk\r
+#define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)\r
+#define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */\r
+#define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk\r
+\r
+/********************  Bit definition for RCC_AHB1ENR register  ***************/\r
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)\r
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk\r
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)\r
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk\r
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)\r
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk\r
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)\r
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */\r
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk\r
+#define RCC_AHB1ENR_TSCEN_Pos                (16U)\r
+#define RCC_AHB1ENR_TSCEN_Msk                (0x1UL << RCC_AHB1ENR_TSCEN_Pos)  /*!< 0x00010000 */\r
+#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk\r
+\r
+/********************  Bit definition for RCC_AHB2ENR register  ***************/\r
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)\r
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk\r
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)\r
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk\r
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)\r
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk\r
+#define RCC_AHB2ENR_GPIODEN_Pos              (3U)\r
+#define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk\r
+#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)\r
+#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk\r
+#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)\r
+#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk\r
+#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)\r
+#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk\r
+#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)\r
+#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk\r
+#define RCC_AHB2ENR_OTGFSEN_Pos              (12U)\r
+#define RCC_AHB2ENR_OTGFSEN_Msk              (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk\r
+#define RCC_AHB2ENR_ADCEN_Pos                (13U)\r
+#define RCC_AHB2ENR_ADCEN_Msk                (0x1UL << RCC_AHB2ENR_ADCEN_Pos)  /*!< 0x00002000 */\r
+#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk\r
+#define RCC_AHB2ENR_RNGEN_Pos                (18U)\r
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x00040000 */\r
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk\r
+\r
+/********************  Bit definition for RCC_AHB3ENR register  ***************/\r
+#define RCC_AHB3ENR_FMCEN_Pos                (0U)\r
+#define RCC_AHB3ENR_FMCEN_Msk                (0x1UL << RCC_AHB3ENR_FMCEN_Pos)  /*!< 0x00000001 */\r
+#define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk\r
+#define RCC_AHB3ENR_QSPIEN_Pos               (8U)\r
+#define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk\r
+\r
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/\r
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)\r
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk\r
+#define RCC_APB1ENR1_TIM3EN_Pos              (1U)\r
+#define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk\r
+#define RCC_APB1ENR1_TIM4EN_Pos              (2U)\r
+#define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk\r
+#define RCC_APB1ENR1_TIM5EN_Pos              (3U)\r
+#define RCC_APB1ENR1_TIM5EN_Msk              (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk\r
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)\r
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk\r
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)\r
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk\r
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)\r
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk\r
+#define RCC_APB1ENR1_SPI2EN_Pos              (14U)\r
+#define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk\r
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)\r
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk\r
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)\r
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk\r
+#define RCC_APB1ENR1_USART3EN_Pos            (18U)\r
+#define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk\r
+#define RCC_APB1ENR1_UART4EN_Pos             (19U)\r
+#define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk\r
+#define RCC_APB1ENR1_UART5EN_Pos             (20U)\r
+#define RCC_APB1ENR1_UART5EN_Msk             (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk\r
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)\r
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk\r
+#define RCC_APB1ENR1_I2C2EN_Pos              (22U)\r
+#define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk\r
+#define RCC_APB1ENR1_I2C3EN_Pos              (23U)\r
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk\r
+#define RCC_APB1ENR1_CAN1EN_Pos              (25U)\r
+#define RCC_APB1ENR1_CAN1EN_Msk              (0x1UL << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk\r
+#define RCC_APB1ENR1_PWREN_Pos               (28U)\r
+#define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk\r
+#define RCC_APB1ENR1_DAC1EN_Pos              (29U)\r
+#define RCC_APB1ENR1_DAC1EN_Msk              (0x1UL << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk\r
+#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)\r
+#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk\r
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)\r
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk\r
+\r
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/\r
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)\r
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk\r
+#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)\r
+#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk\r
+#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)\r
+#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk\r
+\r
+/********************  Bit definition for RCC_APB2ENR register  ***************/\r
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)\r
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk\r
+#define RCC_APB2ENR_FWEN_Pos                 (7U)\r
+#define RCC_APB2ENR_FWEN_Msk                 (0x1UL << RCC_APB2ENR_FWEN_Pos)   /*!< 0x00000080 */\r
+#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk\r
+#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)\r
+#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk\r
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)\r
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk\r
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)\r
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk\r
+#define RCC_APB2ENR_TIM8EN_Pos               (13U)\r
+#define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk\r
+#define RCC_APB2ENR_USART1EN_Pos             (14U)\r
+#define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk\r
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)\r
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk\r
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)\r
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk\r
+#define RCC_APB2ENR_TIM17EN_Pos              (18U)\r
+#define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk\r
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)\r
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk\r
+#define RCC_APB2ENR_SAI2EN_Pos               (22U)\r
+#define RCC_APB2ENR_SAI2EN_Msk               (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk\r
+#define RCC_APB2ENR_DFSDM1EN_Pos             (24U)\r
+#define RCC_APB2ENR_DFSDM1EN_Msk             (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */\r
+#define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk\r
+\r
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/\r
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)\r
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk\r
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)\r
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk\r
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)\r
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk\r
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)\r
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk\r
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)\r
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk\r
+#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)\r
+#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk\r
+\r
+/********************  Bit definition for RCC_AHB2SMENR register  *************/\r
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)\r
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk\r
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)\r
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk\r
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)\r
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk\r
+#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)\r
+#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk\r
+#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)\r
+#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk\r
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)\r
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk\r
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)\r
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk\r
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)\r
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk\r
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)\r
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk\r
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)\r
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1UL << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk\r
+#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)\r
+#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */\r
+#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk\r
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)\r
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */\r
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk\r
+\r
+/********************  Bit definition for RCC_AHB3SMENR register  *************/\r
+#define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)\r
+#define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk\r
+#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)\r
+#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk\r
+\r
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/\r
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)\r
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk\r
+#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)\r
+#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk\r
+#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)\r
+#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk\r
+#define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)\r
+#define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk\r
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)\r
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk\r
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)\r
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk\r
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)\r
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk\r
+#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)\r
+#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk\r
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)\r
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk\r
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)\r
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk\r
+#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)\r
+#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk\r
+#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)\r
+#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk\r
+#define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)\r
+#define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk\r
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)\r
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk\r
+#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)\r
+#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk\r
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)\r
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk\r
+#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)\r
+#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk\r
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)\r
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk\r
+#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)\r
+#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk\r
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)\r
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk\r
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)\r
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk\r
+\r
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/\r
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)\r
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk\r
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)\r
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk\r
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)\r
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk\r
+\r
+/********************  Bit definition for RCC_APB2SMENR register  *************/\r
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)\r
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk\r
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)\r
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1UL << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk\r
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)\r
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk\r
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)\r
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk\r
+#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)\r
+#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk\r
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)\r
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk\r
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)\r
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk\r
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)\r
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk\r
+#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)\r
+#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk\r
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)\r
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk\r
+#define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)\r
+#define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk\r
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)\r
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1UL << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */\r
+#define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk\r
+\r
+/********************  Bit definition for RCC_CCIPR register  ******************/\r
+#define RCC_CCIPR_USART1SEL_Pos              (0U)\r
+#define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */\r
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk\r
+#define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */\r
+#define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */\r
+\r
+#define RCC_CCIPR_USART2SEL_Pos              (2U)\r
+#define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */\r
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk\r
+#define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */\r
+#define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */\r
+\r
+#define RCC_CCIPR_USART3SEL_Pos              (4U)\r
+#define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */\r
+#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk\r
+#define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */\r
+#define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */\r
+\r
+#define RCC_CCIPR_UART4SEL_Pos               (6U)\r
+#define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */\r
+#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk\r
+#define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */\r
+#define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */\r
+\r
+#define RCC_CCIPR_UART5SEL_Pos               (8U)\r
+#define RCC_CCIPR_UART5SEL_Msk               (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */\r
+#define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk\r
+#define RCC_CCIPR_UART5SEL_0                 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */\r
+#define RCC_CCIPR_UART5SEL_1                 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */\r
+\r
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)\r
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */\r
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk\r
+#define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */\r
+#define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */\r
+\r
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)\r
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */\r
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk\r
+#define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */\r
+#define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */\r
+\r
+#define RCC_CCIPR_I2C2SEL_Pos                (14U)\r
+#define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */\r
+#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk\r
+#define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */\r
+#define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */\r
+\r
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)\r
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */\r
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk\r
+#define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */\r
+#define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */\r
+\r
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)\r
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */\r
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk\r
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */\r
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */\r
+\r
+#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)\r
+#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */\r
+#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk\r
+#define RCC_CCIPR_LPTIM2SEL_0                (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */\r
+#define RCC_CCIPR_LPTIM2SEL_1                (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */\r
+\r
+#define RCC_CCIPR_SAI1SEL_Pos                (22U)\r
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00C00000 */\r
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk\r
+#define RCC_CCIPR_SAI1SEL_0                  (0x1UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00400000 */\r
+#define RCC_CCIPR_SAI1SEL_1                  (0x2UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00800000 */\r
+\r
+#define RCC_CCIPR_SAI2SEL_Pos                (24U)\r
+#define RCC_CCIPR_SAI2SEL_Msk                (0x3UL << RCC_CCIPR_SAI2SEL_Pos)  /*!< 0x03000000 */\r
+#define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk\r
+#define RCC_CCIPR_SAI2SEL_0                  (0x1UL << RCC_CCIPR_SAI2SEL_Pos)  /*!< 0x01000000 */\r
+#define RCC_CCIPR_SAI2SEL_1                  (0x2UL << RCC_CCIPR_SAI2SEL_Pos)  /*!< 0x02000000 */\r
+\r
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)\r
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */\r
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk\r
+#define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */\r
+#define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */\r
+\r
+#define RCC_CCIPR_ADCSEL_Pos                 (28U)\r
+#define RCC_CCIPR_ADCSEL_Msk                 (0x3UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x30000000 */\r
+#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk\r
+#define RCC_CCIPR_ADCSEL_0                   (0x1UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x10000000 */\r
+#define RCC_CCIPR_ADCSEL_1                   (0x2UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x20000000 */\r
+\r
+#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)\r
+#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */\r
+#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk\r
+\r
+#define RCC_CCIPR_DFSDM1SEL_Pos              (31U)\r
+#define RCC_CCIPR_DFSDM1SEL_Msk              (0x1UL << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */\r
+#define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk\r
+\r
+/********************  Bit definition for RCC_BDCR register  ******************/\r
+#define RCC_BDCR_LSEON_Pos                   (0U)\r
+#define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */\r
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk\r
+#define RCC_BDCR_LSERDY_Pos                  (1U)\r
+#define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */\r
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk\r
+#define RCC_BDCR_LSEBYP_Pos                  (2U)\r
+#define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */\r
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk\r
+\r
+#define RCC_BDCR_LSEDRV_Pos                  (3U)\r
+#define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */\r
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk\r
+#define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */\r
+#define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */\r
+\r
+#define RCC_BDCR_LSECSSON_Pos                (5U)\r
+#define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */\r
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk\r
+#define RCC_BDCR_LSECSSD_Pos                 (6U)\r
+#define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */\r
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk\r
+\r
+#define RCC_BDCR_RTCSEL_Pos                  (8U)\r
+#define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */\r
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk\r
+#define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */\r
+#define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */\r
+\r
+#define RCC_BDCR_RTCEN_Pos                   (15U)\r
+#define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */\r
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk\r
+#define RCC_BDCR_BDRST_Pos                   (16U)\r
+#define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */\r
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk\r
+#define RCC_BDCR_LSCOEN_Pos                  (24U)\r
+#define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */\r
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk\r
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)\r
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */\r
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk\r
+\r
+/********************  Bit definition for RCC_CSR register  *******************/\r
+#define RCC_CSR_LSION_Pos                    (0U)\r
+#define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */\r
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk\r
+#define RCC_CSR_LSIRDY_Pos                   (1U)\r
+#define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */\r
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk\r
+\r
+#define RCC_CSR_MSISRANGE_Pos                (8U)\r
+#define RCC_CSR_MSISRANGE_Msk                (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */\r
+#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk\r
+#define RCC_CSR_MSISRANGE_1                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */\r
+#define RCC_CSR_MSISRANGE_2                  (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */\r
+#define RCC_CSR_MSISRANGE_4                  (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */\r
+#define RCC_CSR_MSISRANGE_8                  (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */\r
+\r
+#define RCC_CSR_RMVF_Pos                     (23U)\r
+#define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */\r
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk\r
+#define RCC_CSR_FWRSTF_Pos                   (24U)\r
+#define RCC_CSR_FWRSTF_Msk                   (0x1UL << RCC_CSR_FWRSTF_Pos)     /*!< 0x01000000 */\r
+#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk\r
+#define RCC_CSR_OBLRSTF_Pos                  (25U)\r
+#define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */\r
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk\r
+#define RCC_CSR_PINRSTF_Pos                  (26U)\r
+#define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */\r
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk\r
+#define RCC_CSR_BORRSTF_Pos                  (27U)\r
+#define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */\r
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk\r
+#define RCC_CSR_SFTRSTF_Pos                  (28U)\r
+#define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */\r
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk\r
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)\r
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */\r
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk\r
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)\r
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */\r
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk\r
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)\r
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */\r
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    RNG                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bits definition for RNG_CR register  *******************/\r
+#define RNG_CR_RNGEN_Pos    (2U)\r
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */\r
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\r
+#define RNG_CR_IE_Pos       (3U)\r
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */\r
+#define RNG_CR_IE           RNG_CR_IE_Msk\r
+\r
+/********************  Bits definition for RNG_SR register  *******************/\r
+#define RNG_SR_DRDY_Pos     (0U)\r
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */\r
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\r
+#define RNG_SR_CECS_Pos     (1U)\r
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */\r
+#define RNG_SR_CECS         RNG_SR_CECS_Msk\r
+#define RNG_SR_SECS_Pos     (2U)\r
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */\r
+#define RNG_SR_SECS         RNG_SR_SECS_Msk\r
+#define RNG_SR_CEIS_Pos     (5U)\r
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */\r
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\r
+#define RNG_SR_SEIS_Pos     (6U)\r
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */\r
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                           Real-Time Clock (RTC)                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*\r
+* @brief Specific device feature definitions\r
+*/\r
+#define RTC_TAMPER1_SUPPORT\r
+#define RTC_TAMPER2_SUPPORT\r
+#define RTC_TAMPER3_SUPPORT\r
+#define RTC_WAKEUP_SUPPORT\r
+#define RTC_BACKUP_SUPPORT\r
+\r
+/********************  Bits definition for RTC_TR register  *******************/\r
+#define RTC_TR_PM_Pos                  (22U)\r
+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */\r
+#define RTC_TR_PM                      RTC_TR_PM_Msk\r
+#define RTC_TR_HT_Pos                  (20U)\r
+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */\r
+#define RTC_TR_HT                      RTC_TR_HT_Msk\r
+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */\r
+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */\r
+#define RTC_TR_HU_Pos                  (16U)\r
+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */\r
+#define RTC_TR_HU                      RTC_TR_HU_Msk\r
+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */\r
+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */\r
+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */\r
+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */\r
+#define RTC_TR_MNT_Pos                 (12U)\r
+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */\r
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk\r
+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */\r
+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */\r
+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */\r
+#define RTC_TR_MNU_Pos                 (8U)\r
+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */\r
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk\r
+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */\r
+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */\r
+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */\r
+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */\r
+#define RTC_TR_ST_Pos                  (4U)\r
+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */\r
+#define RTC_TR_ST                      RTC_TR_ST_Msk\r
+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */\r
+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */\r
+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */\r
+#define RTC_TR_SU_Pos                  (0U)\r
+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */\r
+#define RTC_TR_SU                      RTC_TR_SU_Msk\r
+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */\r
+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */\r
+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */\r
+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */\r
+\r
+/********************  Bits definition for RTC_DR register  *******************/\r
+#define RTC_DR_YT_Pos                  (20U)\r
+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */\r
+#define RTC_DR_YT                      RTC_DR_YT_Msk\r
+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */\r
+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */\r
+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */\r
+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */\r
+#define RTC_DR_YU_Pos                  (16U)\r
+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */\r
+#define RTC_DR_YU                      RTC_DR_YU_Msk\r
+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */\r
+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */\r
+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */\r
+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */\r
+#define RTC_DR_WDU_Pos                 (13U)\r
+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */\r
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk\r
+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */\r
+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */\r
+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */\r
+#define RTC_DR_MT_Pos                  (12U)\r
+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */\r
+#define RTC_DR_MT                      RTC_DR_MT_Msk\r
+#define RTC_DR_MU_Pos                  (8U)\r
+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */\r
+#define RTC_DR_MU                      RTC_DR_MU_Msk\r
+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */\r
+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */\r
+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */\r
+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */\r
+#define RTC_DR_DT_Pos                  (4U)\r
+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */\r
+#define RTC_DR_DT                      RTC_DR_DT_Msk\r
+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */\r
+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */\r
+#define RTC_DR_DU_Pos                  (0U)\r
+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */\r
+#define RTC_DR_DU                      RTC_DR_DU_Msk\r
+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */\r
+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */\r
+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */\r
+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */\r
+\r
+/********************  Bits definition for RTC_CR register  *******************/\r
+#define RTC_CR_ITSE_Pos                (24U)\r
+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */\r
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk\r
+#define RTC_CR_COE_Pos                 (23U)\r
+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */\r
+#define RTC_CR_COE                     RTC_CR_COE_Msk\r
+#define RTC_CR_OSEL_Pos                (21U)\r
+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */\r
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk\r
+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */\r
+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */\r
+#define RTC_CR_POL_Pos                 (20U)\r
+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */\r
+#define RTC_CR_POL                     RTC_CR_POL_Msk\r
+#define RTC_CR_COSEL_Pos               (19U)\r
+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */\r
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk\r
+#define RTC_CR_BKP_Pos                 (18U)\r
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */\r
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk\r
+#define RTC_CR_SUB1H_Pos               (17U)\r
+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */\r
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk\r
+#define RTC_CR_ADD1H_Pos               (16U)\r
+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */\r
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk\r
+#define RTC_CR_TSIE_Pos                (15U)\r
+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */\r
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk\r
+#define RTC_CR_WUTIE_Pos               (14U)\r
+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */\r
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk\r
+#define RTC_CR_ALRBIE_Pos              (13U)\r
+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */\r
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk\r
+#define RTC_CR_ALRAIE_Pos              (12U)\r
+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */\r
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk\r
+#define RTC_CR_TSE_Pos                 (11U)\r
+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */\r
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk\r
+#define RTC_CR_WUTE_Pos                (10U)\r
+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */\r
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk\r
+#define RTC_CR_ALRBE_Pos               (9U)\r
+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */\r
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk\r
+#define RTC_CR_ALRAE_Pos               (8U)\r
+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */\r
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk\r
+#define RTC_CR_FMT_Pos                 (6U)\r
+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */\r
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk\r
+#define RTC_CR_BYPSHAD_Pos             (5U)\r
+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */\r
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk\r
+#define RTC_CR_REFCKON_Pos             (4U)\r
+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */\r
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk\r
+#define RTC_CR_TSEDGE_Pos              (3U)\r
+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */\r
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk\r
+#define RTC_CR_WUCKSEL_Pos             (0U)\r
+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */\r
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk\r
+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */\r
+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */\r
+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */\r
+\r
+/* Legacy defines */\r
+#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos\r
+#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk\r
+#define RTC_CR_BCK                     RTC_CR_BKP\r
+\r
+/********************  Bits definition for RTC_ISR register  ******************/\r
+#define RTC_ISR_ITSF_Pos               (17U)\r
+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */\r
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk\r
+#define RTC_ISR_RECALPF_Pos            (16U)\r
+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */\r
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk\r
+#define RTC_ISR_TAMP3F_Pos             (15U)\r
+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */\r
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk\r
+#define RTC_ISR_TAMP2F_Pos             (14U)\r
+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */\r
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk\r
+#define RTC_ISR_TAMP1F_Pos             (13U)\r
+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */\r
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk\r
+#define RTC_ISR_TSOVF_Pos              (12U)\r
+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */\r
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk\r
+#define RTC_ISR_TSF_Pos                (11U)\r
+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */\r
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk\r
+#define RTC_ISR_WUTF_Pos               (10U)\r
+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */\r
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk\r
+#define RTC_ISR_ALRBF_Pos              (9U)\r
+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */\r
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk\r
+#define RTC_ISR_ALRAF_Pos              (8U)\r
+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */\r
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk\r
+#define RTC_ISR_INIT_Pos               (7U)\r
+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */\r
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk\r
+#define RTC_ISR_INITF_Pos              (6U)\r
+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */\r
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk\r
+#define RTC_ISR_RSF_Pos                (5U)\r
+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */\r
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk\r
+#define RTC_ISR_INITS_Pos              (4U)\r
+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */\r
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk\r
+#define RTC_ISR_SHPF_Pos               (3U)\r
+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */\r
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk\r
+#define RTC_ISR_WUTWF_Pos              (2U)\r
+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */\r
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk\r
+#define RTC_ISR_ALRBWF_Pos             (1U)\r
+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */\r
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk\r
+#define RTC_ISR_ALRAWF_Pos             (0U)\r
+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */\r
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk\r
+\r
+/********************  Bits definition for RTC_PRER register  *****************/\r
+#define RTC_PRER_PREDIV_A_Pos          (16U)\r
+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */\r
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk\r
+#define RTC_PRER_PREDIV_S_Pos          (0U)\r
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */\r
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk\r
+\r
+/********************  Bits definition for RTC_WUTR register  *****************/\r
+#define RTC_WUTR_WUT_Pos               (0U)\r
+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */\r
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk\r
+\r
+/********************  Bits definition for RTC_ALRMAR register  ***************/\r
+#define RTC_ALRMAR_MSK4_Pos            (31U)\r
+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */\r
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk\r
+#define RTC_ALRMAR_WDSEL_Pos           (30U)\r
+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */\r
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk\r
+#define RTC_ALRMAR_DT_Pos              (28U)\r
+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */\r
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk\r
+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */\r
+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */\r
+#define RTC_ALRMAR_DU_Pos              (24U)\r
+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */\r
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk\r
+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */\r
+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */\r
+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */\r
+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */\r
+#define RTC_ALRMAR_MSK3_Pos            (23U)\r
+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */\r
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk\r
+#define RTC_ALRMAR_PM_Pos              (22U)\r
+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */\r
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk\r
+#define RTC_ALRMAR_HT_Pos              (20U)\r
+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */\r
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk\r
+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */\r
+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */\r
+#define RTC_ALRMAR_HU_Pos              (16U)\r
+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */\r
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk\r
+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */\r
+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */\r
+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */\r
+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */\r
+#define RTC_ALRMAR_MSK2_Pos            (15U)\r
+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */\r
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk\r
+#define RTC_ALRMAR_MNT_Pos             (12U)\r
+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */\r
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk\r
+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */\r
+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */\r
+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */\r
+#define RTC_ALRMAR_MNU_Pos             (8U)\r
+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */\r
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk\r
+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */\r
+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */\r
+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */\r
+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */\r
+#define RTC_ALRMAR_MSK1_Pos            (7U)\r
+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */\r
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk\r
+#define RTC_ALRMAR_ST_Pos              (4U)\r
+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */\r
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk\r
+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */\r
+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */\r
+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */\r
+#define RTC_ALRMAR_SU_Pos              (0U)\r
+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */\r
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk\r
+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */\r
+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */\r
+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */\r
+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */\r
+\r
+/********************  Bits definition for RTC_ALRMBR register  ***************/\r
+#define RTC_ALRMBR_MSK4_Pos            (31U)\r
+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */\r
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk\r
+#define RTC_ALRMBR_WDSEL_Pos           (30U)\r
+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */\r
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk\r
+#define RTC_ALRMBR_DT_Pos              (28U)\r
+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */\r
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk\r
+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */\r
+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */\r
+#define RTC_ALRMBR_DU_Pos              (24U)\r
+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */\r
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk\r
+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */\r
+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */\r
+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */\r
+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */\r
+#define RTC_ALRMBR_MSK3_Pos            (23U)\r
+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */\r
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk\r
+#define RTC_ALRMBR_PM_Pos              (22U)\r
+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */\r
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk\r
+#define RTC_ALRMBR_HT_Pos              (20U)\r
+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */\r
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk\r
+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */\r
+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */\r
+#define RTC_ALRMBR_HU_Pos              (16U)\r
+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */\r
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk\r
+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */\r
+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */\r
+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */\r
+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */\r
+#define RTC_ALRMBR_MSK2_Pos            (15U)\r
+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */\r
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk\r
+#define RTC_ALRMBR_MNT_Pos             (12U)\r
+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */\r
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk\r
+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */\r
+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */\r
+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */\r
+#define RTC_ALRMBR_MNU_Pos             (8U)\r
+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */\r
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk\r
+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */\r
+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */\r
+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */\r
+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */\r
+#define RTC_ALRMBR_MSK1_Pos            (7U)\r
+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */\r
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk\r
+#define RTC_ALRMBR_ST_Pos              (4U)\r
+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */\r
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk\r
+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */\r
+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */\r
+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */\r
+#define RTC_ALRMBR_SU_Pos              (0U)\r
+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */\r
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk\r
+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */\r
+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */\r
+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */\r
+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */\r
+\r
+/********************  Bits definition for RTC_WPR register  ******************/\r
+#define RTC_WPR_KEY_Pos                (0U)\r
+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */\r
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk\r
+\r
+/********************  Bits definition for RTC_SSR register  ******************/\r
+#define RTC_SSR_SS_Pos                 (0U)\r
+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */\r
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk\r
+\r
+/********************  Bits definition for RTC_SHIFTR register  ***************/\r
+#define RTC_SHIFTR_SUBFS_Pos           (0U)\r
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */\r
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk\r
+#define RTC_SHIFTR_ADD1S_Pos           (31U)\r
+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */\r
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk\r
+\r
+/********************  Bits definition for RTC_TSTR register  *****************/\r
+#define RTC_TSTR_PM_Pos                (22U)\r
+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */\r
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk\r
+#define RTC_TSTR_HT_Pos                (20U)\r
+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */\r
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk\r
+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */\r
+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */\r
+#define RTC_TSTR_HU_Pos                (16U)\r
+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */\r
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk\r
+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */\r
+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */\r
+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */\r
+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */\r
+#define RTC_TSTR_MNT_Pos               (12U)\r
+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */\r
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk\r
+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */\r
+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */\r
+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */\r
+#define RTC_TSTR_MNU_Pos               (8U)\r
+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */\r
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk\r
+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */\r
+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */\r
+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */\r
+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */\r
+#define RTC_TSTR_ST_Pos                (4U)\r
+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */\r
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk\r
+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */\r
+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */\r
+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */\r
+#define RTC_TSTR_SU_Pos                (0U)\r
+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */\r
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk\r
+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */\r
+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */\r
+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */\r
+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */\r
+\r
+/********************  Bits definition for RTC_TSDR register  *****************/\r
+#define RTC_TSDR_WDU_Pos               (13U)\r
+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */\r
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk\r
+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */\r
+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */\r
+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */\r
+#define RTC_TSDR_MT_Pos                (12U)\r
+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */\r
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk\r
+#define RTC_TSDR_MU_Pos                (8U)\r
+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */\r
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk\r
+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */\r
+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */\r
+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */\r
+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */\r
+#define RTC_TSDR_DT_Pos                (4U)\r
+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */\r
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk\r
+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */\r
+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */\r
+#define RTC_TSDR_DU_Pos                (0U)\r
+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */\r
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk\r
+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */\r
+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */\r
+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */\r
+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */\r
+\r
+/********************  Bits definition for RTC_TSSSR register  ****************/\r
+#define RTC_TSSSR_SS_Pos               (0U)\r
+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */\r
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk\r
+\r
+/********************  Bits definition for RTC_CAL register  *****************/\r
+#define RTC_CALR_CALP_Pos              (15U)\r
+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */\r
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk\r
+#define RTC_CALR_CALW8_Pos             (14U)\r
+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */\r
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk\r
+#define RTC_CALR_CALW16_Pos            (13U)\r
+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */\r
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk\r
+#define RTC_CALR_CALM_Pos              (0U)\r
+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */\r
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk\r
+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */\r
+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */\r
+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */\r
+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */\r
+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */\r
+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */\r
+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */\r
+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */\r
+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */\r
+\r
+/********************  Bits definition for RTC_TAMPCR register  ***************/\r
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)\r
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */\r
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk\r
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)\r
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */\r
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)\r
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */\r
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk\r
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)\r
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */\r
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk\r
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)\r
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */\r
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)\r
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */\r
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk\r
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)\r
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */\r
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk\r
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)\r
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */\r
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)\r
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */\r
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk\r
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)\r
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */\r
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk\r
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)\r
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */\r
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk\r
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00002000 */\r
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00004000 */\r
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)\r
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */\r
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk\r
+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00000800 */\r
+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001000 */\r
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)\r
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */\r
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk\r
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000100 */\r
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000200 */\r
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000400 */\r
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)\r
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */\r
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk\r
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)\r
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */\r
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk\r
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)\r
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */\r
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk\r
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)\r
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */\r
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk\r
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)\r
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */\r
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk\r
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)\r
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */\r
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk\r
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)\r
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */\r
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk\r
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)\r
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */\r
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk\r
+\r
+/********************  Bits definition for RTC_ALRMASSR register  *************/\r
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)\r
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */\r
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk\r
+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */\r
+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */\r
+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */\r
+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */\r
+#define RTC_ALRMASSR_SS_Pos            (0U)\r
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */\r
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk\r
+\r
+/********************  Bits definition for RTC_ALRMBSSR register  *************/\r
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)\r
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */\r
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk\r
+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */\r
+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */\r
+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */\r
+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */\r
+#define RTC_ALRMBSSR_SS_Pos            (0U)\r
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */\r
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk\r
+\r
+/********************  Bits definition for RTC_0R register  *******************/\r
+#define RTC_OR_OUT_RMP_Pos             (1U)\r
+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */\r
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk\r
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)\r
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */\r
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk\r
+\r
+\r
+/********************  Bits definition for RTC_BKP0R register  ****************/\r
+#define RTC_BKP0R_Pos                  (0U)\r
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP0R                      RTC_BKP0R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP1R register  ****************/\r
+#define RTC_BKP1R_Pos                  (0U)\r
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP1R                      RTC_BKP1R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP2R register  ****************/\r
+#define RTC_BKP2R_Pos                  (0U)\r
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP2R                      RTC_BKP2R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP3R register  ****************/\r
+#define RTC_BKP3R_Pos                  (0U)\r
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP3R                      RTC_BKP3R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP4R register  ****************/\r
+#define RTC_BKP4R_Pos                  (0U)\r
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP4R                      RTC_BKP4R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP5R register  ****************/\r
+#define RTC_BKP5R_Pos                  (0U)\r
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP5R                      RTC_BKP5R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP6R register  ****************/\r
+#define RTC_BKP6R_Pos                  (0U)\r
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP6R                      RTC_BKP6R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP7R register  ****************/\r
+#define RTC_BKP7R_Pos                  (0U)\r
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP7R                      RTC_BKP7R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP8R register  ****************/\r
+#define RTC_BKP8R_Pos                  (0U)\r
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP8R                      RTC_BKP8R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP9R register  ****************/\r
+#define RTC_BKP9R_Pos                  (0U)\r
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */\r
+#define RTC_BKP9R                      RTC_BKP9R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP10R register  ***************/\r
+#define RTC_BKP10R_Pos                 (0U)\r
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP10R                     RTC_BKP10R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP11R register  ***************/\r
+#define RTC_BKP11R_Pos                 (0U)\r
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP11R                     RTC_BKP11R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP12R register  ***************/\r
+#define RTC_BKP12R_Pos                 (0U)\r
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP12R                     RTC_BKP12R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP13R register  ***************/\r
+#define RTC_BKP13R_Pos                 (0U)\r
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP13R                     RTC_BKP13R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP14R register  ***************/\r
+#define RTC_BKP14R_Pos                 (0U)\r
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP14R                     RTC_BKP14R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP15R register  ***************/\r
+#define RTC_BKP15R_Pos                 (0U)\r
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP15R                     RTC_BKP15R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP16R register  ***************/\r
+#define RTC_BKP16R_Pos                 (0U)\r
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP16R                     RTC_BKP16R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP17R register  ***************/\r
+#define RTC_BKP17R_Pos                 (0U)\r
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP17R                     RTC_BKP17R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP18R register  ***************/\r
+#define RTC_BKP18R_Pos                 (0U)\r
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP18R                     RTC_BKP18R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP19R register  ***************/\r
+#define RTC_BKP19R_Pos                 (0U)\r
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP19R                     RTC_BKP19R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP20R register  ***************/\r
+#define RTC_BKP20R_Pos                 (0U)\r
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP20R                     RTC_BKP20R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP21R register  ***************/\r
+#define RTC_BKP21R_Pos                 (0U)\r
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP21R                     RTC_BKP21R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP22R register  ***************/\r
+#define RTC_BKP22R_Pos                 (0U)\r
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP22R                     RTC_BKP22R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP23R register  ***************/\r
+#define RTC_BKP23R_Pos                 (0U)\r
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP23R                     RTC_BKP23R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP24R register  ***************/\r
+#define RTC_BKP24R_Pos                 (0U)\r
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP24R                     RTC_BKP24R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP25R register  ***************/\r
+#define RTC_BKP25R_Pos                 (0U)\r
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP25R                     RTC_BKP25R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP26R register  ***************/\r
+#define RTC_BKP26R_Pos                 (0U)\r
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP26R                     RTC_BKP26R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP27R register  ***************/\r
+#define RTC_BKP27R_Pos                 (0U)\r
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP27R                     RTC_BKP27R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP28R register  ***************/\r
+#define RTC_BKP28R_Pos                 (0U)\r
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP28R                     RTC_BKP28R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP29R register  ***************/\r
+#define RTC_BKP29R_Pos                 (0U)\r
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP29R                     RTC_BKP29R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP30R register  ***************/\r
+#define RTC_BKP30R_Pos                 (0U)\r
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP30R                     RTC_BKP30R_Msk\r
+\r
+/********************  Bits definition for RTC_BKP31R register  ***************/\r
+#define RTC_BKP31R_Pos                 (0U)\r
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */\r
+#define RTC_BKP31R                     RTC_BKP31R_Msk\r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER                       32U\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          Serial Audio Interface                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for SAI_GCR register  *******************/\r
+#define SAI_GCR_SYNCIN_Pos         (0U)\r
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */\r
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\r
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000001 */\r
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000002 */\r
+\r
+#define SAI_GCR_SYNCOUT_Pos        (4U)\r
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */\r
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000010 */\r
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000020 */\r
+\r
+/*******************  Bit definition for SAI_xCR1 register  *******************/\r
+#define SAI_xCR1_MODE_Pos          (0U)\r
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */\r
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\r
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000001 */\r
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000002 */\r
+\r
+#define SAI_xCR1_PRTCFG_Pos        (2U)\r
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */\r
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\r
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000004 */\r
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000008 */\r
+\r
+#define SAI_xCR1_DS_Pos            (5U)\r
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */\r
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000020 */\r
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000040 */\r
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000080 */\r
+\r
+#define SAI_xCR1_LSBFIRST_Pos      (8U)\r
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */\r
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\r
+#define SAI_xCR1_CKSTR_Pos         (9U)\r
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */\r
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\r
+\r
+#define SAI_xCR1_SYNCEN_Pos        (10U)\r
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */\r
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000400 */\r
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000800 */\r
+\r
+#define SAI_xCR1_MONO_Pos          (12U)\r
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */\r
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\r
+#define SAI_xCR1_OUTDRIV_Pos       (13U)\r
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */\r
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\r
+#define SAI_xCR1_SAIEN_Pos         (16U)\r
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */\r
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\r
+#define SAI_xCR1_DMAEN_Pos         (17U)\r
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */\r
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\r
+#define SAI_xCR1_NODIV_Pos         (19U)\r
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */\r
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\r
+\r
+#define SAI_xCR1_MCKDIV_Pos        (20U)\r
+#define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00F00000 */\r
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\r
+#define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */\r
+#define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */\r
+#define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */\r
+#define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */\r
+\r
+/*******************  Bit definition for SAI_xCR2 register  *******************/\r
+#define SAI_xCR2_FTH_Pos           (0U)\r
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */\r
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\r
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000001 */\r
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000002 */\r
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000004 */\r
+\r
+#define SAI_xCR2_FFLUSH_Pos        (3U)\r
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */\r
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\r
+#define SAI_xCR2_TRIS_Pos          (4U)\r
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */\r
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE_Pos          (5U)\r
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */\r
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\r
+#define SAI_xCR2_MUTEVAL_Pos       (6U)\r
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */\r
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\r
+\r
+\r
+#define SAI_xCR2_MUTECNT_Pos       (7U)\r
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */\r
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000080 */\r
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000100 */\r
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000200 */\r
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000400 */\r
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000800 */\r
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001000 */\r
+\r
+#define SAI_xCR2_CPL_Pos           (13U)\r
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */\r
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */\r
+#define SAI_xCR2_COMP_Pos          (14U)\r
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */\r
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                /*!< 0x00004000 */\r
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                /*!< 0x00008000 */\r
+\r
+\r
+/******************  Bit definition for SAI_xFRCR register  *******************/\r
+#define SAI_xFRCR_FRL_Pos          (0U)\r
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */\r
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */\r
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000001 */\r
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000002 */\r
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000004 */\r
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000008 */\r
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000010 */\r
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000020 */\r
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000040 */\r
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000080 */\r
+\r
+#define SAI_xFRCR_FSALL_Pos        (8U)\r
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */\r
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */\r
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000100 */\r
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000200 */\r
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000400 */\r
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000800 */\r
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00001000 */\r
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00002000 */\r
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00004000 */\r
+\r
+#define SAI_xFRCR_FSDEF_Pos        (16U)\r
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */\r
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPOL_Pos        (17U)\r
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */\r
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\r
+#define SAI_xFRCR_FSOFF_Pos        (18U)\r
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */\r
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\r
+\r
+/******************  Bit definition for SAI_xSLOTR register  *******************/\r
+#define SAI_xSLOTR_FBOFF_Pos       (0U)\r
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */\r
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\r
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000001 */\r
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000002 */\r
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000004 */\r
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000008 */\r
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000010 */\r
+\r
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\r
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */\r
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\r
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000040 */\r
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000080 */\r
+\r
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)\r
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */\r
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\r
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000100 */\r
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000200 */\r
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000400 */\r
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000800 */\r
+\r
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)\r
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */\r
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\r
+\r
+/*******************  Bit definition for SAI_xIMR register  *******************/\r
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)\r
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */\r
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\r
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)\r
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */\r
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\r
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)\r
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */\r
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\r
+#define SAI_xIMR_FREQIE_Pos        (3U)\r
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */\r
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\r
+#define SAI_xIMR_CNRDYIE_Pos       (4U)\r
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */\r
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\r
+#define SAI_xIMR_AFSDETIE_Pos      (5U)\r
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */\r
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\r
+#define SAI_xIMR_LFSDETIE_Pos      (6U)\r
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */\r
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\r
+\r
+/********************  Bit definition for SAI_xSR register  *******************/\r
+#define SAI_xSR_OVRUDR_Pos         (0U)\r
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */\r
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\r
+#define SAI_xSR_MUTEDET_Pos        (1U)\r
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */\r
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\r
+#define SAI_xSR_WCKCFG_Pos         (2U)\r
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */\r
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\r
+#define SAI_xSR_FREQ_Pos           (3U)\r
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */\r
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\r
+#define SAI_xSR_CNRDY_Pos          (4U)\r
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */\r
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\r
+#define SAI_xSR_AFSDET_Pos         (5U)\r
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */\r
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\r
+#define SAI_xSR_LFSDET_Pos         (6U)\r
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */\r
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\r
+\r
+#define SAI_xSR_FLVL_Pos           (16U)\r
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */\r
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\r
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00010000 */\r
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00020000 */\r
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00040000 */\r
+\r
+/******************  Bit definition for SAI_xCLRFR register  ******************/\r
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)\r
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */\r
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\r
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\r
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */\r
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\r
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\r
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */\r
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\r
+#define SAI_xCLRFR_CFREQ_Pos       (3U)\r
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */\r
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\r
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)\r
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */\r
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\r
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)\r
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */\r
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\r
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)\r
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */\r
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\r
+\r
+/******************  Bit definition for SAI_xDR register  ******************/\r
+#define SAI_xDR_DATA_Pos           (0U)\r
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */\r
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                           SDMMC Interface                                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for SDMMC_POWER register  ******************/\r
+#define SDMMC_POWER_PWRCTRL_Pos         (0U)\r
+#define SDMMC_POWER_PWRCTRL_Msk         (0x3UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000003 */\r
+#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDMMC_POWER_PWRCTRL_0           (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */\r
+#define SDMMC_POWER_PWRCTRL_1           (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */\r
+\r
+/******************  Bit definition for SDMMC_CLKCR register  ******************/\r
+#define SDMMC_CLKCR_CLKDIV_Pos          (0U)\r
+#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000000FF */\r
+#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */\r
+#define SDMMC_CLKCR_CLKEN_Pos           (8U)\r
+#define SDMMC_CLKCR_CLKEN_Msk           (0x1UL << SDMMC_CLKCR_CLKEN_Pos)       /*!< 0x00000100 */\r
+#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */\r
+#define SDMMC_CLKCR_PWRSAV_Pos          (9U)\r
+#define SDMMC_CLKCR_PWRSAV_Msk          (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)      /*!< 0x00000200 */\r
+#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */\r
+#define SDMMC_CLKCR_BYPASS_Pos          (10U)\r
+#define SDMMC_CLKCR_BYPASS_Msk          (0x1UL << SDMMC_CLKCR_BYPASS_Pos)      /*!< 0x00000400 */\r
+#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */\r
+\r
+#define SDMMC_CLKCR_WIDBUS_Pos          (11U)\r
+#define SDMMC_CLKCR_WIDBUS_Msk          (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00001800 */\r
+#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDMMC_CLKCR_WIDBUS_0            (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00000800 */\r
+#define SDMMC_CLKCR_WIDBUS_1            (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00001000 */\r
+\r
+#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)\r
+#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)     /*!< 0x00002000 */\r
+#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */\r
+#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)\r
+#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)     /*!< 0x00004000 */\r
+#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */\r
+\r
+/*******************  Bit definition for SDMMC_ARG register  *******************/\r
+#define SDMMC_ARG_CMDARG_Pos            (0U)\r
+#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */\r
+\r
+/*******************  Bit definition for SDMMC_CMD register  *******************/\r
+#define SDMMC_CMD_CMDINDEX_Pos          (0U)\r
+#define SDMMC_CMD_CMDINDEX_Msk          (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)     /*!< 0x0000003F */\r
+#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */\r
+\r
+#define SDMMC_CMD_WAITRESP_Pos          (6U)\r
+#define SDMMC_CMD_WAITRESP_Msk          (0x3UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x000000C0 */\r
+#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDMMC_CMD_WAITRESP_0            (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000040 */\r
+#define SDMMC_CMD_WAITRESP_1            (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000080 */\r
+\r
+#define SDMMC_CMD_WAITINT_Pos           (8U)\r
+#define SDMMC_CMD_WAITINT_Msk           (0x1UL << SDMMC_CMD_WAITINT_Pos)       /*!< 0x00000100 */\r
+#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */\r
+#define SDMMC_CMD_WAITPEND_Pos          (9U)\r
+#define SDMMC_CMD_WAITPEND_Msk          (0x1UL << SDMMC_CMD_WAITPEND_Pos)      /*!< 0x00000200 */\r
+#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDMMC_CMD_CPSMEN_Pos            (10U)\r
+#define SDMMC_CMD_CPSMEN_Msk            (0x1UL << SDMMC_CMD_CPSMEN_Pos)        /*!< 0x00000400 */\r
+#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */\r
+#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)\r
+#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)   /*!< 0x00000800 */\r
+#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */\r
+\r
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\r
+#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)\r
+#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)  /*!< 0x0000003F */\r
+#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */\r
+\r
+/******************  Bit definition for SDMMC_RESP1 register  ******************/\r
+#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)\r
+#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */\r
+\r
+/******************  Bit definition for SDMMC_RESP2 register  ******************/\r
+#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)\r
+#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */\r
+\r
+/******************  Bit definition for SDMMC_RESP3 register  ******************/\r
+#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)\r
+#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */\r
+\r
+/******************  Bit definition for SDMMC_RESP4 register  ******************/\r
+#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)\r
+#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */\r
+\r
+/******************  Bit definition for SDMMC_DTIMER register  *****************/\r
+#define SDMMC_DTIMER_DATATIME_Pos       (0U)\r
+#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */\r
+\r
+/******************  Bit definition for SDMMC_DLEN register  *******************/\r
+#define SDMMC_DLEN_DATALENGTH_Pos       (0U)\r
+#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */\r
+\r
+/******************  Bit definition for SDMMC_DCTRL register  ******************/\r
+#define SDMMC_DCTRL_DTEN_Pos            (0U)\r
+#define SDMMC_DCTRL_DTEN_Msk            (0x1UL << SDMMC_DCTRL_DTEN_Pos)        /*!< 0x00000001 */\r
+#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */\r
+#define SDMMC_DCTRL_DTDIR_Pos           (1U)\r
+#define SDMMC_DCTRL_DTDIR_Msk           (0x1UL << SDMMC_DCTRL_DTDIR_Pos)       /*!< 0x00000002 */\r
+#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */\r
+#define SDMMC_DCTRL_DTMODE_Pos          (2U)\r
+#define SDMMC_DCTRL_DTMODE_Msk          (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */\r
+#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */\r
+#define SDMMC_DCTRL_DMAEN_Pos           (3U)\r
+#define SDMMC_DCTRL_DMAEN_Msk           (0x1UL << SDMMC_DCTRL_DMAEN_Pos)       /*!< 0x00000008 */\r
+#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */\r
+\r
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)\r
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x000000F0 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */\r
+\r
+#define SDMMC_DCTRL_RWSTART_Pos         (8U)\r
+#define SDMMC_DCTRL_RWSTART_Msk         (0x1UL << SDMMC_DCTRL_RWSTART_Pos)     /*!< 0x00000100 */\r
+#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */\r
+#define SDMMC_DCTRL_RWSTOP_Pos          (9U)\r
+#define SDMMC_DCTRL_RWSTOP_Msk          (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)      /*!< 0x00000200 */\r
+#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */\r
+#define SDMMC_DCTRL_RWMOD_Pos           (10U)\r
+#define SDMMC_DCTRL_RWMOD_Msk           (0x1UL << SDMMC_DCTRL_RWMOD_Pos)       /*!< 0x00000400 */\r
+#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */\r
+#define SDMMC_DCTRL_SDIOEN_Pos          (11U)\r
+#define SDMMC_DCTRL_SDIOEN_Msk          (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)      /*!< 0x00000800 */\r
+#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */\r
+\r
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/\r
+#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)\r
+#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */\r
+\r
+/******************  Bit definition for SDMMC_STA register  ********************/\r
+#define SDMMC_STA_CCRCFAIL_Pos          (0U)\r
+#define SDMMC_STA_CCRCFAIL_Msk          (0x1UL << SDMMC_STA_CCRCFAIL_Pos)      /*!< 0x00000001 */\r
+#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */\r
+#define SDMMC_STA_DCRCFAIL_Pos          (1U)\r
+#define SDMMC_STA_DCRCFAIL_Msk          (0x1UL << SDMMC_STA_DCRCFAIL_Pos)      /*!< 0x00000002 */\r
+#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */\r
+#define SDMMC_STA_CTIMEOUT_Pos          (2U)\r
+#define SDMMC_STA_CTIMEOUT_Msk          (0x1UL << SDMMC_STA_CTIMEOUT_Pos)      /*!< 0x00000004 */\r
+#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */\r
+#define SDMMC_STA_DTIMEOUT_Pos          (3U)\r
+#define SDMMC_STA_DTIMEOUT_Msk          (0x1UL << SDMMC_STA_DTIMEOUT_Pos)      /*!< 0x00000008 */\r
+#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */\r
+#define SDMMC_STA_TXUNDERR_Pos          (4U)\r
+#define SDMMC_STA_TXUNDERR_Msk          (0x1UL << SDMMC_STA_TXUNDERR_Pos)      /*!< 0x00000010 */\r
+#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */\r
+#define SDMMC_STA_RXOVERR_Pos           (5U)\r
+#define SDMMC_STA_RXOVERR_Msk           (0x1UL << SDMMC_STA_RXOVERR_Pos)       /*!< 0x00000020 */\r
+#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */\r
+#define SDMMC_STA_CMDREND_Pos           (6U)\r
+#define SDMMC_STA_CMDREND_Msk           (0x1UL << SDMMC_STA_CMDREND_Pos)       /*!< 0x00000040 */\r
+#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */\r
+#define SDMMC_STA_CMDSENT_Pos           (7U)\r
+#define SDMMC_STA_CMDSENT_Msk           (0x1UL << SDMMC_STA_CMDSENT_Pos)       /*!< 0x00000080 */\r
+#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */\r
+#define SDMMC_STA_DATAEND_Pos           (8U)\r
+#define SDMMC_STA_DATAEND_Msk           (0x1UL << SDMMC_STA_DATAEND_Pos)       /*!< 0x00000100 */\r
+#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */\r
+#define SDMMC_STA_STBITERR_Pos          (9U)\r
+#define SDMMC_STA_STBITERR_Msk          (0x1UL << SDMMC_STA_STBITERR_Pos)      /*!< 0x00000200 */\r
+#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */\r
+#define SDMMC_STA_DBCKEND_Pos           (10U)\r
+#define SDMMC_STA_DBCKEND_Msk           (0x1UL << SDMMC_STA_DBCKEND_Pos)       /*!< 0x00000400 */\r
+#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */\r
+#define SDMMC_STA_CMDACT_Pos            (11U)\r
+#define SDMMC_STA_CMDACT_Msk            (0x1UL << SDMMC_STA_CMDACT_Pos)        /*!< 0x00000800 */\r
+#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */\r
+#define SDMMC_STA_TXACT_Pos             (12U)\r
+#define SDMMC_STA_TXACT_Msk             (0x1UL << SDMMC_STA_TXACT_Pos)         /*!< 0x00001000 */\r
+#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */\r
+#define SDMMC_STA_RXACT_Pos             (13U)\r
+#define SDMMC_STA_RXACT_Msk             (0x1UL << SDMMC_STA_RXACT_Pos)         /*!< 0x00002000 */\r
+#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */\r
+#define SDMMC_STA_TXFIFOHE_Pos          (14U)\r
+#define SDMMC_STA_TXFIFOHE_Msk          (0x1UL << SDMMC_STA_TXFIFOHE_Pos)      /*!< 0x00004000 */\r
+#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDMMC_STA_RXFIFOHF_Pos          (15U)\r
+#define SDMMC_STA_RXFIFOHF_Msk          (0x1UL << SDMMC_STA_RXFIFOHF_Pos)      /*!< 0x00008000 */\r
+#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDMMC_STA_TXFIFOF_Pos           (16U)\r
+#define SDMMC_STA_TXFIFOF_Msk           (0x1UL << SDMMC_STA_TXFIFOF_Pos)       /*!< 0x00010000 */\r
+#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */\r
+#define SDMMC_STA_RXFIFOF_Pos           (17U)\r
+#define SDMMC_STA_RXFIFOF_Msk           (0x1UL << SDMMC_STA_RXFIFOF_Pos)       /*!< 0x00020000 */\r
+#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */\r
+#define SDMMC_STA_TXFIFOE_Pos           (18U)\r
+#define SDMMC_STA_TXFIFOE_Msk           (0x1UL << SDMMC_STA_TXFIFOE_Pos)       /*!< 0x00040000 */\r
+#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */\r
+#define SDMMC_STA_RXFIFOE_Pos           (19U)\r
+#define SDMMC_STA_RXFIFOE_Msk           (0x1UL << SDMMC_STA_RXFIFOE_Pos)       /*!< 0x00080000 */\r
+#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */\r
+#define SDMMC_STA_TXDAVL_Pos            (20U)\r
+#define SDMMC_STA_TXDAVL_Msk            (0x1UL << SDMMC_STA_TXDAVL_Pos)        /*!< 0x00100000 */\r
+#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */\r
+#define SDMMC_STA_RXDAVL_Pos            (21U)\r
+#define SDMMC_STA_RXDAVL_Msk            (0x1UL << SDMMC_STA_RXDAVL_Pos)        /*!< 0x00200000 */\r
+#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */\r
+#define SDMMC_STA_SDIOIT_Pos            (22U)\r
+#define SDMMC_STA_SDIOIT_Msk            (0x1UL << SDMMC_STA_SDIOIT_Pos)        /*!< 0x00400000 */\r
+#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */\r
+\r
+/*******************  Bit definition for SDMMC_ICR register  *******************/\r
+#define SDMMC_ICR_CCRCFAILC_Pos         (0U)\r
+#define SDMMC_ICR_CCRCFAILC_Msk         (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)     /*!< 0x00000001 */\r
+#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_DCRCFAILC_Pos         (1U)\r
+#define SDMMC_ICR_DCRCFAILC_Msk         (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)     /*!< 0x00000002 */\r
+#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)\r
+#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)     /*!< 0x00000004 */\r
+#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)\r
+#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)     /*!< 0x00000008 */\r
+#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_TXUNDERRC_Pos         (4U)\r
+#define SDMMC_ICR_TXUNDERRC_Msk         (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)     /*!< 0x00000010 */\r
+#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */\r
+#define SDMMC_ICR_RXOVERRC_Pos          (5U)\r
+#define SDMMC_ICR_RXOVERRC_Msk          (0x1UL << SDMMC_ICR_RXOVERRC_Pos)      /*!< 0x00000020 */\r
+#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */\r
+#define SDMMC_ICR_CMDRENDC_Pos          (6U)\r
+#define SDMMC_ICR_CMDRENDC_Msk          (0x1UL << SDMMC_ICR_CMDRENDC_Pos)      /*!< 0x00000040 */\r
+#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */\r
+#define SDMMC_ICR_CMDSENTC_Pos          (7U)\r
+#define SDMMC_ICR_CMDSENTC_Msk          (0x1UL << SDMMC_ICR_CMDSENTC_Pos)      /*!< 0x00000080 */\r
+#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */\r
+#define SDMMC_ICR_DATAENDC_Pos          (8U)\r
+#define SDMMC_ICR_DATAENDC_Msk          (0x1UL << SDMMC_ICR_DATAENDC_Pos)      /*!< 0x00000100 */\r
+#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */\r
+#define SDMMC_ICR_STBITERRC_Pos         (9U)\r
+#define SDMMC_ICR_STBITERRC_Msk         (0x1UL << SDMMC_ICR_STBITERRC_Pos)     /*!< 0x00000200 */\r
+#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */\r
+#define SDMMC_ICR_DBCKENDC_Pos          (10U)\r
+#define SDMMC_ICR_DBCKENDC_Msk          (0x1UL << SDMMC_ICR_DBCKENDC_Pos)      /*!< 0x00000400 */\r
+#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */\r
+#define SDMMC_ICR_SDIOITC_Pos           (22U)\r
+#define SDMMC_ICR_SDIOITC_Msk           (0x1UL << SDMMC_ICR_SDIOITC_Pos)       /*!< 0x00400000 */\r
+#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */\r
+\r
+/******************  Bit definition for SDMMC_MASK register  *******************/\r
+#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)\r
+#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)   /*!< 0x00000001 */\r
+#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */\r
+#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)\r
+#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)   /*!< 0x00000002 */\r
+#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */\r
+#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)\r
+#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)   /*!< 0x00000004 */\r
+#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */\r
+#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)\r
+#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)   /*!< 0x00000008 */\r
+#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */\r
+#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)\r
+#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)   /*!< 0x00000010 */\r
+#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */\r
+#define SDMMC_MASK_RXOVERRIE_Pos        (5U)\r
+#define SDMMC_MASK_RXOVERRIE_Msk        (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)    /*!< 0x00000020 */\r
+#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */\r
+#define SDMMC_MASK_CMDRENDIE_Pos        (6U)\r
+#define SDMMC_MASK_CMDRENDIE_Msk        (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)    /*!< 0x00000040 */\r
+#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */\r
+#define SDMMC_MASK_CMDSENTIE_Pos        (7U)\r
+#define SDMMC_MASK_CMDSENTIE_Msk        (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)    /*!< 0x00000080 */\r
+#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */\r
+#define SDMMC_MASK_DATAENDIE_Pos        (8U)\r
+#define SDMMC_MASK_DATAENDIE_Msk        (0x1UL << SDMMC_MASK_DATAENDIE_Pos)    /*!< 0x00000100 */\r
+#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */\r
+#define SDMMC_MASK_DBCKENDIE_Pos        (10U)\r
+#define SDMMC_MASK_DBCKENDIE_Msk        (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)    /*!< 0x00000400 */\r
+#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */\r
+#define SDMMC_MASK_CMDACTIE_Pos         (11U)\r
+#define SDMMC_MASK_CMDACTIE_Msk         (0x1UL << SDMMC_MASK_CMDACTIE_Pos)     /*!< 0x00000800 */\r
+#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */\r
+#define SDMMC_MASK_TXACTIE_Pos          (12U)\r
+#define SDMMC_MASK_TXACTIE_Msk          (0x1UL << SDMMC_MASK_TXACTIE_Pos)      /*!< 0x00001000 */\r
+#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */\r
+#define SDMMC_MASK_RXACTIE_Pos          (13U)\r
+#define SDMMC_MASK_RXACTIE_Msk          (0x1UL << SDMMC_MASK_RXACTIE_Pos)      /*!< 0x00002000 */\r
+#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */\r
+#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)\r
+#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)   /*!< 0x00004000 */\r
+#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */\r
+#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)\r
+#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)   /*!< 0x00008000 */\r
+#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */\r
+#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)\r
+#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)    /*!< 0x00010000 */\r
+#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */\r
+#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)\r
+#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)    /*!< 0x00020000 */\r
+#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */\r
+#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)\r
+#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)    /*!< 0x00040000 */\r
+#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */\r
+#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)\r
+#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)    /*!< 0x00080000 */\r
+#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */\r
+#define SDMMC_MASK_TXDAVLIE_Pos         (20U)\r
+#define SDMMC_MASK_TXDAVLIE_Msk         (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)     /*!< 0x00100000 */\r
+#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDMMC_MASK_RXDAVLIE_Pos         (21U)\r
+#define SDMMC_MASK_RXDAVLIE_Msk         (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)     /*!< 0x00200000 */\r
+#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDMMC_MASK_SDIOITIE_Pos         (22U)\r
+#define SDMMC_MASK_SDIOITIE_Msk         (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */\r
+#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */\r
+\r
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/\r
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)\r
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\r
+#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/******************  Bit definition for SDMMC_FIFO register  *******************/\r
+#define SDMMC_FIFO_FIFODATA_Pos         (0U)\r
+#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Serial Peripheral Interface (SPI)                   */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for SPI_CR1 register  ********************/\r
+#define SPI_CR1_CPHA_Pos         (0U)\r
+#define SPI_CR1_CPHA_Msk         (0x1UL << SPI_CR1_CPHA_Pos)                   /*!< 0x00000001 */\r
+#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */\r
+#define SPI_CR1_CPOL_Pos         (1U)\r
+#define SPI_CR1_CPOL_Msk         (0x1UL << SPI_CR1_CPOL_Pos)                   /*!< 0x00000002 */\r
+#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */\r
+#define SPI_CR1_MSTR_Pos         (2U)\r
+#define SPI_CR1_MSTR_Msk         (0x1UL << SPI_CR1_MSTR_Pos)                   /*!< 0x00000004 */\r
+#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */\r
+\r
+#define SPI_CR1_BR_Pos           (3U)\r
+#define SPI_CR1_BR_Msk           (0x7UL << SPI_CR1_BR_Pos)                     /*!< 0x00000038 */\r
+#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0             (0x1UL << SPI_CR1_BR_Pos)                     /*!< 0x00000008 */\r
+#define SPI_CR1_BR_1             (0x2UL << SPI_CR1_BR_Pos)                     /*!< 0x00000010 */\r
+#define SPI_CR1_BR_2             (0x4UL << SPI_CR1_BR_Pos)                     /*!< 0x00000020 */\r
+\r
+#define SPI_CR1_SPE_Pos          (6U)\r
+#define SPI_CR1_SPE_Msk          (0x1UL << SPI_CR1_SPE_Pos)                    /*!< 0x00000040 */\r
+#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */\r
+#define SPI_CR1_LSBFIRST_Pos     (7U)\r
+#define SPI_CR1_LSBFIRST_Msk     (0x1UL << SPI_CR1_LSBFIRST_Pos)               /*!< 0x00000080 */\r
+#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */\r
+#define SPI_CR1_SSI_Pos          (8U)\r
+#define SPI_CR1_SSI_Msk          (0x1UL << SPI_CR1_SSI_Pos)                    /*!< 0x00000100 */\r
+#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */\r
+#define SPI_CR1_SSM_Pos          (9U)\r
+#define SPI_CR1_SSM_Msk          (0x1UL << SPI_CR1_SSM_Pos)                    /*!< 0x00000200 */\r
+#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */\r
+#define SPI_CR1_RXONLY_Pos       (10U)\r
+#define SPI_CR1_RXONLY_Msk       (0x1UL << SPI_CR1_RXONLY_Pos)                 /*!< 0x00000400 */\r
+#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */\r
+#define SPI_CR1_CRCL_Pos         (11U)\r
+#define SPI_CR1_CRCL_Msk         (0x1UL << SPI_CR1_CRCL_Pos)                   /*!< 0x00000800 */\r
+#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */\r
+#define SPI_CR1_CRCNEXT_Pos      (12U)\r
+#define SPI_CR1_CRCNEXT_Msk      (0x1UL << SPI_CR1_CRCNEXT_Pos)                /*!< 0x00001000 */\r
+#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */\r
+#define SPI_CR1_CRCEN_Pos        (13U)\r
+#define SPI_CR1_CRCEN_Msk        (0x1UL << SPI_CR1_CRCEN_Pos)                  /*!< 0x00002000 */\r
+#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */\r
+#define SPI_CR1_BIDIOE_Pos       (14U)\r
+#define SPI_CR1_BIDIOE_Msk       (0x1UL << SPI_CR1_BIDIOE_Pos)                 /*!< 0x00004000 */\r
+#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE_Pos     (15U)\r
+#define SPI_CR1_BIDIMODE_Msk     (0x1UL << SPI_CR1_BIDIMODE_Pos)               /*!< 0x00008000 */\r
+#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */\r
+\r
+/*******************  Bit definition for SPI_CR2 register  ********************/\r
+#define SPI_CR2_RXDMAEN_Pos      (0U)\r
+#define SPI_CR2_RXDMAEN_Msk      (0x1UL << SPI_CR2_RXDMAEN_Pos)                /*!< 0x00000001 */\r
+#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN_Pos      (1U)\r
+#define SPI_CR2_TXDMAEN_Msk      (0x1UL << SPI_CR2_TXDMAEN_Pos)                /*!< 0x00000002 */\r
+#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE_Pos         (2U)\r
+#define SPI_CR2_SSOE_Msk         (0x1UL << SPI_CR2_SSOE_Pos)                   /*!< 0x00000004 */\r
+#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */\r
+#define SPI_CR2_NSSP_Pos         (3U)\r
+#define SPI_CR2_NSSP_Msk         (0x1UL << SPI_CR2_NSSP_Pos)                   /*!< 0x00000008 */\r
+#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */\r
+#define SPI_CR2_FRF_Pos          (4U)\r
+#define SPI_CR2_FRF_Msk          (0x1UL << SPI_CR2_FRF_Pos)                    /*!< 0x00000010 */\r
+#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */\r
+#define SPI_CR2_ERRIE_Pos        (5U)\r
+#define SPI_CR2_ERRIE_Msk        (0x1UL << SPI_CR2_ERRIE_Pos)                  /*!< 0x00000020 */\r
+#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE_Pos       (6U)\r
+#define SPI_CR2_RXNEIE_Msk       (0x1UL << SPI_CR2_RXNEIE_Pos)                 /*!< 0x00000040 */\r
+#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE_Pos        (7U)\r
+#define SPI_CR2_TXEIE_Msk        (0x1UL << SPI_CR2_TXEIE_Pos)                  /*!< 0x00000080 */\r
+#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */\r
+#define SPI_CR2_DS_Pos           (8U)\r
+#define SPI_CR2_DS_Msk           (0xFUL << SPI_CR2_DS_Pos)                     /*!< 0x00000F00 */\r
+#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */\r
+#define SPI_CR2_DS_0             (0x1UL << SPI_CR2_DS_Pos)                     /*!< 0x00000100 */\r
+#define SPI_CR2_DS_1             (0x2UL << SPI_CR2_DS_Pos)                     /*!< 0x00000200 */\r
+#define SPI_CR2_DS_2             (0x4UL << SPI_CR2_DS_Pos)                     /*!< 0x00000400 */\r
+#define SPI_CR2_DS_3             (0x8UL << SPI_CR2_DS_Pos)                     /*!< 0x00000800 */\r
+#define SPI_CR2_FRXTH_Pos        (12U)\r
+#define SPI_CR2_FRXTH_Msk        (0x1UL << SPI_CR2_FRXTH_Pos)                  /*!< 0x00001000 */\r
+#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */\r
+#define SPI_CR2_LDMARX_Pos       (13U)\r
+#define SPI_CR2_LDMARX_Msk       (0x1UL << SPI_CR2_LDMARX_Pos)                 /*!< 0x00002000 */\r
+#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */\r
+#define SPI_CR2_LDMATX_Pos       (14U)\r
+#define SPI_CR2_LDMATX_Msk       (0x1UL << SPI_CR2_LDMATX_Pos)                 /*!< 0x00004000 */\r
+#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */\r
+\r
+/********************  Bit definition for SPI_SR register  ********************/\r
+#define SPI_SR_RXNE_Pos          (0U)\r
+#define SPI_SR_RXNE_Msk          (0x1UL << SPI_SR_RXNE_Pos)                    /*!< 0x00000001 */\r
+#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE_Pos           (1U)\r
+#define SPI_SR_TXE_Msk           (0x1UL << SPI_SR_TXE_Pos)                     /*!< 0x00000002 */\r
+#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE_Pos        (2U)\r
+#define SPI_SR_CHSIDE_Msk        (0x1UL << SPI_SR_CHSIDE_Pos)                  /*!< 0x00000004 */\r
+#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */\r
+#define SPI_SR_UDR_Pos           (3U)\r
+#define SPI_SR_UDR_Msk           (0x1UL << SPI_SR_UDR_Pos)                     /*!< 0x00000008 */\r
+#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */\r
+#define SPI_SR_CRCERR_Pos        (4U)\r
+#define SPI_SR_CRCERR_Msk        (0x1UL << SPI_SR_CRCERR_Pos)                  /*!< 0x00000010 */\r
+#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */\r
+#define SPI_SR_MODF_Pos          (5U)\r
+#define SPI_SR_MODF_Msk          (0x1UL << SPI_SR_MODF_Pos)                    /*!< 0x00000020 */\r
+#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */\r
+#define SPI_SR_OVR_Pos           (6U)\r
+#define SPI_SR_OVR_Msk           (0x1UL << SPI_SR_OVR_Pos)                     /*!< 0x00000040 */\r
+#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */\r
+#define SPI_SR_BSY_Pos           (7U)\r
+#define SPI_SR_BSY_Msk           (0x1UL << SPI_SR_BSY_Pos)                     /*!< 0x00000080 */\r
+#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */\r
+#define SPI_SR_FRE_Pos           (8U)\r
+#define SPI_SR_FRE_Msk           (0x1UL << SPI_SR_FRE_Pos)                     /*!< 0x00000100 */\r
+#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */\r
+#define SPI_SR_FRLVL_Pos         (9U)\r
+#define SPI_SR_FRLVL_Msk         (0x3UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000600 */\r
+#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */\r
+#define SPI_SR_FRLVL_0           (0x1UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000200 */\r
+#define SPI_SR_FRLVL_1           (0x2UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000400 */\r
+#define SPI_SR_FTLVL_Pos         (11U)\r
+#define SPI_SR_FTLVL_Msk         (0x3UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001800 */\r
+#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */\r
+#define SPI_SR_FTLVL_0           (0x1UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00000800 */\r
+#define SPI_SR_FTLVL_1           (0x2UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001000 */\r
+\r
+/********************  Bit definition for SPI_DR register  ********************/\r
+#define SPI_DR_DR_Pos            (0U)\r
+#define SPI_DR_DR_Msk            (0xFFFFUL << SPI_DR_DR_Pos)                   /*!< 0x0000FFFF */\r
+#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */\r
+\r
+/*******************  Bit definition for SPI_CRCPR register  ******************/\r
+#define SPI_CRCPR_CRCPOLY_Pos    (0U)\r
+#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)           /*!< 0x0000FFFF */\r
+#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */\r
+\r
+/******************  Bit definition for SPI_RXCRCR register  ******************/\r
+#define SPI_RXCRCR_RXCRC_Pos     (0U)\r
+#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)            /*!< 0x0000FFFF */\r
+#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */\r
+\r
+/******************  Bit definition for SPI_TXCRCR register  ******************/\r
+#define SPI_TXCRCR_TXCRC_Pos     (0U)\r
+#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)            /*!< 0x0000FFFF */\r
+#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    QUADSPI                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*****************  Bit definition for QUADSPI_CR register  *******************/\r
+#define QUADSPI_CR_EN_Pos              (0U)\r
+#define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */\r
+#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */\r
+#define QUADSPI_CR_ABORT_Pos           (1U)\r
+#define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */\r
+#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */\r
+#define QUADSPI_CR_DMAEN_Pos           (2U)\r
+#define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */\r
+#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */\r
+#define QUADSPI_CR_TCEN_Pos            (3U)\r
+#define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */\r
+#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */\r
+#define QUADSPI_CR_SSHIFT_Pos          (4U)\r
+#define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */\r
+#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */\r
+#define QUADSPI_CR_FTHRES_Pos          (8U)\r
+#define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */\r
+#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */\r
+#define QUADSPI_CR_TEIE_Pos            (16U)\r
+#define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */\r
+#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */\r
+#define QUADSPI_CR_TCIE_Pos            (17U)\r
+#define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */\r
+#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */\r
+#define QUADSPI_CR_FTIE_Pos            (18U)\r
+#define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */\r
+#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */\r
+#define QUADSPI_CR_SMIE_Pos            (19U)\r
+#define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */\r
+#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */\r
+#define QUADSPI_CR_TOIE_Pos            (20U)\r
+#define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */\r
+#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */\r
+#define QUADSPI_CR_APMS_Pos            (22U)\r
+#define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */\r
+#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */\r
+#define QUADSPI_CR_PMM_Pos             (23U)\r
+#define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */\r
+#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */\r
+#define QUADSPI_CR_PRESCALER_Pos       (24U)\r
+#define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */\r
+#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */\r
+\r
+/*****************  Bit definition for QUADSPI_DCR register  ******************/\r
+#define QUADSPI_DCR_CKMODE_Pos         (0U)\r
+#define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */\r
+#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */\r
+#define QUADSPI_DCR_CSHT_Pos           (8U)\r
+#define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */\r
+#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */\r
+#define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */\r
+#define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */\r
+#define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */\r
+#define QUADSPI_DCR_FSIZE_Pos          (16U)\r
+#define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */\r
+#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */\r
+\r
+/******************  Bit definition for QUADSPI_SR register  *******************/\r
+#define QUADSPI_SR_TEF_Pos             (0U)\r
+#define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */\r
+#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */\r
+#define QUADSPI_SR_TCF_Pos             (1U)\r
+#define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */\r
+#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */\r
+#define QUADSPI_SR_FTF_Pos             (2U)\r
+#define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */\r
+#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_SMF_Pos             (3U)\r
+#define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */\r
+#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */\r
+#define QUADSPI_SR_TOF_Pos             (4U)\r
+#define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */\r
+#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */\r
+#define QUADSPI_SR_BUSY_Pos            (5U)\r
+#define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */\r
+#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */\r
+#define QUADSPI_SR_FLEVEL_Pos          (8U)\r
+#define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */\r
+#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */\r
+\r
+/******************  Bit definition for QUADSPI_FCR register  ******************/\r
+#define QUADSPI_FCR_CTEF_Pos           (0U)\r
+#define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */\r
+#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */\r
+#define QUADSPI_FCR_CTCF_Pos           (1U)\r
+#define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */\r
+#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */\r
+#define QUADSPI_FCR_CSMF_Pos           (3U)\r
+#define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */\r
+#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */\r
+#define QUADSPI_FCR_CTOF_Pos           (4U)\r
+#define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */\r
+#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */\r
+\r
+/******************  Bit definition for QUADSPI_DLR register  ******************/\r
+#define QUADSPI_DLR_DL_Pos             (0U)\r
+#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */\r
+\r
+/******************  Bit definition for QUADSPI_CCR register  ******************/\r
+#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)\r
+#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\r
+#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */\r
+#define QUADSPI_CCR_IMODE_Pos          (8U)\r
+#define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */\r
+#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */\r
+#define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */\r
+#define QUADSPI_CCR_ADMODE_Pos         (10U)\r
+#define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */\r
+#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */\r
+#define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */\r
+#define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */\r
+#define QUADSPI_CCR_ADSIZE_Pos         (12U)\r
+#define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */\r
+#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */\r
+#define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */\r
+#define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */\r
+#define QUADSPI_CCR_ABMODE_Pos         (14U)\r
+#define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */\r
+#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
+#define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */\r
+#define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */\r
+#define QUADSPI_CCR_ABSIZE_Pos         (16U)\r
+#define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */\r
+#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */\r
+#define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */\r
+#define QUADSPI_CCR_DCYC_Pos           (18U)\r
+#define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */\r
+#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */\r
+#define QUADSPI_CCR_DMODE_Pos          (24U)\r
+#define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */\r
+#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */\r
+#define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */\r
+#define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */\r
+#define QUADSPI_CCR_FMODE_Pos          (26U)\r
+#define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */\r
+#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */\r
+#define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */\r
+#define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */\r
+#define QUADSPI_CCR_SIOO_Pos           (28U)\r
+#define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */\r
+#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */\r
+#define QUADSPI_CCR_DDRM_Pos           (31U)\r
+#define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */\r
+#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */\r
+\r
+/******************  Bit definition for QUADSPI_AR register  *******************/\r
+#define QUADSPI_AR_ADDRESS_Pos         (0U)\r
+#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */\r
+\r
+/******************  Bit definition for QUADSPI_ABR register  ******************/\r
+#define QUADSPI_ABR_ALTERNATE_Pos      (0U)\r
+#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */\r
+\r
+/******************  Bit definition for QUADSPI_DR register  *******************/\r
+#define QUADSPI_DR_DATA_Pos            (0U)\r
+#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */\r
+\r
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/\r
+#define QUADSPI_PSMKR_MASK_Pos         (0U)\r
+#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */\r
+\r
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/\r
+#define QUADSPI_PSMAR_MATCH_Pos        (0U)\r
+#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */\r
+\r
+/******************  Bit definition for QUADSPI_PIR register  *****************/\r
+#define QUADSPI_PIR_INTERVAL_Pos       (0U)\r
+#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */\r
+#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */\r
+\r
+/******************  Bit definition for QUADSPI_LPTR register  *****************/\r
+#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)\r
+#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */\r
+#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                 SYSCFG                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\r
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)\r
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */\r
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */\r
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */\r
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */\r
+\r
+#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)\r
+#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */\r
+#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */\r
+\r
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/\r
+#define SYSCFG_CFGR1_FWDIS_Pos          (0U)\r
+#define SYSCFG_CFGR1_FWDIS_Msk          (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)      /*!< 0x00000001 */\r
+#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/\r
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)\r
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */\r
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */\r
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)\r
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)\r
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */\r
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)\r
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */\r
+#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)\r
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */\r
+#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)\r
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */\r
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)\r
+#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */\r
+#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)\r
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */\r
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */\r
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000UL)                         /*!<  Invalid operation Interrupt enable */\r
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000UL)                         /*!<  Divide-by-zero Interrupt enable */\r
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000UL)                         /*!<  Underflow Interrupt enable */\r
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000UL)                         /*!<  Overflow Interrupt enable */\r
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000UL)                         /*!<  Input denormal Interrupt enable */\r
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000UL)                         /*!<  Inexact Interrupt enable (interrupt disabled at reset) */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)\r
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x00000007 */\r
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)\r
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x00000070 */\r
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)\r
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000700 */\r
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)\r
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x00007000 */\r
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */\r
+\r
+/**\r
+  * @brief   EXTI0 configuration\r
+  */\r
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000UL)                     /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001UL)                     /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002UL)                     /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003UL)                     /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004UL)                     /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005UL)                     /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006UL)                     /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007UL)                     /*!<PH[0] pin */\r
+\r
+/**\r
+  * @brief   EXTI1 configuration\r
+  */\r
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000UL)                     /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010UL)                     /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020UL)                     /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030UL)                     /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040UL)                     /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050UL)                     /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060UL)                     /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070UL)                     /*!<PH[1] pin */\r
+\r
+/**\r
+  * @brief   EXTI2 configuration\r
+  */\r
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000UL)                     /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100UL)                     /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200UL)                     /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300UL)                     /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400UL)                     /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500UL)                     /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600UL)                     /*!<PG[2] pin */\r
+\r
+/**\r
+  * @brief   EXTI3 configuration\r
+  */\r
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000UL)                     /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000UL)                     /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000UL)                     /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000UL)                     /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000UL)                     /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000UL)                     /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000UL)                     /*!<PG[3] pin */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\r
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)\r
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x00000007 */\r
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)\r
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x00000070 */\r
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)\r
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000700 */\r
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)\r
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x00007000 */\r
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */\r
+/**\r
+  * @brief   EXTI4 configuration\r
+  */\r
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000UL)                     /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001UL)                     /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002UL)                     /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003UL)                     /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004UL)                     /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005UL)                     /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006UL)                     /*!<PG[4] pin */\r
+\r
+/**\r
+  * @brief   EXTI5 configuration\r
+  */\r
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000UL)                     /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010UL)                     /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020UL)                     /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030UL)                     /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040UL)                     /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050UL)                     /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060UL)                     /*!<PG[5] pin */\r
+\r
+/**\r
+  * @brief   EXTI6 configuration\r
+  */\r
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000UL)                     /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100UL)                     /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200UL)                     /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300UL)                     /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400UL)                     /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500UL)                     /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600UL)                     /*!<PG[6] pin */\r
+\r
+/**\r
+  * @brief   EXTI7 configuration\r
+  */\r
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000UL)                     /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000UL)                     /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000UL)                     /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000UL)                     /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000UL)                     /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000UL)                     /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000UL)                     /*!<PG[7] pin */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\r
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)\r
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x00000007 */\r
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)\r
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x00000070 */\r
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)\r
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000700 */\r
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)\r
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x00007000 */\r
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */\r
+\r
+/**\r
+  * @brief   EXTI8 configuration\r
+  */\r
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000UL)                     /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001UL)                     /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002UL)                     /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003UL)                     /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004UL)                     /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005UL)                     /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006UL)                     /*!<PG[8] pin */\r
+\r
+/**\r
+  * @brief   EXTI9 configuration\r
+  */\r
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000UL)                     /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010UL)                     /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020UL)                     /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030UL)                     /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040UL)                     /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050UL)                     /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060UL)                     /*!<PG[9] pin */\r
+\r
+/**\r
+  * @brief   EXTI10 configuration\r
+  */\r
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000UL)                     /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100UL)                     /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200UL)                     /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300UL)                     /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400UL)                     /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500UL)                     /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600UL)                     /*!<PG[10] pin */\r
+\r
+/**\r
+  * @brief   EXTI11 configuration\r
+  */\r
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000UL)                     /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000UL)                     /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000UL)                     /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000UL)                     /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000UL)                     /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000UL)                     /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000UL)                     /*!<PG[11] pin */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\r
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)\r
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */\r
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)\r
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */\r
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)\r
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */\r
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)\r
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */\r
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */\r
+\r
+/**\r
+  * @brief   EXTI12 configuration\r
+  */\r
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000UL)                     /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001UL)                     /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002UL)                     /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003UL)                     /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004UL)                     /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005UL)                     /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006UL)                     /*!<PG[12] pin */\r
+\r
+/**\r
+  * @brief   EXTI13 configuration\r
+  */\r
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000UL)                     /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010UL)                     /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020UL)                     /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030UL)                     /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040UL)                     /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050UL)                     /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060UL)                     /*!<PG[13] pin */\r
+\r
+/**\r
+  * @brief   EXTI14 configuration\r
+  */\r
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000UL)                     /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100UL)                     /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200UL)                     /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300UL)                     /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400UL)                     /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500UL)                     /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600UL)                     /*!<PG[14] pin */\r
+\r
+/**\r
+  * @brief   EXTI15 configuration\r
+  */\r
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000UL)                     /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000UL)                     /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000UL)                     /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000UL)                     /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000UL)                     /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000UL)                     /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000UL)                     /*!<PG[15] pin */\r
+\r
+/******************  Bit definition for SYSCFG_SCSR register  ****************/\r
+#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)\r
+#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)     /*!< 0x00000001 */\r
+#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */\r
+#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)\r
+#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)    /*!< 0x00000002 */\r
+#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */\r
+\r
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/\r
+#define SYSCFG_CFGR2_CLL_Pos            (0U)\r
+#define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */\r
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */\r
+#define SYSCFG_CFGR2_SPL_Pos            (1U)\r
+#define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */\r
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/\r
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)\r
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */\r
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */\r
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)\r
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */\r
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/\r
+#define SYSCFG_CFGR2_SPF_Pos            (8U)\r
+#define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */\r
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */\r
+\r
+/******************  Bit definition for SYSCFG_SWPR register  ****************/\r
+#define SYSCFG_SWPR_PAGE0_Pos           (0U)\r
+#define SYSCFG_SWPR_PAGE0_Msk           (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */\r
+#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */\r
+#define SYSCFG_SWPR_PAGE1_Pos           (1U)\r
+#define SYSCFG_SWPR_PAGE1_Msk           (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */\r
+#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */\r
+#define SYSCFG_SWPR_PAGE2_Pos           (2U)\r
+#define SYSCFG_SWPR_PAGE2_Msk           (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */\r
+#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */\r
+#define SYSCFG_SWPR_PAGE3_Pos           (3U)\r
+#define SYSCFG_SWPR_PAGE3_Msk           (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */\r
+#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */\r
+#define SYSCFG_SWPR_PAGE4_Pos           (4U)\r
+#define SYSCFG_SWPR_PAGE4_Msk           (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */\r
+#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */\r
+#define SYSCFG_SWPR_PAGE5_Pos           (5U)\r
+#define SYSCFG_SWPR_PAGE5_Msk           (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */\r
+#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */\r
+#define SYSCFG_SWPR_PAGE6_Pos           (6U)\r
+#define SYSCFG_SWPR_PAGE6_Msk           (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */\r
+#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */\r
+#define SYSCFG_SWPR_PAGE7_Pos           (7U)\r
+#define SYSCFG_SWPR_PAGE7_Msk           (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */\r
+#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */\r
+#define SYSCFG_SWPR_PAGE8_Pos           (8U)\r
+#define SYSCFG_SWPR_PAGE8_Msk           (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */\r
+#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */\r
+#define SYSCFG_SWPR_PAGE9_Pos           (9U)\r
+#define SYSCFG_SWPR_PAGE9_Msk           (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */\r
+#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */\r
+#define SYSCFG_SWPR_PAGE10_Pos          (10U)\r
+#define SYSCFG_SWPR_PAGE10_Msk          (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */\r
+#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/\r
+#define SYSCFG_SWPR_PAGE11_Pos          (11U)\r
+#define SYSCFG_SWPR_PAGE11_Msk          (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */\r
+#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/\r
+#define SYSCFG_SWPR_PAGE12_Pos          (12U)\r
+#define SYSCFG_SWPR_PAGE12_Msk          (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */\r
+#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/\r
+#define SYSCFG_SWPR_PAGE13_Pos          (13U)\r
+#define SYSCFG_SWPR_PAGE13_Msk          (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */\r
+#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/\r
+#define SYSCFG_SWPR_PAGE14_Pos          (14U)\r
+#define SYSCFG_SWPR_PAGE14_Msk          (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */\r
+#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/\r
+#define SYSCFG_SWPR_PAGE15_Pos          (15U)\r
+#define SYSCFG_SWPR_PAGE15_Msk          (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */\r
+#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/\r
+#define SYSCFG_SWPR_PAGE16_Pos          (16U)\r
+#define SYSCFG_SWPR_PAGE16_Msk          (0x1UL << SYSCFG_SWPR_PAGE16_Pos)      /*!< 0x00010000 */\r
+#define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/\r
+#define SYSCFG_SWPR_PAGE17_Pos          (17U)\r
+#define SYSCFG_SWPR_PAGE17_Msk          (0x1UL << SYSCFG_SWPR_PAGE17_Pos)      /*!< 0x00020000 */\r
+#define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/\r
+#define SYSCFG_SWPR_PAGE18_Pos          (18U)\r
+#define SYSCFG_SWPR_PAGE18_Msk          (0x1UL << SYSCFG_SWPR_PAGE18_Pos)      /*!< 0x00040000 */\r
+#define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/\r
+#define SYSCFG_SWPR_PAGE19_Pos          (19U)\r
+#define SYSCFG_SWPR_PAGE19_Msk          (0x1UL << SYSCFG_SWPR_PAGE19_Pos)      /*!< 0x00080000 */\r
+#define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/\r
+#define SYSCFG_SWPR_PAGE20_Pos          (20U)\r
+#define SYSCFG_SWPR_PAGE20_Msk          (0x1UL << SYSCFG_SWPR_PAGE20_Pos)      /*!< 0x00100000 */\r
+#define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/\r
+#define SYSCFG_SWPR_PAGE21_Pos          (21U)\r
+#define SYSCFG_SWPR_PAGE21_Msk          (0x1UL << SYSCFG_SWPR_PAGE21_Pos)      /*!< 0x00200000 */\r
+#define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/\r
+#define SYSCFG_SWPR_PAGE22_Pos          (22U)\r
+#define SYSCFG_SWPR_PAGE22_Msk          (0x1UL << SYSCFG_SWPR_PAGE22_Pos)      /*!< 0x00400000 */\r
+#define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/\r
+#define SYSCFG_SWPR_PAGE23_Pos          (23U)\r
+#define SYSCFG_SWPR_PAGE23_Msk          (0x1UL << SYSCFG_SWPR_PAGE23_Pos)      /*!< 0x00800000 */\r
+#define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/\r
+#define SYSCFG_SWPR_PAGE24_Pos          (24U)\r
+#define SYSCFG_SWPR_PAGE24_Msk          (0x1UL << SYSCFG_SWPR_PAGE24_Pos)      /*!< 0x01000000 */\r
+#define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/\r
+#define SYSCFG_SWPR_PAGE25_Pos          (25U)\r
+#define SYSCFG_SWPR_PAGE25_Msk          (0x1UL << SYSCFG_SWPR_PAGE25_Pos)      /*!< 0x02000000 */\r
+#define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/\r
+#define SYSCFG_SWPR_PAGE26_Pos          (26U)\r
+#define SYSCFG_SWPR_PAGE26_Msk          (0x1UL << SYSCFG_SWPR_PAGE26_Pos)      /*!< 0x04000000 */\r
+#define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/\r
+#define SYSCFG_SWPR_PAGE27_Pos          (27U)\r
+#define SYSCFG_SWPR_PAGE27_Msk          (0x1UL << SYSCFG_SWPR_PAGE27_Pos)      /*!< 0x08000000 */\r
+#define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/\r
+#define SYSCFG_SWPR_PAGE28_Pos          (28U)\r
+#define SYSCFG_SWPR_PAGE28_Msk          (0x1UL << SYSCFG_SWPR_PAGE28_Pos)      /*!< 0x10000000 */\r
+#define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/\r
+#define SYSCFG_SWPR_PAGE29_Pos          (29U)\r
+#define SYSCFG_SWPR_PAGE29_Msk          (0x1UL << SYSCFG_SWPR_PAGE29_Pos)      /*!< 0x20000000 */\r
+#define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/\r
+#define SYSCFG_SWPR_PAGE30_Pos          (30U)\r
+#define SYSCFG_SWPR_PAGE30_Msk          (0x1UL << SYSCFG_SWPR_PAGE30_Pos)      /*!< 0x40000000 */\r
+#define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/\r
+#define SYSCFG_SWPR_PAGE31_Pos          (31U)\r
+#define SYSCFG_SWPR_PAGE31_Msk          (0x1UL << SYSCFG_SWPR_PAGE31_Pos)      /*!< 0x80000000 */\r
+#define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/\r
+\r
+/******************  Bit definition for SYSCFG_SKR register  ****************/\r
+#define SYSCFG_SKR_KEY_Pos              (0U)\r
+#define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */\r
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */\r
+\r
+\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    TIM                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for TIM_CR1 register  ********************/\r
+#define TIM_CR1_CEN_Pos           (0U)\r
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */\r
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */\r
+#define TIM_CR1_UDIS_Pos          (1U)\r
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */\r
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */\r
+#define TIM_CR1_URS_Pos           (2U)\r
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */\r
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\r
+#define TIM_CR1_OPM_Pos           (3U)\r
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */\r
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */\r
+#define TIM_CR1_DIR_Pos           (4U)\r
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */\r
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */\r
+\r
+#define TIM_CR1_CMS_Pos           (5U)\r
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */\r
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */\r
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */\r
+\r
+#define TIM_CR1_ARPE_Pos          (7U)\r
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */\r
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD_Pos           (8U)\r
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */\r
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */\r
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */\r
+\r
+#define TIM_CR1_UIFREMAP_Pos      (11U)\r
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */\r
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */\r
+\r
+/*******************  Bit definition for TIM_CR2 register  ********************/\r
+#define TIM_CR2_CCPC_Pos          (0U)\r
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */\r
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS_Pos          (2U)\r
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */\r
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS_Pos          (3U)\r
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */\r
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS_Pos           (4U)\r
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */\r
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */\r
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */\r
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */\r
+\r
+#define TIM_CR2_TI1S_Pos          (7U)\r
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */\r
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1_Pos          (8U)\r
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */\r
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N_Pos         (9U)\r
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */\r
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2_Pos          (10U)\r
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */\r
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N_Pos         (11U)\r
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */\r
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3_Pos          (12U)\r
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */\r
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N_Pos         (13U)\r
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */\r
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4_Pos          (14U)\r
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */\r
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS5_Pos          (16U)\r
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */\r
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */\r
+#define TIM_CR2_OIS6_Pos          (18U)\r
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */\r
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */\r
+\r
+#define TIM_CR2_MMS2_Pos          (20U)\r
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */\r
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */\r
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */\r
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */\r
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */\r
+\r
+/*******************  Bit definition for TIM_SMCR register  *******************/\r
+#define TIM_SMCR_SMS_Pos          (0U)\r
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */\r
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */\r
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */\r
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */\r
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */\r
+\r
+#define TIM_SMCR_OCCS_Pos         (3U)\r
+#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */\r
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */\r
+\r
+#define TIM_SMCR_TS_Pos           (4U)\r
+#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000070 */\r
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000010 */\r
+#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000020 */\r
+#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000040 */\r
+\r
+#define TIM_SMCR_MSM_Pos          (7U)\r
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */\r
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF_Pos          (8U)\r
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */\r
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */\r
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */\r
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */\r
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */\r
+\r
+#define TIM_SMCR_ETPS_Pos         (12U)\r
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */\r
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */\r
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */\r
+\r
+#define TIM_SMCR_ECE_Pos          (14U)\r
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */\r
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */\r
+#define TIM_SMCR_ETP_Pos          (15U)\r
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */\r
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\r
+\r
+/*******************  Bit definition for TIM_DIER register  *******************/\r
+#define TIM_DIER_UIE_Pos          (0U)\r
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */\r
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE_Pos        (1U)\r
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */\r
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE_Pos        (2U)\r
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */\r
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE_Pos        (3U)\r
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */\r
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE_Pos        (4U)\r
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */\r
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE_Pos        (5U)\r
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */\r
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE_Pos          (6U)\r
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */\r
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE_Pos          (7U)\r
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */\r
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE_Pos          (8U)\r
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */\r
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE_Pos        (9U)\r
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */\r
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE_Pos        (10U)\r
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */\r
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE_Pos        (11U)\r
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */\r
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE_Pos        (12U)\r
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */\r
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE_Pos        (13U)\r
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */\r
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE_Pos          (14U)\r
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */\r
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */\r
+\r
+/********************  Bit definition for TIM_SR register  ********************/\r
+#define TIM_SR_UIF_Pos            (0U)\r
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */\r
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF_Pos          (1U)\r
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */\r
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF_Pos          (2U)\r
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */\r
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF_Pos          (3U)\r
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */\r
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF_Pos          (4U)\r
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */\r
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF_Pos          (5U)\r
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */\r
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF_Pos            (6U)\r
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */\r
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF_Pos            (7U)\r
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */\r
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */\r
+#define TIM_SR_B2IF_Pos           (8U)\r
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */\r
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */\r
+#define TIM_SR_CC1OF_Pos          (9U)\r
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */\r
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF_Pos          (10U)\r
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */\r
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF_Pos          (11U)\r
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */\r
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF_Pos          (12U)\r
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */\r
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\r
+#define TIM_SR_SBIF_Pos           (13U)\r
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */\r
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */\r
+#define TIM_SR_CC5IF_Pos          (16U)\r
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */\r
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\r
+#define TIM_SR_CC6IF_Pos          (17U)\r
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */\r
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\r
+\r
+\r
+/*******************  Bit definition for TIM_EGR register  ********************/\r
+#define TIM_EGR_UG_Pos            (0U)\r
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */\r
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */\r
+#define TIM_EGR_CC1G_Pos          (1U)\r
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */\r
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G_Pos          (2U)\r
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */\r
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G_Pos          (3U)\r
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */\r
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G_Pos          (4U)\r
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */\r
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG_Pos          (5U)\r
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */\r
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG_Pos            (6U)\r
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */\r
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */\r
+#define TIM_EGR_BG_Pos            (7U)\r
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */\r
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */\r
+#define TIM_EGR_B2G_Pos           (8U)\r
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */\r
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */\r
+\r
+\r
+/******************  Bit definition for TIM_CCMR1 register  *******************/\r
+#define TIM_CCMR1_CC1S_Pos        (0U)\r
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */\r
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */\r
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR1_OC1FE_Pos       (2U)\r
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */\r
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE_Pos       (3U)\r
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */\r
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M_Pos        (4U)\r
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */\r
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */\r
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */\r
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */\r
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR1_OC1CE_Pos       (7U)\r
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */\r
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S_Pos        (8U)\r
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */\r
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */\r
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR1_OC2FE_Pos       (10U)\r
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */\r
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE_Pos       (11U)\r
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */\r
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M_Pos        (12U)\r
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */\r
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */\r
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */\r
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */\r
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR1_OC2CE_Pos       (15U)\r
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */\r
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#define TIM_CCMR1_IC1PSC_Pos      (2U)\r
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */\r
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */\r
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */\r
+\r
+#define TIM_CCMR1_IC1F_Pos        (4U)\r
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */\r
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */\r
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */\r
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */\r
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */\r
+\r
+#define TIM_CCMR1_IC2PSC_Pos      (10U)\r
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */\r
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */\r
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */\r
+\r
+#define TIM_CCMR1_IC2F_Pos        (12U)\r
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */\r
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */\r
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */\r
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */\r
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */\r
+\r
+/******************  Bit definition for TIM_CCMR2 register  *******************/\r
+#define TIM_CCMR2_CC3S_Pos        (0U)\r
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */\r
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */\r
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR2_OC3FE_Pos       (2U)\r
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */\r
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE_Pos       (3U)\r
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */\r
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M_Pos        (4U)\r
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */\r
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */\r
+#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */\r
+#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */\r
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR2_OC3CE_Pos       (7U)\r
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */\r
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S_Pos        (8U)\r
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */\r
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */\r
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR2_OC4FE_Pos       (10U)\r
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */\r
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE_Pos       (11U)\r
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */\r
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M_Pos        (12U)\r
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */\r
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */\r
+#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */\r
+#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */\r
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR2_OC4CE_Pos       (15U)\r
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */\r
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#define TIM_CCMR2_IC3PSC_Pos      (2U)\r
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */\r
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */\r
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */\r
+\r
+#define TIM_CCMR2_IC3F_Pos        (4U)\r
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */\r
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */\r
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */\r
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */\r
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */\r
+\r
+#define TIM_CCMR2_IC4PSC_Pos      (10U)\r
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */\r
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */\r
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */\r
+\r
+#define TIM_CCMR2_IC4F_Pos        (12U)\r
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */\r
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */\r
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */\r
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */\r
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */\r
+\r
+/******************  Bit definition for TIM_CCMR3 register  *******************/\r
+#define TIM_CCMR3_OC5FE_Pos       (2U)\r
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */\r
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\r
+#define TIM_CCMR3_OC5PE_Pos       (3U)\r
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */\r
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\r
+\r
+#define TIM_CCMR3_OC5M_Pos        (4U)\r
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */\r
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */\r
+#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */\r
+#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */\r
+#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */\r
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR3_OC5CE_Pos       (7U)\r
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */\r
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\r
+\r
+#define TIM_CCMR3_OC6FE_Pos       (10U)\r
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */\r
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */\r
+#define TIM_CCMR3_OC6PE_Pos       (11U)\r
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */\r
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */\r
+\r
+#define TIM_CCMR3_OC6M_Pos        (12U)\r
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */\r
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */\r
+#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */\r
+#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */\r
+#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */\r
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR3_OC6CE_Pos       (15U)\r
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */\r
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */\r
+\r
+/*******************  Bit definition for TIM_CCER register  *******************/\r
+#define TIM_CCER_CC1E_Pos         (0U)\r
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */\r
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P_Pos         (1U)\r
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */\r
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE_Pos        (2U)\r
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */\r
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP_Pos        (3U)\r
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */\r
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E_Pos         (4U)\r
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */\r
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P_Pos         (5U)\r
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */\r
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE_Pos        (6U)\r
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */\r
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP_Pos        (7U)\r
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */\r
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E_Pos         (8U)\r
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */\r
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P_Pos         (9U)\r
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */\r
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE_Pos        (10U)\r
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */\r
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP_Pos        (11U)\r
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */\r
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E_Pos         (12U)\r
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */\r
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P_Pos         (13U)\r
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */\r
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP_Pos        (15U)\r
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */\r
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\r
+#define TIM_CCER_CC5E_Pos         (16U)\r
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */\r
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\r
+#define TIM_CCER_CC5P_Pos         (17U)\r
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */\r
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\r
+#define TIM_CCER_CC6E_Pos         (20U)\r
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */\r
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\r
+#define TIM_CCER_CC6P_Pos         (21U)\r
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */\r
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\r
+\r
+/*******************  Bit definition for TIM_CNT register  ********************/\r
+#define TIM_CNT_CNT_Pos           (0U)\r
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */\r
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */\r
+#define TIM_CNT_UIFCPY_Pos        (31U)\r
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */\r
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */\r
+\r
+/*******************  Bit definition for TIM_PSC register  ********************/\r
+#define TIM_PSC_PSC_Pos           (0U)\r
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */\r
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */\r
+\r
+/*******************  Bit definition for TIM_ARR register  ********************/\r
+#define TIM_ARR_ARR_Pos           (0U)\r
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */\r
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */\r
+\r
+/*******************  Bit definition for TIM_RCR register  ********************/\r
+#define TIM_RCR_REP_Pos           (0U)\r
+#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */\r
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\r
+\r
+/*******************  Bit definition for TIM_CCR1 register  *******************/\r
+#define TIM_CCR1_CCR1_Pos         (0U)\r
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */\r
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */\r
+\r
+/*******************  Bit definition for TIM_CCR2 register  *******************/\r
+#define TIM_CCR2_CCR2_Pos         (0U)\r
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */\r
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */\r
+\r
+/*******************  Bit definition for TIM_CCR3 register  *******************/\r
+#define TIM_CCR3_CCR3_Pos         (0U)\r
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */\r
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */\r
+\r
+/*******************  Bit definition for TIM_CCR4 register  *******************/\r
+#define TIM_CCR4_CCR4_Pos         (0U)\r
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */\r
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */\r
+\r
+/*******************  Bit definition for TIM_CCR5 register  *******************/\r
+#define TIM_CCR5_CCR5_Pos         (0U)\r
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */\r
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\r
+#define TIM_CCR5_GC5C1_Pos        (29U)\r
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */\r
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\r
+#define TIM_CCR5_GC5C2_Pos        (30U)\r
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */\r
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\r
+#define TIM_CCR5_GC5C3_Pos        (31U)\r
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */\r
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\r
+\r
+/*******************  Bit definition for TIM_CCR6 register  *******************/\r
+#define TIM_CCR6_CCR6_Pos         (0U)\r
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */\r
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */\r
+\r
+/*******************  Bit definition for TIM_BDTR register  *******************/\r
+#define TIM_BDTR_DTG_Pos          (0U)\r
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */\r
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */\r
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */\r
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */\r
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */\r
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */\r
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */\r
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */\r
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */\r
+\r
+#define TIM_BDTR_LOCK_Pos         (8U)\r
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */\r
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */\r
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */\r
+\r
+#define TIM_BDTR_OSSI_Pos         (10U)\r
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */\r
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR_Pos         (11U)\r
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */\r
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE_Pos          (12U)\r
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */\r
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */\r
+#define TIM_BDTR_BKP_Pos          (13U)\r
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */\r
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */\r
+#define TIM_BDTR_AOE_Pos          (14U)\r
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */\r
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE_Pos          (15U)\r
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */\r
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */\r
+\r
+#define TIM_BDTR_BKF_Pos          (16U)\r
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */\r
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */\r
+#define TIM_BDTR_BK2F_Pos         (20U)\r
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */\r
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */\r
+\r
+#define TIM_BDTR_BK2E_Pos         (24U)\r
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */\r
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */\r
+#define TIM_BDTR_BK2P_Pos         (25U)\r
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */\r
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */\r
+\r
+/*******************  Bit definition for TIM_DCR register  ********************/\r
+#define TIM_DCR_DBA_Pos           (0U)\r
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */\r
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */\r
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */\r
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */\r
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */\r
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */\r
+\r
+#define TIM_DCR_DBL_Pos           (8U)\r
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */\r
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */\r
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */\r
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */\r
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */\r
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */\r
+\r
+/*******************  Bit definition for TIM_DMAR register  *******************/\r
+#define TIM_DMAR_DMAB_Pos         (0U)\r
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */\r
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */\r
+\r
+/*******************  Bit definition for TIM1_OR1 register  *******************/\r
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)\r
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000003 */\r
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */\r
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000001 */\r
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000002 */\r
+\r
+#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)\r
+#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x0000000C */\r
+#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */\r
+#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000004 */\r
+#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000008 */\r
+\r
+#define TIM1_OR1_TI1_RMP_Pos           (4U)\r
+#define TIM1_OR1_TI1_RMP_Msk           (0x1UL << TIM1_OR1_TI1_RMP_Pos)         /*!< 0x00000010 */\r
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */\r
+\r
+/*******************  Bit definition for TIM1_OR2 register  *******************/\r
+#define TIM1_OR2_BKINE_Pos             (0U)\r
+#define TIM1_OR2_BKINE_Msk             (0x1UL << TIM1_OR2_BKINE_Pos)           /*!< 0x00000001 */\r
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */\r
+#define TIM1_OR2_BKCMP1E_Pos           (1U)\r
+#define TIM1_OR2_BKCMP1E_Msk           (0x1UL << TIM1_OR2_BKCMP1E_Pos)         /*!< 0x00000002 */\r
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */\r
+#define TIM1_OR2_BKCMP2E_Pos           (2U)\r
+#define TIM1_OR2_BKCMP2E_Msk           (0x1UL << TIM1_OR2_BKCMP2E_Pos)         /*!< 0x00000004 */\r
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */\r
+#define TIM1_OR2_BKDF1BK0E_Pos         (8U)\r
+#define TIM1_OR2_BKDF1BK0E_Msk         (0x1UL << TIM1_OR2_BKDF1BK0E_Pos)       /*!< 0x00000100 */\r
+#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */\r
+#define TIM1_OR2_BKINP_Pos             (9U)\r
+#define TIM1_OR2_BKINP_Msk             (0x1UL << TIM1_OR2_BKINP_Pos)           /*!< 0x00000200 */\r
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */\r
+#define TIM1_OR2_BKCMP1P_Pos           (10U)\r
+#define TIM1_OR2_BKCMP1P_Msk           (0x1UL << TIM1_OR2_BKCMP1P_Pos)         /*!< 0x00000400 */\r
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */\r
+#define TIM1_OR2_BKCMP2P_Pos           (11U)\r
+#define TIM1_OR2_BKCMP2P_Msk           (0x1UL << TIM1_OR2_BKCMP2P_Pos)         /*!< 0x00000800 */\r
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */\r
+\r
+#define TIM1_OR2_ETRSEL_Pos            (14U)\r
+#define TIM1_OR2_ETRSEL_Msk            (0x7UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x0001C000 */\r
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */\r
+#define TIM1_OR2_ETRSEL_0              (0x1UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00004000 */\r
+#define TIM1_OR2_ETRSEL_1              (0x2UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00008000 */\r
+#define TIM1_OR2_ETRSEL_2              (0x4UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00010000 */\r
+\r
+/*******************  Bit definition for TIM1_OR3 register  *******************/\r
+#define TIM1_OR3_BK2INE_Pos            (0U)\r
+#define TIM1_OR3_BK2INE_Msk            (0x1UL << TIM1_OR3_BK2INE_Pos)          /*!< 0x00000001 */\r
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */\r
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)\r
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1UL << TIM1_OR3_BK2CMP1E_Pos)        /*!< 0x00000002 */\r
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */\r
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)\r
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1UL << TIM1_OR3_BK2CMP2E_Pos)        /*!< 0x00000004 */\r
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */\r
+#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)\r
+#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1UL << TIM1_OR3_BK2DF1BK1E_Pos)      /*!< 0x00000100 */\r
+#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */\r
+#define TIM1_OR3_BK2INP_Pos            (9U)\r
+#define TIM1_OR3_BK2INP_Msk            (0x1UL << TIM1_OR3_BK2INP_Pos)          /*!< 0x00000200 */\r
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */\r
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)\r
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1UL << TIM1_OR3_BK2CMP1P_Pos)        /*!< 0x00000400 */\r
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */\r
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)\r
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1UL << TIM1_OR3_BK2CMP2P_Pos)        /*!< 0x00000800 */\r
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */\r
+\r
+/*******************  Bit definition for TIM8_OR1 register  *******************/\r
+#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)\r
+#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos)    /*!< 0x00000003 */\r
+#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */\r
+#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos)    /*!< 0x00000001 */\r
+#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos)    /*!< 0x00000002 */\r
+\r
+#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)\r
+#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3UL << TIM8_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x0000000C */\r
+#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */\r
+#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1UL << TIM8_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000004 */\r
+#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2UL << TIM8_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000008 */\r
+\r
+#define TIM8_OR1_TI1_RMP_Pos           (4U)\r
+#define TIM8_OR1_TI1_RMP_Msk           (0x1UL << TIM8_OR1_TI1_RMP_Pos)         /*!< 0x00000010 */\r
+#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */\r
+\r
+/*******************  Bit definition for TIM8_OR2 register  *******************/\r
+#define TIM8_OR2_BKINE_Pos             (0U)\r
+#define TIM8_OR2_BKINE_Msk             (0x1UL << TIM8_OR2_BKINE_Pos)           /*!< 0x00000001 */\r
+#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */\r
+#define TIM8_OR2_BKCMP1E_Pos           (1U)\r
+#define TIM8_OR2_BKCMP1E_Msk           (0x1UL << TIM8_OR2_BKCMP1E_Pos)         /*!< 0x00000002 */\r
+#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */\r
+#define TIM8_OR2_BKCMP2E_Pos           (2U)\r
+#define TIM8_OR2_BKCMP2E_Msk           (0x1UL << TIM8_OR2_BKCMP2E_Pos)         /*!< 0x00000004 */\r
+#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */\r
+#define TIM8_OR2_BKDF1BK2E_Pos         (8U)\r
+#define TIM8_OR2_BKDF1BK2E_Msk         (0x1UL << TIM8_OR2_BKDF1BK2E_Pos)       /*!< 0x00000100 */\r
+#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */\r
+#define TIM8_OR2_BKINP_Pos             (9U)\r
+#define TIM8_OR2_BKINP_Msk             (0x1UL << TIM8_OR2_BKINP_Pos)           /*!< 0x00000200 */\r
+#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */\r
+#define TIM8_OR2_BKCMP1P_Pos           (10U)\r
+#define TIM8_OR2_BKCMP1P_Msk           (0x1UL << TIM8_OR2_BKCMP1P_Pos)         /*!< 0x00000400 */\r
+#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */\r
+#define TIM8_OR2_BKCMP2P_Pos           (11U)\r
+#define TIM8_OR2_BKCMP2P_Msk           (0x1UL << TIM8_OR2_BKCMP2P_Pos)         /*!< 0x00000800 */\r
+#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */\r
+\r
+#define TIM8_OR2_ETRSEL_Pos            (14U)\r
+#define TIM8_OR2_ETRSEL_Msk            (0x7UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x0001C000 */\r
+#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */\r
+#define TIM8_OR2_ETRSEL_0              (0x1UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x00004000 */\r
+#define TIM8_OR2_ETRSEL_1              (0x2UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x00008000 */\r
+#define TIM8_OR2_ETRSEL_2              (0x4UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x00010000 */\r
+\r
+/*******************  Bit definition for TIM8_OR3 register  *******************/\r
+#define TIM8_OR3_BK2INE_Pos            (0U)\r
+#define TIM8_OR3_BK2INE_Msk            (0x1UL << TIM8_OR3_BK2INE_Pos)          /*!< 0x00000001 */\r
+#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */\r
+#define TIM8_OR3_BK2CMP1E_Pos          (1U)\r
+#define TIM8_OR3_BK2CMP1E_Msk          (0x1UL << TIM8_OR3_BK2CMP1E_Pos)        /*!< 0x00000002 */\r
+#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */\r
+#define TIM8_OR3_BK2CMP2E_Pos          (2U)\r
+#define TIM8_OR3_BK2CMP2E_Msk          (0x1UL << TIM8_OR3_BK2CMP2E_Pos)        /*!< 0x00000004 */\r
+#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */\r
+#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)\r
+#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1UL << TIM8_OR3_BK2DF1BK3E_Pos)      /*!< 0x00000100 */\r
+#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */\r
+#define TIM8_OR3_BK2INP_Pos            (9U)\r
+#define TIM8_OR3_BK2INP_Msk            (0x1UL << TIM8_OR3_BK2INP_Pos)          /*!< 0x00000200 */\r
+#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */\r
+#define TIM8_OR3_BK2CMP1P_Pos          (10U)\r
+#define TIM8_OR3_BK2CMP1P_Msk          (0x1UL << TIM8_OR3_BK2CMP1P_Pos)        /*!< 0x00000400 */\r
+#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */\r
+#define TIM8_OR3_BK2CMP2P_Pos          (11U)\r
+#define TIM8_OR3_BK2CMP2P_Msk          (0x1UL << TIM8_OR3_BK2CMP2P_Pos)        /*!< 0x00000800 */\r
+#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */\r
+\r
+/*******************  Bit definition for TIM2_OR1 register  *******************/\r
+#define TIM2_OR1_ITR1_RMP_Pos     (0U)\r
+#define TIM2_OR1_ITR1_RMP_Msk     (0x1UL << TIM2_OR1_ITR1_RMP_Pos)             /*!< 0x00000001 */\r
+#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */\r
+#define TIM2_OR1_ETR1_RMP_Pos     (1U)\r
+#define TIM2_OR1_ETR1_RMP_Msk     (0x1UL << TIM2_OR1_ETR1_RMP_Pos)             /*!< 0x00000002 */\r
+#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */\r
+\r
+#define TIM2_OR1_TI4_RMP_Pos      (2U)\r
+#define TIM2_OR1_TI4_RMP_Msk      (0x3UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x0000000C */\r
+#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */\r
+#define TIM2_OR1_TI4_RMP_0        (0x1UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000004 */\r
+#define TIM2_OR1_TI4_RMP_1        (0x2UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000008 */\r
+\r
+/*******************  Bit definition for TIM2_OR2 register  *******************/\r
+#define TIM2_OR2_ETRSEL_Pos       (14U)\r
+#define TIM2_OR2_ETRSEL_Msk       (0x7UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */\r
+#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */\r
+#define TIM2_OR2_ETRSEL_0         (0x1UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00004000 */\r
+#define TIM2_OR2_ETRSEL_1         (0x2UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00008000 */\r
+#define TIM2_OR2_ETRSEL_2         (0x4UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00010000 */\r
+\r
+/*******************  Bit definition for TIM3_OR1 register  *******************/\r
+#define TIM3_OR1_TI1_RMP_Pos      (0U)\r
+#define TIM3_OR1_TI1_RMP_Msk      (0x3UL << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000003 */\r
+#define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */\r
+#define TIM3_OR1_TI1_RMP_0        (0x1UL << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000001 */\r
+#define TIM3_OR1_TI1_RMP_1        (0x2UL << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000002 */\r
+\r
+/*******************  Bit definition for TIM3_OR2 register  *******************/\r
+#define TIM3_OR2_ETRSEL_Pos       (14U)\r
+#define TIM3_OR2_ETRSEL_Msk       (0x7UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */\r
+#define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */\r
+#define TIM3_OR2_ETRSEL_0         (0x1UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00004000 */\r
+#define TIM3_OR2_ETRSEL_1         (0x2UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00008000 */\r
+#define TIM3_OR2_ETRSEL_2         (0x4UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00010000 */\r
+\r
+/*******************  Bit definition for TIM15_OR1 register  ******************/\r
+#define TIM15_OR1_TI1_RMP_Pos           (0U)\r
+#define TIM15_OR1_TI1_RMP_Msk           (0x1UL << TIM15_OR1_TI1_RMP_Pos)       /*!< 0x00000001 */\r
+#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */\r
+\r
+#define TIM15_OR1_ENCODER_MODE_Pos      (1U)\r
+#define TIM15_OR1_ENCODER_MODE_Msk      (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000006 */\r
+#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */\r
+#define TIM15_OR1_ENCODER_MODE_0        (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000002 */\r
+#define TIM15_OR1_ENCODER_MODE_1        (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000004 */\r
+\r
+/*******************  Bit definition for TIM15_OR2 register  ******************/\r
+#define TIM15_OR2_BKINE_Pos             (0U)\r
+#define TIM15_OR2_BKINE_Msk             (0x1UL << TIM15_OR2_BKINE_Pos)         /*!< 0x00000001 */\r
+#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */\r
+#define TIM15_OR2_BKCMP1E_Pos           (1U)\r
+#define TIM15_OR2_BKCMP1E_Msk           (0x1UL << TIM15_OR2_BKCMP1E_Pos)       /*!< 0x00000002 */\r
+#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */\r
+#define TIM15_OR2_BKCMP2E_Pos           (2U)\r
+#define TIM15_OR2_BKCMP2E_Msk           (0x1UL << TIM15_OR2_BKCMP2E_Pos)       /*!< 0x00000004 */\r
+#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */\r
+#define TIM15_OR2_BKDF1BK0E_Pos         (8U)\r
+#define TIM15_OR2_BKDF1BK0E_Msk         (0x1UL << TIM15_OR2_BKDF1BK0E_Pos)     /*!< 0x00000100 */\r
+#define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */\r
+#define TIM15_OR2_BKINP_Pos             (9U)\r
+#define TIM15_OR2_BKINP_Msk             (0x1UL << TIM15_OR2_BKINP_Pos)         /*!< 0x00000200 */\r
+#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */\r
+#define TIM15_OR2_BKCMP1P_Pos           (10U)\r
+#define TIM15_OR2_BKCMP1P_Msk           (0x1UL << TIM15_OR2_BKCMP1P_Pos)       /*!< 0x00000400 */\r
+#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */\r
+#define TIM15_OR2_BKCMP2P_Pos           (11U)\r
+#define TIM15_OR2_BKCMP2P_Msk           (0x1UL << TIM15_OR2_BKCMP2P_Pos)       /*!< 0x00000800 */\r
+#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */\r
+\r
+/*******************  Bit definition for TIM16_OR1 register  ******************/\r
+#define TIM16_OR1_TI1_RMP_Pos      (0U)\r
+#define TIM16_OR1_TI1_RMP_Msk      (0x3UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */\r
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */\r
+#define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */\r
+#define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */\r
+\r
+/*******************  Bit definition for TIM16_OR2 register  ******************/\r
+#define TIM16_OR2_BKINE_Pos        (0U)\r
+#define TIM16_OR2_BKINE_Msk        (0x1UL << TIM16_OR2_BKINE_Pos)              /*!< 0x00000001 */\r
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */\r
+#define TIM16_OR2_BKCMP1E_Pos      (1U)\r
+#define TIM16_OR2_BKCMP1E_Msk      (0x1UL << TIM16_OR2_BKCMP1E_Pos)            /*!< 0x00000002 */\r
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */\r
+#define TIM16_OR2_BKCMP2E_Pos      (2U)\r
+#define TIM16_OR2_BKCMP2E_Msk      (0x1UL << TIM16_OR2_BKCMP2E_Pos)            /*!< 0x00000004 */\r
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */\r
+#define TIM16_OR2_BKDF1BK1E_Pos    (8U)\r
+#define TIM16_OR2_BKDF1BK1E_Msk    (0x1UL << TIM16_OR2_BKDF1BK1E_Pos)          /*!< 0x00000100 */\r
+#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */\r
+#define TIM16_OR2_BKINP_Pos        (9U)\r
+#define TIM16_OR2_BKINP_Msk        (0x1UL << TIM16_OR2_BKINP_Pos)              /*!< 0x00000200 */\r
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */\r
+#define TIM16_OR2_BKCMP1P_Pos      (10U)\r
+#define TIM16_OR2_BKCMP1P_Msk      (0x1UL << TIM16_OR2_BKCMP1P_Pos)            /*!< 0x00000400 */\r
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */\r
+#define TIM16_OR2_BKCMP2P_Pos      (11U)\r
+#define TIM16_OR2_BKCMP2P_Msk      (0x1UL << TIM16_OR2_BKCMP2P_Pos)            /*!< 0x00000800 */\r
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */\r
+\r
+/*******************  Bit definition for TIM17_OR1 register  ******************/\r
+#define TIM17_OR1_TI1_RMP_Pos      (0U)\r
+#define TIM17_OR1_TI1_RMP_Msk      (0x3UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */\r
+#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */\r
+#define TIM17_OR1_TI1_RMP_0        (0x1UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */\r
+#define TIM17_OR1_TI1_RMP_1        (0x2UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */\r
+\r
+/*******************  Bit definition for TIM17_OR2 register  ******************/\r
+#define TIM17_OR2_BKINE_Pos        (0U)\r
+#define TIM17_OR2_BKINE_Msk        (0x1UL << TIM17_OR2_BKINE_Pos)              /*!< 0x00000001 */\r
+#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */\r
+#define TIM17_OR2_BKCMP1E_Pos      (1U)\r
+#define TIM17_OR2_BKCMP1E_Msk      (0x1UL << TIM17_OR2_BKCMP1E_Pos)            /*!< 0x00000002 */\r
+#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */\r
+#define TIM17_OR2_BKCMP2E_Pos      (2U)\r
+#define TIM17_OR2_BKCMP2E_Msk      (0x1UL << TIM17_OR2_BKCMP2E_Pos)            /*!< 0x00000004 */\r
+#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */\r
+#define TIM17_OR2_BKDF1BK2E_Pos    (8U)\r
+#define TIM17_OR2_BKDF1BK2E_Msk    (0x1UL << TIM17_OR2_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r
+#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */\r
+#define TIM17_OR2_BKINP_Pos        (9U)\r
+#define TIM17_OR2_BKINP_Msk        (0x1UL << TIM17_OR2_BKINP_Pos)              /*!< 0x00000200 */\r
+#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */\r
+#define TIM17_OR2_BKCMP1P_Pos      (10U)\r
+#define TIM17_OR2_BKCMP1P_Msk      (0x1UL << TIM17_OR2_BKCMP1P_Pos)            /*!< 0x00000400 */\r
+#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */\r
+#define TIM17_OR2_BKCMP2P_Pos      (11U)\r
+#define TIM17_OR2_BKCMP2P_Msk      (0x1UL << TIM17_OR2_BKCMP2P_Pos)            /*!< 0x00000800 */\r
+#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         Low Power Timer (LPTIM)                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for LPTIM_ISR register  *******************/\r
+#define LPTIM_ISR_CMPM_Pos          (0U)\r
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */\r
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */\r
+#define LPTIM_ISR_ARRM_Pos          (1U)\r
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */\r
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */\r
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)\r
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */\r
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */\r
+#define LPTIM_ISR_CMPOK_Pos         (3U)\r
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */\r
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */\r
+#define LPTIM_ISR_ARROK_Pos         (4U)\r
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */\r
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */\r
+#define LPTIM_ISR_UP_Pos            (5U)\r
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */\r
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */\r
+#define LPTIM_ISR_DOWN_Pos          (6U)\r
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */\r
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */\r
+\r
+/******************  Bit definition for LPTIM_ICR register  *******************/\r
+#define LPTIM_ICR_CMPMCF_Pos        (0U)\r
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */\r
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */\r
+#define LPTIM_ICR_ARRMCF_Pos        (1U)\r
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */\r
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */\r
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)\r
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */\r
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */\r
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)\r
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */\r
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */\r
+#define LPTIM_ICR_ARROKCF_Pos       (4U)\r
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */\r
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */\r
+#define LPTIM_ICR_UPCF_Pos          (5U)\r
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */\r
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */\r
+#define LPTIM_ICR_DOWNCF_Pos        (6U)\r
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */\r
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */\r
+\r
+/******************  Bit definition for LPTIM_IER register ********************/\r
+#define LPTIM_IER_CMPMIE_Pos        (0U)\r
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */\r
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */\r
+#define LPTIM_IER_ARRMIE_Pos        (1U)\r
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */\r
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */\r
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)\r
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */\r
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */\r
+#define LPTIM_IER_CMPOKIE_Pos       (3U)\r
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */\r
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */\r
+#define LPTIM_IER_ARROKIE_Pos       (4U)\r
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */\r
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */\r
+#define LPTIM_IER_UPIE_Pos          (5U)\r
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */\r
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */\r
+#define LPTIM_IER_DOWNIE_Pos        (6U)\r
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */\r
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */\r
+\r
+/******************  Bit definition for LPTIM_CFGR register *******************/\r
+#define LPTIM_CFGR_CKSEL_Pos        (0U)\r
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */\r
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */\r
+\r
+#define LPTIM_CFGR_CKPOL_Pos        (1U)\r
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */\r
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */\r
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */\r
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */\r
+\r
+#define LPTIM_CFGR_CKFLT_Pos        (3U)\r
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */\r
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */\r
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */\r
+\r
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)\r
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */\r
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */\r
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */\r
+\r
+#define LPTIM_CFGR_PRESC_Pos        (9U)\r
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */\r
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */\r
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */\r
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */\r
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */\r
+\r
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)\r
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */\r
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */\r
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */\r
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */\r
+\r
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)\r
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */\r
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */\r
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */\r
+\r
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)\r
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */\r
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */\r
+#define LPTIM_CFGR_WAVE_Pos         (20U)\r
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */\r
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */\r
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)\r
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */\r
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */\r
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)\r
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */\r
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */\r
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)\r
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */\r
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */\r
+#define LPTIM_CFGR_ENC_Pos          (24U)\r
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */\r
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */\r
+\r
+/******************  Bit definition for LPTIM_CR register  ********************/\r
+#define LPTIM_CR_ENABLE_Pos         (0U)\r
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */\r
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */\r
+#define LPTIM_CR_SNGSTRT_Pos        (1U)\r
+#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */\r
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */\r
+#define LPTIM_CR_CNTSTRT_Pos        (2U)\r
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */\r
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */\r
+\r
+/******************  Bit definition for LPTIM_CMP register  *******************/\r
+#define LPTIM_CMP_CMP_Pos           (0U)\r
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */\r
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */\r
+\r
+/******************  Bit definition for LPTIM_ARR register  *******************/\r
+#define LPTIM_ARR_ARR_Pos           (0U)\r
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */\r
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */\r
+\r
+/******************  Bit definition for LPTIM_CNT register  *******************/\r
+#define LPTIM_CNT_CNT_Pos           (0U)\r
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */\r
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */\r
+\r
+/******************  Bit definition for LPTIM_OR register  ********************/\r
+#define LPTIM_OR_OR_Pos             (0U)\r
+#define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */\r
+#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */\r
+#define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */\r
+#define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      Analog Comparators (COMP)                             */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/**********************  Bit definition for COMP_CSR register  ****************/\r
+#define COMP_CSR_EN_Pos            (0U)\r
+#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */\r
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */\r
+\r
+#define COMP_CSR_PWRMODE_Pos       (2U)\r
+#define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */\r
+#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */\r
+#define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */\r
+#define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */\r
+\r
+#define COMP_CSR_INMSEL_Pos        (4U)\r
+#define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */\r
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */\r
+#define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */\r
+#define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */\r
+#define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */\r
+\r
+#define COMP_CSR_INPSEL_Pos        (7U)\r
+#define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */\r
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */\r
+#define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */\r
+\r
+#define COMP_CSR_WINMODE_Pos       (9U)\r
+#define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000200 */\r
+#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */\r
+\r
+#define COMP_CSR_POLARITY_Pos      (15U)\r
+#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */\r
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */\r
+\r
+#define COMP_CSR_HYST_Pos          (16U)\r
+#define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */\r
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */\r
+#define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */\r
+#define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */\r
+\r
+#define COMP_CSR_BLANKING_Pos      (18U)\r
+#define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */\r
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */\r
+#define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */\r
+#define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */\r
+#define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */\r
+\r
+#define COMP_CSR_BRGEN_Pos         (22U)\r
+#define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */\r
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */\r
+#define COMP_CSR_SCALEN_Pos        (23U)\r
+#define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */\r
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */\r
+\r
+#define COMP_CSR_VALUE_Pos         (30U)\r
+#define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */\r
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */\r
+\r
+#define COMP_CSR_LOCK_Pos          (31U)\r
+#define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */\r
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         Operational Amplifier (OPAMP)                      */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*********************  Bit definition for OPAMPx_CSR register  ***************/\r
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)\r
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */\r
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */\r
+#define OPAMP_CSR_OPALPM_Pos             (1U)\r
+#define OPAMP_CSR_OPALPM_Msk             (0x1UL << OPAMP_CSR_OPALPM_Pos)       /*!< 0x00000002 */\r
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */\r
+\r
+#define OPAMP_CSR_OPAMODE_Pos            (2U)\r
+#define OPAMP_CSR_OPAMODE_Msk            (0x3UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x0000000C */\r
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */\r
+#define OPAMP_CSR_OPAMODE_0              (0x1UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000004 */\r
+#define OPAMP_CSR_OPAMODE_1              (0x2UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000008 */\r
+\r
+#define OPAMP_CSR_PGGAIN_Pos             (4U)\r
+#define OPAMP_CSR_PGGAIN_Msk             (0x3UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000030 */\r
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */\r
+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000010 */\r
+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000020 */\r
+\r
+#define OPAMP_CSR_VMSEL_Pos              (8U)\r
+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000300 */\r
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */\r
+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000100 */\r
+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000200 */\r
+\r
+#define OPAMP_CSR_VPSEL_Pos              (10U)\r
+#define OPAMP_CSR_VPSEL_Msk              (0x1UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x00000400 */\r
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */\r
+#define OPAMP_CSR_CALON_Pos              (12U)\r
+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00001000 */\r
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */\r
+#define OPAMP_CSR_CALSEL_Pos             (13U)\r
+#define OPAMP_CSR_CALSEL_Msk             (0x1UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00002000 */\r
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */\r
+#define OPAMP_CSR_USERTRIM_Pos           (14U)\r
+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00004000 */\r
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */\r
+#define OPAMP_CSR_CALOUT_Pos             (15U)\r
+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x00008000 */\r
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */\r
+\r
+/*********************  Bit definition for OPAMP1_CSR register  ***************/\r
+#define OPAMP1_CSR_OPAEN_Pos              (0U)\r
+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */\r
+#define OPAMP1_CSR_OPALPM_Pos             (1U)\r
+#define OPAMP1_CSR_OPALPM_Msk             (0x1UL << OPAMP1_CSR_OPALPM_Pos)     /*!< 0x00000002 */\r
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */\r
+\r
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)\r
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x0000000C */\r
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */\r
+#define OPAMP1_CSR_OPAMODE_0              (0x1UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000004 */\r
+#define OPAMP1_CSR_OPAMODE_1              (0x2UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000008 */\r
+\r
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)\r
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000030 */\r
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */\r
+#define OPAMP1_CSR_PGAGAIN_0              (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000010 */\r
+#define OPAMP1_CSR_PGAGAIN_1              (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000020 */\r
+\r
+#define OPAMP1_CSR_VMSEL_Pos              (8U)\r
+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000300 */\r
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r
+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000100 */\r
+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000200 */\r
+\r
+#define OPAMP1_CSR_VPSEL_Pos              (10U)\r
+#define OPAMP1_CSR_VPSEL_Msk              (0x1UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x00000400 */\r
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r
+#define OPAMP1_CSR_CALON_Pos              (12U)\r
+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00001000 */\r
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */\r
+#define OPAMP1_CSR_CALSEL_Pos             (13U)\r
+#define OPAMP1_CSR_CALSEL_Msk             (0x1UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00002000 */\r
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */\r
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)\r
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00004000 */\r
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */\r
+#define OPAMP1_CSR_CALOUT_Pos             (15U)\r
+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x00008000 */\r
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */\r
+\r
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)\r
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1UL << OPAMP1_CSR_OPARANGE_Pos)   /*!< 0x80000000 */\r
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */\r
+\r
+/*********************  Bit definition for OPAMP2_CSR register  ***************/\r
+#define OPAMP2_CSR_OPAEN_Pos              (0U)\r
+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */\r
+#define OPAMP2_CSR_OPALPM_Pos             (1U)\r
+#define OPAMP2_CSR_OPALPM_Msk             (0x1UL << OPAMP2_CSR_OPALPM_Pos)     /*!< 0x00000002 */\r
+#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */\r
+\r
+#define OPAMP2_CSR_OPAMODE_Pos            (2U)\r
+#define OPAMP2_CSR_OPAMODE_Msk            (0x3UL << OPAMP2_CSR_OPAMODE_Pos)    /*!< 0x0000000C */\r
+#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */\r
+#define OPAMP2_CSR_OPAMODE_0              (0x1UL << OPAMP2_CSR_OPAMODE_Pos)    /*!< 0x00000004 */\r
+#define OPAMP2_CSR_OPAMODE_1              (0x2UL << OPAMP2_CSR_OPAMODE_Pos)    /*!< 0x00000008 */\r
+\r
+#define OPAMP2_CSR_PGAGAIN_Pos            (4U)\r
+#define OPAMP2_CSR_PGAGAIN_Msk            (0x3UL << OPAMP2_CSR_PGAGAIN_Pos)    /*!< 0x00000030 */\r
+#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */\r
+#define OPAMP2_CSR_PGAGAIN_0              (0x1UL << OPAMP2_CSR_PGAGAIN_Pos)    /*!< 0x00000010 */\r
+#define OPAMP2_CSR_PGAGAIN_1              (0x2UL << OPAMP2_CSR_PGAGAIN_Pos)    /*!< 0x00000020 */\r
+\r
+#define OPAMP2_CSR_VMSEL_Pos              (8U)\r
+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000300 */\r
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r
+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000100 */\r
+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000200 */\r
+\r
+#define OPAMP2_CSR_VPSEL_Pos              (10U)\r
+#define OPAMP2_CSR_VPSEL_Msk              (0x1UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x00000400 */\r
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r
+#define OPAMP2_CSR_CALON_Pos              (12U)\r
+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00001000 */\r
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */\r
+#define OPAMP2_CSR_CALSEL_Pos             (13U)\r
+#define OPAMP2_CSR_CALSEL_Msk             (0x1UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00002000 */\r
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */\r
+#define OPAMP2_CSR_USERTRIM_Pos           (14U)\r
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00004000 */\r
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */\r
+#define OPAMP2_CSR_CALOUT_Pos             (15U)\r
+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x00008000 */\r
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */\r
+\r
+/*******************  Bit definition for OPAMP_OTR register  ******************/\r
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)\r
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */\r
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)\r
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */\r
+\r
+/*******************  Bit definition for OPAMP1_OTR register  ******************/\r
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)\r
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)\r
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r
+\r
+/*******************  Bit definition for OPAMP2_OTR register  ******************/\r
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)\r
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)\r
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r
+\r
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/\r
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)\r
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */\r
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)\r
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */\r
+\r
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/\r
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)\r
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)\r
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r
+\r
+/*******************  Bit definition for OPAMP2_LPOTR register  ****************/\r
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)\r
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)\r
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          Touch Sensing Controller (TSC)                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for TSC_CR register  *********************/\r
+#define TSC_CR_TSCE_Pos          (0U)\r
+#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */\r
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */\r
+#define TSC_CR_START_Pos         (1U)\r
+#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */\r
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */\r
+#define TSC_CR_AM_Pos            (2U)\r
+#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */\r
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */\r
+#define TSC_CR_SYNCPOL_Pos       (3U)\r
+#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */\r
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */\r
+#define TSC_CR_IODEF_Pos         (4U)\r
+#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */\r
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */\r
+\r
+#define TSC_CR_MCV_Pos           (5U)\r
+#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */\r
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */\r
+#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */\r
+#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */\r
+#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */\r
+\r
+#define TSC_CR_PGPSC_Pos         (12U)\r
+#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */\r
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */\r
+#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */\r
+#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */\r
+#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */\r
+\r
+#define TSC_CR_SSPSC_Pos         (15U)\r
+#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */\r
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */\r
+#define TSC_CR_SSE_Pos           (16U)\r
+#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */\r
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */\r
+\r
+#define TSC_CR_SSD_Pos           (17U)\r
+#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */\r
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */\r
+#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */\r
+#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */\r
+#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */\r
+#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */\r
+#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */\r
+#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */\r
+#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */\r
+\r
+#define TSC_CR_CTPL_Pos          (24U)\r
+#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */\r
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */\r
+#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */\r
+#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */\r
+#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */\r
+#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */\r
+\r
+#define TSC_CR_CTPH_Pos          (28U)\r
+#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */\r
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */\r
+#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */\r
+#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */\r
+#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */\r
+#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */\r
+\r
+/*******************  Bit definition for TSC_IER register  ********************/\r
+#define TSC_IER_EOAIE_Pos        (0U)\r
+#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */\r
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */\r
+#define TSC_IER_MCEIE_Pos        (1U)\r
+#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */\r
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */\r
+\r
+/*******************  Bit definition for TSC_ICR register  ********************/\r
+#define TSC_ICR_EOAIC_Pos        (0U)\r
+#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */\r
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */\r
+#define TSC_ICR_MCEIC_Pos        (1U)\r
+#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */\r
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */\r
+\r
+/*******************  Bit definition for TSC_ISR register  ********************/\r
+#define TSC_ISR_EOAF_Pos         (0U)\r
+#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */\r
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */\r
+#define TSC_ISR_MCEF_Pos         (1U)\r
+#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */\r
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */\r
+\r
+/*******************  Bit definition for TSC_IOHCR register  ******************/\r
+#define TSC_IOHCR_G1_IO1_Pos     (0U)\r
+#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */\r
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G1_IO2_Pos     (1U)\r
+#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */\r
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G1_IO3_Pos     (2U)\r
+#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */\r
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G1_IO4_Pos     (3U)\r
+#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */\r
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G2_IO1_Pos     (4U)\r
+#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */\r
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G2_IO2_Pos     (5U)\r
+#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */\r
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G2_IO3_Pos     (6U)\r
+#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */\r
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G2_IO4_Pos     (7U)\r
+#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */\r
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G3_IO1_Pos     (8U)\r
+#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */\r
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G3_IO2_Pos     (9U)\r
+#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */\r
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G3_IO3_Pos     (10U)\r
+#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */\r
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G3_IO4_Pos     (11U)\r
+#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */\r
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G4_IO1_Pos     (12U)\r
+#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */\r
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G4_IO2_Pos     (13U)\r
+#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */\r
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G4_IO3_Pos     (14U)\r
+#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */\r
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G4_IO4_Pos     (15U)\r
+#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */\r
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G5_IO1_Pos     (16U)\r
+#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */\r
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G5_IO2_Pos     (17U)\r
+#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */\r
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G5_IO3_Pos     (18U)\r
+#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */\r
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G5_IO4_Pos     (19U)\r
+#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */\r
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G6_IO1_Pos     (20U)\r
+#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */\r
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G6_IO2_Pos     (21U)\r
+#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */\r
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G6_IO3_Pos     (22U)\r
+#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */\r
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G6_IO4_Pos     (23U)\r
+#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */\r
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G7_IO1_Pos     (24U)\r
+#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */\r
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G7_IO2_Pos     (25U)\r
+#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */\r
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G7_IO3_Pos     (26U)\r
+#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */\r
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G7_IO4_Pos     (27U)\r
+#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */\r
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G8_IO1_Pos     (28U)\r
+#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)               /*!< 0x10000000 */\r
+#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G8_IO2_Pos     (29U)\r
+#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)               /*!< 0x20000000 */\r
+#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G8_IO3_Pos     (30U)\r
+#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)               /*!< 0x40000000 */\r
+#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */\r
+#define TSC_IOHCR_G8_IO4_Pos     (31U)\r
+#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)               /*!< 0x80000000 */\r
+#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */\r
+\r
+/*******************  Bit definition for TSC_IOASCR register  *****************/\r
+#define TSC_IOASCR_G1_IO1_Pos    (0U)\r
+#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */\r
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */\r
+#define TSC_IOASCR_G1_IO2_Pos    (1U)\r
+#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */\r
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */\r
+#define TSC_IOASCR_G1_IO3_Pos    (2U)\r
+#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */\r
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */\r
+#define TSC_IOASCR_G1_IO4_Pos    (3U)\r
+#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */\r
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */\r
+#define TSC_IOASCR_G2_IO1_Pos    (4U)\r
+#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */\r
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */\r
+#define TSC_IOASCR_G2_IO2_Pos    (5U)\r
+#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */\r
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */\r
+#define TSC_IOASCR_G2_IO3_Pos    (6U)\r
+#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */\r
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */\r
+#define TSC_IOASCR_G2_IO4_Pos    (7U)\r
+#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */\r
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */\r
+#define TSC_IOASCR_G3_IO1_Pos    (8U)\r
+#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */\r
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */\r
+#define TSC_IOASCR_G3_IO2_Pos    (9U)\r
+#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */\r
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */\r
+#define TSC_IOASCR_G3_IO3_Pos    (10U)\r
+#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */\r
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */\r
+#define TSC_IOASCR_G3_IO4_Pos    (11U)\r
+#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */\r
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */\r
+#define TSC_IOASCR_G4_IO1_Pos    (12U)\r
+#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */\r
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */\r
+#define TSC_IOASCR_G4_IO2_Pos    (13U)\r
+#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */\r
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */\r
+#define TSC_IOASCR_G4_IO3_Pos    (14U)\r
+#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */\r
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */\r
+#define TSC_IOASCR_G4_IO4_Pos    (15U)\r
+#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */\r
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */\r
+#define TSC_IOASCR_G5_IO1_Pos    (16U)\r
+#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */\r
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */\r
+#define TSC_IOASCR_G5_IO2_Pos    (17U)\r
+#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */\r
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */\r
+#define TSC_IOASCR_G5_IO3_Pos    (18U)\r
+#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */\r
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */\r
+#define TSC_IOASCR_G5_IO4_Pos    (19U)\r
+#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */\r
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */\r
+#define TSC_IOASCR_G6_IO1_Pos    (20U)\r
+#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */\r
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */\r
+#define TSC_IOASCR_G6_IO2_Pos    (21U)\r
+#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */\r
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */\r
+#define TSC_IOASCR_G6_IO3_Pos    (22U)\r
+#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */\r
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */\r
+#define TSC_IOASCR_G6_IO4_Pos    (23U)\r
+#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */\r
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */\r
+#define TSC_IOASCR_G7_IO1_Pos    (24U)\r
+#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */\r
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */\r
+#define TSC_IOASCR_G7_IO2_Pos    (25U)\r
+#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */\r
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */\r
+#define TSC_IOASCR_G7_IO3_Pos    (26U)\r
+#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */\r
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */\r
+#define TSC_IOASCR_G7_IO4_Pos    (27U)\r
+#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */\r
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */\r
+#define TSC_IOASCR_G8_IO1_Pos    (28U)\r
+#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)              /*!< 0x10000000 */\r
+#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */\r
+#define TSC_IOASCR_G8_IO2_Pos    (29U)\r
+#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)              /*!< 0x20000000 */\r
+#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */\r
+#define TSC_IOASCR_G8_IO3_Pos    (30U)\r
+#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)              /*!< 0x40000000 */\r
+#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */\r
+#define TSC_IOASCR_G8_IO4_Pos    (31U)\r
+#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)              /*!< 0x80000000 */\r
+#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */\r
+\r
+/*******************  Bit definition for TSC_IOSCR register  ******************/\r
+#define TSC_IOSCR_G1_IO1_Pos     (0U)\r
+#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */\r
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */\r
+#define TSC_IOSCR_G1_IO2_Pos     (1U)\r
+#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */\r
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */\r
+#define TSC_IOSCR_G1_IO3_Pos     (2U)\r
+#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */\r
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */\r
+#define TSC_IOSCR_G1_IO4_Pos     (3U)\r
+#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */\r
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */\r
+#define TSC_IOSCR_G2_IO1_Pos     (4U)\r
+#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */\r
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */\r
+#define TSC_IOSCR_G2_IO2_Pos     (5U)\r
+#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */\r
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */\r
+#define TSC_IOSCR_G2_IO3_Pos     (6U)\r
+#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */\r
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */\r
+#define TSC_IOSCR_G2_IO4_Pos     (7U)\r
+#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */\r
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */\r
+#define TSC_IOSCR_G3_IO1_Pos     (8U)\r
+#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */\r
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */\r
+#define TSC_IOSCR_G3_IO2_Pos     (9U)\r
+#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */\r
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */\r
+#define TSC_IOSCR_G3_IO3_Pos     (10U)\r
+#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */\r
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */\r
+#define TSC_IOSCR_G3_IO4_Pos     (11U)\r
+#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */\r
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */\r
+#define TSC_IOSCR_G4_IO1_Pos     (12U)\r
+#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */\r
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */\r
+#define TSC_IOSCR_G4_IO2_Pos     (13U)\r
+#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */\r
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */\r
+#define TSC_IOSCR_G4_IO3_Pos     (14U)\r
+#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */\r
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */\r
+#define TSC_IOSCR_G4_IO4_Pos     (15U)\r
+#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */\r
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */\r
+#define TSC_IOSCR_G5_IO1_Pos     (16U)\r
+#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */\r
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */\r
+#define TSC_IOSCR_G5_IO2_Pos     (17U)\r
+#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */\r
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */\r
+#define TSC_IOSCR_G5_IO3_Pos     (18U)\r
+#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */\r
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */\r
+#define TSC_IOSCR_G5_IO4_Pos     (19U)\r
+#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */\r
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */\r
+#define TSC_IOSCR_G6_IO1_Pos     (20U)\r
+#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */\r
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */\r
+#define TSC_IOSCR_G6_IO2_Pos     (21U)\r
+#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */\r
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */\r
+#define TSC_IOSCR_G6_IO3_Pos     (22U)\r
+#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */\r
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */\r
+#define TSC_IOSCR_G6_IO4_Pos     (23U)\r
+#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */\r
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */\r
+#define TSC_IOSCR_G7_IO1_Pos     (24U)\r
+#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */\r
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */\r
+#define TSC_IOSCR_G7_IO2_Pos     (25U)\r
+#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */\r
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */\r
+#define TSC_IOSCR_G7_IO3_Pos     (26U)\r
+#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */\r
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */\r
+#define TSC_IOSCR_G7_IO4_Pos     (27U)\r
+#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */\r
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */\r
+#define TSC_IOSCR_G8_IO1_Pos     (28U)\r
+#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)               /*!< 0x10000000 */\r
+#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */\r
+#define TSC_IOSCR_G8_IO2_Pos     (29U)\r
+#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)               /*!< 0x20000000 */\r
+#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */\r
+#define TSC_IOSCR_G8_IO3_Pos     (30U)\r
+#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)               /*!< 0x40000000 */\r
+#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */\r
+#define TSC_IOSCR_G8_IO4_Pos     (31U)\r
+#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)               /*!< 0x80000000 */\r
+#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */\r
+\r
+/*******************  Bit definition for TSC_IOCCR register  ******************/\r
+#define TSC_IOCCR_G1_IO1_Pos     (0U)\r
+#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */\r
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */\r
+#define TSC_IOCCR_G1_IO2_Pos     (1U)\r
+#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */\r
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */\r
+#define TSC_IOCCR_G1_IO3_Pos     (2U)\r
+#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */\r
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */\r
+#define TSC_IOCCR_G1_IO4_Pos     (3U)\r
+#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */\r
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */\r
+#define TSC_IOCCR_G2_IO1_Pos     (4U)\r
+#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */\r
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */\r
+#define TSC_IOCCR_G2_IO2_Pos     (5U)\r
+#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */\r
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */\r
+#define TSC_IOCCR_G2_IO3_Pos     (6U)\r
+#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */\r
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */\r
+#define TSC_IOCCR_G2_IO4_Pos     (7U)\r
+#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */\r
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */\r
+#define TSC_IOCCR_G3_IO1_Pos     (8U)\r
+#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */\r
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */\r
+#define TSC_IOCCR_G3_IO2_Pos     (9U)\r
+#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */\r
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */\r
+#define TSC_IOCCR_G3_IO3_Pos     (10U)\r
+#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */\r
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */\r
+#define TSC_IOCCR_G3_IO4_Pos     (11U)\r
+#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */\r
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */\r
+#define TSC_IOCCR_G4_IO1_Pos     (12U)\r
+#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */\r
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */\r
+#define TSC_IOCCR_G4_IO2_Pos     (13U)\r
+#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */\r
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */\r
+#define TSC_IOCCR_G4_IO3_Pos     (14U)\r
+#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */\r
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */\r
+#define TSC_IOCCR_G4_IO4_Pos     (15U)\r
+#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */\r
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */\r
+#define TSC_IOCCR_G5_IO1_Pos     (16U)\r
+#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */\r
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */\r
+#define TSC_IOCCR_G5_IO2_Pos     (17U)\r
+#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */\r
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */\r
+#define TSC_IOCCR_G5_IO3_Pos     (18U)\r
+#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */\r
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */\r
+#define TSC_IOCCR_G5_IO4_Pos     (19U)\r
+#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */\r
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */\r
+#define TSC_IOCCR_G6_IO1_Pos     (20U)\r
+#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */\r
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */\r
+#define TSC_IOCCR_G6_IO2_Pos     (21U)\r
+#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */\r
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */\r
+#define TSC_IOCCR_G6_IO3_Pos     (22U)\r
+#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */\r
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */\r
+#define TSC_IOCCR_G6_IO4_Pos     (23U)\r
+#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */\r
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */\r
+#define TSC_IOCCR_G7_IO1_Pos     (24U)\r
+#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */\r
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */\r
+#define TSC_IOCCR_G7_IO2_Pos     (25U)\r
+#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */\r
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */\r
+#define TSC_IOCCR_G7_IO3_Pos     (26U)\r
+#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */\r
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */\r
+#define TSC_IOCCR_G7_IO4_Pos     (27U)\r
+#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */\r
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */\r
+#define TSC_IOCCR_G8_IO1_Pos     (28U)\r
+#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)               /*!< 0x10000000 */\r
+#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */\r
+#define TSC_IOCCR_G8_IO2_Pos     (29U)\r
+#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)               /*!< 0x20000000 */\r
+#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */\r
+#define TSC_IOCCR_G8_IO3_Pos     (30U)\r
+#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)               /*!< 0x40000000 */\r
+#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */\r
+#define TSC_IOCCR_G8_IO4_Pos     (31U)\r
+#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)               /*!< 0x80000000 */\r
+#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */\r
+\r
+/*******************  Bit definition for TSC_IOGCSR register  *****************/\r
+#define TSC_IOGCSR_G1E_Pos       (0U)\r
+#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */\r
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */\r
+#define TSC_IOGCSR_G2E_Pos       (1U)\r
+#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */\r
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */\r
+#define TSC_IOGCSR_G3E_Pos       (2U)\r
+#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */\r
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */\r
+#define TSC_IOGCSR_G4E_Pos       (3U)\r
+#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */\r
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */\r
+#define TSC_IOGCSR_G5E_Pos       (4U)\r
+#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */\r
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */\r
+#define TSC_IOGCSR_G6E_Pos       (5U)\r
+#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */\r
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */\r
+#define TSC_IOGCSR_G7E_Pos       (6U)\r
+#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */\r
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */\r
+#define TSC_IOGCSR_G8E_Pos       (7U)\r
+#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                 /*!< 0x00000080 */\r
+#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */\r
+#define TSC_IOGCSR_G1S_Pos       (16U)\r
+#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */\r
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */\r
+#define TSC_IOGCSR_G2S_Pos       (17U)\r
+#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */\r
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */\r
+#define TSC_IOGCSR_G3S_Pos       (18U)\r
+#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */\r
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */\r
+#define TSC_IOGCSR_G4S_Pos       (19U)\r
+#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */\r
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */\r
+#define TSC_IOGCSR_G5S_Pos       (20U)\r
+#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */\r
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */\r
+#define TSC_IOGCSR_G6S_Pos       (21U)\r
+#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */\r
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */\r
+#define TSC_IOGCSR_G7S_Pos       (22U)\r
+#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */\r
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */\r
+#define TSC_IOGCSR_G8S_Pos       (23U)\r
+#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                 /*!< 0x00800000 */\r
+#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */\r
+\r
+/*******************  Bit definition for TSC_IOGXCR register  *****************/\r
+#define TSC_IOGXCR_CNT_Pos       (0U)\r
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */\r
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for USART_CR1 register  *******************/\r
+#define USART_CR1_UE_Pos              (0U)\r
+#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)              /*!< 0x00000001 */\r
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */\r
+#define USART_CR1_UESM_Pos            (1U)\r
+#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)            /*!< 0x00000002 */\r
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */\r
+#define USART_CR1_RE_Pos              (2U)\r
+#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)              /*!< 0x00000004 */\r
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */\r
+#define USART_CR1_TE_Pos              (3U)\r
+#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)              /*!< 0x00000008 */\r
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE_Pos          (4U)\r
+#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)          /*!< 0x00000010 */\r
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE_Pos          (5U)\r
+#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)          /*!< 0x00000020 */\r
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE_Pos            (6U)\r
+#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)            /*!< 0x00000040 */\r
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE_Pos           (7U)\r
+#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)           /*!< 0x00000080 */\r
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */\r
+#define USART_CR1_PEIE_Pos            (8U)\r
+#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)            /*!< 0x00000100 */\r
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS_Pos              (9U)\r
+#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)              /*!< 0x00000200 */\r
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */\r
+#define USART_CR1_PCE_Pos             (10U)\r
+#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)             /*!< 0x00000400 */\r
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE_Pos            (11U)\r
+#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)            /*!< 0x00000800 */\r
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */\r
+#define USART_CR1_M_Pos               (12U)\r
+#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)           /*!< 0x10001000 */\r
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */\r
+#define USART_CR1_M0_Pos              (12U)\r
+#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)              /*!< 0x00001000 */\r
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */\r
+#define USART_CR1_MME_Pos             (13U)\r
+#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)             /*!< 0x00002000 */\r
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE_Pos            (14U)\r
+#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)            /*!< 0x00004000 */\r
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8_Pos           (15U)\r
+#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)           /*!< 0x00008000 */\r
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT_Pos            (16U)\r
+#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)           /*!< 0x001F0000 */\r
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)           /*!< 0x00010000 */\r
+#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)           /*!< 0x00020000 */\r
+#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)           /*!< 0x00040000 */\r
+#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)           /*!< 0x00080000 */\r
+#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)           /*!< 0x00100000 */\r
+#define USART_CR1_DEAT_Pos            (21U)\r
+#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)           /*!< 0x03E00000 */\r
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)           /*!< 0x00200000 */\r
+#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)           /*!< 0x00400000 */\r
+#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)           /*!< 0x00800000 */\r
+#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)           /*!< 0x01000000 */\r
+#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)           /*!< 0x02000000 */\r
+#define USART_CR1_RTOIE_Pos           (26U)\r
+#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)           /*!< 0x04000000 */\r
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE_Pos           (27U)\r
+#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)           /*!< 0x08000000 */\r
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */\r
+#define USART_CR1_M1_Pos              (28U)\r
+#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)              /*!< 0x10000000 */\r
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */\r
+\r
+/******************  Bit definition for USART_CR2 register  *******************/\r
+#define USART_CR2_ADDM7_Pos           (4U)\r
+#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)           /*!< 0x00000010 */\r
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL_Pos            (5U)\r
+#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)            /*!< 0x00000020 */\r
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE_Pos           (6U)\r
+#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)           /*!< 0x00000040 */\r
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL_Pos            (8U)\r
+#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)            /*!< 0x00000100 */\r
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA_Pos            (9U)\r
+#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)            /*!< 0x00000200 */\r
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */\r
+#define USART_CR2_CPOL_Pos            (10U)\r
+#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)            /*!< 0x00000400 */\r
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN_Pos           (11U)\r
+#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)           /*!< 0x00000800 */\r
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */\r
+#define USART_CR2_STOP_Pos            (12U)\r
+#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)            /*!< 0x00003000 */\r
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)            /*!< 0x00001000 */\r
+#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)            /*!< 0x00002000 */\r
+#define USART_CR2_LINEN_Pos           (14U)\r
+#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)           /*!< 0x00004000 */\r
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */\r
+#define USART_CR2_SWAP_Pos            (15U)\r
+#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)            /*!< 0x00008000 */\r
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV_Pos           (16U)\r
+#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)           /*!< 0x00010000 */\r
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV_Pos           (17U)\r
+#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)           /*!< 0x00020000 */\r
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV_Pos         (18U)\r
+#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)         /*!< 0x00040000 */\r
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST_Pos        (19U)\r
+#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)        /*!< 0x00080000 */\r
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN_Pos           (20U)\r
+#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)           /*!< 0x00100000 */\r
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/\r
+#define USART_CR2_ABRMODE_Pos         (21U)\r
+#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00600000 */\r
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00200000 */\r
+#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00400000 */\r
+#define USART_CR2_RTOEN_Pos           (23U)\r
+#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)           /*!< 0x00800000 */\r
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD_Pos             (24U)\r
+#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)            /*!< 0xFF000000 */\r
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */\r
+\r
+/******************  Bit definition for USART_CR3 register  *******************/\r
+#define USART_CR3_EIE_Pos             (0U)\r
+#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)             /*!< 0x00000001 */\r
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN_Pos            (1U)\r
+#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)            /*!< 0x00000002 */\r
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP_Pos            (2U)\r
+#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)            /*!< 0x00000004 */\r
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL_Pos           (3U)\r
+#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)           /*!< 0x00000008 */\r
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK_Pos            (4U)\r
+#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)            /*!< 0x00000010 */\r
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN_Pos            (5U)\r
+#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)            /*!< 0x00000020 */\r
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR_Pos            (6U)\r
+#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)            /*!< 0x00000040 */\r
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT_Pos            (7U)\r
+#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)            /*!< 0x00000080 */\r
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE_Pos            (8U)\r
+#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)            /*!< 0x00000100 */\r
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */\r
+#define USART_CR3_CTSE_Pos            (9U)\r
+#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)            /*!< 0x00000200 */\r
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */\r
+#define USART_CR3_CTSIE_Pos           (10U)\r
+#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)           /*!< 0x00000400 */\r
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT_Pos          (11U)\r
+#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)          /*!< 0x00000800 */\r
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS_Pos          (12U)\r
+#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)          /*!< 0x00001000 */\r
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */\r
+#define USART_CR3_DDRE_Pos            (13U)\r
+#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)            /*!< 0x00002000 */\r
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM_Pos             (14U)\r
+#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)             /*!< 0x00004000 */\r
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP_Pos             (15U)\r
+#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)             /*!< 0x00008000 */\r
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT_Pos         (17U)\r
+#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)         /*!< 0x000E0000 */\r
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00020000 */\r
+#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00040000 */\r
+#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00080000 */\r
+#define USART_CR3_WUS_Pos             (20U)\r
+#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)             /*!< 0x00300000 */\r
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\r
+#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)             /*!< 0x00100000 */\r
+#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)             /*!< 0x00200000 */\r
+#define USART_CR3_WUFIE_Pos           (22U)\r
+#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)           /*!< 0x00400000 */\r
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */\r
+#define USART_CR3_UCESM_Pos           (23U)\r
+#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)           /*!< 0x02000000 */\r
+#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< USART Clock enable in Stop mode */\r
+\r
+/******************  Bit definition for USART_BRR register  *******************/\r
+#define USART_BRR_DIV_FRACTION_Pos    (0U)\r
+#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)    /*!< 0x0000000F */\r
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)\r
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)  /*!< 0x0000FFF0 */\r
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */\r
+\r
+/******************  Bit definition for USART_GTPR register  ******************/\r
+#define USART_GTPR_PSC_Pos            (0U)\r
+#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)           /*!< 0x000000FF */\r
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT_Pos             (8U)\r
+#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)            /*!< 0x0000FF00 */\r
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */\r
+\r
+/*******************  Bit definition for USART_RTOR register  *****************/\r
+#define USART_RTOR_RTO_Pos            (0U)\r
+#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)       /*!< 0x00FFFFFF */\r
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN_Pos           (24U)\r
+#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)          /*!< 0xFF000000 */\r
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */\r
+\r
+/*******************  Bit definition for USART_RQR register  ******************/\r
+#define USART_RQR_ABRRQ_Pos           (0U)\r
+#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)           /*!< 0x00000001 */\r
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ_Pos           (1U)\r
+#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)           /*!< 0x00000002 */\r
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */\r
+#define USART_RQR_MMRQ_Pos            (2U)\r
+#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)            /*!< 0x00000004 */\r
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ_Pos           (3U)\r
+#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)           /*!< 0x00000008 */\r
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ_Pos           (4U)\r
+#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)           /*!< 0x00000010 */\r
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */\r
+\r
+/*******************  Bit definition for USART_ISR register  ******************/\r
+#define USART_ISR_PE_Pos              (0U)\r
+#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)              /*!< 0x00000001 */\r
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */\r
+#define USART_ISR_FE_Pos              (1U)\r
+#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)              /*!< 0x00000002 */\r
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */\r
+#define USART_ISR_NE_Pos              (2U)\r
+#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)              /*!< 0x00000004 */\r
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise Error detected Flag */\r
+#define USART_ISR_ORE_Pos             (3U)\r
+#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)             /*!< 0x00000008 */\r
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */\r
+#define USART_ISR_IDLE_Pos            (4U)\r
+#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)            /*!< 0x00000010 */\r
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */\r
+#define USART_ISR_RXNE_Pos            (5U)\r
+#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)            /*!< 0x00000020 */\r
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */\r
+#define USART_ISR_TC_Pos              (6U)\r
+#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)              /*!< 0x00000040 */\r
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */\r
+#define USART_ISR_TXE_Pos             (7U)\r
+#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)             /*!< 0x00000080 */\r
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */\r
+#define USART_ISR_LBDF_Pos            (8U)\r
+#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)            /*!< 0x00000100 */\r
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF_Pos           (9U)\r
+#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)           /*!< 0x00000200 */\r
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS_Pos             (10U)\r
+#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)             /*!< 0x00000400 */\r
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */\r
+#define USART_ISR_RTOF_Pos            (11U)\r
+#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)            /*!< 0x00000800 */\r
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF_Pos            (12U)\r
+#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)            /*!< 0x00001000 */\r
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */\r
+#define USART_ISR_ABRE_Pos            (14U)\r
+#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)            /*!< 0x00004000 */\r
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF_Pos            (15U)\r
+#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)            /*!< 0x00008000 */\r
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY_Pos            (16U)\r
+#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)            /*!< 0x00010000 */\r
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */\r
+#define USART_ISR_CMF_Pos             (17U)\r
+#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)             /*!< 0x00020000 */\r
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */\r
+#define USART_ISR_SBKF_Pos            (18U)\r
+#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)            /*!< 0x00040000 */\r
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */\r
+#define USART_ISR_RWU_Pos             (19U)\r
+#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)             /*!< 0x00080000 */\r
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_WUF_Pos             (20U)\r
+#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)             /*!< 0x00100000 */\r
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */\r
+#define USART_ISR_TEACK_Pos           (21U)\r
+#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)           /*!< 0x00200000 */\r
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */\r
+#define USART_ISR_REACK_Pos           (22U)\r
+#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)           /*!< 0x00400000 */\r
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */\r
+\r
+/*******************  Bit definition for USART_ICR register  ******************/\r
+#define USART_ICR_PECF_Pos            (0U)\r
+#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)            /*!< 0x00000001 */\r
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF_Pos            (1U)\r
+#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)            /*!< 0x00000002 */\r
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NECF_Pos            (2U)\r
+#define USART_ICR_NECF_Msk            (0x1UL << USART_ICR_NECF_Pos)            /*!< 0x00000004 */\r
+#define USART_ICR_NECF                USART_ICR_NECF_Msk                       /*!< Noise Error detected Clear Flag */\r
+#define USART_ICR_ORECF_Pos           (3U)\r
+#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)           /*!< 0x00000008 */\r
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF_Pos          (4U)\r
+#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)          /*!< 0x00000010 */\r
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TCCF_Pos            (6U)\r
+#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)            /*!< 0x00000040 */\r
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_LBDCF_Pos           (8U)\r
+#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)           /*!< 0x00000100 */\r
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF_Pos           (9U)\r
+#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)           /*!< 0x00000200 */\r
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF_Pos           (11U)\r
+#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)           /*!< 0x00000800 */\r
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF_Pos           (12U)\r
+#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)           /*!< 0x00001000 */\r
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */\r
+#define USART_ICR_CMCF_Pos            (17U)\r
+#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)            /*!< 0x00020000 */\r
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */\r
+#define USART_ICR_WUCF_Pos            (20U)\r
+#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)            /*!< 0x00100000 */\r
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */\r
+\r
+/* Legacy defines */\r
+#define USART_ICR_NCF_Pos             USART_ICR_NECF_Pos\r
+#define USART_ICR_NCF_Msk             USART_ICR_NECF_Msk\r
+#define USART_ICR_NCF                 USART_ICR_NECF\r
+\r
+/*******************  Bit definition for USART_RDR register  ******************/\r
+#define USART_RDR_RDR_Pos             (0U)\r
+#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */\r
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/*******************  Bit definition for USART_TDR register  ******************/\r
+#define USART_TDR_TDR_Pos             (0U)\r
+#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */\r
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*           Single Wire Protocol Master Interface (SWPMI)                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for SWPMI_CR register   ********************/\r
+#define SWPMI_CR_RXDMA_Pos       (0U)\r
+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */\r
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */\r
+#define SWPMI_CR_TXDMA_Pos       (1U)\r
+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */\r
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */\r
+#define SWPMI_CR_RXMODE_Pos      (2U)\r
+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */\r
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */\r
+#define SWPMI_CR_TXMODE_Pos      (3U)\r
+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */\r
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */\r
+#define SWPMI_CR_LPBK_Pos        (4U)\r
+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */\r
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */\r
+#define SWPMI_CR_SWPACT_Pos      (5U)\r
+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */\r
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */\r
+#define SWPMI_CR_DEACT_Pos       (10U)\r
+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */\r
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */\r
+\r
+/*******************  Bit definition for SWPMI_BRR register  ********************/\r
+#define SWPMI_BRR_BR_Pos         (0U)\r
+#define SWPMI_BRR_BR_Msk         (0x3FUL << SWPMI_BRR_BR_Pos)                  /*!< 0x0000003F */\r
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */\r
+\r
+/*******************  Bit definition for SWPMI_ISR register  ********************/\r
+#define SWPMI_ISR_RXBFF_Pos      (0U)\r
+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */\r
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */\r
+#define SWPMI_ISR_TXBEF_Pos      (1U)\r
+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */\r
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */\r
+#define SWPMI_ISR_RXBERF_Pos     (2U)\r
+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */\r
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */\r
+#define SWPMI_ISR_RXOVRF_Pos     (3U)\r
+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */\r
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */\r
+#define SWPMI_ISR_TXUNRF_Pos     (4U)\r
+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */\r
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */\r
+#define SWPMI_ISR_RXNE_Pos       (5U)\r
+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */\r
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */\r
+#define SWPMI_ISR_TXE_Pos        (6U)\r
+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */\r
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */\r
+#define SWPMI_ISR_TCF_Pos        (7U)\r
+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */\r
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */\r
+#define SWPMI_ISR_SRF_Pos        (8U)\r
+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */\r
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */\r
+#define SWPMI_ISR_SUSP_Pos       (9U)\r
+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */\r
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */\r
+#define SWPMI_ISR_DEACTF_Pos     (10U)\r
+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */\r
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */\r
+\r
+/*******************  Bit definition for SWPMI_ICR register  ********************/\r
+#define SWPMI_ICR_CRXBFF_Pos     (0U)\r
+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */\r
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */\r
+#define SWPMI_ICR_CTXBEF_Pos     (1U)\r
+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */\r
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */\r
+#define SWPMI_ICR_CRXBERF_Pos    (2U)\r
+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */\r
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */\r
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)\r
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */\r
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */\r
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)\r
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */\r
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */\r
+#define SWPMI_ICR_CTCF_Pos       (7U)\r
+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */\r
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */\r
+#define SWPMI_ICR_CSRF_Pos       (8U)\r
+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */\r
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */\r
+\r
+/*******************  Bit definition for SWPMI_IER register  ********************/\r
+#define SWPMI_IER_SRIE_Pos       (8U)\r
+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */\r
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */\r
+#define SWPMI_IER_TCIE_Pos       (7U)\r
+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */\r
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */\r
+#define SWPMI_IER_TIE_Pos        (6U)\r
+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */\r
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */\r
+#define SWPMI_IER_RIE_Pos        (5U)\r
+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */\r
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */\r
+#define SWPMI_IER_TXUNRIE_Pos    (4U)\r
+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */\r
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */\r
+#define SWPMI_IER_RXOVRIE_Pos    (3U)\r
+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */\r
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */\r
+#define SWPMI_IER_RXBERIE_Pos    (2U)\r
+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */\r
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */\r
+#define SWPMI_IER_TXBEIE_Pos     (1U)\r
+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */\r
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */\r
+#define SWPMI_IER_RXBFIE_Pos     (0U)\r
+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */\r
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */\r
+\r
+/*******************  Bit definition for SWPMI_RFL register  ********************/\r
+#define SWPMI_RFL_RFL_Pos        (0U)\r
+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */\r
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */\r
+#define SWPMI_RFL_RFL_0_1_Pos    (0U)\r
+#define SWPMI_RFL_RFL_0_1_Msk    (0x3UL << SWPMI_RFL_RFL_0_1_Pos)              /*!< 0x00000003 */\r
+#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */\r
+\r
+/*******************  Bit definition for SWPMI_TDR register  ********************/\r
+#define SWPMI_TDR_TD_Pos         (0U)\r
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */\r
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */\r
+\r
+/*******************  Bit definition for SWPMI_RDR register  ********************/\r
+#define SWPMI_RDR_RD_Pos         (0U)\r
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */\r
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */\r
+\r
+/*******************  Bit definition for SWPMI_OR register  ********************/\r
+#define SWPMI_OR_TBYP_Pos        (0U)\r
+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */\r
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */\r
+#define SWPMI_OR_CLASS_Pos       (1U)\r
+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */\r
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                 VREFBUF                                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for VREFBUF_CSR register  ****************/\r
+#define VREFBUF_CSR_ENVR_Pos    (0U)\r
+#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */\r
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */\r
+#define VREFBUF_CSR_HIZ_Pos     (1U)\r
+#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */\r
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */\r
+#define VREFBUF_CSR_VRS_Pos     (2U)\r
+#define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */\r
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */\r
+#define VREFBUF_CSR_VRR_Pos     (3U)\r
+#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */\r
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */\r
+\r
+/*******************  Bit definition for VREFBUF_CCR register  ******************/\r
+#define VREFBUF_CCR_TRIM_Pos    (0U)\r
+#define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */\r
+#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                            Window WATCHDOG                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for WWDG_CR register  ********************/\r
+#define WWDG_CR_T_Pos           (0U)\r
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */\r
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */\r
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */\r
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */\r
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */\r
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */\r
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */\r
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */\r
+\r
+#define WWDG_CR_WDGA_Pos        (7U)\r
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */\r
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\r
+\r
+/*******************  Bit definition for WWDG_CFR register  *******************/\r
+#define WWDG_CFR_W_Pos          (0U)\r
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */\r
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */\r
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */\r
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */\r
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */\r
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */\r
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */\r
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */\r
+\r
+#define WWDG_CFR_WDGTB_Pos      (7U)\r
+#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000180 */\r
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000080 */\r
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000100 */\r
+\r
+#define WWDG_CFR_EWI_Pos        (9U)\r
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */\r
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\r
+\r
+/*******************  Bit definition for WWDG_SR register  ********************/\r
+#define WWDG_SR_EWIF_Pos        (0U)\r
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */\r
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                 Debug MCU                                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for DBGMCU_IDCODE register  *************/\r
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)\r
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk\r
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)\r
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk\r
+\r
+/********************  Bit definition for DBGMCU_CR register  *****************/\r
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)\r
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk\r
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)\r
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk\r
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)\r
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk\r
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)\r
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk\r
+\r
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)\r
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\r
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk\r
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\r
+\r
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/\r
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)\r
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)\r
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)\r
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)\r
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)\r
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)\r
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)\r
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\r
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)\r
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)\r
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\r
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)\r
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)\r
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)\r
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */\r
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)\r
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */\r
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk\r
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)\r
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */\r
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk\r
+\r
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/\r
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)\r
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk\r
+\r
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/\r
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)\r
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk\r
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)\r
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */\r
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk\r
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)\r
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk\r
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)\r
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */\r
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk\r
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)\r
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                       USB_OTG                              */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/\r
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\r
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\r
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\r
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\r
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\r
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\r
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\r
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\r
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\r
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\r
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\r
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/\r
+\r
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\r
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\r
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */\r
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\r
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */\r
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\r
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\r
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\r
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */\r
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\r
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */\r
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\r
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */\r
+\r
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\r
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\r
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\r
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\r
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\r
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\r
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\r
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\r
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\r
+\r
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\r
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\r
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\r
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\r
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\r
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\r
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\r
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\r
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\r
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\r
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\r
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */\r
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\r
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */\r
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\r
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */\r
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\r
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\r
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\r
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */\r
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\r
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */\r
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\r
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */\r
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\r
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */\r
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\r
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */\r
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\r
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */\r
+\r
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\r
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\r
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */\r
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\r
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */\r
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\r
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\r
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\r
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\r
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\r
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\r
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\r
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\r
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\r
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\r
+\r
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\r
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\r
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */\r
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\r
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */\r
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\r
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */\r
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\r
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */\r
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\r
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */\r
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\r
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\r
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */\r
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\r
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */\r
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\r
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */\r
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\r
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */\r
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\r
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */\r
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\r
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */\r
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\r
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */\r
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\r
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */\r
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\r
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */\r
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\r
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */\r
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\r
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */\r
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\r
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */\r
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\r
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */\r
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\r
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\r
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */\r
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\r
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */\r
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\r
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */\r
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\r
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\r
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\r
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */\r
+\r
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\r
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\r
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\r
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */\r
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\r
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */\r
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\r
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */\r
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\r
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\r
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */\r
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\r
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */\r
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\r
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */\r
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\r
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */\r
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\r
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */\r
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\r
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */\r
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\r
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */\r
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\r
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */\r
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\r
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\r
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\r
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\r
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */\r
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\r
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */\r
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\r
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */\r
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\r
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */\r
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\r
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\r
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */\r
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\r
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */\r
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\r
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */\r
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\r
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\r
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\r
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */\r
+\r
+/********************  Bit definition for USB_OTG_GRXSTSR/GRXSTSP registers  ***********/\r
+/* Host mode */\r
+#define USB_OTG_CHNUM_Pos                        (0U)\r
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */\r
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\r
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000001 */\r
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000002 */\r
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000004 */\r
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000008 */\r
+/* Device mode */\r
+#define USB_OTG_EPNUM_Pos                        (0U)\r
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */\r
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000001 */\r
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000002 */\r
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000004 */\r
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000008 */\r
+#define USB_OTG_FRMNUM_Pos                       (21U)\r
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */\r
+/* Host/Device mode */\r
+#define USB_OTG_BCNT_Pos                         (4U)\r
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\r
+#define USB_OTG_DPID_Pos                         (15U)\r
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */\r
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\r
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)   /*!< 0x00008000 */\r
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)   /*!< 0x00010000 */\r
+#define USB_OTG_PKTSTS_Pos                       (17U)\r
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */\r
+\r
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\r
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\r
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\r
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\r
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\r
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\r
+\r
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\r
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\r
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\r
+\r
+/********************  Bit definition for USB_OTG_HNPTXFSIZ/DIEPTXF0 register  *********/\r
+#define USB_OTG_NPTXFSA_Pos                      (0U)\r
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\r
+#define USB_OTG_NPTXFD_Pos                       (16U)\r
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */\r
+#define USB_OTG_TX0FSA_Pos                       (0U)\r
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */\r
+#define USB_OTG_TX0FD_Pos                        (16U)\r
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */\r
+\r
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r
+\r
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/\r
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\r
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\r
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)\r
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\r
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)\r
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\r
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\r
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\r
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\r
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\r
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\r
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\r
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\r
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\r
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\r
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\r
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\r
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\r
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\r
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */\r
+\r
+/********************  Bit definition for USB_OTG_CID register  ********************/\r
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\r
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\r
+\r
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\r
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\r
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */\r
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\r
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */\r
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\r
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */\r
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\r
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */\r
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\r
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */\r
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\r
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */\r
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\r
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */\r
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\r
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */\r
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\r
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */\r
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\r
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\r
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */\r
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\r
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/\r
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\r
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */\r
+\r
+/* Legacy defines */\r
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           USB_OTG_GLPMCFG_L1RSMOK_Pos\r
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           USB_OTG_GLPMCFG_L1RSMOK_Msk\r
+#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1RSMOK\r
+\r
+/********************  Bit definition for USB_OTG_GPWRDN register  **********************/\r
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)\r
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1UL << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */\r
+\r
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\r
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\r
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */\r
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\r
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */\r
+\r
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\r
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\r
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\r
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\r
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\r
+\r
+/********************  Bit definition for USB_OTG_HCFG register  ********************/\r
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\r
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */\r
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\r
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\r
+\r
+/********************  Bit definition for USB_OTG_HFIR register  ********************/\r
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\r
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\r
+\r
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/\r
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\r
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */\r
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\r
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\r
+\r
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\r
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\r
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r
+\r
+/********************  Bit definition for USB_OTG_HAINT register  ********************/\r
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)\r
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\r
+\r
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\r
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\r
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\r
+\r
+/********************  Bit definition for USB_OTG_HPRT register  ********************/\r
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\r
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */\r
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)\r
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */\r
+#define USB_OTG_HPRT_PENA_Pos                    (2U)\r
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */\r
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\r
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\r
+#define USB_OTG_HPRT_POCA_Pos                    (4U)\r
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */\r
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\r
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */\r
+#define USB_OTG_HPRT_PRES_Pos                    (6U)\r
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */\r
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\r
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */\r
+#define USB_OTG_HPRT_PRST_Pos                    (8U)\r
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */\r
+\r
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\r
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */\r
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)\r
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */\r
+\r
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\r
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */\r
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)\r
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */\r
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r
+\r
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\r
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\r
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\r
+\r
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\r
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\r
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\r
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\r
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\r
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\r
+\r
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\r
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\r
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r
+\r
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)\r
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\r
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r
+\r
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\r
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\r
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\r
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\r
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\r
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\r
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\r
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\r
+\r
+/********************  Bit definition for USB_OTG_HCINT register  ********************/\r
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)\r
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\r
+#define USB_OTG_HCINT_CHH_Pos                    (1U)\r
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\r
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\r
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\r
+#define USB_OTG_HCINT_STALL_Pos                  (3U)\r
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\r
+#define USB_OTG_HCINT_NAK_Pos                    (4U)\r
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\r
+#define USB_OTG_HCINT_ACK_Pos                    (5U)\r
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\r
+#define USB_OTG_HCINT_NYET_Pos                   (6U)\r
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\r
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)\r
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\r
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)\r
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\r
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\r
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\r
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)\r
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\r
+\r
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/\r
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\r
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\r
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\r
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\r
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\r
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\r
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\r
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\r
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\r
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\r
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\r
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\r
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\r
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\r
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\r
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\r
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\r
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\r
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\r
+\r
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\r
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\r
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\r
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\r
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\r
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\r
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\r
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\r
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\r
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r
+\r
+/********************  Bit definition for USB_OTG_HCDMA register  *********************/\r
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\r
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\r
+\r
+/********************  Bit definition for USB_OTG_DCFG register  ********************/\r
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)\r
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\r
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\r
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\r
+#define USB_OTG_DCFG_DAD_Pos                     (4U)\r
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\r
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\r
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\r
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\r
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\r
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r
+\r
+/********************  Bit definition for USB_OTG_DCTL register  ********************/\r
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\r
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\r
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)\r
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */\r
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\r
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */\r
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\r
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */\r
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)\r
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\r
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\r
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */\r
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\r
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */\r
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\r
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */\r
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\r
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */\r
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\r
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\r
+\r
+/********************  Bit definition for USB_OTG_DSTS register  ********************/\r
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\r
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */\r
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\r
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\r
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DSTS_EERR_Pos                    (3U)\r
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */\r
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\r
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\r
+\r
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\r
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\r
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\r
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\r
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\r
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\r
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\r
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\r
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */\r
+\r
+/* Legacy defines */\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           USB_OTG_DIEPMSK_XFRCM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           USB_OTG_DIEPMSK_XFRCM_Msk\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPMSK_XFRCM\r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            USB_OTG_DIEPMSK_EPDM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            USB_OTG_DIEPMSK_EPDM_Msk\r
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPMSK_EPDM\r
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             USB_OTG_DIEPMSK_TOM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             USB_OTG_DIEPMSK_TOM_Msk\r
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPMSK_TOM\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       USB_OTG_DIEPMSK_ITTXFEMSK_Pos\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       USB_OTG_DIEPMSK_ITTXFEMSK_Msk\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPMSK_ITTXFEMSK\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         USB_OTG_DIEPMSK_INEPNMM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         USB_OTG_DIEPMSK_INEPNMM_Msk\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPMSK_INEPNMM\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         USB_OTG_DIEPMSK_INEPNEM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         USB_OTG_DIEPMSK_INEPNEM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPMSK_INEPNEM\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          USB_OTG_DIEPMSK_TXFURM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          USB_OTG_DIEPMSK_TXFURM_Msk\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPMSK_TXFURM\r
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             USB_OTG_DIEPMSK_BIM_Pos\r
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             USB_OTG_DIEPMSK_BIM_Msk\r
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPMSK_BIM\r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+\r
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\r
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\r
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\r
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\r
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */\r
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\r
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\r
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\r
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */\r
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\r
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\r
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */\r
+\r
+/* Legacy defines */\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           USB_OTG_DOEPMSK_XFRCM_Pos\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           USB_OTG_DOEPMSK_XFRCM_Msk\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPMSK_XFRCM\r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            USB_OTG_DOEPMSK_EPDM_Pos\r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            USB_OTG_DOEPMSK_EPDM_Msk\r
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPMSK_EPDM\r
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             USB_OTG_DOEPMSK_STUPM_Pos\r
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             USB_OTG_DOEPMSK_STUPM_Msk\r
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPMSK_STUPM\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       USB_OTG_DOEPMSK_OTEPDM_Pos\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       USB_OTG_DOEPMSK_OTEPDM_Msk\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPMSK_OTEPDM\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         USB_OTG_DOEPMSK_B2BSTUP_Pos\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         USB_OTG_DOEPMSK_B2BSTUP_Msk\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPMSK_B2BSTUP\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          USB_OTG_DOEPMSK_OPEM_Pos\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          USB_OTG_DOEPMSK_OPEM_Msk\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPMSK_OPEM\r
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             USB_OTG_DOEPMSK_BOIM_Pos\r
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             USB_OTG_DOEPMSK_BOIM_Msk\r
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPMSK_BOIM\r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\r
+\r
+/********************  Bit definition for USB_OTG_DAINT register  ********************/\r
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\r
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */\r
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\r
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\r
+\r
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\r
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\r
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\r
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\r
+\r
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\r
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\r
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\r
+\r
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/\r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r
+\r
+/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/\r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\r
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\r
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\r
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\r
+\r
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r
+\r
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\r
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\r
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */\r
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\r
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\r
+\r
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r
+\r
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\r
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\r
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */\r
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\r
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\r
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\r
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */\r
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\r
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */\r
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\r
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */\r
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\r
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */\r
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\r
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */\r
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\r
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\r
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\r
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\r
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */\r
+\r
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\r
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\r
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\r
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\r
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\r
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\r
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\r
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\r
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\r
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\r
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\r
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\r
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\r
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\r
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\r
+\r
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\r
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\r
+\r
+/********************  Bit definition for USB_OTG_DIEPDMA register  *********************/\r
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\r
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\r
+\r
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */\r
+\r
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\r
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\r
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\r
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\r
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\r
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\r
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\r
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\r
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\r
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\r
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\r
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\r
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\r
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\r
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\r
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\r
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\r
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\r
+\r
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\r
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\r
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\r
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\r
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\r
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\r
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\r
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\r
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\r
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\r
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\r
+\r
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r
+\r
+/********************  Bit definition for USB_OTG_PCGCCTL register  ********************/\r
+#define USB_OTG_PCGCCTL_STPPCLK_Pos              (0U)\r
+#define USB_OTG_PCGCCTL_STPPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STPPCLK_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_PCGCCTL_STPPCLK                  USB_OTG_PCGCCTL_STPPCLK_Msk   /*!< Stop PHY clock */\r
+#define USB_OTG_PCGCCTL_GATEHCLK_Pos             (1U)\r
+#define USB_OTG_PCGCCTL_GATEHCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATEHCLK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_PCGCCTL_GATEHCLK                 USB_OTG_PCGCCTL_GATEHCLK_Msk   /*!< Gate HCLK */\r
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\r
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\r
+\r
+/* Legacy defines */\r
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              USB_OTG_PCGCCTL_STPPCLK_Pos\r
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              USB_OTG_PCGCCTL_STPPCLK_Msk\r
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STPPCLK\r
+#define USB_OTG_PCGCCTL_GATECLK_Pos              USB_OTG_PCGCCTL_GATEHCLK_Pos\r
+#define USB_OTG_PCGCCTL_GATECLK_Msk              USB_OTG_PCGCCTL_GATEHCLK_Msk\r
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATEHCLK\r
+#define USB_OTG_PCGCR_STPPCLK_Pos                USB_OTG_PCGCCTL_STPPCLK_Pos\r
+#define USB_OTG_PCGCR_STPPCLK_Msk                USB_OTG_PCGCCTL_STPPCLK_Msk\r
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCCTL_STPPCLK\r
+#define USB_OTG_PCGCR_GATEHCLK_Pos               USB_OTG_PCGCCTL_GATEHCLK_Pos\r
+#define USB_OTG_PCGCR_GATEHCLK_Msk               USB_OTG_PCGCCTL_GATEHCLK_Msk\r
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCCTL_GATEHCLK\r
+#define USB_OTG_PCGCR_PHYSUSP_Pos                USB_OTG_PCGCCTL_PHYSUSP_Pos\r
+#define USB_OTG_PCGCR_PHYSUSP_Msk                USB_OTG_PCGCCTL_PHYSUSP_Msk\r
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCCTL_PHYSUSP\r
+#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)\r
+#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1UL << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */\r
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\r
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\r
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\r
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\r
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\r
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\r
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\r
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\r
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\r
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Exported_macros\r
+  * @{\r
+  */\r
+\r
+/******************************* ADC Instances ********************************/\r
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\r
+                                       ((INSTANCE) == ADC2) || \\r
+                                       ((INSTANCE) == ADC3))\r
+\r
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r
+\r
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\r
+\r
+/******************************** CAN Instances ******************************/\r
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)\r
+\r
+/******************************** COMP Instances ******************************/\r
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\r
+                                        ((INSTANCE) == COMP2))\r
+\r
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)\r
+\r
+/******************** COMP Instances with window mode capability **************/\r
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)\r
+\r
+/******************************* CRC Instances ********************************/\r
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\r
+\r
+/******************************* DAC Instances ********************************/\r
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\r
+\r
+/****************************** DFSDM Instances *******************************/\r
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\r
+                                                ((INSTANCE) == DFSDM1_Filter1) || \\r
+                                                ((INSTANCE) == DFSDM1_Filter2) || \\r
+                                                ((INSTANCE) == DFSDM1_Filter3))\r
+\r
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\r
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \\r
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \\r
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \\r
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \\r
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \\r
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \\r
+                                                 ((INSTANCE) == DFSDM1_Channel7))\r
+\r
+/******************************** DMA Instances *******************************/\r
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \\r
+                                       ((INSTANCE) == DMA1_Channel2) || \\r
+                                       ((INSTANCE) == DMA1_Channel3) || \\r
+                                       ((INSTANCE) == DMA1_Channel4) || \\r
+                                       ((INSTANCE) == DMA1_Channel5) || \\r
+                                       ((INSTANCE) == DMA1_Channel6) || \\r
+                                       ((INSTANCE) == DMA1_Channel7) || \\r
+                                       ((INSTANCE) == DMA2_Channel1) || \\r
+                                       ((INSTANCE) == DMA2_Channel2) || \\r
+                                       ((INSTANCE) == DMA2_Channel3) || \\r
+                                       ((INSTANCE) == DMA2_Channel4) || \\r
+                                       ((INSTANCE) == DMA2_Channel5) || \\r
+                                       ((INSTANCE) == DMA2_Channel6) || \\r
+                                       ((INSTANCE) == DMA2_Channel7))\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\r
+                                        ((INSTANCE) == GPIOB) || \\r
+                                        ((INSTANCE) == GPIOC) || \\r
+                                        ((INSTANCE) == GPIOD) || \\r
+                                        ((INSTANCE) == GPIOE) || \\r
+                                        ((INSTANCE) == GPIOF) || \\r
+                                        ((INSTANCE) == GPIOG) || \\r
+                                        ((INSTANCE) == GPIOH))\r
+\r
+/******************************* GPIO AF Instances ****************************/\r
+/* On L4, all GPIO Bank support AF */\r
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)\r
+\r
+/**************************** GPIO Lock Instances *****************************/\r
+/* On L4, all GPIO Bank support the Lock mechanism */\r
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
+\r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
+                                       ((INSTANCE) == I2C2) || \\r
+                                       ((INSTANCE) == I2C3))\r
+\r
+/****************** I2C Instances : wakeup capability from stop modes *********/\r
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\r
+\r
+/******************************* HCD Instances *******************************/\r
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)\r
+\r
+/****************************** OPAMP Instances *******************************/\r
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\r
+                                         ((INSTANCE) == OPAMP2))\r
+\r
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\r
+\r
+/******************************* PCD Instances *******************************/\r
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)\r
+\r
+/******************************* QSPI Instances *******************************/\r
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)\r
+\r
+/******************************* RNG Instances ********************************/\r
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\r
+\r
+/******************************** SAI Instances *******************************/\r
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \\r
+                                       ((INSTANCE) == SAI1_Block_B) || \\r
+                                       ((INSTANCE) == SAI2_Block_A) || \\r
+                                       ((INSTANCE) == SAI2_Block_B))\r
+\r
+/****************************** SDMMC Instances *******************************/\r
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)\r
+\r
+/****************************** SMBUS Instances *******************************/\r
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
+                                         ((INSTANCE) == I2C2) || \\r
+                                         ((INSTANCE) == I2C3))\r
+\r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\r
+                                       ((INSTANCE) == SPI2) || \\r
+                                       ((INSTANCE) == SPI3))\r
+\r
+/******************************** SWPMI Instances *****************************/\r
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)\r
+\r
+/****************** LPTIM Instances : All supported instances *****************/\r
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\r
+                                         ((INSTANCE) == LPTIM2))\r
+\r
+/****************** LPTIM Instances : supporting the encoder mode *************/\r
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)\r
+\r
+/****************** TIM Instances : All supported instances *******************/\r
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\r
+                                         ((INSTANCE) == TIM2)   || \\r
+                                         ((INSTANCE) == TIM3)   || \\r
+                                         ((INSTANCE) == TIM4)   || \\r
+                                         ((INSTANCE) == TIM5)   || \\r
+                                         ((INSTANCE) == TIM6)   || \\r
+                                         ((INSTANCE) == TIM7)   || \\r
+                                         ((INSTANCE) == TIM8)   || \\r
+                                         ((INSTANCE) == TIM15)  || \\r
+                                         ((INSTANCE) == TIM16)  || \\r
+                                         ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting 32 bits counter ****************/\r
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \\r
+                                               ((INSTANCE) == TIM5))\r
+\r
+/****************** TIM Instances : supporting the break function *************/\r
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\r
+                                            ((INSTANCE) == TIM8)    || \\r
+                                            ((INSTANCE) == TIM15)   || \\r
+                                            ((INSTANCE) == TIM16)   || \\r
+                                            ((INSTANCE) == TIM17))\r
+\r
+/************** TIM Instances : supporting Break source selection *************/\r
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
+                                               ((INSTANCE) == TIM8)   || \\r
+                                               ((INSTANCE) == TIM15)  || \\r
+                                               ((INSTANCE) == TIM16)  || \\r
+                                               ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting 2 break inputs *****************/\r
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\r
+                                            ((INSTANCE) == TIM8))\r
+\r
+/************* TIM Instances : at least 1 capture/compare channel *************/\r
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
+                                         ((INSTANCE) == TIM2)   || \\r
+                                         ((INSTANCE) == TIM3)   || \\r
+                                         ((INSTANCE) == TIM4)   || \\r
+                                         ((INSTANCE) == TIM5)   || \\r
+                                         ((INSTANCE) == TIM8)   || \\r
+                                         ((INSTANCE) == TIM15)  || \\r
+                                         ((INSTANCE) == TIM16)  || \\r
+                                         ((INSTANCE) == TIM17))\r
+\r
+/************ TIM Instances : at least 2 capture/compare channels *************/\r
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
+                                         ((INSTANCE) == TIM2)   || \\r
+                                         ((INSTANCE) == TIM3)   || \\r
+                                         ((INSTANCE) == TIM4)   || \\r
+                                         ((INSTANCE) == TIM5)   || \\r
+                                         ((INSTANCE) == TIM8)   || \\r
+                                         ((INSTANCE) == TIM15))\r
+\r
+/************ TIM Instances : at least 3 capture/compare channels *************/\r
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
+                                         ((INSTANCE) == TIM2)   || \\r
+                                         ((INSTANCE) == TIM3)   || \\r
+                                         ((INSTANCE) == TIM4)   || \\r
+                                         ((INSTANCE) == TIM5)   || \\r
+                                         ((INSTANCE) == TIM8))\r
+\r
+/************ TIM Instances : at least 4 capture/compare channels *************/\r
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
+                                         ((INSTANCE) == TIM2)   || \\r
+                                         ((INSTANCE) == TIM3)   || \\r
+                                         ((INSTANCE) == TIM4)   || \\r
+                                         ((INSTANCE) == TIM5)   || \\r
+                                         ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : at least 5 capture/compare channels *******/\r
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
+                                         ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : at least 6 capture/compare channels *******/\r
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
+                                         ((INSTANCE) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/\r
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \\r
+                                            ((INSTANCE) == TIM8)   || \\r
+                                            ((INSTANCE) == TIM15)  || \\r
+                                            ((INSTANCE) == TIM16)  || \\r
+                                            ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/\r
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\r
+                                            ((INSTANCE) == TIM2)   || \\r
+                                            ((INSTANCE) == TIM3)   || \\r
+                                            ((INSTANCE) == TIM4)   || \\r
+                                            ((INSTANCE) == TIM5)   || \\r
+                                            ((INSTANCE) == TIM6)   || \\r
+                                            ((INSTANCE) == TIM7)   || \\r
+                                            ((INSTANCE) == TIM8)   || \\r
+                                            ((INSTANCE) == TIM15)  || \\r
+                                            ((INSTANCE) == TIM16)  || \\r
+                                            ((INSTANCE) == TIM17))\r
+\r
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/\r
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
+                                            ((INSTANCE) == TIM2)   || \\r
+                                            ((INSTANCE) == TIM3)   || \\r
+                                            ((INSTANCE) == TIM4)   || \\r
+                                            ((INSTANCE) == TIM5)   || \\r
+                                            ((INSTANCE) == TIM8)   || \\r
+                                            ((INSTANCE) == TIM15)  || \\r
+                                            ((INSTANCE) == TIM16)  || \\r
+                                            ((INSTANCE) == TIM17))\r
+\r
+/******************** TIM Instances : DMA burst feature ***********************/\r
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
+                                            ((INSTANCE) == TIM2)   || \\r
+                                            ((INSTANCE) == TIM3)   || \\r
+                                            ((INSTANCE) == TIM4)   || \\r
+                                            ((INSTANCE) == TIM5)   || \\r
+                                            ((INSTANCE) == TIM8)   || \\r
+                                            ((INSTANCE) == TIM15)  || \\r
+                                            ((INSTANCE) == TIM16)  || \\r
+                                            ((INSTANCE) == TIM17))\r
+\r
+/******************* TIM Instances : output(s) available **********************/\r
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\r
+    ((((INSTANCE) == TIM1) &&                  \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_6)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM2) &&                  \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM3) &&                  \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM4) &&                  \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM5) &&                  \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM8) &&                  \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_6)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM15) &&                 \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
+      ((CHANNEL) == TIM_CHANNEL_2)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM16) &&                 \\r
+     (((CHANNEL) == TIM_CHANNEL_1)))           \\r
+     ||                                        \\r
+     (((INSTANCE) == TIM17) &&                 \\r
+      (((CHANNEL) == TIM_CHANNEL_1))))\r
+\r
+/****************** TIM Instances : supporting complementary output(s) ********/\r
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\r
+   ((((INSTANCE) == TIM1) &&                    \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \\r
+      ((CHANNEL) == TIM_CHANNEL_3)))            \\r
+    ||                                          \\r
+    (((INSTANCE) == TIM8) &&                    \\r
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \\r
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \\r
+      ((CHANNEL) == TIM_CHANNEL_3)))            \\r
+    ||                                          \\r
+    (((INSTANCE) == TIM15) &&                   \\r
+     ((CHANNEL) == TIM_CHANNEL_1))              \\r
+    ||                                          \\r
+    (((INSTANCE) == TIM16) &&                   \\r
+     ((CHANNEL) == TIM_CHANNEL_1))              \\r
+    ||                                          \\r
+    (((INSTANCE) == TIM17) &&                   \\r
+     ((CHANNEL) == TIM_CHANNEL_1)))\r
+\r
+/****************** TIM Instances : supporting clock division *****************/\r
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \\r
+                                                    ((INSTANCE) == TIM2)    || \\r
+                                                    ((INSTANCE) == TIM3)    || \\r
+                                                    ((INSTANCE) == TIM4)    || \\r
+                                                    ((INSTANCE) == TIM5)    || \\r
+                                                    ((INSTANCE) == TIM8)    || \\r
+                                                    ((INSTANCE) == TIM15)   || \\r
+                                                    ((INSTANCE) == TIM16)   || \\r
+                                                    ((INSTANCE) == TIM17))\r
+\r
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+                                                        ((INSTANCE) == TIM2) || \\r
+                                                        ((INSTANCE) == TIM3) || \\r
+                                                        ((INSTANCE) == TIM4) || \\r
+                                                        ((INSTANCE) == TIM5) || \\r
+                                                        ((INSTANCE) == TIM8) || \\r
+                                                        ((INSTANCE) == TIM15))\r
+\r
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+                                                        ((INSTANCE) == TIM2) || \\r
+                                                        ((INSTANCE) == TIM3) || \\r
+                                                        ((INSTANCE) == TIM4) || \\r
+                                                        ((INSTANCE) == TIM5) || \\r
+                                                        ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\r
+                                                        ((INSTANCE) == TIM2) || \\r
+                                                        ((INSTANCE) == TIM3) || \\r
+                                                        ((INSTANCE) == TIM4) || \\r
+                                                        ((INSTANCE) == TIM5) || \\r
+                                                        ((INSTANCE) == TIM8) || \\r
+                                                        ((INSTANCE) == TIM15))\r
+\r
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\r
+                                                        ((INSTANCE) == TIM2) || \\r
+                                                        ((INSTANCE) == TIM3) || \\r
+                                                        ((INSTANCE) == TIM4) || \\r
+                                                        ((INSTANCE) == TIM5) || \\r
+                                                        ((INSTANCE) == TIM8) || \\r
+                                                        ((INSTANCE) == TIM15))\r
+\r
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
+                                                     ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting commutation event generation ***/\r
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
+                                                     ((INSTANCE) == TIM8)   || \\r
+                                                     ((INSTANCE) == TIM15)  || \\r
+                                                     ((INSTANCE) == TIM16)  || \\r
+                                                     ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting counting mode selection ********/\r
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\r
+                                                        ((INSTANCE) == TIM2) || \\r
+                                                        ((INSTANCE) == TIM3) || \\r
+                                                        ((INSTANCE) == TIM4) || \\r
+                                                        ((INSTANCE) == TIM5) || \\r
+                                                        ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting encoder interface **************/\r
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\r
+                                                      ((INSTANCE) == TIM2)  || \\r
+                                                      ((INSTANCE) == TIM3)  || \\r
+                                                      ((INSTANCE) == TIM4)  || \\r
+                                                      ((INSTANCE) == TIM5)  || \\r
+                                                      ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting Hall sensor interface **********/\r
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
+                                                         ((INSTANCE) == TIM2)   || \\r
+                                                         ((INSTANCE) == TIM3)   || \\r
+                                                         ((INSTANCE) == TIM4)   || \\r
+                                                         ((INSTANCE) == TIM5)   || \\r
+                                                         ((INSTANCE) == TIM8))\r
+\r
+/**************** TIM Instances : external trigger input available ************/\r
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \\r
+                                            ((INSTANCE) == TIM2)  || \\r
+                                            ((INSTANCE) == TIM3)  || \\r
+                                            ((INSTANCE) == TIM4)  || \\r
+                                            ((INSTANCE) == TIM5)  || \\r
+                                            ((INSTANCE) == TIM8))\r
+\r
+/************* TIM Instances : supporting ETR source selection ***************/\r
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\r
+                                             ((INSTANCE) == TIM2)  || \\r
+                                             ((INSTANCE) == TIM3)  || \\r
+                                             ((INSTANCE) == TIM8))\r
+\r
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/\r
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\r
+                                            ((INSTANCE) == TIM2)  || \\r
+                                            ((INSTANCE) == TIM3)  || \\r
+                                            ((INSTANCE) == TIM4)  || \\r
+                                            ((INSTANCE) == TIM5)  || \\r
+                                            ((INSTANCE) == TIM6)  || \\r
+                                            ((INSTANCE) == TIM7)  || \\r
+                                            ((INSTANCE) == TIM8)  || \\r
+                                            ((INSTANCE) == TIM15))\r
+\r
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\r
+                                            ((INSTANCE) == TIM2)  || \\r
+                                            ((INSTANCE) == TIM3)  || \\r
+                                            ((INSTANCE) == TIM4)  || \\r
+                                            ((INSTANCE) == TIM5)  || \\r
+                                            ((INSTANCE) == TIM8)  || \\r
+                                            ((INSTANCE) == TIM15))\r
+\r
+/****************** TIM Instances : supporting OCxREF clear *******************/\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\r
+                                                       ((INSTANCE) == TIM2) || \\r
+                                                       ((INSTANCE) == TIM3) || \\r
+                                                       ((INSTANCE) == TIM4) || \\r
+                                                       ((INSTANCE) == TIM5) || \\r
+                                                       ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : remapping capability **********************/\r
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\r
+                                            ((INSTANCE) == TIM2)  || \\r
+                                            ((INSTANCE) == TIM3)  || \\r
+                                            ((INSTANCE) == TIM8)  || \\r
+                                            ((INSTANCE) == TIM15) || \\r
+                                            ((INSTANCE) == TIM16) || \\r
+                                            ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting repetition counter *************/\r
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\r
+                                                       ((INSTANCE) == TIM8)  || \\r
+                                                       ((INSTANCE) == TIM15) || \\r
+                                                       ((INSTANCE) == TIM16) || \\r
+                                                       ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting synchronization ****************/\r
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)\r
+\r
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\r
+                                            ((INSTANCE) == TIM8))\r
+\r
+/******************* TIM Instances : Timer input XOR function *****************/\r
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\r
+                                            ((INSTANCE) == TIM2)   || \\r
+                                            ((INSTANCE) == TIM3)   || \\r
+                                            ((INSTANCE) == TIM4)   || \\r
+                                            ((INSTANCE) == TIM5)   || \\r
+                                            ((INSTANCE) == TIM8)   || \\r
+                                            ((INSTANCE) == TIM15))\r
+\r
+/****************** TIM Instances : Advanced timer instances *******************/\r
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\r
+                                                  ((INSTANCE) == TIM8))\r
+\r
+/****************************** TSC Instances *********************************/\r
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)\r
+\r
+/******************** USART Instances : Synchronous mode **********************/\r
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+                                     ((INSTANCE) == USART2) || \\r
+                                     ((INSTANCE) == USART3))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+                                    ((INSTANCE) == USART2) || \\r
+                                    ((INSTANCE) == USART3) || \\r
+                                    ((INSTANCE) == UART4)  || \\r
+                                    ((INSTANCE) == UART5))\r
+\r
+/****************** UART Instances : Auto Baud Rate detection ****************/\r
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+                                                            ((INSTANCE) == USART2) || \\r
+                                                            ((INSTANCE) == USART3) || \\r
+                                                            ((INSTANCE) == UART4)  || \\r
+                                                            ((INSTANCE) == UART5))\r
+\r
+/****************** UART Instances : Driver Enable *****************/\r
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \\r
+                                                      ((INSTANCE) == USART2) || \\r
+                                                      ((INSTANCE) == USART3) || \\r
+                                                      ((INSTANCE) == UART4)  || \\r
+                                                      ((INSTANCE) == UART5)  || \\r
+                                                      ((INSTANCE) == LPUART1))\r
+\r
+/******************** UART Instances : Half-Duplex mode **********************/\r
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\r
+                                                 ((INSTANCE) == USART2) || \\r
+                                                 ((INSTANCE) == USART3) || \\r
+                                                 ((INSTANCE) == UART4)  || \\r
+                                                 ((INSTANCE) == UART5)  || \\r
+                                                 ((INSTANCE) == LPUART1))\r
+\r
+/****************** UART Instances : Hardware Flow control ********************/\r
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+                                           ((INSTANCE) == USART2) || \\r
+                                           ((INSTANCE) == USART3) || \\r
+                                           ((INSTANCE) == UART4)  || \\r
+                                           ((INSTANCE) == UART5)  || \\r
+                                           ((INSTANCE) == LPUART1))\r
+\r
+/******************** UART Instances : LIN mode **********************/\r
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\r
+                                          ((INSTANCE) == USART2) || \\r
+                                          ((INSTANCE) == USART3) || \\r
+                                          ((INSTANCE) == UART4)  || \\r
+                                          ((INSTANCE) == UART5))\r
+\r
+/******************** UART Instances : Wake-up from Stop mode **********************/\r
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\r
+                                                      ((INSTANCE) == USART2) || \\r
+                                                      ((INSTANCE) == USART3) || \\r
+                                                      ((INSTANCE) == UART4)  || \\r
+                                                      ((INSTANCE) == UART5)  || \\r
+                                                      ((INSTANCE) == LPUART1))\r
+\r
+/*********************** UART Instances : IRDA mode ***************************/\r
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+                                    ((INSTANCE) == USART2) || \\r
+                                    ((INSTANCE) == USART3) || \\r
+                                    ((INSTANCE) == UART4)  || \\r
+                                    ((INSTANCE) == UART5))\r
+\r
+/********************* USART Instances : Smard card mode ***********************/\r
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+                                         ((INSTANCE) == USART2) || \\r
+                                         ((INSTANCE) == USART3))\r
+\r
+/******************** LPUART Instance *****************************************/\r
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)\r
+\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/******************************************************************************/\r
+/*  For a painless codes migration between the STM32L4xx device product       */\r
+/*  lines, the aliases defined below are put in place to overcome the         */\r
+/*  differences in the interrupt handlers and IRQn definitions.               */\r
+/*  No need to update developed interrupt code when moving across             */\r
+/*  product lines within the same STM32L4 Family                              */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+#define TIM6_IRQn                      TIM6_DAC_IRQn\r
+#define ADC1_IRQn                      ADC1_2_IRQn\r
+#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn\r
+#define TIM8_IRQn                      TIM8_UP_IRQn\r
+#define HASH_RNG_IRQn                  RNG_IRQn\r
+#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn\r
+#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn\r
+#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn\r
+#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn\r
+\r
+/* Aliases for __IRQHandler */\r
+#define TIM6_IRQHandler                TIM6_DAC_IRQHandler\r
+#define ADC1_IRQHandler                ADC1_2_IRQHandler\r
+#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler\r
+#define TIM8_IRQHandler                TIM8_UP_IRQHandler\r
+#define HASH_RNG_IRQHandler            RNG_IRQHandler\r
+#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler\r
+#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler\r
+#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler\r
+#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32L475xx_H */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+  /**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h
new file mode 100644 (file)
index 0000000..0bf6c83
--- /dev/null
@@ -0,0 +1,248 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx.h\r
+  * @author  MCD Application Team\r
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.\r
+  *\r
+  *          The file is the unique include file that the application programmer\r
+  *          is using in the C source code, usually in main.c. This file contains:\r
+  *           - Configuration section that allows to select:\r
+  *              - The STM32L4xx device used in the target application\r
+  *              - To use or not the peripheral\92s drivers in application code(i.e.\r
+  *                code will be based on direct access to peripheral\92s registers\r
+  *                rather than drivers API), this option is controlled by\r
+  *                "#define USE_HAL_DRIVER"\r
+  *\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l4xx\r
+  * @{\r
+  */\r
+\r
+#ifndef __STM32L4xx_H\r
+#define __STM32L4xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Library_configuration_section\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief STM32 Family\r
+  */\r
+#if !defined (STM32L4)\r
+#define STM32L4\r
+#endif /* STM32L4 */\r
+\r
+/* Uncomment the line below according to the target STM32L4 device used in your\r
+   application\r
+  */\r
+\r
+#if !defined (STM32L412xx) && !defined (STM32L422xx) && \\r
+    !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \\r
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \\r
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \\r
+    !defined (STM32L496xx) && !defined (STM32L4A6xx) && \\r
+    !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)\r
+  /* #define STM32L412xx */   /*!< STM32L412xx Devices */\r
+  /* #define STM32L422xx */   /*!< STM32L422xx Devices */\r
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */\r
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */\r
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */\r
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */\r
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */\r
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */\r
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */\r
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */\r
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */\r
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */\r
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */\r
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */\r
+  /* #define STM32L486xx */   /*!< STM32L486xx Devices */\r
+  /* #define STM32L496xx */   /*!< STM32L496xx Devices */\r
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */\r
+  /* #define STM32L4R5xx */   /*!< STM32L4R5xx Devices */\r
+  /* #define STM32L4R7xx */   /*!< STM32L4R7xx Devices */\r
+  /* #define STM32L4R9xx */   /*!< STM32L4R9xx Devices */\r
+  /* #define STM32L4S5xx */   /*!< STM32L4S5xx Devices */\r
+  /* #define STM32L4S7xx */   /*!< STM32L4S7xx Devices */\r
+  /* #define STM32L4S9xx */   /*!< STM32L4S9xx Devices */\r
+#endif\r
+\r
+/*  Tip: To avoid modifying this file each time you need to switch between these\r
+        devices, you can define the device in your toolchain compiler preprocessor.\r
+  */\r
+#if !defined  (USE_HAL_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+   In this case, these drivers will not be included and the application code will\r
+   be based on direct access to peripherals registers\r
+   */\r
+  /*#define USE_HAL_DRIVER */\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+/**\r
+  * @brief CMSIS Device version number\r
+  */\r
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */\r
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */\r
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */\r
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */\r
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\\r
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\\r
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\\r
+                                       |(__STM32L4_CMSIS_VERSION_RC))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Device_Included\r
+  * @{\r
+  */\r
+\r
+#if defined(STM32L412xx)\r
+  #include "stm32l412xx.h"\r
+#elif defined(STM32L422xx)\r
+  #include "stm32l422xx.h"\r
+#elif defined(STM32L431xx)\r
+  #include "stm32l431xx.h"\r
+#elif defined(STM32L432xx)\r
+  #include "stm32l432xx.h"\r
+#elif defined(STM32L433xx)\r
+  #include "stm32l433xx.h"\r
+#elif defined(STM32L442xx)\r
+  #include "stm32l442xx.h"\r
+#elif defined(STM32L443xx)\r
+  #include "stm32l443xx.h"\r
+#elif defined(STM32L451xx)\r
+  #include "stm32l451xx.h"\r
+#elif defined(STM32L452xx)\r
+  #include "stm32l452xx.h"\r
+#elif defined(STM32L462xx)\r
+  #include "stm32l462xx.h"\r
+#elif defined(STM32L471xx)\r
+  #include "stm32l471xx.h"\r
+#elif defined(STM32L475xx)\r
+  #include "stm32l475xx.h"\r
+#elif defined(STM32L476xx)\r
+  #include "stm32l476xx.h"\r
+#elif defined(STM32L485xx)\r
+  #include "stm32l485xx.h"\r
+#elif defined(STM32L486xx)\r
+  #include "stm32l486xx.h"\r
+#elif defined(STM32L496xx)\r
+  #include "stm32l496xx.h"\r
+#elif defined(STM32L4A6xx)\r
+  #include "stm32l4a6xx.h"\r
+#elif defined(STM32L4R5xx)\r
+  #include "stm32l4r5xx.h"\r
+#elif defined(STM32L4R7xx)\r
+  #include "stm32l4r7xx.h"\r
+#elif defined(STM32L4R9xx)\r
+  #include "stm32l4r9xx.h"\r
+#elif defined(STM32L4S5xx)\r
+  #include "stm32l4s5xx.h"\r
+#elif defined(STM32L4S7xx)\r
+  #include "stm32l4s7xx.h"\r
+#elif defined(STM32L4S9xx)\r
+  #include "stm32l4s9xx.h"\r
+#else\r
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Exported_types\r
+  * @{\r
+  */\r
+typedef enum\r
+{\r
+  RESET = 0,\r
+  SET = !RESET\r
+} FlagStatus, ITStatus;\r
+\r
+typedef enum\r
+{\r
+  DISABLE = 0,\r
+  ENABLE = !DISABLE\r
+} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum\r
+{\r
+  SUCCESS = 0,\r
+  ERROR = !SUCCESS\r
+} ErrorStatus;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @addtogroup Exported_macros\r
+  * @{\r
+  */\r
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG)        ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\r
+\r
+#define READ_REG(REG)         ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined (USE_HAL_DRIVER)\r
+ #include "stm32l4xx_hal.h"\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32L4xx_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h
new file mode 100644 (file)
index 0000000..9eceb00
--- /dev/null
@@ -0,0 +1,107 @@
+/**\r
+  ******************************************************************************\r
+  * @file    system_stm32l4xx.h\r
+  * @author  MCD Application Team\r
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l4xx_system\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Define to prevent recursive inclusion\r
+  */\r
+#ifndef __SYSTEM_STM32L4XX_H\r
+#define __SYSTEM_STM32L4XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** @addtogroup STM32L4xx_System_Includes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @addtogroup STM32L4xx_System_Exported_Variables\r
+  * @{\r
+  */\r
+  /* The SystemCoreClock variable is updated in three ways:\r
+      1) by calling CMSIS function SystemCoreClockUpdate()\r
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
+         Note: If you use this function to configure the system clock; then there\r
+               is no need to call the 2 first functions listed above, since SystemCoreClock\r
+               variable is updated automatically.\r
+  */\r
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */\r
+\r
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\r
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\r
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L4xx_System_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32L4XX_H */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_armcc.h
new file mode 100644 (file)
index 0000000..7d751fb
--- /dev/null
@@ -0,0 +1,865 @@
+/**************************************************************************//**\r
+ * @file     cmsis_armcc.h\r
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file\r
+ * @version  V5.0.4\r
+ * @date     10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* CMSIS compiler control architecture macros */\r
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \\r
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )\r
+  #define __ARM_ARCH_6M__           1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))\r
+  #define __ARM_ARCH_7M__           1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\r
+  #define __ARM_ARCH_7EM__          1\r
+#endif\r
+\r
+  /* __ARM_ARCH_8M_BASE__  not applicable */\r
+  /* __ARM_ARCH_8M_MAIN__  not applicable */\r
+\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef   __ASM\r
+  #define __ASM                                  __asm\r
+#endif\r
+#ifndef   __INLINE\r
+  #define __INLINE                               __inline\r
+#endif\r
+#ifndef   __STATIC_INLINE\r
+  #define __STATIC_INLINE                        static __inline\r
+#endif\r
+#ifndef   __STATIC_FORCEINLINE                 \r
+  #define __STATIC_FORCEINLINE                   static __forceinline\r
+#endif           \r
+#ifndef   __NO_RETURN\r
+  #define __NO_RETURN                            __declspec(noreturn)\r
+#endif\r
+#ifndef   __USED\r
+  #define __USED                                 __attribute__((used))\r
+#endif\r
+#ifndef   __WEAK\r
+  #define __WEAK                                 __attribute__((weak))\r
+#endif\r
+#ifndef   __PACKED\r
+  #define __PACKED                               __attribute__((packed))\r
+#endif\r
+#ifndef   __PACKED_STRUCT\r
+  #define __PACKED_STRUCT                        __packed struct\r
+#endif\r
+#ifndef   __PACKED_UNION\r
+  #define __PACKED_UNION                         __packed union\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32        /* deprecated */\r
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT16_WRITE\r
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT16_READ\r
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32_WRITE\r
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32_READ\r
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))\r
+#endif\r
+#ifndef   __ALIGNED\r
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
+#endif\r
+#ifndef   __RESTRICT\r
+  #define __RESTRICT                             __restrict\r
+#endif\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+/** \ingroup  CMSIS_Core_FunctionInterface\r
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Enable IRQ Interrupts\r
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq();     */\r
+\r
+\r
+/**\r
+  \brief   Disable IRQ Interrupts\r
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq();    */\r
+\r
+/**\r
+  \brief   Get Control Register\r
+  \details Returns the content of the Control Register.\r
+  \return               Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Control Register\r
+  \details Writes the given value to the Control Register.\r
+  \param [in]    control  Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get IPSR Register\r
+  \details Returns the content of the IPSR Register.\r
+  \return               IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+  register uint32_t __regIPSR          __ASM("ipsr");\r
+  return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get APSR Register\r
+  \details Returns the content of the APSR Register.\r
+  \return               APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+  register uint32_t __regAPSR          __ASM("apsr");\r
+  return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get xPSR Register\r
+  \details Returns the content of the xPSR Register.\r
+  \return               xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+  register uint32_t __regXPSR          __ASM("xpsr");\r
+  return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Process Stack Pointer\r
+  \details Returns the current value of the Process Stack Pointer (PSP).\r
+  \return               PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+  register uint32_t __regProcessStackPointer  __ASM("psp");\r
+  return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Process Stack Pointer\r
+  \details Assigns the given value to the Process Stack Pointer (PSP).\r
+  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  register uint32_t __regProcessStackPointer  __ASM("psp");\r
+  __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Main Stack Pointer\r
+  \details Returns the current value of the Main Stack Pointer (MSP).\r
+  \return               MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+  register uint32_t __regMainStackPointer     __ASM("msp");\r
+  return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Main Stack Pointer\r
+  \details Assigns the given value to the Main Stack Pointer (MSP).\r
+  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  register uint32_t __regMainStackPointer     __ASM("msp");\r
+  __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Mask\r
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+  \return               Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Priority Mask\r
+  \details Assigns the given value to the Priority Mask Register.\r
+  \param [in]    priMask  Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
+\r
+/**\r
+  \brief   Enable FIQ\r
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq                __enable_fiq\r
+\r
+\r
+/**\r
+  \brief   Disable FIQ\r
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq               __disable_fiq\r
+\r
+\r
+/**\r
+  \brief   Get Base Priority\r
+  \details Returns the current value of the Base Priority register.\r
+  \return               Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority\r
+  \details Assigns the given value to the Base Priority register.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority with condition\r
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+           or the new value increases the BASEPRI priority level.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+  register uint32_t __regBasePriMax      __ASM("basepri_max");\r
+  __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Fault Mask\r
+  \details Returns the current value of the Fault Mask register.\r
+  \return               Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Fault Mask\r
+  \details Assigns the given value to the Fault Mask register.\r
+  \param [in]    faultMask  Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  __regFaultMask = (faultMask & (uint32_t)1U);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
+\r
+\r
+/**\r
+  \brief   Get FPSCR\r
+  \details Returns the current value of the Floating Point Status/Control register.\r
+  \return               Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
+  register uint32_t __regfpscr         __ASM("fpscr");\r
+  return(__regfpscr);\r
+#else\r
+   return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set FPSCR\r
+  \details Assigns the given value to the Floating Point Status/Control register.\r
+  \param [in]    fpscr  Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
+  register uint32_t __regfpscr         __ASM("fpscr");\r
+  __regfpscr = (fpscr);\r
+#else\r
+  (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+  Access to dedicated instructions\r
+  @{\r
+*/\r
+\r
+/**\r
+  \brief   No Operation\r
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP                             __nop\r
+\r
+\r
+/**\r
+  \brief   Wait For Interrupt\r
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI                             __wfi\r
+\r
+\r
+/**\r
+  \brief   Wait For Event\r
+  \details Wait For Event is a hint instruction that permits the processor to enter\r
+           a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE                             __wfe\r
+\r
+\r
+/**\r
+  \brief   Send Event\r
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV                             __sev\r
+\r
+\r
+/**\r
+  \brief   Instruction Synchronization Barrier\r
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+           so that all instructions following the ISB are fetched from cache or memory,\r
+           after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+                   __schedule_barrier();\\r
+                   __isb(0xF);\\r
+                   __schedule_barrier();\\r
+                } while (0U)\r
+\r
+/**\r
+  \brief   Data Synchronization Barrier\r
+  \details Acts as a special kind of Data Memory Barrier.\r
+           It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+                   __schedule_barrier();\\r
+                   __dsb(0xF);\\r
+                   __schedule_barrier();\\r
+                } while (0U)\r
+\r
+/**\r
+  \brief   Data Memory Barrier\r
+  \details Ensures the apparent order of the explicit memory operations before\r
+           and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+                   __schedule_barrier();\\r
+                   __dmb(0xF);\\r
+                   __schedule_barrier();\\r
+                } while (0U)\r
+\r
+                  \r
+/**\r
+  \brief   Reverse byte order (32 bit)\r
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#define __REV                             __rev\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (16 bit)\r
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+  rev16 r0, r0\r
+  bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (16 bit)\r
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\r
+{\r
+  revsh r0, r0\r
+  bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Rotate Right in unsigned value (32 bit)\r
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+  \param [in]    op1  Value to rotate\r
+  \param [in]    op2  Number of Bits to rotate\r
+  \return               Rotated value\r
+ */\r
+#define __ROR                             __ror\r
+\r
+\r
+/**\r
+  \brief   Breakpoint\r
+  \details Causes the processor to enter Debug state.\r
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+  \param [in]    value  is ignored by the processor.\r
+                 If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value)                       __breakpoint(value)\r
+\r
+\r
+/**\r
+  \brief   Reverse bit order of value\r
+  \details Reverses the bit order of the given value.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
+  #define __RBIT                          __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+  uint32_t result;\r
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r
+  for (value >>= 1U; value != 0U; value >>= 1U)\r
+  {\r
+    result <<= 1U;\r
+    result |= value & 1U;\r
+    s--;\r
+  }\r
+  result <<= s;                        /* shift when v's highest bits are zero */\r
+  return result;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Count leading zeros\r
+  \details Counts the number of leading zeros of a data value.\r
+  \param [in]  value  Value to count the leading zeros\r
+  \return             number of leading zeros in value\r
+ */\r
+#define __CLZ                             __clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
+\r
+/**\r
+  \brief   LDR Exclusive (8 bit)\r
+  \details Executes a exclusive LDR instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\r
+#else\r
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (16 bit)\r
+  \details Executes a exclusive LDR instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\r
+#else\r
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (32 bit)\r
+  \details Executes a exclusive LDR instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\r
+#else\r
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (8 bit)\r
+  \details Executes a exclusive STR instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\r
+#else\r
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (16 bit)\r
+  \details Executes a exclusive STR instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\r
+#else\r
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (32 bit)\r
+  \details Executes a exclusive STR instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\r
+#else\r
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Remove the exclusive lock\r
+  \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX                           __clrex\r
+\r
+\r
+/**\r
+  \brief   Signed Saturate\r
+  \details Saturates a signed value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (1..32)\r
+  \return             Saturated value\r
+ */\r
+#define __SSAT                            __ssat\r
+\r
+\r
+/**\r
+  \brief   Unsigned Saturate\r
+  \details Saturates an unsigned value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (0..31)\r
+  \return             Saturated value\r
+ */\r
+#define __USAT                            __usat\r
+\r
+\r
+/**\r
+  \brief   Rotate Right with Extend (32 bit)\r
+  \details Moves each bit of a bitstring right by one bit.\r
+           The carry input is shifted in at the left end of the bitstring.\r
+  \param [in]    value  Value to rotate\r
+  \return               Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+  rrx r0, r0\r
+  bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+#define __STRBT(value, ptr)               __strt(value, ptr)\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+#define __STRHT(value, ptr)               __strt(value, ptr)\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+#define __STRT(value, ptr)                __strt(value, ptr)\r
+\r
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
+\r
+/**\r
+  \brief   Signed Saturate\r
+  \details Saturates a signed value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (1..32)\r
+  \return             Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+  if ((sat >= 1U) && (sat <= 32U))\r
+  {\r
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+    const int32_t min = -1 - max ;\r
+    if (val > max)\r
+    {\r
+      return max;\r
+    }\r
+    else if (val < min)\r
+    {\r
+      return min;\r
+    }\r
+  }\r
+  return val;\r
+}\r
+\r
+/**\r
+  \brief   Unsigned Saturate\r
+  \details Saturates an unsigned value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (0..31)\r
+  \return             Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+  if (sat <= 31U)\r
+  {\r
+    const uint32_t max = ((1U << sat) - 1U);\r
+    if (val > (int32_t)max)\r
+    {\r
+      return max;\r
+    }\r
+    else if (val < 0)\r
+    {\r
+      return 0U;\r
+    }\r
+  }\r
+  return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+  Access to dedicated SIMD instructions\r
+  @{\r
+*/\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
+\r
+#define __SADD8                           __sadd8\r
+#define __QADD8                           __qadd8\r
+#define __SHADD8                          __shadd8\r
+#define __UADD8                           __uadd8\r
+#define __UQADD8                          __uqadd8\r
+#define __UHADD8                          __uhadd8\r
+#define __SSUB8                           __ssub8\r
+#define __QSUB8                           __qsub8\r
+#define __SHSUB8                          __shsub8\r
+#define __USUB8                           __usub8\r
+#define __UQSUB8                          __uqsub8\r
+#define __UHSUB8                          __uhsub8\r
+#define __SADD16                          __sadd16\r
+#define __QADD16                          __qadd16\r
+#define __SHADD16                         __shadd16\r
+#define __UADD16                          __uadd16\r
+#define __UQADD16                         __uqadd16\r
+#define __UHADD16                         __uhadd16\r
+#define __SSUB16                          __ssub16\r
+#define __QSUB16                          __qsub16\r
+#define __SHSUB16                         __shsub16\r
+#define __USUB16                          __usub16\r
+#define __UQSUB16                         __uqsub16\r
+#define __UHSUB16                         __uhsub16\r
+#define __SASX                            __sasx\r
+#define __QASX                            __qasx\r
+#define __SHASX                           __shasx\r
+#define __UASX                            __uasx\r
+#define __UQASX                           __uqasx\r
+#define __UHASX                           __uhasx\r
+#define __SSAX                            __ssax\r
+#define __QSAX                            __qsax\r
+#define __SHSAX                           __shsax\r
+#define __USAX                            __usax\r
+#define __UQSAX                           __uqsax\r
+#define __UHSAX                           __uhsax\r
+#define __USAD8                           __usad8\r
+#define __USADA8                          __usada8\r
+#define __SSAT16                          __ssat16\r
+#define __USAT16                          __usat16\r
+#define __UXTB16                          __uxtb16\r
+#define __UXTAB16                         __uxtab16\r
+#define __SXTB16                          __sxtb16\r
+#define __SXTAB16                         __sxtab16\r
+#define __SMUAD                           __smuad\r
+#define __SMUADX                          __smuadx\r
+#define __SMLAD                           __smlad\r
+#define __SMLADX                          __smladx\r
+#define __SMLALD                          __smlald\r
+#define __SMLALDX                         __smlaldx\r
+#define __SMUSD                           __smusd\r
+#define __SMUSDX                          __smusdx\r
+#define __SMLSD                           __smlsd\r
+#define __SMLSDX                          __smlsdx\r
+#define __SMLSLD                          __smlsld\r
+#define __SMLSLDX                         __smlsldx\r
+#define __SEL                             __sel\r
+#define __QADD                            __qadd\r
+#define __QSUB                            __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\r
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\r
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_armclang.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_armclang.h
new file mode 100644 (file)
index 0000000..d8031b0
--- /dev/null
@@ -0,0 +1,1869 @@
+/**************************************************************************//**\r
+ * @file     cmsis_armclang.h\r
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\r
+ * @version  V5.0.4\r
+ * @date     10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\r
+\r
+#ifndef __CMSIS_ARMCLANG_H\r
+#define __CMSIS_ARMCLANG_H\r
+\r
+#pragma clang system_header   /* treat file as system include file */\r
+\r
+#ifndef __ARM_COMPAT_H\r
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef   __ASM\r
+  #define __ASM                                  __asm\r
+#endif\r
+#ifndef   __INLINE\r
+  #define __INLINE                               __inline\r
+#endif\r
+#ifndef   __STATIC_INLINE\r
+  #define __STATIC_INLINE                        static __inline\r
+#endif\r
+#ifndef   __STATIC_FORCEINLINE                 \r
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\r
+#endif                                           \r
+#ifndef   __NO_RETURN\r
+  #define __NO_RETURN                            __attribute__((__noreturn__))\r
+#endif\r
+#ifndef   __USED\r
+  #define __USED                                 __attribute__((used))\r
+#endif\r
+#ifndef   __WEAK\r
+  #define __WEAK                                 __attribute__((weak))\r
+#endif\r
+#ifndef   __PACKED\r
+  #define __PACKED                               __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef   __PACKED_STRUCT\r
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef   __PACKED_UNION\r
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32        /* deprecated */\r
+  #pragma clang diagnostic push\r
+  #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\r
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+  #pragma clang diagnostic pop\r
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef   __UNALIGNED_UINT16_WRITE\r
+  #pragma clang diagnostic push\r
+  #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\r
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+  #pragma clang diagnostic pop\r
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT16_READ\r
+  #pragma clang diagnostic push\r
+  #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\r
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+  #pragma clang diagnostic pop\r
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32_WRITE\r
+  #pragma clang diagnostic push\r
+  #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\r
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+  #pragma clang diagnostic pop\r
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32_READ\r
+  #pragma clang diagnostic push\r
+  #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\r
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+  #pragma clang diagnostic pop\r
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef   __ALIGNED\r
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
+#endif\r
+#ifndef   __RESTRICT\r
+  #define __RESTRICT                             __restrict\r
+#endif\r
+\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+/** \ingroup  CMSIS_Core_FunctionInterface\r
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Enable IRQ Interrupts\r
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq();  see arm_compat.h */\r
+\r
+\r
+/**\r
+  \brief   Disable IRQ Interrupts\r
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq();  see arm_compat.h */\r
+\r
+\r
+/**\r
+  \brief   Get Control Register\r
+  \details Returns the content of the Control Register.\r
+  \return               Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Control Register (non-secure)\r
+  \details Returns the content of the non-secure Control Register when in secure mode.\r
+  \return               non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Control Register\r
+  \details Writes the given value to the Control Register.\r
+  \param [in]    control  Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Control Register (non-secure)\r
+  \details Writes the given value to the non-secure Control Register when in secure state.\r
+  \param [in]    control  Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get IPSR Register\r
+  \details Returns the content of the IPSR Register.\r
+  \return               IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get APSR Register\r
+  \details Returns the content of the APSR Register.\r
+  \return               APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get xPSR Register\r
+  \details Returns the content of the xPSR Register.\r
+  \return               xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Process Stack Pointer\r
+  \details Returns the current value of the Process Stack Pointer (PSP).\r
+  \return               PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Process Stack Pointer (non-secure)\r
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+  \return               PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Process Stack Pointer\r
+  \details Assigns the given value to the Process Stack Pointer (PSP).\r
+  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Process Stack Pointer (non-secure)\r
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get Main Stack Pointer\r
+  \details Returns the current value of the Main Stack Pointer (MSP).\r
+  \return               MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Main Stack Pointer (non-secure)\r
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+  \return               MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Main Stack Pointer\r
+  \details Assigns the given value to the Main Stack Pointer (MSP).\r
+  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Main Stack Pointer (non-secure)\r
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Stack Pointer (non-secure)\r
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+  \return               SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Stack Pointer (non-secure)\r
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+  \param [in]    topOfStack  Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get Priority Mask\r
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+  \return               Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Priority Mask (non-secure)\r
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+  \return               Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Priority Mask\r
+  \details Assigns the given value to the Priority Mask Register.\r
+  \param [in]    priMask  Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Priority Mask (non-secure)\r
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+  \param [in]    priMask  Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
+/**\r
+  \brief   Enable FIQ\r
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */\r
+\r
+\r
+/**\r
+  \brief   Disable FIQ\r
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */\r
+\r
+\r
+/**\r
+  \brief   Get Base Priority\r
+  \details Returns the current value of the Base Priority register.\r
+  \return               Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Base Priority (non-secure)\r
+  \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+  \return               Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority\r
+  \details Assigns the given value to the Base Priority register.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Base Priority (non-secure)\r
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority with condition\r
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+           or the new value increases the BASEPRI priority level.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Fault Mask\r
+  \details Returns the current value of the Fault Mask register.\r
+  \return               Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Fault Mask (non-secure)\r
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+  \return               Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Fault Mask\r
+  \details Assigns the given value to the Fault Mask register.\r
+  \param [in]    faultMask  Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Fault Mask (non-secure)\r
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+  \param [in]    faultMask  Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+\r
+/**\r
+  \brief   Get Process Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always in non-secure\r
+  mode.\r
+  \r
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+  \return               PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Process Stack Pointer Limit (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always in non-secure\r
+  mode.\r
+\r
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+  \return               PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Process Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+  mode.\r
+  \r
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  (void)ProcStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
+/**\r
+  \brief   Set Process Stack Pointer (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+  mode.\r
+\r
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  (void)ProcStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get Main Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always.\r
+\r
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+  \return               MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
+/**\r
+  \brief   Get Main Stack Pointer Limit (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always.\r
+\r
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+  \return               MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Main Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  (void)MainStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
+/**\r
+  \brief   Set Main Stack Pointer Limit (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  (void)MainStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
+\r
+/**\r
+  \brief   Get FPSCR\r
+  \details Returns the current value of the Floating Point Status/Control register.\r
+  \return               Floating Point Status/Control register value\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\r
+#else\r
+#define __get_FPSCR()      ((uint32_t)0U)\r
+#endif\r
+\r
+/**\r
+  \brief   Set FPSCR\r
+  \details Assigns the given value to the Floating Point Status/Control register.\r
+  \param [in]    fpscr  Floating Point Status/Control value to set\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
+#define __set_FPSCR      __builtin_arm_set_fpscr\r
+#else\r
+#define __set_FPSCR(x)      ((void)(x))\r
+#endif\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+  Access to dedicated instructions\r
+  @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+  \brief   No Operation\r
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP          __builtin_arm_nop\r
+\r
+/**\r
+  \brief   Wait For Interrupt\r
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI          __builtin_arm_wfi\r
+\r
+\r
+/**\r
+  \brief   Wait For Event\r
+  \details Wait For Event is a hint instruction that permits the processor to enter\r
+           a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE          __builtin_arm_wfe\r
+\r
+\r
+/**\r
+  \brief   Send Event\r
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV          __builtin_arm_sev\r
+\r
+\r
+/**\r
+  \brief   Instruction Synchronization Barrier\r
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+           so that all instructions following the ISB are fetched from cache or memory,\r
+           after the instruction has been completed.\r
+ */\r
+#define __ISB()        __builtin_arm_isb(0xF);\r
+\r
+/**\r
+  \brief   Data Synchronization Barrier\r
+  \details Acts as a special kind of Data Memory Barrier.\r
+           It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB()        __builtin_arm_dsb(0xF);\r
+\r
+\r
+/**\r
+  \brief   Data Memory Barrier\r
+  \details Ensures the apparent order of the explicit memory operations before\r
+           and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB()        __builtin_arm_dmb(0xF);\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (32 bit)\r
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#define __REV(value)   __builtin_bswap32(value)\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (16 bit)\r
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#define __REV16(value) __ROR(__REV(value), 16)\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (16 bit)\r
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)\r
+\r
+\r
+/**\r
+  \brief   Rotate Right in unsigned value (32 bit)\r
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+  \param [in]    op1  Value to rotate\r
+  \param [in]    op2  Number of Bits to rotate\r
+  \return               Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+  op2 %= 32U;\r
+  if (op2 == 0U)\r
+  {\r
+    return op1;\r
+  }\r
+  return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Breakpoint\r
+  \details Causes the processor to enter Debug state.\r
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+  \param [in]    value  is ignored by the processor.\r
+                 If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+  \brief   Reverse bit order of value\r
+  \details Reverses the bit order of the given value.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+#define __RBIT            __builtin_arm_rbit\r
+\r
+/**\r
+  \brief   Count leading zeros\r
+  \details Counts the number of leading zeros of a data value.\r
+  \param [in]  value  Value to count the leading zeros\r
+  \return             number of leading zeros in value\r
+ */\r
+#define __CLZ             (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+/**\r
+  \brief   LDR Exclusive (8 bit)\r
+  \details Executes a exclusive LDR instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (16 bit)\r
+  \details Executes a exclusive LDR instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (32 bit)\r
+  \details Executes a exclusive LDR instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (8 bit)\r
+  \details Executes a exclusive STR instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#define __STREXB        (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (16 bit)\r
+  \details Executes a exclusive STR instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#define __STREXH        (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (32 bit)\r
+  \details Executes a exclusive STR instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#define __STREXW        (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+  \brief   Remove the exclusive lock\r
+  \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX             __builtin_arm_clrex\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
+\r
+/**\r
+  \brief   Signed Saturate\r
+  \details Saturates a signed value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (1..32)\r
+  \return             Saturated value\r
+ */\r
+#define __SSAT             __builtin_arm_ssat\r
+\r
+\r
+/**\r
+  \brief   Unsigned Saturate\r
+  \details Saturates an unsigned value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (0..31)\r
+  \return             Saturated value\r
+ */\r
+#define __USAT             __builtin_arm_usat\r
+\r
+\r
+/**\r
+  \brief   Rotate Right with Extend (32 bit)\r
+  \details Moves each bit of a bitstring right by one bit.\r
+           The carry input is shifted in at the left end of the bitstring.\r
+  \param [in]    value  Value to rotate\r
+  \return               Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+  return ((uint8_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+  return ((uint16_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
+\r
+/**\r
+  \brief   Signed Saturate\r
+  \details Saturates a signed value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (1..32)\r
+  \return             Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+  if ((sat >= 1U) && (sat <= 32U))\r
+  {\r
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+    const int32_t min = -1 - max ;\r
+    if (val > max)\r
+    {\r
+      return max;\r
+    }\r
+    else if (val < min)\r
+    {\r
+      return min;\r
+    }\r
+  }\r
+  return val;\r
+}\r
+\r
+/**\r
+  \brief   Unsigned Saturate\r
+  \details Saturates an unsigned value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (0..31)\r
+  \return             Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+  if (sat <= 31U)\r
+  {\r
+    const uint32_t max = ((1U << sat) - 1U);\r
+    if (val > (int32_t)max)\r
+    {\r
+      return max;\r
+    }\r
+    else if (val < 0)\r
+    {\r
+      return 0U;\r
+    }\r
+  }\r
+  return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+/**\r
+  \brief   Load-Acquire (8 bit)\r
+  \details Executes a LDAB instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+  return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire (16 bit)\r
+  \details Executes a LDAH instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+  return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire (32 bit)\r
+  \details Executes a LDA instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release (8 bit)\r
+  \details Executes a STLB instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release (16 bit)\r
+  \details Executes a STLH instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release (32 bit)\r
+  \details Executes a STL instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire Exclusive (8 bit)\r
+  \details Executes a LDAB exclusive instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire Exclusive (16 bit)\r
+  \details Executes a LDAH exclusive instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire Exclusive (32 bit)\r
+  \details Executes a LDA exclusive instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+  \brief   Store-Release Exclusive (8 bit)\r
+  \details Executes a STLB exclusive instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+  \brief   Store-Release Exclusive (16 bit)\r
+  \details Executes a STLH exclusive instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+  \brief   Store-Release Exclusive (32 bit)\r
+  \details Executes a STL exclusive instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+  Access to dedicated SIMD instructions\r
+  @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({                          \\r
+  int32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r
+{\r
+  int32_t result;\r
+\r
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r
+{\r
+  int32_t result;\r
+\r
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
+  __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+  if (ARG3 == 0) \\r
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \\r
+  else \\r
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
+  __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\r
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\r
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+  int32_t result;\r
+\r
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCLANG_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_compiler.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_compiler.h
new file mode 100644 (file)
index 0000000..79a2cac
--- /dev/null
@@ -0,0 +1,266 @@
+/**************************************************************************//**\r
+ * @file     cmsis_compiler.h\r
+ * @brief    CMSIS compiler generic header file\r
+ * @version  V5.0.4\r
+ * @date     10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_COMPILER_H\r
+#define __CMSIS_COMPILER_H\r
+\r
+#include <stdint.h>\r
+\r
+/*\r
+ * Arm Compiler 4/5\r
+ */\r
+#if   defined ( __CC_ARM )\r
+  #include "cmsis_armcc.h"\r
+\r
+\r
+/*\r
+ * Arm Compiler 6 (armclang)\r
+ */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #include "cmsis_armclang.h"\r
+\r
+\r
+/*\r
+ * GNU Compiler\r
+ */\r
+#elif defined ( __GNUC__ )\r
+  #include "cmsis_gcc.h"\r
+\r
+\r
+/*\r
+ * IAR Compiler\r
+ */\r
+#elif defined ( __ICCARM__ )\r
+  #include <cmsis_iccarm.h>\r
+\r
+\r
+/*\r
+ * TI Arm Compiler\r
+ */\r
+#elif defined ( __TI_ARM__ )\r
+  #include <cmsis_ccs.h>\r
+\r
+  #ifndef   __ASM\r
+    #define __ASM                                  __asm\r
+  #endif\r
+  #ifndef   __INLINE\r
+    #define __INLINE                               inline\r
+  #endif\r
+  #ifndef   __STATIC_INLINE\r
+    #define __STATIC_INLINE                        static inline\r
+  #endif\r
+  #ifndef   __STATIC_FORCEINLINE\r
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\r
+  #endif\r
+  #ifndef   __NO_RETURN\r
+    #define __NO_RETURN                            __attribute__((noreturn))\r
+  #endif\r
+  #ifndef   __USED\r
+    #define __USED                                 __attribute__((used))\r
+  #endif\r
+  #ifndef   __WEAK\r
+    #define __WEAK                                 __attribute__((weak))\r
+  #endif\r
+  #ifndef   __PACKED\r
+    #define __PACKED                               __attribute__((packed))\r
+  #endif\r
+  #ifndef   __PACKED_STRUCT\r
+    #define __PACKED_STRUCT                        struct __attribute__((packed))\r
+  #endif\r
+  #ifndef   __PACKED_UNION\r
+    #define __PACKED_UNION                         union __attribute__((packed))\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */\r
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT16_WRITE\r
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT16_READ\r
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32_WRITE\r
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32_READ\r
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+  #endif\r
+  #ifndef   __ALIGNED\r
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
+  #endif\r
+  #ifndef   __RESTRICT\r
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+    #define __RESTRICT\r
+  #endif\r
+\r
+\r
+/*\r
+ * TASKING Compiler\r
+ */\r
+#elif defined ( __TASKING__ )\r
+  /*\r
+   * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+   * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+   * Including the CMSIS ones.\r
+   */\r
+\r
+  #ifndef   __ASM\r
+    #define __ASM                                  __asm\r
+  #endif\r
+  #ifndef   __INLINE\r
+    #define __INLINE                               inline\r
+  #endif\r
+  #ifndef   __STATIC_INLINE\r
+    #define __STATIC_INLINE                        static inline\r
+  #endif\r
+  #ifndef   __STATIC_FORCEINLINE\r
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\r
+  #endif\r
+  #ifndef   __NO_RETURN\r
+    #define __NO_RETURN                            __attribute__((noreturn))\r
+  #endif\r
+  #ifndef   __USED\r
+    #define __USED                                 __attribute__((used))\r
+  #endif\r
+  #ifndef   __WEAK\r
+    #define __WEAK                                 __attribute__((weak))\r
+  #endif\r
+  #ifndef   __PACKED\r
+    #define __PACKED                               __packed__\r
+  #endif\r
+  #ifndef   __PACKED_STRUCT\r
+    #define __PACKED_STRUCT                        struct __packed__\r
+  #endif\r
+  #ifndef   __PACKED_UNION\r
+    #define __PACKED_UNION                         union __packed__\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */\r
+    struct __packed__ T_UINT32 { uint32_t v; };\r
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT16_WRITE\r
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT16_READ\r
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32_WRITE\r
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32_READ\r
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+  #endif\r
+  #ifndef   __ALIGNED\r
+    #define __ALIGNED(x)              __align(x)\r
+  #endif\r
+  #ifndef   __RESTRICT\r
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+    #define __RESTRICT\r
+  #endif\r
+\r
+\r
+/*\r
+ * COSMIC Compiler\r
+ */\r
+#elif defined ( __CSMC__ )\r
+   #include <cmsis_csm.h>\r
+\r
+ #ifndef   __ASM\r
+    #define __ASM                                  _asm\r
+  #endif\r
+  #ifndef   __INLINE\r
+    #define __INLINE                               inline\r
+  #endif\r
+  #ifndef   __STATIC_INLINE\r
+    #define __STATIC_INLINE                        static inline\r
+  #endif\r
+  #ifndef   __STATIC_FORCEINLINE\r
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\r
+  #endif\r
+  #ifndef   __NO_RETURN\r
+    // NO RETURN is automatically detected hence no warning here\r
+    #define __NO_RETURN\r
+  #endif\r
+  #ifndef   __USED\r
+    #warning No compiler specific solution for __USED. __USED is ignored.\r
+    #define __USED\r
+  #endif\r
+  #ifndef   __WEAK\r
+    #define __WEAK                                 __weak\r
+  #endif\r
+  #ifndef   __PACKED\r
+    #define __PACKED                               @packed\r
+  #endif\r
+  #ifndef   __PACKED_STRUCT\r
+    #define __PACKED_STRUCT                        @packed struct\r
+  #endif\r
+  #ifndef   __PACKED_UNION\r
+    #define __PACKED_UNION                         @packed union\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */\r
+    @packed struct T_UINT32 { uint32_t v; };\r
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT16_WRITE\r
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT16_READ\r
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32_WRITE\r
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+  #endif\r
+  #ifndef   __UNALIGNED_UINT32_READ\r
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+  #endif\r
+  #ifndef   __ALIGNED\r
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
+    #define __ALIGNED(x)\r
+  #endif\r
+  #ifndef   __RESTRICT\r
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+    #define __RESTRICT\r
+  #endif\r
+\r
+\r
+#else\r
+  #error Unknown compiler.\r
+#endif\r
+\r
+\r
+#endif /* __CMSIS_COMPILER_H */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_gcc.h
new file mode 100644 (file)
index 0000000..1bd41a4
--- /dev/null
@@ -0,0 +1,2085 @@
+/**************************************************************************//**\r
+ * @file     cmsis_gcc.h\r
+ * @brief    CMSIS compiler GCC header file\r
+ * @version  V5.0.4\r
+ * @date     09. April 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+/* Fallback for __has_builtin */\r
+#ifndef __has_builtin\r
+  #define __has_builtin(x) (0)\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef   __ASM\r
+  #define __ASM                                  __asm\r
+#endif\r
+#ifndef   __INLINE\r
+  #define __INLINE                               inline\r
+#endif\r
+#ifndef   __STATIC_INLINE\r
+  #define __STATIC_INLINE                        static inline\r
+#endif\r
+#ifndef   __STATIC_FORCEINLINE                 \r
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\r
+#endif                                           \r
+#ifndef   __NO_RETURN\r
+  #define __NO_RETURN                            __attribute__((__noreturn__))\r
+#endif\r
+#ifndef   __USED\r
+  #define __USED                                 __attribute__((used))\r
+#endif\r
+#ifndef   __WEAK\r
+  #define __WEAK                                 __attribute__((weak))\r
+#endif\r
+#ifndef   __PACKED\r
+  #define __PACKED                               __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef   __PACKED_STRUCT\r
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef   __PACKED_UNION\r
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32        /* deprecated */\r
+  #pragma GCC diagnostic push\r
+  #pragma GCC diagnostic ignored "-Wpacked"\r
+  #pragma GCC diagnostic ignored "-Wattributes"\r
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+  #pragma GCC diagnostic pop\r
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef   __UNALIGNED_UINT16_WRITE\r
+  #pragma GCC diagnostic push\r
+  #pragma GCC diagnostic ignored "-Wpacked"\r
+  #pragma GCC diagnostic ignored "-Wattributes"\r
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+  #pragma GCC diagnostic pop\r
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT16_READ\r
+  #pragma GCC diagnostic push\r
+  #pragma GCC diagnostic ignored "-Wpacked"\r
+  #pragma GCC diagnostic ignored "-Wattributes"\r
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+  #pragma GCC diagnostic pop\r
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32_WRITE\r
+  #pragma GCC diagnostic push\r
+  #pragma GCC diagnostic ignored "-Wpacked"\r
+  #pragma GCC diagnostic ignored "-Wattributes"\r
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+  #pragma GCC diagnostic pop\r
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef   __UNALIGNED_UINT32_READ\r
+  #pragma GCC diagnostic push\r
+  #pragma GCC diagnostic ignored "-Wpacked"\r
+  #pragma GCC diagnostic ignored "-Wattributes"\r
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+  #pragma GCC diagnostic pop\r
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef   __ALIGNED\r
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
+#endif\r
+#ifndef   __RESTRICT\r
+  #define __RESTRICT                             __restrict\r
+#endif\r
+\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+/** \ingroup  CMSIS_Core_FunctionInterface\r
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Enable IRQ Interrupts\r
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_irq(void)\r
+{\r
+  __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable IRQ Interrupts\r
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_irq(void)\r
+{\r
+  __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Control Register\r
+  \details Returns the content of the Control Register.\r
+  \return               Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Control Register (non-secure)\r
+  \details Returns the content of the non-secure Control Register when in secure mode.\r
+  \return               non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Control Register\r
+  \details Writes the given value to the Control Register.\r
+  \param [in]    control  Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Control Register (non-secure)\r
+  \details Writes the given value to the non-secure Control Register when in secure state.\r
+  \param [in]    control  Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get IPSR Register\r
+  \details Returns the content of the IPSR Register.\r
+  \return               IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get APSR Register\r
+  \details Returns the content of the APSR Register.\r
+  \return               APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get xPSR Register\r
+  \details Returns the content of the xPSR Register.\r
+  \return               xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Process Stack Pointer\r
+  \details Returns the current value of the Process Stack Pointer (PSP).\r
+  \return               PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Process Stack Pointer (non-secure)\r
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+  \return               PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Process Stack Pointer\r
+  \details Assigns the given value to the Process Stack Pointer (PSP).\r
+  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Process Stack Pointer (non-secure)\r
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get Main Stack Pointer\r
+  \details Returns the current value of the Main Stack Pointer (MSP).\r
+  \return               MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Main Stack Pointer (non-secure)\r
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+  \return               MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Main Stack Pointer\r
+  \details Assigns the given value to the Main Stack Pointer (MSP).\r
+  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Main Stack Pointer (non-secure)\r
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Stack Pointer (non-secure)\r
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+  \return               SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Stack Pointer (non-secure)\r
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+  \param [in]    topOfStack  Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get Priority Mask\r
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+  \return               Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Priority Mask (non-secure)\r
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+  \return               Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Priority Mask\r
+  \details Assigns the given value to the Priority Mask Register.\r
+  \param [in]    priMask  Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Priority Mask (non-secure)\r
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+  \param [in]    priMask  Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
+/**\r
+  \brief   Enable FIQ\r
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_fault_irq(void)\r
+{\r
+  __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable FIQ\r
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_fault_irq(void)\r
+{\r
+  __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Base Priority\r
+  \details Returns the current value of the Base Priority register.\r
+  \return               Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Base Priority (non-secure)\r
+  \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+  \return               Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority\r
+  \details Assigns the given value to the Base Priority register.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Base Priority (non-secure)\r
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority with condition\r
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+           or the new value increases the BASEPRI priority level.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Fault Mask\r
+  \details Returns the current value of the Fault Mask register.\r
+  \return               Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Fault Mask (non-secure)\r
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+  \return               Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+  return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Fault Mask\r
+  \details Assigns the given value to the Fault Mask register.\r
+  \param [in]    faultMask  Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Set Fault Mask (non-secure)\r
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+  \param [in]    faultMask  Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+\r
+/**\r
+  \brief   Get Process Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always in non-secure\r
+  mode.\r
+  \r
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+  \return               PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+  \brief   Get Process Stack Pointer Limit (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always.\r
+\r
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+  \return               PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Process Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+  mode.\r
+  \r
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  (void)ProcStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
+/**\r
+  \brief   Set Process Stack Pointer (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+  (void)ProcStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Get Main Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always in non-secure\r
+  mode.\r
+\r
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+  \return               MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
+/**\r
+  \brief   Get Main Stack Pointer Limit (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence zero is returned always.\r
+\r
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+  \return               MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  return 0U;\r
+#else\r
+  uint32_t result;\r
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+  return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Main Stack Pointer Limit\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+  mode.\r
+\r
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  (void)MainStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
+/**\r
+  \brief   Set Main Stack Pointer Limit (non-secure)\r
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+  Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+  (void)MainStackPtrLimit;\r
+#else\r
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
+\r
+\r
+/**\r
+  \brief   Get FPSCR\r
+  \details Returns the current value of the Floating Point Status/Control register.\r
+  \return               Floating Point Status/Control register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
+#if __has_builtin(__builtin_arm_get_fpscr) \r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+  return __builtin_arm_get_fpscr();\r
+#else\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+  return(result);\r
+#endif\r
+#else\r
+  return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set FPSCR\r
+  \details Assigns the given value to the Floating Point Status/Control register.\r
+  \param [in]    fpscr  Floating Point Status/Control value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
+#if __has_builtin(__builtin_arm_set_fpscr)\r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+  __builtin_arm_set_fpscr(fpscr);\r
+#else\r
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");\r
+#endif\r
+#else\r
+  (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+  Access to dedicated instructions\r
+  @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+  \brief   No Operation\r
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP()                             __ASM volatile ("nop")\r
+\r
+/**\r
+  \brief   Wait For Interrupt\r
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI()                             __ASM volatile ("wfi")\r
+\r
+\r
+/**\r
+  \brief   Wait For Event\r
+  \details Wait For Event is a hint instruction that permits the processor to enter\r
+           a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE()                             __ASM volatile ("wfe")\r
+\r
+\r
+/**\r
+  \brief   Send Event\r
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV()                             __ASM volatile ("sev")\r
+\r
+\r
+/**\r
+  \brief   Instruction Synchronization Barrier\r
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+           so that all instructions following the ISB are fetched from cache or memory,\r
+           after the instruction has been completed.\r
+ */\r
+__STATIC_FORCEINLINE void __ISB(void)\r
+{\r
+  __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Data Synchronization Barrier\r
+  \details Acts as a special kind of Data Memory Barrier.\r
+           It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__STATIC_FORCEINLINE void __DSB(void)\r
+{\r
+  __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Data Memory Barrier\r
+  \details Ensures the apparent order of the explicit memory operations before\r
+           and after the instruction, without ensuring their completion.\r
+ */\r
+__STATIC_FORCEINLINE void __DMB(void)\r
+{\r
+  __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (32 bit)\r
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+  return __builtin_bswap32(value);\r
+#else\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (16 bit)\r
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return result;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (16 bit)\r
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+  return (int16_t)__builtin_bswap16(value);\r
+#else\r
+  int16_t result;\r
+\r
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Rotate Right in unsigned value (32 bit)\r
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+  \param [in]    op1  Value to rotate\r
+  \param [in]    op2  Number of Bits to rotate\r
+  \return               Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+  op2 %= 32U;\r
+  if (op2 == 0U)\r
+  {\r
+    return op1;\r
+  }\r
+  return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Breakpoint\r
+  \details Causes the processor to enter Debug state.\r
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+  \param [in]    value  is ignored by the processor.\r
+                 If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+  \brief   Reverse bit order of value\r
+  \details Reverses the bit order of the given value.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+  uint32_t result;\r
+\r
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r
+  for (value >>= 1U; value != 0U; value >>= 1U)\r
+  {\r
+    result <<= 1U;\r
+    result |= value & 1U;\r
+    s--;\r
+  }\r
+  result <<= s;                        /* shift when v's highest bits are zero */\r
+#endif\r
+  return result;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Count leading zeros\r
+  \details Counts the number of leading zeros of a data value.\r
+  \param [in]  value  Value to count the leading zeros\r
+  \return             number of leading zeros in value\r
+ */\r
+#define __CLZ             (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+/**\r
+  \brief   LDR Exclusive (8 bit)\r
+  \details Executes a exclusive LDR instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+   return ((uint8_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (16 bit)\r
+  \details Executes a exclusive LDR instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+   return ((uint16_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (32 bit)\r
+  \details Executes a exclusive LDR instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (8 bit)\r
+  \details Executes a exclusive STR instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (16 bit)\r
+  \details Executes a exclusive STR instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (32 bit)\r
+  \details Executes a exclusive STR instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Remove the exclusive lock\r
+  \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__STATIC_FORCEINLINE void __CLREX(void)\r
+{\r
+  __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
+/**\r
+  \brief   Signed Saturate\r
+  \details Saturates a signed value.\r
+  \param [in]  ARG1  Value to be saturated\r
+  \param [in]  ARG2  Bit position to saturate to (1..32)\r
+  \return             Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+__extension__ \\r
+({                          \\r
+  int32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+\r
+/**\r
+  \brief   Unsigned Saturate\r
+  \details Saturates an unsigned value.\r
+  \param [in]  ARG1  Value to be saturated\r
+  \param [in]  ARG2  Bit position to saturate to (0..31)\r
+  \return             Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+ __extension__ \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+\r
+/**\r
+  \brief   Rotate Right with Extend (32 bit)\r
+  \details Moves each bit of a bitstring right by one bit.\r
+           The carry input is shifted in at the left end of the bitstring.\r
+  \param [in]    value  Value to rotate\r
+  \return               Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+   return ((uint8_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+   return ((uint16_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
+\r
+/**\r
+  \brief   Signed Saturate\r
+  \details Saturates a signed value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (1..32)\r
+  \return             Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+  if ((sat >= 1U) && (sat <= 32U))\r
+  {\r
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+    const int32_t min = -1 - max ;\r
+    if (val > max)\r
+    {\r
+      return max;\r
+    }\r
+    else if (val < min)\r
+    {\r
+      return min;\r
+    }\r
+  }\r
+  return val;\r
+}\r
+\r
+/**\r
+  \brief   Unsigned Saturate\r
+  \details Saturates an unsigned value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (0..31)\r
+  \return             Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+  if (sat <= 31U)\r
+  {\r
+    const uint32_t max = ((1U << sat) - 1U);\r
+    if (val > (int32_t)max)\r
+    {\r
+      return max;\r
+    }\r
+    else if (val < 0)\r
+    {\r
+      return 0U;\r
+    }\r
+  }\r
+  return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+/**\r
+  \brief   Load-Acquire (8 bit)\r
+  \details Executes a LDAB instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+   return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire (16 bit)\r
+  \details Executes a LDAH instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+   return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire (32 bit)\r
+  \details Executes a LDA instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release (8 bit)\r
+  \details Executes a STLB instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release (16 bit)\r
+  \details Executes a STLH instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release (32 bit)\r
+  \details Executes a STL instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire Exclusive (8 bit)\r
+  \details Executes a LDAB exclusive instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+   return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire Exclusive (16 bit)\r
+  \details Executes a LDAH exclusive instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+   return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Load-Acquire Exclusive (32 bit)\r
+  \details Executes a LDA exclusive instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release Exclusive (8 bit)\r
+  \details Executes a STLB exclusive instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release Exclusive (16 bit)\r
+  \details Executes a STLH exclusive instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Store-Release Exclusive (32 bit)\r
+  \details Executes a STL exclusive instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+   return(result);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+  Access to dedicated SIMD instructions\r
+  @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({                          \\r
+  int32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r
+{\r
+  int32_t result;\r
+\r
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r
+{\r
+  int32_t result;\r
+\r
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
+  __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+  if (ARG3 == 0) \\r
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \\r
+  else \\r
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
+  __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\r
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\r
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#pragma GCC diagnostic pop\r
+\r
+#endif /* __CMSIS_GCC_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h
new file mode 100644 (file)
index 0000000..3c90a2c
--- /dev/null
@@ -0,0 +1,935 @@
+/**************************************************************************//**\r
+ * @file     cmsis_iccarm.h\r
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
+ * @version  V5.0.7\r
+ * @date     19. June 2018\r
+ ******************************************************************************/\r
+\r
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2017-2018 IAR Systems\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License")\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+//     http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef __CMSIS_ICCARM_H__\r
+#define __CMSIS_ICCARM_H__\r
+\r
+#ifndef __ICCARM__\r
+  #error This file should only be compiled by ICCARM\r
+#endif\r
+\r
+#pragma system_include\r
+\r
+#define __IAR_FT _Pragma("inline=forced") __intrinsic\r
+\r
+#if (__VER__ >= 8000000)\r
+  #define __ICCARM_V8 1\r
+#else\r
+  #define __ICCARM_V8 0\r
+#endif\r
+\r
+#ifndef __ALIGNED\r
+  #if __ICCARM_V8\r
+    #define __ALIGNED(x) __attribute__((aligned(x)))\r
+  #elif (__VER__ >= 7080000)\r
+    /* Needs IAR language extensions */\r
+    #define __ALIGNED(x) __attribute__((aligned(x)))\r
+  #else\r
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\r
+    #define __ALIGNED(x)\r
+  #endif\r
+#endif\r
+\r
+\r
+/* Define compiler macros for CPU architecture, used in CMSIS 5.\r
+ */\r
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\r
+/* Macros already defined */\r
+#else\r
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\r
+    #define __ARM_ARCH_8M_MAIN__ 1\r
+  #elif defined(__ARM8M_BASELINE__)\r
+    #define __ARM_ARCH_8M_BASE__ 1\r
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\r
+    #if __ARM_ARCH == 6\r
+      #define __ARM_ARCH_6M__ 1\r
+    #elif __ARM_ARCH == 7\r
+      #if __ARM_FEATURE_DSP\r
+        #define __ARM_ARCH_7EM__ 1\r
+      #else\r
+        #define __ARM_ARCH_7M__ 1\r
+      #endif\r
+    #endif /* __ARM_ARCH */\r
+  #endif /* __ARM_ARCH_PROFILE == 'M' */\r
+#endif\r
+\r
+/* Alternativ core deduction for older ICCARM's */\r
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\r
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\r
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\r
+    #define __ARM_ARCH_6M__ 1\r
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\r
+    #define __ARM_ARCH_7M__ 1\r
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\r
+    #define __ARM_ARCH_7EM__  1\r
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\r
+    #define __ARM_ARCH_8M_BASE__ 1\r
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\r
+    #define __ARM_ARCH_8M_MAIN__ 1\r
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\r
+    #define __ARM_ARCH_8M_MAIN__ 1\r
+  #else\r
+    #error "Unknown target."\r
+  #endif\r
+#endif\r
+\r
+\r
+\r
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\r
+  #define __IAR_M0_FAMILY  1\r
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\r
+  #define __IAR_M0_FAMILY  1\r
+#else\r
+  #define __IAR_M0_FAMILY  0\r
+#endif\r
+\r
+\r
+#ifndef __ASM\r
+  #define __ASM __asm\r
+#endif\r
+\r
+#ifndef __INLINE\r
+  #define __INLINE inline\r
+#endif\r
+\r
+#ifndef   __NO_RETURN\r
+  #if __ICCARM_V8\r
+    #define __NO_RETURN __attribute__((__noreturn__))\r
+  #else\r
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")\r
+  #endif\r
+#endif\r
+\r
+#ifndef   __PACKED\r
+  #if __ICCARM_V8\r
+    #define __PACKED __attribute__((packed, aligned(1)))\r
+  #else\r
+    /* Needs IAR language extensions */\r
+    #define __PACKED __packed\r
+  #endif\r
+#endif\r
+\r
+#ifndef   __PACKED_STRUCT\r
+  #if __ICCARM_V8\r
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+  #else\r
+    /* Needs IAR language extensions */\r
+    #define __PACKED_STRUCT __packed struct\r
+  #endif\r
+#endif\r
+\r
+#ifndef   __PACKED_UNION\r
+  #if __ICCARM_V8\r
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+  #else\r
+    /* Needs IAR language extensions */\r
+    #define __PACKED_UNION __packed union\r
+  #endif\r
+#endif\r
+\r
+#ifndef   __RESTRICT\r
+  #define __RESTRICT            __restrict\r
+#endif\r
+\r
+#ifndef   __STATIC_INLINE\r
+  #define __STATIC_INLINE       static inline\r
+#endif\r
+\r
+#ifndef   __FORCEINLINE\r
+  #define __FORCEINLINE         _Pragma("inline=forced")\r
+#endif\r
+\r
+#ifndef   __STATIC_FORCEINLINE\r
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT16_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\r
+{\r
+  return *(__packed uint16_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\r
+#endif\r
+\r
+\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\r
+{\r
+  *(__packed uint16_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\r
+{\r
+  return *(__packed uint32_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\r
+{\r
+  *(__packed uint32_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32   /* deprecated */\r
+#pragma language=save\r
+#pragma language=extended\r
+__packed struct  __iar_u32 { uint32_t v; };\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\r
+#endif\r
+\r
+#ifndef   __USED\r
+  #if __ICCARM_V8\r
+    #define __USED __attribute__((used))\r
+  #else\r
+    #define __USED _Pragma("__root")\r
+  #endif\r
+#endif\r
+\r
+#ifndef   __WEAK\r
+  #if __ICCARM_V8\r
+    #define __WEAK __attribute__((weak))\r
+  #else\r
+    #define __WEAK _Pragma("__weak")\r
+  #endif\r
+#endif\r
+\r
+\r
+#ifndef __ICCARM_INTRINSICS_VERSION__\r
+  #define __ICCARM_INTRINSICS_VERSION__  0\r
+#endif\r
+\r
+#if __ICCARM_INTRINSICS_VERSION__ == 2\r
+\r
+  #if defined(__CLZ)\r
+    #undef __CLZ\r
+  #endif\r
+  #if defined(__REVSH)\r
+    #undef __REVSH\r
+  #endif\r
+  #if defined(__RBIT)\r
+    #undef __RBIT\r
+  #endif\r
+  #if defined(__SSAT)\r
+    #undef __SSAT\r
+  #endif\r
+  #if defined(__USAT)\r
+    #undef __USAT\r
+  #endif\r
+\r
+  #include "iccarm_builtin.h"\r
+\r
+  #define __disable_fault_irq __iar_builtin_disable_fiq\r
+  #define __disable_irq       __iar_builtin_disable_interrupt\r
+  #define __enable_fault_irq  __iar_builtin_enable_fiq\r
+  #define __enable_irq        __iar_builtin_enable_interrupt\r
+  #define __arm_rsr           __iar_builtin_rsr\r
+  #define __arm_wsr           __iar_builtin_wsr\r
+\r
+\r
+  #define __get_APSR()                (__arm_rsr("APSR"))\r
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))\r
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))\r
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))\r
+\r
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))\r
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))\r
+  #else\r
+    #define __get_FPSCR()             ( 0 )\r
+    #define __set_FPSCR(VALUE)        ((void)VALUE)\r
+  #endif\r
+\r
+  #define __get_IPSR()                (__arm_rsr("IPSR"))\r
+  #define __get_MSP()                 (__arm_rsr("MSP"))\r
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+    #define __get_MSPLIM()            (0U)\r
+  #else\r
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))\r
+  #endif\r
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))\r
+  #define __get_PSP()                 (__arm_rsr("PSP"))\r
+\r
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+    #define __get_PSPLIM()            (0U)\r
+  #else\r
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))\r
+  #endif\r
+\r
+  #define __get_xPSR()                (__arm_rsr("xPSR"))\r
+\r
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))\r
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))\r
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))\r
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))\r
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))\r
+\r
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))\r
+  #else\r
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))\r
+  #endif\r
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))\r
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))\r
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))\r
+  #else\r
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))\r
+  #endif\r
+\r
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))\r
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))\r
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))\r
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))\r
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))\r
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))\r
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))\r
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))\r
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))\r
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))\r
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))\r
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))\r
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))\r
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
+\r
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+    #define __TZ_get_PSPLIM_NS()      (0U)\r
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\r
+  #else\r
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))\r
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+  #endif\r
+\r
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))\r
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))\r
+\r
+  #define __NOP     __iar_builtin_no_operation\r
+\r
+  #define __CLZ     __iar_builtin_CLZ\r
+  #define __CLREX   __iar_builtin_CLREX\r
+\r
+  #define __DMB     __iar_builtin_DMB\r
+  #define __DSB     __iar_builtin_DSB\r
+  #define __ISB     __iar_builtin_ISB\r
+\r
+  #define __LDREXB  __iar_builtin_LDREXB\r
+  #define __LDREXH  __iar_builtin_LDREXH\r
+  #define __LDREXW  __iar_builtin_LDREX\r
+\r
+  #define __RBIT    __iar_builtin_RBIT\r
+  #define __REV     __iar_builtin_REV\r
+  #define __REV16   __iar_builtin_REV16\r
+\r
+  __IAR_FT int16_t __REVSH(int16_t val)\r
+  {\r
+    return (int16_t) __iar_builtin_REVSH(val);\r
+  }\r
+\r
+  #define __ROR     __iar_builtin_ROR\r
+  #define __RRX     __iar_builtin_RRX\r
+\r
+  #define __SEV     __iar_builtin_SEV\r
+\r
+  #if !__IAR_M0_FAMILY\r
+    #define __SSAT    __iar_builtin_SSAT\r
+  #endif\r
+\r
+  #define __STREXB  __iar_builtin_STREXB\r
+  #define __STREXH  __iar_builtin_STREXH\r
+  #define __STREXW  __iar_builtin_STREX\r
+\r
+  #if !__IAR_M0_FAMILY\r
+    #define __USAT    __iar_builtin_USAT\r
+  #endif\r
+\r
+  #define __WFE     __iar_builtin_WFE\r
+  #define __WFI     __iar_builtin_WFI\r
+\r
+  #if __ARM_MEDIA__\r
+    #define __SADD8   __iar_builtin_SADD8\r
+    #define __QADD8   __iar_builtin_QADD8\r
+    #define __SHADD8  __iar_builtin_SHADD8\r
+    #define __UADD8   __iar_builtin_UADD8\r
+    #define __UQADD8  __iar_builtin_UQADD8\r
+    #define __UHADD8  __iar_builtin_UHADD8\r
+    #define __SSUB8   __iar_builtin_SSUB8\r
+    #define __QSUB8   __iar_builtin_QSUB8\r
+    #define __SHSUB8  __iar_builtin_SHSUB8\r
+    #define __USUB8   __iar_builtin_USUB8\r
+    #define __UQSUB8  __iar_builtin_UQSUB8\r
+    #define __UHSUB8  __iar_builtin_UHSUB8\r
+    #define __SADD16  __iar_builtin_SADD16\r
+    #define __QADD16  __iar_builtin_QADD16\r
+    #define __SHADD16 __iar_builtin_SHADD16\r
+    #define __UADD16  __iar_builtin_UADD16\r
+    #define __UQADD16 __iar_builtin_UQADD16\r
+    #define __UHADD16 __iar_builtin_UHADD16\r
+    #define __SSUB16  __iar_builtin_SSUB16\r
+    #define __QSUB16  __iar_builtin_QSUB16\r
+    #define __SHSUB16 __iar_builtin_SHSUB16\r
+    #define __USUB16  __iar_builtin_USUB16\r
+    #define __UQSUB16 __iar_builtin_UQSUB16\r
+    #define __UHSUB16 __iar_builtin_UHSUB16\r
+    #define __SASX    __iar_builtin_SASX\r
+    #define __QASX    __iar_builtin_QASX\r
+    #define __SHASX   __iar_builtin_SHASX\r
+    #define __UASX    __iar_builtin_UASX\r
+    #define __UQASX   __iar_builtin_UQASX\r
+    #define __UHASX   __iar_builtin_UHASX\r
+    #define __SSAX    __iar_builtin_SSAX\r
+    #define __QSAX    __iar_builtin_QSAX\r
+    #define __SHSAX   __iar_builtin_SHSAX\r
+    #define __USAX    __iar_builtin_USAX\r
+    #define __UQSAX   __iar_builtin_UQSAX\r
+    #define __UHSAX   __iar_builtin_UHSAX\r
+    #define __USAD8   __iar_builtin_USAD8\r
+    #define __USADA8  __iar_builtin_USADA8\r
+    #define __SSAT16  __iar_builtin_SSAT16\r
+    #define __USAT16  __iar_builtin_USAT16\r
+    #define __UXTB16  __iar_builtin_UXTB16\r
+    #define __UXTAB16 __iar_builtin_UXTAB16\r
+    #define __SXTB16  __iar_builtin_SXTB16\r
+    #define __SXTAB16 __iar_builtin_SXTAB16\r
+    #define __SMUAD   __iar_builtin_SMUAD\r
+    #define __SMUADX  __iar_builtin_SMUADX\r
+    #define __SMMLA   __iar_builtin_SMMLA\r
+    #define __SMLAD   __iar_builtin_SMLAD\r
+    #define __SMLADX  __iar_builtin_SMLADX\r
+    #define __SMLALD  __iar_builtin_SMLALD\r
+    #define __SMLALDX __iar_builtin_SMLALDX\r
+    #define __SMUSD   __iar_builtin_SMUSD\r
+    #define __SMUSDX  __iar_builtin_SMUSDX\r
+    #define __SMLSD   __iar_builtin_SMLSD\r
+    #define __SMLSDX  __iar_builtin_SMLSDX\r
+    #define __SMLSLD  __iar_builtin_SMLSLD\r
+    #define __SMLSLDX __iar_builtin_SMLSLDX\r
+    #define __SEL     __iar_builtin_SEL\r
+    #define __QADD    __iar_builtin_QADD\r
+    #define __QSUB    __iar_builtin_QSUB\r
+    #define __PKHBT   __iar_builtin_PKHBT\r
+    #define __PKHTB   __iar_builtin_PKHTB\r
+  #endif\r
+\r
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+  #if __IAR_M0_FAMILY\r
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+    #define __CLZ  __cmsis_iar_clz_not_active\r
+    #define __SSAT __cmsis_iar_ssat_not_active\r
+    #define __USAT __cmsis_iar_usat_not_active\r
+    #define __RBIT __cmsis_iar_rbit_not_active\r
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active\r
+  #endif\r
+\r
+\r
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\r
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\r
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\r
+  #endif\r
+\r
+  #ifdef __INTRINSICS_INCLUDED\r
+  #error intrinsics.h is already included previously!\r
+  #endif\r
+\r
+  #include <intrinsics.h>\r
+\r
+  #if __IAR_M0_FAMILY\r
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+    #undef __CLZ\r
+    #undef __SSAT\r
+    #undef __USAT\r
+    #undef __RBIT\r
+    #undef __get_APSR\r
+\r
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)\r
+    {\r
+      if (data == 0U) { return 32U; }\r
+\r
+      uint32_t count = 0U;\r
+      uint32_t mask = 0x80000000U;\r
+\r
+      while ((data & mask) == 0U)\r
+      {\r
+        count += 1U;\r
+        mask = mask >> 1U;\r
+      }\r
+      return count;\r
+    }\r
+\r
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)\r
+    {\r
+      uint8_t sc = 31U;\r
+      uint32_t r = v;\r
+      for (v >>= 1U; v; v >>= 1U)\r
+      {\r
+        r <<= 1U;\r
+        r |= v & 1U;\r
+        sc--;\r
+      }\r
+      return (r << sc);\r
+    }\r
+\r
+    __STATIC_INLINE  uint32_t __get_APSR(void)\r
+    {\r
+      uint32_t res;\r
+      __asm("MRS      %0,APSR" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+  #endif\r
+\r
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\r
+    #undef __get_FPSCR\r
+    #undef __set_FPSCR\r
+    #define __get_FPSCR()       (0)\r
+    #define __set_FPSCR(VALUE)  ((void)VALUE)\r
+  #endif\r
+\r
+  #pragma diag_suppress=Pe940\r
+  #pragma diag_suppress=Pe177\r
+\r
+  #define __enable_irq    __enable_interrupt\r
+  #define __disable_irq   __disable_interrupt\r
+  #define __NOP           __no_operation\r
+\r
+  #define __get_xPSR      __get_PSR\r
+\r
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\r
+\r
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\r
+    {\r
+      return __LDREX((unsigned long *)ptr);\r
+    }\r
+\r
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\r
+    {\r
+      return __STREX(value, (unsigned long *)ptr);\r
+    }\r
+  #endif\r
+\r
+\r
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+  #if (__CORTEX_M >= 0x03)\r
+\r
+    __IAR_FT uint32_t __RRX(uint32_t value)\r
+    {\r
+      uint32_t result;\r
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");\r
+      return(result);\r
+    }\r
+\r
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));\r
+    }\r
+\r
+\r
+    #define __enable_fault_irq  __enable_fiq\r
+    #define __disable_fault_irq __disable_fiq\r
+\r
+\r
+  #endif /* (__CORTEX_M >= 0x03) */\r
+\r
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+  {\r
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\r
+  }\r
+\r
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+\r
+   __IAR_FT uint32_t __get_MSPLIM(void)\r
+    {\r
+      uint32_t res;\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+      res = 0U;\r
+    #else\r
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));\r
+    #endif\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __set_MSPLIM(uint32_t value)\r
+    {\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+      (void)value;\r
+    #else\r
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));\r
+    #endif\r
+    }\r
+\r
+    __IAR_FT uint32_t __get_PSPLIM(void)\r
+    {\r
+      uint32_t res;\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+      res = 0U;\r
+    #else\r
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));\r
+    #endif\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __set_PSPLIM(uint32_t value)\r
+    {\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+      (void)value;\r
+    #else\r
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));\r
+    #endif\r
+    }\r
+\r
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)\r
+    {\r
+      uint32_t res;\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+      res = 0U;\r
+    #else\r
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));\r
+    #endif\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)\r
+    {\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+      (void)value;\r
+    #else\r
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));\r
+    #endif\r
+    }\r
+\r
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)\r
+    {\r
+      uint32_t res;\r
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));\r
+      return res;\r
+    }\r
+\r
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)\r
+    {\r
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));\r
+    }\r
+\r
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))\r
+\r
+#if __IAR_M0_FAMILY\r
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+  {\r
+    if ((sat >= 1U) && (sat <= 32U))\r
+    {\r
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+      const int32_t min = -1 - max ;\r
+      if (val > max)\r
+      {\r
+        return max;\r
+      }\r
+      else if (val < min)\r
+      {\r
+        return min;\r
+      }\r
+    }\r
+    return val;\r
+  }\r
+\r
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+  {\r
+    if (sat <= 31U)\r
+    {\r
+      const uint32_t max = ((1U << sat) - 1U);\r
+      if (val > (int32_t)max)\r
+      {\r
+        return max;\r
+      }\r
+      else if (val < 0)\r
+      {\r
+        return 0U;\r
+      }\r
+    }\r
+    return (uint32_t)val;\r
+  }\r
+#endif\r
+\r
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+\r
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\r
+  {\r
+    uint32_t res;\r
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+    return ((uint8_t)res);\r
+  }\r
+\r
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\r
+  {\r
+    uint32_t res;\r
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+    return ((uint16_t)res);\r
+  }\r
+\r
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\r
+  {\r
+    uint32_t res;\r
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+    return res;\r
+  }\r
+\r
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+  {\r
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+  }\r
+\r
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+  {\r
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+  }\r
+\r
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\r
+  {\r
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");\r
+  }\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
+\r
+\r
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+    return ((uint8_t)res);\r
+  }\r
+\r
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+    return ((uint16_t)res);\r
+  }\r
+\r
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+    return res;\r
+  }\r
+\r
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+  {\r
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+  }\r
+\r
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+  {\r
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+  }\r
+\r
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
+  {\r
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+  }\r
+\r
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+    return ((uint8_t)res);\r
+  }\r
+\r
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+    return ((uint16_t)res);\r
+  }\r
+\r
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+    return res;\r
+  }\r
+\r
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+    return res;\r
+  }\r
+\r
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+    return res;\r
+  }\r
+\r
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+  {\r
+    uint32_t res;\r
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+    return res;\r
+  }\r
+\r
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#undef __IAR_FT\r
+#undef __IAR_M0_FAMILY\r
+#undef __ICCARM_V8\r
+\r
+#pragma diag_default=Pe940\r
+#pragma diag_default=Pe177\r
+\r
+#endif /* __CMSIS_ICCARM_H__ */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_version.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/cmsis_version.h
new file mode 100644 (file)
index 0000000..ae3f2e3
--- /dev/null
@@ -0,0 +1,39 @@
+/**************************************************************************//**\r
+ * @file     cmsis_version.h\r
+ * @brief    CMSIS Core(M) Version definitions\r
+ * @version  V5.0.2\r
+ * @date     19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CMSIS_VERSION_H\r
+#define __CMSIS_VERSION_H\r
+\r
+/*  CMSIS Version definitions */\r
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\r
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\r
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\r
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\r
+#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_armv8mbl.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_armv8mbl.h
new file mode 100644 (file)
index 0000000..ec76ab2
--- /dev/null
@@ -0,0 +1,1918 @@
+/**************************************************************************//**\r
+ * @file     core_armv8mbl.h\r
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\r
+ * @version  V5.0.7\r
+ * @date     22. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MBL_H_GENERIC\r
+#define __CORE_ARMV8MBL_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_ARMv8MBL\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/*  CMSIS definitions */\r
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\r
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT\r
+#define __CORE_ARMV8MBL_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __ARMv8MBL_REV\r
+    #define __ARMv8MBL_REV               0x0000U\r
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __FPU_PRESENT\r
+    #define __FPU_PRESENT             0U\r
+    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __SAUREGION_PRESENT\r
+    #define __SAUREGION_PRESENT       0U\r
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __VTOR_PRESENT\r
+    #define __VTOR_PRESENT            0U\r
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          2U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __ETM_PRESENT\r
+    #define __ETM_PRESENT             0U\r
+    #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MTB_PRESENT\r
+    #define __MTB_PRESENT             0U\r
+    #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MBL */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+  - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[16U];\r
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[16U];\r
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[16U];\r
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[16U];\r
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[16U];\r
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
+        uint32_t RESERVED5[16U];\r
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
+}  NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+#else\r
+        uint32_t RESERVED0;\r
+#endif\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+        uint32_t RESERVED1;\r
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+        uint32_t RESERVED0[6U];\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+        uint32_t RESERVED3[1U];\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+        uint32_t RESERVED5[1U];\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED6[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+        uint32_t RESERVED7[1U];\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+        uint32_t RESERVED8[1U];\r
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
+        uint32_t RESERVED9[1U];\r
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
+        uint32_t RESERVED10[1U];\r
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
+        uint32_t RESERVED11[1U];\r
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
+        uint32_t RESERVED12[1U];\r
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
+        uint32_t RESERVED13[1U];\r
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
+        uint32_t RESERVED14[1U];\r
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
+        uint32_t RESERVED15[1U];\r
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
+        uint32_t RESERVED16[1U];\r
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
+        uint32_t RESERVED17[1U];\r
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
+        uint32_t RESERVED18[1U];\r
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
+        uint32_t RESERVED19[1U];\r
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
+        uint32_t RESERVED20[1U];\r
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
+        uint32_t RESERVED21[1U];\r
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
+        uint32_t RESERVED22[1U];\r
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
+        uint32_t RESERVED23[1U];\r
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
+        uint32_t RESERVED24[1U];\r
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
+        uint32_t RESERVED25[1U];\r
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
+        uint32_t RESERVED26[1U];\r
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
+        uint32_t RESERVED27[1U];\r
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
+        uint32_t RESERVED28[1U];\r
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
+        uint32_t RESERVED29[1U];\r
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
+        uint32_t RESERVED30[1U];\r
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
+        uint32_t RESERVED31[1U];\r
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
+        uint32_t RESERVED3[809U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\r
+        uint32_t RESERVED4[4U];\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
+        uint32_t RESERVED0[7U];\r
+  union {\r
+  __IOM uint32_t MAIR[2];\r
+  struct {\r
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
+  };\r
+  };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
+  \brief    Type definitions for the Security Attribution Unit (SAU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
+\r
+\r
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
+  #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
+  #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\r
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
+#endif\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping()  (0U)\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Get Interrupt Target State\r
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+  \return             1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Target State\r
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Interrupt Target State\r
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+           If VTOR is not present address 0 must be mapped to SRAM.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                 SCB_AIRCR_SYSRESETREQ_Msk);\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Enable Interrupt (non-secure)\r
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status (non-secure)\r
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt (non-secure)\r
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt (non-secure)\r
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt (non-secure)\r
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt (non-secure)\r
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt (non-secure)\r
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority (non-secure)\r
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority (non-secure)\r
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##########################   SAU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+  \brief    Functions that configure the SAU.\r
+  @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+  \brief   Enable SAU\r
+  \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+  \brief   Disable SAU\r
+  \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   System Tick Configuration (non-secure)\r
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                         /* Reload value impossible */\r
+  }\r
+\r
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                      SysTick_CTRL_TICKINT_Msk   |\r
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                           /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_armv8mml.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_armv8mml.h
new file mode 100644 (file)
index 0000000..2d0f106
--- /dev/null
@@ -0,0 +1,2927 @@
+/**************************************************************************//**\r
+ * @file     core_armv8mml.h\r
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\r
+ * @version  V5.0.7\r
+ * @date     06. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MML_H_GENERIC\r
+#define __CORE_ARMV8MML_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_ARMv8MML\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/*  CMSIS Armv8MML definitions */\r
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\r
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined(__ARM_FEATURE_DSP)\r
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined(__ARM_FEATURE_DSP)\r
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined(__ARM_FEATURE_DSP)\r
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined(__ARM_FEATURE_DSP)\r
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MML_H_DEPENDANT\r
+#define __CORE_ARMV8MML_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __ARMv8MML_REV\r
+    #define __ARMv8MML_REV               0x0000U\r
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __FPU_PRESENT\r
+    #define __FPU_PRESENT             0U\r
+    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __SAUREGION_PRESENT\r
+    #define __SAUREGION_PRESENT       0U\r
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __DSP_PRESENT\r
+    #define __DSP_PRESENT             0U\r
+    #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          3U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MML */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+  - Core SAU Register\r
+  - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\r
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\r
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[16U];\r
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[16U];\r
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[16U];\r
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[16U];\r
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[16U];\r
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
+        uint32_t RESERVED5[16U];\r
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
+        uint32_t RESERVED6[580U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
+}  NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\r
+        uint32_t RESERVED3[92U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r
+        uint32_t RESERVED4[15U];\r
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\r
+        uint32_t RESERVED5[1U];\r
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r
+        uint32_t RESERVED6[1U];\r
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r
+        uint32_t RESERVED7[6U];\r
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r
+        uint32_t RESERVED8[1U];\r
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+  __OM  union\r
+  {\r
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
+        uint32_t RESERVED0[864U];\r
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
+        uint32_t RESERVED1[15U];\r
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
+        uint32_t RESERVED2[15U];\r
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
+        uint32_t RESERVED3[29U];\r
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
+        uint32_t RESERVED4[43U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
+        uint32_t RESERVED5[1U];\r
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\r
+        uint32_t RESERVED6[4U];\r
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+        uint32_t RESERVED3[1U];\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+        uint32_t RESERVED5[1U];\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED6[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+        uint32_t RESERVED7[1U];\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+        uint32_t RESERVED8[1U];\r
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
+        uint32_t RESERVED9[1U];\r
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
+        uint32_t RESERVED10[1U];\r
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
+        uint32_t RESERVED11[1U];\r
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
+        uint32_t RESERVED12[1U];\r
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
+        uint32_t RESERVED13[1U];\r
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
+        uint32_t RESERVED14[1U];\r
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
+        uint32_t RESERVED15[1U];\r
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
+        uint32_t RESERVED16[1U];\r
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
+        uint32_t RESERVED17[1U];\r
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
+        uint32_t RESERVED18[1U];\r
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
+        uint32_t RESERVED19[1U];\r
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
+        uint32_t RESERVED20[1U];\r
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
+        uint32_t RESERVED21[1U];\r
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
+        uint32_t RESERVED22[1U];\r
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
+        uint32_t RESERVED23[1U];\r
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
+        uint32_t RESERVED24[1U];\r
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
+        uint32_t RESERVED25[1U];\r
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
+        uint32_t RESERVED26[1U];\r
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
+        uint32_t RESERVED27[1U];\r
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
+        uint32_t RESERVED28[1U];\r
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
+        uint32_t RESERVED29[1U];\r
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
+        uint32_t RESERVED30[1U];\r
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
+        uint32_t RESERVED31[1U];\r
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
+        uint32_t RESERVED32[934U];\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r
+        uint32_t RESERVED33[1U];\r
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
+        uint32_t RESERVED3[809U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\r
+        uint32_t RESERVED4[4U];\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\r
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\r
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\r
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\r
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\r
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\r
+        uint32_t RESERVED0[1];\r
+  union {\r
+  __IOM uint32_t MAIR[2];\r
+  struct {\r
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
+  };\r
+  };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
+  \brief    Type definitions for the Security Attribution Unit (SAU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
+#else\r
+        uint32_t RESERVED0[3];\r
+#endif\r
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\r
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
+  \brief    Type definitions for the Floating Point Unit (FPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\r
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
+\r
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\r
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\r
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
+  #endif\r
+\r
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\r
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\r
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
+  #endif\r
+\r
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\r
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Debug Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\r
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Priority Grouping\r
+  \details Sets the priority grouping field using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping\r
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Get Interrupt Target State\r
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+  \return             1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Target State\r
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Interrupt Target State\r
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Set Priority Grouping (non-secure)\r
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r
+  SCB_NS->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping (non-secure)\r
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt (non-secure)\r
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status (non-secure)\r
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt (non-secure)\r
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt (non-secure)\r
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt (non-secure)\r
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt (non-secure)\r
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt (non-secure)\r
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority (non-secure)\r
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority (non-secure)\r
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+  uint32_t mvfr0;\r
+\r
+  mvfr0 = FPU->MVFR0;\r
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+  {\r
+    return 2U;           /* Double + Single precision FPU */\r
+  }\r
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+  {\r
+    return 1U;           /* Single precision FPU */\r
+  }\r
+  else\r
+  {\r
+    return 0U;           /* No FPU */\r
+  }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##########################   SAU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+  \brief    Functions that configure the SAU.\r
+  @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+  \brief   Enable SAU\r
+  \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+  \brief   Disable SAU\r
+  \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   System Tick Configuration (non-secure)\r
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                         /* Reload value impossible */\r
+  }\r
+\r
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                      SysTick_CTRL_TICKINT_Msk   |\r
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                           /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+  \brief    Functions that access the ITM debug interface.\r
+  @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+  \brief   ITM Send Character\r
+  \details Transmits a character via the ITM channel 0, and\r
+           \li Just returns when no debugger is connected that has booked the output.\r
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+  \param [in]     ch  Character to transmit.\r
+  \returns            Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0U].u32 == 0UL)\r
+    {\r
+      __NOP();\r
+    }\r
+    ITM->PORT[0U].u8 = (uint8_t)ch;\r
+  }\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Receive Character\r
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+  \return             Received character.\r
+  \return         -1  No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+  int32_t ch = -1;                           /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+  {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Check Character\r
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+  \return          0  No character available.\r
+  \return          1  Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+  {\r
+    return (0);                              /* no character available */\r
+  }\r
+  else\r
+  {\r
+    return (1);                              /*    character available */\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm0.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm0.h
new file mode 100644 (file)
index 0000000..6f82227
--- /dev/null
@@ -0,0 +1,949 @@
+/**************************************************************************//**\r
+ * @file     core_cm0.h\r
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.5\r
+ * @date     28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_M0\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
\r
+/*  CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\r
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM0_REV\r
+    #define __CM0_REV               0x0000U\r
+    #warning "__CM0_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          2U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[31U];\r
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[31U];\r
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[31U];\r
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[31U];\r
+        uint32_t RESERVED4[64U];\r
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
+}  NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+        uint32_t RESERVED0;\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+        uint32_t RESERVED1;\r
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+            Therefore they are not covered by the Cortex-M0 header file.\r
+  @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping()  (0U)\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           Address 0 must be mapped to SRAM.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                 SCB_AIRCR_SYSRESETREQ_Msk);\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm0plus.h
new file mode 100644 (file)
index 0000000..b9377e8
--- /dev/null
@@ -0,0 +1,1083 @@
+/**************************************************************************//**\r
+ * @file     core_cm0plus.h\r
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
+ * @version  V5.0.6\r
+ * @date     28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0PLUS_H_GENERIC\r
+#define __CORE_CM0PLUS_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex-M0+\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
\r
+/*  CMSIS CM0+ definitions */\r
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\r
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
+#define __CORE_CM0PLUS_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM0PLUS_REV\r
+    #define __CM0PLUS_REV             0x0000U\r
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __VTOR_PRESENT\r
+    #define __VTOR_PRESENT            0U\r
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          2U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex-M0+ */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[31U];\r
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[31U];\r
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[31U];\r
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[31U];\r
+        uint32_t RESERVED4[64U];\r
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
+}  NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+#else\r
+        uint32_t RESERVED0;\r
+#endif\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+        uint32_t RESERVED1;\r
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+            Therefore they are not covered by the Cortex-M0+ header file.\r
+  @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping()  (0U)\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+           If VTOR is not present address 0 must be mapped to SRAM.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+    uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                 SCB_AIRCR_SYSRESETREQ_Msk);\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm1.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm1.h
new file mode 100644 (file)
index 0000000..fd1c407
--- /dev/null
@@ -0,0 +1,976 @@
+/**************************************************************************//**\r
+ * @file     core_cm1.h\r
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File\r
+ * @version  V1.0.0\r
+ * @date     23. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM1_H_GENERIC\r
+#define __CORE_CM1_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_M1\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
\r
+/*  CMSIS CM1 definitions */\r
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\r
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM1_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM1_H_DEPENDANT\r
+#define __CORE_CM1_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM1_REV\r
+    #define __CM1_REV               0x0100U\r
+    #warning "__CM1_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          2U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M1 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[31U];\r
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[31U];\r
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[31U];\r
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[31U];\r
+        uint32_t RESERVED4[64U];\r
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
+}  NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+        uint32_t RESERVED0;\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+        uint32_t RESERVED1;\r
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\r
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\r
+\r
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\r
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+            Therefore they are not covered by the Cortex-M1 header file.\r
+  @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping()  (0U)\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           Address 0 must be mapped to SRAM.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                 SCB_AIRCR_SYSRESETREQ_Msk);\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM1_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm23.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm23.h
new file mode 100644 (file)
index 0000000..8202a8d
--- /dev/null
@@ -0,0 +1,1993 @@
+/**************************************************************************//**\r
+ * @file     core_cm23.h\r
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.7\r
+ * @date     22. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM23_H_GENERIC\r
+#define __CORE_CM23_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_M23\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/*  CMSIS definitions */\r
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\r
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM23_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM23_H_DEPENDANT\r
+#define __CORE_CM23_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM23_REV\r
+    #define __CM23_REV                0x0000U\r
+    #warning "__CM23_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __FPU_PRESENT\r
+    #define __FPU_PRESENT             0U\r
+    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __SAUREGION_PRESENT\r
+    #define __SAUREGION_PRESENT       0U\r
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __VTOR_PRESENT\r
+    #define __VTOR_PRESENT            0U\r
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          2U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __ETM_PRESENT\r
+    #define __ETM_PRESENT             0U\r
+    #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MTB_PRESENT\r
+    #define __MTB_PRESENT             0U\r
+    #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M23 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+  - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[16U];\r
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[16U];\r
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[16U];\r
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[16U];\r
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[16U];\r
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
+        uint32_t RESERVED5[16U];\r
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
+}  NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+#else\r
+        uint32_t RESERVED0;\r
+#endif\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+        uint32_t RESERVED1;\r
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+        uint32_t RESERVED0[6U];\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+        uint32_t RESERVED3[1U];\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+        uint32_t RESERVED5[1U];\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED6[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+        uint32_t RESERVED7[1U];\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+        uint32_t RESERVED8[1U];\r
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
+        uint32_t RESERVED9[1U];\r
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
+        uint32_t RESERVED10[1U];\r
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
+        uint32_t RESERVED11[1U];\r
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
+        uint32_t RESERVED12[1U];\r
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
+        uint32_t RESERVED13[1U];\r
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
+        uint32_t RESERVED14[1U];\r
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
+        uint32_t RESERVED15[1U];\r
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
+        uint32_t RESERVED16[1U];\r
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
+        uint32_t RESERVED17[1U];\r
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
+        uint32_t RESERVED18[1U];\r
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
+        uint32_t RESERVED19[1U];\r
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
+        uint32_t RESERVED20[1U];\r
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
+        uint32_t RESERVED21[1U];\r
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
+        uint32_t RESERVED22[1U];\r
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
+        uint32_t RESERVED23[1U];\r
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
+        uint32_t RESERVED24[1U];\r
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
+        uint32_t RESERVED25[1U];\r
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
+        uint32_t RESERVED26[1U];\r
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
+        uint32_t RESERVED27[1U];\r
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
+        uint32_t RESERVED28[1U];\r
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
+        uint32_t RESERVED29[1U];\r
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
+        uint32_t RESERVED30[1U];\r
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
+        uint32_t RESERVED31[1U];\r
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
+        uint32_t RESERVED3[759U];\r
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\r
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\r
+        uint32_t RESERVED4[1U];\r
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\r
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\r
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
+        uint32_t RESERVED5[39U];\r
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
+        uint32_t RESERVED7[8U];\r
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\r
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\r
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\r
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\r
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 0 Definitions */\r
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\r
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\r
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\r
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\r
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\r
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
+        uint32_t RESERVED0[7U];\r
+  union {\r
+  __IOM uint32_t MAIR[2];\r
+  struct {\r
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
+  };\r
+  };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
+  \brief    Type definitions for the Security Attribution Unit (SAU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
+\r
+\r
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
+  #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
+  #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */\r
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \r
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
+#else \r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
+#endif\r
+\r
+       \r
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping()  (0U)\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Get Interrupt Target State\r
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+  \return             1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Target State\r
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Interrupt Target State\r
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+           If VTOR is not present address 0 must be mapped to SRAM.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+  uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                 SCB_AIRCR_SYSRESETREQ_Msk);\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Enable Interrupt (non-secure)\r
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status (non-secure)\r
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt (non-secure)\r
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt (non-secure)\r
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt (non-secure)\r
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt (non-secure)\r
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt (non-secure)\r
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority (non-secure)\r
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority (non-secure)\r
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##########################   SAU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+  \brief    Functions that configure the SAU.\r
+  @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+  \brief   Enable SAU\r
+  \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+  \brief   Disable SAU\r
+  \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   System Tick Configuration (non-secure)\r
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                         /* Reload value impossible */\r
+  }\r
+\r
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                      SysTick_CTRL_TICKINT_Msk   |\r
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                           /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM23_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm3.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm3.h
new file mode 100644 (file)
index 0000000..b0dfbd3
--- /dev/null
@@ -0,0 +1,1941 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.h\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.8\r
+ * @date     04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_M3\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/*  CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM3_REV\r
+    #define __CM3_REV               0x0200U\r
+    #warning "__CM3_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          3U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[24U];\r
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[24U];\r
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[24U];\r
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[24U];\r
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[56U];\r
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
+        uint32_t RESERVED5[644U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
+}  NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
+        uint32_t RESERVED0[5U];\r
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\r
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
+#else\r
+        uint32_t RESERVED1[1U];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+  __OM  union\r
+  {\r
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
+        uint32_t RESERVED0[864U];\r
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
+        uint32_t RESERVED1[15U];\r
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
+        uint32_t RESERVED2[15U];\r
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
+        uint32_t RESERVED3[29U];\r
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
+        uint32_t RESERVED4[43U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
+        uint32_t RESERVED5[6U];\r
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
+        uint32_t RESERVED3[759U];\r
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
+        uint32_t RESERVED4[1U];\r
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
+        uint32_t RESERVED5[39U];\r
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
+        uint32_t RESERVED7[8U];\r
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Debug Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+\r
+\r
+/**\r
+  \brief   Set Priority Grouping\r
+  \details Sets the priority grouping field using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping\r
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+  \brief    Functions that access the ITM debug interface.\r
+  @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+  \brief   ITM Send Character\r
+  \details Transmits a character via the ITM channel 0, and\r
+           \li Just returns when no debugger is connected that has booked the output.\r
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+  \param [in]     ch  Character to transmit.\r
+  \returns            Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0U].u32 == 0UL)\r
+    {\r
+      __NOP();\r
+    }\r
+    ITM->PORT[0U].u8 = (uint8_t)ch;\r
+  }\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Receive Character\r
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+  \return             Received character.\r
+  \return         -1  No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+  int32_t ch = -1;                           /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+  {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Check Character\r
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+  \return          0  No character available.\r
+  \return          1  Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+  {\r
+    return (0);                              /* no character available */\r
+  }\r
+  else\r
+  {\r
+    return (1);                              /*    character available */\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm33.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm33.h
new file mode 100644 (file)
index 0000000..02f82e2
--- /dev/null
@@ -0,0 +1,3002 @@
+/**************************************************************************//**\r
+ * @file     core_cm33.h\r
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.9\r
+ * @date     06. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM33_H_GENERIC\r
+#define __CORE_CM33_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_M33\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/*  CMSIS CM33 definitions */\r
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\r
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+  #if defined (__TARGET_FPU_VFP)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined (__ARM_PCS_VFP)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined (__ARMVFP__)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+      #define __DSP_USED       1U\r
+    #else\r
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+      #define __DSP_USED         0U\r
+    #endif\r
+  #else\r
+    #define __DSP_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined (__TI_VFP_SUPPORT__)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined (__FPU_VFP__)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM33_H_DEPENDANT\r
+#define __CORE_CM33_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM33_REV\r
+    #define __CM33_REV                0x0000U\r
+    #warning "__CM33_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __FPU_PRESENT\r
+    #define __FPU_PRESENT             0U\r
+    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __SAUREGION_PRESENT\r
+    #define __SAUREGION_PRESENT       0U\r
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __DSP_PRESENT\r
+    #define __DSP_PRESENT             0U\r
+    #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          3U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M33 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+  - Core SAU Register\r
+  - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\r
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\r
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[16U];\r
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[16U];\r
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[16U];\r
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[16U];\r
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[16U];\r
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
+        uint32_t RESERVED5[16U];\r
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
+        uint32_t RESERVED6[580U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
+}  NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\r
+        uint32_t RESERVED3[92U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r
+        uint32_t RESERVED4[15U];\r
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\r
+        uint32_t RESERVED5[1U];\r
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r
+        uint32_t RESERVED6[1U];\r
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r
+        uint32_t RESERVED7[6U];\r
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r
+        uint32_t RESERVED8[1U];\r
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+  __OM  union\r
+  {\r
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
+        uint32_t RESERVED0[864U];\r
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
+        uint32_t RESERVED1[15U];\r
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
+        uint32_t RESERVED2[15U];\r
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
+        uint32_t RESERVED3[29U];\r
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
+        uint32_t RESERVED4[43U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
+        uint32_t RESERVED5[1U];\r
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\r
+        uint32_t RESERVED6[4U];\r
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+        uint32_t RESERVED3[1U];\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+        uint32_t RESERVED5[1U];\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED6[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+        uint32_t RESERVED7[1U];\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+        uint32_t RESERVED8[1U];\r
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
+        uint32_t RESERVED9[1U];\r
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
+        uint32_t RESERVED10[1U];\r
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
+        uint32_t RESERVED11[1U];\r
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
+        uint32_t RESERVED12[1U];\r
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
+        uint32_t RESERVED13[1U];\r
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
+        uint32_t RESERVED14[1U];\r
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
+        uint32_t RESERVED15[1U];\r
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
+        uint32_t RESERVED16[1U];\r
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
+        uint32_t RESERVED17[1U];\r
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
+        uint32_t RESERVED18[1U];\r
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
+        uint32_t RESERVED19[1U];\r
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
+        uint32_t RESERVED20[1U];\r
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
+        uint32_t RESERVED21[1U];\r
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
+        uint32_t RESERVED22[1U];\r
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
+        uint32_t RESERVED23[1U];\r
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
+        uint32_t RESERVED24[1U];\r
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
+        uint32_t RESERVED25[1U];\r
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
+        uint32_t RESERVED26[1U];\r
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
+        uint32_t RESERVED27[1U];\r
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
+        uint32_t RESERVED28[1U];\r
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
+        uint32_t RESERVED29[1U];\r
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
+        uint32_t RESERVED30[1U];\r
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
+        uint32_t RESERVED31[1U];\r
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
+        uint32_t RESERVED32[934U];\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r
+        uint32_t RESERVED33[1U];\r
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
+        uint32_t RESERVED3[759U];\r
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\r
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\r
+        uint32_t RESERVED4[1U];\r
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\r
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\r
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
+        uint32_t RESERVED5[39U];\r
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
+        uint32_t RESERVED7[8U];\r
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\r
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\r
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\r
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\r
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 0 Definitions */\r
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\r
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\r
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\r
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\r
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\r
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\r
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\r
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\r
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\r
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\r
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\r
+        uint32_t RESERVED0[1];\r
+  union {\r
+  __IOM uint32_t MAIR[2];\r
+  struct {\r
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
+  };\r
+  };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
+  \brief    Type definitions for the Security Attribution Unit (SAU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
+#else\r
+        uint32_t RESERVED0[3];\r
+#endif\r
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\r
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
+  \brief    Type definitions for the Floating Point Unit (FPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+        uint32_t RESERVED4[1U];\r
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\r
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
+\r
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\r
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\r
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
+  #endif\r
+\r
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
+  #endif\r
+\r
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\r
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\r
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
+\r
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
+  #endif\r
+\r
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\r
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Debug Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \r
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
+#else \r
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
+#endif\r
+\r
+\r
+/**\r
+  \brief   Set Priority Grouping\r
+  \details Sets the priority grouping field using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping\r
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Get Interrupt Target State\r
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+  \return             1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Target State\r
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Interrupt Target State\r
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  if interrupt is assigned to Secure\r
+                      1  if interrupt is assigned to Non Secure\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   Set Priority Grouping (non-secure)\r
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\r
+  SCB_NS->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping (non-secure)\r
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt (non-secure)\r
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status (non-secure)\r
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt (non-secure)\r
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt (non-secure)\r
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt (non-secure)\r
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt (non-secure)\r
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt (non-secure)\r
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority (non-secure)\r
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority (non-secure)\r
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+  uint32_t mvfr0;\r
+\r
+  mvfr0 = FPU->MVFR0;\r
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+  {\r
+    return 2U;           /* Double + Single precision FPU */\r
+  }\r
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+  {\r
+    return 1U;           /* Single precision FPU */\r
+  }\r
+  else\r
+  {\r
+    return 0U;           /* No FPU */\r
+  }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##########################   SAU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+  \brief    Functions that configure the SAU.\r
+  @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+  \brief   Enable SAU\r
+  \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+  \brief   Disable SAU\r
+  \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+  \brief   System Tick Configuration (non-secure)\r
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                         /* Reload value impossible */\r
+  }\r
+\r
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                      SysTick_CTRL_TICKINT_Msk   |\r
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                           /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+  \brief    Functions that access the ITM debug interface.\r
+  @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+  \brief   ITM Send Character\r
+  \details Transmits a character via the ITM channel 0, and\r
+           \li Just returns when no debugger is connected that has booked the output.\r
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+  \param [in]     ch  Character to transmit.\r
+  \returns            Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0U].u32 == 0UL)\r
+    {\r
+      __NOP();\r
+    }\r
+    ITM->PORT[0U].u8 = (uint8_t)ch;\r
+  }\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Receive Character\r
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+  \return             Received character.\r
+  \return         -1  No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+  int32_t ch = -1;                           /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+  {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Check Character\r
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+  \return          0  No character available.\r
+  \return          1  Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+  {\r
+    return (0);                              /* no character available */\r
+  }\r
+  else\r
+  {\r
+    return (1);                              /*    character available */\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm4.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm4.h
new file mode 100644 (file)
index 0000000..308b868
--- /dev/null
@@ -0,0 +1,2129 @@
+/**************************************************************************//**\r
+ * @file     core_cm4.h\r
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.8\r
+ * @date     04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_M4\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM4_REV\r
+    #define __CM4_REV               0x0000U\r
+    #warning "__CM4_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __FPU_PRESENT\r
+    #define __FPU_PRESENT             0U\r
+    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          3U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+  - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[24U];\r
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[24U];\r
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[24U];\r
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[24U];\r
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[56U];\r
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
+        uint32_t RESERVED5[644U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
+}  NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
+        uint32_t RESERVED0[5U];\r
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+  __OM  union\r
+  {\r
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
+        uint32_t RESERVED0[864U];\r
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
+        uint32_t RESERVED1[15U];\r
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
+        uint32_t RESERVED2[15U];\r
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
+        uint32_t RESERVED3[29U];\r
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
+        uint32_t RESERVED4[43U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
+        uint32_t RESERVED5[6U];\r
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
+        uint32_t RESERVED3[759U];\r
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
+        uint32_t RESERVED4[1U];\r
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
+        uint32_t RESERVED5[39U];\r
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
+        uint32_t RESERVED7[8U];\r
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
+  \brief    Type definitions for the Floating Point Unit (FPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Debug Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\r
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\r
+\r
+\r
+/**\r
+  \brief   Set Priority Grouping\r
+  \details Sets the priority grouping field using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping\r
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+  uint32_t mvfr0;\r
+\r
+  mvfr0 = FPU->MVFR0;\r
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+  {\r
+    return 1U;           /* Single precision FPU */\r
+  }\r
+  else\r
+  {\r
+    return 0U;           /* No FPU */\r
+  }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+  \brief    Functions that access the ITM debug interface.\r
+  @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+  \brief   ITM Send Character\r
+  \details Transmits a character via the ITM channel 0, and\r
+           \li Just returns when no debugger is connected that has booked the output.\r
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+  \param [in]     ch  Character to transmit.\r
+  \returns            Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0U].u32 == 0UL)\r
+    {\r
+      __NOP();\r
+    }\r
+    ITM->PORT[0U].u8 = (uint8_t)ch;\r
+  }\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Receive Character\r
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+  \return             Received character.\r
+  \return         -1  No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+  int32_t ch = -1;                           /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+  {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Check Character\r
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+  \return          0  No character available.\r
+  \return          1  Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+  {\r
+    return (0);                              /* no character available */\r
+  }\r
+  else\r
+  {\r
+    return (1);                              /*    character available */\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm7.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_cm7.h
new file mode 100644 (file)
index 0000000..ada6c2a
--- /dev/null
@@ -0,0 +1,2671 @@
+/**************************************************************************//**\r
+ * @file     core_cm7.h\r
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.8\r
+ * @date     04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup Cortex_M7\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+      #define __FPU_USED       1U\r
+    #else\r
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+      #define __FPU_USED       0U\r
+    #endif\r
+  #else\r
+    #define __FPU_USED         0U\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __CM7_REV\r
+    #define __CM7_REV               0x0000U\r
+    #warning "__CM7_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __FPU_PRESENT\r
+    #define __FPU_PRESENT             0U\r
+    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __ICACHE_PRESENT\r
+    #define __ICACHE_PRESENT          0U\r
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __DCACHE_PRESENT\r
+    #define __DCACHE_PRESENT          0U\r
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __DTCM_PRESENT\r
+    #define __DTCM_PRESENT            0U\r
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          3U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+  - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[24U];\r
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[24U];\r
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[24U];\r
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[24U];\r
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[56U];\r
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
+        uint32_t RESERVED5[644U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
+}  NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
+        uint32_t RESERVED0[1U];\r
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
+        uint32_t RESERVED3[93U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r
+        uint32_t RESERVED4[15U];\r
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\r
+        uint32_t RESERVED5[1U];\r
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r
+        uint32_t RESERVED6[1U];\r
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r
+        uint32_t RESERVED7[6U];\r
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r
+        uint32_t RESERVED8[1U];\r
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+  __OM  union\r
+  {\r
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
+        uint32_t RESERVED0[864U];\r
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
+        uint32_t RESERVED1[15U];\r
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
+        uint32_t RESERVED2[15U];\r
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
+        uint32_t RESERVED3[29U];\r
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
+        uint32_t RESERVED4[43U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
+        uint32_t RESERVED5[6U];\r
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+        uint32_t RESERVED3[981U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
+        uint32_t RESERVED3[759U];\r
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
+        uint32_t RESERVED4[1U];\r
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
+        uint32_t RESERVED5[39U];\r
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
+        uint32_t RESERVED7[8U];\r
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES                  4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
+  \brief    Type definitions for the Floating Point Unit (FPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Debug Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\r
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\r
+\r
+\r
+/**\r
+  \brief   Set Priority Grouping\r
+  \details Sets the priority grouping field using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping\r
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ##########################  MPU functions  #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+  uint32_t mvfr0;\r
+\r
+  mvfr0 = SCB->MVFR0;\r
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+  {\r
+    return 2U;           /* Double + Single precision FPU */\r
+  }\r
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+  {\r
+    return 1U;           /* Single precision FPU */\r
+  }\r
+  else\r
+  {\r
+    return 0U;           /* No FPU */\r
+  }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##########################  Cache functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+  \brief    Functions that configure Instruction and Data cache.\r
+  @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\r
+\r
+\r
+/**\r
+  \brief   Enable I-Cache\r
+  \details Turns on I-Cache\r
+  */\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
+{\r
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+    __DSB();\r
+    __ISB();\r
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r
+    __DSB();\r
+    __ISB();\r
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable I-Cache\r
+  \details Turns off I-Cache\r
+  */\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
+{\r
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+    __DSB();\r
+    __ISB();\r
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\r
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Invalidate I-Cache\r
+  \details Invalidates I-Cache\r
+  */\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
+{\r
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+    __DSB();\r
+    __ISB();\r
+    SCB->ICIALLU = 0UL;\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable D-Cache\r
+  \details Turns on D-Cache\r
+  */\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+    uint32_t ccsidr;\r
+    uint32_t sets;\r
+    uint32_t ways;\r
+\r
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
+    __DSB();\r
+\r
+    ccsidr = SCB->CCSIDR;\r
+\r
+                                            /* invalidate D-Cache */\r
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+    do {\r
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+      do {\r
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r
+        #if defined ( __CC_ARM )\r
+          __schedule_barrier();\r
+        #endif\r
+      } while (ways-- != 0U);\r
+    } while(sets-- != 0U);\r
+    __DSB();\r
+\r
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable D-Cache\r
+  \details Turns off D-Cache\r
+  */\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+    uint32_t ccsidr;\r
+    uint32_t sets;\r
+    uint32_t ways;\r
+\r
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
+    __DSB();\r
+\r
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\r
+    __DSB();\r
+\r
+    ccsidr = SCB->CCSIDR;\r
+\r
+                                            /* clean & invalidate D-Cache */\r
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+    do {\r
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+      do {\r
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r
+        #if defined ( __CC_ARM )\r
+          __schedule_barrier();\r
+        #endif\r
+      } while (ways-- != 0U);\r
+    } while(sets-- != 0U);\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Invalidate D-Cache\r
+  \details Invalidates D-Cache\r
+  */\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+    uint32_t ccsidr;\r
+    uint32_t sets;\r
+    uint32_t ways;\r
+\r
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
+    __DSB();\r
+\r
+    ccsidr = SCB->CCSIDR;\r
+\r
+                                            /* invalidate D-Cache */\r
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+    do {\r
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+      do {\r
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r
+        #if defined ( __CC_ARM )\r
+          __schedule_barrier();\r
+        #endif\r
+      } while (ways-- != 0U);\r
+    } while(sets-- != 0U);\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clean D-Cache\r
+  \details Cleans D-Cache\r
+  */\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+    uint32_t ccsidr;\r
+    uint32_t sets;\r
+    uint32_t ways;\r
+\r
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
+   __DSB();\r
+\r
+    ccsidr = SCB->CCSIDR;\r
+\r
+                                            /* clean D-Cache */\r
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+    do {\r
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+      do {\r
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\r
+        #if defined ( __CC_ARM )\r
+          __schedule_barrier();\r
+        #endif\r
+      } while (ways-- != 0U);\r
+    } while(sets-- != 0U);\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clean & Invalidate D-Cache\r
+  \details Cleans and Invalidates D-Cache\r
+  */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+    uint32_t ccsidr;\r
+    uint32_t sets;\r
+    uint32_t ways;\r
+\r
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
+    __DSB();\r
+\r
+    ccsidr = SCB->CCSIDR;\r
+\r
+                                            /* clean & invalidate D-Cache */\r
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+    do {\r
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+      do {\r
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r
+        #if defined ( __CC_ARM )\r
+          __schedule_barrier();\r
+        #endif\r
+      } while (ways-- != 0U);\r
+    } while(sets-- != 0U);\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   D-Cache Invalidate by address\r
+  \details Invalidates D-Cache for the given address\r
+  \param[in]   addr    address (aligned to 32-byte boundary)\r
+  \param[in]   dsize   size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+     int32_t op_size = dsize;\r
+    uint32_t op_addr = (uint32_t)addr;\r
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+    __DSB();\r
+\r
+    while (op_size > 0) {\r
+      SCB->DCIMVAC = op_addr;\r
+      op_addr += (uint32_t)linesize;\r
+      op_size -=           linesize;\r
+    }\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   D-Cache Clean by address\r
+  \details Cleans D-Cache for the given address\r
+  \param[in]   addr    address (aligned to 32-byte boundary)\r
+  \param[in]   dsize   size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+     int32_t op_size = dsize;\r
+    uint32_t op_addr = (uint32_t) addr;\r
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+    __DSB();\r
+\r
+    while (op_size > 0) {\r
+      SCB->DCCMVAC = op_addr;\r
+      op_addr += (uint32_t)linesize;\r
+      op_size -=           linesize;\r
+    }\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   D-Cache Clean and Invalidate by address\r
+  \details Cleans and invalidates D_Cache for the given address\r
+  \param[in]   addr    address (aligned to 32-byte boundary)\r
+  \param[in]   dsize   size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+     int32_t op_size = dsize;\r
+    uint32_t op_addr = (uint32_t) addr;\r
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+    __DSB();\r
+\r
+    while (op_size > 0) {\r
+      SCB->DCCIMVAC = op_addr;\r
+      op_addr += (uint32_t)linesize;\r
+      op_size -=           linesize;\r
+    }\r
+\r
+    __DSB();\r
+    __ISB();\r
+  #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+  \brief    Functions that access the ITM debug interface.\r
+  @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+  \brief   ITM Send Character\r
+  \details Transmits a character via the ITM channel 0, and\r
+           \li Just returns when no debugger is connected that has booked the output.\r
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+  \param [in]     ch  Character to transmit.\r
+  \returns            Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0U].u32 == 0UL)\r
+    {\r
+      __NOP();\r
+    }\r
+    ITM->PORT[0U].u8 = (uint8_t)ch;\r
+  }\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Receive Character\r
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+  \return             Received character.\r
+  \return         -1  No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+  int32_t ch = -1;                           /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+  {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Check Character\r
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+  \return          0  No character available.\r
+  \return          1  Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+  {\r
+    return (0);                              /* no character available */\r
+  }\r
+  else\r
+  {\r
+    return (1);                              /*    character available */\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_sc000.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_sc000.h
new file mode 100644 (file)
index 0000000..9086c64
--- /dev/null
@@ -0,0 +1,1022 @@
+/**************************************************************************//**\r
+ * @file     core_sc000.h\r
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.5\r
+ * @date     28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC000_H_GENERIC\r
+#define __CORE_SC000_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup SC000\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/*  CMSIS SC000 definitions */\r
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\r
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC000_H_DEPENDANT\r
+#define __CORE_SC000_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __SC000_REV\r
+    #define __SC000_REV             0x0000U\r
+    #warning "__SC000_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          2U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC000 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[31U];\r
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[31U];\r
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[31U];\r
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[31U];\r
+        uint32_t RESERVED4[64U];\r
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
+}  NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+        uint32_t RESERVED1[154U];\r
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+            Therefore they are not covered by the SC000 header file.\r
+  @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */\r
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+  else\r
+  {\r
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                 SCB_AIRCR_SYSRESETREQ_Msk);\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_sc300.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/core_sc300.h
new file mode 100644 (file)
index 0000000..665822d
--- /dev/null
@@ -0,0 +1,1915 @@
+/**************************************************************************//**\r
+ * @file     core_sc300.h\r
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\r
+ * @version  V5.0.6\r
+ * @date     04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC300_H_GENERIC\r
+#define __CORE_SC300_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
+  CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+   \li Required Rule 8.5, object/function definition in header file.<br>\r
+     Function definitions in header files are used to allow 'inlining'.\r
+\r
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+     Unions are used for effective representation of core registers.\r
+\r
+   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+     Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ *                 CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+  \ingroup SC3000\r
+  @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/*  CMSIS SC300 definitions */\r
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\r
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+    This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED       0U\r
+\r
+#if defined ( __CC_ARM )\r
+  #if defined __TARGET_FPU_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #if defined __ARM_PCS_VFP\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #if defined __ARMVFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+  #if defined __TI_VFP_SUPPORT__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+  #if defined __FPU_VFP__\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+  #if ( __CSMC__ & 0x400U)\r
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+  #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC300_H_DEPENDANT\r
+#define __CORE_SC300_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+  #ifndef __SC300_REV\r
+    #define __SC300_REV               0x0000U\r
+    #warning "__SC300_REV not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __MPU_PRESENT\r
+    #define __MPU_PRESENT             0U\r
+    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __NVIC_PRIO_BITS\r
+    #define __NVIC_PRIO_BITS          3U\r
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+  #endif\r
+\r
+  #ifndef __Vendor_SysTickConfig\r
+    #define __Vendor_SysTickConfig    0U\r
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+  #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+    <strong>IO Type Qualifiers</strong> are used\r
+    \li to specify the access to peripheral variables.\r
+    \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
+#else\r
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
+#endif\r
+#define     __O     volatile             /*!< Defines 'write only' permissions */\r
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC300 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+  Core Register contain:\r
+  - Core Register\r
+  - Core NVIC Register\r
+  - Core SCB Register\r
+  - Core SysTick Register\r
+  - Core Debug Register\r
+  - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_core_register Defines and Type Definitions\r
+  \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_CORE  Status and Control Registers\r
+  \brief      Core Register type definitions.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\r
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+  \brief  Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
+  } b;                                   /*!< Structure used for bit  access */\r
+  uint32_t w;                            /*!< Type      used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
+  \brief      Type definitions for the NVIC Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
+        uint32_t RESERVED0[24U];\r
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
+        uint32_t RSERVED1[24U];\r
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
+        uint32_t RESERVED2[24U];\r
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
+        uint32_t RESERVED3[24U];\r
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
+        uint32_t RESERVED4[56U];\r
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
+        uint32_t RESERVED5[644U];\r
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
+}  NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCB     System Control Block (SCB)\r
+  \brief    Type definitions for the System Control Block Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
+        uint32_t RESERVED0[5U];\r
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
+        uint32_t RESERVED1[129U];\r
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+  \brief    Type definitions for the System Control and ID Register not in the SCB\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+        uint32_t RESERVED0[1U];\r
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
+        uint32_t RESERVED1[1U];\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
+  \brief    Type definitions for the System Timer Registers.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+  __OM  union\r
+  {\r
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
+        uint32_t RESERVED0[864U];\r
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
+        uint32_t RESERVED1[15U];\r
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
+        uint32_t RESERVED2[15U];\r
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
+        uint32_t RESERVED3[29U];\r
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
+        uint32_t RESERVED4[43U];\r
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
+        uint32_t RESERVED5[6U];\r
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
+        uint32_t RESERVED0[1U];\r
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
+        uint32_t RESERVED1[1U];\r
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
+        uint32_t RESERVED2[1U];\r
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
+  \brief    Type definitions for the Trace Port Interface (TPI)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
+        uint32_t RESERVED0[2U];\r
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
+        uint32_t RESERVED1[55U];\r
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
+        uint32_t RESERVED2[131U];\r
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
+        uint32_t RESERVED3[759U];\r
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
+        uint32_t RESERVED4[1U];\r
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
+        uint32_t RESERVED5[39U];\r
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
+        uint32_t RESERVED7[8U];\r
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
+  \brief    Type definitions for the Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+  \ingroup  CMSIS_core_register\r
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
+  \brief    Type definitions for the Core Debug Registers\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Mask and shift a bit field value for use in a register bit range.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+  \brief     Mask and shift a register value to extract a bit filed value.\r
+  \param[in] field  Name of the register bit field.\r
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
+  \return           Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+  \ingroup    CMSIS_core_register\r
+  \defgroup   CMSIS_core_base     Core Definitions\r
+  \brief      Definitions for base addresses, unions, and structures.\r
+  @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+  Core Function Interface contains:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Debug Functions\r
+  - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
+  @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+  #endif\r
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
+  #define NVIC_GetActive              __NVIC_GetActive\r
+  #define NVIC_SetPriority            __NVIC_SetPriority\r
+  #define NVIC_GetPriority            __NVIC_GetPriority\r
+  #define NVIC_SystemReset            __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+  #endif\r
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+  #define NVIC_SetVector              __NVIC_SetVector\r
+  #define NVIC_GetVector              __NVIC_GetVector\r
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET          16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
+\r
+\r
+\r
+/**\r
+  \brief   Set Priority Grouping\r
+  \details Sets the priority grouping field using the required unlock sequence.\r
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+           Only values from 0..7 are used.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]      PriorityGroup  Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Grouping\r
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Enable Interrupt\r
+  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Enable status\r
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt is not enabled.\r
+  \return             1  Interrupt is enabled.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable Interrupt\r
+  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+    __DSB();\r
+    __ISB();\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Pending Interrupt\r
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not pending.\r
+  \return             1  Interrupt status is pending.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Pending Interrupt\r
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Clear Pending Interrupt\r
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Active Interrupt\r
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+  \param [in]      IRQn  Device specific interrupt number.\r
+  \return             0  Interrupt status is not active.\r
+  \return             1  Interrupt status is active.\r
+  \note    IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+  }\r
+  else\r
+  {\r
+    return(0U);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Priority\r
+  \details Sets the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]      IRQn  Interrupt number.\r
+  \param [in]  priority  Priority to set.\r
+  \note    The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+  else\r
+  {\r
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Priority\r
+  \details Reads the priority of a device specific interrupt or a processor exception.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn  Interrupt number.\r
+  \return             Interrupt Priority.\r
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if ((int32_t)(IRQn) >= 0)\r
+  {\r
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+  else\r
+  {\r
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  \brief   Encode Priority\r
+  \details Encodes the priority for an interrupt with the given priority group,\r
+           preemptive priority value, and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [in]       SubPriority  Subpriority value (starting from 0).\r
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  return (\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+  \brief   Decode Priority\r
+  \details Decodes an interrupt priority value with a given priority group to\r
+           preemptive priority value and subpriority value.\r
+           In case of a conflict between priority grouping and available\r
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+  \param [in]     PriorityGroup  Used priority group.\r
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
+  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Interrupt Vector\r
+  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+           VTOR must been relocated to SRAM before.\r
+  \param [in]   IRQn      Interrupt number\r
+  \param [in]   vector    Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Interrupt Vector\r
+  \details Reads an interrupt vector from interrupt vector table.\r
+           The interrupt number can be positive to specify a device specific interrupt,\r
+           or negative to specify a processor exception.\r
+  \param [in]   IRQn      Interrupt number.\r
+  \return                 Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+  \brief   System Reset\r
+  \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+\r
+  for(;;)                                                           /* wait until reset */\r
+  {\r
+    __NOP();\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ##########################  FPU functions  #################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+  \brief    Function that provides FPU type.\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   get FPU type\r
+  \details returns the FPU type\r
+  \returns\r
+   - \b  0: No FPU\r
+   - \b  1: Single precision FPU\r
+   - \b  2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+    return 0U;           /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+  \brief    Functions that configure the System.\r
+  @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+  \brief   System Tick Configuration\r
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+           Counter is in free running mode to generate periodic interrupts.\r
+  \param [in]  ticks  Number of ticks between two interrupts.\r
+  \return          0  Function succeeded.\r
+  \return          1  Function failed.\r
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+           must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+  {\r
+    return (1UL);                                                   /* Reload value impossible */\r
+  }\r
+\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+  \ingroup  CMSIS_Core_FunctionInterface\r
+  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+  \brief    Functions that access the ITM debug interface.\r
+  @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+  \brief   ITM Send Character\r
+  \details Transmits a character via the ITM channel 0, and\r
+           \li Just returns when no debugger is connected that has booked the output.\r
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+  \param [in]     ch  Character to transmit.\r
+  \returns            Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0U].u32 == 0UL)\r
+    {\r
+      __NOP();\r
+    }\r
+    ITM->PORT[0U].u8 = (uint8_t)ch;\r
+  }\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Receive Character\r
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+  \return             Received character.\r
+  \return         -1  No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+  int32_t ch = -1;                           /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+  {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+  \brief   ITM Check Character\r
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+  \return          0  No character available.\r
+  \return          1  Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+  {\r
+    return (0);                              /* no character available */\r
+  }\r
+  else\r
+  {\r
+    return (1);                              /*    character available */\r
+  }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/mpu_armv7.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/mpu_armv7.h
new file mode 100644 (file)
index 0000000..7d4b600
--- /dev/null
@@ -0,0 +1,270 @@
+/******************************************************************************\r
+ * @file     mpu_armv7.h\r
+ * @brief    CMSIS MPU API for Armv7-M MPU\r
+ * @version  V5.0.4\r
+ * @date     10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header    /* treat file as system include file */\r
+#endif\r
\r
+#ifndef ARM_MPU_ARMV7_H\r
+#define ARM_MPU_ARMV7_H\r
+\r
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\r
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\r
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\r
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\r
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\r
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\r
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\r
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\r
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\r
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\r
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\r
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\r
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\r
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\r
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\r
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\r
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\r
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\r
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\r
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\r
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\r
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\r
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\r
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\r
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\r
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\r
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\r
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\r
+\r
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\r
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\r
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only\r
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\r
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only\r
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access\r
+\r
+/** MPU Region Base Address Register Value\r
+*\r
+* \param Region The region to be configured, number 0 to 15.\r
+* \param BaseAddress The base address for the region.\r
+*/\r
+#define ARM_MPU_RBAR(Region, BaseAddress) \\r
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \\r
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \\r
+   (MPU_RBAR_VALID_Msk))\r
+\r
+/**\r
+* MPU Memory Access Attributes\r
+* \r
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable       Region is shareable between multiple bus masters.\r
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+*/  \r
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \\r
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \\r
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \\r
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \\r
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\r
+\r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.\r
+* \param SubRegionDisable  Sub-region disable field.\r
+* \param Size              Region size of the region to be configured, for example 4K, 8K.\r
+*/\r
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \\r
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \\r
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \\r
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))\r
+  \r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable       Region is shareable between multiple bus masters.\r
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+* \param SubRegionDisable  Sub-region disable field.\r
+* \param Size              Region size of the region to be configured, for example 4K, 8K.\r
+*/                         \r
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\r
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\r
+\r
+/**\r
+* MPU Memory Access Attribute for strongly ordered memory.\r
+*  - TEX: 000b\r
+*  - Shareable\r
+*  - Non-cacheable\r
+*  - Non-bufferable\r
+*/ \r
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\r
+\r
+/**\r
+* MPU Memory Access Attribute for device memory.\r
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)\r
+*  - Shareable or non-shareable\r
+*  - Non-cacheable\r
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)\r
+*\r
+* \param IsShareable Configures the device memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\r
+\r
+/**\r
+* MPU Memory Access Attribute for normal memory.\r
+*  - TEX: 1BBb (reflecting outer cacheability rules)\r
+*  - Shareable or non-shareable\r
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)\r
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)\r
+*\r
+* \param OuterCp Configures the outer cache policy.\r
+* \param InnerCp Configures the inner cache policy.\r
+* \param IsShareable Configures the memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\r
+\r
+/**\r
+* MPU Memory Access Attribute non-cacheable policy.\r
+*/\r
+#define ARM_MPU_CACHEP_NOCACHE 0U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, write and read allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_WRA 1U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-through, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WT_NWA 2U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_NWA 3U\r
+\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+  uint32_t RBAR; //!< The region base address register value (RBAR)\r
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR\r
+} ARM_MPU_Region_t;\r
+    \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+  __DSB();\r
+  __ISB();\r
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+  __DSB();\r
+  __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+  MPU->RNR = rnr;\r
+  MPU->RASR = 0U;\r
+}\r
+\r
+/** Configure an MPU region.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/   \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\r
+{\r
+  MPU->RBAR = rbar;\r
+  MPU->RASR = rasr;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/   \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\r
+{\r
+  MPU->RNR = rnr;\r
+  MPU->RBAR = rbar;\r
+  MPU->RASR = rasr;\r
+}\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+  uint32_t i;\r
+  for (i = 0U; i < len; ++i) \r
+  {\r
+    dst[i] = src[i];\r
+  }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+  while (cnt > MPU_TYPE_RALIASES) {\r
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\r
+    table += MPU_TYPE_RALIASES;\r
+    cnt -= MPU_TYPE_RALIASES;\r
+  }\r
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\r
+}\r
+\r
+#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/mpu_armv8.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/mpu_armv8.h
new file mode 100644 (file)
index 0000000..99ee9f9
--- /dev/null
@@ -0,0 +1,333 @@
+/******************************************************************************\r
+ * @file     mpu_armv8.h\r
+ * @brief    CMSIS MPU API for Armv8-M MPU\r
+ * @version  V5.0.4\r
+ * @date     10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header    /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef ARM_MPU_ARMV8_H\r
+#define ARM_MPU_ARMV8_H\r
+\r
+/** \brief Attribute for device memory (outer only) */\r
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )\r
+\r
+/** \brief Attribute for non-cacheable, normal memory */\r
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\r
+\r
+/** \brief Attribute for normal memory (outer and inner)\r
+* \param NT Non-Transient: Set to 1 for non-transient data.\r
+* \param WB Write-Back: Set to 1 to use write-back update policy.\r
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.\r
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.\r
+*/\r
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\r
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)\r
+\r
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)\r
+\r
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)\r
+\r
+/** \brief Memory Attribute\r
+* \param O Outer memory attributes\r
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\r
+*/\r
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\r
+\r
+/** \brief Normal memory non-shareable  */\r
+#define ARM_MPU_SH_NON   (0U)\r
+\r
+/** \brief Normal memory outer shareable  */\r
+#define ARM_MPU_SH_OUTER (2U)\r
+\r
+/** \brief Normal memory inner shareable  */\r
+#define ARM_MPU_SH_INNER (3U)\r
+\r
+/** \brief Memory access permissions\r
+* \param RO Read-Only: Set to 1 for read-only memory.\r
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.\r
+*/\r
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\r
+\r
+/** \brief Region Base Address Register value\r
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\r
+* \param SH Defines the Shareability domain for this memory region.\r
+* \param RO Read-Only: Set to 1 for a read-only memory region.\r
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.\r
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r
+*/\r
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\r
+  ((BASE & MPU_RBAR_BASE_Msk) | \\r
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\r
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\r
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r
+\r
+/** \brief Region Limit Address Register value\r
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
+* \param IDX The attribute index to be associated with this memory region.\r
+*/\r
+#define ARM_MPU_RLAR(LIMIT, IDX) \\r
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
+  (MPU_RLAR_EN_Msk))\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+  uint32_t RBAR;                   /*!< Region Base Address Register value */\r
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */\r
+} ARM_MPU_Region_t;\r
+    \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+  __DSB();\r
+  __ISB();\r
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+  __DSB();\r
+  __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Enable the Non-secure MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r
+{\r
+  __DSB();\r
+  __ISB();\r
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the Non-secure MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)\r
+{\r
+  __DSB();\r
+  __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+#endif\r
+\r
+/** Set the memory attribute encoding to the given MPU.\r
+* \param mpu Pointer to the MPU to be configured.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\r
+{\r
+  const uint8_t reg = idx / 4U;\r
+  const uint32_t pos = ((idx % 4U) * 8U);\r
+  const uint32_t mask = 0xFFU << pos;\r
+  \r
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\r
+    return; // invalid index\r
+  }\r
+  \r
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\r
+}\r
+\r
+/** Set the memory attribute encoding.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\r
+{\r
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Set the memory attribute encoding to the Non-secure MPU.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\r
+{\r
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\r
+}\r
+#endif\r
+\r
+/** Clear and disable the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\r
+{\r
+  mpu->RNR = rnr;\r
+  mpu->RLAR = 0U;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+  ARM_MPU_ClrRegionEx(MPU, rnr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Clear and disable the given Non-secure MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\r
+{  \r
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);\r
+}\r
+#endif\r
+\r
+/** Configure the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/   \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+  mpu->RNR = rnr;\r
+  mpu->RBAR = rbar;\r
+  mpu->RLAR = rlar;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/   \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Configure the given Non-secure MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/   \r
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  \r
+}\r
+#endif\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+  uint32_t i;\r
+  for (i = 0U; i < len; ++i) \r
+  {\r
+    dst[i] = src[i];\r
+  }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table to the given MPU.\r
+* \param mpu Pointer to the MPU registers to be used.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+  if (cnt == 1U) {\r
+    mpu->RNR = rnr;\r
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
+  } else {\r
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\r
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r
+    \r
+    mpu->RNR = rnrBase;\r
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
+      table += c;\r
+      cnt -= c;\r
+      rnrOffset = 0U;\r
+      rnrBase += MPU_TYPE_RALIASES;\r
+      mpu->RNR = rnrBase;\r
+    }\r
+    \r
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
+  }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Load the given number of MPU regions from a table to the Non-secure MPU.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/tz_context.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/CMSIS/Include/tz_context.h
new file mode 100644 (file)
index 0000000..d4c1474
--- /dev/null
@@ -0,0 +1,70 @@
+/******************************************************************************\r
+ * @file     tz_context.h\r
+ * @brief    Context Management for Armv8-M TrustZone\r
+ * @version  V1.0.1\r
+ * @date     10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if   defined ( __ICCARM__ )\r
+  #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef TZ_CONTEXT_H\r
+#define TZ_CONTEXT_H\r
\r
+#include <stdint.h>\r
\r
+#ifndef TZ_MODULEID_T\r
+#define TZ_MODULEID_T\r
+/// \details Data type that identifies secure software modules called by a process.\r
+typedef uint32_t TZ_ModuleId_t;\r
+#endif\r
\r
+/// \details TZ Memory ID identifies an allocated memory slot.\r
+typedef uint32_t TZ_MemoryId_t;\r
+  \r
+/// Initialize secure context memory system\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_InitContextSystem_S (void);\r
\r
+/// Allocate context memory for calling secure software modules in TrustZone\r
+/// \param[in]  module   identifies software modules called from non-secure mode\r
+/// \return value != 0 id TrustZone memory slot identifier\r
+/// \return value 0    no memory available or internal error\r
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\r
\r
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S\r
+/// \param[in]  id  TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\r
\r
+/// Load secure context (called on RTOS thread context switch)\r
+/// \param[in]  id  TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\r
\r
+/// Store secure context (called on RTOS thread context switch)\r
+/// \param[in]  id  TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\r
\r
+#endif  // TZ_CONTEXT_H\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644 (file)
index 0000000..359e92f
--- /dev/null
@@ -0,0 +1,3533 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32_hal_legacy.h\r
+  * @author  MCD Application Team\r
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants\r
+  *          macros and functions maintained for legacy purpose.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32_HAL_LEGACY\r
+#define STM32_HAL_LEGACY\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR\r
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR\r
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF\r
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR\r
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B\r
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B\r
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B\r
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B\r
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN\r
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED\r
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV\r
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV\r
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV\r
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP\r
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP\r
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP\r
+#define AWD_EVENT                       ADC_AWD_EVENT\r
+#define AWD1_EVENT                      ADC_AWD1_EVENT\r
+#define AWD2_EVENT                      ADC_AWD2_EVENT\r
+#define AWD3_EVENT                      ADC_AWD3_EVENT\r
+#define OVR_EVENT                       ADC_OVR_EVENT\r
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT\r
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS\r
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS\r
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS\r
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR\r
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8\r
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO\r
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2\r
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO\r
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4\r
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO\r
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11\r
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1\r
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE\r
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING\r
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING\r
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5\r
+\r
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY\r
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY\r
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC\r
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC\r
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL\r
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL\r
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1\r
+\r
+#if defined(STM32H7)\r
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT\r
+#endif /* STM32H7 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE\r
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE\r
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1\r
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2\r
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3\r
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4\r
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5\r
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6\r
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7\r
+#if defined(STM32L0)\r
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */\r
+#endif\r
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR\r
+#if defined(STM32F373xC) || defined(STM32F378xx)\r
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1\r
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR\r
+#endif /* STM32F373xC || STM32F378xx */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r
+\r
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1\r
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2\r
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3\r
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4\r
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5\r
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6\r
+\r
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT\r
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT\r
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT\r
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT\r
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1\r
+#if defined(STM32L0)\r
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */\r
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */\r
+/* to the second dedicated IO (only for COMP2).                               */\r
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2\r
+#else\r
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2\r
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3\r
+#endif\r
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4\r
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5\r
+\r
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW\r
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH\r
+\r
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */\r
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */\r
+#if defined(COMP_CSR_LOCK)\r
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK\r
+#elif defined(COMP_CSR_COMP1LOCK)\r
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK\r
+#elif defined(COMP_CSR_COMPxLOCK)\r
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1\r
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2\r
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2\r
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2\r
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE\r
+#endif\r
+\r
+#if defined(STM32L0)\r
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER\r
+#else\r
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED\r
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER\r
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER\r
+#endif\r
+\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE\r
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1\r
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2\r
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1\r
+#define DAC_WAVE_NONE                                   0x00000000U\r
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0\r
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1\r
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE\r
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE\r
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE\r
+\r
+#if defined(STM32G4)\r
+#define DAC_CHIPCONNECT_DISABLE       (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)\r
+#define DAC_CHIPCONNECT_ENABLE        (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)\r
+#endif\r
+\r
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5)\r
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID\r
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2\r
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4\r
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5\r
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4\r
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2\r
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32\r
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6\r
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7\r
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67\r
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67\r
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76\r
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6\r
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7\r
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6\r
+\r
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP\r
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE\r
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE\r
+\r
+#if defined(STM32L4)\r
+\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE\r
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT\r
+\r
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING\r
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
+\r
+#endif /* STM32L4 */\r
+\r
+#if defined(STM32H7)\r
+\r
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1\r
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2\r
+\r
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX\r
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX\r
+\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO\r
+\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2\r
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT\r
+\r
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING\r
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
+\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT\r
+\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD\r
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD\r
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS\r
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE\r
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE\r
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE\r
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE\r
+#define OBEX_PCROP                    OPTIONBYTE_PCROP\r
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG\r
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE\r
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE\r
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE\r
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD\r
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD\r
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE\r
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD\r
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD\r
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE\r
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD\r
+#define PAGESIZE                      FLASH_PAGE_SIZE\r
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD\r
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1\r
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2\r
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3\r
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4\r
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST\r
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST\r
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA\r
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB\r
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA\r
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB\r
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE\r
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN\r
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE\r
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN\r
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE\r
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD\r
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP\r
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV\r
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR\r
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA\r
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS\r
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST\r
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR\r
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO\r
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS\r
+#define OB_WDG_SW                     OB_IWDG_SW\r
+#define OB_WDG_HW                     OB_IWDG_HW\r
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET\r
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET\r
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET\r
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET\r
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR\r
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0\r
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1\r
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2\r
+#if defined(STM32G0)\r
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE\r
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH\r
+#else\r
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE\r
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE\r
+#endif\r
+#if defined(STM32H7)\r
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1\r
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1\r
+#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1\r
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2\r
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2\r
+#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE\r
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE\r
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET\r
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3\r
+#if defined(STM32G4)\r
+\r
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster\r
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster\r
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD\r
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD\r
+#endif /* STM32G4 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
+  * @{\r
+  */\r
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)\r
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16\r
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)\r
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef\r
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX\r
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX\r
+\r
+#if defined(STM32F4)\r
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO\r
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1\r
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1\r
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1\r
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2\r
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2\r
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2\r
+#endif\r
+\r
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1\r
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1\r
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1\r
+\r
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)\r
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW\r
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM\r
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH\r
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH\r
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/\r
+\r
+#if defined(STM32L1)\r
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW\r
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM\r
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH\r
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH\r
+#endif /* STM32L1 */\r
+\r
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r
+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW\r
+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH\r
+#endif /* STM32F0 || STM32F3 || STM32F1 */\r
+\r
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r
+\r
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER\r
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER\r
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD\r
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD\r
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE\r
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE\r
+\r
+#if defined(STM32G4)\r
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig\r
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable\r
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable\r
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset\r
+#endif /* STM32G4 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE\r
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE\r
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE\r
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE\r
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE\r
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE\r
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE\r
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE\r
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE\r
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD\r
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE\r
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE\r
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
+\r
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING\r
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING\r
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING\r
+\r
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
+\r
+/* The following 3 definition have also been present in a temporary version of lptim.h */\r
+/* They need to be renamed also to the right name, just in case */\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b\r
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b\r
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b\r
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b\r
+\r
+#define NAND_AddressTypedef             NAND_AddressTypeDef\r
+\r
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS\r
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE\r
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE\r
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE\r
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef\r
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS\r
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING\r
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR\r
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT\r
+\r
+#define __NOR_WRITE                    NOR_WRITE\r
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0\r
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1\r
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2\r
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3\r
+\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3\r
+\r
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0\r
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0\r
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0\r
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO\r
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0\r
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1\r
+\r
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5)\r
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID\r
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID\r
+#endif\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS\r
+\r
+#if defined(STM32H7)\r
+  #define I2S_IT_TXE               I2S_IT_TXP\r
+  #define I2S_IT_RXNE              I2S_IT_RXP\r
+\r
+  #define I2S_FLAG_TXE             I2S_FLAG_TXP\r
+  #define I2S_FLAG_RXNE            I2S_FLAG_RXP\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+/* Compact Flash-ATA registers description */\r
+#define CF_DATA                       ATA_DATA\r
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT\r
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER\r
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW\r
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH\r
+#define CF_CARD_HEAD                  ATA_CARD_HEAD\r
+#define CF_STATUS_CMD                 ATA_STATUS_CMD\r
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE\r
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA\r
+\r
+/* Compact Flash-ATA commands */\r
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD\r
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD\r
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD\r
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD\r
+\r
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef\r
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS\r
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING\r
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR\r
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define FORMAT_BIN                  RTC_FORMAT_BIN\r
+#define FORMAT_BCD                  RTC_FORMAT_BCD\r
+\r
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE\r
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE\r
+\r
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE\r
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE\r
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT\r
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT\r
+\r
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT\r
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1\r
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2\r
+\r
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE\r
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1\r
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1\r
+\r
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT\r
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1\r
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE\r
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE\r
+\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE\r
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE\r
+\r
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE\r
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE\r
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE\r
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE\r
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE\r
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE\r
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE\r
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE\r
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE\r
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE\r
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE\r
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE\r
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE\r
+\r
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE\r
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE\r
+\r
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE\r
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE\r
+\r
+#if defined(STM32H7)\r
+\r
+ #define SPI_FLAG_TXE                    SPI_FLAG_TXP\r
+ #define SPI_FLAG_RXNE                   SPI_FLAG_RXP\r
+\r
+ #define SPI_IT_TXE                      SPI_IT_TXP\r
+ #define SPI_IT_RXNE                     SPI_IT_RXP\r
+\r
+ #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET\r
+ #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET\r
+ #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET\r
+ #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET\r
+\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK\r
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK\r
+\r
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1\r
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2\r
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR\r
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER\r
+#define TIM_DMABase_SR                   TIM_DMABASE_SR\r
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR\r
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1\r
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2\r
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER\r
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT\r
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC\r
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR\r
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR\r
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1\r
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2\r
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3\r
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4\r
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR\r
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR\r
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR\r
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1\r
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3\r
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5\r
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6\r
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2\r
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3\r
+#define TIM_DMABase_OR                   TIM_DMABASE_OR\r
+\r
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE\r
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1\r
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2\r
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3\r
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4\r
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM\r
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER\r
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK\r
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2\r
+\r
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER\r
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS\r
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS\r
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS\r
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS\r
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS\r
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS\r
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS\r
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS\r
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS\r
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS\r
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS\r
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS\r
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS\r
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS\r
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS\r
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS\r
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS\r
+\r
+#if defined(STM32L0)\r
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO\r
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO\r
+#endif\r
+\r
+#if defined(STM32F3)\r
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1\r
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2\r
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1\r
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2\r
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1\r
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2\r
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1\r
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1\r
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2\r
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1\r
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2\r
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2\r
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1\r
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2\r
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING\r
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE\r
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
+\r
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16\r
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16\r
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16\r
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16\r
+\r
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8\r
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8\r
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8\r
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8\r
+\r
+#define __DIV_LPUART                    UART_DIV_LPUART\r
+\r
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE\r
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE\r
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE\r
+\r
+#define USARTNACK_ENABLED               USART_NACK_ENABLE\r
+#define USARTNACK_DISABLED              USART_NACK_DISABLE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define CFR_BASE                    WWDG_CFR_BASE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0\r
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1\r
+#define CAN_IT_RQCP0                CAN_IT_TME\r
+#define CAN_IT_RQCP1                CAN_IT_TME\r
+#define CAN_IT_RQCP2                CAN_IT_TME\r
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE\r
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE\r
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)\r
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)\r
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define VLAN_TAG                ETH_VLAN_TAG\r
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD\r
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD\r
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD\r
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK\r
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK\r
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK\r
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK\r
+\r
+#define ETH_MMCCR              0x00000100U\r
+#define ETH_MMCRIR             0x00000104U\r
+#define ETH_MMCTIR             0x00000108U\r
+#define ETH_MMCRIMR            0x0000010CU\r
+#define ETH_MMCTIMR            0x00000110U\r
+#define ETH_MMCTGFSCCR         0x0000014CU\r
+#define ETH_MMCTGFMSCCR        0x00000150U\r
+#define ETH_MMCTGFCR           0x00000168U\r
+#define ETH_MMCRFCECR          0x00000194U\r
+#define ETH_MMCRFAECR          0x00000198U\r
+#define ETH_MMCRGUFCR          0x000001C4U\r
+\r
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */\r
+#if defined(STM32F1)\r
+#else\r
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#endif\r
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR\r
+#define DCMI_IT_OVF             DCMI_IT_OVR\r
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI\r
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI\r
+\r
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop\r
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop\r
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \\r
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \\r
+  || defined(STM32H7)\r
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888\r
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888\r
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565\r
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555\r
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444\r
+\r
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888\r
+#define CM_RGB888               DMA2D_INPUT_RGB888\r
+#define CM_RGB565               DMA2D_INPUT_RGB565\r
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555\r
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444\r
+#define CM_L8                   DMA2D_INPUT_L8\r
+#define CM_AL44                 DMA2D_INPUT_AL44\r
+#define CM_AL88                 DMA2D_INPUT_AL88\r
+#define CM_L4                   DMA2D_INPUT_L4\r
+#define CM_A8                   DMA2D_INPUT_A8\r
+#define CM_A4                   DMA2D_INPUT_A4\r
+/**\r
+  * @}\r
+  */\r
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */\r
+\r
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef\r
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef\r
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish\r
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish\r
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish\r
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish\r
+\r
+/*HASH Algorithm Selection*/\r
+\r
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1\r
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224\r
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256\r
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5\r
+\r
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH\r
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC\r
+\r
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY\r
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect\r
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
+#if defined(STM32L0)\r
+#else\r
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
+#endif\r
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram\r
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown\r
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown\r
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock\r
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock\r
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase\r
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program\r
+\r
+ /**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter\r
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter\r
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter\r
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter\r
+\r
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
+\r
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)\r
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT\r
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT\r
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT\r
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT\r
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA\r
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA\r
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA\r
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA\r
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */\r
+\r
+#if defined(STM32F4)\r
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT\r
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT\r
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT\r
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT\r
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA\r
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA\r
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA\r
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA\r
+#endif /* STM32F4 */\r
+ /**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD\r
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg\r
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown\r
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor\r
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg\r
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown\r
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor\r
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler\r
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD\r
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler\r
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback\r
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive\r
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive\r
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC\r
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC\r
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM\r
+\r
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL\r
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING\r
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING\r
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING\r
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING\r
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING\r
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING\r
+\r
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB\r
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB\r
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER\r
+#define CR_PMODE_BB                                   CR_VOS_BB\r
+\r
+#define DBP_BitNumber                                 DBP_BIT_NUMBER\r
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER\r
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER\r
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER\r
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER\r
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER\r
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER\r
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER\r
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER\r
+#define BRE_BitNumber                                 BRE_BIT_NUMBER\r
+\r
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL\r
+\r
+ /**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT\r
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback\r
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt\r
+#define HAL_TIM_DMAError                                TIM_DMAError\r
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt\r
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt\r
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)\r
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro\r
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT\r
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback\r
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent\r
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT\r
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA\r
+#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4  || STM32L0 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload\r
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig\r
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define AES_IT_CC                      CRYP_IT_CC\r
+#define AES_IT_ERR                     CRYP_IT_ERR\r
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE\r
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH\r
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM\r
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC\r
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM\r
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC\r
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK\r
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG\r
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG\r
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE\r
+\r
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY\r
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48\r
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS\r
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER\r
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE\r
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE\r
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS\r
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS\r
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE\r
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE\r
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR\r
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING\r
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE\r
+\r
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION\r
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK\r
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT\r
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR\r
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION\r
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE\r
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT\r
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS\r
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN\r
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ\r
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET\r
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET\r
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL\r
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL\r
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET\r
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET\r
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD\r
+\r
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER\r
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI\r
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE\r
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE\r
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER\r
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE\r
+\r
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT\r
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT\r
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL\r
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET\r
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE\r
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE\r
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER\r
+\r
+#define __HAL_ADC_SQR1                                   ADC_SQR1\r
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1\r
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2\r
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK\r
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK\r
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK\r
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS\r
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS\r
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV\r
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection\r
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq\r
+#define __HAL_ADC_JSQR                                   ADC_JSQR\r
+\r
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL\r
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF\r
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT\r
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS\r
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN\r
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR\r
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT\r
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT\r
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT\r
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
+\r
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
+\r
+\r
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
+#if defined(STM32H7)\r
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1\r
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1\r
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1\r
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1\r
+#else\r
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
+#endif /* STM32H7 */\r
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#if defined(STM32F3)\r
+#define COMP_START                                       __HAL_COMP_ENABLE\r
+#define COMP_STOP                                        __HAL_COMP_DISABLE\r
+#define COMP_LOCK                                        __HAL_COMP_LOCK\r
+\r
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F302xE) || defined(STM32F302xC)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\r
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\r
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\r
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F373xC) ||defined(STM32F378xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+# endif\r
+#else\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+#endif\r
+\r
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/* Note: On these STM32 families, the only argument of this macro             */\r
+/*       is COMP_FLAG_LOCK.                                                   */\r
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */\r
+/*       argument.                                                            */\r
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+/**\r
+  * @}\r
+  */\r
+#endif\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
+                          ((WAVE) == DAC_WAVE_NOISE)|| \\r
+                          ((WAVE) == DAC_WAVE_TRIANGLE))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define IS_WRPAREA          IS_OB_WRPAREA\r
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE\r
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS\r
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2\r
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START\r
+#if defined(STM32F1)\r
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE\r
+#else\r
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE\r
+#endif /* STM32F1 */\r
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME\r
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD\r
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST\r
+#define __HAL_I2C_SPEED                 I2C_SPEED\r
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE\r
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ\r
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS\r
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE\r
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ\r
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB\r
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB\r
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE\r
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT\r
+\r
+#if defined(STM32H7)\r
+  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE\r
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE\r
+\r
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE\r
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION\r
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE\r
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION\r
+\r
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS\r
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT\r
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT\r
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD\r
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX\r
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX\r
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX\r
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX\r
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L\r
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H\r
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM\r
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES\r
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX\r
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT\r
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION\r
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE\r
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine\r
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention\r
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2\r
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2\r
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB\r
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB\r
+\r
+#if defined (STM32F4)\r
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT\r
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG\r
+#endif /* STM32F4 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI\r
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI\r
+\r
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
+\r
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE\r
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE\r
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET\r
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET\r
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE\r
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE\r
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET\r
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET\r
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE\r
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE\r
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE\r
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE\r
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE\r
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE\r
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET\r
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET\r
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE\r
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE\r
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET\r
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET\r
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE\r
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE\r
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET\r
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET\r
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE\r
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE\r
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET\r
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET\r
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
+\r
+#if defined(STM32WB)\r
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE\r
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET\r
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED\r
+#define QSPI_IRQHandler QUADSPI_IRQHandler\r
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */\r
+\r
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE\r
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE\r
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET\r
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET\r
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE\r
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE\r
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET\r
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE\r
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE\r
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET\r
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET\r
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE\r
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE\r
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET\r
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET\r
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE\r
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE\r
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET\r
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE\r
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE\r
+\r
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/\r
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/\r
+\r
+\r
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED\r
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED\r
+#endif\r
+\r
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
+\r
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE\r
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE\r
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET\r
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET\r
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE\r
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE\r
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET\r
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET\r
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
+\r
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE\r
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE\r
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE\r
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE\r
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE\r
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET\r
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET\r
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE\r
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE\r
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE\r
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET\r
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET\r
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE\r
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE\r
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE\r
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET\r
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET\r
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE\r
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE\r
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE\r
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET\r
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET\r
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE\r
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE\r
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE\r
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE\r
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE\r
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE\r
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE\r
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE\r
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE\r
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE\r
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE\r
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE\r
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET\r
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET\r
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE\r
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE\r
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE\r
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET\r
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET\r
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE\r
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE\r
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE\r
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET\r
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET\r
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE\r
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE\r
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE\r
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET\r
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET\r
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE\r
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE\r
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE\r
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET\r
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE\r
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE\r
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE\r
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE\r
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE\r
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET\r
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET\r
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE\r
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE\r
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE\r
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET\r
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET\r
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE\r
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE\r
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE\r
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET\r
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET\r
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE\r
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED\r
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE\r
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE\r
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE\r
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE\r
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET\r
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET\r
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE\r
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET\r
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE\r
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE\r
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET\r
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET\r
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
+\r
+/* alias define maintained for legacy */\r
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+\r
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE\r
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE\r
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE\r
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE\r
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE\r
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE\r
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE\r
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE\r
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE\r
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE\r
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE\r
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE\r
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE\r
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE\r
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE\r
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE\r
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE\r
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE\r
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE\r
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE\r
+\r
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET\r
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET\r
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET\r
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET\r
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET\r
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET\r
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET\r
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET\r
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET\r
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET\r
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET\r
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET\r
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET\r
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET\r
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET\r
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET\r
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET\r
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET\r
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET\r
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET\r
+\r
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED\r
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED\r
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED\r
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED\r
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED\r
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED\r
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED\r
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED\r
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED\r
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED\r
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED\r
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED\r
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED\r
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED\r
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED\r
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED\r
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED\r
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED\r
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED\r
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED\r
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED\r
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED\r
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED\r
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED\r
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED\r
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED\r
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED\r
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED\r
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED\r
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED\r
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED\r
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED\r
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED\r
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED\r
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED\r
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED\r
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED\r
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED\r
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED\r
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED\r
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED\r
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED\r
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED\r
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED\r
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED\r
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED\r
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED\r
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED\r
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED\r
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED\r
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED\r
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED\r
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED\r
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED\r
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED\r
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED\r
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED\r
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED\r
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED\r
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED\r
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED\r
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED\r
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED\r
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED\r
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED\r
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED\r
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED\r
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED\r
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED\r
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED\r
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED\r
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED\r
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED\r
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED\r
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED\r
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED\r
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED\r
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED\r
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED\r
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED\r
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED\r
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED\r
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED\r
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED\r
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED\r
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED\r
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED\r
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED\r
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED\r
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED\r
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED\r
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED\r
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED\r
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED\r
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED\r
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED\r
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED\r
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED\r
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED\r
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED\r
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED\r
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED\r
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED\r
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED\r
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED\r
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED\r
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED\r
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED\r
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED\r
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED\r
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED\r
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED\r
+\r
+#if defined(STM32L1)\r
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE\r
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET\r
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET\r
+#endif /* STM32L1 */\r
+\r
+#if defined(STM32F4)\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED\r
+#define Sdmmc1ClockSelection               SdioClockSelection\r
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO\r
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48\r
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK\r
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET\r
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE\r
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r
+#define SdioClockSelection                 Sdmmc1ClockSelection\r
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1\r
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG\r
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48\r
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()\r
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()\r
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()\r
+#endif\r
+\r
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG\r
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG\r
+\r
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE\r
+\r
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE\r
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE\r
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK\r
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK\r
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK\r
+\r
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY\r
+\r
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS\r
+#define RCC_IT_CSSHSE               RCC_IT_CSS\r
+\r
+#define RCC_PLLMUL_3                RCC_PLL_MUL3\r
+#define RCC_PLLMUL_4                RCC_PLL_MUL4\r
+#define RCC_PLLMUL_6                RCC_PLL_MUL6\r
+#define RCC_PLLMUL_8                RCC_PLL_MUL8\r
+#define RCC_PLLMUL_12               RCC_PLL_MUL12\r
+#define RCC_PLLMUL_16               RCC_PLL_MUL16\r
+#define RCC_PLLMUL_24               RCC_PLL_MUL24\r
+#define RCC_PLLMUL_32               RCC_PLL_MUL32\r
+#define RCC_PLLMUL_48               RCC_PLL_MUL48\r
+\r
+#define RCC_PLLDIV_2                RCC_PLL_DIV2\r
+#define RCC_PLLDIV_3                RCC_PLL_DIV3\r
+#define RCC_PLLDIV_4                RCC_PLL_DIV4\r
+\r
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE\r
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG\r
+#define RCC_MCO_NODIV               RCC_MCODIV_1\r
+#define RCC_MCO_DIV1                RCC_MCODIV_1\r
+#define RCC_MCO_DIV2                RCC_MCODIV_2\r
+#define RCC_MCO_DIV4                RCC_MCODIV_4\r
+#define RCC_MCO_DIV8                RCC_MCODIV_8\r
+#define RCC_MCO_DIV16               RCC_MCODIV_16\r
+#define RCC_MCO_DIV32               RCC_MCODIV_32\r
+#define RCC_MCO_DIV64               RCC_MCODIV_64\r
+#define RCC_MCO_DIV128              RCC_MCODIV_128\r
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK\r
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI\r
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE\r
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK\r
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI\r
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14\r
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48\r
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE\r
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2\r
+\r
+#if defined(STM32L4)\r
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE\r
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)\r
+#else\r
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK\r
+#endif\r
+\r
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1\r
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI\r
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5\r
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2\r
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3\r
+\r
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER\r
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER\r
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER\r
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER\r
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER\r
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER\r
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER\r
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER\r
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER\r
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER\r
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER\r
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER\r
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER\r
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER\r
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER\r
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER\r
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER\r
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER\r
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER\r
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER\r
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER\r
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER\r
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER\r
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER\r
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER\r
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS\r
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS\r
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS\r
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS\r
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE\r
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE\r
+\r
+#define CR_HSION_BB            RCC_CR_HSION_BB\r
+#define CR_CSSON_BB            RCC_CR_CSSON_BB\r
+#define CR_PLLON_BB            RCC_CR_PLLON_BB\r
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB\r
+#define CR_MSION_BB            RCC_CR_MSION_BB\r
+#define CSR_LSION_BB           RCC_CSR_LSION_BB\r
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB\r
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB\r
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB\r
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB\r
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB\r
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB\r
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB\r
+#define CR_HSEON_BB            RCC_CR_HSEON_BB\r
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB\r
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB\r
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB\r
+\r
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r
+\r
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT\r
+\r
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN\r
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF\r
+\r
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48\r
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ\r
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP\r
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ\r
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE\r
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48\r
+\r
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET\r
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r
+#define DfsdmClockSelection         Dfsdm1ClockSelection\r
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1\r
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK\r
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG\r
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE\r
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1\r
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1\r
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1\r
+\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2\r
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1\r
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2\r
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2\r
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)\r
+#else\r
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG\r
+#endif\r
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT\r
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT\r
+\r
+#if defined (STM32F1)\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
+                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \\r
+                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
+#endif   /* STM32F1 */\r
+\r
+#define IS_ALARM                                  IS_RTC_ALARM\r
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK\r
+#define IS_TAMPER                                 IS_RTC_TAMPER\r
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE\r
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER\r
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT\r
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE\r
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION\r
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE\r
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ\r
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER\r
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK\r
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER\r
+\r
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE\r
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE\r
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS\r
+\r
+#if defined(STM32F4) || defined(STM32F2)\r
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED\r
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY\r
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED\r
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION\r
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND\r
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT\r
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED\r
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE\r
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE\r
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE\r
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL\r
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT\r
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT\r
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG\r
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG\r
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT\r
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT\r
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS\r
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT\r
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND\r
+/* alias CMSIS */\r
+#define  SDMMC1_IRQn                SDIO_IRQn\r
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED\r
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY\r
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED\r
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION\r
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND\r
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT\r
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED\r
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE\r
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE\r
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE\r
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE\r
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT\r
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT\r
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG\r
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG\r
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT\r
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT\r
+#define  SDIO_STATIC_FLAGS             SDMMC_STATIC_FLAGS\r
+#define  SDIO_CMD0TIMEOUT                SDMMC_CMD0TIMEOUT\r
+#define  SD_SDIO_SEND_IF_COND        SD_SDMMC_SEND_IF_COND\r
+/* alias CMSIS for compatibilities */\r
+#define  SDIO_IRQn                  SDMMC1_IRQn\r
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)\r
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef\r
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef\r
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef\r
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback\r
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback\r
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback\r
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback\r
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback\r
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback\r
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback\r
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback\r
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT\r
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT\r
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE\r
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE\r
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
+\r
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE\r
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE\r
+\r
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1\r
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2\r
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START\r
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH\r
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR\r
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE\r
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE\r
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX\r
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX\r
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE\r
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION\r
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE\r
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION\r
+\r
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD\r
+\r
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE\r
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT\r
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT\r
+#define __USART_ENABLE                  __HAL_USART_ENABLE\r
+#define __USART_DISABLE                 __HAL_USART_DISABLE\r
+\r
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE\r
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE\r
+\r
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE\r
+\r
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE\r
+\r
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+\r
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup\r
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup\r
+\r
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo\r
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE\r
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
+\r
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE\r
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT\r
+\r
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE\r
+\r
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN\r
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER\r
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER\r
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER\r
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD\r
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD\r
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION\r
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION\r
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER\r
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER\r
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE\r
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE\r
+\r
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
+\r
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE\r
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE\r
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define __HAL_LTDC_LAYER LTDC_LAYER\r
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE\r
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE\r
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE\r
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE\r
+#define SAI_STREOMODE                     SAI_STEREOMODE\r
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY\r
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL\r
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL\r
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL\r
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL\r
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL\r
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE\r
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1\r
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#if defined(STM32H7)\r
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow\r
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT\r
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose\r
+  * @{\r
+  */\r
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)\r
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT\r
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA\r
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart\r
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT\r
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA\r
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+#if defined (STM32L4)\r
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32_HAL_LEGACY */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h
new file mode 100644 (file)
index 0000000..b0eca91
--- /dev/null
@@ -0,0 +1,701 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal.h\r
+  * @author  MCD Application Team\r
+  * @brief   This file contains all the functions prototypes for the HAL\r
+  *          module driver.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_H\r
+#define STM32L4xx_HAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_conf.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup HAL\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Constants HAL Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup HAL_TICK_FREQ Tick Frequency\r
+  * @{\r
+  */\r
+#define  HAL_TICK_FREQ_10HZ         100U\r
+#define  HAL_TICK_FREQ_100HZ        10U\r
+#define  HAL_TICK_FREQ_1KHZ         1U\r
+#define  HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SYSCFG_BootMode Boot Mode\r
+  * @{\r
+  */\r
+#define SYSCFG_BOOT_MAINFLASH          0U\r
+#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
+       /* STM32L496xx || STM32L4A6xx || */\r
+       /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define SYSCFG_BOOT_OCTOPSPI1          (SYSCFG_MEMRMP_MEM_MODE_2)\r
+#define SYSCFG_BOOT_OCTOPSPI2          (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0)\r
+#else\r
+#define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts\r
+  * @{\r
+  */\r
+#define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */\r
+#define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */\r
+#define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */\r
+#define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */\r
+#define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */\r
+#define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)\r
+  * @{\r
+  */\r
+#define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */\r
+#define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */\r
+#define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */\r
+#define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */\r
+#define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */\r
+#define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */\r
+#define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */\r
+#define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */\r
+#define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */\r
+#define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */\r
+#define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */\r
+#define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */\r
+#define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */\r
+#define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */\r
+#define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */\r
+#define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */\r
+#if defined(SYSCFG_SWPR_PAGE31)\r
+#define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */\r
+#define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */\r
+#define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */\r
+#define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */\r
+#define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */\r
+#define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */\r
+#define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */\r
+#define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */\r
+#define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */\r
+#define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */\r
+#define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */\r
+#define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */\r
+#define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */\r
+#define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */\r
+#define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */\r
+#define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */\r
+#endif /* SYSCFG_SWPR_PAGE31 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(SYSCFG_SWPR2_PAGE63)\r
+/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)\r
+  * @{\r
+  */\r
+#define SYSCFG_SRAM2WRP_PAGE32         SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */\r
+#define SYSCFG_SRAM2WRP_PAGE33         SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */\r
+#define SYSCFG_SRAM2WRP_PAGE34         SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */\r
+#define SYSCFG_SRAM2WRP_PAGE35         SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */\r
+#define SYSCFG_SRAM2WRP_PAGE36         SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */\r
+#define SYSCFG_SRAM2WRP_PAGE37         SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */\r
+#define SYSCFG_SRAM2WRP_PAGE38         SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */\r
+#define SYSCFG_SRAM2WRP_PAGE39         SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */\r
+#define SYSCFG_SRAM2WRP_PAGE40         SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */\r
+#define SYSCFG_SRAM2WRP_PAGE41         SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */\r
+#define SYSCFG_SRAM2WRP_PAGE42         SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */\r
+#define SYSCFG_SRAM2WRP_PAGE43         SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */\r
+#define SYSCFG_SRAM2WRP_PAGE44         SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */\r
+#define SYSCFG_SRAM2WRP_PAGE45         SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */\r
+#define SYSCFG_SRAM2WRP_PAGE46         SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */\r
+#define SYSCFG_SRAM2WRP_PAGE47         SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */\r
+#define SYSCFG_SRAM2WRP_PAGE48         SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */\r
+#define SYSCFG_SRAM2WRP_PAGE49         SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */\r
+#define SYSCFG_SRAM2WRP_PAGE50         SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */\r
+#define SYSCFG_SRAM2WRP_PAGE51         SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */\r
+#define SYSCFG_SRAM2WRP_PAGE52         SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */\r
+#define SYSCFG_SRAM2WRP_PAGE53         SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */\r
+#define SYSCFG_SRAM2WRP_PAGE54         SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */\r
+#define SYSCFG_SRAM2WRP_PAGE55         SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */\r
+#define SYSCFG_SRAM2WRP_PAGE56         SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */\r
+#define SYSCFG_SRAM2WRP_PAGE57         SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */\r
+#define SYSCFG_SRAM2WRP_PAGE58         SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */\r
+#define SYSCFG_SRAM2WRP_PAGE59         SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */\r
+#define SYSCFG_SRAM2WRP_PAGE60         SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */\r
+#define SYSCFG_SRAM2WRP_PAGE61         SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */\r
+#define SYSCFG_SRAM2WRP_PAGE62         SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */\r
+#define SYSCFG_SRAM2WRP_PAGE63         SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* SYSCFG_SWPR2_PAGE63 */\r
+\r
+#if defined(VREFBUF)\r
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale\r
+  * @{\r
+  */\r
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0U               /*!< Voltage reference scale 0 (VREF_OUT1) */\r
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS  /*!< Voltage reference scale 1 (VREF_OUT2) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance\r
+  * @{\r
+  */\r
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0U               /*!< VREF_plus pin is internally connected to Voltage reference buffer output */\r
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ  /*!< VREF_plus pin is high impedance */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* VREFBUF */\r
+\r
+/** @defgroup SYSCFG_flags_definition Flags\r
+  * @{\r
+  */\r
+\r
+#define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */\r
+#define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO\r
+  * @{\r
+  */\r
+\r
+/** @brief  Fast-mode Plus driving capability on a specific GPIO\r
+  */\r
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */\r
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */\r
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)\r
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */\r
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */\r
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)\r
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */\r
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode\r
+  */\r
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
+#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
+#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
+#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
+#define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
+#define __HAL_DBGMCU_FREEZE_CAN2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_CAN2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
+#endif\r
+\r
+#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Main Flash memory mapped at 0x00000000.\r
+  */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
+\r
+/** @brief  System Flash memory mapped at 0x00000000.\r
+  */\r
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)\r
+\r
+/** @brief  Embedded SRAM mapped at 0x00000000.\r
+  */\r
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+\r
+/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.\r
+  */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)\r
+\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
+       /* STM32L496xx || STM32L4A6xx || */\r
+       /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+\r
+/** @brief  OCTOSPI mapped at 0x00000000.\r
+  */\r
+#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1()    MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2))\r
+#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2()    MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0))\r
+\r
+#else\r
+\r
+/** @brief  QUADSPI mapped at 0x00000000.\r
+  */\r
+#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/**\r
+  * @brief  Return the boot mode as configured by user.\r
+  * @retval The boot mode as configured by user. The returned value can be one\r
+  *         of the following values:\r
+  *           @arg @ref SYSCFG_BOOT_MAINFLASH\r
+  *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH\r
+  @if STM32L486xx\r
+  *           @arg @ref SYSCFG_BOOT_FMC\r
+  @endif\r
+  *           @arg @ref SYSCFG_BOOT_SRAM\r
+  *           @arg @ref SYSCFG_BOOT_QUADSPI\r
+  */\r
+#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
+\r
+/** @brief  SRAM2 page 0 to 31 write protection enable macro\r
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP\r
+  * @note   Write protection can only be disabled by a system reset\r
+  */\r
+#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\\r
+                                                                SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\\r
+                                                            }while(0)\r
+\r
+#if defined(SYSCFG_SWPR2_PAGE63)\r
+/** @brief  SRAM2 page 32 to 63 write protection enable macro\r
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63\r
+  * @note   Write protection can only be disabled by a system reset\r
+  */\r
+#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\\r
+                                                                SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\\r
+                                                            }while(0)\r
+#endif /* SYSCFG_SWPR2_PAGE63 */\r
+\r
+/** @brief  SRAM2 page write protection unlock prior to erase\r
+  * @note   Writing a wrong key reactivates the write protection\r
+  */\r
+#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\\r
+                                                 SYSCFG->SKR = 0x53;\\r
+                                                }while(0)\r
+\r
+/** @brief  SRAM2 erase\r
+  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase\r
+  */\r
+#define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)\r
+\r
+/** @brief  Floating Point Unit interrupt enable/disable macros\r
+  * @param __INTERRUPT__  This parameter can be a value of @ref SYSCFG_FPU_Interrupts\r
+  */\r
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\\r
+                                                                SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\\r
+                                                            }while(0)\r
+\r
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\\r
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\\r
+                                                            }while(0)\r
+\r
+/** @brief  SYSCFG Break ECC lock.\r
+  *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.\r
+  * @note   The selected configuration is locked and can be unlocked only by system reset.\r
+  */\r
+#define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)\r
+\r
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.\r
+  *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.\r
+  * @note   The selected configuration is locked and can be unlocked only by system reset.\r
+  */\r
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)\r
+\r
+/** @brief  SYSCFG Break PVD lock.\r
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.\r
+  * @note   The selected configuration is locked and can be unlocked only by system reset.\r
+  */\r
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)\r
+\r
+/** @brief  SYSCFG Break SRAM2 parity lock.\r
+  *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.\r
+  * @note   The selected configuration is locked and can be unlocked by system reset.\r
+  */\r
+#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)\r
+\r
+/** @brief  Check SYSCFG flag is set or not.\r
+  * @param  __FLAG__  specifies the flag to check.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag\r
+  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing\r
+  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)\r
+\r
+/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.\r
+  */\r
+#define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)\r
+\r
+/** @brief  Fast-mode Plus driving capability enable/disable macros\r
+  * @param __FASTMODEPLUS__  This parameter can be a value of :\r
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6\r
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7\r
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8\r
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9\r
+  */\r
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\\r
+                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\\r
+                                                               }while(0)\r
+\r
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\\r
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\\r
+                                                               }while(0)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup HAL_Private_Macros HAL Private Macros\r
+  * @{\r
+  */\r
+\r
+#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ)  || \\r
+                               ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \\r
+                               ((__FREQ__) == HAL_TICK_FREQ_1KHZ))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros\r
+  * @{\r
+  */\r
+\r
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \\r
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \\r
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \\r
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \\r
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \\r
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))\r
+\r
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \\r
+                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \\r
+                                            ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \\r
+                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))\r
+\r
+#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))\r
+\r
+#if defined(VREFBUF)\r
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \\r
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))\r
+\r
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \\r
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))\r
+\r
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))\r
+#endif /* VREFBUF */\r
+\r
+#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)\r
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))\r
+#elif defined(SYSCFG_FASTMODEPLUS_PB8)\r
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))\r
+#elif defined(SYSCFG_FASTMODEPLUS_PB9)\r
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))\r
+#else\r
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+\r
+/** @addtogroup HAL_Exported_Variables\r
+  * @{\r
+  */\r
+extern __IO uint32_t uwTick;\r
+extern uint32_t uwTickPrio;\r
+extern uint32_t uwTickFreq;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup HAL_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+\r
+/* Initialization and de-initialization functions  ******************************/\r
+HAL_StatusTypeDef HAL_Init(void);\r
+HAL_StatusTypeDef HAL_DeInit(void);\r
+void              HAL_MspInit(void);\r
+void              HAL_MspDeInit(void);\r
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+\r
+/* Peripheral Control functions  ************************************************/\r
+void               HAL_IncTick(void);\r
+void               HAL_Delay(uint32_t Delay);\r
+uint32_t           HAL_GetTick(void);\r
+uint32_t           HAL_GetTickPrio(void);\r
+HAL_StatusTypeDef  HAL_SetTickFreq(uint32_t Freq);\r
+uint32_t           HAL_GetTickFreq(void);\r
+void               HAL_SuspendTick(void);\r
+void               HAL_ResumeTick(void);\r
+uint32_t           HAL_GetHalVersion(void);\r
+uint32_t           HAL_GetREVID(void);\r
+uint32_t           HAL_GetDEVID(void);\r
+uint32_t           HAL_GetUIDw0(void);\r
+uint32_t           HAL_GetUIDw1(void);\r
+uint32_t           HAL_GetUIDw2(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group3\r
+  * @{\r
+  */\r
+\r
+/* DBGMCU Peripheral Control functions  *****************************************/\r
+void              HAL_DBGMCU_EnableDBGSleepMode(void);\r
+void              HAL_DBGMCU_DisableDBGSleepMode(void);\r
+void              HAL_DBGMCU_EnableDBGStopMode(void);\r
+void              HAL_DBGMCU_DisableDBGStopMode(void);\r
+void              HAL_DBGMCU_EnableDBGStandbyMode(void);\r
+void              HAL_DBGMCU_DisableDBGStandbyMode(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group4\r
+  * @{\r
+  */\r
+\r
+/* SYSCFG Control functions  ****************************************************/\r
+void              HAL_SYSCFG_SRAM2Erase(void);\r
+void              HAL_SYSCFG_EnableMemorySwappingBank(void);\r
+void              HAL_SYSCFG_DisableMemorySwappingBank(void);\r
+\r
+#if defined(VREFBUF)\r
+void              HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);\r
+void              HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);\r
+void              HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);\r
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);\r
+void              HAL_SYSCFG_DisableVREFBUF(void);\r
+#endif /* VREFBUF */\r
+\r
+void              HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);\r
+void              HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
new file mode 100644 (file)
index 0000000..af333b8
--- /dev/null
@@ -0,0 +1,417 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_cortex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of CORTEX HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_CORTEX_H\r
+#define __STM32L4xx_HAL_CORTEX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup CORTEX CORTEX\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types\r
+  * @{\r
+  */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
+  * @{\r
+  */\r
+typedef struct\r
+{\r
+  uint8_t                Enable;                /*!< Specifies the status of the region.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */\r
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */\r
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */\r
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */\r
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.\r
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */\r
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */\r
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */\r
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */\r
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */\r
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */\r
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.\r
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */\r
+}MPU_Region_InitTypeDef;\r
+/**\r
+  * @}\r
+  */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r
+  * @{\r
+  */\r
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,\r
+                                                                 4 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,\r
+                                                                 3 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,\r
+                                                                 2 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,\r
+                                                                 1 bit  for subpriority */\r
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,\r
+                                                                 0 bit  for subpriority */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source\r
+  * @{\r
+  */\r
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)\r
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control\r
+  * @{\r
+  */\r
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)\r
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)\r
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)\r
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
+  * @{\r
+  */\r
+#define  MPU_REGION_ENABLE           ((uint8_t)0x01)\r
+#define  MPU_REGION_DISABLE          ((uint8_t)0x00)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
+  * @{\r
+  */\r
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)\r
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
+  * @{\r
+  */\r
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)\r
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
+  * @{\r
+  */\r
+#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)\r
+#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
+  * @{\r
+  */\r
+#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)\r
+#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels\r
+  * @{\r
+  */\r
+#define  MPU_TEX_LEVEL0              ((uint8_t)0x00)\r
+#define  MPU_TEX_LEVEL1              ((uint8_t)0x01)\r
+#define  MPU_TEX_LEVEL2              ((uint8_t)0x02)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
+  * @{\r
+  */\r
+#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)\r
+#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)\r
+#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)\r
+#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)\r
+#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)\r
+#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)\r
+#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)\r
+#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)\r
+#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)\r
+#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)\r
+#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)\r
+#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)\r
+#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)\r
+#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)\r
+#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)\r
+#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)\r
+#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)\r
+#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)\r
+#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)\r
+#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)\r
+#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)\r
+#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)\r
+#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)\r
+#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)\r
+#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)\r
+#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)\r
+#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)\r
+#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes\r
+  * @{\r
+  */\r
+#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)\r
+#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)\r
+#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)\r
+#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)\r
+#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)\r
+#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
+  * @{\r
+  */\r
+#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)\r
+#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)\r
+#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)\r
+#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)\r
+#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)\r
+#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)\r
+#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)\r
+#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)\r
+/**\r
+  * @}\r
+  */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions\r
+  * @brief    Initialization and Configuration functions\r
+  * @{\r
+  */\r
+/* Initialization and Configuration functions *****************************/\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SystemReset(void);\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
+  * @brief   Cortex control functions\r
+  * @{\r
+  */\r
+/* Peripheral Control functions ***********************************************/\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
+void HAL_SYSTICK_IRQHandler(void);\r
+void HAL_SYSTICK_Callback(void);\r
+\r
+#if (__MPU_PRESENT == 1)\r
+void HAL_MPU_Enable(uint32_t MPU_Control);\r
+void HAL_MPU_Disable(void);\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
+#endif /* __MPU_PRESENT */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
+  * @{\r
+  */\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)\r
+\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
+\r
+#if (__MPU_PRESENT == 1)\r
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
+                                     ((STATE) == MPU_REGION_DISABLE))\r
+\r
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
+\r
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
+\r
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
+\r
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
+\r
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \\r
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \\r
+                                ((TYPE) == MPU_TEX_LEVEL2))\r
+\r
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \\r
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \\r
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \\r
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
+\r
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \\r
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \\r
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \\r
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \\r
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \\r
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \\r
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \\r
+                                         ((NUMBER) == MPU_REGION_NUMBER7))\r
+\r
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \\r
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))\r
+\r
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_CORTEX_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
new file mode 100644 (file)
index 0000000..e96526d
--- /dev/null
@@ -0,0 +1,197 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_def.h\r
+  * @author  MCD Application Team\r
+  * @brief   This file contains HAL common defines, enumeration, macros and\r
+  *          structures definitions.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_DEF_H\r
+#define STM32L4xx_HAL_DEF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx.h"\r
+#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */\r
+#include <stddef.h>\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/**\r
+  * @brief  HAL Status structures definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_OK       = 0x00,\r
+  HAL_ERROR    = 0x01,\r
+  HAL_BUSY     = 0x02,\r
+  HAL_TIMEOUT  = 0x03\r
+} HAL_StatusTypeDef;\r
+\r
+/**\r
+  * @brief  HAL Lock structures definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_UNLOCKED = 0x00,\r
+  HAL_LOCKED   = 0x01\r
+} HAL_LockTypeDef;\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */\r
+\r
+#define HAL_MAX_DELAY      0xFFFFFFFFU\r
+\r
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))\r
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)\r
+\r
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \\r
+                        do{                                                      \\r
+                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\r
+                            (__DMA_HANDLE__).Parent = (__HANDLE__);              \\r
+                        } while(0)\r
+\r
+/** @brief Reset the Handle's State field.\r
+  * @param __HANDLE__: specifies the Peripheral Handle.\r
+  * @note  This macro can be used for the following purpose:\r
+  *          - When the Handle is declared as local variable; before passing it as parameter\r
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro\r
+  *            to set to 0 the Handle's "State" field.\r
+  *            Otherwise, "State" field may have any random value and the first time the function\r
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
+  *            (i.e. HAL_PPP_MspInit() will not be executed).\r
+  *          - When there is a need to reconfigure the low level hardware: instead of calling\r
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
+  * @retval None\r
+  */\r
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)\r
+\r
+#if (USE_RTOS == 1)\r
+  /* Reserved for future use */\r
+  #error " USE_RTOS should be 0 in the current HAL release "\r
+#else\r
+  #define __HAL_LOCK(__HANDLE__)                                           \\r
+                                do{                                        \\r
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\r
+                                    {                                      \\r
+                                       return HAL_BUSY;                    \\r
+                                    }                                      \\r
+                                    else                                   \\r
+                                    {                                      \\r
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\r
+                                    }                                      \\r
+                                  }while (0)\r
+\r
+  #define __HAL_UNLOCK(__HANDLE__)                                          \\r
+                                  do{                                       \\r
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\r
+                                    }while (0)\r
+#endif /* USE_RTOS */\r
+\r
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
+  #ifndef __weak\r
+    #define __weak   __attribute__((weak))\r
+  #endif /* __weak */\r
+  #ifndef __packed\r
+    #define __packed __attribute__((__packed__))\r
+  #endif /* __packed */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
+  #ifndef __ALIGN_END\r
+    #define __ALIGN_END    __attribute__ ((aligned (4)))\r
+  #endif /* __ALIGN_END */\r
+  #ifndef __ALIGN_BEGIN\r
+    #define __ALIGN_BEGIN\r
+  #endif /* __ALIGN_BEGIN */\r
+#else\r
+  #ifndef __ALIGN_END\r
+    #define __ALIGN_END\r
+  #endif /* __ALIGN_END */\r
+  #ifndef __ALIGN_BEGIN\r
+    #if defined   (__CC_ARM)      /* ARM Compiler */\r
+      #define __ALIGN_BEGIN    __align(4)\r
+    #elif defined (__ICCARM__)    /* IAR Compiler */\r
+      #define __ALIGN_BEGIN\r
+    #endif /* __CC_ARM */\r
+  #endif /* __ALIGN_BEGIN */\r
+#endif /* __GNUC__ */\r
+\r
+/**\r
+  * @brief  __RAM_FUNC definition\r
+  */\r
+#if defined ( __CC_ARM   )\r
+/* ARM Compiler\r
+   ------------\r
+   RAM functions are defined using the toolchain options.\r
+   Functions that are executed in RAM should reside in a separate source module.\r
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'\r
+   area of a module to a memory space in physical RAM.\r
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
+   dialog.\r
+*/\r
+#define __RAM_FUNC HAL_StatusTypeDef\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+   ---------------\r
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
+*/\r
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef\r
+\r
+#elif defined   (  __GNUC__  )\r
+/* GNU Compiler\r
+   ------------\r
+  RAM functions are defined using a specific toolchain attribute\r
+   "__attribute__((section(".RamFunc")))".\r
+*/\r
+#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))\r
+\r
+#endif\r
+\r
+/**\r
+  * @brief  __NOINLINE definition\r
+  */\r
+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )\r
+/* ARM & GNUCompiler\r
+   ----------------\r
+*/\r
+#define __NOINLINE __attribute__ ( (noinline) )\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+   ---------------\r
+*/\r
+#define __NOINLINE _Pragma("optimize = no_inline")\r
+\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_DEF_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h
new file mode 100644 (file)
index 0000000..50ce0b2
--- /dev/null
@@ -0,0 +1,887 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_dfsdm.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of DFSDM HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_DFSDM_H\r
+#define STM32L4xx_HAL_DFSDM_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
+    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup DFSDM\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  HAL DFSDM Channel states definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */\r
+  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */\r
+  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */\r
+} HAL_DFSDM_Channel_StateTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM channel output clock structure definition\r
+  */\r
+typedef struct\r
+{\r
+  FunctionalState Activation; /*!< Output clock enable/disable */\r
+  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.\r
+                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */\r
+  uint32_t        Divider;    /*!< Output clock divider.\r
+                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */\r
+} DFSDM_Channel_OutputClockTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM channel input structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.\r
+                             ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,\r
+                             STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx,\r
+                             STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products.\r
+                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */\r
+  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.\r
+                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */\r
+  uint32_t Pins;        /*!< Input pins are taken from same or following channel.\r
+                             This parameter can be a value of @ref DFSDM_Channel_InputPins */\r
+} DFSDM_Channel_InputTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM channel serial interface structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Type;     /*!< SPI or Manchester modes.\r
+                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */\r
+  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).\r
+                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */\r
+} DFSDM_Channel_SerialInterfaceTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM channel analog watchdog structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.\r
+                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */\r
+  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.\r
+                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
+} DFSDM_Channel_AwdTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM channel init structure definition\r
+  */\r
+typedef struct\r
+{\r
+  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */\r
+  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */\r
+  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */\r
+  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */\r
+  int32_t                              Offset;          /*!< DFSDM channel offset.\r
+                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
+  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.\r
+                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
+} DFSDM_Channel_InitTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM channel handle structure definition\r
+  */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+typedef struct __DFSDM_Channel_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
+{\r
+  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */\r
+  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */\r
+  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);       /*!< DFSDM channel clock absence detection callback */\r
+  void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);        /*!< DFSDM channel short circuit detection callback */\r
+  void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);    /*!< DFSDM channel MSP init callback */\r
+  void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);  /*!< DFSDM channel MSP de-init callback */\r
+#endif\r
+} DFSDM_Channel_HandleTypeDef;\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  DFSDM channel callback ID enumeration definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_DFSDM_CHANNEL_CKAB_CB_ID      = 0x00U, /*!< DFSDM channel clock absence detection callback ID */\r
+  HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U, /*!< DFSDM channel short circuit detection callback ID */\r
+  HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U, /*!< DFSDM channel MSP init callback ID */\r
+  HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U  /*!< DFSDM channel MSP de-init callback ID */\r
+} HAL_DFSDM_Channel_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM channel callback pointer definition\r
+  */\r
+typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+#endif\r
+\r
+/**\r
+  * @brief  HAL DFSDM Filter states definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */\r
+  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */\r
+  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */\r
+  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */\r
+  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */\r
+  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */\r
+} HAL_DFSDM_Filter_StateTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM filter regular conversion parameters structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.\r
+                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
+  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */\r
+  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */\r
+} DFSDM_Filter_RegularParamTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM filter injected conversion parameters structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.\r
+                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
+  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */\r
+  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */\r
+  uint32_t        ExtTrigger;     /*!< External trigger.\r
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */\r
+  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.\r
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */\r
+} DFSDM_Filter_InjectedParamTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM filter parameters structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t SincOrder;       /*!< Sinc filter order.\r
+                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */\r
+  uint32_t Oversampling;    /*!< Filter oversampling ratio.\r
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */\r
+  uint32_t IntOversampling; /*!< Integrator oversampling ratio.\r
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */\r
+} DFSDM_Filter_FilterParamTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM filter init structure definition\r
+  */\r
+typedef struct\r
+{\r
+  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */\r
+  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */\r
+  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */\r
+} DFSDM_Filter_InitTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM filter handle structure definition\r
+  */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+typedef struct __DFSDM_Filter_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
+{\r
+  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */\r
+  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */\r
+  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */\r
+  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */\r
+  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */\r
+  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */\r
+  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */\r
+  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */\r
+  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */\r
+  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */\r
+  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */\r
+  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */\r
+  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                      uint32_t Channel, uint32_t Threshold);                            /*!< DFSDM filter analog watchdog callback */\r
+  void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter regular conversion complete callback */\r
+  void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half regular conversion complete callback */\r
+  void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter injected conversion complete callback */\r
+  void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half injected conversion complete callback */\r
+  void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);            /*!< DFSDM filter error callback */\r
+  void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);          /*!< DFSDM filter MSP init callback */\r
+  void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);        /*!< DFSDM filter MSP de-init callback */\r
+#endif\r
+} DFSDM_Filter_HandleTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM filter analog watchdog parameters structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.\r
+                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */\r
+  uint32_t Channel;         /*!< Analog watchdog channel selection.\r
+                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */\r
+  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.\r
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
+  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.\r
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
+  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.\r
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
+  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.\r
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
+} DFSDM_Filter_AwdParamTypeDef;\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  DFSDM filter callback ID enumeration definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID     = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */\r
+  HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */\r
+  HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID     = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */\r
+  HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */\r
+  HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U, /*!< DFSDM filter error callback ID */\r
+  HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U, /*!< DFSDM filter MSP init callback ID */\r
+  HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U  /*!< DFSDM filter MSP de-init callback ID */\r
+} HAL_DFSDM_Filter_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  DFSDM filter callback pointer definition\r
+  */\r
+typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection\r
+  * @{\r
+  */\r
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U             /*!< Source for ouput clock is system clock */\r
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer\r
+  * @{\r
+  */\r
+#define DFSDM_CHANNEL_EXTERNAL_INPUTS    0x00000000U             /*!< Data are taken from external inputs */\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
+    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing\r
+  * @{\r
+  */\r
+#define DFSDM_CHANNEL_STANDARD_MODE         0x00000000U             /*!< Standard data packing mode */\r
+#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */\r
+#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins\r
+  * @{\r
+  */\r
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U             /*!< Input from pins on same channel */\r
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type\r
+  * @{\r
+  */\r
+#define DFSDM_CHANNEL_SPI_RISING         0x00000000U             /*!< SPI with rising edge */\r
+#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */\r
+#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */\r
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection\r
+  * @{\r
+  */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U              /*!< External SPI clock */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order\r
+  * @{\r
+  */\r
+#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U             /*!< FastSinc filter type */\r
+#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */\r
+#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */\r
+#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger\r
+  * @{\r
+  */\r
+#define DFSDM_FILTER_SW_TRIGGER   0x00000000U /*!< Software trigger */\r
+#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */\r
+#define DFSDM_FILTER_EXT_TRIGGER  0x00000002U /*!< External trigger (only for injected conversion) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger\r
+  * @{\r
+  */\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \\r
+                                          DFSDM_FLTCR1_JEXTSEL_2)                          /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  DFSDM_FLTCR1_JEXTSEL_3                            /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
+                                          DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
+                                          DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */\r
+#else\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 0, 1 and 2 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge\r
+  * @{\r
+  */\r
+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */\r
+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */\r
+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order\r
+  * @{\r
+  */\r
+#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                                 /*!< FastSinc filter type */\r
+#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */\r
+#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */\r
+#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */\r
+#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */\r
+#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source\r
+  * @{\r
+  */\r
+#define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U             /*!< From digital filter */\r
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code\r
+  * @{\r
+  */\r
+#define DFSDM_FILTER_ERROR_NONE             0x00000000U /*!< No error */\r
+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U /*!< Overrun occurs during regular conversion */\r
+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */\r
+#define DFSDM_FILTER_ERROR_DMA              0x00000003U /*!< DMA error occurs */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_BreakSignals DFSDM break signals\r
+  * @{\r
+  */\r
+#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */\r
+#define DFSDM_BREAK_SIGNAL_0  0x00000001U /*!< Break signal 0 */\r
+#define DFSDM_BREAK_SIGNAL_1  0x00000002U /*!< Break signal 1 */\r
+#define DFSDM_BREAK_SIGNAL_2  0x00000004U /*!< Break signal 2 */\r
+#define DFSDM_BREAK_SIGNAL_3  0x00000008U /*!< Break signal 3 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection\r
+  * @{\r
+  */\r
+/* DFSDM Channels ------------------------------------------------------------*/\r
+/* The DFSDM channels are defined as follows:\r
+   - in 16-bit LSB the channel mask is set\r
+   - in 16-bit MSB the channel number is set\r
+   e.g. for channel 5 definition:\r
+        - the channel mask is 0x00000020 (bit 5 is set)\r
+        - the channel number 5 is 0x00050000\r
+        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define DFSDM_CHANNEL_0                              0x00000001U\r
+#define DFSDM_CHANNEL_1                              0x00010002U\r
+#define DFSDM_CHANNEL_2                              0x00020004U\r
+#define DFSDM_CHANNEL_3                              0x00030008U\r
+#else\r
+#define DFSDM_CHANNEL_0                              0x00000001U\r
+#define DFSDM_CHANNEL_1                              0x00010002U\r
+#define DFSDM_CHANNEL_2                              0x00020004U\r
+#define DFSDM_CHANNEL_3                              0x00030008U\r
+#define DFSDM_CHANNEL_4                              0x00040010U\r
+#define DFSDM_CHANNEL_5                              0x00050020U\r
+#define DFSDM_CHANNEL_6                              0x00060040U\r
+#define DFSDM_CHANNEL_7                              0x00070080U\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode\r
+  * @{\r
+  */\r
+#define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U /*!< Conversion are not continuous */\r
+#define DFSDM_CONTINUOUS_CONV_ON             0x00000001U /*!< Conversion are continuous */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold\r
+  * @{\r
+  */\r
+#define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U /*!< Analog watchdog high threshold */\r
+#define DFSDM_AWD_LOW_THRESHOLD             0x00000001U /*!< Analog watchdog low threshold */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief  Reset DFSDM channel handle state.\r
+  * @param  __HANDLE__ DFSDM channel handle.\r
+  * @retval None\r
+  */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \\r
+                                                               (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \\r
+                                                               (__HANDLE__)->MspInitCallback = NULL;                \\r
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;              \\r
+                                                             } while(0)\r
+#else\r
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)\r
+#endif\r
+\r
+/** @brief  Reset DFSDM filter handle state.\r
+  * @param  __HANDLE__ DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \\r
+                                                              (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \\r
+                                                              (__HANDLE__)->MspInitCallback = NULL;               \\r
+                                                              (__HANDLE__)->MspDeInitCallback = NULL;             \\r
+                                                            } while(0)\r
+#else\r
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported macros ----------------------------------------------------*/\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+/* Include DFSDM HAL Extension module */\r
+#include "stm32l4xx_hal_dfsdm_ex.h"\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r
+  * @{\r
+  */\r
+/* Channel initialization and de-initialization functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/* Channel callbacks register/unregister functions ****************************/\r
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
+                                                     HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,\r
+                                                     pDFSDM_Channel_CallbackTypeDef      pCallback);\r
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
+                                                       HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r
+  * @{\r
+  */\r
+/* Channel operation functions ************************************************/\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+\r
+int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);\r
+\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
+\r
+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r
+  * @{\r
+  */\r
+/* Channel state function *****************************************************/\r
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r
+  * @{\r
+  */\r
+/* Filter initialization and de-initialization functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/* Filter callbacks register/unregister functions ****************************/\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
+                                                    HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,\r
+                                                    pDFSDM_Filter_CallbackTypeDef      pCallback);\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
+                                                      HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,\r
+                                                       pDFSDM_Filter_AwdCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r
+  * @{\r
+  */\r
+/* Filter control functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                   uint32_t                    Channel,\r
+                                                   uint32_t                    ContinuousMode);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                   uint32_t                    Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r
+  * @{\r
+  */\r
+/* Filter operation functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                              DFSDM_Filter_AwdParamTypeDef *awdParam);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
+\r
+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r
+  * @{\r
+  */\r
+/* Filter state functions *****************************************************/\r
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros\r
+* @{\r
+*/\r
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \\r
+                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))\r
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
+    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
+                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \\r
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
+#else\r
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
+/* STM32L496xx || STM32L4A6xx ||                */\r
+/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \\r
+                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \\r
+                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))\r
+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \\r
+                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))\r
+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \\r
+                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \\r
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \\r
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))\r
+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \\r
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \\r
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \\r
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))\r
+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))\r
+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))\r
+#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)\r
+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)\r
+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))\r
+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
+#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))\r
+#else\r
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \\r
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \\r
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))\r
+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \\r
+                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))\r
+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))\r
+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))\r
+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \\r
+                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))\r
+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
+#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3))\r
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))\r
+#else\r
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \\r
+                                                       ((CHANNEL) == DFSDM_CHANNEL_7))\r
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \\r
+                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))\r
+/**\r
+  * @}\r
+  */\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
+/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
+/* STM32L496xx || STM32L4A6xx || */\r
+/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_DFSDM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
new file mode 100644 (file)
index 0000000..f165a5d
--- /dev/null
@@ -0,0 +1,749 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_dma.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of DMA HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_DMA_H\r
+#define STM32L4xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup DMA\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  DMA Configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.\r
+                                           This parameter can be a value of @ref DMA_request */\r
+\r
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,\r
+                                           from memory to memory or from peripheral to memory.\r
+                                           This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.\r
+                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.\r
+                                           This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.\r
+                                           This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.\r
+                                           This parameter can be a value of @ref DMA_mode\r
+                                           @note The circular buffer mode cannot be used if the memory-to-memory\r
+                                                 data transfer is configured on the selected Channel */\r
+\r
+  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.\r
+                                           This parameter can be a value of @ref DMA_Priority_level */\r
+} DMA_InitTypeDef;\r
+\r
+/**\r
+  * @brief  HAL DMA State structures definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */\r
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */\r
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */\r
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/**\r
+  * @brief  HAL DMA Error Code structure definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */\r
+  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+\r
+/**\r
+  * @brief  HAL DMA Callback ID structure definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */\r
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */\r
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */\r
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */\r
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */\r
+}HAL_DMA_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  DMA handle Structure definition\r
+  */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+  DMA_Channel_TypeDef    *Instance;                                                     /*!< Register base address                */\r
+\r
+  DMA_InitTypeDef       Init;                                                           /*!< DMA communication parameters         */\r
+\r
+  HAL_LockTypeDef       Lock;                                                           /*!< DMA locking object                   */\r
+\r
+  __IO HAL_DMA_StateTypeDef  State;                                                     /*!< DMA transfer state                   */\r
+\r
+  void                  *Parent;                                                        /*!< Parent object state                  */\r
+\r
+  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer complete callback       */\r
+\r
+  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA Half transfer complete callback  */\r
+\r
+  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer error callback          */\r
+\r
+  void                  (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer abort callback          */\r
+\r
+  __IO uint32_t         ErrorCode;                                                      /*!< DMA Error code                       */\r
+\r
+  DMA_TypeDef           *DmaBaseAddress;                                                /*!< DMA Channel Base Address             */\r
+\r
+  uint32_t              ChannelIndex;                                                   /*!< DMA Channel Index                    */\r
+\r
+#if defined(DMAMUX1)\r
+  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                      /*!< Register base address                */\r
+\r
+  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                /*!< DMAMUX Channels Status Base Address  */\r
+\r
+  uint32_t                         DMAmuxChannelStatusMask;                             /*!< DMAMUX Channel Status Mask           */\r
+\r
+  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                   /*!< DMAMUX request generator Base Address */\r
+\r
+  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                             /*!< DMAMUX request generator Address     */\r
+\r
+  uint32_t                         DMAmuxRequestGenStatusMask;                          /*!< DMAMUX request generator Status mask */\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+}DMA_HandleTypeDef;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+  * @{\r
+  */\r
+#define HAL_DMA_ERROR_NONE                 0x00000000U    /*!< No error                                */\r
+#define HAL_DMA_ERROR_TE                   0x00000001U    /*!< Transfer error                          */\r
+#define HAL_DMA_ERROR_NO_XFER              0x00000004U    /*!< Abort requested with no Xfer ongoing    */\r
+#define HAL_DMA_ERROR_TIMEOUT              0x00000020U    /*!< Timeout error                           */\r
+#define HAL_DMA_ERROR_NOT_SUPPORTED        0x00000100U    /*!< Not supported mode                      */\r
+#define HAL_DMA_ERROR_SYNC                 0x00000200U    /*!< DMAMUX sync overrun  error              */\r
+#define HAL_DMA_ERROR_REQGEN               0x00000400U    /*!< DMAMUX request generator overrun  error */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_request DMA request\r
+  * @{\r
+  */\r
+#if !defined (DMAMUX1)\r
+\r
+#define DMA_REQUEST_0                     0U\r
+#define DMA_REQUEST_1                     1U\r
+#define DMA_REQUEST_2                     2U\r
+#define DMA_REQUEST_3                     3U\r
+#define DMA_REQUEST_4                     4U\r
+#define DMA_REQUEST_5                     5U\r
+#define DMA_REQUEST_6                     6U\r
+#define DMA_REQUEST_7                     7U\r
+\r
+#endif\r
+\r
+#if defined(DMAMUX1)\r
+\r
+#define DMA_REQUEST_MEM2MEM                 0U  /*!< memory to memory transfer   */\r
+\r
+#define DMA_REQUEST_GENERATOR0              1U  /*!< DMAMUX1 request generator 0 */\r
+#define DMA_REQUEST_GENERATOR1              2U  /*!< DMAMUX1 request generator 1 */\r
+#define DMA_REQUEST_GENERATOR2              3U  /*!< DMAMUX1 request generator 2 */\r
+#define DMA_REQUEST_GENERATOR3              4U  /*!< DMAMUX1 request generator 3 */\r
+\r
+#define DMA_REQUEST_ADC1                    5U  /*!< DMAMUX1 ADC1 request      */\r
+\r
+#define DMA_REQUEST_DAC1_CH1                6U  /*!< DMAMUX1 DAC1 CH1 request  */\r
+#define DMA_REQUEST_DAC1_CH2                7U  /*!< DMAMUX1 DAC1 CH2 request  */\r
+\r
+#define DMA_REQUEST_TIM6_UP                 8U  /*!< DMAMUX1 TIM6 UP request   */\r
+#define DMA_REQUEST_TIM7_UP                 9U  /*!< DMAMUX1 TIM7 UP request   */\r
+\r
+#define DMA_REQUEST_SPI1_RX                10U  /*!< DMAMUX1 SPI1 RX request   */\r
+#define DMA_REQUEST_SPI1_TX                11U  /*!< DMAMUX1 SPI1 TX request   */\r
+#define DMA_REQUEST_SPI2_RX                12U  /*!< DMAMUX1 SPI2 RX request   */\r
+#define DMA_REQUEST_SPI2_TX                13U  /*!< DMAMUX1 SPI2 TX request   */\r
+#define DMA_REQUEST_SPI3_RX                14U  /*!< DMAMUX1 SPI3 RX request   */\r
+#define DMA_REQUEST_SPI3_TX                15U  /*!< DMAMUX1 SPI3 TX request   */\r
+\r
+#define DMA_REQUEST_I2C1_RX                16U  /*!< DMAMUX1 I2C1 RX request   */\r
+#define DMA_REQUEST_I2C1_TX                17U  /*!< DMAMUX1 I2C1 TX request   */\r
+#define DMA_REQUEST_I2C2_RX                18U  /*!< DMAMUX1 I2C2 RX request   */\r
+#define DMA_REQUEST_I2C2_TX                19U  /*!< DMAMUX1 I2C2 TX request   */\r
+#define DMA_REQUEST_I2C3_RX                20U  /*!< DMAMUX1 I2C3 RX request   */\r
+#define DMA_REQUEST_I2C3_TX                21U  /*!< DMAMUX1 I2C3 TX request   */\r
+#define DMA_REQUEST_I2C4_RX                22U  /*!< DMAMUX1 I2C4 RX request   */\r
+#define DMA_REQUEST_I2C4_TX                23U  /*!< DMAMUX1 I2C4 TX request   */\r
+\r
+#define DMA_REQUEST_USART1_RX              24U  /*!< DMAMUX1 USART1 RX request */\r
+#define DMA_REQUEST_USART1_TX              25U  /*!< DMAMUX1 USART1 TX request */\r
+#define DMA_REQUEST_USART2_RX              26U  /*!< DMAMUX1 USART2 RX request */\r
+#define DMA_REQUEST_USART2_TX              27U  /*!< DMAMUX1 USART2 TX request */\r
+#define DMA_REQUEST_USART3_RX              28U  /*!< DMAMUX1 USART3 RX request */\r
+#define DMA_REQUEST_USART3_TX              29U  /*!< DMAMUX1 USART3 TX request */\r
+\r
+#define DMA_REQUEST_UART4_RX               30U  /*!< DMAMUX1 UART4 RX request  */\r
+#define DMA_REQUEST_UART4_TX               31U  /*!< DMAMUX1 UART4 TX request  */\r
+#define DMA_REQUEST_UART5_RX               32U  /*!< DMAMUX1 UART5 RX request  */\r
+#define DMA_REQUEST_UART5_TX               33U  /*!< DMAMUX1 UART5 TX request  */\r
+\r
+#define DMA_REQUEST_LPUART1_RX             34U  /*!< DMAMUX1 LP_UART1_RX request */\r
+#define DMA_REQUEST_LPUART1_TX             35U  /*!< DMAMUX1 LP_UART1_RX request */\r
+\r
+#define DMA_REQUEST_SAI1_A                 36U  /*!< DMAMUX1 SAI1 A request    */\r
+#define DMA_REQUEST_SAI1_B                 37U  /*!< DMAMUX1 SAI1 B request    */\r
+#define DMA_REQUEST_SAI2_A                 38U  /*!< DMAMUX1 SAI2 A request    */\r
+#define DMA_REQUEST_SAI2_B                 39U  /*!< DMAMUX1 SAI2 B request    */\r
+\r
+#define DMA_REQUEST_OCTOSPI1               40U  /*!< DMAMUX1 OCTOSPI1 request  */\r
+#define DMA_REQUEST_OCTOSPI2               41U  /*!< DMAMUX1 OCTOSPI2 request  */\r
+\r
+#define DMA_REQUEST_TIM1_CH1               42U  /*!< DMAMUX1 TIM1 CH1 request  */\r
+#define DMA_REQUEST_TIM1_CH2               43U  /*!< DMAMUX1 TIM1 CH2 request  */\r
+#define DMA_REQUEST_TIM1_CH3               44U  /*!< DMAMUX1 TIM1 CH3 request  */\r
+#define DMA_REQUEST_TIM1_CH4               45U  /*!< DMAMUX1 TIM1 CH4 request  */\r
+#define DMA_REQUEST_TIM1_UP                46U  /*!< DMAMUX1 TIM1 UP  request  */\r
+#define DMA_REQUEST_TIM1_TRIG              47U  /*!< DMAMUX1 TIM1 TRIG request */\r
+#define DMA_REQUEST_TIM1_COM               48U  /*!< DMAMUX1 TIM1 COM request  */\r
+\r
+#define DMA_REQUEST_TIM8_CH1               49U  /*!< DMAMUX1 TIM8 CH1 request  */\r
+#define DMA_REQUEST_TIM8_CH2               50U  /*!< DMAMUX1 TIM8 CH2 request  */\r
+#define DMA_REQUEST_TIM8_CH3               51U  /*!< DMAMUX1 TIM8 CH3 request  */\r
+#define DMA_REQUEST_TIM8_CH4               52U  /*!< DMAMUX1 TIM8 CH4 request  */\r
+#define DMA_REQUEST_TIM8_UP                53U  /*!< DMAMUX1 TIM8 UP  request  */\r
+#define DMA_REQUEST_TIM8_TRIG              54U  /*!< DMAMUX1 TIM8 TRIG request */\r
+#define DMA_REQUEST_TIM8_COM               55U  /*!< DMAMUX1 TIM8 COM request  */\r
+\r
+#define DMA_REQUEST_TIM2_CH1               56U  /*!< DMAMUX1 TIM2 CH1 request  */\r
+#define DMA_REQUEST_TIM2_CH2               57U  /*!< DMAMUX1 TIM2 CH2 request  */\r
+#define DMA_REQUEST_TIM2_CH3               58U  /*!< DMAMUX1 TIM2 CH3 request  */\r
+#define DMA_REQUEST_TIM2_CH4               59U  /*!< DMAMUX1 TIM2 CH4 request  */\r
+#define DMA_REQUEST_TIM2_UP                60U  /*!< DMAMUX1 TIM2 UP  request  */\r
+\r
+#define DMA_REQUEST_TIM3_CH1               61U  /*!< DMAMUX1 TIM3 CH1 request  */\r
+#define DMA_REQUEST_TIM3_CH2               62U  /*!< DMAMUX1 TIM3 CH2 request  */\r
+#define DMA_REQUEST_TIM3_CH3               63U  /*!< DMAMUX1 TIM3 CH3 request  */\r
+#define DMA_REQUEST_TIM3_CH4               64U  /*!< DMAMUX1 TIM3 CH4 request  */\r
+#define DMA_REQUEST_TIM3_UP                65U  /*!< DMAMUX1 TIM3 UP  request  */\r
+#define DMA_REQUEST_TIM3_TRIG              66U  /*!< DMAMUX1 TIM3 TRIG request */\r
+\r
+#define DMA_REQUEST_TIM4_CH1               67U  /*!< DMAMUX1 TIM4 CH1 request  */\r
+#define DMA_REQUEST_TIM4_CH2               68U  /*!< DMAMUX1 TIM4 CH2 request  */\r
+#define DMA_REQUEST_TIM4_CH3               69U  /*!< DMAMUX1 TIM4 CH3 request  */\r
+#define DMA_REQUEST_TIM4_CH4               70U  /*!< DMAMUX1 TIM4 CH4 request  */\r
+#define DMA_REQUEST_TIM4_UP                71U  /*!< DMAMUX1 TIM4 UP  request  */\r
+\r
+#define DMA_REQUEST_TIM5_CH1               72U  /*!< DMAMUX1 TIM5 CH1 request  */\r
+#define DMA_REQUEST_TIM5_CH2               73U  /*!< DMAMUX1 TIM5 CH2 request  */\r
+#define DMA_REQUEST_TIM5_CH3               74U  /*!< DMAMUX1 TIM5 CH3 request  */\r
+#define DMA_REQUEST_TIM5_CH4               75U  /*!< DMAMUX1 TIM5 CH4 request  */\r
+#define DMA_REQUEST_TIM5_UP                76U  /*!< DMAMUX1 TIM5 UP  request  */\r
+#define DMA_REQUEST_TIM5_TRIG              77U  /*!< DMAMUX1 TIM5 TRIG request */\r
+\r
+#define DMA_REQUEST_TIM15_CH1              78U  /*!< DMAMUX1 TIM15 CH1 request */\r
+#define DMA_REQUEST_TIM15_UP               79U  /*!< DMAMUX1 TIM15 UP  request */\r
+#define DMA_REQUEST_TIM15_TRIG             80U  /*!< DMAMUX1 TIM15 TRIG request */\r
+#define DMA_REQUEST_TIM15_COM              81U  /*!< DMAMUX1 TIM15 COM request */\r
+\r
+#define DMA_REQUEST_TIM16_CH1              82U  /*!< DMAMUX1 TIM16 CH1 request */\r
+#define DMA_REQUEST_TIM16_UP               83U  /*!< DMAMUX1 TIM16 UP  request */\r
+#define DMA_REQUEST_TIM17_CH1              84U  /*!< DMAMUX1 TIM17 CH1 request */\r
+#define DMA_REQUEST_TIM17_UP               85U  /*!< DMAMUX1 TIM17 UP  request */\r
+\r
+#define DMA_REQUEST_DFSDM1_FLT0            86U  /*!< DMAMUX1 DFSDM1 Filter0 request */\r
+#define DMA_REQUEST_DFSDM1_FLT1            87U  /*!< DMAMUX1 DFSDM1 Filter1 request */\r
+#define DMA_REQUEST_DFSDM1_FLT2            88U  /*!< DMAMUX1 DFSDM1 Filter2 request */\r
+#define DMA_REQUEST_DFSDM1_FLT3            89U  /*!< DMAMUX1 DFSDM1 Filter3 request */\r
+\r
+#define DMA_REQUEST_DCMI                   90U  /*!< DMAMUX1 DCMI request      */\r
+\r
+#define DMA_REQUEST_AES_IN                 91U  /*!< DMAMUX1 AES IN request    */\r
+#define DMA_REQUEST_AES_OUT                92U  /*!< DMAMUX1 AES OUT request   */\r
+\r
+#define DMA_REQUEST_HASH_IN                93U  /*!< DMAMUX1 HASH IN request   */\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+  * @{\r
+  */\r
+#define DMA_PERIPH_TO_MEMORY         0x00000000U        /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR        /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM    /*!< Memory to memory direction     */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+  * @{\r
+  */\r
+#define DMA_PINC_ENABLE              DMA_CCR_PINC  /*!< Peripheral increment mode Enable */\r
+#define DMA_PINC_DISABLE             0x00000000U   /*!< Peripheral increment mode Disable */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+  * @{\r
+  */\r
+#define DMA_MINC_ENABLE              DMA_CCR_MINC   /*!< Memory increment mode Enable  */\r
+#define DMA_MINC_DISABLE             0x00000000U    /*!< Memory increment mode Disable */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+  * @{\r
+  */\r
+#define DMA_PDATAALIGN_BYTE          0x00000000U       /*!< Peripheral data alignment : Byte     */\r
+#define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0   /*!< Peripheral data alignment : HalfWord */\r
+#define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1   /*!< Peripheral data alignment : Word     */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+  * @{\r
+  */\r
+#define DMA_MDATAALIGN_BYTE          0x00000000U       /*!< Memory data alignment : Byte     */\r
+#define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0   /*!< Memory data alignment : HalfWord */\r
+#define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1   /*!< Memory data alignment : Word     */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+  * @{\r
+  */\r
+#define DMA_NORMAL                   0x00000000U     /*!< Normal mode                  */\r
+#define DMA_CIRCULAR                 DMA_CCR_CIRC    /*!< Circular mode                */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+  * @{\r
+  */\r
+#define DMA_PRIORITY_LOW             0x00000000U     /*!< Priority level : Low       */\r
+#define DMA_PRIORITY_MEDIUM          DMA_CCR_PL_0    /*!< Priority level : Medium    */\r
+#define DMA_PRIORITY_HIGH            DMA_CCR_PL_1    /*!< Priority level : High      */\r
+#define DMA_PRIORITY_VERY_HIGH       DMA_CCR_PL      /*!< Priority level : Very_High */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+  * @{\r
+  */\r
+#define DMA_IT_TC                         DMA_CCR_TCIE\r
+#define DMA_IT_HT                         DMA_CCR_HTIE\r
+#define DMA_IT_TE                         DMA_CCR_TEIE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+  * @{\r
+  */\r
+#define DMA_FLAG_GL1                      DMA_ISR_GIF1\r
+#define DMA_FLAG_TC1                      DMA_ISR_TCIF1\r
+#define DMA_FLAG_HT1                      DMA_ISR_HTIF1\r
+#define DMA_FLAG_TE1                      DMA_ISR_TEIF1\r
+#define DMA_FLAG_GL2                      DMA_ISR_GIF2\r
+#define DMA_FLAG_TC2                      DMA_ISR_TCIF2\r
+#define DMA_FLAG_HT2                      DMA_ISR_HTIF2\r
+#define DMA_FLAG_TE2                      DMA_ISR_TEIF2\r
+#define DMA_FLAG_GL3                      DMA_ISR_GIF3\r
+#define DMA_FLAG_TC3                      DMA_ISR_TCIF3\r
+#define DMA_FLAG_HT3                      DMA_ISR_HTIF3\r
+#define DMA_FLAG_TE3                      DMA_ISR_TEIF3\r
+#define DMA_FLAG_GL4                      DMA_ISR_GIF4\r
+#define DMA_FLAG_TC4                      DMA_ISR_TCIF4\r
+#define DMA_FLAG_HT4                      DMA_ISR_HTIF4\r
+#define DMA_FLAG_TE4                      DMA_ISR_TEIF4\r
+#define DMA_FLAG_GL5                      DMA_ISR_GIF5\r
+#define DMA_FLAG_TC5                      DMA_ISR_TCIF5\r
+#define DMA_FLAG_HT5                      DMA_ISR_HTIF5\r
+#define DMA_FLAG_TE5                      DMA_ISR_TEIF5\r
+#define DMA_FLAG_GL6                      DMA_ISR_GIF6\r
+#define DMA_FLAG_TC6                      DMA_ISR_TCIF6\r
+#define DMA_FLAG_HT6                      DMA_ISR_HTIF6\r
+#define DMA_FLAG_TE6                      DMA_ISR_TEIF6\r
+#define DMA_FLAG_GL7                      DMA_ISR_GIF7\r
+#define DMA_FLAG_TC7                      DMA_ISR_TCIF7\r
+#define DMA_FLAG_HT7                      DMA_ISR_HTIF7\r
+#define DMA_FLAG_TE7                      DMA_ISR_TEIF7\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup DMA_Exported_Macros DMA Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Reset DMA handle state.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval None\r
+  */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+  * @brief  Enable the specified DMA Channel.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval None\r
+  */\r
+#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)\r
+\r
+/**\r
+  * @brief  Disable the specified DMA Channel.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval None\r
+  */\r
+#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)\r
+\r
+\r
+/* Interrupt & Flag management */\r
+\r
+/**\r
+  * @brief  Return the current DMA Channel transfer complete flag.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval The specified transfer complete flag index.\r
+  */\r
+\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\\r
+   DMA_FLAG_TC7)\r
+\r
+/**\r
+  * @brief  Return the current DMA Channel half transfer complete flag.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval The specified half transfer complete flag index.\r
+  */\r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\\r
+   DMA_FLAG_HT7)\r
+\r
+/**\r
+  * @brief  Return the current DMA Channel transfer error flag.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval The specified transfer error flag index.\r
+  */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\\r
+   DMA_FLAG_TE7)\r
+\r
+/**\r
+  * @brief  Return the current DMA Channel Global interrupt flag.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval The specified transfer error flag index.\r
+  */\r
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\\r
+   DMA_ISR_GIF7)\r
+\r
+/**\r
+  * @brief  Get the DMA Channel pending flags.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @param  __FLAG__ Get the specified flag.\r
+  *          This parameter can be any combination of the following values:\r
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag\r
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag\r
+  *            @arg DMA_FLAG_TEx:  Transfer error flag\r
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag\r
+  *         Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+  * @retval The state of FLAG (SET or RESET).\r
+  */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
+ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))\r
+\r
+/**\r
+  * @brief  Clear the DMA Channel pending flags.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @param  __FLAG__ specifies the flag to clear.\r
+  *          This parameter can be any combination of the following values:\r
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag\r
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag\r
+  *            @arg DMA_FLAG_TEx:  Transfer error flag\r
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag\r
+  *         Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+  * @retval None\r
+  */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
+ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))\r
+\r
+/**\r
+  * @brief  Enable the specified DMA Channel interrupts.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
+  *          This parameter can be any combination of the following values:\r
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask\r
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask\r
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask\r
+  * @retval None\r
+  */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))\r
+\r
+/**\r
+  * @brief  Disable the specified DMA Channel interrupts.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
+  *          This parameter can be any combination of the following values:\r
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask\r
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask\r
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask\r
+  * @retval None\r
+  */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask\r
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask\r
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask\r
+  * @retval The state of DMA_IT (SET or RESET).\r
+  */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))\r
+\r
+/**\r
+  * @brief  Return the number of remaining data units in the current DMA Channel transfer.\r
+  * @param  __HANDLE__ DMA handle\r
+  * @retval The number of remaining data units in the current DMA Channel transfer.\r
+  */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(DMAMUX1)\r
+/* Include DMA HAL Extension module */\r
+#include "stm32l4xx_hal_dma_ex.h"\r
+#endif /* DMAMUX1 */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup DMA_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+/* Initialization and de-initialization functions *****************************/\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group3\r
+  * @{\r
+  */\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+  * @{\r
+  */\r
+\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \\r
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+                                            ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \\r
+                                        ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#if !defined (DMAMUX1)\r
+\r
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \\r
+                                     ((REQUEST) == DMA_REQUEST_1) || \\r
+                                     ((REQUEST) == DMA_REQUEST_2) || \\r
+                                     ((REQUEST) == DMA_REQUEST_3) || \\r
+                                     ((REQUEST) == DMA_REQUEST_4) || \\r
+                                     ((REQUEST) == DMA_REQUEST_5) || \\r
+                                     ((REQUEST) == DMA_REQUEST_6) || \\r
+                                     ((REQUEST) == DMA_REQUEST_7))\r
+#endif\r
+\r
+#if defined(DMAMUX1)\r
+\r
+#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \\r
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \\r
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \\r
+                           ((MODE) == DMA_CIRCULAR))\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \\r
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \\r
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h
new file mode 100644 (file)
index 0000000..81da436
--- /dev/null
@@ -0,0 +1,282 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_dma_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of DMA HAL extension module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_DMA_EX_H\r
+#define STM32L4xx_HAL_DMA_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#if defined(DMAMUX1)\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup DMAEx\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  HAL DMA Synchro definition\r
+  */\r
+\r
+\r
+/**\r
+  * @brief  HAL DMAMUX Synchronization configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.\r
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */\r
+\r
+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.\r
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */\r
+\r
+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled\r
+                                    This parameter can take the value ENABLE or DISABLE*/\r
+\r
+\r
+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.\r
+                                       This parameter can take the value ENABLE or DISABLE */\r
+\r
+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event\r
+                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
+\r
+\r
+}HAL_DMA_MuxSyncConfigTypeDef;\r
+\r
+\r
+/**\r
+  * @brief  HAL DMAMUX request generator parameters structure definition\r
+  */\r
+typedef struct\r
+{\r
+ uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator\r
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */\r
+\r
+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.\r
+                             This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */\r
+\r
+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event\r
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
+\r
+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection\r
+  * @{\r
+  */\r
+#define HAL_DMAMUX1_SYNC_EXTI0                0U           /*!<  Synchronization Signal is EXTI0  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI1                1U           /*!<  Synchronization Signal is EXTI1  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI2                2U           /*!<  Synchronization Signal is EXTI2  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI3                3U           /*!<  Synchronization Signal is EXTI3  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI4                4U           /*!<  Synchronization Signal is EXTI4  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI5                5U           /*!<  Synchronization Signal is EXTI5  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI6                6U           /*!<  Synchronization Signal is EXTI6  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI7                7U           /*!<  Synchronization Signal is EXTI7  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI8                8U           /*!<  Synchronization Signal is EXTI8  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI9                9U           /*!<  Synchronization Signal is EXTI9  IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI10              10U           /*!<  Synchronization Signal is EXTI10 IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI11              11U           /*!<  Synchronization Signal is EXTI11 IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI12              12U           /*!<  Synchronization Signal is EXTI12 IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI13              13U           /*!<  Synchronization Signal is EXTI13 IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI14              14U           /*!<  Synchronization Signal is EXTI14 IT   */\r
+#define HAL_DMAMUX1_SYNC_EXTI15              15U           /*!<  Synchronization Signal is EXTI15 IT   */\r
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT     16U           /*!<  Synchronization Signal is DMAMUX1 Channel0 Event  */\r
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT     17U           /*!<  Synchronization Signal is DMAMUX1 Channel1 Event  */\r
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT     18U           /*!<  Synchronization Signal is DMAMUX1 Channel2 Event  */\r
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT     19U           /*!<  Synchronization Signal is DMAMUX1 Channel3 Event  */\r
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT          20U           /*!<  Synchronization Signal is LPTIM1 OUT */\r
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT          21U           /*!<  Synchronization Signal is LPTIM2 OUT */\r
+#define HAL_DMAMUX1_SYNC_DSI_TE              22U           /*!<  Synchronization Signal is DSI Tearing Effect      */\r
+#define HAL_DMAMUX1_SYNC_DSI_EOT             23U           /*!<  Synchronization Signal is DSI End of refresh      */\r
+#define HAL_DMAMUX1_SYNC_DMA2D_EOT           24U           /*!<  Synchronization Signal is DMA2D End of Transfer   */\r
+#define HAL_DMAMUX1_SYNC_LDTC_IT             25U           /*!<  Synchronization Signal is LDTC IT    */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection\r
+  * @{\r
+  */\r
+#define HAL_DMAMUX_SYNC_NO_EVENT                               0U    /*!< block synchronization events        */\r
+#define HAL_DMAMUX_SYNC_RISING                 DMAMUX_CxCR_SPOL_0    /*!< synchronize with rising edge events */\r
+#define HAL_DMAMUX_SYNC_FALLING                DMAMUX_CxCR_SPOL_1    /*!< synchronize with falling edge events */\r
+#define HAL_DMAMUX_SYNC_RISING_FALLING         DMAMUX_CxCR_SPOL      /*!< synchronize with rising and falling edge events */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection\r
+  * @{\r
+  */\r
+\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI0                0U        /*!< Request generator Signal is EXTI0 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI1                1U        /*!< Request generator Signal is EXTI1 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI2                2U        /*!< Request generator Signal is EXTI2 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI3                3U        /*!< Request generator Signal is EXTI3 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI4                4U        /*!< Request generator Signal is EXTI4 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI5                5U        /*!< Request generator Signal is EXTI5 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI6                6U        /*!< Request generator Signal is EXTI6 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI7                7U        /*!< Request generator Signal is EXTI7 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI8                8U        /*!< Request generator Signal is EXTI8 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI9                9U        /*!< Request generator Signal is EXTI9 IT    */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI10              10U        /*!< Request generator Signal is EXTI10 IT   */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI11              11U        /*!< Request generator Signal is EXTI11 IT   */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI12              12U        /*!< Request generator Signal is EXTI12 IT   */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI13              13U        /*!< Request generator Signal is EXTI13 IT   */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI14              14U        /*!< Request generator Signal is EXTI14 IT   */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI15              15U        /*!< Request generator Signal is EXTI15 IT   */\r
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT     16U        /*!< Request generator Signal is DMAMUX1 Channel0 Event */\r
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT     17U        /*!< Request generator Signal is DMAMUX1 Channel1 Event */\r
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT     18U        /*!< Request generator Signal is DMAMUX1 Channel2 Event */\r
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT     19U        /*!< Request generator Signal is DMAMUX1 Channel3 Event */\r
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT          20U        /*!< Request generator Signal is LPTIM1 OUT  */\r
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT          21U        /*!< Request generator Signal is LPTIM2 OUT  */\r
+#define HAL_DMAMUX1_REQ_GEN_DSI_TE              22U        /*!< Request generator Signal is DSI Tearing Effect      */\r
+#define HAL_DMAMUX1_REQ_GEN_DSI_EOT             23U        /*!< Request generator Signal is DSI End of refresh      */\r
+#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT           24U        /*!< Request generator Signal is DMA2D End of Transfer   */\r
+#define HAL_DMAMUX1_REQ_GEN_LTDC_IT             25U        /*!< Request generator Signal is LTDC IT     */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection\r
+  * @{\r
+  */\r
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT       0U                     /*!< block request generator events        */\r
+#define HAL_DMAMUX_REQ_GEN_RISING         DMAMUX_RGxCR_GPOL_0    /*!< generate request on rising edge events */\r
+#define HAL_DMAMUX_REQ_GEN_FALLING        DMAMUX_RGxCR_GPOL_1    /*!< generate request on falling edge events */\r
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL      /*!< generate request on rising and falling edge events */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DMAEx_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/* IO operation functions *****************************************************/\r
+/** @addtogroup DMAEx_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+\r
+/* ------------------------- REQUEST -----------------------------------------*/\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,\r
+             HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);\r
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);\r
+/* -------------------------------------------------------------------------- */\r
+\r
+/* ------------------------- SYNCHRO -----------------------------------------*/\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);\r
+/* -------------------------------------------------------------------------- */\r
+\r
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Macros DMAEx Private Macros\r
+  * @brief    DMAEx private macros\r
+  * @{\r
+  */\r
+\r
+#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT)\r
+\r
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))\r
+\r
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \\r
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \\r
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \\r
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))\r
+\r
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))\r
+\r
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \\r
+                                     ((EVENT) == ENABLE))\r
+\r
+#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT)\r
+\r
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))\r
+\r
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)   || \\r
+                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \\r
+                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \\r
+                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h
new file mode 100644 (file)
index 0000000..c90e9d0
--- /dev/null
@@ -0,0 +1,860 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_exti.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of EXTI HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_EXTI_H\r
+#define STM32L4xx_HAL_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI EXTI\r
+  * @brief EXTI HAL module driver\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Exported_Types EXTI Exported Types\r
+  * @{\r
+  */\r
+typedef enum\r
+{\r
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,\r
+  HAL_EXTI_RISING_CB_ID          = 0x01U,\r
+  HAL_EXTI_FALLING_CB_ID         = 0x02U,\r
+} EXTI_CallbackIDTypeDef;\r
+\r
+\r
+/**\r
+  * @brief  EXTI Handle structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Line;                    /*!<  Exti line number */\r
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */\r
+} EXTI_HandleTypeDef;\r
+\r
+/**\r
+  * @brief  EXTI Configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter\r
+                           can be a value of @ref EXTI_Line */\r
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.\r
+                           This parameter can be a combination of @ref EXTI_Mode */\r
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter\r
+                           can be a value of @ref EXTI_Trigger */\r
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.\r
+                           This parameter is only possible for line 0 to 15. It\r
+                           can be a value of @ref EXTI_GPIOSel */\r
+} EXTI_ConfigTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Line  EXTI Line\r
+  * @{\r
+  */\r
+#if defined(STM32L412xx) || defined(STM32L422xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_RESERVED | EXTI_REG1              | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
+\r
+#endif /* STM32L412xx || STM32L422xx */\r
+\r
+#if defined(STM32L431xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1              | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2              | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
+\r
+#endif /* STM32L431xx */\r
+\r
+#if defined(STM32L432xx) || defined(STM32L442xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_RESERVED | EXTI_REG1              | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_RESERVED | EXTI_REG1              | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
+\r
+#endif /* STM32L432xx || STM32L442xx */\r
+\r
+#if defined(STM32L433xx) || defined(STM32L443xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
+\r
+#endif /* STM32L433xx || STM32L443xx */\r
+\r
+#if defined(STM32L451xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1              | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2              | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
+\r
+#endif /* STM32L451xx */\r
+\r
+#if defined(STM32L452xx) || defined(STM32L462xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
+\r
+#endif /* STM32L452xx || STM32L462xx */\r
+\r
+#if defined(STM32L471xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1              | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2              | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
+\r
+#endif /* STM32L471xx */\r
+\r
+#if defined(STM32L475xx) || defined(STM32L485xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
+\r
+#endif /* STM32L475xx || STM32L485xx  */\r
+\r
+#if defined(STM32L476xx) || defined(STM32L486xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
+\r
+#endif /*  STM32L476xx || STM32L486xx */\r
+\r
+#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
+\r
+#endif /*  STM32L496xx || STM32L4A6xx */\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+\r
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
+#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
+#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Mode  EXTI Mode\r
+  * @{\r
+  */\r
+#define EXTI_MODE_NONE                      0x00000000u\r
+#define EXTI_MODE_INTERRUPT                 0x00000001u\r
+#define EXTI_MODE_EVENT                     0x00000002u\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Trigger  EXTI Trigger\r
+  * @{\r
+  */\r
+#define EXTI_TRIGGER_NONE                   0x00000000u\r
+#define EXTI_TRIGGER_RISING                 0x00000001u\r
+#define EXTI_TRIGGER_FALLING                0x00000002u\r
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel\r
+  * @brief\r
+  * @{\r
+  */\r
+#define EXTI_GPIOA                          0x00000000u\r
+#define EXTI_GPIOB                          0x00000001u\r
+#define EXTI_GPIOC                          0x00000002u\r
+#define EXTI_GPIOD                          0x00000003u\r
+#define EXTI_GPIOE                          0x00000004u\r
+#define EXTI_GPIOF                          0x00000005u\r
+#define EXTI_GPIOG                          0x00000005u\r
+#define EXTI_GPIOH                          0x00000007u\r
+#define EXTI_GPIOI                          0x00000008u\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private constants --------------------------------------------------------*/\r
+/** @defgroup EXTI_Private_Constants EXTI Private Constants\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  EXTI Line property definition\r
+  */\r
+#define EXTI_PROPERTY_SHIFT                  24u\r
+#define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)\r
+#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)\r
+#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)\r
+#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)\r
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)\r
+\r
+/**\r
+  * @brief  EXTI Event presence definition\r
+  */\r
+#define EXTI_EVENT_PRESENCE_SHIFT           28u\r
+#define EXTI_EVENT                          (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)\r
+#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)\r
+\r
+/**\r
+  * @brief  EXTI Register and bit usage\r
+  */\r
+#define EXTI_REG_SHIFT                      16u\r
+#define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)\r
+#define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)\r
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)\r
+#define EXTI_PIN_MASK                       0x0000001Fu\r
+\r
+/**\r
+  * @brief  EXTI Mask for interrupt & event mode\r
+  */\r
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)\r
+\r
+/**\r
+  * @brief  EXTI Mask for trigger possibilities\r
+  */\r
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)\r
+\r
+/**\r
+  * @brief  EXTI Line number\r
+  */\r
+#define EXTI_LINE_NB                        41u\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup EXTI_Private_Macros EXTI Private Macros\r
+  * @{\r
+  */\r
+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \\r
+                                        ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \\r
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \\r
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \\r
+                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \\r
+                                         (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))\r
+\r
+#define IS_EXTI_MODE(__LINE__)          ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \\r
+                                         (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))\r
+\r
+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)\r
+\r
+#define IS_EXTI_PENDING_EDGE(__LINE__)  ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)\r
+\r
+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00u)\r
+\r
+#if defined(STM32L412xx) || defined(STM32L422xx)\r
+\r
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
+                                         ((__PORT__) == EXTI_GPIOB) || \\r
+                                         ((__PORT__) == EXTI_GPIOC) || \\r
+                                         ((__PORT__) == EXTI_GPIOD) || \\r
+                                         ((__PORT__) == EXTI_GPIOH))\r
+\r
+#endif /* STM32L412xx || STM32L422xx */\r
+\r
+#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)\r
+\r
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
+                                         ((__PORT__) == EXTI_GPIOB) || \\r
+                                         ((__PORT__) == EXTI_GPIOC) || \\r
+                                         ((__PORT__) == EXTI_GPIOD) || \\r
+                                         ((__PORT__) == EXTI_GPIOE) || \\r
+                                         ((__PORT__) == EXTI_GPIOH))\r
+\r
+#endif /* STM32L431xx || STM32L433xx || STM32L443xx */\r
+\r
+#if defined(STM32L432xx) || defined(STM32L442xx)\r
+\r
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
+                                         ((__PORT__) == EXTI_GPIOB) || \\r
+                                         ((__PORT__) == EXTI_GPIOC) || \\r
+                                         ((__PORT__) == EXTI_GPIOH))\r
+\r
+#endif /* STM32L432xx || STM32L442xx */\r
+\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+\r
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
+                                         ((__PORT__) == EXTI_GPIOB) || \\r
+                                         ((__PORT__) == EXTI_GPIOC) || \\r
+                                         ((__PORT__) == EXTI_GPIOD) || \\r
+                                         ((__PORT__) == EXTI_GPIOE) || \\r
+                                         ((__PORT__) == EXTI_GPIOH))\r
+\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+\r
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
+                                         ((__PORT__) == EXTI_GPIOB) || \\r
+                                         ((__PORT__) == EXTI_GPIOC) || \\r
+                                         ((__PORT__) == EXTI_GPIOD) || \\r
+                                         ((__PORT__) == EXTI_GPIOE) || \\r
+                                         ((__PORT__) == EXTI_GPIOF) || \\r
+                                         ((__PORT__) == EXTI_GPIOG) || \\r
+                                         ((__PORT__) == EXTI_GPIOH))\r
+\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
+\r
+#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
+\r
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
+                                         ((__PORT__) == EXTI_GPIOB) || \\r
+                                         ((__PORT__) == EXTI_GPIOC) || \\r
+                                         ((__PORT__) == EXTI_GPIOD) || \\r
+                                         ((__PORT__) == EXTI_GPIOE) || \\r
+                                         ((__PORT__) == EXTI_GPIOF) || \\r
+                                         ((__PORT__) == EXTI_GPIOG) || \\r
+                                         ((__PORT__) == EXTI_GPIOH) || \\r
+                                         ((__PORT__) == EXTI_GPIOI))\r
+\r
+#endif /* STM32L496xx || STM32L4A6xx */\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+\r
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
+                                         ((__PORT__) == EXTI_GPIOB) || \\r
+                                         ((__PORT__) == EXTI_GPIOC) || \\r
+                                         ((__PORT__) == EXTI_GPIOD) || \\r
+                                         ((__PORT__) == EXTI_GPIOE) || \\r
+                                         ((__PORT__) == EXTI_GPIOF) || \\r
+                                         ((__PORT__) == EXTI_GPIOG) || \\r
+                                         ((__PORT__) == EXTI_GPIOH) || \\r
+                                         ((__PORT__) == EXTI_GPIOI))\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16u)\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions\r
+  * @brief    EXTI Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions\r
+  * @brief    Configuration functions\r
+  * @{\r
+  */\r
+/* Configuration functions ****************************************************/\r
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\r
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\r
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);\r
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));\r
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions\r
+  * @brief    IO operation functions\r
+  * @{\r
+  */\r
+/* IO operation functions *****************************************************/\r
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);\r
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\r
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\r
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_EXTI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
new file mode 100644 (file)
index 0000000..afe5626
--- /dev/null
@@ -0,0 +1,1041 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_flash.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of FLASH HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_FLASH_H\r
+#define __STM32L4xx_HAL_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FLASH\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  FLASH Erase structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t TypeErase;   /*!< Mass erase or page erase.\r
+                             This parameter can be a value of @ref FLASH_Type_Erase */\r
+  uint32_t Banks;       /*!< Select bank to erase.\r
+                             This parameter must be a value of @ref FLASH_Banks\r
+                             (FLASH_BANK_BOTH should be used only for mass erase) */\r
+  uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled\r
+                             This parameter must be a value between 0 and (max number of pages in the bank - 1)\r
+                             (eg : 255 for 1MB dual bank) */\r
+  uint32_t NbPages;     /*!< Number of pages to be erased.\r
+                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/\r
+} FLASH_EraseInitTypeDef;\r
+\r
+/**\r
+  * @brief  FLASH Option Bytes Program structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t OptionType;     /*!< Option byte to be configured.\r
+                                This parameter can be a combination of the values of @ref FLASH_OB_Type */\r
+  uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).\r
+                                Only one WRP area could be programmed at the same time.\r
+                                This parameter can be value of @ref FLASH_OB_WRP_Area */\r
+  uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).\r
+                                This parameter must be a value between 0 and (max number of pages in the bank - 1)\r
+                                (eg : 25 for 1MB dual bank) */\r
+  uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).\r
+                                This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */\r
+  uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).\r
+                                This parameter can be a value of @ref FLASH_OB_Read_Protection */\r
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).\r
+                                This parameter can be a combination of @ref FLASH_OB_USER_Type */\r
+  uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).\r
+                                This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,\r
+                                @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,\r
+                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,\r
+                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,\r
+                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,\r
+                                @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,\r
+                                @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */\r
+  uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).\r
+                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)\r
+                                and @ref FLASH_OB_PCROP_RDP */\r
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).\r
+                                This parameter must be a value between begin and end of bank\r
+                                => Be careful of the bank swapping for the address */\r
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).\r
+                                This parameter must be a value between PCROP Start address and end of bank */\r
+} FLASH_OBProgramInitTypeDef;\r
+\r
+/**\r
+  * @brief  FLASH Procedure structure definition\r
+  */\r
+typedef enum\r
+{\r
+  FLASH_PROC_NONE = 0,\r
+  FLASH_PROC_PAGE_ERASE,\r
+  FLASH_PROC_MASS_ERASE,\r
+  FLASH_PROC_PROGRAM,\r
+  FLASH_PROC_PROGRAM_LAST\r
+} FLASH_ProcedureTypeDef;\r
+\r
+/**\r
+  * @brief  FLASH Cache structure definition\r
+  */\r
+typedef enum\r
+{\r
+  FLASH_CACHE_DISABLED = 0,\r
+  FLASH_CACHE_ICACHE_ENABLED,\r
+  FLASH_CACHE_DCACHE_ENABLED,\r
+  FLASH_CACHE_ICACHE_DCACHE_ENABLED\r
+} FLASH_CacheTypeDef;\r
+\r
+/**\r
+  * @brief  FLASH handle Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  HAL_LockTypeDef             Lock;              /* FLASH locking object */\r
+  __IO uint32_t               ErrorCode;         /* FLASH error code */\r
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */\r
+  __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */\r
+  __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */\r
+  __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */\r
+  __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */\r
+  __IO FLASH_CacheTypeDef     CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */\r
+}FLASH_ProcessTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup FLASH_Error FLASH Error\r
+  * @{\r
+  */\r
+#define HAL_FLASH_ERROR_NONE      0x00000000U\r
+#define HAL_FLASH_ERROR_OP        FLASH_FLAG_OPERR\r
+#define HAL_FLASH_ERROR_PROG      FLASH_FLAG_PROGERR\r
+#define HAL_FLASH_ERROR_WRP       FLASH_FLAG_WRPERR\r
+#define HAL_FLASH_ERROR_PGA       FLASH_FLAG_PGAERR\r
+#define HAL_FLASH_ERROR_SIZ       FLASH_FLAG_SIZERR\r
+#define HAL_FLASH_ERROR_PGS       FLASH_FLAG_PGSERR\r
+#define HAL_FLASH_ERROR_MIS       FLASH_FLAG_MISERR\r
+#define HAL_FLASH_ERROR_FAST      FLASH_FLAG_FASTERR\r
+#define HAL_FLASH_ERROR_RD        FLASH_FLAG_RDERR\r
+#define HAL_FLASH_ERROR_OPTV      FLASH_FLAG_OPTVERR\r
+#define HAL_FLASH_ERROR_ECCD      FLASH_FLAG_ECCD\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \\r
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \\r
+    defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define HAL_FLASH_ERROR_PEMPTY    FLASH_FLAG_PEMPTY\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Type_Erase FLASH Erase Type\r
+  * @{\r
+  */\r
+#define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/\r
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)  /*!<Flash mass erase activation*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Banks FLASH Banks\r
+  * @{\r
+  */\r
+#define FLASH_BANK_1              ((uint32_t)0x01)                          /*!< Bank 1   */\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define FLASH_BANK_2              ((uint32_t)0x02)                          /*!< Bank 2   */\r
+#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */\r
+#else\r
+#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1))                /*!< Bank 1   */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup FLASH_Type_Program FLASH Program Type\r
+  * @{\r
+  */\r
+#define FLASH_TYPEPROGRAM_DOUBLEWORD    ((uint32_t)0x00)  /*!<Program a double-word (64-bit) at a specified address.*/\r
+#define FLASH_TYPEPROGRAM_FAST          ((uint32_t)0x01)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.\r
+                                                                 And another 32 row double-word (64-bit) will be programmed */\r
+#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.\r
+                                                                 And this is the last 32 row double-word (64-bit) programmed */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_Type FLASH Option Bytes Type\r
+  * @{\r
+  */\r
+#define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!< WRP option byte configuration */\r
+#define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!< RDP option byte configuration */\r
+#define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!< USER option byte configuration */\r
+#define OPTIONBYTE_PCROP          ((uint32_t)0x08)  /*!< PCROP option byte configuration */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area\r
+  * @{\r
+  */\r
+#define OB_WRPAREA_BANK1_AREAA    ((uint32_t)0x00)  /*!< Flash Bank 1 Area A */\r
+#define OB_WRPAREA_BANK1_AREAB    ((uint32_t)0x01)  /*!< Flash Bank 1 Area B */\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define OB_WRPAREA_BANK2_AREAA    ((uint32_t)0x02)  /*!< Flash Bank 2 Area A */\r
+#define OB_WRPAREA_BANK2_AREAB    ((uint32_t)0x04)  /*!< Flash Bank 2 Area B */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection\r
+  * @{\r
+  */\r
+#define OB_RDP_LEVEL_0            ((uint32_t)0xAA)\r
+#define OB_RDP_LEVEL_1            ((uint32_t)0xBB)\r
+#define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2\r
+                                                        it's no more possible to go back to level 1 or 0 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type\r
+  * @{\r
+  */\r
+#define OB_USER_BOR_LEV           ((uint32_t)0x0001)                   /*!< BOR reset Level */\r
+#define OB_USER_nRST_STOP         ((uint32_t)0x0002)                   /*!< Reset generated when entering the stop mode */\r
+#define OB_USER_nRST_STDBY        ((uint32_t)0x0004)                   /*!< Reset generated when entering the standby mode */\r
+#define OB_USER_IWDG_SW           ((uint32_t)0x0008)                   /*!< Independent watchdog selection */\r
+#define OB_USER_IWDG_STOP         ((uint32_t)0x0010)                   /*!< Independent watchdog counter freeze in stop mode */\r
+#define OB_USER_IWDG_STDBY        ((uint32_t)0x0020)                   /*!< Independent watchdog counter freeze in standby mode */\r
+#define OB_USER_WWDG_SW           ((uint32_t)0x0040)                   /*!< Window watchdog selection */\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define OB_USER_BFB2              ((uint32_t)0x0080)                   /*!< Dual-bank boot */\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 1MB or 512kB Flash memory devices */\r
+#else\r
+#define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 512KB or 256KB Flash memory devices */\r
+#endif\r
+#endif\r
+#define OB_USER_nBOOT1            ((uint32_t)0x0200)                   /*!< Boot configuration */\r
+#define OB_USER_SRAM2_PE          ((uint32_t)0x0400)                   /*!< SRAM2 parity check enable */\r
+#define OB_USER_SRAM2_RST         ((uint32_t)0x0800)                   /*!< SRAM2 Erase when system reset */\r
+#define OB_USER_nRST_SHDW         ((uint32_t)0x1000)                   /*!< Reset generated when entering the shutdown mode */\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
+    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define OB_USER_nSWBOOT0          ((uint32_t)0x2000)                   /*!< Software BOOT0 */\r
+#define OB_USER_nBOOT0            ((uint32_t)0x4000)                   /*!< nBOOT0 option bit */\r
+#endif\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define OB_USER_DBANK             ((uint32_t)0x8000)                   /*!< Single bank with 128-bits data or two banks with 64-bits data */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level\r
+  * @{\r
+  */\r
+#define OB_BOR_LEVEL_0            ((uint32_t)FLASH_OPTR_BOR_LEV_0)     /*!< Reset level threshold is around 1.7V */\r
+#define OB_BOR_LEVEL_1            ((uint32_t)FLASH_OPTR_BOR_LEV_1)     /*!< Reset level threshold is around 2.0V */\r
+#define OB_BOR_LEVEL_2            ((uint32_t)FLASH_OPTR_BOR_LEV_2)     /*!< Reset level threshold is around 2.2V */\r
+#define OB_BOR_LEVEL_3            ((uint32_t)FLASH_OPTR_BOR_LEV_3)     /*!< Reset level threshold is around 2.5V */\r
+#define OB_BOR_LEVEL_4            ((uint32_t)FLASH_OPTR_BOR_LEV_4)     /*!< Reset level threshold is around 2.8V */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop\r
+  * @{\r
+  */\r
+#define OB_STOP_RST               ((uint32_t)0x0000)                   /*!< Reset generated when entering the stop mode */\r
+#define OB_STOP_NORST             ((uint32_t)FLASH_OPTR_nRST_STOP)     /*!< No reset generated when entering the stop mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby\r
+  * @{\r
+  */\r
+#define OB_STANDBY_RST            ((uint32_t)0x0000)                   /*!< Reset generated when entering the standby mode */\r
+#define OB_STANDBY_NORST          ((uint32_t)FLASH_OPTR_nRST_STDBY)    /*!< No reset generated when entering the standby mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown\r
+  * @{\r
+  */\r
+#define OB_SHUTDOWN_RST           ((uint32_t)0x0000)                   /*!< Reset generated when entering the shutdown mode */\r
+#define OB_SHUTDOWN_NORST         ((uint32_t)FLASH_OPTR_nRST_SHDW)     /*!< No reset generated when entering the shutdown mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type\r
+  * @{\r
+  */\r
+#define OB_IWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware independent watchdog */\r
+#define OB_IWDG_SW                ((uint32_t)FLASH_OPTR_IWDG_SW)       /*!< Software independent watchdog */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop\r
+  * @{\r
+  */\r
+#define OB_IWDG_STOP_FREEZE       ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Stop mode */\r
+#define OB_IWDG_STOP_RUN          ((uint32_t)FLASH_OPTR_IWDG_STOP)     /*!< Independent watchdog counter is running in Stop mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby\r
+  * @{\r
+  */\r
+#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Standby mode */\r
+#define OB_IWDG_STDBY_RUN         ((uint32_t)FLASH_OPTR_IWDG_STDBY)    /*!< Independent watchdog counter is running in Standby mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type\r
+  * @{\r
+  */\r
+#define OB_WWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware window watchdog */\r
+#define OB_WWDG_SW                ((uint32_t)FLASH_OPTR_WWDG_SW)       /*!< Software window watchdog */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode\r
+  * @{\r
+  */\r
+#define OB_BFB2_DISABLE           ((uint32_t)0x000000)                 /*!< Dual-bank boot disable */\r
+#define OB_BFB2_ENABLE            ((uint32_t)FLASH_OPTR_BFB2)          /*!< Dual-bank boot enable */\r
+/**\r
+  * @}\r
+  */\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type\r
+  * @{\r
+  */\r
+#define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 1 MB/512 kB Single-bank Flash */\r
+#define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DB1M)          /*!< 1 MB/512 kB Dual-bank Flash */\r
+/**\r
+  * @}\r
+  */\r
+#else\r
+/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type\r
+  * @{\r
+  */\r
+#define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 256 KB/512 KB Single-bank Flash */\r
+#define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DUALBANK)      /*!< 256 KB/512 KB Dual-bank Flash */\r
+/**\r
+  * @}\r
+  */\r
+#endif\r
+#endif\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type\r
+  * @{\r
+  */\r
+#define OB_DBANK_128_BITS         ((uint32_t)0x000000)                 /*!< Single-bank with 128-bits data */\r
+#define OB_DBANK_64_BITS          ((uint32_t)FLASH_OPTR_DBANK)         /*!< Dual-bank with 64-bits data */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type\r
+  * @{\r
+  */\r
+#define OB_BOOT1_SRAM             ((uint32_t)0x000000)                 /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */\r
+#define OB_BOOT1_SYSTEM           ((uint32_t)FLASH_OPTR_nBOOT1)        /*!< System memory is selected as boot space (if BOOT0=1) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type\r
+  * @{\r
+  */\r
+#define OB_SRAM2_PARITY_ENABLE    ((uint32_t)0x0000000)                /*!< SRAM2 parity check enable */\r
+#define OB_SRAM2_PARITY_DISABLE   ((uint32_t)FLASH_OPTR_SRAM2_PE)      /*!< SRAM2 parity check disable */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type\r
+  * @{\r
+  */\r
+#define OB_SRAM2_RST_ERASE        ((uint32_t)0x0000000)                /*!< SRAM2 erased when a system reset occurs */\r
+#define OB_SRAM2_RST_NOT_ERASE    ((uint32_t)FLASH_OPTR_SRAM2_RST)     /*!< SRAM2 is not erased when a system reset occurs */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
+    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+/** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0\r
+  * @{\r
+  */\r
+#define OB_BOOT0_FROM_OB          ((uint32_t)0x0000000)                /*!< BOOT0 taken from the option bit nBOOT0 */\r
+#define OB_BOOT0_FROM_PIN         ((uint32_t)FLASH_OPTR_nSWBOOT0)      /*!< BOOT0 taken from PH3/BOOT0 pin */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit\r
+  * @{\r
+  */\r
+#define OB_BOOT0_RESET            ((uint32_t)0x0000000)                /*!< nBOOT0 = 0 */\r
+#define OB_BOOT0_SET              ((uint32_t)FLASH_OPTR_nBOOT0)        /*!< nBOOT0 = 1 */\r
+/**\r
+  * @}\r
+  */\r
+#endif\r
+\r
+/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type\r
+  * @{\r
+  */\r
+#define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level\r
+                                                                            is decreased from Level 1 to Level 0 */\r
+#define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is\r
+                                                                            decreased from Level 1 to Level 0 (full mass erase) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Latency FLASH Latency\r
+  * @{\r
+  */\r
+#define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS                /*!< FLASH Zero wait state */\r
+#define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS                /*!< FLASH One wait state */\r
+#define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS                /*!< FLASH Two wait states */\r
+#define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS                /*!< FLASH Three wait states */\r
+#define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS                /*!< FLASH Four wait states */\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define FLASH_LATENCY_5           FLASH_ACR_LATENCY_5WS                /*!< FLASH Five wait state */\r
+#define FLASH_LATENCY_6           FLASH_ACR_LATENCY_6WS                /*!< FLASH Six wait state */\r
+#define FLASH_LATENCY_7           FLASH_ACR_LATENCY_7WS                /*!< FLASH Seven wait states */\r
+#define FLASH_LATENCY_8           FLASH_ACR_LATENCY_8WS                /*!< FLASH Eight wait states */\r
+#define FLASH_LATENCY_9           FLASH_ACR_LATENCY_9WS                /*!< FLASH Nine wait states */\r
+#define FLASH_LATENCY_10          FLASH_ACR_LATENCY_10WS               /*!< FLASH Ten wait state */\r
+#define FLASH_LATENCY_11          FLASH_ACR_LATENCY_11WS               /*!< FLASH Eleven wait state */\r
+#define FLASH_LATENCY_12          FLASH_ACR_LATENCY_12WS               /*!< FLASH Twelve wait states */\r
+#define FLASH_LATENCY_13          FLASH_ACR_LATENCY_13WS               /*!< FLASH Thirteen wait states */\r
+#define FLASH_LATENCY_14          FLASH_ACR_LATENCY_14WS               /*!< FLASH Fourteen wait states */\r
+#define FLASH_LATENCY_15          FLASH_ACR_LATENCY_15WS               /*!< FLASH Fifteen wait states */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Keys FLASH Keys\r
+  * @{\r
+  */\r
+#define FLASH_KEY1                0x45670123U                          /*!< Flash key1 */\r
+#define FLASH_KEY2                0xCDEF89ABU                          /*!< Flash key2: used with FLASH_KEY1\r
+                                                                            to unlock the FLASH registers access */\r
+\r
+#define FLASH_PDKEY1              0x04152637U                          /*!< Flash power down key1 */\r
+#define FLASH_PDKEY2              0xFAFBFCFDU                          /*!< Flash power down key2: used with FLASH_PDKEY1\r
+                                                                            to unlock the RUN_PD bit in FLASH_ACR */\r
+\r
+#define FLASH_OPTKEY1             0x08192A3BU                          /*!< Flash option byte key1 */\r
+#define FLASH_OPTKEY2             0x4C5D6E7FU                          /*!< Flash option byte key2: used with FLASH_OPTKEY1\r
+                                                                            to allow option bytes operations */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Flags FLASH Flags Definition\r
+  * @{\r
+  */\r
+#define FLASH_FLAG_EOP            FLASH_SR_EOP                         /*!< FLASH End of operation flag */\r
+#define FLASH_FLAG_OPERR          FLASH_SR_OPERR                       /*!< FLASH Operation error flag */\r
+#define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR                     /*!< FLASH Programming error flag */\r
+#define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR                      /*!< FLASH Write protection error flag */\r
+#define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR                      /*!< FLASH Programming alignment error flag */\r
+#define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR                      /*!< FLASH Size error flag  */\r
+#define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR                      /*!< FLASH Programming sequence error flag */\r
+#define FLASH_FLAG_MISERR         FLASH_SR_MISERR                      /*!< FLASH Fast programming data miss error flag */\r
+#define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR                     /*!< FLASH Fast programming error flag */\r
+#define FLASH_FLAG_RDERR          FLASH_SR_RDERR                       /*!< FLASH PCROP read error flag */\r
+#define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR                     /*!< FLASH Option validity error flag  */\r
+#define FLASH_FLAG_BSY            FLASH_SR_BSY                         /*!< FLASH Busy flag */\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \\r
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \\r
+    defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define FLASH_FLAG_PEMPTY         FLASH_SR_PEMPTY                      /*!< FLASH Program empty */\r
+#define FLASH_FLAG_SR_ERRORS      (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \\r
+                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \\r
+                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \\r
+                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY)\r
+#else\r
+#define FLASH_FLAG_SR_ERRORS      (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \\r
+                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \\r
+                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \\r
+                                   FLASH_FLAG_OPTVERR)\r
+#endif\r
+#define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC                      /*!< FLASH ECC correction */\r
+#define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD                      /*!< FLASH ECC detection */\r
+\r
+#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \\r
+                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \\r
+                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \\r
+                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition\r
+  * @brief FLASH Interrupt definition\r
+  * @{\r
+  */\r
+#define FLASH_IT_EOP              FLASH_CR_EOPIE                       /*!< End of FLASH Operation Interrupt source */\r
+#define FLASH_IT_OPERR            FLASH_CR_ERRIE                       /*!< Error Interrupt source */\r
+#define FLASH_IT_RDERR            FLASH_CR_RDERRIE                     /*!< PCROP Read Error Interrupt source*/\r
+#define FLASH_IT_ECCC             (FLASH_ECCR_ECCIE >> 24)             /*!< ECC Correction Interrupt source */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ *  @brief macros to control FLASH features\r
+ *  @{\r
+ */\r
+\r
+/**\r
+  * @brief  Set the FLASH Latency.\r
+  * @param  __LATENCY__: FLASH Latency\r
+  *         This parameter can be one of the following values :\r
+  *     @arg FLASH_LATENCY_0: FLASH Zero wait state\r
+  *     @arg FLASH_LATENCY_1: FLASH One wait state\r
+  *     @arg FLASH_LATENCY_2: FLASH Two wait states\r
+  *     @arg FLASH_LATENCY_3: FLASH Three wait states\r
+  *     @arg FLASH_LATENCY_4: FLASH Four wait states\r
+  * @retval None\r
+  */\r
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))\r
+\r
+/**\r
+  * @brief  Get the FLASH Latency.\r
+  * @retval FLASH Latency\r
+  *         This parameter can be one of the following values :\r
+  *     @arg FLASH_LATENCY_0: FLASH Zero wait state\r
+  *     @arg FLASH_LATENCY_1: FLASH One wait state\r
+  *     @arg FLASH_LATENCY_2: FLASH Two wait states\r
+  *     @arg FLASH_LATENCY_3: FLASH Three wait states\r
+  *     @arg FLASH_LATENCY_4: FLASH Four wait states\r
+  */\r
+#define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)\r
+\r
+/**\r
+  * @brief  Enable the FLASH prefetch buffer.\r
+  * @retval None\r
+  */\r
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)\r
+\r
+/**\r
+  * @brief  Disable the FLASH prefetch buffer.\r
+  * @retval None\r
+  */\r
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)\r
+\r
+/**\r
+  * @brief  Enable the FLASH instruction cache.\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)\r
+\r
+/**\r
+  * @brief  Disable the FLASH instruction cache.\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)\r
+\r
+/**\r
+  * @brief  Enable the FLASH data cache.\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)\r
+\r
+/**\r
+  * @brief  Disable the FLASH data cache.\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)\r
+\r
+/**\r
+  * @brief  Reset the FLASH instruction Cache.\r
+  * @note   This function must be used only when the Instruction Cache is disabled.\r
+  * @retval None\r
+  */\r
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \\r
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \\r
+                                                   } while (0)\r
+\r
+/**\r
+  * @brief  Reset the FLASH data Cache.\r
+  * @note   This function must be used only when the data Cache is disabled.\r
+  * @retval None\r
+  */\r
+#define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \\r
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \\r
+                                                   } while (0)\r
+\r
+/**\r
+  * @brief  Enable the FLASH power down during Low-power run mode.\r
+  * @note   Writing this bit  to 0 this bit, automatically the keys are\r
+  *         loss and a new unlock sequence is necessary to re-write it to 1.\r
+  */\r
+#define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \\r
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \\r
+                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \\r
+                                                   } while (0)\r
+\r
+/**\r
+  * @brief  Disable the FLASH power down during Low-power run mode.\r
+  * @note   Writing this bit  to 0 this bit, automatically the keys are\r
+  *         loss and a new unlock sequence is necessary to re-write it to 1.\r
+  */\r
+#define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \\r
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \\r
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \\r
+                                                   } while (0)\r
+\r
+/**\r
+  * @brief  Enable the FLASH power down during Low-Power sleep mode\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)\r
+\r
+/**\r
+  * @brief  Disable the FLASH power down during Low-Power sleep mode\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Interrupt FLASH Interrupts Macros\r
+ *  @brief macros to handle FLASH interrupts\r
+ * @{\r
+ */\r
+\r
+/**\r
+  * @brief  Enable the specified FLASH interrupt.\r
+  * @param  __INTERRUPT__: FLASH interrupt\r
+  *         This parameter can be any combination of the following values:\r
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+  *     @arg FLASH_IT_OPERR: Error Interrupt\r
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt\r
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\\r
+                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\\r
+                                                   } while(0)\r
+\r
+/**\r
+  * @brief  Disable the specified FLASH interrupt.\r
+  * @param  __INTERRUPT__: FLASH interrupt\r
+  *         This parameter can be any combination of the following values:\r
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+  *     @arg FLASH_IT_OPERR: Error Interrupt\r
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt\r
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt\r
+  * @retval none\r
+  */\r
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\\r
+                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\\r
+                                                   } while(0)\r
+\r
+/**\r
+  * @brief  Check whether the specified FLASH flag is set or not.\r
+  * @param  __FLAG__: specifies the FLASH flag to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag\r
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag\r
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag\r
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag\r
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag\r
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag\r
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag\r
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag\r
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag\r
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
+  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag\r
+  *     @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)\r
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected\r
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected\r
+  * @retval The new state of FLASH_FLAG (SET or RESET).\r
+  */\r
+#define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \\r
+                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))          : \\r
+                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))\r
+\r
+/**\r
+  * @brief  Clear the FLASH's pending flags.\r
+  * @param  __FLAG__: specifies the FLASH flags to clear.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag\r
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag\r
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag\r
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag\r
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag\r
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag\r
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag\r
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag\r
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag\r
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected\r
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected\r
+  *     @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags\r
+  * @retval None\r
+  */\r
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\\r
+                                                     if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\\r
+                                                   } while(0)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include FLASH HAL Extended module */\r
+#include "stm32l4xx_hal_flash_ex.h"\r
+#include "stm32l4xx_hal_flash_ramfunc.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASH_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/* Program operation functions  ***********************************************/\r
+/** @addtogroup FLASH_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+/* FLASH IRQ handler method */\r
+void               HAL_FLASH_IRQHandler(void);\r
+/* Callbacks in non blocking modes */\r
+void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
+void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Peripheral Control functions  **********************************************/\r
+/** @addtogroup FLASH_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef  HAL_FLASH_Unlock(void);\r
+HAL_StatusTypeDef  HAL_FLASH_Lock(void);\r
+/* Option bytes control */\r
+HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);\r
+HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);\r
+HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Peripheral State functions  ************************************************/\r
+/** @addtogroup FLASH_Exported_Functions_Group3\r
+  * @{\r
+  */\r
+uint32_t HAL_FLASH_GetError(void);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Variables FLASH Private Variables\r
+ * @{\r
+ */\r
+extern FLASH_ProcessTypeDef pFlash;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private function ----------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private constants --------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
+  * @{\r
+  */\r
+#define FLASH_SIZE_DATA_REGISTER           ((uint32_t)0x1FFF75E0)\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \\r
+                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
+#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \\r
+                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)\r
+#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \\r
+                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
+#elif defined (STM32L412xx) || defined (STM32L422xx)\r
+#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) :  \\r
+                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
+#else\r
+#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \\r
+                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
+#endif\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define FLASH_BANK_SIZE                    (FLASH_SIZE >> 1U)\r
+#else\r
+#define FLASH_BANK_SIZE                    (FLASH_SIZE)\r
+#endif\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define FLASH_PAGE_SIZE                    ((uint32_t)0x1000)\r
+#define FLASH_PAGE_SIZE_128_BITS           ((uint32_t)0x2000)\r
+#else\r
+#define FLASH_PAGE_SIZE                    ((uint32_t)0x800)\r
+#endif\r
+\r
+#define FLASH_TIMEOUT_VALUE                ((uint32_t)50000)/* 50 s */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
+ *  @{\r
+ */\r
+\r
+#define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \\r
+                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \\r
+                                            ((BANK) == FLASH_BANK_2)  || \\r
+                                            ((BANK) == FLASH_BANK_BOTH))\r
+\r
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \\r
+                                            ((BANK) == FLASH_BANK_2))\r
+#else\r
+#define IS_FLASH_BANK(BANK)                ((BANK) == FLASH_BANK_1)\r
+\r
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      ((BANK) == FLASH_BANK_1)\r
+#endif\r
+\r
+#define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \\r
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \\r
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU)))\r
+#else\r
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE))         && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \\r
+                                            ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \\r
+                                            ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \\r
+                                            ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \\r
+                                            ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)))))))\r
+#endif\r
+\r
+#define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))\r
+\r
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_FLASH_PAGE(PAGE)                ((PAGE) < 256U)\r
+#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \\r
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \\r
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U)  : \\r
+                                            ((PAGE) < 256U)))))\r
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \\r
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \\r
+                                            ((PAGE) < 256U))))\r
+#else\r
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \\r
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U)  ? ((PAGE) < 64U)  : \\r
+                                            ((PAGE) < 128U))))\r
+#endif\r
+\r
+#define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \\r
+                                            ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))\r
+#else\r
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))\r
+#endif\r
+\r
+#define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\\r
+                                            ((LEVEL) == OB_RDP_LEVEL_1)/* ||\\r
+                                            ((LEVEL) == OB_RDP_LEVEL_2)*/)\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U))\r
+#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U))\r
+#else\r
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U))\r
+#endif\r
+\r
+#define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \\r
+                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \\r
+                                            ((LEVEL) == OB_BOR_LEVEL_4))\r
+\r
+#define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))\r
+\r
+#define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))\r
+\r
+#define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))\r
+\r
+#define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))\r
+\r
+#define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))\r
+\r
+#define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))\r
+\r
+#define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))\r
+\r
+#define IS_OB_USER_DUALBANK(VALUE)         (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))\r
+#endif\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_OB_USER_DBANK(VALUE)            (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))\r
+#endif\r
+\r
+#define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))\r
+\r
+#define IS_OB_USER_SRAM2_PARITY(VALUE)     (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))\r
+\r
+#define IS_OB_USER_SRAM2_RST(VALUE)        (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))\r
+\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
+    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
+    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_OB_USER_SWBOOT0(VALUE)          (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))\r
+\r
+#define IS_OB_USER_BOOT0(VALUE)            (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))\r
+#endif\r
+\r
+#define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))\r
+#else\r
+#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_1) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_2) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_3) || \\r
+                                            ((LATENCY) == FLASH_LATENCY_4))\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_FLASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
new file mode 100644 (file)
index 0000000..5c4f6c8
--- /dev/null
@@ -0,0 +1,128 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_flash_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of FLASH HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_FLASH_EX_H\r
+#define __STM32L4xx_HAL_FLASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FLASHEx\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+#if defined (FLASH_CFGR_LVEN)\r
+/** @addtogroup FLASHEx_Exported_Constants\r
+  * @{\r
+  */\r
+/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration\r
+  * @{\r
+  */\r
+#define FLASH_LVE_PIN_CTRL     0x00000000U       /*!< LVE FLASH pin controlled by power controller       */\r
+#define FLASH_LVE_PIN_FORCED   FLASH_CFGR_LVEN   /*!< LVE FLASH pin enforced to low (external SMPS used) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* FLASH_CFGR_LVEN */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/* Extended Program operation functions  *************************************/\r
+/** @addtogroup FLASHEx_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined (FLASH_CFGR_LVEN)\r
+/** @addtogroup FLASHEx_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE);\r
+/**\r
+  * @}\r
+  */\r
+#endif /* FLASH_CFGR_LVEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private function ----------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions\r
+ * @{\r
+ */\r
+void FLASH_PageErase(uint32_t Page, uint32_t Banks);\r
+void FLASH_FlushCaches(void);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/**\r
+  @cond 0\r
+  */\r
+#if defined (FLASH_CFGR_LVEN)\r
+#define IS_FLASH_LVE_PIN(CFG)  (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED))\r
+#endif /* FLASH_CFGR_LVEN */\r
+/**\r
+  @endcond\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_FLASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
new file mode 100644 (file)
index 0000000..0c719e2
--- /dev/null
@@ -0,0 +1,77 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_flash_ramfunc.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of FLASH RAMFUNC driver.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_FLASH_RAMFUNC_H\r
+#define __STM32L4xx_FLASH_RAMFUNC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FLASH_RAMFUNC\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+/* Peripheral Control functions  ************************************************/\r
+__RAM_FUNC  HAL_FLASHEx_EnableRunPowerDown(void);\r
+__RAM_FUNC  HAL_FLASHEx_DisableRunPowerDown(void);\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+__RAM_FUNC  HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_FLASH_RAMFUNC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
new file mode 100644 (file)
index 0000000..7d50932
--- /dev/null
@@ -0,0 +1,300 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_gpio.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of GPIO HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_GPIO_H\r
+#define __STM32L4xx_HAL_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup GPIO\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
+  * @{\r
+  */\r
+/**\r
+  * @brief   GPIO Init structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.\r
+                           This parameter can be any value of @ref GPIO_pins */\r
+\r
+  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.\r
+                           This parameter can be a value of @ref GPIO_mode */\r
+\r
+  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
+                           This parameter can be a value of @ref GPIO_pull */\r
+\r
+  uint32_t Speed;      /*!< Specifies the speed for the selected pins.\r
+                           This parameter can be a value of @ref GPIO_speed */\r
+\r
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins\r
+                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */\r
+}GPIO_InitTypeDef;\r
+\r
+/**\r
+  * @brief  GPIO Bit SET and Bit RESET enumeration\r
+  */\r
+typedef enum\r
+{\r
+  GPIO_PIN_RESET = 0U,\r
+  GPIO_PIN_SET\r
+}GPIO_PinState;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
+  * @{\r
+  */\r
+/** @defgroup GPIO_pins GPIO pins\r
+  * @{\r
+  */\r
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */\r
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */\r
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */\r
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */\r
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */\r
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */\r
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */\r
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */\r
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */\r
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */\r
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */\r
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */\r
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */\r
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */\r
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */\r
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */\r
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */\r
+\r
+#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_mode GPIO mode\r
+  * @brief GPIO Configuration Mode\r
+  *        Elements values convention: 0xX0yz00YZ\r
+  *           - X  : GPIO mode or EXTI Mode\r
+  *           - y  : External IT or Event trigger detection\r
+  *           - z  : IO configuration on External IT or Event\r
+  *           - Y  : Output type (Push Pull or Open Drain)\r
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)\r
+  * @{\r
+  */\r
+#define  GPIO_MODE_INPUT                        (0x00000000u)   /*!< Input Floating Mode                   */\r
+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001u)   /*!< Output Push Pull Mode                 */\r
+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011u)   /*!< Output Open Drain Mode                */\r
+#define  GPIO_MODE_AF_PP                        (0x00000002u)   /*!< Alternate Function Push Pull Mode     */\r
+#define  GPIO_MODE_AF_OD                        (0x00000012u)   /*!< Alternate Function Open Drain Mode    */\r
+#define  GPIO_MODE_ANALOG                       (0x00000003u)   /*!< Analog Mode  */\r
+#define  GPIO_MODE_ANALOG_ADC_CONTROL           (0x0000000Bu)   /*!< Analog Mode for ADC conversion */\r
+#define  GPIO_MODE_IT_RISING                    (0x10110000u)   /*!< External Interrupt Mode with Rising edge trigger detection          */\r
+#define  GPIO_MODE_IT_FALLING                   (0x10210000u)   /*!< External Interrupt Mode with Falling edge trigger detection         */\r
+#define  GPIO_MODE_IT_RISING_FALLING            (0x10310000u)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */\r
+#define  GPIO_MODE_EVT_RISING                   (0x10120000u)   /*!< External Event Mode with Rising edge trigger detection              */\r
+#define  GPIO_MODE_EVT_FALLING                  (0x10220000u)   /*!< External Event Mode with Falling edge trigger detection             */\r
+#define  GPIO_MODE_EVT_RISING_FALLING           (0x10320000u)   /*!< External Event Mode with Rising/Falling edge trigger detection      */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_speed GPIO speed\r
+  * @brief GPIO Output Maximum frequency\r
+  * @{\r
+  */\r
+#define  GPIO_SPEED_FREQ_LOW        (0x00000000u)   /*!< range up to 5 MHz, please refer to the product datasheet */\r
+#define  GPIO_SPEED_FREQ_MEDIUM     (0x00000001u)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */\r
+#define  GPIO_SPEED_FREQ_HIGH       (0x00000002u)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */\r
+#define  GPIO_SPEED_FREQ_VERY_HIGH  (0x00000003u)   /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */\r
+/**\r
+  * @}\r
+  */\r
+\r
+ /** @defgroup GPIO_pull GPIO pull\r
+   * @brief GPIO Pull-Up or Pull-Down Activation\r
+   * @{\r
+   */\r
+#define  GPIO_NOPULL        (0x00000000u)   /*!< No Pull-up or Pull-down activation  */\r
+#define  GPIO_PULLUP        (0x00000001u)   /*!< Pull-up activation                  */\r
+#define  GPIO_PULLDOWN      (0x00000002u)   /*!< Pull-down activation                */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Check whether the specified EXTI line flag is set or not.\r
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.\r
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)\r
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+  */\r
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))\r
+\r
+/**\r
+  * @brief  Clear the EXTI's line pending flags.\r
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.\r
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+  * @retval None\r
+  */\r
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))\r
+\r
+/**\r
+  * @brief  Check whether the specified EXTI line is asserted or not.\r
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.\r
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+  */\r
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))\r
+\r
+/**\r
+  * @brief  Clear the EXTI's line pending bits.\r
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.\r
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+  * @retval None\r
+  */\r
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))\r
+\r
+/**\r
+  * @brief  Generate a Software interrupt on selected EXTI line.\r
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.\r
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r
+  * @retval None\r
+  */\r
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Macros GPIO Private Macros\r
+  * @{\r
+  */\r
+#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
+\r
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\\r
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))\r
+\r
+#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\\r
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\\r
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\\r
+                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\\r
+                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\\r
+                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\\r
+                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\\r
+                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\\r
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\\r
+                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\\r
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
+                                     ((__MODE__) == GPIO_MODE_ANALOG)             ||\\r
+                                     ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))\r
+\r
+#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\\r
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\\r
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\\r
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))\r
+\r
+#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\\r
+                                     ((__PULL__) == GPIO_PULLUP)   || \\r
+                                     ((__PULL__) == GPIO_PULLDOWN))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include GPIO HAL Extended module */\r
+#include "stm32l4xx_hal_gpio_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions\r
+ *  @brief    Initialization and Configuration functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions *****************************/\r
+void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
+void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
+void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
+void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_GPIO_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
new file mode 100644 (file)
index 0000000..85281c4
--- /dev/null
@@ -0,0 +1,909 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_gpio_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of GPIO HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_GPIO_EX_H\r
+#define __STM32L4xx_HAL_GPIO_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIOEx GPIOEx\r
+  * @brief GPIO Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection\r
+  * @{\r
+  */\r
+\r
+#if defined(STM32L412xx) || defined(STM32L422xx)\r
+/*--------------STM32L412xx/STM32L422xx---*/\r
+/**\r
+  * @brief   AF 0 selection\r
+  */\r
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
+\r
+/**\r
+  * @brief   AF 1 selection\r
+  */\r
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 2 selection\r
+  */\r
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 3 selection\r
+  */\r
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART1 Alternate Function mapping */\r
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 4 selection\r
+  */\r
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 5 selection\r
+  */\r
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 6 selection\r
+  */\r
+#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 7 selection\r
+  */\r
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
+\r
+/**\r
+  * @brief   AF 8 selection\r
+  */\r
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 9 selection\r
+  */\r
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 10 selection\r
+  */\r
+#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */\r
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 12 selection\r
+  */\r
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
+\r
+\r
+/**\r
+  * @brief   AF 14 selection\r
+  */\r
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 15 selection\r
+  */\r
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
+\r
+#endif /* STM32L412xx || STM32L422xx */\r
+\r
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)\r
+/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/\r
+/**\r
+  * @brief   AF 0 selection\r
+  */\r
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
+#if defined(STM32L433xx) || defined(STM32L443xx)\r
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                          */\r
+#endif /* STM32L433xx || STM32L443xx */\r
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
+\r
+/**\r
+  * @brief   AF 1 selection\r
+  */\r
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 2 selection\r
+  */\r
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 3 selection\r
+  */\r
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART1 Alternate Function mapping */\r
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 4 selection\r
+  */\r
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 5 selection\r
+  */\r
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 6 selection\r
+  */\r
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
+#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 7 selection\r
+  */\r
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
+\r
+/**\r
+  * @brief   AF 8 selection\r
+  */\r
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 9 selection\r
+  */\r
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */\r
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 10 selection\r
+  */\r
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)\r
+#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */\r
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
+\r
+#if defined(STM32L433xx) || defined(STM32L443xx)\r
+/**\r
+  * @brief   AF 11 selection\r
+  */\r
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */\r
+#endif /* STM32L433xx || STM32L443xx */\r
+\r
+/**\r
+  * @brief   AF 12 selection\r
+  */\r
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */\r
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 13 selection\r
+  */\r
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 14 selection\r
+  */\r
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 15 selection\r
+  */\r
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
+\r
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
+\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/\r
+/**\r
+  * @brief   AF 0 selection\r
+  */\r
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
+\r
+/**\r
+  * @brief   AF 1 selection\r
+  */\r
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 2 selection\r
+  */\r
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 3 selection\r
+  */\r
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping     */\r
+#define GPIO_AF3_CAN1          ((uint8_t)0x03)  /* CAN1 Alternate Function mapping  */\r
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 4 selection\r
+  */\r
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 5 selection\r
+  */\r
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
+#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 6 selection\r
+  */\r
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
+#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 7 selection\r
+  */\r
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
+\r
+/**\r
+  * @brief   AF 8 selection\r
+  */\r
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping  */\r
+\r
+\r
+/**\r
+  * @brief   AF 9 selection\r
+  */\r
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 10 selection\r
+  */\r
+#if defined(STM32L452xx) || defined(STM32L462xx)\r
+#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */\r
+#endif /* STM32L452xx || STM32L462xx */\r
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF10_CAN1         ((uint8_t)0x0A)  /* CAN1 Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 11 selection\r
+  */\r
+\r
+/**\r
+  * @brief   AF 12 selection\r
+  */\r
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 13 selection\r
+  */\r
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 14 selection\r
+  */\r
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */\r
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 15 selection\r
+  */\r
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
+\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/\r
+/**\r
+  * @brief   AF 0 selection\r
+  */\r
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
+#if defined(STM32L476xx) || defined(STM32L486xx)\r
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                        */\r
+#endif /* STM32L476xx || STM32L486xx */\r
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
+\r
+/**\r
+  * @brief   AF 1 selection\r
+  */\r
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */\r
+#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 2 selection\r
+  */\r
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 3 selection\r
+  */\r
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\r
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 4 selection\r
+  */\r
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 5 selection\r
+  */\r
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 6 selection\r
+  */\r
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 7 selection\r
+  */\r
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
+\r
+/**\r
+  * @brief   AF 8 selection\r
+  */\r
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */\r
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
+\r
+\r
+/**\r
+  * @brief   AF 9 selection\r
+  */\r
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 10 selection\r
+  */\r
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\r
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
+\r
+#if defined(STM32L476xx) || defined(STM32L486xx)\r
+/**\r
+  * @brief   AF 11 selection\r
+  */\r
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */\r
+#endif /* STM32L476xx || STM32L486xx */\r
+\r
+/**\r
+  * @brief   AF 12 selection\r
+  */\r
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */\r
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */\r
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 13 selection\r
+  */\r
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
+#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */\r
+#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 14 selection\r
+  */\r
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */\r
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 15 selection\r
+  */\r
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
+\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
+\r
+#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
+/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/\r
+/**\r
+  * @brief   AF 0 selection\r
+  */\r
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
+\r
+/**\r
+  * @brief   AF 1 selection\r
+  */\r
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */\r
+#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 2 selection\r
+  */\r
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\r
+#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 3 selection\r
+  */\r
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\r
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_CAN2          ((uint8_t)0x03)  /* CAN2 Alternate Function mapping    */\r
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */\r
+#define GPIO_AF3_QUADSPI       ((uint8_t)0x03)  /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF3_SPI2          ((uint8_t)0x03)  /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 4 selection\r
+  */\r
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */\r
+#define GPIO_AF4_DCMI          ((uint8_t)0x04)  /* DCMI Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 5 selection\r
+  */\r
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
+#define GPIO_AF5_DCMI          ((uint8_t)0x05)  /* DCMI Alternate Function mapping   */\r
+#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping */\r
+#define GPIO_AF5_QUADSPI       ((uint8_t)0x05)  /* QUADSPI Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 6 selection\r
+  */\r
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
+#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /* I2C3 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 7 selection\r
+  */\r
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
+\r
+/**\r
+  * @brief   AF 8 selection\r
+  */\r
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */\r
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
+#define GPIO_AF8_CAN2          ((uint8_t)0x08)  /* CAN2 Alternate Function mapping    */\r
+\r
+/**\r
+  * @brief   AF 9 selection\r
+  */\r
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 10 selection\r
+  */\r
+#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\r
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF10_CAN2         ((uint8_t)0x0A)  /* CAN2 Alternate Function mapping */\r
+#define GPIO_AF10_DCMI         ((uint8_t)0x0A)  /* DCMI Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 11 selection\r
+  */\r
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 12 selection\r
+  */\r
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */\r
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */\r
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
+#define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+#define GPIO_AF12_TIM8_COMP2   ((uint8_t)0x0C)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 13 selection\r
+  */\r
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
+#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */\r
+#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 14 selection\r
+  */\r
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */\r
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 15 selection\r
+  */\r
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
+\r
+#endif /* STM32L496xx || STM32L4A6xx */\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+/*---STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx--*/\r
+/**\r
+  * @brief   AF 0 selection\r
+  */\r
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
+\r
+/**\r
+  * @brief   AF 1 selection\r
+  */\r
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */\r
+#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 2 selection\r
+  */\r
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 3 selection\r
+  */\r
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping   */\r
+#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OctoSPI Manager Port 1 Alternate Function mapping */\r
+#define GPIO_AF3_SAI1          ((uint8_t)0x03)  /* SAI1 Alternate Function mapping */\r
+#define GPIO_AF3_SPI2          ((uint8_t)0x03)  /* SPI2 Alternate Function mapping   */\r
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */\r
+#define GPIO_AF3_TIM8_COMP1    ((uint8_t)0x03)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_TIM8_COMP2    ((uint8_t)0x03)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 4 selection\r
+  */\r
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */\r
+#define GPIO_AF4_DCMI          ((uint8_t)0x04)  /* DCMI Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 5 selection\r
+  */\r
+#define GPIO_AF5_DCMI          ((uint8_t)0x05)  /* DCMI Alternate Function mapping     */\r
+#define GPIO_AF5_DFSDM1        ((uint8_t)0x05)  /* DFSDM1 Alternate Function mapping   */\r
+#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping     */\r
+#define GPIO_AF5_OCTOSPIM_P1   ((uint8_t)0x05)  /* OctoSPI Manager Port 1 Alternate Function mapping */\r
+#define GPIO_AF5_OCTOSPIM_P2   ((uint8_t)0x05)  /* OctoSPI Manager Port 2 Alternate Function mapping */\r
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping     */\r
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping     */\r
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping     */\r
+\r
+/**\r
+  * @brief   AF 6 selection\r
+  */\r
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
+#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /* I2C3 Alternate Function mapping   */\r
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 7 selection\r
+  */\r
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */\r
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */\r
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 8 selection\r
+  */\r
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
+#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping  */\r
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 9 selection\r
+  */\r
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping  */\r
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 10 selection\r
+  */\r
+#define GPIO_AF10_DCMI         ((uint8_t)0x0A)  /* DCMI Alternate Function mapping     */\r
+#define GPIO_AF10_OCTOSPIM_P1  ((uint8_t)0x0A)  /* OctoSPI Manager Port 1 Alternate Function mapping */\r
+#define GPIO_AF10_OCTOSPIM_P2  ((uint8_t)0x0A)  /* OctoSPI Manager Port 2 Alternate Function mapping */\r
+#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 11 selection\r
+  */\r
+#define GPIO_AF11_DSI          ((uint8_t)0x0B)  /* DSI Alternate Function mapping  */\r
+#define GPIO_AF11_LTDC         ((uint8_t)0x0B)  /* LTDC Alternate Function mapping */\r
+\r
+/**\r
+  * @brief   AF 12 selection\r
+  */\r
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
+#define GPIO_AF12_DSI          ((uint8_t)0x0C)  /* DSI Alternate Function mapping     */\r
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */\r
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
+#define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
+#define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
+#define GPIO_AF12_TIM8_COMP2   ((uint8_t)0x0C)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 13 selection\r
+  */\r
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
+#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */\r
+#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
+\r
+/**\r
+  * @brief   AF 14 selection\r
+  */\r
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping  */\r
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping  */\r
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping  */\r
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
+#define GPIO_AF14_TIM8_COMP2   ((uint8_t)0x0E)  /* TIM8/COMP2 Break in Alternate Function mapping   */\r
+\r
+/**\r
+  * @brief   AF 15 selection\r
+  */\r
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index\r
+* @{\r
+  */\r
+#if defined(STM32L412xx) || defined(STM32L422xx)\r
+\r
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
+                                      ((__GPIOx__) == (GPIOD))? 3uL : 7uL)\r
+\r
+#endif /* STM32L412xx || STM32L422xx */\r
+\r
+#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)\r
+\r
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
+                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
+                                      ((__GPIOx__) == (GPIOE))? 4uL : 7uL)\r
+\r
+#endif /* STM32L431xx || STM32L433xx || STM32L443xx */\r
+\r
+#if defined(STM32L432xx) || defined(STM32L442xx)\r
+\r
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
+                                      ((__GPIOx__) == (GPIOC))? 2uL : 7uL)\r
+\r
+#endif /* STM32L432xx || STM32L442xx */\r
+\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+\r
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
+                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
+                                      ((__GPIOx__) == (GPIOE))? 4uL : 7uL)\r
+\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+\r
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
+                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
+                                      ((__GPIOx__) == (GPIOE))? 4uL :\\r
+                                      ((__GPIOx__) == (GPIOF))? 5uL :\\r
+                                      ((__GPIOx__) == (GPIOG))? 6uL : 7uL)\r
+\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
+\r
+#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
+\r
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
+                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
+                                      ((__GPIOx__) == (GPIOE))? 4uL :\\r
+                                      ((__GPIOx__) == (GPIOF))? 5uL :\\r
+                                      ((__GPIOx__) == (GPIOG))? 6uL :\\r
+                                      ((__GPIOx__) == (GPIOH))? 7uL : 8uL)\r
+\r
+#endif /* STM32L496xx || STM32L4A6xx */\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+\r
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
+                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
+                                      ((__GPIOx__) == (GPIOE))? 4uL :\\r
+                                      ((__GPIOx__) == (GPIOF))? 5uL :\\r
+                                      ((__GPIOx__) == (GPIOG))? 6uL :\\r
+                                      ((__GPIOx__) == (GPIOH))? 7uL : 8uL)\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_GPIO_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
new file mode 100644 (file)
index 0000000..d69ccd1
--- /dev/null
@@ -0,0 +1,782 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_i2c.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of I2C HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_I2C_H\r
+#define STM32L4xx_HAL_I2C_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup I2C\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup I2C_Exported_Types I2C Exported Types\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r
+  * @brief  I2C Configuration Structure definition\r
+  * @{\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.\r
+                                  This parameter calculated by referring to I2C initialization\r
+                                         section in Reference manual */\r
+\r
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.\r
+                                  This parameter can be a 7-bit or 10-bit address. */\r
+\r
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */\r
+\r
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.\r
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */\r
+\r
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected\r
+                                  This parameter can be a 7-bit address. */\r
+\r
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected\r
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */\r
+\r
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.\r
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */\r
+\r
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.\r
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */\r
+\r
+} I2C_InitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_state_structure_definition HAL state structure definition\r
+  * @brief  HAL State structure definition\r
+  * @note  HAL I2C State value coding follow below described bitmap :\n\r
+  *          b7-b6  Error information\n\r
+  *             00 : No Error\n\r
+  *             01 : Abort (Abort user request on going)\n\r
+  *             10 : Timeout\n\r
+  *             11 : Error\n\r
+  *          b5     Peripheral initialization status\n\r
+  *             0  : Reset (peripheral not initialized)\n\r
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n\r
+  *          b4     (not used)\n\r
+  *             x  : Should be set to 0\n\r
+  *          b3\n\r
+  *             0  : Ready or Busy (No Listen mode ongoing)\n\r
+  *             1  : Listen (peripheral in Address Listen Mode)\n\r
+  *          b2     Intrinsic process state\n\r
+  *             0  : Ready\n\r
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n\r
+  *          b1     Rx state\n\r
+  *             0  : Ready (no Rx operation ongoing)\n\r
+  *             1  : Busy (Rx operation ongoing)\n\r
+  *          b0     Tx state\n\r
+  *             0  : Ready (no Tx operation ongoing)\n\r
+  *             1  : Busy (Tx operation ongoing)\r
+  * @{\r
+  */\r
+typedef enum\r
+{\r
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */\r
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */\r
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */\r
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */\r
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */\r
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */\r
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission\r
+                                                 process is ongoing                         */\r
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception\r
+                                                 process is ongoing                         */\r
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */\r
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */\r
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */\r
+\r
+} HAL_I2C_StateTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition\r
+  * @brief  HAL Mode structure definition\r
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n\r
+  *          b7     (not used)\n\r
+  *             x  : Should be set to 0\n\r
+  *          b6\n\r
+  *             0  : None\n\r
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n\r
+  *          b5\n\r
+  *             0  : None\n\r
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n\r
+  *          b4\n\r
+  *             0  : None\n\r
+  *             1  : Master (HAL I2C communication is in Master Mode)\n\r
+  *          b3-b2-b1-b0  (not used)\n\r
+  *             xxxx : Should be set to 0000\r
+  * @{\r
+  */\r
+typedef enum\r
+{\r
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */\r
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */\r
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */\r
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */\r
+\r
+} HAL_I2C_ModeTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r
+  * @brief  I2C Error Code definition\r
+  * @{\r
+  */\r
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */\r
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */\r
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */\r
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */\r
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */\r
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */\r
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */\r
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */\r
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\r
+  * @brief  I2C handle Structure definition\r
+  * @{\r
+  */\r
+typedef struct __I2C_HandleTypeDef\r
+{\r
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */\r
+\r
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */\r
+\r
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */\r
+\r
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */\r
+\r
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */\r
+\r
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can\r
+                                                  be a value of @ref I2C_XFEROPTIONS */\r
+\r
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */\r
+\r
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */\r
+\r
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */\r
+\r
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */\r
+\r
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */\r
+\r
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */\r
+\r
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */\r
+\r
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */\r
+\r
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */\r
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */\r
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */\r
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */\r
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */\r
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */\r
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */\r
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */\r
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */\r
+\r
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */\r
+\r
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */\r
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */\r
+\r
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+} I2C_HandleTypeDef;\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  HAL I2C Callback ID enumeration definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */\r
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */\r
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */\r
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */\r
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */\r
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */\r
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */\r
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */\r
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */\r
+\r
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */\r
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */\r
+\r
+} HAL_I2C_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  HAL I2C Callback pointer definition\r
+  */\r
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */\r
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */\r
+\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Constants I2C Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options\r
+  * @{\r
+  */\r
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)\r
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)\r
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)\r
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)\r
+\r
+/* List of XferOptions in usage of :\r
+ * 1- Restart condition in all use cases (direction change or not)\r
+ */\r
+#define  I2C_OTHER_FRAME                (0x000000AAU)\r
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode\r
+  * @{\r
+  */\r
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)\r
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode\r
+  * @{\r
+  */\r
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)\r
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks\r
+  * @{\r
+  */\r
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)\r
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)\r
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)\r
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)\r
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)\r
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)\r
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)\r
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode\r
+  * @{\r
+  */\r
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)\r
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode\r
+  * @{\r
+  */\r
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)\r
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size\r
+  * @{\r
+  */\r
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)\r
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View\r
+  * @{\r
+  */\r
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)\r
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode\r
+  * @{\r
+  */\r
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD\r
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND\r
+#define  I2C_SOFTEND_MODE               (0x00000000U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode\r
+  * @{\r
+  */\r
+#define  I2C_NO_STARTSTOP               (0x00000000U)\r
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)\r
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)\r
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r
+  * @brief I2C Interrupt definition\r
+  *        Elements values convention: 0xXXXXXXXX\r
+  *           - XXXXXXXX  : Interrupt control mask\r
+  * @{\r
+  */\r
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE\r
+#define I2C_IT_TCI                      I2C_CR1_TCIE\r
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE\r
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE\r
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE\r
+#define I2C_IT_RXI                      I2C_CR1_RXIE\r
+#define I2C_IT_TXI                      I2C_CR1_TXIE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Flag_definition I2C Flag definition\r
+  * @{\r
+  */\r
+#define I2C_FLAG_TXE                    I2C_ISR_TXE\r
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS\r
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE\r
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR\r
+#define I2C_FLAG_AF                     I2C_ISR_NACKF\r
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF\r
+#define I2C_FLAG_TC                     I2C_ISR_TC\r
+#define I2C_FLAG_TCR                    I2C_ISR_TCR\r
+#define I2C_FLAG_BERR                   I2C_ISR_BERR\r
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO\r
+#define I2C_FLAG_OVR                    I2C_ISR_OVR\r
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR\r
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT\r
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT\r
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY\r
+#define I2C_FLAG_DIR                    I2C_ISR_DIR\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Macros I2C Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief Reset I2C handle state.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @retval None\r
+  */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \\r
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \\r
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \\r
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \\r
+                                                                  } while(0)\r
+#else\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r
+#endif\r
+\r
+/** @brief  Enable the specified I2C interrupt.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.\r
+  *        This parameter can be one of the following values:\r
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r
+\r
+/** @brief  Disable the specified I2C interrupt.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.\r
+  *        This parameter can be one of the following values:\r
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r
+\r
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r
+  *\r
+  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+  */\r
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief  Check whether the specified I2C flag is set or not.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @param  __FLAG__ specifies the flag to check.\r
+  *        This parameter can be one of the following values:\r
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status\r
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty\r
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)\r
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload\r
+  *            @arg @ref I2C_FLAG_BERR    Bus error\r
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun\r
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy\r
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)\r
+  *\r
+  * @retval The new state of __FLAG__ (SET or RESET).\r
+  */\r
+#define I2C_FLAG_MASK  (0x0001FFFFU)\r
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)\r
+\r
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @param  __FLAG__ specifies the flag to clear.\r
+  *          This parameter can be any combination of the following values:\r
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r
+  *            @arg @ref I2C_FLAG_BERR    Bus error\r
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun\r
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \\r
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))\r
+\r
+/** @brief  Enable the specified I2C peripheral.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))\r
+\r
+/** @brief  Disable the specified I2C peripheral.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.\r
+  * @param  __HANDLE__ specifies the I2C Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include I2C HAL Extended module */\r
+#include "stm32l4xx_hal_i2c_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup I2C_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  * @{\r
+  */\r
+/* Initialization and de-initialization functions******************************/\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r
+\r
+/* Callbacks Register/UnRegister functions  ***********************************/\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);\r
+\r
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+  * @{\r
+  */\r
+/* IO operation functions  ****************************************************/\r
+/******* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r
+\r
+/******* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\r
+\r
+/******* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */\r
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\r
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
+  * @{\r
+  */\r
+/* Peripheral State, Mode and Error functions  *********************************/\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\r
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Constants I2C Private Constants\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Macro I2C Private Macros\r
+  * @{\r
+  */\r
+\r
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\r
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r
+\r
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\r
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r
+\r
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \\r
+                                         ((MASK) == I2C_OA2_MASK01) || \\r
+                                         ((MASK) == I2C_OA2_MASK02) || \\r
+                                         ((MASK) == I2C_OA2_MASK03) || \\r
+                                         ((MASK) == I2C_OA2_MASK04) || \\r
+                                         ((MASK) == I2C_OA2_MASK05) || \\r
+                                         ((MASK) == I2C_OA2_MASK06) || \\r
+                                         ((MASK) == I2C_OA2_MASK07))\r
+\r
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \\r
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))\r
+\r
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\r
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r
+\r
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\r
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r
+\r
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \\r
+                                         ((MODE) == I2C_AUTOEND_MODE) || \\r
+                                         ((MODE) == I2C_SOFTEND_MODE))\r
+\r
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \\r
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \\r
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \\r
+                                         ((REQUEST) == I2C_NO_STARTSTOP))\r
+\r
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \\r
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \\r
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \\r
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \\r
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \\r
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \\r
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))\r
+\r
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \\r
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))\r
+\r
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r
+\r
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))\r
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))\r
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)\r
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))\r
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)\r
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)\r
+\r
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))\r
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))\r
+\r
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\r
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r
+\r
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)\r
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+  * @{\r
+  */\r
+/* Private functions are defined in stm32l4xx_hal_i2c.c file */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32L4xx_HAL_I2C_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
new file mode 100644 (file)
index 0000000..690623d
--- /dev/null
@@ -0,0 +1,173 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_i2c_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of I2C HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_I2C_EX_H\r
+#define STM32L4xx_HAL_I2C_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup I2CEx\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter\r
+  * @{\r
+  */\r
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U\r
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus\r
+  * @{\r
+  */\r
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */\r
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */\r
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */\r
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)\r
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */\r
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */\r
+#else\r
+#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */\r
+#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */\r
+#endif\r
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */\r
+#if defined(SYSCFG_CFGR1_I2C2_FMP)\r
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */\r
+#else\r
+#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */\r
+#endif\r
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */\r
+#if defined(SYSCFG_CFGR1_I2C4_FMP)\r
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_CFGR1_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */\r
+#else\r
+#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions\r
+  * @brief    Extended features functions\r
+  * @{\r
+  */\r
+\r
+/* Peripheral Control functions  ************************************************/\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);\r
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros\r
+  * @{\r
+  */\r
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\r
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r
+\r
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)\r
+\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \\r
+                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \\r
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \\r
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \\r
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \\r
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \\r
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \\r
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)    || \\r
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))\r
+\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions\r
+  * @{\r
+  */\r
+/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_I2C_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h
new file mode 100644 (file)
index 0000000..bc1975a
--- /dev/null
@@ -0,0 +1,1004 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pcd.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of PCD HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_PCD_H\r
+#define STM32L4xx_HAL_PCD_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_ll_usb.h"\r
+\r
+#if defined (USB) || defined (USB_OTG_FS)\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup PCD\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Types PCD Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  PCD State structure definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_PCD_STATE_RESET   = 0x00,\r
+  HAL_PCD_STATE_READY   = 0x01,\r
+  HAL_PCD_STATE_ERROR   = 0x02,\r
+  HAL_PCD_STATE_BUSY    = 0x03,\r
+  HAL_PCD_STATE_TIMEOUT = 0x04\r
+} PCD_StateTypeDef;\r
+\r
+/* Device LPM suspend state */\r
+typedef enum\r
+{\r
+  LPM_L0 = 0x00, /* on */\r
+  LPM_L1 = 0x01, /* LPM L1 sleep */\r
+  LPM_L2 = 0x02, /* suspend */\r
+  LPM_L3 = 0x03, /* off */\r
+} PCD_LPM_StateTypeDef;\r
+\r
+typedef enum\r
+{\r
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */\r
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */\r
+} PCD_LPM_MsgTypeDef;\r
+\r
+typedef enum\r
+{\r
+  PCD_BCD_ERROR                     = 0xFF,\r
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,\r
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,\r
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,\r
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,\r
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,\r
+\r
+} PCD_BCD_MsgTypeDef;\r
+\r
+#if defined (USB)\r
+\r
+#endif /* defined (USB) */\r
+#if defined (USB_OTG_FS)\r
+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;\r
+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;\r
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;\r
+#endif /* defined (USB_OTG_FS) */\r
+#if defined (USB)\r
+typedef USB_TypeDef        PCD_TypeDef;\r
+typedef USB_CfgTypeDef     PCD_InitTypeDef;\r
+typedef USB_EPTypeDef      PCD_EPTypeDef;\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @brief  PCD Handle Structure definition\r
+  */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+typedef struct __PCD_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+{\r
+  PCD_TypeDef             *Instance;   /*!< Register base address              */\r
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */\r
+  __IO uint8_t            USB_Address; /*!< USB Address                        */\r
+#if defined (USB_OTG_FS)\r
+  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */\r
+  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */\r
+#endif /* defined (USB_OTG_FS) */\r
+#if defined (USB)\r
+  PCD_EPTypeDef           IN_ep[8];   /*!< IN endpoint parameters             */\r
+  PCD_EPTypeDef           OUT_ep[8];  /*!< OUT endpoint parameters            */\r
+#endif /* defined (USB) */\r
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */\r
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */\r
+  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */\r
+  uint32_t                Setup[12];   /*!< Setup packet buffer                */\r
+  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */\r
+  uint32_t                BESL;\r
+\r
+\r
+  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .\r
+                                       This parameter can be set to ENABLE or DISABLE        */\r
+\r
+  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.\r
+                                       This parameter can be set to ENABLE or DISABLE        */\r
+  void                    *pData;      /*!< Pointer to upper stack Handler */\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */\r
+  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */\r
+  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */\r
+  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */\r
+  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */\r
+  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */\r
+  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */\r
+\r
+  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */\r
+  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */\r
+  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */\r
+  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */\r
+  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */\r
+  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */\r
+\r
+  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */\r
+  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+} PCD_HandleTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include PCD HAL Extended module */\r
+#include "stm32l4xx_hal_pcd_ex.h"\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Constants PCD Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PCD_Speed PCD Speed\r
+  * @{\r
+  */\r
+#define PCD_SPEED_FULL               USBD_FS_SPEED\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PCD_PHY_Module PCD PHY Module\r
+  * @{\r
+  */\r
+#define PCD_PHY_ULPI                 1U\r
+#define PCD_PHY_EMBEDDED             2U\r
+#define PCD_PHY_UTMI                 3U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition\r
+  * @brief  PCD Error Code definition\r
+  * @{\r
+  */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Macros PCD Exported Macros\r
+ *  @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+#if defined (USB_OTG_FS)\r
+#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)\r
+#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)\r
+\r
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))\r
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)\r
+\r
+\r
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \\r
+                                                          ~(USB_OTG_PCGCCTL_STOPCLK)\r
+\r
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK\r
+\r
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)\r
+\r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE\r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+#define __HAL_PCD_ENABLE(__HANDLE__)                                  (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)\r
+#define __HAL_PCD_DISABLE(__HANDLE__)                                 (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)\r
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))\r
+\r
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE\r
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions\r
+  * @{\r
+  */\r
+\r
+/* Initialization/de-initialization functions  ********************************/\r
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition\r
+  * @brief  HAL USB OTG PCD Callback ID enumeration definition\r
+  * @{\r
+  */\r
+typedef enum\r
+{\r
+  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */\r
+  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */\r
+  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */\r
+  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */\r
+  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */\r
+  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */\r
+  HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */\r
+\r
+  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */\r
+  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */\r
+\r
+} HAL_PCD_CallbackIDTypeDef;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition\r
+  * @brief  HAL USB OTG PCD Callback pointer definition\r
+  * @{\r
+  */\r
+\r
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */\r
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */\r
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */\r
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */\r
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */\r
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */\r
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);\r
+\r
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);\r
+\r
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);\r
+\r
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);\r
+\r
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);\r
+\r
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);\r
+\r
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* I/O operation functions  ***************************************************/\r
+/* Non-Blocking mode: Interrupt */\r
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);\r
+\r
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);\r
+\r
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Peripheral Control functions  **********************************************/\r
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);\r
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);\r
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r
+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Peripheral State functions  ************************************************/\r
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions\r
+  * @{\r
+  */\r
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup PCD_Private_Constants PCD Private Constants\r
+  * @{\r
+  */\r
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt\r
+  * @{\r
+  */\r
+#if defined (USB_OTG_FS)\r
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U\r
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU\r
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U\r
+\r
+#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 17)  /*!< USB FS EXTI Line WakeUp Interrupt */\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+#define  USB_WAKEUP_EXTI_LINE                                         (0x1U << 17)  /*!< USB FS EXTI Line WakeUp Interrupt */\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#if defined (USB)\r
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS\r
+  * @{\r
+  */\r
+#define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64\r
+#define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32\r
+#define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16\r
+#define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PCD_ENDP PCD ENDP\r
+  * @{\r
+  */\r
+#define PCD_ENDP0                                                     0U\r
+#define PCD_ENDP1                                                     1U\r
+#define PCD_ENDP2                                                     2U\r
+#define PCD_ENDP3                                                     3U\r
+#define PCD_ENDP4                                                     4U\r
+#define PCD_ENDP5                                                     5U\r
+#define PCD_ENDP6                                                     6U\r
+#define PCD_ENDP7                                                     7U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind\r
+  * @{\r
+  */\r
+#define PCD_SNG_BUF                                                   0U\r
+#define PCD_DBL_BUF                                                   1U\r
+/**\r
+  * @}\r
+  */\r
+#endif /* defined (USB) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined (USB_OTG_FS)\r
+#ifndef USB_OTG_DOEPINT_OTEPSPR\r
+#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */\r
+#endif\r
+\r
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM\r
+#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */\r
+#endif\r
+\r
+#ifndef USB_OTG_DOEPINT_NAK\r
+#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */\r
+#endif\r
+\r
+#ifndef USB_OTG_DOEPMSK_NAKM\r
+#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */\r
+#endif\r
+\r
+#ifndef USB_OTG_DOEPINT_STPKTRX\r
+#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */\r
+#endif\r
+\r
+#ifndef USB_OTG_DOEPMSK_NYETM\r
+#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */\r
+#endif\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PCD_Private_Macros PCD Private Macros\r
+ * @{\r
+ */\r
+#if defined (USB)\r
+/********************  Bit definition for USB_COUNTn_RX register  *************/\r
+#define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)\r
+#define USB_CNTRX_BLSIZE                      (0x1U << 15)\r
+\r
+/* SetENDPOINT */\r
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue)  (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))\r
+\r
+/* GetENDPOINT */\r
+#define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))\r
+\r
+/* ENDPOINT transfer */\r
+#define USB_EP0StartXfer                          USB_EPStartXfer\r
+\r
+/**\r
+  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wType Endpoint Type.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \\r
+                                             ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))\r
+\r
+/**\r
+  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval Endpoint Type\r
+  */\r
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)\r
+\r
+/**\r
+  * @brief free buffer used from the application realizing it to the line\r
+  *         toggles bit SW_BUF in the double buffered endpoint register\r
+  * @param USBx USB device.\r
+  * @param   bEpNum, bDir\r
+  * @retval None\r
+  */\r
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \\r
+  if ((bDir) == 0U) \\r
+  { \\r
+    /* OUT double buffered endpoint */ \\r
+    PCD_TX_DTOG((USBx), (bEpNum)); \\r
+  } \\r
+  else if ((bDir) == 1U) \\r
+  { \\r
+    /* IN double buffered endpoint */ \\r
+    PCD_RX_DTOG((USBx), (bEpNum)); \\r
+  } \\r
+} while(0)\r
+\r
+/**\r
+  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wState new state\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \\r
+   register uint16_t _wRegVal; \\r
+   \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \\r
+   /* toggle first bit ? */ \\r
+   if ((USB_EPTX_DTOG1 & (wState))!= 0U) \\r
+   { \\r
+      _wRegVal ^= USB_EPTX_DTOG1; \\r
+   } \\r
+   /* toggle second bit ?  */ \\r
+   if ((USB_EPTX_DTOG2 & (wState))!= 0U) \\r
+   { \\r
+      _wRegVal ^= USB_EPTX_DTOG2; \\r
+   } \\r
+   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
+  } while(0) /* PCD_SET_EP_TX_STATUS */\r
+\r
+/**\r
+  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wState new state\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \\r
+    /* toggle first bit ? */ \\r
+    if ((USB_EPRX_DTOG1 & (wState))!= 0U) \\r
+    { \\r
+       _wRegVal ^= USB_EPRX_DTOG1; \\r
+    } \\r
+    /* toggle second bit ? */ \\r
+    if ((USB_EPRX_DTOG2 & (wState))!= 0U) \\r
+    { \\r
+       _wRegVal ^= USB_EPRX_DTOG2; \\r
+    } \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
+  } while(0) /* PCD_SET_EP_RX_STATUS */\r
+\r
+/**\r
+  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wStaterx new state.\r
+  * @param  wStatetx new state.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \\r
+    /* toggle first bit ? */ \\r
+    if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \\r
+    { \\r
+      _wRegVal ^= USB_EPRX_DTOG1; \\r
+    } \\r
+    /* toggle second bit ? */ \\r
+    if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \\r
+    { \\r
+      _wRegVal ^= USB_EPRX_DTOG2; \\r
+    } \\r
+    /* toggle first bit ? */ \\r
+    if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \\r
+    { \\r
+      _wRegVal ^= USB_EPTX_DTOG1; \\r
+    } \\r
+    /* toggle second bit ?  */ \\r
+    if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \\r
+    { \\r
+      _wRegVal ^= USB_EPTX_DTOG2; \\r
+    } \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
+  } while(0) /* PCD_SET_EP_TXRX_STATUS */\r
+\r
+/**\r
+  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]\r
+  *         /STAT_RX[1:0])\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval status\r
+  */\r
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)\r
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)\r
+\r
+/**\r
+  * @brief  sets directly the VALID tx/rx-status into the endpoint register\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))\r
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))\r
+\r
+/**\r
+  * @brief  checks stall condition in an endpoint.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval TRUE = endpoint in stall condition.\r
+  */\r
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \\r
+                                   == USB_EP_TX_STALL)\r
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \\r
+                                   == USB_EP_RX_STALL)\r
+\r
+/**\r
+  * @brief  set & clear EP_KIND bit.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_KIND(USBx, bEpNum) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \\r
+  } while(0) /* PCD_SET_EP_KIND */\r
+\r
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
+  } while(0) /* PCD_CLEAR_EP_KIND */\r
+\r
+/**\r
+  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))\r
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))\r
+\r
+/**\r
+  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))\r
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))\r
+\r
+/**\r
+  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \\r
+  } while(0) /* PCD_CLEAR_RX_EP_CTR */\r
+\r
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \\r
+  } while(0) /* PCD_CLEAR_TX_EP_CTR */\r
+\r
+/**\r
+  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_RX_DTOG(USBx, bEpNum) do { \\r
+    register uint16_t _wEPVal; \\r
+    \\r
+    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \\r
+  } while(0) /* PCD_RX_DTOG */\r
+\r
+#define PCD_TX_DTOG(USBx, bEpNum) do { \\r
+    register uint16_t _wEPVal; \\r
+    \\r
+    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \\r
+  } while(0) /* PCD_TX_DTOG */\r
+/**\r
+  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \\r
+    \\r
+    if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\\r
+    { \\r
+      PCD_RX_DTOG((USBx), (bEpNum)); \\r
+    } \\r
+  } while(0) /* PCD_CLEAR_RX_DTOG */\r
+\r
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \\r
+    \\r
+    if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\\r
+    { \\r
+      PCD_TX_DTOG((USBx), (bEpNum)); \\r
+    } \\r
+  } while(0) /* PCD_CLEAR_TX_DTOG */\r
+\r
+/**\r
+  * @brief  Sets address in an endpoint register.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  bAddr Address.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \\r
+    register uint16_t _wRegVal; \\r
+    \\r
+    _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \\r
+    \\r
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
+  } while(0) /* PCD_SET_EP_ADDRESS */\r
+\r
+/**\r
+  * @brief  Gets address in an endpoint register.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))\r
+\r
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))\r
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))\r
+\r
+/**\r
+  * @brief  sets address of the tx/rx buffer.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wAddr address to be set (must be word aligned).\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \\r
+  register uint16_t *_wRegVal; \\r
+  register uint32_t _wRegBase = (uint32_t)USBx; \\r
+  \\r
+  _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
+  _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \\r
+  *_wRegVal = ((wAddr) >> 1) << 1; \\r
+} while(0) /* PCD_SET_EP_TX_ADDRESS */\r
+\r
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \\r
+  register uint16_t *_wRegVal; \\r
+  register uint32_t _wRegBase = (uint32_t)USBx; \\r
+  \\r
+  _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
+  _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \\r
+  *_wRegVal = ((wAddr) >> 1) << 1; \\r
+} while(0) /* PCD_SET_EP_RX_ADDRESS */\r
+\r
+/**\r
+  * @brief  Gets address of the tx/rx buffer.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval address of the buffer.\r
+  */\r
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))\r
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))\r
+\r
+/**\r
+  * @brief  Sets counter of rx buffer with no. of blocks.\r
+  * @param  pdwReg Register pointer\r
+  * @param  wCount Counter.\r
+  * @param  wNBlocks no. of Blocks.\r
+  * @retval None\r
+  */\r
+#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \\r
+    (wNBlocks) = (wCount) >> 5; \\r
+    *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \\r
+  } while(0) /* PCD_CALC_BLK32 */\r
+\r
+#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \\r
+    (wNBlocks) = (wCount) >> 1; \\r
+    if (((wCount) & 0x1U) != 0U) \\r
+    { \\r
+      (wNBlocks)++; \\r
+    } \\r
+    *(pdwReg) = (uint16_t)((wNBlocks) << 10); \\r
+  } while(0) /* PCD_CALC_BLK2 */\r
+\r
+#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount)  do { \\r
+    uint32_t wNBlocks; \\r
+    if ((wCount) == 0U) \\r
+    { \\r
+      *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \\r
+      *(pdwReg) |= USB_CNTRX_BLSIZE; \\r
+    } \\r
+    else if((wCount) < 62U) \\r
+    { \\r
+      PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \\r
+    } \\r
+    else \\r
+    { \\r
+      PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \\r
+    } \\r
+  } while(0) /* PCD_SET_EP_CNT_RX_REG */\r
+\r
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \\r
+     register uint32_t _wRegBase = (uint32_t)(USBx); \\r
+     uint16_t *pdwReg; \\r
+     \\r
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
+    pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \\r
+    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  sets counter for the tx/rx buffer.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wCount Counter value.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \\r
+    register uint32_t _wRegBase = (uint32_t)(USBx); \\r
+    uint16_t *_wRegVal; \\r
+    \\r
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
+    _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \\r
+    *_wRegVal = (uint16_t)(wCount); \\r
+} while(0)\r
+\r
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \\r
+    register uint32_t _wRegBase = (uint32_t)(USBx); \\r
+    uint16_t *_wRegVal; \\r
+    \\r
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
+    _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \\r
+    PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \\r
+} while(0)\r
+\r
+/**\r
+  * @brief  gets counter of the tx buffer.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval Counter value\r
+  */\r
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)\r
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)\r
+\r
+/**\r
+  * @brief  Sets buffer 0/1 address in a double buffer endpoint.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wBuf0Addr buffer 0 address.\r
+  * @retval Counter value\r
+  */\r
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \\r
+    PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \\r
+  } while(0) /* PCD_SET_EP_DBUF0_ADDR */\r
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \\r
+    PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \\r
+  } while(0) /* PCD_SET_EP_DBUF1_ADDR */\r
+\r
+/**\r
+  * @brief  Sets addresses in a double buffer endpoint.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  wBuf0Addr: buffer 0 address.\r
+  * @param  wBuf1Addr = buffer 1 address.\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \\r
+    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \\r
+    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \\r
+  } while(0) /* PCD_SET_EP_DBUF_ADDR */\r
+\r
+/**\r
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))\r
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))\r
+\r
+/**\r
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @param  bDir endpoint dir  EP_DBUF_OUT = OUT\r
+  *         EP_DBUF_IN  = IN\r
+  * @param  wCount: Counter value\r
+  * @retval None\r
+  */\r
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \\r
+    if ((bDir) == 0U) \\r
+      /* OUT endpoint */ \\r
+    { \\r
+      PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \\r
+    } \\r
+    else \\r
+    { \\r
+      if ((bDir) == 1U) \\r
+      { \\r
+        /* IN endpoint */ \\r
+        PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \\r
+      } \\r
+    } \\r
+  } while(0) /* SetEPDblBuf0Count*/\r
+\r
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \\r
+    register uint32_t _wBase = (uint32_t)(USBx); \\r
+    uint16_t *_wEPRegVal; \\r
+    \\r
+    if ((bDir) == 0U) \\r
+    { \\r
+      /* OUT endpoint */ \\r
+      PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \\r
+    } \\r
+    else \\r
+    { \\r
+      if ((bDir) == 1U) \\r
+      { \\r
+        /* IN endpoint */ \\r
+        _wBase += (uint32_t)(USBx)->BTABLE; \\r
+        _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \\r
+        *_wEPRegVal = (uint16_t)(wCount); \\r
+      } \\r
+    } \\r
+  } while(0) /* SetEPDblBuf1Count */\r
+\r
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \\r
+    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \\r
+    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \\r
+  } while(0) /* PCD_SET_EP_DBUF_CNT  */\r
+\r
+/**\r
+  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.\r
+  * @param  USBx USB peripheral instance register address.\r
+  * @param  bEpNum Endpoint Number.\r
+  * @retval None\r
+  */\r
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))\r
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))\r
+\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* defined (USB) || defined (USB_OTG_FS) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_PCD_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h
new file mode 100644 (file)
index 0000000..ac1529e
--- /dev/null
@@ -0,0 +1,97 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pcd_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of PCD HAL Extension module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_PCD_EX_H\r
+#define STM32L4xx_HAL_PCD_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+#if defined (USB) || defined (USB_OTG_FS)\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup PCDEx\r
+  * @{\r
+  */\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions\r
+  * @{\r
+  */\r
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r
+  * @{\r
+  */\r
+\r
+#if defined (USB_OTG_FS)\r
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);\r
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,\r
+                                       uint16_t ep_addr,\r
+                                       uint16_t ep_kind,\r
+                                       uint32_t pmaadress);\r
+#endif /* defined (USB) */\r
+\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);\r
+\r
+\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);\r
+\r
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);\r
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* defined (USB) || defined (USB_OTG_FS) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32L4xx_HAL_PCD_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
new file mode 100644 (file)
index 0000000..1e20ff7
--- /dev/null
@@ -0,0 +1,414 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pwr.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of PWR HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_PWR_H\r
+#define __STM32L4xx_HAL_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup PWR\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Types PWR Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  PWR PVD configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.\r
+                            This parameter can be a value of @ref PWR_PVD_detection_level. */\r
+\r
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.\r
+                           This parameter can be a value of @ref PWR_PVD_Mode. */\r
+}PWR_PVDTypeDef;\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
+  * @{\r
+  */\r
+\r
+\r
+/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels\r
+  * @{\r
+  */\r
+#define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */\r
+#define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */\r
+#define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */\r
+#define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */\r
+#define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */\r
+#define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */\r
+#define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */\r
+#define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode\r
+  * @{\r
+  */\r
+#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */\r
+#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+\r
+\r
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode\r
+  * @{\r
+  */\r
+#define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */\r
+#define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry\r
+  * @{\r
+  */\r
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */\r
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry\r
+  * @{\r
+  */\r
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */\r
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line\r
+  * @{\r
+  */\r
+#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line\r
+  * @{\r
+  */\r
+#define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Macros  PWR Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Check whether or not a specific PWR flag is set.\r
+  * @param  __FLAG__: specifies the flag to check.\r
+  *           This parameter can be one of the following values:\r
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 1.\r
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 2.\r
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 3.\r
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 4.\r
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 5.\r
+  *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system\r
+  *                  entered StandBy mode.\r
+  *            @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates\r
+  *                 that external switch can be closed to connect to the external SMPS, when the Range 2\r
+  *                 of internal regulator is ready.\r
+  *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on\r
+  *                 the internal wakeup line.\r
+  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the\r
+  *                 low-power regulator is ready.\r
+  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the\r
+  *                 regulator is ready in main mode or is in low-power mode.\r
+  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready\r
+  *                 in the selected voltage range or is still changing to the required voltage level.\r
+  *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is\r
+  *                  below or above the selected PVD threshold.\r
+  *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is\r
+  *                  is below or above PVM1 threshold (applicable when USB feature is supported).\r
+  @if STM32L486xx\r
+  *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is\r
+  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device).\r
+  @endif\r
+  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is\r
+  *                  is below or above PVM3 threshold.\r
+  *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is\r
+  *                  is below or above PVM4 threshold.\r
+  *\r
+  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\\r
+                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\\r
+                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )\r
+\r
+/** @brief  Clear a specific PWR flag.\r
+  * @param  __FLAG__: specifies the flag to clear.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 1.\r
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 2.\r
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 3.\r
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 4.\r
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event\r
+  *                  was received from the WKUP pin 5.\r
+  *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.\r
+  *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system\r
+  *                  entered Standby mode.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\\r
+                                         (PWR->SCR  = (__FLAG__)) :\\r
+                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )\r
+/**\r
+  * @brief Enable the PVD Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+  * @brief Disable the PVD Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+  * @brief Enable the PVD Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)\r
+\r
+/**\r
+  * @brief Disable the PVD Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)\r
+\r
+/**\r
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                   \\r
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                    \\r
+    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Generate a Software interrupt on selected EXTI line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+  * @brief Check whether or not the PVD EXTI interrupt flag is set.\r
+  * @retval EXTI PVD Line Status.\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+  * @brief Clear the PVD EXTI interrupt flag.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @addtogroup  PWR_Private_Macros   PWR Private Macros\r
+  * @{\r
+  */\r
+\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
+\r
+#define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\\r
+                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\\r
+                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\\r
+                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\\r
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\\r
+                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\\r
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))\r
+\r
+#define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
+                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
+\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
+\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include PWR HAL Extended module */\r
+#include "stm32l4xx_hal_pwr_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  * @{\r
+  */\r
+\r
+/* Initialization and de-initialization functions *******************************/\r
+void HAL_PWR_DeInit(void);\r
+void HAL_PWR_EnableBkUpAccess(void);\r
+void HAL_PWR_DisableBkUpAccess(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
+  * @{\r
+  */\r
+\r
+/* Peripheral Control functions  ************************************************/\r
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
+void HAL_PWR_EnablePVD(void);\r
+void HAL_PWR_DisablePVD(void);\r
+\r
+\r
+/* WakeUp pins configuration functions ****************************************/\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
+\r
+/* Low Power modes configuration functions ************************************/\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+void HAL_PWR_EnterSTANDBYMode(void);\r
+\r
+void HAL_PWR_EnableSleepOnExit(void);\r
+void HAL_PWR_DisableSleepOnExit(void);\r
+void HAL_PWR_EnableSEVOnPend(void);\r
+void HAL_PWR_DisableSEVOnPend(void);\r
+\r
+void HAL_PWR_PVDCallback(void);\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32L4xx_HAL_PWR_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
new file mode 100644 (file)
index 0000000..b6364c5
--- /dev/null
@@ -0,0 +1,907 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pwr_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of PWR HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_PWR_EX_H\r
+#define __STM32L4xx_HAL_PWR_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup PWREx\r
+  * @{\r
+  */\r
+\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types\r
+  * @{\r
+  */\r
+\r
+\r
+/**\r
+  * @brief  PWR PVM configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.\r
+                           This parameter can be a value of @ref PWREx_PVM_Type.\r
+                           @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).\r
+@if STM32L486xx\r
+                           @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).\r
+@endif\r
+                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.\r
+                           @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */\r
+\r
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.\r
+                           This parameter can be a value of @ref PWREx_PVM_Mode. */\r
+}PWR_PVMTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants\r
+  * @{\r
+  */\r
+#define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins\r
+  * @{\r
+  */\r
+#define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */\r
+#define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */\r
+#define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */\r
+#define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */\r
+#define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */\r
+#define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type\r
+  * @{\r
+  */\r
+#if defined(PWR_CR2_PVME1)\r
+#define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+#define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */\r
+#endif /* PWR_CR2_PVME2 */\r
+#define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */\r
+#define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode\r
+  * @{\r
+  */\r
+#define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */\r
+#define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+\r
+/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale\r
+  * @{\r
+  */\r
+#if defined(PWR_CR5_R1MODE)\r
+#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST  ((uint32_t)0x00000000)  /*!< Voltage scaling range 1 boost mode  */\r
+#endif\r
+#define PWR_REGULATOR_VOLTAGE_SCALE1        PWR_CR1_VOS_0           /*!< Voltage scaling range 1 normal mode */\r
+#define PWR_REGULATOR_VOLTAGE_SCALE2        PWR_CR1_VOS_1           /*!< Voltage scaling range 2             */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection\r
+  * @{\r
+  */\r
+#define PWR_BATTERY_CHARGING_RESISTOR_5          ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor   */\r
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging\r
+  * @{\r
+  */\r
+#define PWR_BATTERY_CHARGING_DISABLE        ((uint32_t)0x00000000)\r
+#define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode\r
+  * @{\r
+  */\r
+#define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */\r
+#define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */\r
+#define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */\r
+#define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */\r
+#define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */\r
+#define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */\r
+#define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */\r
+#define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */\r
+#define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */\r
+#define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */\r
+#define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */\r
+#define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */\r
+#define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */\r
+#define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */\r
+#define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */\r
+#define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_GPIO GPIO port\r
+  * @{\r
+  */\r
+#define PWR_GPIO_A   0x00000000U      /*!< GPIO port A */\r
+#define PWR_GPIO_B   0x00000001U      /*!< GPIO port B */\r
+#define PWR_GPIO_C   0x00000002U      /*!< GPIO port C */\r
+#if defined(GPIOD_BASE)\r
+#define PWR_GPIO_D   0x00000003U      /*!< GPIO port D */\r
+#endif\r
+#if defined(GPIOE_BASE)\r
+#define PWR_GPIO_E   0x00000004U      /*!< GPIO port E */\r
+#endif\r
+#if defined(GPIOF_BASE)\r
+#define PWR_GPIO_F   0x00000005U      /*!< GPIO port F */\r
+#endif\r
+#if defined(GPIOG_BASE)\r
+#define PWR_GPIO_G   0x00000006U      /*!< GPIO port G */\r
+#endif\r
+#define PWR_GPIO_H   0x00000007U      /*!< GPIO port H */\r
+#if defined(GPIOI_BASE)\r
+#define PWR_GPIO_I   0x00000008U      /*!< GPIO port I */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines\r
+  * @{\r
+  */\r
+#if defined(PWR_CR2_PVME1)\r
+#define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+#define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */\r
+#endif /* PWR_CR2_PVME2 */\r
+#define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */\r
+#define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines\r
+  * @{\r
+  */\r
+#if defined(PWR_CR2_PVME1)\r
+#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */\r
+#endif /* PWR_CR2_PVME2 */\r
+#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */\r
+#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_Flag  PWR Status Flags\r
+  *        Elements values convention: 0000 0000 0XXY YYYYb\r
+  *           - Y YYYY  : Flag position in the XX register (5 bits)\r
+  *           - XX  : Status register (2 bits)\r
+  *                 - 01: SR1 register\r
+  *                 - 10: SR2 register\r
+  *        The only exception is PWR_FLAG_WU, encompassing all\r
+  *        wake-up flags and set to PWR_SR1_WUF.\r
+  * @{\r
+  */\r
+#define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */\r
+#define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */\r
+#define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */\r
+#define PWR_FLAG_WUF4                       ((uint32_t)0x0023)   /*!< Wakeup event on wakeup pin 4 */\r
+#define PWR_FLAG_WUF5                       ((uint32_t)0x0024)   /*!< Wakeup event on wakeup pin 5 */\r
+#define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */\r
+#define PWR_FLAG_SB                         ((uint32_t)0x0028)   /*!< Standby flag */\r
+#if defined(PWR_SR1_EXT_SMPS_RDY)\r
+#define PWR_FLAG_EXT_SMPS                   ((uint32_t)0x002D)   /*!< Switching to external SMPS ready flag */\r
+#endif /* PWR_SR1_EXT_SMPS_RDY */\r
+#define PWR_FLAG_WUFI                       ((uint32_t)0x002F)   /*!< Wakeup on internal wakeup line */\r
+\r
+#define PWR_FLAG_REGLPS                     ((uint32_t)0x0048)   /*!< Low-power regulator start flag */\r
+#define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */\r
+#define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */\r
+#define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */\r
+#if defined(PWR_CR2_PVME1)\r
+#define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+#define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */\r
+#endif /* PWR_CR2_PVME2 */\r
+#define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */\r
+#define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros\r
+ * @{\r
+ */\r
+\r
+#if defined(PWR_CR2_PVME1)\r
+/**\r
+  * @brief Enable the PVM1 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Disable the PVM1 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Enable the PVM1 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Disable the PVM1 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Enable the PVM1 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Disable the PVM1 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Enable the PVM1 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)\r
+\r
+\r
+/**\r
+  * @brief Disable the PVM1 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)\r
+\r
+\r
+/**\r
+  * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                    \\r
+    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                     \\r
+    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Generate a Software interrupt on selected EXTI line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.\r
+  * @retval EXTI PVM1 Line Status.\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)\r
+\r
+/**\r
+  * @brief Clear the PVM1 EXTI flag.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)\r
+\r
+#endif /* PWR_CR2_PVME1 */\r
+\r
+\r
+#if defined(PWR_CR2_PVME2)\r
+/**\r
+  * @brief Enable the PVM2 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Disable the PVM2 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Enable the PVM2 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Disable the PVM2 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Enable the PVM2 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Disable the PVM2 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Enable the PVM2 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)\r
+\r
+\r
+/**\r
+  * @brief Disable the PVM2 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)\r
+\r
+\r
+/**\r
+  * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                    \\r
+    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                     \\r
+    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Generate a Software interrupt on selected EXTI line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.\r
+  * @retval EXTI PVM2 Line Status.\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)\r
+\r
+/**\r
+  * @brief Clear the PVM2 EXTI flag.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)\r
+\r
+#endif /* PWR_CR2_PVME2 */\r
+\r
+\r
+/**\r
+  * @brief Enable the PVM3 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Disable the PVM3 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Enable the PVM3 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Disable the PVM3 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Enable the PVM3 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Disable the PVM3 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Enable the PVM3 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)\r
+\r
+\r
+/**\r
+  * @brief Disable the PVM3 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)\r
+\r
+\r
+/**\r
+  * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                    \\r
+    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                     \\r
+    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Generate a Software interrupt on selected EXTI line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.\r
+  * @retval EXTI PVM3 Line Status.\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)\r
+\r
+/**\r
+  * @brief Clear the PVM3 EXTI flag.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)\r
+\r
+\r
+\r
+\r
+/**\r
+  * @brief Enable the PVM4 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Disable the PVM4 Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Enable the PVM4 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Disable the PVM4 Event Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Enable the PVM4 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Disable the PVM4 Extended Interrupt Rising Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Enable the PVM4 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)\r
+\r
+\r
+/**\r
+  * @brief Disable the PVM4 Extended Interrupt Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)\r
+\r
+\r
+/**\r
+  * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                    \\r
+    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                     \\r
+    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \\r
+    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Generate a Software interrupt on selected EXTI line.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.\r
+  * @retval EXTI PVM4 Line Status.\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)\r
+\r
+/**\r
+  * @brief Clear the PVM4 EXTI flag.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)\r
+\r
+\r
+/**\r
+  * @brief Configure the main internal regulator output voltage.\r
+  * @param  __REGULATOR__: specifies the regulator output voltage to achieve\r
+  *         a tradeoff between performance and power consumption.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,\r
+  *                                                typical output voltage at 1.2 V,\r
+  *                                                system frequency up to 80 MHz.\r
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,\r
+  *                                                typical output voltage at 1.0 V,\r
+  *                                                system frequency up to 26 MHz.\r
+  * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check\r
+  *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User\r
+  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.\r
+  * @retval None\r
+  */\r
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \\r
+                                                            __IO uint32_t tmpreg;                               \\r
+                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \\r
+                                                            /* Delay after an RCC peripheral clock enabling */  \\r
+                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \\r
+                                                            UNUSED(tmpreg);                                     \\r
+                                                          } while(0)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros\r
+  * @{\r
+  */\r
+\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN2) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN3) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN4) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN5) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \\r
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW))\r
+\r
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx)                                                   || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\\r
+                               ((TYPE) == PWR_PVM_2) ||\\r
+                               ((TYPE) == PWR_PVM_3) ||\\r
+                               ((TYPE) == PWR_PVM_4))\r
+#elif defined (STM32L471xx)\r
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\\r
+                               ((TYPE) == PWR_PVM_3) ||\\r
+                               ((TYPE) == PWR_PVM_4))\r
+#endif\r
+\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\\r
+                               ((TYPE) == PWR_PVM_3) ||\\r
+                               ((TYPE) == PWR_PVM_4))\r
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)\r
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\\r
+                               ((TYPE) == PWR_PVM_4))\r
+#endif\r
+\r
+#define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\\r
+                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\\r
+                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\\r
+                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\\r
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\\r
+                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\\r
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))\r
+\r
+#if defined(PWR_CR5_R1MODE)\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \\r
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1)       || \\r
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))\r
+#else\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\r
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))\r
+#endif\r
+\r
+\r
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\\r
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))\r
+\r
+#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\\r
+                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))\r
+\r
+#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)\r
+\r
+\r
+#if defined (STM32L412xx) || defined (STM32L422xx)\r
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
+                           ((GPIO) == PWR_GPIO_B) ||\\r
+                           ((GPIO) == PWR_GPIO_C) ||\\r
+                           ((GPIO) == PWR_GPIO_D) ||\\r
+                           ((GPIO) == PWR_GPIO_H))\r
+#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \\r
+      defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
+                           ((GPIO) == PWR_GPIO_B) ||\\r
+                           ((GPIO) == PWR_GPIO_C) ||\\r
+                           ((GPIO) == PWR_GPIO_D) ||\\r
+                           ((GPIO) == PWR_GPIO_E) ||\\r
+                           ((GPIO) == PWR_GPIO_H))\r
+#elif defined (STM32L432xx) || defined (STM32L442xx)\r
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
+                           ((GPIO) == PWR_GPIO_B) ||\\r
+                           ((GPIO) == PWR_GPIO_C) ||\\r
+                           ((GPIO) == PWR_GPIO_H))\r
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)\r
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
+                           ((GPIO) == PWR_GPIO_B) ||\\r
+                           ((GPIO) == PWR_GPIO_C) ||\\r
+                           ((GPIO) == PWR_GPIO_D) ||\\r
+                           ((GPIO) == PWR_GPIO_E) ||\\r
+                           ((GPIO) == PWR_GPIO_F) ||\\r
+                           ((GPIO) == PWR_GPIO_G) ||\\r
+                           ((GPIO) == PWR_GPIO_H))\r
+#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+      defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
+                           ((GPIO) == PWR_GPIO_B) ||\\r
+                           ((GPIO) == PWR_GPIO_C) ||\\r
+                           ((GPIO) == PWR_GPIO_D) ||\\r
+                           ((GPIO) == PWR_GPIO_E) ||\\r
+                           ((GPIO) == PWR_GPIO_F) ||\\r
+                           ((GPIO) == PWR_GPIO_G) ||\\r
+                           ((GPIO) == PWR_GPIO_H) ||\\r
+                           ((GPIO) == PWR_GPIO_I))\r
+#endif\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions\r
+  * @{\r
+  */\r
+\r
+\r
+/* Peripheral Control functions  **********************************************/\r
+uint32_t HAL_PWREx_GetVoltageRange(void);\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);\r
+void HAL_PWREx_DisableBatteryCharging(void);\r
+#if defined(PWR_CR2_USV)\r
+void HAL_PWREx_EnableVddUSB(void);\r
+void HAL_PWREx_DisableVddUSB(void);\r
+#endif /* PWR_CR2_USV */\r
+#if defined(PWR_CR2_IOSV)\r
+void HAL_PWREx_EnableVddIO2(void);\r
+void HAL_PWREx_DisableVddIO2(void);\r
+#endif /* PWR_CR2_IOSV */\r
+void HAL_PWREx_EnableInternalWakeUpLine(void);\r
+void HAL_PWREx_DisableInternalWakeUpLine(void);\r
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);\r
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);\r
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);\r
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);\r
+void HAL_PWREx_EnablePullUpPullDownConfig(void);\r
+void HAL_PWREx_DisablePullUpPullDownConfig(void);\r
+void HAL_PWREx_EnableSRAM2ContentRetention(void);\r
+void HAL_PWREx_DisableSRAM2ContentRetention(void);\r
+#if defined(PWR_CR1_RRSTP)\r
+void HAL_PWREx_EnableSRAM3ContentRetention(void);\r
+void HAL_PWREx_DisableSRAM3ContentRetention(void);\r
+#endif /* PWR_CR1_RRSTP */\r
+#if defined(PWR_CR3_DSIPDEN)\r
+void HAL_PWREx_EnableDSIPinsPDActivation(void);\r
+void HAL_PWREx_DisableDSIPinsPDActivation(void);\r
+#endif /* PWR_CR3_DSIPDEN */\r
+#if defined(PWR_CR2_PVME1)\r
+void HAL_PWREx_EnablePVM1(void);\r
+void HAL_PWREx_DisablePVM1(void);\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+void HAL_PWREx_EnablePVM2(void);\r
+void HAL_PWREx_DisablePVM2(void);\r
+#endif /* PWR_CR2_PVME2 */\r
+void HAL_PWREx_EnablePVM3(void);\r
+void HAL_PWREx_DisablePVM3(void);\r
+void HAL_PWREx_EnablePVM4(void);\r
+void HAL_PWREx_DisablePVM4(void);\r
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);\r
+#if defined(PWR_CR3_ENULP)\r
+void HAL_PWREx_EnableBORPVD_ULP(void);\r
+void HAL_PWREx_DisableBORPVD_ULP(void);\r
+#endif /* PWR_CR3_ENULP */\r
+#if defined(PWR_CR4_EXT_SMPS_ON)\r
+void HAL_PWREx_EnableExtSMPS_0V95(void);\r
+void HAL_PWREx_DisableExtSMPS_0V95(void);\r
+#endif /* PWR_CR4_EXT_SMPS_ON */\r
+\r
+\r
+/* Low Power modes configuration functions ************************************/\r
+void HAL_PWREx_EnableLowPowerRunMode(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);\r
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);\r
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);\r
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);\r
+void HAL_PWREx_EnterSHUTDOWNMode(void);\r
+\r
+void HAL_PWREx_PVD_PVM_IRQHandler(void);\r
+#if defined(PWR_CR2_PVME1)\r
+void HAL_PWREx_PVM1Callback(void);\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+void HAL_PWREx_PVM2Callback(void);\r
+#endif /* PWR_CR2_PVME2 */\r
+void HAL_PWREx_PVM3Callback(void);\r
+void HAL_PWREx_PVM4Callback(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32L4xx_HAL_PWR_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h
new file mode 100644 (file)
index 0000000..f0729a5
--- /dev/null
@@ -0,0 +1,769 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_qspi.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of QSPI HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_QSPI_H\r
+#define STM32L4xx_HAL_QSPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+#if defined(QUADSPI)\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup QSPI\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Types QSPI Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  QSPI Init structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.\r
+                                  This parameter can be a number between 0 and 255 */\r
+  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)\r
+                                  This parameter can be a value between 1 and 16 */\r
+  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to\r
+                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)\r
+                                  This parameter can be a value of @ref QSPI_SampleShifting */\r
+  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits\r
+                                  required to address the flash memory. The flash capacity can be up to 4GB\r
+                                  (addressed using 32 bits) in indirect mode, but the addressable space in\r
+                                  memory-mapped mode is limited to 256MB\r
+                                  This parameter can be a number between 0 and 31 */\r
+  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number\r
+                                  of clock cycles which the chip select must remain high between commands.\r
+                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */\r
+  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.\r
+                                  This parameter can be a value of @ref QSPI_ClockMode */\r
+#if defined(QUADSPI_CR_DFM)\r
+  uint32_t FlashID;            /* Specifies the Flash which will be used,\r
+                                  This parameter can be a value of @ref QSPI_Flash_Select */\r
+  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State\r
+                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */\r
+#endif\r
+}QSPI_InitTypeDef;\r
+\r
+/**\r
+  * @brief HAL QSPI State structures definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */\r
+  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */\r
+  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */\r
+  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */\r
+  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */\r
+  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */\r
+  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */\r
+  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */\r
+  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */\r
+}HAL_QSPI_StateTypeDef;\r
+\r
+/**\r
+  * @brief  QSPI Handle Structure definition\r
+  */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+typedef struct __QSPI_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif\r
+{\r
+  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */\r
+  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */\r
+  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */\r
+  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */\r
+  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */\r
+  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */\r
+  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */\r
+  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */\r
+  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */\r
+  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */\r
+  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */\r
+  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */\r
+  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+  void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* RxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* TxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);\r
+\r
+  void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);\r
+  void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);\r
+#endif\r
+}QSPI_HandleTypeDef;\r
+\r
+/**\r
+  * @brief  QSPI Command structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Instruction;        /* Specifies the Instruction to be sent\r
+                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */\r
+  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)\r
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
+  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)\r
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
+  uint32_t AddressSize;        /* Specifies the Address Size\r
+                                  This parameter can be a value of @ref QSPI_AddressSize */\r
+  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size\r
+                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */\r
+  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.\r
+                                  This parameter can be a number between 0 and 31 */\r
+  uint32_t InstructionMode;    /* Specifies the Instruction Mode\r
+                                  This parameter can be a value of @ref QSPI_InstructionMode */\r
+  uint32_t AddressMode;        /* Specifies the Address Mode\r
+                                  This parameter can be a value of @ref QSPI_AddressMode */\r
+  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode\r
+                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */\r
+  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)\r
+                                  This parameter can be a value of @ref QSPI_DataMode */\r
+  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)\r
+                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length\r
+                                  until end of memory)*/\r
+  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase\r
+                                  This parameter can be a value of @ref QSPI_DdrMode */\r
+  uint32_t DdrHoldHalfCycle;   /* Specifies if the DDR hold is enabled. When enabled it delays the data\r
+                                  output by one half of system clock in DDR mode.\r
+                                  Not available on all devices.\r
+                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */\r
+  uint32_t SIOOMode;           /* Specifies the send instruction only once mode\r
+                                  This parameter can be a value of @ref QSPI_SIOOMode */\r
+}QSPI_CommandTypeDef;\r
+\r
+/**\r
+  * @brief  QSPI Auto Polling mode configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.\r
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r
+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.\r
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r
+  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.\r
+                                  This parameter can be any value between 0 and 0xFFFF */\r
+  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.\r
+                                  This parameter can be any value between 1 and 4 */\r
+  uint32_t MatchMode;          /* Specifies the method used for determining a match.\r
+                                  This parameter can be a value of @ref QSPI_MatchMode */\r
+  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.\r
+                                  This parameter can be a value of @ref QSPI_AutomaticStop */\r
+}QSPI_AutoPollingTypeDef;\r
+\r
+/**\r
+  * @brief  QSPI Memory Mapped mode configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.\r
+                                  This parameter can be any value between 0 and 0xFFFF */\r
+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.\r
+                                  This parameter can be a value of @ref QSPI_TimeOutActivation */\r
+}QSPI_MemoryMappedTypeDef;\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  HAL QSPI Callback ID enumeration definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */\r
+  HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */\r
+  HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */\r
+  HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */\r
+  HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */\r
+  HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */\r
+  HAL_QSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< QSPI Rx Half Complete Callback ID */\r
+  HAL_QSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< QSPI Tx Half Complete Callback ID */\r
+  HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */\r
+  HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */\r
+\r
+  HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */\r
+  HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */\r
+}HAL_QSPI_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  HAL QSPI Callback pointer definition\r
+  */\r
+typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup QSPI_ErrorCode QSPI Error Code\r
+  * @{\r
+  */\r
+#define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */\r
+#define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */\r
+#define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */\r
+#define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */\r
+#define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting\r
+  * @{\r
+  */\r
+#define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/\r
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time\r
+  * @{\r
+  */\r
+#define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/\r
+#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_ClockMode QSPI Clock Mode\r
+  * @{\r
+  */\r
+#define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/\r
+#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(QUADSPI_CR_DFM)\r
+/** @defgroup QSPI_Flash_Select QSPI Flash Select\r
+  * @{\r
+  */\r
+#define QSPI_FLASH_ID_1                0x00000000U                 /*!<FLASH 1 selected*/\r
+#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode\r
+  * @{\r
+  */\r
+#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/\r
+#define QSPI_DUALFLASH_DISABLE         0x00000000U                /*!<Dual-flash mode disabled*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif\r
+/** @defgroup QSPI_AddressSize QSPI Address Size\r
+  * @{\r
+  */\r
+#define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/\r
+#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/\r
+#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/\r
+#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size\r
+  * @{\r
+  */\r
+#define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode\r
+* @{\r
+*/\r
+#define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/\r
+#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/\r
+#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/\r
+#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_AddressMode QSPI Address Mode\r
+* @{\r
+*/\r
+#define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/\r
+#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/\r
+#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/\r
+#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode\r
+* @{\r
+*/\r
+#define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/\r
+#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/\r
+#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_DataMode QSPI Data Mode\r
+  * @{\r
+  */\r
+#define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/\r
+#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/\r
+#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/\r
+#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_DdrMode QSPI DDR Mode\r
+  * @{\r
+  */\r
+#define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/\r
+#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay\r
+  * @{\r
+  */\r
+#define QSPI_DDR_HHC_ANALOG_DELAY      0x00000000U                  /*!<Delay the data output using analog delay in DDR mode*/\r
+#if defined(QUADSPI_CCR_DHHC)\r
+#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode\r
+  * @{\r
+  */\r
+#define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/\r
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_MatchMode QSPI Match Mode\r
+  * @{\r
+  */\r
+#define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/\r
+#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop\r
+  * @{\r
+  */\r
+#define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/\r
+#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation\r
+  * @{\r
+  */\r
+#define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/\r
+#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_Flags QSPI Flags\r
+  * @{\r
+  */\r
+#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/\r
+#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/\r
+#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/\r
+#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/\r
+#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/\r
+#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_Interrupts QSPI Interrupts\r
+  * @{\r
+  */\r
+#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/\r
+#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/\r
+#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/\r
+#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/\r
+#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition\r
+  * @brief QSPI Timeout definition\r
+  * @{\r
+  */\r
+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros\r
+  * @{\r
+  */\r
+/** @brief Reset QSPI handle state.\r
+  * @param  __HANDLE__ : QSPI handle.\r
+  * @retval None\r
+  */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \\r
+                                                                  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \\r
+                                                                  (__HANDLE__)->MspInitCallback = NULL;       \\r
+                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \\r
+                                                               } while(0)\r
+#else\r
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)\r
+#endif\r
+\r
+/** @brief  Enable the QSPI peripheral.\r
+  * @param  __HANDLE__ : specifies the QSPI Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
+\r
+/** @brief  Disable the QSPI peripheral.\r
+  * @param  __HANDLE__ : specifies the QSPI Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
+\r
+/** @brief  Enable the specified QSPI interrupt.\r
+  * @param  __HANDLE__ : specifies the QSPI Handle.\r
+  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to enable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+  * @retval None\r
+  */\r
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
+\r
+\r
+/** @brief  Disable the specified QSPI interrupt.\r
+  * @param  __HANDLE__ : specifies the QSPI Handle.\r
+  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to disable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+  * @retval None\r
+  */\r
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
+\r
+/** @brief  Check whether the specified QSPI interrupt source is enabled or not.\r
+  * @param  __HANDLE__ : specifies the QSPI Handle.\r
+  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/**\r
+  * @brief  Check whether the selected QSPI flag is set or not.\r
+  * @param  __HANDLE__ : specifies the QSPI Handle.\r
+  * @param  __FLAG__ : specifies the QSPI flag to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag\r
+  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag\r
+  *            @arg QSPI_FLAG_SM:   QSPI Status match flag\r
+  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag\r
+  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag\r
+  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag\r
+  * @retval None\r
+  */\r
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)\r
+\r
+/** @brief  Clears the specified QSPI's flag status.\r
+  * @param  __HANDLE__ : specifies the QSPI Handle.\r
+  * @param  __FLAG__ : specifies the QSPI clear register flag that needs to be set\r
+  *          This parameter can be one of the following values:\r
+  *            @arg QSPI_FLAG_TO: QSPI Timeout flag\r
+  *            @arg QSPI_FLAG_SM: QSPI Status match flag\r
+  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r
+  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag\r
+  * @retval None\r
+  */\r
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup QSPI_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+/* Initialization/de-initialization functions  ********************************/\r
+HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+/* IO operation functions *****************************************************/\r
+/* QSPI IRQ handler method */\r
+void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI indirect mode */\r
+HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);\r
+HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
+HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
+HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);\r
+HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+\r
+/* QSPI status flag polling mode */\r
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);\r
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);\r
+\r
+/* QSPI memory-mapped mode */\r
+HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);\r
+\r
+/* Callback functions in non-blocking modes ***********************************/\r
+void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI indirect mode */\r
+void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI status flag polling mode */\r
+void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI memory-mapped mode */\r
+void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+/* QSPI callback registering/unregistering */\r
+HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group3\r
+  * @{\r
+  */\r
+/* Peripheral Control and State functions  ************************************/\r
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);\r
+uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);\r
+void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);\r
+HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);\r
+uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);\r
+#if defined(QUADSPI_CR_DFM)\r
+HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup QSPI_Private_Macros QSPI Private Macros\r
+  * @{\r
+  */\r
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)\r
+\r
+#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 16U))\r
+\r
+#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \\r
+                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))\r
+\r
+#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))\r
+\r
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \\r
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \\r
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \\r
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \\r
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \\r
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \\r
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \\r
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))\r
+\r
+#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \\r
+                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))\r
+\r
+#if defined(QUADSPI_CR_DFM)\r
+#define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \\r
+                                            ((FLASH_ID) == QSPI_FLASH_ID_2))\r
+\r
+#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \\r
+                                            ((MODE) == QSPI_DUALFLASH_DISABLE))\r
+\r
+#endif\r
+#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)\r
+\r
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \\r
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \\r
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \\r
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))\r
+\r
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \\r
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \\r
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \\r
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))\r
+\r
+#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)\r
+\r
+#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \\r
+                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \\r
+                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \\r
+                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))\r
+\r
+#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \\r
+                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \\r
+                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \\r
+                                            ((MODE) == QSPI_ADDRESS_4_LINES))\r
+\r
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \\r
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \\r
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \\r
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))\r
+\r
+#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \\r
+                                            ((MODE) == QSPI_DATA_1_LINE)  || \\r
+                                            ((MODE) == QSPI_DATA_2_LINES) || \\r
+                                            ((MODE) == QSPI_DATA_4_LINES))\r
+\r
+#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \\r
+                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))\r
+\r
+#if defined(QUADSPI_CCR_DHHC)\r
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \\r
+                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))\r
+\r
+#else\r
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))\r
+\r
+#endif\r
+#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \\r
+                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))\r
+\r
+#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)\r
+\r
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))\r
+\r
+#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \\r
+                                            ((MODE) == QSPI_MATCH_MODE_OR))\r
+\r
+#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \\r
+                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))\r
+\r
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \\r
+                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))\r
+\r
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)\r
+/**\r
+* @}\r
+*/\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_QSPI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
new file mode 100644 (file)
index 0000000..5111e73
--- /dev/null
@@ -0,0 +1,4743 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_rcc.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of RCC HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_RCC_H\r
+#define __STM32L4xx_HAL_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup RCC\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Types RCC Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  RCC PLL configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t PLLState;   /*!< The new state of the PLL.\r
+                            This parameter can be a value of @ref RCC_PLL_Config                      */\r
+\r
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.\r
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */\r
+\r
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.\r
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */\r
+\r
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.\r
+                            This parameter must be a number between Min_Data = 8 and Max_Data = 86    */\r
+\r
+#if defined(RCC_PLLP_SUPPORT)\r
+  uint32_t PLLP;       /*!< PLLP: Division factor for SAI clock.\r
+                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */\r
+#endif /* RCC_PLLP_SUPPORT */\r
+\r
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.\r
+                            This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */\r
+\r
+  uint32_t PLLR;       /*!< PLLR: Division for the main system clock.\r
+                            User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ\r
+                            on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices.\r
+                            This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */\r
+\r
+}RCC_PLLInitTypeDef;\r
+\r
+/**\r
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.\r
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */\r
+\r
+  uint32_t HSEState;             /*!< The new state of the HSE.\r
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */\r
+\r
+  uint32_t LSEState;             /*!< The new state of the LSE.\r
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */\r
+\r
+  uint32_t HSIState;             /*!< The new state of the HSI.\r
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */\r
+\r
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.\r
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */\r
+\r
+  uint32_t LSIState;             /*!< The new state of the LSI.\r
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+\r
+  uint32_t LSIDiv;               /*!< The division factor of the LSI.\r
+                                      This parameter can be a value of @ref RCC_LSI_Div                           */\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+\r
+  uint32_t MSIState;             /*!< The new state of the MSI.\r
+                                      This parameter can be a value of @ref RCC_MSI_Config */\r
+\r
+  uint32_t MSICalibrationValue;  /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).\r
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
+\r
+  uint32_t MSIClockRange;        /*!< The MSI frequency range.\r
+                                      This parameter can be a value of @ref RCC_MSI_Clock_Range  */\r
+\r
+  uint32_t HSI48State;             /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).\r
+                                        This parameter can be a value of @ref RCC_HSI48_Config */\r
+\r
+  RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */\r
+\r
+}RCC_OscInitTypeDef;\r
+\r
+/**\r
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t ClockType;             /*!< The clock to be configured.\r
+                                       This parameter can be a value of @ref RCC_System_Clock_Type      */\r
+\r
+  uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).\r
+                                       This parameter can be a value of @ref RCC_System_Clock_Source    */\r
+\r
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
+                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */\r
+\r
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+}RCC_ClkInitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC_Timeout_Value Timeout Values\r
+  * @{\r
+  */\r
+#define RCC_DBP_TIMEOUT_VALUE          2U            /* 2 ms (minimum Tick + 1) */\r
+#define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Oscillator_Type Oscillator Type\r
+  * @{\r
+  */\r
+#define RCC_OSCILLATORTYPE_NONE        0x00000000U   /*!< Oscillator configuration unchanged */\r
+#define RCC_OSCILLATORTYPE_HSE         0x00000001U   /*!< HSE to configure */\r
+#define RCC_OSCILLATORTYPE_HSI         0x00000002U   /*!< HSI to configure */\r
+#define RCC_OSCILLATORTYPE_LSE         0x00000004U   /*!< LSE to configure */\r
+#define RCC_OSCILLATORTYPE_LSI         0x00000008U   /*!< LSI to configure */\r
+#define RCC_OSCILLATORTYPE_MSI         0x00000010U   /*!< MSI to configure */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define RCC_OSCILLATORTYPE_HSI48       0x00000020U   /*!< HSI48 to configure */\r
+#endif /* RCC_HSI48_SUPPORT */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_HSE_Config HSE Config\r
+  * @{\r
+  */\r
+#define RCC_HSE_OFF                    0x00000000U                    /*!< HSE clock deactivation */\r
+#define RCC_HSE_ON                     RCC_CR_HSEON                   /*!< HSE clock activation */\r
+#define RCC_HSE_BYPASS                 (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_LSE_Config LSE Config\r
+  * @{\r
+  */\r
+#define RCC_LSE_OFF                    0x00000000U                           /*!< LSE clock deactivation */\r
+#define RCC_LSE_ON                     RCC_BDCR_LSEON                        /*!< LSE clock activation */\r
+#define RCC_LSE_BYPASS                 (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)    /*!< External clock source for LSE clock */\r
+#if defined(RCC_BDCR_LSESYSDIS)\r
+#define RCC_LSE_ON_RTC_ONLY            (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */\r
+#define RCC_LSE_BYPASS_RTC_ONLY        (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */\r
+#endif /* RCC_BDCR_LSESYSDIS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_HSI_Config HSI Config\r
+  * @{\r
+  */\r
+#define RCC_HSI_OFF                    0x00000000U   /*!< HSI clock deactivation */\r
+#define RCC_HSI_ON                     RCC_CR_HSION  /*!< HSI clock activation */\r
+\r
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \\r
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+#define RCC_HSICALIBRATION_DEFAULT     0x10U         /* Default HSI calibration trimming value */\r
+#else\r
+#define RCC_HSICALIBRATION_DEFAULT     0x40U         /* Default HSI calibration trimming value */\r
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */\r
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx    */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_LSI_Config LSI Config\r
+  * @{\r
+  */\r
+#define RCC_LSI_OFF                    0x00000000U   /*!< LSI clock deactivation */\r
+#define RCC_LSI_ON                     RCC_CSR_LSION /*!< LSI clock activation */\r
+/**\r
+  * @}\r
+  */\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+\r
+/** @defgroup RCC_LSI_Div LSI Div\r
+  * @{\r
+  */\r
+#define RCC_LSI_DIV1                   0x00000000U       /*!< LSI clock not divided    */\r
+#define RCC_LSI_DIV128                 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+\r
+/** @defgroup RCC_MSI_Config MSI Config\r
+  * @{\r
+  */\r
+#define RCC_MSI_OFF                    0x00000000U   /*!< MSI clock deactivation */\r
+#define RCC_MSI_ON                     RCC_CR_MSION  /*!< MSI clock activation */\r
+\r
+#define RCC_MSICALIBRATION_DEFAULT     0U            /*!< Default MSI calibration trimming value */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+/** @defgroup RCC_HSI48_Config HSI48 Config\r
+  * @{\r
+  */\r
+#define RCC_HSI48_OFF                  0x00000000U       /*!< HSI48 clock deactivation */\r
+#define RCC_HSI48_ON                   RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */\r
+/**\r
+  * @}\r
+  */\r
+#else\r
+/** @defgroup RCC_HSI48_Config HSI48 Config\r
+  * @{\r
+  */\r
+#define RCC_HSI48_OFF                  0x00000000U   /*!< HSI48 clock deactivation */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+/** @defgroup RCC_PLL_Config PLL Config\r
+  * @{\r
+  */\r
+#define RCC_PLL_NONE                   0x00000000U   /*!< PLL configuration unchanged */\r
+#define RCC_PLL_OFF                    0x00000001U   /*!< PLL deactivation */\r
+#define RCC_PLL_ON                     0x00000002U   /*!< PLL activation */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(RCC_PLLP_SUPPORT)\r
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r
+  * @{\r
+  */\r
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
+#define RCC_PLLP_DIV2                  0x00000002U   /*!< PLLP division factor = 2  */\r
+#define RCC_PLLP_DIV3                  0x00000003U   /*!< PLLP division factor = 3  */\r
+#define RCC_PLLP_DIV4                  0x00000004U   /*!< PLLP division factor = 4  */\r
+#define RCC_PLLP_DIV5                  0x00000005U   /*!< PLLP division factor = 5  */\r
+#define RCC_PLLP_DIV6                  0x00000006U   /*!< PLLP division factor = 6  */\r
+#define RCC_PLLP_DIV7                  0x00000007U   /*!< PLLP division factor = 7  */\r
+#define RCC_PLLP_DIV8                  0x00000008U   /*!< PLLP division factor = 8  */\r
+#define RCC_PLLP_DIV9                  0x00000009U   /*!< PLLP division factor = 9  */\r
+#define RCC_PLLP_DIV10                 0x0000000AU   /*!< PLLP division factor = 10 */\r
+#define RCC_PLLP_DIV11                 0x0000000BU   /*!< PLLP division factor = 11 */\r
+#define RCC_PLLP_DIV12                 0x0000000CU   /*!< PLLP division factor = 12 */\r
+#define RCC_PLLP_DIV13                 0x0000000DU   /*!< PLLP division factor = 13 */\r
+#define RCC_PLLP_DIV14                 0x0000000EU   /*!< PLLP division factor = 14 */\r
+#define RCC_PLLP_DIV15                 0x0000000FU   /*!< PLLP division factor = 15 */\r
+#define RCC_PLLP_DIV16                 0x00000010U   /*!< PLLP division factor = 16 */\r
+#define RCC_PLLP_DIV17                 0x00000011U   /*!< PLLP division factor = 17 */\r
+#define RCC_PLLP_DIV18                 0x00000012U   /*!< PLLP division factor = 18 */\r
+#define RCC_PLLP_DIV19                 0x00000013U   /*!< PLLP division factor = 19 */\r
+#define RCC_PLLP_DIV20                 0x00000014U   /*!< PLLP division factor = 20 */\r
+#define RCC_PLLP_DIV21                 0x00000015U   /*!< PLLP division factor = 21 */\r
+#define RCC_PLLP_DIV22                 0x00000016U   /*!< PLLP division factor = 22 */\r
+#define RCC_PLLP_DIV23                 0x00000017U   /*!< PLLP division factor = 23 */\r
+#define RCC_PLLP_DIV24                 0x00000018U   /*!< PLLP division factor = 24 */\r
+#define RCC_PLLP_DIV25                 0x00000019U   /*!< PLLP division factor = 25 */\r
+#define RCC_PLLP_DIV26                 0x0000001AU   /*!< PLLP division factor = 26 */\r
+#define RCC_PLLP_DIV27                 0x0000001BU   /*!< PLLP division factor = 27 */\r
+#define RCC_PLLP_DIV28                 0x0000001CU   /*!< PLLP division factor = 28 */\r
+#define RCC_PLLP_DIV29                 0x0000001DU   /*!< PLLP division factor = 29 */\r
+#define RCC_PLLP_DIV30                 0x0000001EU   /*!< PLLP division factor = 30 */\r
+#define RCC_PLLP_DIV31                 0x0000001FU   /*!< PLLP division factor = 31 */\r
+#else\r
+#define RCC_PLLP_DIV7                  0x00000007U   /*!< PLLP division factor = 7  */\r
+#define RCC_PLLP_DIV17                 0x00000011U   /*!< PLLP division factor = 17 */\r
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* RCC_PLLP_SUPPORT */\r
+\r
+/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider\r
+  * @{\r
+  */\r
+#define RCC_PLLQ_DIV2                  0x00000002U   /*!< PLLQ division factor = 2 */\r
+#define RCC_PLLQ_DIV4                  0x00000004U   /*!< PLLQ division factor = 4 */\r
+#define RCC_PLLQ_DIV6                  0x00000006U   /*!< PLLQ division factor = 6 */\r
+#define RCC_PLLQ_DIV8                  0x00000008U   /*!< PLLQ division factor = 8 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider\r
+  * @{\r
+  */\r
+#define RCC_PLLR_DIV2                  0x00000002U   /*!< PLLR division factor = 2 */\r
+#define RCC_PLLR_DIV4                  0x00000004U   /*!< PLLR division factor = 4 */\r
+#define RCC_PLLR_DIV6                  0x00000006U   /*!< PLLR division factor = 6 */\r
+#define RCC_PLLR_DIV8                  0x00000008U   /*!< PLLR division factor = 8 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
+  * @{\r
+  */\r
+#define RCC_PLLSOURCE_NONE             0x00000000U             /*!< No clock selected as PLL entry clock source  */\r
+#define RCC_PLLSOURCE_MSI              RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */\r
+#define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */\r
+#define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_PLL_Clock_Output PLL Clock Output\r
+  * @{\r
+  */\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+#define RCC_PLL_SAI3CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */\r
+#elif defined(RCC_PLLSAI1_SUPPORT)\r
+#define RCC_PLL_SAI2CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+#define RCC_PLL_48M1CLK                RCC_PLLCFGR_PLLQEN      /*!< PLL48M1CLK selection from main PLL */\r
+#define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */\r
+/**\r
+  * @}\r
+  */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output\r
+  * @{\r
+  */\r
+#define RCC_PLLSAI1_SAI1CLK            RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */\r
+#define RCC_PLLSAI1_48M2CLK            RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */\r
+#define RCC_PLLSAI1_ADC1CLK            RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output\r
+  * @{\r
+  */\r
+#define RCC_PLLSAI2_SAI2CLK            RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+#define RCC_PLLSAI2_DSICLK             RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2  */\r
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+#define RCC_PLLSAI2_ADC2CLK            RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */\r
+#else\r
+#define RCC_PLLSAI2_LTDCCLK            RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+/** @defgroup RCC_MSI_Clock_Range MSI Clock Range\r
+  * @{\r
+  */\r
+#define RCC_MSIRANGE_0                 RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */\r
+#define RCC_MSIRANGE_1                 RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */\r
+#define RCC_MSIRANGE_2                 RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */\r
+#define RCC_MSIRANGE_3                 RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */\r
+#define RCC_MSIRANGE_4                 RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */\r
+#define RCC_MSIRANGE_5                 RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */\r
+#define RCC_MSIRANGE_6                 RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */\r
+#define RCC_MSIRANGE_7                 RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */\r
+#define RCC_MSIRANGE_8                 RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */\r
+#define RCC_MSIRANGE_9                 RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */\r
+#define RCC_MSIRANGE_10                RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */\r
+#define RCC_MSIRANGE_11                RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_System_Clock_Type System Clock Type\r
+  * @{\r
+  */\r
+#define RCC_CLOCKTYPE_SYSCLK           0x00000001U   /*!< SYSCLK to configure */\r
+#define RCC_CLOCKTYPE_HCLK             0x00000002U   /*!< HCLK to configure */\r
+#define RCC_CLOCKTYPE_PCLK1            0x00000004U   /*!< PCLK1 to configure */\r
+#define RCC_CLOCKTYPE_PCLK2            0x00000008U   /*!< PCLK2 to configure */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_System_Clock_Source System Clock Source\r
+  * @{\r
+  */\r
+#define RCC_SYSCLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */\r
+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */\r
+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */\r
+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
+  * @{\r
+  */\r
+#define RCC_SYSCLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source\r
+  * @{\r
+  */\r
+#define RCC_SYSCLK_DIV1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */\r
+#define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */\r
+#define RCC_SYSCLK_DIV4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */\r
+#define RCC_SYSCLK_DIV8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */\r
+#define RCC_SYSCLK_DIV16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */\r
+#define RCC_SYSCLK_DIV64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */\r
+#define RCC_SYSCLK_DIV128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\r
+#define RCC_SYSCLK_DIV256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\r
+#define RCC_SYSCLK_DIV512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_HCLK_DIV1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */\r
+#define RCC_HCLK_DIV2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */\r
+#define RCC_HCLK_DIV4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */\r
+#define RCC_HCLK_DIV8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */\r
+#define RCC_HCLK_DIV16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source\r
+  * @{\r
+  */\r
+#define RCC_RTCCLKSOURCE_NONE          0x00000000U          /*!< No clock used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0    /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1    /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL      /*!< HSE oscillator clock divided by 32 used as RTC clock */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_MCO_Index MCO Index\r
+  * @{\r
+  */\r
+#define RCC_MCO1                       0x00000000U\r
+#define RCC_MCO                        RCC_MCO1      /*!< MCO1 to be compliant with other families with 2 MCOs*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_MCO1SOURCE_NOCLOCK         0x00000000U                            /*!< MCO1 output disabled, no clock on MCO1 */\r
+#define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */\r
+#define RCC_MCO1SOURCE_MSI             RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */\r
+#define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */\r
+#define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */\r
+#define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */\r
+#define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */\r
+#define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define RCC_MCO1SOURCE_HSI48           RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */\r
+#endif /* RCC_HSI48_SUPPORT */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler\r
+  * @{\r
+  */\r
+#define RCC_MCODIV_1                   RCC_CFGR_MCOPRE_DIV1     /*!< MCO not divided  */\r
+#define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_DIV2     /*!< MCO divided by 2 */\r
+#define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_DIV4     /*!< MCO divided by 4 */\r
+#define RCC_MCODIV_8                   RCC_CFGR_MCOPRE_DIV8     /*!< MCO divided by 8 */\r
+#define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_DIV16    /*!< MCO divided by 16 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Interrupt Interrupts\r
+  * @{\r
+  */\r
+#define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */\r
+#define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */\r
+#define RCC_IT_MSIRDY                  RCC_CIFR_MSIRDYF      /*!< MSI Ready Interrupt flag */\r
+#define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF      /*!< HSI16 Ready Interrupt flag */\r
+#define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */\r
+#define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define RCC_IT_PLLSAI1RDY              RCC_CIFR_PLLSAI1RDYF  /*!< PLLSAI1 Ready Interrupt flag */\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+#define RCC_IT_PLLSAI2RDY              RCC_CIFR_PLLSAI2RDYF  /*!< PLLSAI2 Ready Interrupt flag */\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+#define RCC_IT_CSS                     RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */\r
+#define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define RCC_IT_HSI48RDY                RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */\r
+#endif /* RCC_HSI48_SUPPORT */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Flag Flags\r
+  *        Elements values convention: XXXYYYYYb\r
+  *           - YYYYY  : Flag position in the register\r
+  *           - XXX  : Register index\r
+  *                 - 001: CR register\r
+  *                 - 010: BDCR register\r
+  *                 - 011: CSR register\r
+  *                 - 100: CRRCR register\r
+  * @{\r
+  */\r
+/* Flags in the CR register */\r
+#define RCC_FLAG_MSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */\r
+#define RCC_FLAG_HSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */\r
+#define RCC_FLAG_HSERDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */\r
+#define RCC_FLAG_PLLRDY                ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define RCC_FLAG_PLLSAI1RDY            ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+#define RCC_FLAG_PLLSAI2RDY            ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+/* Flags in the BDCR register */\r
+#define RCC_FLAG_LSERDY                ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)  /*!< LSE Ready flag */\r
+#define RCC_FLAG_LSECSSD               ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */\r
+\r
+/* Flags in the CSR register */\r
+#define RCC_FLAG_LSIRDY                ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)    /*!< LSI Ready flag */\r
+#define RCC_FLAG_FWRST                 ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)    /*!< Firewall reset flag */\r
+#define RCC_FLAG_OBLRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)   /*!< Option Byte Loader reset flag */\r
+#define RCC_FLAG_PINRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)   /*!< PIN reset flag */\r
+#define RCC_FLAG_BORRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)   /*!< BOR reset flag */\r
+#define RCC_FLAG_SFTRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)   /*!< Software Reset flag */\r
+#define RCC_FLAG_IWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)  /*!< Independent Watchdog reset flag */\r
+#define RCC_FLAG_WWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)  /*!< Window watchdog reset flag */\r
+#define RCC_FLAG_LPWRRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)  /*!< Low-Power reset flag */\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+/* Flags in the CRRCR register */\r
+#define RCC_FLAG_HSI48RDY              ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */\r
+#endif /* RCC_HSI48_SUPPORT */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config\r
+  * @{\r
+  */\r
+#define RCC_LSEDRIVE_LOW                 0x00000000U         /*!< LSE low drive capability */\r
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0   /*!< LSE medium low drive capability */\r
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1   /*!< LSE medium high drive capability */\r
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV     /*!< LSE high drive capability */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock\r
+  * @{\r
+  */\r
+#define RCC_STOP_WAKEUPCLOCK_MSI       0x00000000U           /*!< MSI selection after wake-up from STOP */\r
+#define RCC_STOP_WAKEUPCLOCK_HSI       RCC_CFGR_STOPWUCK     /*!< HSI selection after wake-up from STOP */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r
+  * @brief  Enable or disable the AHB1 peripheral clock.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_DMA1_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_DMA2_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_CLK_ENABLE()         do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_CRC_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_TSC_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* GFXMMU */\r
+\r
+\r
+#define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)\r
+\r
+#define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_CLK_DISABLE()        CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)\r
+\r
+#define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)\r
+\r
+#define __HAL_RCC_TSC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_CLK_DISABLE()         CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)\r
+#endif /* GFXMMU */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\r
+  * @brief  Enable or disable the AHB2 peripheral clock.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* GPIOI */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()      do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */\r
+\r
+\r
+#define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)\r
+#endif /* GPIOI */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()     CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE()         CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN)\r
+#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable\r
+  * @brief  Enable or disable the AHB3 peripheral clock.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* FMC_BANK1 */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* OCTOSPI2 */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)\r
+#endif /* FMC_BANK1 */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_CLK_DISABLE()          CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_CLK_DISABLE()          CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN)\r
+#endif /* OCTOSPI2 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r
+  * @brief  Enable or disable the APB1 peripheral clock.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_TIM2_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1ENR1_RTCAPBEN)\r
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* RCC_APB1ENR1_RTCAPBEN */\r
+\r
+#define __HAL_RCC_WWDG_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+\r
+#define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1ENR1_RTCAPBEN)\r
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);\r
+#endif /* RCC_APB1ENR1_RTCAPBEN */\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)\r
+\r
+#define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\r
+  * @brief  Enable or disable the APB2 peripheral clock.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_FIREWALL_CLK_ENABLE()        do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
+\r
+#define __HAL_RCC_TIM1_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_SPI1_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+\r
+#define __HAL_RCC_TIM15_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#define __HAL_RCC_TIM16_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_CLK_ENABLE()           do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_CLK_ENABLE()          do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_ENABLE()            do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_ENABLE()             do { \\r
+                                                 __IO uint32_t tmpreg; \\r
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \\r
+                                                 /* Delay after an RCC peripheral clock enabling */ \\r
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \\r
+                                                 UNUSED(tmpreg); \\r
+                                               } while(0)\r
+#endif /* DSI */\r
+\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)\r
+#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
+\r
+#define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)\r
+\r
+#define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)\r
+\r
+#define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)\r
+\r
+#define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_DISABLE()            CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN)\r
+#endif /* DSI */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status\r
+  * @brief  Check whether the AHB1 peripheral clock is enabled or not.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)\r
+\r
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)\r
+\r
+#define __HAL_RCC_TSC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U)\r
+#endif /* GFXMMU */\r
+\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)\r
+\r
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED()    (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)\r
+\r
+#define __HAL_RCC_TSC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U)\r
+#endif /* GFXMMU */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status\r
+  * @brief  Check whether the AHB2 peripheral clock is enabled or not.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)\r
+\r
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)\r
+\r
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U)\r
+#endif /* GPIOI */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)\r
+\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)\r
+\r
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)\r
+\r
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U)\r
+#endif /* GPIOI */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status\r
+  * @brief  Check whether the AHB3 peripheral clock is enabled or not.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)\r
+#endif /* FMC_BANK1 */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)\r
+#endif /* FMC_BANK1 */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)\r
+#endif /* QUADSPI */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status\r
+  * @brief  Check whether the APB1 peripheral clock is enabled or not.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U)\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1ENR1_RTCAPBEN)\r
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)\r
+#endif /* RCC_APB1ENR1_RTCAPBEN */\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U)\r
+\r
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)\r
+\r
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)\r
+\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U)\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1ENR1_RTCAPBEN)\r
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)\r
+#endif /* RCC_APB1ENR1_RTCAPBEN */\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U)\r
+\r
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)\r
+\r
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status\r
+  * @brief  Check whether the APB2 peripheral clock is enabled or not.\r
+  * @note   After reset, the peripheral clock (used for registers read/write access)\r
+  *         is disabled and the application software has to enable this clock before\r
+  *         using it.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)\r
+\r
+#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U)\r
+#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)\r
+\r
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)\r
+\r
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)\r
+\r
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()         (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U)\r
+#endif /* DSI */\r
+\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U)\r
+#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)\r
+\r
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)\r
+\r
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)\r
+\r
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U)\r
+#endif /* DSI */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset\r
+  * @brief  Force or release AHB1 peripheral reset.\r
+  * @{\r
+  */\r
+#define __HAL_RCC_AHB1_FORCE_RESET()           WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)\r
+\r
+#define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)\r
+\r
+#define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_FORCE_RESET()        SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)\r
+\r
+#define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)\r
+\r
+#define __HAL_RCC_TSC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_FORCE_RESET()         SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)\r
+#endif /* GFXMMU */\r
+\r
+\r
+#define __HAL_RCC_AHB1_RELEASE_RESET()         WRITE_REG(RCC->AHB1RSTR, 0x00000000U)\r
+\r
+#define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)\r
+\r
+#define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_RELEASE_RESET()      CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)\r
+\r
+#define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)\r
+\r
+#define __HAL_RCC_TSC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_RELEASE_RESET()       CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)\r
+#endif /* GFXMMU */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset\r
+  * @brief  Force or release AHB2 peripheral reset.\r
+  * @{\r
+  */\r
+#define __HAL_RCC_AHB2_FORCE_RESET()           WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)\r
+\r
+#define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)\r
+\r
+#define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)\r
+\r
+#define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)\r
+#endif /* GPIOI */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()     SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET()         SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)\r
+#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */\r
+\r
+\r
+#define __HAL_RCC_AHB2_RELEASE_RESET()         WRITE_REG(RCC->AHB2RSTR, 0x00000000U)\r
+\r
+#define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)\r
+\r
+#define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)\r
+\r
+#define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)\r
+#endif /* GPIOI */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()   CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()       CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)\r
+#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset\r
+  * @brief  Force or release AHB3 peripheral reset.\r
+  * @{\r
+  */\r
+#define __HAL_RCC_AHB3_FORCE_RESET()           WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_FORCE_RESET()            SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)\r
+#endif /* FMC_BANK1 */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_FORCE_RESET()           SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_FORCE_RESET()          SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_FORCE_RESET()          SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)\r
+#endif /* OCTOSPI2 */\r
+\r
+#define __HAL_RCC_AHB3_RELEASE_RESET()         WRITE_REG(RCC->AHB3RSTR, 0x00000000U)\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)\r
+#endif /* FMC_BANK1 */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_RELEASE_RESET()        CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_RELEASE_RESET()        CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)\r
+#endif /* OCTOSPI2 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset\r
+  * @brief  Force or release APB1 peripheral reset.\r
+  * @{\r
+  */\r
+#define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)\r
+\r
+#define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)\r
+#endif /* LCD */\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)\r
+\r
+#define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)\r
+\r
+#define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)\r
+\r
+\r
+#define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APB1RSTR1, 0x00000000U)\r
+\r
+#define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)\r
+#endif /* LCD */\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)\r
+\r
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)\r
+\r
+#define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset\r
+  * @brief  Force or release APB2 peripheral reset.\r
+  * @{\r
+  */\r
+#define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)\r
+\r
+#define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)\r
+#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */\r
+\r
+#define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)\r
+\r
+#define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)\r
+\r
+#define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)\r
+\r
+#define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_FORCE_RESET()            SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)\r
+#endif /* DSI */\r
+\r
+\r
+#define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APB2RSTR, 0x00000000U)\r
+\r
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)\r
+#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */\r
+\r
+#define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)\r
+\r
+#define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)\r
+\r
+#define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)\r
+\r
+#define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_RELEASE_RESET()          CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)\r
+#endif /* DSI */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable\r
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)\r
+\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)\r
+\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)\r
+\r
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)\r
+\r
+#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)\r
+#endif /* GFXMMU */\r
+\r
+\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)\r
+\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)\r
+\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)\r
+\r
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)\r
+\r
+#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)\r
+#endif /* GFXMMU */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable\r
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)\r
+#endif /* GPIOI */\r
+\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)\r
+\r
+#if defined(SRAM3)\r
+#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)\r
+#endif /* SRAM3 */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)\r
+#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
+\r
+\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)\r
+#endif /* GPIOI */\r
+\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)\r
+\r
+#if defined(SRAM3)\r
+#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)\r
+#endif /* SRAM3 */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)\r
+#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable\r
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)\r
+#endif /* OCTOSPI2 */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)\r
+#endif /* FMC_BANK1 */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)\r
+#endif /* OCTOSPI2 */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)\r
+#endif /* FMC_BANK1 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable\r
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)\r
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
+\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)\r
+\r
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)\r
+\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)\r
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
+\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)\r
+\r
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable\r
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)\r
+#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
+\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)\r
+\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)\r
+\r
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)\r
+\r
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)\r
+#endif /* DSI */\r
+\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)\r
+#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
+\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)\r
+\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)\r
+\r
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)\r
+\r
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)\r
+#endif /* DSI */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status\r
+  * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)\r
+\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)\r
+\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)\r
+\r
+#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U)\r
+#endif /* GFXMMU */\r
+\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)\r
+\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)\r
+\r
+#if defined(DMAMUX1)\r
+#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)\r
+#endif /* DMAMUX1 */\r
+\r
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)\r
+\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)\r
+\r
+#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U)\r
+\r
+#if defined(DMA2D)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U)\r
+#endif /* DMA2D */\r
+\r
+#if defined(GFXMMU)\r
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U)\r
+#endif /* GFXMMU */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status\r
+  * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)\r
+\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)\r
+\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U)\r
+#endif /* GPIOI */\r
+\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)\r
+\r
+#if defined(SRAM3)\r
+#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U)\r
+#endif /* SRAM3 */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U)\r
+#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
+\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)\r
+\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)\r
+\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)\r
+\r
+#if defined(GPIOD)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)\r
+#endif /* GPIOD */\r
+\r
+#if defined(GPIOE)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)\r
+#endif /* GPIOE */\r
+\r
+#if defined(GPIOF)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)\r
+#endif /* GPIOF */\r
+\r
+#if defined(GPIOG)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)\r
+#endif /* GPIOG */\r
+\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U)\r
+\r
+#if defined(GPIOI)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U)\r
+#endif /* GPIOI */\r
+\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)\r
+\r
+#if defined(SRAM3)\r
+#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U)\r
+#endif /* SRAM3 */\r
+\r
+#if defined(USB_OTG_FS)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U)\r
+#endif /* USB_OTG_FS */\r
+\r
+#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U)\r
+\r
+#if defined(DCMI)\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U)\r
+#endif /* DCMI */\r
+\r
+#if defined(AES)\r
+#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)\r
+#endif /* AES */\r
+\r
+#if defined(HASH)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U)\r
+#endif /* HASH */\r
+\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)\r
+\r
+#if defined(OCTOSPIM)\r
+#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U)\r
+#endif /* OCTOSPIM */\r
+\r
+#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U)\r
+#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status\r
+  * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U)\r
+#endif /* OCTOSPI2 */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)\r
+#endif /* FMC_BANK1 */\r
+\r
+\r
+#if defined(QUADSPI)\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)\r
+#endif /* QUADSPI */\r
+\r
+#if defined(OCTOSPI1)\r
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U)\r
+#endif /* OCTOSPI1 */\r
+\r
+#if defined(OCTOSPI2)\r
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U)\r
+#endif /* OCTOSPI2 */\r
+\r
+#if defined(FMC_BANK1)\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)\r
+#endif /* FMC_BANK1 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status\r
+  * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U)\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)\r
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U)\r
+\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)\r
+\r
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U)\r
+\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)\r
+\r
+#if defined(TIM3)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)\r
+#endif /* TIM3 */\r
+\r
+#if defined(TIM4)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)\r
+#endif /* TIM4 */\r
+\r
+#if defined(TIM5)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)\r
+#endif /* TIM5 */\r
+\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)\r
+\r
+#if defined(TIM7)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)\r
+#endif /* TIM7 */\r
+\r
+#if defined(LCD)\r
+#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U)\r
+#endif /* LCD */\r
+\r
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)\r
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)\r
+\r
+#if defined(SPI2)\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)\r
+#endif /* SPI2 */\r
+\r
+#if defined(SPI3)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)\r
+#endif /* SPI3 */\r
+\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)\r
+\r
+#if defined(USART3)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)\r
+#endif /* UART5 */\r
+\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)\r
+\r
+#if defined(I2C2)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)\r
+#endif /* I2C2 */\r
+\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)\r
+\r
+#if defined(I2C4)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)\r
+#endif /* I2C4 */\r
+\r
+#if defined(CRS)\r
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)\r
+#endif /* CRS */\r
+\r
+#if defined(CAN1)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U)\r
+#endif /* CAN1 */\r
+\r
+#if defined(CAN2)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U)\r
+#endif /* CAN2 */\r
+\r
+#if defined(USB)\r
+#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U)\r
+#endif /* USB */\r
+\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)\r
+\r
+#if defined(DAC1)\r
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U)\r
+#endif /* DAC1 */\r
+\r
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U)\r
+\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)\r
+\r
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)\r
+\r
+#if defined(SWPMI1)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U)\r
+#endif /* SWPMI1 */\r
+\r
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status\r
+  * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
+  *         power consumption.\r
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
+  * @{\r
+  */\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U)\r
+#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)\r
+\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)\r
+\r
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)\r
+\r
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U)\r
+#endif /* DSI */\r
+\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)\r
+\r
+#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U)\r
+#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)\r
+\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)\r
+\r
+#if defined(TIM8)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)\r
+#endif /* TIM8 */\r
+\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)\r
+\r
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)\r
+\r
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)\r
+\r
+#if defined(TIM17)\r
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)\r
+#endif /* TIM17 */\r
+\r
+#if defined(SAI1)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U)\r
+#endif /* SAI2 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U)\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U)\r
+#endif /* DSI */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset\r
+  * @{\r
+  */\r
+\r
+/** @brief  Macros to force or release the Backup domain reset.\r
+  * @note   This function resets the RTC peripheral (including the backup registers)\r
+  *         and the RTC clock source selection in RCC_CSR register.\r
+  * @note   The BKPSRAM is not affected by this reset.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
+\r
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration\r
+  * @{\r
+  */\r
+\r
+/** @brief  Macros to enable or disable the RTC clock.\r
+  * @note   As the RTC is in the Backup domain and write access is denied to\r
+  *         this domain after reset, you have to enable write access using\r
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC\r
+  *         (to be done once after reset).\r
+  * @note   These macros must be used after the RTC clock source was selected.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
+\r
+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @brief  Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).\r
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+  *         It is used (enabled by hardware) as system clock source after startup\r
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
+  *         of the HSE used directly or indirectly as system clock (if the Clock\r
+  *         Security System CSS is enabled).\r
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,\r
+  *         you have to select another source of the system clock then stop the HSI.\r
+  * @note   After enabling the HSI, the application software should wait on HSIRDY\r
+  *         flag to be set indicating that HSI clock is stable and can be used as\r
+  *         system clock source.\r
+  *         This parameter can be: ENABLE or DISABLE.\r
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+  *         clock cycles.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)\r
+\r
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)\r
+\r
+/** @brief  Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.\r
+  * @note   The calibration is used to compensate for the variations in voltage\r
+  *         and temperature that influence the frequency of the internal HSI RC.\r
+  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value\r
+  *         (default is RCC_HSICALIBRATION_DEFAULT).\r
+  *         This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \\r
+                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)\r
+\r
+/**\r
+  * @brief    Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)\r
+  *           in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.\r
+  * @note     The enable of this function has not effect on the HSION bit.\r
+  *           This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIASFS)\r
+\r
+#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE()  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)\r
+\r
+/**\r
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)\r
+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.\r
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication\r
+  *           speed because of the HSI startup time.\r
+  * @note     The enable of this function has not effect on the HSION bit.\r
+  *           This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)\r
+\r
+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)\r
+\r
+/**\r
+  * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).\r
+  * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
+  *           It is used (enabled by hardware) as system clock source after\r
+  *           startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
+  *           of failure of the HSE used directly or indirectly as system clock\r
+  *           (if the Clock Security System CSS is enabled).\r
+  * @note     MSI can not be stopped if it is used as system clock source.\r
+  *           In this case, you have to select another source of the system\r
+  *           clock then stop the MSI.\r
+  * @note     After enabling the MSI, the application software should wait on\r
+  *           MSIRDY flag to be set indicating that MSI clock is stable and can\r
+  *           be used as system clock source.\r
+  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
+  *         clock cycles.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)\r
+\r
+#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)\r
+\r
+/** @brief  Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
+  * @note   The calibration is used to compensate for the variations in voltage\r
+  *         and temperature that influence the frequency of the internal MSI RC.\r
+  *         Refer to the Application Note AN3300 for more details on how to\r
+  *         calibrate the MSI.\r
+  * @param  __MSICALIBRATIONVALUE__ specifies the calibration trimming value\r
+  *         (default is RCC_MSICALIBRATION_DEFAULT).\r
+  *         This parameter must be a number between 0 and 255.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \\r
+                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)\r
+\r
+/**\r
+  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode\r
+  * @note     After restart from Reset , the MSI clock is around 4 MHz.\r
+  *           After stop the startup clock can be MSI (at any of its possible\r
+  *           frequencies, the one that was used before entering stop mode) or HSI.\r
+  *          After Standby its frequency can be selected between 4 possible values\r
+  *          (1, 2, 4 or 8 MHz).\r
+  * @note     MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready\r
+  *          (MSIRDY=1).\r
+  * @note    The MSI clock range after reset can be modified on the fly.\r
+  * @param  __MSIRANGEVALUE__ specifies the MSI clock range.\r
+  *         This parameter must be one of the following values:\r
+  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz\r
+  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz\r
+  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz\r
+  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz\r
+  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz\r
+  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz\r
+  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)\r
+  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz\r
+  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz\r
+  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz\r
+  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz\r
+  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \\r
+                  do {                                                         \\r
+                    SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \\r
+                    MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \\r
+                  } while(0)\r
+\r
+/**\r
+  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode\r
+  *         After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).\r
+  * @param  __MSIRANGEVALUE__ specifies the MSI clock range.\r
+  *         This parameter must be one of the following values:\r
+  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz\r
+  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz\r
+  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)\r
+  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \\r
+                  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)\r
+\r
+/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode\r
+  * @retval MSI clock range.\r
+  *         This parameter must be one of the following values:\r
+  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz\r
+  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz\r
+  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz\r
+  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz\r
+  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz\r
+  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz\r
+  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)\r
+  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz\r
+  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz\r
+  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz\r
+  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz\r
+  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz\r
+  */\r
+#define __HAL_RCC_GET_MSI_RANGE()                                              \\r
+                  ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ?             \\r
+                   READ_BIT(RCC->CR, RCC_CR_MSIRANGE) :                        \\r
+                   (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U))\r
+\r
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).\r
+  * @note   After enabling the LSI, the application software should wait on\r
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can\r
+  *         be used to clock the IWDG and/or the RTC.\r
+  * @note   LSI can not be disabled if the IWDG is running.\r
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+  *         clock cycles.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)\r
+\r
+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)\r
+\r
+/**\r
+  * @brief  Macro to configure the External High Speed oscillator (HSE).\r
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+  *         supported by this macro. User should request a transition to HSE Off\r
+  *         first and then HSE On or HSE Bypass.\r
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+  *         software should wait on HSERDY flag to be set indicating that HSE clock\r
+  *         is stable and can be used to clock the PLL and/or system clock.\r
+  * @note   HSE state can not be changed if it is used directly or through the\r
+  *         PLL as system clock. In this case, you have to select another source\r
+  *         of the system clock then change the HSE state (ex. disable it).\r
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)\r
+  *         was previously enabled you have to enable it again after calling this\r
+  *         function.\r
+  * @param  __STATE__ specifies the new state of the HSE.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after\r
+  *                              6 HSE oscillator clock cycles.\r
+  *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.\r
+  *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                      \\r
+                    do {                                     \\r
+                      if((__STATE__) == RCC_HSE_ON)          \\r
+                      {                                      \\r
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \\r
+                      }                                      \\r
+                      else if((__STATE__) == RCC_HSE_BYPASS) \\r
+                      {                                      \\r
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \\r
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \\r
+                      }                                      \\r
+                      else                                   \\r
+                      {                                      \\r
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \\r
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \\r
+                      }                                      \\r
+                    } while(0)\r
+\r
+/**\r
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).\r
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
+  *         supported by this macro. User should request a transition to LSE Off\r
+  *         first and then LSE On or LSE Bypass.\r
+  * @note   As the LSE is in the Backup domain and write access is denied to\r
+  *         this domain after reset, you have to enable write access using\r
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+  *         (to be done once after reset).\r
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
+  *         software should wait on LSERDY flag to be set indicating that LSE clock\r
+  *         is stable and can be used to clock the RTC.\r
+  * @param  __STATE__ specifies the new state of the LSE.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after\r
+  *                              6 LSE oscillator clock cycles.\r
+  *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.\r
+  *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LSE_CONFIG(__STATE__)                        \\r
+                    do {                                       \\r
+                      if((__STATE__) == RCC_LSE_ON)            \\r
+                      {                                        \\r
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\r
+                      }                                        \\r
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \\r
+                      {                                        \\r
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \\r
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\r
+                      }                                        \\r
+                      else                                     \\r
+                      {                                        \\r
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \\r
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+                      }                                        \\r
+                    } while(0)\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+\r
+/** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).\r
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.\r
+  * @note   After enabling the HSI48, the application software should wait on HSI48RDY\r
+  *         flag to be set indicating that HSI48 clock is stable.\r
+  *         This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_HSI48_ENABLE()  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)\r
+\r
+#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)\r
+\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+/** @brief  Macros to configure the RTC clock (RTCCLK).\r
+  * @note   As the RTC clock configuration bits are in the Backup domain and write\r
+  *         access is denied to this domain after reset, you have to enable write\r
+  *         access using the Power Backup Access macro before to configure\r
+  *         the RTC clock source (to be done once after reset).\r
+  * @note   Once the RTC clock is configured it cannot be changed unless the\r
+  *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by\r
+  *         a Power On Reset (POR).\r
+  *\r
+  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.\r
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.\r
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.\r
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected\r
+  *\r
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.\r
+  *         However, when the HSE clock is used as RTC clock source, the RTC\r
+  *         cannot be used in STOP and STANDBY modes.\r
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+  *         RTC clock source).\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \\r
+                  MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))\r
+\r
+\r
+/** @brief  Macro to get the RTC clock source.\r
+  * @retval The returned value can be one of the following:\r
+  *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.\r
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.\r
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.\r
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected\r
+  */\r
+#define  __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))\r
+\r
+/** @brief  Macros to enable or disable the main PLL.\r
+  * @note   After enabling the main PLL, the application software should wait on\r
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can\r
+  *         be used as system clock source.\r
+  * @note   The main PLL can not be disabled if it is used as system clock source\r
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)\r
+\r
+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r
+\r
+/** @brief  Macro to configure the PLL clock source.\r
+  * @note   This function must be used only when the main PLL is disabled.\r
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry\r
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry\r
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry\r
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry\r
+  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).\r
+  * @retval None\r
+  *\r
+  */\r
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \\r
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r
+\r
+/** @brief  Macro to configure the PLL source division factor M.\r
+  * @note   This function must be used only when the main PLL is disabled.\r
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\r
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.\r
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r
+  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency\r
+  *         of 16 MHz to limit PLL jitter.\r
+  * @retval None\r
+  *\r
+  */\r
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \\r
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)\r
+\r
+/**\r
+  * @brief  Macro to configure the main PLL clock source, multiplication and division factors.\r
+  * @note   This function must be used only when the main PLL is disabled.\r
+  *\r
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry\r
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry\r
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry\r
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry\r
+  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).\r
+  *\r
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock.\r
+  *          This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
+  *          This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.\r
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r
+  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency\r
+  *         of 16 MHz to limit PLL jitter.\r
+  *\r
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock.\r
+  *          This parameter must be a number between 8 and 86.\r
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\r
+  *         output frequency is between 64 and 344 MHz.\r
+  *\r
+  * @param  __PLLP__ specifies the division factor for SAI clock when SAI available on device.\r
+  *          This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x\r
+  *          else (2 to 31).\r
+  *\r
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.\r
+  *          This parameter must be in the range (2, 4, 6 or 8).\r
+  * @note   If the USB OTG FS is used in your application, you have to set the\r
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
+  *         the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work\r
+  *         correctly.\r
+  * @param  __PLLR__ specifies the division factor for the main system clock.\r
+  * @note   You have to set the PLLR parameter correctly to not exceed 80MHZ.\r
+  *          This parameter must be in the range (2, 4, 6 or 8).\r
+  * @retval None\r
+  */\r
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
+\r
+#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \\r
+                  MODIFY_REG(RCC->PLLCFGR, \\r
+                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
+                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \\r
+                             ((__PLLSOURCE__) | \\r
+                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
+                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
+                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
+                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \\r
+                              ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))\r
+\r
+#elif defined(RCC_PLLP_SUPPORT)\r
+\r
+#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \\r
+                  MODIFY_REG(RCC->PLLCFGR, \\r
+                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
+                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \\r
+                             ((__PLLSOURCE__) | \\r
+                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
+                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
+                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
+                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \\r
+                              (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos)))\r
+\r
+#else\r
+\r
+#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \\r
+                  MODIFY_REG(RCC->PLLCFGR, \\r
+                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
+                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \\r
+                             ((__PLLSOURCE__) | \\r
+                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
+                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
+                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
+                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))\r
+\r
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
+\r
+/** @brief  Macro to get the oscillator used as PLL clock source.\r
+  * @retval The oscillator used as PLL clock source. The returned value can be one\r
+  *         of the following:\r
+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.\r
+  *              - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.\r
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r
+  */\r
+#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))\r
+\r
+/**\r
+  * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)\r
+  * @note   Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime\r
+  *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot\r
+  *         be stopped if used as System Clock.\r
+  * @param  __PLLCLOCKOUT__ specifies the PLL clock to be output.\r
+  *          This parameter can be one or a combination of the following values:\r
+  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                   high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),\r
+  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
+  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
+\r
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
+\r
+/**\r
+  * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)\r
+  * @param  __PLLCLOCKOUT__ specifies the output PLL clock to be checked.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                   high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),\r
+  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
+  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)\r
+  * @retval SET / RESET\r
+  */\r
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
+\r
+/**\r
+  * @brief  Macro to configure the system clock source.\r
+  * @param  __SYSCLKSOURCE__ specifies the system clock source.\r
+  *          This parameter can be one of the following values:\r
+  *              - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.\r
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))\r
+\r
+/** @brief  Macro to get the clock source used as system clock.\r
+  * @retval The clock source used as system clock. The returned value can be one\r
+  *         of the following:\r
+  *              - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.\r
+  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r
+  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r
+  */\r
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))\r
+\r
+/**\r
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.\r
+  * @note   As the LSE is in the Backup domain and write access is denied to\r
+  *         this domain after reset, you have to enable write access using\r
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+  *         (to be done once after reset).\r
+  * @param  __LSEDRIVE__ specifies the new state of the LSE drive capability.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.\r
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.\r
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.\r
+  *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \\r
+                  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))\r
+\r
+/**\r
+  * @brief  Macro to configure the wake up from stop clock.\r
+  * @param  __STOPWUCLK__ specifies the clock source used after wake up from stop.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI selected as system clock source\r
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI selected as system clock source\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \\r
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))\r
+\r
+\r
+/** @brief  Macro to configure the MCO clock.\r
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled\r
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee\r
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48\r
+  @endif\r
+  * @param  __MCODIV__ specifies the MCO clock prescaler.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1\r
+  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2\r
+  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4\r
+  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8\r
+  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16\r
+  */\r
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r
+\r
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
+  * @brief macros to manage the specified RCC Flags and interrupts.\r
+  * @{\r
+  */\r
+\r
+/** @brief  Enable RCC interrupt(s).\r
+  * @param  __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.\r
+  *         This parameter can be any combination of the following values:\r
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
+  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))\r
+\r
+/** @brief Disable RCC interrupt(s).\r
+  * @param  __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.\r
+  *         This parameter can be any combination of the following values:\r
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
+  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))\r
+\r
+/** @brief  Clear the RCC's interrupt pending bits.\r
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+  *         This parameter can be any combination of the following values:\r
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
+  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
+  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt\r
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))\r
+\r
+/** @brief  Check whether the RCC interrupt has occurred or not.\r
+  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
+  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
+  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt\r
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
+  @endif\r
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/** @brief Set RMVF bit to clear the reset flags.\r
+  *        The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,\r
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r
+  * @retval None\r
+ */\r
+#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)\r
+\r
+/** @brief  Check whether the selected RCC flag is set or not.\r
+  * @param  __FLAG__ specifies the flag to check.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_FLAG_MSIRDY  MSI oscillator clock ready\r
+  *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready\r
+  *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready\r
+  *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready\r
+  *            @arg @ref RCC_FLAG_PLLSAI1RDY  PLLSAI1 clock ready for devices with PLLSAI1\r
+  *            @arg @ref RCC_FLAG_PLLSAI2RDY  PLLSAI2 clock ready for devices with PLLSAI2\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48\r
+  @endif\r
+  *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready\r
+  *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection\r
+  *            @arg @ref RCC_FLAG_LSIRDY  LSI oscillator clock ready\r
+  *            @arg @ref RCC_FLAG_BORRST  BOR reset\r
+  *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset\r
+  *            @arg @ref RCC_FLAG_PINRST  Pin reset\r
+  *            @arg @ref RCC_FLAG_FWRST  FIREWALL reset\r
+  *            @arg @ref RCC_FLAG_SFTRST  Software reset\r
+  *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset\r
+  *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset\r
+  *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset\r
+  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+  */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \\r
+                                        ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR :                 \\r
+                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \\r
+                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) &   \\r
+                                          (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)\r
+#else\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \\r
+                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \\r
+                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) &    \\r
+                                          (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Constants RCC Private Constants\r
+  * @{\r
+  */\r
+/* Defines used for Flags */\r
+#define CR_REG_INDEX              1U\r
+#define BDCR_REG_INDEX            2U\r
+#define CSR_REG_INDEX             3U\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define CRRCR_REG_INDEX           4U\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+#define RCC_FLAG_MASK             0x1FU\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCC_Private_Macros\r
+  * @{\r
+  */\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)   == RCC_OSCILLATORTYPE_MSI)   || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE))\r
+#else\r
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \\r
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+#define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \\r
+                              ((__HSE__) == RCC_HSE_BYPASS))\r
+\r
+#if defined(RCC_BDCR_LSESYSDIS)\r
+#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \\r
+                              ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS))\r
+#else\r
+#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \\r
+                              ((__LSE__) == RCC_LSE_BYPASS))\r
+#endif /* RCC_BDCR_LSESYSDIS */\r
+\r
+#define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))\r
+\r
+#define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))\r
+\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+#define IS_RCC_LSIDIV(__LSIDIV__)  (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+\r
+#define IS_RCC_MSI(__MSI__)  (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))\r
+\r
+#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \\r
+                             ((__PLL__) == RCC_PLL_ON))\r
+\r
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \\r
+                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \\r
+                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \\r
+                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))\r
+\r
+#if defined(RCC_PLLM_DIV_1_16_SUPPORT)\r
+#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))\r
+#else\r
+#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))\r
+#endif /*RCC_PLLM_DIV_1_16_SUPPORT */\r
+\r
+#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))\r
+\r
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
+#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))\r
+#else\r
+#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))\r
+#endif /*RCC_PLLP_DIV_2_31_SUPPORT */\r
+\r
+#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
+                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
+\r
+#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
+                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \\r
+                                                  (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK)  || \\r
+                                                  (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \\r
+                                                 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK)  || \\r
+                                                  (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \\r
+                                                 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))\r
+#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK)  || \\r
+                                                  (((__VALUE__) & RCC_PLLSAI2_DSICLK)  == RCC_PLLSAI2_DSICLK)   || \\r
+                                                  (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \\r
+                                                 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U))\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_1)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_2)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_3)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_4)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_5)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_6)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_7)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_8)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_9)  || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_10) || \\r
+                                           ((__RANGE__) == RCC_MSIRANGE_11))\r
+\r
+#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4)  || \\r
+                                                   ((__RANGE__) == RCC_MSIRANGE_5)  || \\r
+                                                   ((__RANGE__) == RCC_MSIRANGE_6)  || \\r
+                                                   ((__RANGE__) == RCC_MSIRANGE_7))\r
+\r
+#define IS_RCC_CLOCKTYPE(__CLK__)  ((1U <= (__CLK__)) && ((__CLK__) <= 15U))\r
+\r
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \\r
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \\r
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \\r
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))\r
+\r
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \\r
+                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \\r
+                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \\r
+                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \\r
+                               ((__HCLK__) == RCC_SYSCLK_DIV512))\r
+\r
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \\r
+                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \\r
+                               ((__PCLK__) == RCC_HCLK_DIV16))\r
+\r
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE)   || \\r
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \\r
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \\r
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))\r
+\r
+#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))\r
+#else\r
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \\r
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE))\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \\r
+                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \\r
+                                ((__DIV__) == RCC_MCODIV_16))\r
+\r
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \\r
+                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \\r
+                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \\r
+                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))\r
+\r
+#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \\r
+                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include RCC HAL Extended module */\r
+#include "stm32l4xx_hal_rcc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCC_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+\r
+/* Initialization and de-initialization functions  ******************************/\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void);\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+\r
+/* Peripheral Control functions  ************************************************/\r
+void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
+void              HAL_RCC_EnableCSS(void);\r
+uint32_t          HAL_RCC_GetSysClockFreq(void);\r
+uint32_t          HAL_RCC_GetHCLKFreq(void);\r
+uint32_t          HAL_RCC_GetPCLK1Freq(void);\r
+uint32_t          HAL_RCC_GetPCLK2Freq(void);\r
+void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
+/* CSS NMI IRQ handler */\r
+void              HAL_RCC_NMI_IRQHandler(void);\r
+/* User Callbacks in non blocking mode (IT mode) */\r
+void              HAL_RCC_CSSCallback(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_RCC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
new file mode 100644 (file)
index 0000000..8f5a2fb
--- /dev/null
@@ -0,0 +1,3125 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_rcc_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of RCC HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L4xx_HAL_RCC_EX_H\r
+#define __STM32L4xx_HAL_RCC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup RCCEx\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
+  * @{\r
+  */\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+/**\r
+  * @brief  PLLSAI1 Clock structure definition\r
+  */\r
+typedef struct\r
+{\r
+\r
+  uint32_t PLLSAI1Source;    /*!< PLLSAI1Source: PLLSAI1 entry clock source.\r
+                                  This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
+\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+  uint32_t PLLSAI1M;         /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.\r
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r
+#else\r
+  uint32_t PLLSAI1M;         /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.\r
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 8 */\r
+#endif\r
+\r
+  uint32_t PLLSAI1N;         /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.\r
+                                  This parameter must be a number between 8 and 86 or 127 depending on devices. */\r
+\r
+  uint32_t PLLSAI1P;         /*!< PLLSAI1P: specifies the division factor for SAI clock.\r
+                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
+\r
+  uint32_t PLLSAI1Q;         /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.\r
+                                  This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */\r
+\r
+  uint32_t PLLSAI1R;         /*!< PLLSAI1R: specifies the division factor for ADC clock.\r
+                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */\r
+\r
+  uint32_t PLLSAI1ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.\r
+                                  This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */\r
+}RCC_PLLSAI1InitTypeDef;\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+/**\r
+  * @brief  PLLSAI2 Clock structure definition\r
+  */\r
+typedef struct\r
+{\r
+\r
+  uint32_t PLLSAI2Source;    /*!< PLLSAI2Source: PLLSAI2 entry clock source.\r
+                                  This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
+\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+  uint32_t PLLSAI2M;         /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.\r
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r
+#else\r
+  uint32_t PLLSAI2M;         /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.\r
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 8 */\r
+#endif\r
+\r
+  uint32_t PLLSAI2N;         /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.\r
+                                  This parameter must be a number between 8 and 86 or 127 depending on devices. */\r
+\r
+  uint32_t PLLSAI2P;         /*!< PLLSAI2P: specifies the division factor for SAI clock.\r
+                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
+\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+  uint32_t PLLSAI2Q;         /*!< PLLSAI2Q: specifies the division factor for DSI clock.\r
+                                  This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */\r
+#endif\r
+\r
+  uint32_t PLLSAI2R;         /*!< PLLSAI2R: specifies the division factor for ADC clock.\r
+                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */\r
+\r
+  uint32_t PLLSAI2ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.\r
+                                  This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */\r
+}RCC_PLLSAI2InitTypeDef;\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+/**\r
+  * @brief  RCC extended clocks structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.\r
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+  RCC_PLLSAI1InitTypeDef PLLSAI1;  /*!< PLLSAI1 structure parameters.\r
+                                        This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+  RCC_PLLSAI2InitTypeDef PLLSAI2;  /*!< PLLSAI2 structure parameters.\r
+                                        This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+  uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source */\r
+\r
+  uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source */\r
+\r
+#if defined(USART3)\r
+\r
+  uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_USART3_Clock_Source */\r
+\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+\r
+  uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_UART4_Clock_Source */\r
+\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+\r
+  uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_UART5_Clock_Source */\r
+\r
+#endif /* UART5 */\r
+\r
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */\r
+\r
+  uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */\r
+\r
+#if defined(I2C2)\r
+\r
+  uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */\r
+\r
+#endif /* I2C2 */\r
+\r
+  uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */\r
+\r
+#if defined(I2C4)\r
+\r
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r
+\r
+#endif /* I2C4 */\r
+\r
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r
+\r
+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */\r
+#if defined(SAI1)\r
+\r
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+\r
+  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\r
+\r
+#endif /* SAI2 */\r
+\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+\r
+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).\r
+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source */\r
+\r
+#endif /* USB_OTG_FS || USB */\r
+\r
+#if defined(SDMMC1)\r
+\r
+  uint32_t Sdmmc1ClockSelection;   /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).\r
+                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */\r
+\r
+#endif /* SDMMC1 */\r
+\r
+  uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).\r
+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source */\r
+\r
+#if !defined(STM32L412xx) && !defined(STM32L422xx)\r
+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.\r
+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source */\r
+#endif /* !STM32L412xx && !STM32L422xx */\r
+\r
+#if defined(SWPMI1)\r
+\r
+  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */\r
+\r
+#endif /* SWPMI1 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+\r
+  uint32_t Dfsdm1ClockSelection;   /*!< Specifies DFSDM1 clock source.\r
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+  uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source.\r
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+\r
+  uint32_t LtdcClockSelection;     /*!< Specifies LTDC clock source.\r
+                                        This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */\r
+\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+\r
+  uint32_t DsiClockSelection;      /*!< Specifies DSI clock source.\r
+                                        This parameter can be a value of @ref RCCEx_DSI_Clock_Source */\r
+\r
+#endif /* DSI */\r
+\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+\r
+  uint32_t OspiClockSelection;     /*!< Specifies OctoSPI clock source.\r
+                                        This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */\r
+\r
+#endif\r
+\r
+  uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.\r
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */\r
+}RCC_PeriphCLKInitTypeDef;\r
+\r
+#if defined(CRS)\r
+\r
+/**\r
+  * @brief RCC_CRS Init structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.\r
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */\r
+\r
+  uint32_t Source;                /*!< Specifies the SYNC signal source.\r
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource */\r
+\r
+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.\r
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */\r
+\r
+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.\r
+                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)\r
+                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/\r
+\r
+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.\r
+                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */\r
+\r
+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.\r
+                                     This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise,\r
+                                     or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */\r
+\r
+}RCC_CRSInitTypeDef;\r
+\r
+/**\r
+  * @brief RCC_CRS Synchronization structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.\r
+                                     This parameter must be a number between 0 and 0xFFFF */\r
+\r
+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.\r
+                                     This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */\r
+\r
+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter\r
+                                                                    value latched in the time of the last SYNC event.\r
+                                    This parameter must be a number between 0 and 0xFFFF */\r
+\r
+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the\r
+                                                                    frequency error counter latched in the time of the last SYNC event.\r
+                                                                    It shows whether the actual frequency is below or above the target.\r
+                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/\r
+\r
+}RCC_CRSSynchroInfoTypeDef;\r
+\r
+#endif /* CRS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source\r
+  * @{\r
+  */\r
+#define RCC_LSCOSOURCE_LSI             0x00000000U         /*!< LSI selection for low speed clock output */\r
+#define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL    /*!< LSE selection for low speed clock output */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection\r
+  * @{\r
+  */\r
+#define RCC_PERIPHCLK_USART1           0x00000001U\r
+#define RCC_PERIPHCLK_USART2           0x00000002U\r
+#if defined(USART3)\r
+#define RCC_PERIPHCLK_USART3           0x00000004U\r
+#endif\r
+#if defined(UART4)\r
+#define RCC_PERIPHCLK_UART4            0x00000008U\r
+#endif\r
+#if defined(UART5)\r
+#define RCC_PERIPHCLK_UART5            0x00000010U\r
+#endif\r
+#define RCC_PERIPHCLK_LPUART1          0x00000020U\r
+#define RCC_PERIPHCLK_I2C1             0x00000040U\r
+#if defined(I2C2)\r
+#define RCC_PERIPHCLK_I2C2             0x00000080U\r
+#endif\r
+#define RCC_PERIPHCLK_I2C3             0x00000100U\r
+#define RCC_PERIPHCLK_LPTIM1           0x00000200U\r
+#define RCC_PERIPHCLK_LPTIM2           0x00000400U\r
+#if defined(SAI1)\r
+#define RCC_PERIPHCLK_SAI1             0x00000800U\r
+#endif\r
+#if defined(SAI2)\r
+#define RCC_PERIPHCLK_SAI2             0x00001000U\r
+#endif\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+#define RCC_PERIPHCLK_USB              0x00002000U\r
+#endif\r
+#define RCC_PERIPHCLK_ADC              0x00004000U\r
+#if defined(SWPMI1)\r
+#define RCC_PERIPHCLK_SWPMI1           0x00008000U\r
+#endif\r
+#if defined(DFSDM1_Filter0)\r
+#define RCC_PERIPHCLK_DFSDM1           0x00010000U\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define RCC_PERIPHCLK_DFSDM1AUDIO      0x00200000U\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#endif\r
+#define RCC_PERIPHCLK_RTC              0x00020000U\r
+#define RCC_PERIPHCLK_RNG              0x00040000U\r
+#if defined(SDMMC1)\r
+#define RCC_PERIPHCLK_SDMMC1           0x00080000U\r
+#endif\r
+#if defined(I2C4)\r
+#define RCC_PERIPHCLK_I2C4             0x00100000U\r
+#endif\r
+#if defined(LTDC)\r
+#define RCC_PERIPHCLK_LTDC             0x00400000U\r
+#endif\r
+#if defined(DSI)\r
+#define RCC_PERIPHCLK_DSI              0x00800000U\r
+#endif\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+#define RCC_PERIPHCLK_OSPI             0x01000000U\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_USART1CLKSOURCE_PCLK2      0x00000000U\r
+#define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0\r
+#define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1\r
+#define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_USART2CLKSOURCE_PCLK1      0x00000000U\r
+#define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0\r
+#define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1\r
+#define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(USART3)\r
+/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_USART3CLKSOURCE_PCLK1      0x00000000U\r
+#define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0\r
+#define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1\r
+#define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)\r
+/**\r
+  * @}\r
+  */\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_UART4CLKSOURCE_PCLK1       0x00000000U\r
+#define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0\r
+#define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1\r
+#define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)\r
+/**\r
+  * @}\r
+  */\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_UART5CLKSOURCE_PCLK1       0x00000000U\r
+#define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0\r
+#define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1\r
+#define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)\r
+/**\r
+  * @}\r
+  */\r
+#endif /* UART5 */\r
+\r
+/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_LPUART1CLKSOURCE_PCLK1     0x00000000U\r
+#define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0\r
+#define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1\r
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_I2C1CLKSOURCE_PCLK1        0x00000000U\r
+#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0\r
+#define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(I2C2)\r
+/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_I2C2CLKSOURCE_PCLK1        0x00000000U\r
+#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0\r
+#define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1\r
+/**\r
+  * @}\r
+  */\r
+#endif /* I2C2 */\r
+\r
+/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_I2C3CLKSOURCE_PCLK1        0x00000000U\r
+#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0\r
+#define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(I2C4)\r
+/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_I2C4CLKSOURCE_PCLK1        0x00000000U\r
+#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_CCIPR2_I2C4SEL_0\r
+#define RCC_I2C4CLKSOURCE_HSI          RCC_CCIPR2_I2C4SEL_1\r
+/**\r
+  * @}\r
+  */\r
+#endif /* I2C4 */\r
+\r
+#if defined(SAI1)\r
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_SAI1CLKSOURCE_PLLSAI1      0x00000000U\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR2_SAI1SEL_0\r
+#else\r
+#define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI1SEL_0\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR2_SAI1SEL_1\r
+#define RCC_SAI1CLKSOURCE_PIN          (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)\r
+#define RCC_SAI1CLKSOURCE_HSI          RCC_CCIPR2_SAI1SEL_2\r
+#else\r
+#define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_1\r
+#define RCC_SAI1CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_SAI2CLKSOURCE_PLLSAI1      0x00000000U\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR2_SAI2SEL_0\r
+#define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR2_SAI2SEL_1\r
+#define RCC_SAI2CLKSOURCE_PIN          (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)\r
+#define RCC_SAI2CLKSOURCE_HSI          RCC_CCIPR2_SAI2SEL_2\r
+#else\r
+#define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI2SEL_0\r
+#define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR_SAI2SEL_1\r
+#define RCC_SAI2CLKSOURCE_PIN          RCC_CCIPR_SAI2SEL\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* SAI2 */\r
+\r
+/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_LPTIM1CLKSOURCE_PCLK1      0x00000000U\r
+#define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0\r
+#define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1\r
+#define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_LPTIM2CLKSOURCE_PCLK1      0x00000000U\r
+#define RCC_LPTIM2CLKSOURCE_LSI        RCC_CCIPR_LPTIM2SEL_0\r
+#define RCC_LPTIM2CLKSOURCE_HSI        RCC_CCIPR_LPTIM2SEL_1\r
+#define RCC_LPTIM2CLKSOURCE_LSE        RCC_CCIPR_LPTIM2SEL\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(SDMMC1)\r
+/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source\r
+  * @{\r
+  */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define RCC_SDMMC1CLKSOURCE_HSI48      0x00000000U  /*!< HSI48 clock selected as SDMMC1 clock          */\r
+#else\r
+#define RCC_SDMMC1CLKSOURCE_NONE       0x00000000U  /*!< No clock selected as SDMMC1 clock             */\r
+#endif /* RCC_HSI48_SUPPORT */\r
+#define RCC_SDMMC1CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0     /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock    */\r
+#define RCC_SDMMC1CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1     /*!< PLL "Q" clock selected as SDMMC1 clock        */\r
+#define RCC_SDMMC1CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL       /*!< MSI clock selected as SDMMC1 clock            */\r
+#if defined(RCC_CCIPR2_SDMMCSEL)\r
+#define RCC_SDMMC1CLKSOURCE_PLLP       RCC_CCIPR2_SDMMCSEL      /*!< PLL "P" clock selected as SDMMC1 kernel clock */\r
+#endif /* RCC_CCIPR2_SDMMCSEL */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* SDMMC1 */\r
+\r
+/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source\r
+  * @{\r
+  */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define RCC_RNGCLKSOURCE_HSI48         0x00000000U\r
+#else\r
+#define RCC_RNGCLKSOURCE_NONE          0x00000000U\r
+#endif /* RCC_HSI48_SUPPORT */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define RCC_RNGCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1\r
+#define RCC_RNGCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+/** @defgroup RCCEx_USB_Clock_Source USB Clock Source\r
+  * @{\r
+  */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+#define RCC_USBCLKSOURCE_HSI48         0x00000000U\r
+#else\r
+#define RCC_USBCLKSOURCE_NONE          0x00000000U\r
+#endif /* RCC_HSI48_SUPPORT */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define RCC_USBCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1\r
+#define RCC_USBCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL\r
+/**\r
+  * @}\r
+  */\r
+#endif /* USB_OTG_FS || USB */\r
+\r
+/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source\r
+  * @{\r
+  */\r
+#define RCC_ADCCLKSOURCE_NONE         0x00000000U\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define RCC_ADCCLKSOURCE_PLLSAI1      RCC_CCIPR_ADCSEL_0\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+#define RCC_ADCCLKSOURCE_PLLSAI2      RCC_CCIPR_ADCSEL_1\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
+#if defined(RCC_CCIPR_ADCSEL)\r
+#define RCC_ADCCLKSOURCE_SYSCLK       RCC_CCIPR_ADCSEL\r
+#else\r
+#define RCC_ADCCLKSOURCE_SYSCLK       0x30000000U\r
+#endif /* RCC_CCIPR_ADCSEL */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(SWPMI1)\r
+/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_SWPMI1CLKSOURCE_PCLK1      0x00000000U\r
+#define RCC_SWPMI1CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL\r
+/**\r
+  * @}\r
+  */\r
+#endif /* SWPMI1 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source\r
+  * @{\r
+  */\r
+#define RCC_DFSDM1CLKSOURCE_PCLK2      0x00000000U\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define RCC_DFSDM1CLKSOURCE_SYSCLK     RCC_CCIPR2_DFSDM1SEL\r
+#else\r
+#define RCC_DFSDM1CLKSOURCE_SYSCLK     RCC_CCIPR_DFSDM1SEL\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source\r
+  * @{\r
+  */\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1   0x00000000U\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_HSI    RCC_CCIPR2_ADFSDM1SEL_0\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_MSI    RCC_CCIPR2_ADFSDM1SEL_1\r
+/**\r
+  * @}\r
+  */\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source\r
+  * @{\r
+  */\r
+#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2  0x00000000U\r
+#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4  RCC_CCIPR2_PLLSAI2DIVR_0\r
+#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8  RCC_CCIPR2_PLLSAI2DIVR_1\r
+#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR\r
+/**\r
+  * @}\r
+  */\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source\r
+  * @{\r
+  */\r
+#define RCC_DSICLKSOURCE_DSIPHY        0x00000000U\r
+#define RCC_DSICLKSOURCE_PLLSAI2       RCC_CCIPR2_DSISEL\r
+/**\r
+  * @}\r
+  */\r
+#endif /* DSI */\r
+\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source\r
+  * @{\r
+  */\r
+#define RCC_OSPICLKSOURCE_SYSCLK    0x00000000U\r
+#define RCC_OSPICLKSOURCE_MSI       RCC_CCIPR2_OSPISEL_0\r
+#define RCC_OSPICLKSOURCE_PLL       RCC_CCIPR2_OSPISEL_1\r
+/**\r
+  * @}\r
+  */\r
+#endif /* OCTOSPI1 || OCTOSPI2 */\r
+\r
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line\r
+  * @{\r
+  */\r
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(CRS)\r
+\r
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status\r
+  * @{\r
+  */\r
+#define RCC_CRS_NONE                   0x00000000U\r
+#define RCC_CRS_TIMEOUT                0x00000001U\r
+#define RCC_CRS_SYNCOK                 0x00000002U\r
+#define RCC_CRS_SYNCWARN               0x00000004U\r
+#define RCC_CRS_SYNCERR                0x00000008U\r
+#define RCC_CRS_SYNCMISS               0x00000010U\r
+#define RCC_CRS_TRIMOVF                0x00000020U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource\r
+  * @{\r
+  */\r
+#define RCC_CRS_SYNC_SOURCE_GPIO       0x00000000U             /*!< Synchro Signal source GPIO */\r
+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */\r
+#define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider\r
+  * @{\r
+  */\r
+#define RCC_CRS_SYNC_DIV1        0x00000000U                               /*!< Synchro Signal not divided (default) */\r
+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */\r
+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */\r
+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */\r
+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */\r
+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */\r
+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */\r
+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity\r
+  * @{\r
+  */\r
+#define RCC_CRS_SYNC_POLARITY_RISING   0x00000000U         /*!< Synchro Active on rising edge (default) */\r
+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL    /*!< Synchro Active on falling edge */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault\r
+  * @{\r
+  */\r
+#define RCC_CRS_RELOADVALUE_DEFAULT    0x0000BB7FU   /*!< The reset value of the RELOAD field corresponds\r
+                                                          to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault\r
+  * @{\r
+  */\r
+#define RCC_CRS_ERRORLIMIT_DEFAULT     0x00000022U   /*!< Default Frequency error limit */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault\r
+  * @{\r
+  */\r
+#if defined(STM32L412xx) || defined(STM32L422xx)\r
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval.\r
+                                                          The trimming step is specified in the product datasheet. A higher TRIM value\r
+                                                          corresponds to a higher output frequency */\r
+#else\r
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval.\r
+                                                          The trimming step is specified in the product datasheet. A higher TRIM value\r
+                                                          corresponds to a higher output frequency */\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection\r
+  * @{\r
+  */\r
+#define RCC_CRS_FREQERRORDIR_UP        0x00000000U   /*!< Upcounting direction, the actual frequency is above the target */\r
+#define RCC_CRS_FREQERRORDIR_DOWN      CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources\r
+  * @{\r
+  */\r
+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */\r
+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */\r
+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */\r
+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */\r
+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */\r
+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */\r
+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags\r
+  * @{\r
+  */\r
+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */\r
+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */\r
+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */\r
+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */\r
+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */\r
+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/\r
+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* CRS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
+ * @{\r
+ */\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+/**\r
+  * @brief  Macro to configure the PLLSAI1 clock multiplication and division factors.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI1 is disabled.\r
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  @if STM32L4S9xx\r
+  * @param  __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock.\r
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
+  *\r
+  @endif\r
+  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.\r
+  *         This parameter must be a number between 8 and 86.\r
+  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO\r
+  *         output frequency is between 64 and 344 MHz.\r
+  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N\r
+  *\r
+  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.\r
+  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx\r
+  *         else (2 to 31).\r
+  *         SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P\r
+  *\r
+  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.\r
+  *         This parameter must be in the range (2, 4, 6 or 8).\r
+  *         USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q\r
+  *\r
+  * @param  __PLLSAI1R__ specifies the division factor for SAR ADC clock.\r
+  *         This parameter must be in the range (2, 4, 6 or 8).\r
+  *         ADC clock frequency = f(PLLSAI1) / PLLSAI1R\r
+  *\r
+  * @retval None\r
+  */\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+\r
+#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
+                             (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
+                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \\r
+                             ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \\r
+                              ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
+                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
+                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
+                              ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))\r
+\r
+#else\r
+\r
+#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
+                             (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
+                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \\r
+                             ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \\r
+                              ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
+                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
+                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
+                              (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))\r
+\r
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
+\r
+#else\r
+\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+\r
+#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
+                             (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
+                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \\r
+                             (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
+                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
+                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
+                              ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))\r
+\r
+#else\r
+\r
+#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
+                             (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
+                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \\r
+                             (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
+                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
+                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
+                              (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))\r
+\r
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
+\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+\r
+/**\r
+  * @brief  Macro to configure the PLLSAI1 clock multiplication factor N.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI1 is disabled.\r
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.\r
+  *          This parameter must be a number between 8 and 86.\r
+  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO\r
+  *         output frequency is between 64 and 344 MHz.\r
+  *         Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)\r
+\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+\r
+/** @brief  Macro to configure the PLLSAI1 input clock division factor M.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI1 is disabled.\r
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI1M__ specifies the division factor for PLLSAI1 clock.\r
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
+  *\r
+  * @retval None\r
+  */\r
+\r
+#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)\r
+\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+\r
+/** @brief  Macro to configure the PLLSAI1 clock division factor P.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI1 is disabled.\r
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.\r
+  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx\r
+  *         else (2 to 31).\r
+  *         Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P\r
+  *\r
+  * @retval None\r
+  */\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+\r
+#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)\r
+\r
+#else\r
+\r
+#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)\r
+\r
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
+\r
+/** @brief  Macro to configure the PLLSAI1 clock division factor Q.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI1 is disabled.\r
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.\r
+  *         This parameter must be in the range (2, 4, 6 or 8).\r
+  *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)\r
+\r
+/** @brief  Macro to configure the PLLSAI1 clock division factor R.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI1 is disabled.\r
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI1R__ specifies the division factor for ADC clock.\r
+  *         This parameter must be in the range (2, 4, 6 or 8)\r
+  *         Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \\r
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)\r
+\r
+/**\r
+  * @brief  Macros to enable or disable the PLLSAI1.\r
+  * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.\r
+  * @retval None\r
+  */\r
+\r
+#define __HAL_RCC_PLLSAI1_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)\r
+\r
+#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)\r
+\r
+/**\r
+  * @brief  Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).\r
+  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.\r
+  *         This is mainly used to save Power.\r
+  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.\r
+  *         This parameter can be one or a combination of the following values:\r
+  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                   high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),\r
+  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
+  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.\r
+  * @retval None\r
+  */\r
+\r
+#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__)   SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))\r
+\r
+#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__)  CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))\r
+\r
+/**\r
+  * @brief  Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).\r
+  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                   high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),\r
+  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
+  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.\r
+  * @retval SET / RESET\r
+  */\r
+#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__)  READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+/**\r
+  * @brief  Macro to configure the PLLSAI2 clock multiplication and division factors.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI2 is disabled.\r
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  @if STM32L4S9xx\r
+  * @param  __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock.\r
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
+  *\r
+  @endif\r
+  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.\r
+  *          This parameter must be a number between 8 and 86.\r
+  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO\r
+  *         output frequency is between 64 and 344 MHz.\r
+  *\r
+  * @param  __PLLSAI2P__ specifies the division factor for SAI clock.\r
+  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx\r
+  *         else (2 to 31).\r
+  *         SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P\r
+  *\r
+  @if STM32L4S9xx\r
+  * @param  __PLLSAI2Q__ specifies the division factor for DSI clock.\r
+  *         This parameter must be in the range (2, 4, 6 or 8).\r
+  *         DSI clock frequency = f(PLLSAI2) / PLLSAI2Q\r
+  *\r
+  @endif\r
+  * @param  __PLLSAI2R__ specifies the division factor for SAR ADC clock.\r
+  *         This parameter must be in the range (2, 4, 6 or 8).\r
+  *\r
+  * @retval None\r
+  */\r
+\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+\r
+# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+\r
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
+                             (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
+                              RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
+                             ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \\r
+                              ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
+                              ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \\r
+                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
+                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
+\r
+# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
+\r
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
+                             (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
+                              RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
+                             ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \\r
+                              ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
+                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
+                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
+\r
+# else\r
+\r
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
+                             (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
+                              RCC_PLLSAI2CFGR_PLLSAI2R), \\r
+                             ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \\r
+                              ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
+                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
+                              (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))\r
+\r
+# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
+\r
+#else\r
+\r
+#  if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+\r
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
+                             (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
+                              RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
+                             (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
+                              ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \\r
+                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
+                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
+\r
+# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
+\r
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
+                             (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
+                              RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
+                             (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
+                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
+                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
+\r
+# else\r
+\r
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
+                             (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
+                              RCC_PLLSAI2CFGR_PLLSAI2R), \\r
+                             (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
+                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
+                              (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))\r
+\r
+# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
+\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
+\r
+\r
+/**\r
+  * @brief  Macro to configure the PLLSAI2 clock multiplication factor N.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI2 is disabled.\r
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.\r
+  *          This parameter must be a number between 8 and 86.\r
+  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO\r
+  *         output frequency is between 64 and 344 MHz.\r
+  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)\r
+\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+\r
+/** @brief  Macro to configure the PLLSAI2 input clock division factor M.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI2 is disabled.\r
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI2M__ specifies the division factor for PLLSAI2 clock.\r
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
+  *\r
+  * @retval None\r
+  */\r
+\r
+#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M,  ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)\r
+\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
+\r
+/** @brief  Macro to configure the PLLSAI2 clock division factor P.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI2 is disabled.\r
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI2P__ specifies the division factor.\r
+  *         This parameter must be a number in the range (7 or 17).\r
+  *         Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)\r
+\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+\r
+/** @brief  Macro to configure the PLLSAI2 clock division factor Q.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI2 is disabled.\r
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock.\r
+  *         This parameter must be in the range (2, 4, 6 or 8).\r
+  *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)\r
+\r
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
+\r
+/** @brief  Macro to configure the PLLSAI2 clock division factor R.\r
+  *\r
+  * @note   This function must be used only when the PLLSAI2 is disabled.\r
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
+  *         __HAL_RCC_PLL_CONFIG() macro)\r
+  *\r
+  * @param  __PLLSAI2R__ specifies the division factor.\r
+  *         This parameter must be in the range (2, 4, 6 or 8).\r
+  *         Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__\r
+  *\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \\r
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)\r
+\r
+/**\r
+  * @brief  Macros to enable or disable the PLLSAI2.\r
+  * @note   The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.\r
+  * @retval None\r
+  */\r
+\r
+#define __HAL_RCC_PLLSAI2_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)\r
+\r
+#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)\r
+\r
+/**\r
+  * @brief  Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).\r
+  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.\r
+  *         This is mainly used to save Power.\r
+  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.\r
+  *         This parameter can be one or a combination of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                           high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                           high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                           high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI2_DSICLK   Clock used to clock DSI peripheral.\r
+  @endif\r
+  * @retval None\r
+  */\r
+\r
+#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__)  SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))\r
+\r
+#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))\r
+\r
+/**\r
+  * @brief  Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).\r
+  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.\r
+  *          This parameter can be one of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                           high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                           high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
+  *                                           high-quality audio performance on SAI interface in case.\r
+  *            @arg @ref RCC_PLLSAI2_DSICLK   Clock used to clock DSI peripheral.\r
+  @endif\r
+  * @retval SET / RESET\r
+  */\r
+#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__)  READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+#if defined(SAI1)\r
+\r
+/**\r
+  * @brief  Macro to configure the SAI1 clock source.\r
+  * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived\r
+  *         from the PLLSAI1, system PLL or external clock (through a dedicated pin).\r
+  *          This parameter can be one of the following values:\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
+  @if STM32L486xx\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2\r
+  @endif\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)\r
+  @if STM32L4S9xx\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_HSI  SAI1 clock = HSI16\r
+  @endif\r
+  *\r
+  @if STM32L443xx\r
+  * @note  HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.\r
+  @endif\r
+  *\r
+  * @retval None\r
+  */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__))\r
+#else\r
+#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/** @brief  Macro to get the SAI1 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
+  @if STM32L486xx\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2\r
+  @endif\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)\r
+  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)\r
+  *\r
+  * @note  Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1\r
+  *        clock source when PLLs are disabled for devices without PLLSAI2.\r
+  *\r
+  */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))\r
+#else\r
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+\r
+/**\r
+  * @brief  Macro to configure the SAI2 clock source.\r
+  * @param  __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived\r
+  *         from the PLLSAI2, system PLL or external clock (through a dedicated pin).\r
+  *          This parameter can be one of the following values:\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)\r
+  @if STM32L4S9xx\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_HSI  SAI2 clock = HSI16\r
+  @endif\r
+  *\r
+  * @retval None\r
+  */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__))\r
+#else\r
+#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/** @brief  Macro to get the SAI2 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)\r
+  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)\r
+  */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))\r
+#else\r
+#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* SAI2 */\r
+\r
+/** @brief  Macro to configure the I2C1 clock (I2C1CLK).\r
+  *\r
+  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock\r
+  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock\r
+  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the I2C1 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock\r
+  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock\r
+  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock\r
+  */\r
+#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))\r
+\r
+#if defined(I2C2)\r
+\r
+/** @brief  Macro to configure the I2C2 clock (I2C2CLK).\r
+  *\r
+  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock\r
+  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock\r
+  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the I2C2 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock\r
+  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock\r
+  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock\r
+  */\r
+#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))\r
+\r
+#endif /* I2C2 */\r
+\r
+/** @brief  Macro to configure the I2C3 clock (I2C3CLK).\r
+  *\r
+  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock\r
+  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock\r
+  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the I2C3 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock\r
+  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock\r
+  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock\r
+  */\r
+#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))\r
+\r
+#if defined(I2C4)\r
+\r
+/** @brief  Macro to configure the I2C4 clock (I2C4CLK).\r
+  *\r
+  * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock\r
+  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock\r
+  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the I2C4 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock\r
+  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock\r
+  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock\r
+  */\r
+#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))\r
+\r
+#endif /* I2C4 */\r
+\r
+\r
+/** @brief  Macro to configure the USART1 clock (USART1CLK).\r
+  *\r
+  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock\r
+  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock\r
+  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock\r
+  *            @arg @ref RCC_USART1CLKSOURCE_LSE  SE selected as USART1 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the USART1 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock\r
+  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock\r
+  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock\r
+  *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock\r
+  */\r
+#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))\r
+\r
+/** @brief  Macro to configure the USART2 clock (USART2CLK).\r
+  *\r
+  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock\r
+  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock\r
+  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock\r
+  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the USART2 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock\r
+  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock\r
+  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock\r
+  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock\r
+  */\r
+#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))\r
+\r
+#if defined(USART3)\r
+\r
+/** @brief  Macro to configure the USART3 clock (USART3CLK).\r
+  *\r
+  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock\r
+  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock\r
+  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock\r
+  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the USART3 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock\r
+  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock\r
+  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock\r
+  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock\r
+  */\r
+#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))\r
+\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+\r
+/** @brief  Macro to configure the UART4 clock (UART4CLK).\r
+  *\r
+  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock\r
+  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock\r
+  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock\r
+  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the UART4 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock\r
+  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock\r
+  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock\r
+  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock\r
+  */\r
+#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))\r
+\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+\r
+/** @brief  Macro to configure the UART5 clock (UART5CLK).\r
+  *\r
+  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock\r
+  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock\r
+  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock\r
+  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the UART5 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock\r
+  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock\r
+  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock\r
+  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock\r
+  */\r
+#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))\r
+\r
+#endif /* UART5 */\r
+\r
+/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).\r
+  *\r
+  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the LPUART1 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
+  */\r
+#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))\r
+\r
+/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).\r
+  *\r
+  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the LPTIM1 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
+  */\r
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))\r
+\r
+/** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).\r
+  *\r
+  * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPTIM2 clock\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPTIM2 clock\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  LSI selected as LPTIM2 clock\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPTIM2 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the LPTIM2 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  System Clock selected as LPUART1 clock\r
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
+  */\r
+#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))\r
+\r
+#if defined(SDMMC1)\r
+\r
+/** @brief  Macro to configure the SDMMC1 clock.\r
+  *\r
+  @if STM32L486xx\r
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
+  @endif\r
+  *\r
+  @if STM32L443xx\r
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
+  @endif\r
+  *\r
+  * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.\r
+  *         This parameter can be one of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" Clock selected as SDMMC1 clock\r
+  @endif\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" Clock selected as SDMMC1 clock\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" Clock selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLP  PLL "P" Clock selected as SDMMC1 clock\r
+  @endif\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" Clock selected as SDMMC1 clock\r
+  * @retval None\r
+  */\r
+#if defined(RCC_CCIPR2_SDMMCSEL)\r
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\r
+                  do \\r
+                  {  \\r
+                    if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \\r
+                    { \\r
+                      SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \\r
+                    } \\r
+                    else \\r
+                    { \\r
+                      CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \\r
+                      MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \\r
+                    } \\r
+                  } while(0)\r
+#else\r
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))\r
+#endif /* RCC_CCIPR2_SDMMCSEL */\r
+\r
+/** @brief  Macro to get the SDMMC1 clock.\r
+  * @retval The clock source can be one of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock\r
+  @endif\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLP  PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock\r
+  @endif\r
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock\r
+  */\r
+#if defined(RCC_CCIPR2_SDMMCSEL)\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE() \\r
+                  ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))\r
+#else\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE() \\r
+                  (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))\r
+#endif /* RCC_CCIPR2_SDMMCSEL */\r
+\r
+#endif /* SDMMC1 */\r
+\r
+/** @brief  Macro to configure the RNG clock.\r
+  *\r
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
+  *\r
+  * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.\r
+  *         This parameter can be one of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48\r
+  @endif\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48\r
+  @endif\r
+  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock\r
+  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as RNG clock\r
+  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the RNG clock.\r
+  * @retval The clock source can be one of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48\r
+  @endif\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48\r
+  @endif\r
+  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock\r
+  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock\r
+  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as RNG clock\r
+  */\r
+#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))\r
+\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+\r
+/** @brief  Macro to configure the USB clock (USBCLK).\r
+  *\r
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
+  *\r
+  * @param  __USB_CLKSOURCE__ specifies the USB clock source.\r
+  *         This parameter can be one of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48\r
+  @endif\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48\r
+  @endif\r
+  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock\r
+  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock\r
+  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the USB clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48\r
+  @endif\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48\r
+  @endif\r
+  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock\r
+  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock\r
+  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock\r
+  */\r
+#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))\r
+\r
+#endif /* USB_OTG_FS || USB */\r
+\r
+#if defined(RCC_CCIPR_ADCSEL)\r
+\r
+/** @brief  Macro to configure the ADC interface clock.\r
+  * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock\r
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices\r
+  @endif\r
+  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the ADC clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock\r
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices\r
+  @endif\r
+  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock\r
+  */\r
+#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))\r
+#else\r
+\r
+/** @brief  Macro to get the ADC clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock\r
+  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock\r
+  */\r
+#define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE)\r
+\r
+#endif /* RCC_CCIPR_ADCSEL */\r
+\r
+#if defined(SWPMI1)\r
+\r
+/** @brief  Macro to configure the SWPMI1 clock.\r
+  * @param  __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1  PCLK1 Clock selected as SWPMI1 clock\r
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the SWPMI1 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1  PCLK1 Clock selected as SWPMI1 clock\r
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock\r
+  */\r
+#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))\r
+\r
+#endif /* SWPMI1 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+/** @brief  Macro to configure the DFSDM1 clock.\r
+  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2  PCLK2 Clock selected as DFSDM1 clock\r
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock\r
+  * @retval None\r
+  */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))\r
+#else\r
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/** @brief  Macro to get the DFSDM1 clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2  PCLK2 Clock selected as DFSDM1 clock\r
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock\r
+  */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))\r
+#else\r
+#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+\r
+/** @brief  Macro to configure the DFSDM1 audio clock.\r
+  * @param  __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1  SAI1 clock selected as DFSDM1 audio clock\r
+  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI   HSI clock selected as DFSDM1 audio clock\r
+  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI   MSI clock selected as DFSDM1 audio clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the DFSDM1 audio clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1  SAI1 clock selected as DFSDM1 audio clock\r
+  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI   HSI clock selected as DFSDM1 audio clock\r
+  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI   MSI clock selected as DFSDM1 audio clock\r
+  */\r
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+\r
+/** @brief  Macro to configure the LTDC clock.\r
+  * @param  __LTDC_CLKSOURCE__ specifies the DSI clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2   PLLSAI2 divider R divided by 2 clock selected as LTDC clock\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4   PLLSAI2 divider R divided by 4 clock selected as LTDC clock\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8   PLLSAI2 divider R divided by 8 clock selected as LTDC clock\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16  PLLSAI2 divider R divided by 16 clock selected as LTDC clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the LTDC clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2   PLLSAI2 divider R divided by 2 clock selected as LTDC clock\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4   PLLSAI2 divider R divided by 4 clock selected as LTDC clock\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8   PLLSAI2 divider R divided by 8 clock selected as LTDC clock\r
+  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16  PLLSAI2 divider R divided by 16 clock selected as LTDC clock\r
+  */\r
+#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))\r
+\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+\r
+/** @brief  Macro to configure the DSI clock.\r
+  * @param  __DSI_CLKSOURCE__ specifies the DSI clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_DSICLKSOURCE_DSIPHY  DSI-PHY clock selected as DSI clock\r
+  *            @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the DSI clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_DSICLKSOURCE_DSIPHY  DSI-PHY clock selected as DSI clock\r
+  *            @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock\r
+  */\r
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))\r
+\r
+#endif /* DSI */\r
+\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+\r
+/** @brief  Macro to configure the OctoSPI clock.\r
+  * @param  __OSPI_CLKSOURCE__ specifies the OctoSPI clock source.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_OSPICLKSOURCE_SYSCLK  System Clock selected as OctoSPI clock\r
+  *            @arg @ref RCC_OSPICLKSOURCE_MSI     MSI clock selected as OctoSPI clock\r
+  *            @arg @ref RCC_OSPICLKSOURCE_PLL     PLL Q divider clock selected as OctoSPI clock\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \\r
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__))\r
+\r
+/** @brief  Macro to get the OctoSPI clock source.\r
+  * @retval The clock source can be one of the following values:\r
+  *            @arg @ref RCC_OSPICLKSOURCE_SYSCLK  System Clock selected as OctoSPI clock\r
+  *            @arg @ref RCC_OSPICLKSOURCE_MSI     MSI clock selected as OctoSPI clock\r
+  *            @arg @ref RCC_OSPICLKSOURCE_PLL     PLL Q divider clock selected as OctoSPI clock\r
+  */\r
+#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))\r
+\r
+#endif /* OCTOSPI1 || OCTOSPI2 */\r
+\r
+/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management\r
+  * @brief macros to manage the specified RCC Flags and interrupts.\r
+  * @{\r
+  */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+/** @brief Enable PLLSAI1RDY interrupt.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI1_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)\r
+\r
+/** @brief Disable PLLSAI1RDY interrupt.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)\r
+\r
+/** @brief Clear the PLLSAI1RDY interrupt pending bit.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI1_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)\r
+\r
+/** @brief Check whether PLLSAI1RDY interrupt has occurred or not.\r
+  * @retval TRUE or FALSE.\r
+  */\r
+#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)\r
+\r
+/** @brief  Check whether the PLLSAI1RDY flag is set or not.\r
+  * @retval TRUE or FALSE.\r
+  */\r
+#define __HAL_RCC_PLLSAI1_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+/** @brief Enable PLLSAI2RDY interrupt.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI2_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)\r
+\r
+/** @brief Disable PLLSAI2RDY interrupt.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)\r
+\r
+/** @brief Clear the PLLSAI2RDY interrupt pending bit.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_PLLSAI2_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)\r
+\r
+/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.\r
+  * @retval TRUE or FALSE.\r
+  */\r
+#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)\r
+\r
+/** @brief  Check whether the PLLSAI2RDY flag is set or not.\r
+  * @retval TRUE or FALSE.\r
+  */\r
+#define __HAL_RCC_PLLSAI2_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+\r
+/**\r
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+  * @brief Enable the RCC LSE CSS Event Line.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+  * @brief Disable the RCC LSE CSS Event Line.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+\r
+/**\r
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+\r
+/**\r
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+\r
+/**\r
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                      \\r
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \\r
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
+  do {                                                       \\r
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \\r
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.\r
+  * @retval EXTI RCC LSE CSS Line Status.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+  * @brief Clear the RCC LSE CSS EXTI flag.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)\r
+\r
+/**\r
+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.\r
+  * @retval None.\r
+  */\r
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)\r
+\r
+\r
+#if defined(CRS)\r
+\r
+/**\r
+  * @brief  Enable the specified CRS interrupts.\r
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.\r
+  *          This parameter can be any combination of the following values:\r
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))\r
+\r
+/**\r
+  * @brief  Disable the specified CRS interrupts.\r
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.\r
+  *          This parameter can be any combination of the following values:\r
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))\r
+\r
+/** @brief  Check whether the CRS interrupt has occurred or not.\r
+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.\r
+  *         This parameter can be one of the following values:\r
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
+  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+  */\r
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)\r
+\r
+/** @brief  Clear the CRS interrupt pending bits\r
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+  *         This parameter can be any combination of the following values:\r
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt\r
+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt\r
+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt\r
+  */\r
+/* CRS IT Error Mask */\r
+#define  RCC_CRS_IT_ERROR_MASK                 (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)\r
+\r
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \\r
+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \\r
+                                                 { \\r
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \\r
+                                                 } \\r
+                                                 else \\r
+                                                 { \\r
+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \\r
+                                                 } \\r
+                                               } while(0)\r
+\r
+/**\r
+  * @brief  Check whether the specified CRS flag is set or not.\r
+  * @param  __FLAG__ specifies the flag to check.\r
+  *          This parameter can be one of the following values:\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning\r
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error\r
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC\r
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed\r
+  * @retval The new state of _FLAG_ (TRUE or FALSE).\r
+  */\r
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+  * @brief  Clear the CRS specified FLAG.\r
+  * @param __FLAG__ specifies the flag to clear.\r
+  *          This parameter can be one of the following values:\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning\r
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error\r
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC\r
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error\r
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed\r
+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR\r
+  * @retval None\r
+  */\r
+\r
+/* CRS Flag Error Mask */\r
+#define RCC_CRS_FLAG_ERROR_MASK                (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)\r
+\r
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \\r
+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \\r
+                                                 { \\r
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \\r
+                                                 } \\r
+                                                 else \\r
+                                                 { \\r
+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \\r
+                                                 } \\r
+                                               } while(0)\r
+\r
+#endif /* CRS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(CRS)\r
+\r
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Enable the oscillator clock for frequency error counter.\r
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)\r
+\r
+/**\r
+  * @brief  Disable the oscillator clock for frequency error counter.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)\r
+\r
+/**\r
+  * @brief  Enable the automatic hardware adjustement of TRIM bits.\r
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)\r
+\r
+/**\r
+  * @brief  Enable or disable the automatic hardware adjustement of TRIM bits.\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)\r
+\r
+/**\r
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies\r
+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency\r
+  *             of the synchronization source after prescaling. It is then decreased by one in order to\r
+  *             reach the expected synchronization on the zero value. The formula is the following:\r
+  *             RELOAD = (fTARGET / fSYNC) -1\r
+  * @param  __FTARGET__ Target frequency (value in Hz)\r
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)\r
+  * @retval None\r
+  */\r
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* CRS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup RCCEx_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r
+void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r
+uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup RCCEx_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init);\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init);\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);\r
+void              HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);\r
+void              HAL_RCCEx_EnableLSECSS(void);\r
+void              HAL_RCCEx_DisableLSECSS(void);\r
+void              HAL_RCCEx_EnableLSECSS_IT(void);\r
+void              HAL_RCCEx_LSECSS_IRQHandler(void);\r
+void              HAL_RCCEx_LSECSS_Callback(void);\r
+void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);\r
+void              HAL_RCCEx_DisableLSCO(void);\r
+void              HAL_RCCEx_EnableMSIPLLMode(void);\r
+void              HAL_RCCEx_DisableMSIPLLMode(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(CRS)\r
+\r
+/** @addtogroup RCCEx_Exported_Functions_Group3\r
+  * @{\r
+  */\r
+\r
+void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);\r
+void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);\r
+void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);\r
+uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);\r
+void              HAL_RCCEx_CRS_IRQHandler(void);\r
+void              HAL_RCCEx_CRS_SyncOkCallback(void);\r
+void              HAL_RCCEx_CRS_SyncWarnCallback(void);\r
+void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);\r
+void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* CRS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Private_Macros\r
+  * @{\r
+  */\r
+\r
+#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \\r
+                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))\r
+\r
+#if defined(STM32L412xx) || defined(STM32L422xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG))\r
+\r
+#elif defined(STM32L431xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
+\r
+#elif defined(STM32L432xx) || defined(STM32L442xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG))\r
+\r
+#elif defined(STM32L433xx) || defined(STM32L443xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
+\r
+#elif defined(STM32L451xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
+\r
+#elif defined(STM32L452xx) || defined(STM32L462xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
+\r
+#elif defined(STM32L471xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
+\r
+#elif defined(STM32L496xx) || defined(STM32L4A6xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
+\r
+#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)      == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)         == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)      == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_OSPI)        == RCC_PERIPHCLK_OSPI))\r
+\r
+#elif defined(STM32L4R7xx) || defined(STM32L4S7xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)      == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)         == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)      == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_OSPI)        == RCC_PERIPHCLK_OSPI) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC))\r
+\r
+#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)      == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)         == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)      == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_OSPI)        == RCC_PERIPHCLK_OSPI)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DSI)         == RCC_PERIPHCLK_DSI))\r
+\r
+#else\r
+\r
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
+\r
+#endif /* STM32L412xx || STM32L422xx */\r
+\r
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \\r
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \\r
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \\r
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \\r
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \\r
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \\r
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))\r
+\r
+#if defined(USART3)\r
+\r
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \\r
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \\r
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \\r
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))\r
+\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+\r
+#define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \\r
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \\r
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \\r
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))\r
+\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+\r
+#define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \\r
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \\r
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \\r
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))\r
+\r
+#endif /* UART5 */\r
+\r
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \\r
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \\r
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \\r
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \\r
+                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \\r
+                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))\r
+\r
+#if defined(I2C2)\r
+\r
+#define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \\r
+                ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \\r
+                ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))\r
+\r
+#endif /* I2C2 */\r
+\r
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \\r
+                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \\r
+                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))\r
+\r
+#if defined(I2C4)\r
+\r
+#define IS_RCC_I2C4CLKSOURCE(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \\r
+                ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \\r
+                ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))\r
+\r
+#endif /* I2C4 */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_RCC_SAI1CLK(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)     || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))\r
+#else\r
+#define IS_RCC_SAI1CLK(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#elif defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+#define IS_RCC_SAI1CLK(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_RCC_SAI2CLK(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \\r
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)     || \\r
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))\r
+#else\r
+#define IS_RCC_SAI2CLK(__SOURCE__)   \\r
+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \\r
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+#define IS_RCC_LPTIM1CLK(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \\r
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)   || \\r
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)   || \\r
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))\r
+\r
+#define IS_RCC_LPTIM2CLK(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \\r
+                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)   || \\r
+                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)   || \\r
+                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))\r
+\r
+#if defined(SDMMC1)\r
+#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL)\r
+\r
+#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP)    || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48)   || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))\r
+\r
+#elif defined(RCC_HSI48_SUPPORT)\r
+\r
+#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48)   || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))\r
+#else\r
+\r
+#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE)    || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))\r
+\r
+#endif /* RCC_HSI48_SUPPORT */\r
+#endif /* SDMMC1 */\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))\r
+#else\r
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#else\r
+\r
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)    || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))\r
+\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+#if defined(RCC_HSI48_SUPPORT)\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))\r
+#else\r
+#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#else\r
+\r
+#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_USBCLKSOURCE_NONE)    || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \\r
+                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))\r
+\r
+#endif /* RCC_HSI48_SUPPORT */\r
+#endif /* USB_OTG_FS || USB */\r
+\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+\r
+#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \\r
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \\r
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))\r
+\r
+#else\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \\r
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \\r
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))\r
+#else\r
+#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \\r
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
+\r
+#if defined(SWPMI1)\r
+\r
+#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \\r
+                ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))\r
+\r
+#endif /* SWPMI1 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+\r
+#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \\r
+                ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+\r
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \\r
+                ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \\r
+                ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI))\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+\r
+#define IS_RCC_LTDCCLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \\r
+                ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \\r
+                ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \\r
+                ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16))\r
+\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+\r
+#define IS_RCC_DSICLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \\r
+                ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2))\r
+\r
+#endif /* DSI */\r
+\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+\r
+#define IS_RCC_OSPICLKSOURCE(__SOURCE__)  \\r
+               (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \\r
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \\r
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL))\r
+\r
+#endif /* OCTOSPI1 || OCTOSPI2 */\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+#define IS_RCC_PLLSAI1SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)\r
+\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+#define IS_RCC_PLLSAI1M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))\r
+#else\r
+#define IS_RCC_PLLSAI1M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+\r
+#define IS_RCC_PLLSAI1N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))\r
+\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+#define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))\r
+#else\r
+#define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))\r
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
+\r
+#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
+                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
+\r
+#define IS_RCC_PLLSAI1R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
+                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+#define IS_RCC_PLLSAI2SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)\r
+\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+#define IS_RCC_PLLSAI2M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))\r
+#else\r
+#define IS_RCC_PLLSAI2M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
+\r
+#define IS_RCC_PLLSAI2N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))\r
+\r
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
+#define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))\r
+#else\r
+#define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))\r
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
+                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
+\r
+#define IS_RCC_PLLSAI2R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
+                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+#if defined(CRS)\r
+\r
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \\r
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \\r
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))\r
+\r
+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \\r
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \\r
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \\r
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))\r
+\r
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \\r
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))\r
+\r
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))\r
+\r
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))\r
+\r
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))\r
+\r
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \\r
+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))\r
+\r
+#endif /* CRS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L4xx_HAL_RCC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h
new file mode 100644 (file)
index 0000000..cd35f17
--- /dev/null
@@ -0,0 +1,846 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_spi.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of SPI HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_SPI_H\r
+#define STM32L4xx_HAL_SPI_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup SPI\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Types SPI Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  SPI Configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Mode;                /*!< Specifies the SPI operating mode.\r
+                                     This parameter can be a value of @ref SPI_Mode */\r
+\r
+  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.\r
+                                     This parameter can be a value of @ref SPI_Direction */\r
+\r
+  uint32_t DataSize;            /*!< Specifies the SPI data size.\r
+                                     This parameter can be a value of @ref SPI_Data_Size */\r
+\r
+  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.\r
+                                     This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.\r
+                                     This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by\r
+                                     hardware (NSS pin) or by software using the SSI bit.\r
+                                     This parameter can be a value of @ref SPI_Slave_Select_management */\r
+\r
+  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be\r
+                                     used to configure the transmit and receive SCK clock.\r
+                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
+                                     @note The communication clock is derived from the master\r
+                                     clock. The slave clock does not need to be set. */\r
+\r
+  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.\r
+                                     This parameter can be a value of @ref SPI_TI_mode */\r
+\r
+  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.\r
+                                     This parameter can be a value of @ref SPI_CRC_Calculation */\r
+\r
+  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.\r
+                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */\r
+\r
+  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.\r
+                                     CRC Length is only used with Data8 and Data16, not other data size\r
+                                     This parameter can be a value of @ref SPI_CRC_length */\r
+\r
+  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .\r
+                                     This parameter can be a value of @ref SPI_NSSP_Mode\r
+                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and\r
+                                     it takes effect only if the SPI interface is configured as Motorola SPI\r
+                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,\r
+                                     CPOL setting is ignored).. */\r
+} SPI_InitTypeDef;\r
+\r
+/**\r
+  * @brief  HAL SPI State structure definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */\r
+  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */\r
+  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */\r
+  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */\r
+  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */\r
+  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */\r
+  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */\r
+  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */\r
+} HAL_SPI_StateTypeDef;\r
+\r
+/**\r
+  * @brief  SPI handle Structure definition\r
+  */\r
+typedef struct __SPI_HandleTypeDef\r
+{\r
+  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */\r
+\r
+  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */\r
+\r
+  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */\r
+\r
+  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */\r
+\r
+  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */\r
+\r
+  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */\r
+\r
+  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */\r
+\r
+  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */\r
+\r
+  uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */\r
+\r
+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */\r
+\r
+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */\r
+\r
+  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */\r
+\r
+  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */\r
+\r
+  HAL_LockTypeDef            Lock;           /*!< Locking object                           */\r
+\r
+  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */\r
+\r
+  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */\r
+\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */\r
+  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */\r
+  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */\r
+  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */\r
+  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */\r
+  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */\r
+  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */\r
+  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */\r
+  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */\r
+  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */\r
+\r
+#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+} SPI_HandleTypeDef;\r
+\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+/**\r
+  * @brief  HAL SPI Callback ID enumeration definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */\r
+  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */\r
+  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */\r
+  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */\r
+  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */\r
+  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */\r
+  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */\r
+  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */\r
+  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */\r
+  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */\r
+\r
+} HAL_SPI_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  HAL SPI Callback pointer definition\r
+  */\r
+typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */\r
+\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Constants SPI Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SPI_Error_Code SPI Error Code\r
+  * @{\r
+  */\r
+#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */\r
+#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */\r
+#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */\r
+#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */\r
+#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */\r
+#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */\r
+#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */\r
+#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Mode SPI Mode\r
+  * @{\r
+  */\r
+#define SPI_MODE_SLAVE                  (0x00000000U)\r
+#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Direction SPI Direction Mode\r
+  * @{\r
+  */\r
+#define SPI_DIRECTION_2LINES            (0x00000000U)\r
+#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY\r
+#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Data_Size SPI Data Size\r
+  * @{\r
+  */\r
+#define SPI_DATASIZE_4BIT               (0x00000300U)\r
+#define SPI_DATASIZE_5BIT               (0x00000400U)\r
+#define SPI_DATASIZE_6BIT               (0x00000500U)\r
+#define SPI_DATASIZE_7BIT               (0x00000600U)\r
+#define SPI_DATASIZE_8BIT               (0x00000700U)\r
+#define SPI_DATASIZE_9BIT               (0x00000800U)\r
+#define SPI_DATASIZE_10BIT              (0x00000900U)\r
+#define SPI_DATASIZE_11BIT              (0x00000A00U)\r
+#define SPI_DATASIZE_12BIT              (0x00000B00U)\r
+#define SPI_DATASIZE_13BIT              (0x00000C00U)\r
+#define SPI_DATASIZE_14BIT              (0x00000D00U)\r
+#define SPI_DATASIZE_15BIT              (0x00000E00U)\r
+#define SPI_DATASIZE_16BIT              (0x00000F00U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\r
+  * @{\r
+  */\r
+#define SPI_POLARITY_LOW                (0x00000000U)\r
+#define SPI_POLARITY_HIGH               SPI_CR1_CPOL\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Clock_Phase SPI Clock Phase\r
+  * @{\r
+  */\r
+#define SPI_PHASE_1EDGE                 (0x00000000U)\r
+#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management\r
+  * @{\r
+  */\r
+#define SPI_NSS_SOFT                    SPI_CR1_SSM\r
+#define SPI_NSS_HARD_INPUT              (0x00000000U)\r
+#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode\r
+  * @{\r
+  */\r
+#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP\r
+#define SPI_NSS_PULSE_DISABLE           (0x00000000U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\r
+  * @{\r
+  */\r
+#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)\r
+#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)\r
+#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)\r
+#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)\r
+#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)\r
+#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)\r
+#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)\r
+#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission\r
+  * @{\r
+  */\r
+#define SPI_FIRSTBIT_MSB                (0x00000000U)\r
+#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_TI_mode SPI TI Mode\r
+  * @{\r
+  */\r
+#define SPI_TIMODE_DISABLE              (0x00000000U)\r
+#define SPI_TIMODE_ENABLE               SPI_CR2_FRF\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\r
+  * @{\r
+  */\r
+#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)\r
+#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_CRC_length SPI CRC Length\r
+  * @{\r
+  * This parameter can be one of the following values:\r
+  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size\r
+  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit\r
+  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit\r
+  */\r
+#define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)\r
+#define SPI_CRC_LENGTH_8BIT             (0x00000001U)\r
+#define SPI_CRC_LENGTH_16BIT            (0x00000002U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold\r
+  * @{\r
+  * This parameter can be one of the following values:\r
+  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :\r
+  *          RXNE event is generated if the FIFO\r
+  *          level is greater or equal to 1/4(8-bits).\r
+  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO\r
+  *          level is greater or equal to 1/2(16 bits). */\r
+#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH\r
+#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH\r
+#define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition\r
+  * @{\r
+  */\r
+#define SPI_IT_TXE                      SPI_CR2_TXEIE\r
+#define SPI_IT_RXNE                     SPI_CR2_RXNEIE\r
+#define SPI_IT_ERR                      SPI_CR2_ERRIE\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Flags_definition SPI Flags Definition\r
+  * @{\r
+  */\r
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */\r
+#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */\r
+#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */\r
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */\r
+#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */\r
+#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */\r
+#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */\r
+#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */\r
+#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */\r
+#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level\r
+  * @{\r
+  */\r
+#define SPI_FTLVL_EMPTY                 (0x00000000U)\r
+#define SPI_FTLVL_QUARTER_FULL          (0x00000800U)\r
+#define SPI_FTLVL_HALF_FULL             (0x00001000U)\r
+#define SPI_FTLVL_FULL                  (0x00001800U)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level\r
+  * @{\r
+  */\r
+#define SPI_FRLVL_EMPTY                 (0x00000000U)\r
+#define SPI_FRLVL_QUARTER_FULL          (0x00000200U)\r
+#define SPI_FRLVL_HALF_FULL             (0x00000400U)\r
+#define SPI_FRLVL_FULL                  (0x00000600U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Macros SPI Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Reset SPI handle state.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \\r
+                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \\r
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \\r
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \\r
+                                                                  } while(0)\r
+#else\r
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\r
+#endif\r
+\r
+/** @brief  Enable the specified SPI interrupts.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+  *            @arg SPI_IT_ERR: Error interrupt enable\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))\r
+\r
+/** @brief  Disable the specified SPI interrupts.\r
+  * @param  __HANDLE__ specifies the SPI handle.\r
+  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+  *            @arg SPI_IT_ERR: Error interrupt enable\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))\r
+\r
+/** @brief  Check whether the specified SPI interrupt source is enabled or not.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+  *            @arg SPI_IT_ERR: Error interrupt enable\r
+  * @retval The new state of __IT__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief  Check whether the specified SPI flag is set or not.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @param  __FLAG__ specifies the flag to check.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\r
+  *            @arg SPI_FLAG_CRCERR: CRC error flag\r
+  *            @arg SPI_FLAG_MODF: Mode fault flag\r
+  *            @arg SPI_FLAG_OVR: Overrun flag\r
+  *            @arg SPI_FLAG_BSY: Busy flag\r
+  *            @arg SPI_FLAG_FRE: Frame format error flag\r
+  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r
+  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level\r
+  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief  Clear the SPI CRCERR pending flag.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\r
+\r
+/** @brief  Clear the SPI MODF pending flag.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \\r
+  do{                                                    \\r
+    __IO uint32_t tmpreg_modf = 0x00U;                   \\r
+    tmpreg_modf = (__HANDLE__)->Instance->SR;            \\r
+    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \\r
+    UNUSED(tmpreg_modf);                                 \\r
+  } while(0U)\r
+\r
+/** @brief  Clear the SPI OVR pending flag.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \\r
+  do{                                              \\r
+    __IO uint32_t tmpreg_ovr = 0x00U;              \\r
+    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \\r
+    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \\r
+    UNUSED(tmpreg_ovr);                            \\r
+  } while(0U)\r
+\r
+/** @brief  Clear the SPI FRE pending flag.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \\r
+  do{                                              \\r
+  __IO uint32_t tmpreg_fre = 0x00U;                \\r
+  tmpreg_fre = (__HANDLE__)->Instance->SR;         \\r
+  UNUSED(tmpreg_fre);                              \\r
+  }while(0U)\r
+\r
+/** @brief  Enable the SPI peripheral.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)\r
+\r
+/** @brief  Disable the SPI peripheral.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup SPI_Private_Macros SPI Private Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Set the SPI transmit-only mode.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)\r
+\r
+/** @brief  Set the SPI receive-only mode.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)\r
+\r
+/** @brief  Reset the CRC calculation of the SPI.\r
+  * @param  __HANDLE__ specifies the SPI Handle.\r
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\\r
+                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)\r
+\r
+/** @brief  Check whether the specified SPI flag is set or not.\r
+  * @param  __SR__  copy of SPI SR regsiter.\r
+  * @param  __FLAG__ specifies the flag to check.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\r
+  *            @arg SPI_FLAG_CRCERR: CRC error flag\r
+  *            @arg SPI_FLAG_MODF: Mode fault flag\r
+  *            @arg SPI_FLAG_OVR: Overrun flag\r
+  *            @arg SPI_FLAG_BSY: Busy flag\r
+  *            @arg SPI_FLAG_FRE: Frame format error flag\r
+  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r
+  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level\r
+  * @retval SET or RESET.\r
+  */\r
+#define SPI_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)\r
+\r
+/** @brief  Check whether the specified SPI Interrupt is set or not.\r
+  * @param  __CR2__  copy of SPI CR2 regsiter.\r
+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+  *            @arg SPI_IT_ERR: Error interrupt enable\r
+  * @retval SET or RESET.\r
+  */\r
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief  Checks if SPI Mode parameter is in allowed range.\r
+  * @param  __MODE__ specifies the SPI Mode.\r
+  *         This parameter can be a value of @ref SPI_Mode\r
+  * @retval None\r
+  */\r
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \\r
+                               ((__MODE__) == SPI_MODE_MASTER))\r
+\r
+/** @brief  Checks if SPI Direction Mode parameter is in allowed range.\r
+  * @param  __MODE__ specifies the SPI Direction Mode.\r
+  *         This parameter can be a value of @ref SPI_Direction\r
+  * @retval None\r
+  */\r
+#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \\r
+                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \\r
+                                    ((__MODE__) == SPI_DIRECTION_1LINE))\r
+\r
+/** @brief  Checks if SPI Direction Mode parameter is 2 lines.\r
+  * @param  __MODE__ specifies the SPI Direction Mode.\r
+  * @retval None\r
+  */\r
+#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)\r
+\r
+/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.\r
+  * @param  __MODE__ specifies the SPI Direction Mode.\r
+  * @retval None\r
+  */\r
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \\r
+                                                    ((__MODE__) == SPI_DIRECTION_1LINE))\r
+\r
+/** @brief  Checks if SPI Data Size parameter is in allowed range.\r
+  * @param  __DATASIZE__ specifies the SPI Data Size.\r
+  *         This parameter can be a value of @ref SPI_Data_Size\r
+  * @retval None\r
+  */\r
+#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \\r
+                                       ((__DATASIZE__) == SPI_DATASIZE_4BIT))\r
+\r
+/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.\r
+  * @param  __CPOL__ specifies the SPI serial clock steady state.\r
+  *         This parameter can be a value of @ref SPI_Clock_Polarity\r
+  * @retval None\r
+  */\r
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \\r
+                               ((__CPOL__) == SPI_POLARITY_HIGH))\r
+\r
+/** @brief  Checks if SPI Clock Phase parameter is in allowed range.\r
+  * @param  __CPHA__ specifies the SPI Clock Phase.\r
+  *         This parameter can be a value of @ref SPI_Clock_Phase\r
+  * @retval None\r
+  */\r
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \\r
+                               ((__CPHA__) == SPI_PHASE_2EDGE))\r
+\r
+/** @brief  Checks if SPI Slave Select parameter is in allowed range.\r
+  * @param  __NSS__ specifies the SPI Slave Select management parameter.\r
+  *         This parameter can be a value of @ref SPI_Slave_Select_management\r
+  * @retval None\r
+  */\r
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT)       || \\r
+                             ((__NSS__) == SPI_NSS_HARD_INPUT) || \\r
+                             ((__NSS__) == SPI_NSS_HARD_OUTPUT))\r
+\r
+/** @brief  Checks if SPI NSS Pulse parameter is in allowed range.\r
+  * @param  __NSSP__ specifies the SPI NSS Pulse Mode parameter.\r
+  *         This parameter can be a value of @ref SPI_NSSP_Mode\r
+  * @retval None\r
+  */\r
+#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \\r
+                               ((__NSSP__) == SPI_NSS_PULSE_DISABLE))\r
+\r
+/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.\r
+  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.\r
+  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
+  * @retval None\r
+  */\r
+#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \\r
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \\r
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \\r
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \\r
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \\r
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \\r
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \\r
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))\r
+\r
+/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.\r
+  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).\r
+  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission\r
+  * @retval None\r
+  */\r
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \\r
+                                   ((__BIT__) == SPI_FIRSTBIT_LSB))\r
+\r
+/** @brief  Checks if SPI TI mode parameter is in allowed range.\r
+  * @param  __MODE__ specifies the SPI TI mode.\r
+  *         This parameter can be a value of @ref SPI_TI_mode\r
+  * @retval None\r
+  */\r
+#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \\r
+                                 ((__MODE__) == SPI_TIMODE_ENABLE))\r
+\r
+/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.\r
+  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.\r
+  *         This parameter can be a value of @ref SPI_CRC_Calculation\r
+  * @retval None\r
+  */\r
+#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \\r
+                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))\r
+\r
+/** @brief  Checks if SPI CRC length is in allowed range.\r
+  * @param  __LENGTH__ specifies the SPI CRC length.\r
+  *         This parameter can be a value of @ref SPI_CRC_length\r
+  * @retval None\r
+  */\r
+#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\\r
+                                       ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)  ||   \\r
+                                       ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))\r
+\r
+/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.\r
+  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.\r
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535\r
+  * @retval None\r
+  */\r
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))\r
+\r
+/** @brief  Checks if DMA handle is valid.\r
+  * @param  __HANDLE__ specifies a DMA Handle.\r
+  * @retval None\r
+  */\r
+#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include SPI HAL Extended module */\r
+#include "stm32l4xx_hal_spi_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SPI_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+/* Initialization/de-initialization functions  ********************************/\r
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\r
+\r
+/* Callbacks Register/UnRegister functions  ***********************************/\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+/* I/O operation functions  ***************************************************/\r
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\r
+                                          uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r
+                                             uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r
+                                              uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\r
+/* Transfer Abort functions */\r
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);\r
+\r
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group3\r
+  * @{\r
+  */\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\r
+uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_SPI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h
new file mode 100644 (file)
index 0000000..c7f6edb
--- /dev/null
@@ -0,0 +1,75 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_spi_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of SPI HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_SPI_EX_H\r
+#define STM32L4xx_HAL_SPI_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup SPIEx\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SPIEx_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/* Initialization and de-initialization functions  ****************************/\r
+/* IO operation functions *****************************************************/\r
+/** @addtogroup SPIEx_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_SPI_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
new file mode 100644 (file)
index 0000000..42cb4ea
--- /dev/null
@@ -0,0 +1,2141 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_tim.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of TIM HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_TIM_H\r
+#define STM32L4xx_HAL_TIM_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup TIM\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Types TIM Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  TIM Time base Configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.\r
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+  uint32_t CounterMode;       /*!< Specifies the counter mode.\r
+                                   This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active\r
+                                   Auto-Reload Register at the next update event.\r
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */\r
+\r
+  uint32_t ClockDivision;     /*!< Specifies the clock division.\r
+                                   This parameter can be a value of @ref TIM_ClockDivision */\r
+\r
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+                                    reaches zero, an update event is generated and counting restarts\r
+                                    from the RCR value (N).\r
+                                    This means in PWM mode that (N+1) corresponds to:\r
+                                        - the number of PWM periods in edge-aligned mode\r
+                                        - the number of half PWM period in center-aligned mode\r
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.\r
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.\r
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */\r
+} TIM_Base_InitTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Output Compare Configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t OCMode;        /*!< Specifies the TIM mode.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+                               @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.\r
+                               This parameter can be a value of @ref TIM_Output_Fast_State\r
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */\r
+\r
+\r
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+                               @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+                               @note This parameter is valid only for timer instances supporting break feature. */\r
+} TIM_OC_InitTypeDef;\r
+\r
+/**\r
+  * @brief  TIM One Pulse Mode Configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t OCMode;        /*!< Specifies the TIM mode.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+                               @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+                               @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+                               @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.\r
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+  uint32_t ICSelection;   /*!< Specifies the input.\r
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.\r
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_OnePulse_InitTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Input Capture Configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.\r
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+  uint32_t ICSelection;  /*!< Specifies the input.\r
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.\r
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.\r
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_IC_InitTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Encoder Configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.\r
+                               This parameter can be a value of @ref TIM_Encoder_Mode */\r
+\r
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.\r
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+  uint32_t IC1Selection;  /*!< Specifies the input.\r
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.\r
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.\r
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.\r
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+  uint32_t IC2Selection;  /*!< Specifies the input.\r
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.\r
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.\r
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_Encoder_InitTypeDef;\r
+\r
+/**\r
+  * @brief  Clock Configuration Handle Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t ClockSource;     /*!< TIM clock sources\r
+                                 This parameter can be a value of @ref TIM_Clock_Source */\r
+  uint32_t ClockPolarity;   /*!< TIM clock polarity\r
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */\r
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler\r
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */\r
+  uint32_t ClockFilter;     /*!< TIM clock filter\r
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClockConfigTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Clear Input Configuration Handle Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t ClearInputState;      /*!< TIM clear Input state\r
+                                      This parameter can be ENABLE or DISABLE */\r
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources\r
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */\r
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity\r
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */\r
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler\r
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter\r
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClearInputConfigTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Master configuration Structure definition\r
+  * @note   Advanced timers provide TRGO2 internal line which is redirected\r
+  *         to the ADC\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection\r
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */\r
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection\r
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */\r
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection\r
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
+} TIM_MasterConfigTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Slave configuration Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t  SlaveMode;         /*!< Slave mode selection\r
+                                    This parameter can be a value of @ref TIM_Slave_Mode */\r
+  uint32_t  InputTrigger;      /*!< Input Trigger source\r
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */\r
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity\r
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */\r
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler\r
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */\r
+  uint32_t  TriggerFilter;     /*!< Input trigger filter\r
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */\r
+\r
+} TIM_SlaveConfigTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition\r
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable\r
+  *        filter and polarity.\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode\r
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode\r
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
+  uint32_t LockLevel;            /*!< TIM Lock level\r
+                                      This parameter can be a value of @ref TIM_Lock_level */\r
+  uint32_t DeadTime;             /*!< TIM dead Time\r
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
+  uint32_t BreakState;           /*!< TIM Break State\r
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity\r
+                                      This parameter can be a value of @ref TIM_Break_Polarity */\r
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.\r
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+  uint32_t Break2State;          /*!< TIM Break2 State\r
+                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */\r
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity\r
+                                      This parameter can be a value of @ref TIM_Break2_Polarity */\r
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.\r
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state\r
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BreakDeadTimeConfigTypeDef;\r
+\r
+/**\r
+  * @brief  HAL State structures definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */\r
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */\r
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */\r
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */\r
+} HAL_TIM_StateTypeDef;\r
+\r
+/**\r
+  * @brief  HAL Active channel structures definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */\r
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */\r
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */\r
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */\r
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */\r
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */\r
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */\r
+} HAL_TIM_ActiveChannel;\r
+\r
+/**\r
+  * @brief  TIM Time Base Handle Structure definition\r
+  */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+typedef struct __TIM_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+{\r
+  TIM_TypeDef                 *Instance;     /*!< Register base address             */\r
+  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */\r
+  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */\r
+  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array\r
+                                                  This array is accessed by a @ref DMA_Handle_index */\r
+  HAL_LockTypeDef             Lock;          /*!< Locking object                    */\r
+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */\r
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */\r
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */\r
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */\r
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */\r
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */\r
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */\r
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */\r
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */\r
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */\r
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */\r
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */\r
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */\r
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */\r
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */\r
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */\r
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */\r
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */\r
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */\r
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */\r
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */\r
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */\r
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */\r
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */\r
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */\r
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */\r
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */\r
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+} TIM_HandleTypeDef;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  HAL TIM Callback ID enumeration definition\r
+  */\r
+typedef enum\r
+{\r
+   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */\r
+  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */\r
+  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */\r
+  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */\r
+  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */\r
+  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */\r
+  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */\r
+  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */\r
+  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */\r
+  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */\r
+  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */\r
+  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */\r
+  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */\r
+  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */\r
+  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */\r
+  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */\r
+  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */\r
+  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */\r
+\r
+  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */\r
+  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */\r
+  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */\r
+  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */\r
+  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */\r
+  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */\r
+  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */\r
+  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */\r
+  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */\r
+  ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */\r
+} HAL_TIM_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  HAL TIM Callback pointer definition\r
+  */\r
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */\r
+\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Constants TIM Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source\r
+  * @{\r
+  */\r
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */\r
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */\r
+#define TIM_CLEARINPUTSOURCE_OCREFCLR       0x00000002U   /*!< OCREF_CLR is connected to OCREF_CLR_INT */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address\r
+  * @{\r
+  */\r
+#define TIM_DMABASE_CR1                    0x00000000U\r
+#define TIM_DMABASE_CR2                    0x00000001U\r
+#define TIM_DMABASE_SMCR                   0x00000002U\r
+#define TIM_DMABASE_DIER                   0x00000003U\r
+#define TIM_DMABASE_SR                     0x00000004U\r
+#define TIM_DMABASE_EGR                    0x00000005U\r
+#define TIM_DMABASE_CCMR1                  0x00000006U\r
+#define TIM_DMABASE_CCMR2                  0x00000007U\r
+#define TIM_DMABASE_CCER                   0x00000008U\r
+#define TIM_DMABASE_CNT                    0x00000009U\r
+#define TIM_DMABASE_PSC                    0x0000000AU\r
+#define TIM_DMABASE_ARR                    0x0000000BU\r
+#define TIM_DMABASE_RCR                    0x0000000CU\r
+#define TIM_DMABASE_CCR1                   0x0000000DU\r
+#define TIM_DMABASE_CCR2                   0x0000000EU\r
+#define TIM_DMABASE_CCR3                   0x0000000FU\r
+#define TIM_DMABASE_CCR4                   0x00000010U\r
+#define TIM_DMABASE_BDTR                   0x00000011U\r
+#define TIM_DMABASE_DCR                    0x00000012U\r
+#define TIM_DMABASE_DMAR                   0x00000013U\r
+#define TIM_DMABASE_OR1                    0x00000014U\r
+#define TIM_DMABASE_CCMR3                  0x00000015U\r
+#define TIM_DMABASE_CCR5                   0x00000016U\r
+#define TIM_DMABASE_CCR6                   0x00000017U\r
+#define TIM_DMABASE_OR2                    0x00000018U\r
+#define TIM_DMABASE_OR3                    0x00000019U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Event_Source TIM Event Source\r
+  * @{\r
+  */\r
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */\r
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */\r
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */\r
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */\r
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */\r
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */\r
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */\r
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */\r
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity\r
+  * @{\r
+  */\r
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */\r
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */\r
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\r
+  * @{\r
+  */\r
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */\r
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\r
+  * @{\r
+  */\r
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */\r
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */\r
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */\r
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Counter_Mode TIM Counter Mode\r
+  * @{\r
+  */\r
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */\r
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */\r
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */\r
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */\r
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_ClockDivision TIM Clock Division\r
+  * @{\r
+  */\r
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */\r
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */\r
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r
+  * @{\r
+  */\r
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */\r
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\r
+  * @{\r
+  */\r
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */\r
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State\r
+  * @{\r
+  */\r
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */\r
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r
+  * @{\r
+  */\r
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */\r
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity\r
+  * @{\r
+  */\r
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */\r
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r
+  * @{\r
+  */\r
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */\r
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State\r
+  * @{\r
+  */\r
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */\r
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State\r
+  * @{\r
+  */\r
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */\r
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity\r
+  * @{\r
+  */\r
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */\r
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */\r
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\r
+  * @{\r
+  */\r
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */\r
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\r
+  * @{\r
+  */\r
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */\r
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */\r
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */\r
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r
+  * @{\r
+  */\r
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */\r
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r
+  * @{\r
+  */\r
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */\r
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */\r
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition\r
+  * @{\r
+  */\r
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */\r
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */\r
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */\r
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */\r
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */\r
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */\r
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */\r
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source\r
+  * @{\r
+  */\r
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */\r
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_DMA_sources TIM DMA Sources\r
+  * @{\r
+  */\r
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */\r
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */\r
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */\r
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */\r
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */\r
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */\r
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Flag_definition TIM Flag Definition\r
+  * @{\r
+  */\r
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */\r
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */\r
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */\r
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */\r
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */\r
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */\r
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */\r
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */\r
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */\r
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */\r
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */\r
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */\r
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */\r
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */\r
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */\r
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Channel TIM Channel\r
+  * @{\r
+  */\r
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */\r
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */\r
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */\r
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */\r
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */\r
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */\r
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Clock_Source TIM Clock Source\r
+  * @{\r
+  */\r
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */\r
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */\r
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */\r
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */\r
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */\r
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */\r
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */\r
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */\r
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */\r
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\r
+  * @{\r
+  */\r
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\r
+  * @{\r
+  */\r
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */\r
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\r
+  * @{\r
+  */\r
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */\r
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r
+  * @{\r
+  */\r
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */\r
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\r
+  * @{\r
+  */\r
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */\r
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\r
+  * @{\r
+  */\r
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */\r
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
+/**\r
+  * @}\r
+  */\r
+/** @defgroup TIM_Lock_level  TIM Lock level\r
+  * @{\r
+  */\r
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */\r
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */\r
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */\r
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable\r
+  * @{\r
+  */\r
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */\r
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity\r
+  * @{\r
+  */\r
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */\r
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable\r
+  * @{\r
+  */\r
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */\r
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity\r
+  * @{\r
+  */\r
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */\r
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable\r
+  * @{\r
+  */\r
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */\r
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event \r
+                                                                                    (if none of the break inputs BRK and BRK2 is active) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3\r
+  * @{\r
+  */\r
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */\r
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */\r
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r
+  * @{\r
+  */\r
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */\r
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */\r
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */\r
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */\r
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */\r
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */\r
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)\r
+  * @{\r
+  */\r
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */\r
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */\r
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */\r
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */\r
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */\r
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */\r
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */\r
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */\r
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */\r
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */\r
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */\r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */\r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */\r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode\r
+  * @{\r
+  */\r
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */\r
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Slave_Mode TIM Slave mode\r
+  * @{\r
+  */\r
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */\r
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */\r
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */\r
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */\r
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */\r
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes\r
+  * @{\r
+  */\r
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */\r
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */\r
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */\r
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */\r
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */\r
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */\r
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */\r
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */\r
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */\r
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */\r
+#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */\r
+#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\r
+  * @{\r
+  */\r
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */\r
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */\r
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */\r
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */\r
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */\r
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */\r
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */\r
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */\r
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r
+  * @{\r
+  */\r
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */\r
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */\r
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r
+  * @{\r
+  */\r
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */\r
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection\r
+  * @{\r
+  */\r
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */\r
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length\r
+  * @{\r
+  */\r
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */\r
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Handle_index TIM DMA Handle Index\r
+  * @{\r
+  */\r
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */\r
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */\r
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State\r
+  * @{\r
+  */\r
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */\r
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */\r
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */\r
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Break_System TIM Break System\r
+  * @{\r
+  */\r
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */\r
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */\r
+#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR  SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */\r
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Macros TIM Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Reset TIM handle state.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @retval None\r
+  */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \\r
+                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \\r
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \\r
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \\r
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \\r
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \\r
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \\r
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \\r
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \\r
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \\r
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \\r
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \\r
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \\r
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \\r
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \\r
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \\r
+                                                     } while(0)\r
+#else\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @brief  Enable the TIM peripheral.\r
+  * @param  __HANDLE__ TIM handle\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r
+\r
+/**\r
+  * @brief  Enable the TIM main Output.\r
+  * @param  __HANDLE__ TIM handle\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r
+\r
+/**\r
+  * @brief  Disable the TIM peripheral.\r
+  * @param  __HANDLE__ TIM handle\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_DISABLE(__HANDLE__) \\r
+  do { \\r
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
+    { \\r
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
+      { \\r
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\r
+      } \\r
+    } \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Disable the TIM main Output.\r
+  * @param  __HANDLE__ TIM handle\r
+  * @retval None\r
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled\r
+  */\r
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\r
+  do { \\r
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
+    { \\r
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
+      { \\r
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\r
+      } \\r
+    } \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Disable the TIM main Output.\r
+  * @param  __HANDLE__ TIM handle\r
+  * @retval None\r
+  * @note The Main Output Enable of a timer instance is disabled unconditionally\r
+  */\r
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)\r
+\r
+/** @brief  Enable the specified TIM interrupt.\r
+  * @param  __HANDLE__ specifies the TIM Handle.\r
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_IT_UPDATE: Update interrupt\r
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
+  *            @arg TIM_IT_COM:   Commutation interrupt\r
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
+  *            @arg TIM_IT_BREAK: Break interrupt\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r
+\r
+/** @brief  Disable the specified TIM interrupt.\r
+  * @param  __HANDLE__ specifies the TIM Handle.\r
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_IT_UPDATE: Update interrupt\r
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
+  *            @arg TIM_IT_COM:   Commutation interrupt\r
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
+  *            @arg TIM_IT_BREAK: Break interrupt\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r
+\r
+/** @brief  Enable the specified DMA request.\r
+  * @param  __HANDLE__ specifies the TIM Handle.\r
+  * @param  __DMA__ specifies the TIM DMA request to enable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_DMA_UPDATE: Update DMA request\r
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\r
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\r
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\r
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\r
+  *            @arg TIM_DMA_COM:   Commutation DMA request\r
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))\r
+\r
+/** @brief  Disable the specified DMA request.\r
+  * @param  __HANDLE__ specifies the TIM Handle.\r
+  * @param  __DMA__ specifies the TIM DMA request to disable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_DMA_UPDATE: Update DMA request\r
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\r
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\r
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\r
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\r
+  *            @arg TIM_DMA_COM:   Commutation DMA request\r
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r
+\r
+/** @brief  Check whether the specified TIM interrupt flag is set or not.\r
+  * @param  __HANDLE__ specifies the TIM Handle.\r
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.\r
+  *        This parameter can be one of the following values:\r
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\r
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag\r
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief  Clear the specified TIM interrupt flag.\r
+  * @param  __HANDLE__ specifies the TIM Handle.\r
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.\r
+  *        This parameter can be one of the following values:\r
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\r
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag\r
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
+\r
+/**\r
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.\r
+  * @param  __HANDLE__ TIM handle\r
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_IT_UPDATE: Update interrupt\r
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
+  *            @arg TIM_IT_COM:   Commutation interrupt\r
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
+  *            @arg TIM_IT_BREAK: Break interrupt\r
+  * @retval The state of TIM_IT (SET or RESET).\r
+  */\r
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \\r
+                                                             == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Clear the TIM interrupt pending bits.\r
+  * @param  __HANDLE__ TIM handle\r
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_IT_UPDATE: Update interrupt\r
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
+  *            @arg TIM_IT_COM:   Commutation interrupt\r
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
+  *            @arg TIM_IT_BREAK: Break interrupt\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r
+\r
+/**\r
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\r
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder\r
+mode.\r
+  */\r
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r
+\r
+/**\r
+  * @brief  Set the TIM Prescaler on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __PRESC__ specifies the Prescaler new value.\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))\r
+\r
+/**\r
+  * @brief  Set the TIM Counter Register value on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __COUNTER__ specifies the Counter register new value.\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r
+\r
+/**\r
+  * @brief  Get the TIM Counter Register value on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)\r
+  */\r
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)\r
+\r
+/**\r
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __AUTORELOAD__ specifies the Counter register new value.\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\r
+  do{                                                    \\r
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \\r
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Get the TIM Autoreload Register value on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)\r
+  */\r
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)\r
+\r
+/**\r
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CKD__ specifies the clock division value.\r
+  *          This parameter can be one of the following value:\r
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\r
+  do{                                                   \\r
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \\r
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \\r
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Get the TIM Clock Division value on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @retval The clock division can be one of the following values:\r
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+  */\r
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r
+\r
+/**\r
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CHANNEL__ TIM Channels to be configured.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICPSC_DIV1: no prescaler\r
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+  do{                                                    \\r
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \\r
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\r
+  } while(0)\r
+\r
+/**\r
+  * @brief  Get the TIM Input Capture prescaler on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CHANNEL__ TIM Channels to be configured.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r
+  * @retval The input capture prescaler can be one of the following values:\r
+  *            @arg TIM_ICPSC_DIV1: no prescaler\r
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+  */\r
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\r
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)\r
+\r
+/**\r
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CHANNEL__ TIM Channels to be configured.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @param  __COMPARE__ specifies the Capture Compare register new value.\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\r
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))\r
+\r
+/**\r
+  * @brief  Get the TIM Capture Compare Register value on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value\r
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value\r
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)\r
+  */\r
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\r
+   ((__HANDLE__)->Instance->CCR6))\r
+\r
+/**\r
+  * @brief  Set the TIM Output compare preload.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CHANNEL__ TIM Channels to be configured.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\\r
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))\r
+\r
+/**\r
+  * @brief  Reset the TIM Output compare preload.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CHANNEL__ TIM Channels to be configured.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\\r
+   ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))\r
+\r
+/**\r
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter\r
+  *        overflow/underflow generates an update interrupt or DMA request (if\r
+  *        enabled)\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)\r
+\r
+/**\r
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the\r
+  *        following events generate an update interrupt or DMA request (if\r
+  *        enabled):\r
+  *           _ Counter overflow underflow\r
+  *           _ Setting the UG bit\r
+  *           _ Update generation through the slave mode controller\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)\r
+\r
+/**\r
+  * @brief  Set the TIM Capture x input polarity on runtime.\r
+  * @param  __HANDLE__ TIM handle.\r
+  * @param  __CHANNEL__ TIM Channels to be configured.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @param  __POLARITY__ Polarity for TIx source\r
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r
+  * @retval None\r
+  */\r
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \\r
+  do{                                                                     \\r
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \\r
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\r
+  }while(0)\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported macros ----------------------------------------------------*/\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Constants TIM Private Constants\r
+  * @{\r
+  */\r
+/* The counter of a timer instance is disabled only if all the CCx and CCxN\r
+   channels have been disabled */\r
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r
+/**\r
+  * @}\r
+  */\r
+/* End of private constants --------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Macros TIM Private Macros\r
+  * @{\r
+  */\r
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \\r
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \\r
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))\r
+\r
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \\r
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_OR1)    || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \\r
+                                   ((__BASE__) == TIM_DMABASE_OR2)   || \\r
+                                   ((__BASE__) == TIM_DMABASE_OR3))\r
+\r
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \\r
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \\r
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \\r
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \\r
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r
+\r
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\r
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\r
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r
+\r
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\r
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\r
+\r
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \\r
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))\r
+\r
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\r
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\r
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \\r
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))\r
+\r
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\r
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))\r
+\r
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \\r
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \\r
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\r
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\r
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))\r
+\r
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\r
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\r
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\r
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))\r
+\r
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \\r
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))\r
+\r
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \\r
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \\r
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))\r
+\r
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \\r
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))\r
+\r
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))\r
+\r
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))\r
+\r
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \\r
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r
+\r
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \\r
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\r
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \\r
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \\r
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\r
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\r
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\r
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\r
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r
+\r
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\r
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\r
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\r
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \\r
+                                            ((__STATE__) == TIM_OSSR_DISABLE))\r
+\r
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \\r
+                                            ((__STATE__) == TIM_OSSI_DISABLE))\r
+\r
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\r
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \\r
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \\r
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))\r
+\r
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)\r
+\r
+\r
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \\r
+                                            ((__STATE__) == TIM_BREAK_DISABLE))\r
+\r
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\r
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\r
+\r
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \\r
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))\r
+\r
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\r
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r
+\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\r
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\r
+\r
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))\r
+\r
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \\r
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \\r
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \\r
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \\r
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \\r
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \\r
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \\r
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))\r
+\r
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \\r
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r
+\r
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\r
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r
+\r
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \\r
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \\r
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \\r
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \\r
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \\r
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
+\r
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \\r
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \\r
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \\r
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \\r
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \\r
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))\r
+\r
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \\r
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \\r
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \\r
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \\r
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \\r
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \\r
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\r
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r
+\r
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \\r
+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \\r
+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \\r
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \\r
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \\r
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \\r
+                                                 ((__SELECTION__) == TIM_TS_ETRF))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \\r
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \\r
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \\r
+                                                               ((__SELECTION__) == TIM_TS_NONE))\r
+\r
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \\r
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\r
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \\r
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \\r
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))\r
+\r
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\r
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\r
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\r
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))\r
+\r
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\r
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r
+\r
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\r
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r
+\r
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)\r
+\r
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \\r
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \\r
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)   || \\r
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))\r
+\r
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \\r
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
+\r
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\r
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))\r
+\r
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\r
+   ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r
+\r
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\\r
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))\r
+\r
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\r
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\r
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\r
+   ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/* Include TIM HAL Extended module */\r
+#include "stm32l4xx_hal_tim_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+  *  @brief   Time Base functions\r
+  * @{\r
+  */\r
+/* Time Base functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+  *  @brief   TIM Output Compare functions\r
+  * @{\r
+  */\r
+/* Timer Output Compare functions *********************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+  *  @brief   TIM PWM functions\r
+  * @{\r
+  */\r
+/* Timer PWM functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+  *  @brief   TIM Input Capture functions\r
+  * @{\r
+  */\r
+/* Timer Input Capture functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+  *  @brief   TIM One Pulse functions\r
+  * @{\r
+  */\r
+/* Timer One Pulse functions **************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+  *  @brief   TIM Encoder functions\r
+  * @{\r
+  */\r
+/* Timer Encoder functions ****************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\r
+                                            uint32_t *pData2, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+  *  @brief   IRQ handler management\r
+  * @{\r
+  */\r
+/* Interrupt Handler functions  ***********************************************/\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+  *  @brief   Peripheral Control functions\r
+  * @{\r
+  */\r
+/* Control functions  *********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,\r
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+                                           uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+  *  @brief   TIM Callbacks functions\r
+  * @{\r
+  */\r
+/* Callback in non blocking modes (Interrupt and DMA) *************************/\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r
+\r
+/* Callbacks Register/UnRegister functions  ***********************************/\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\r
+                                           pTIM_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+  *  @brief  Peripheral State functions\r
+  * @{\r
+  */\r
+/* Peripheral State functions  ************************************************/\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions----------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+  * @{\r
+  */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r
+\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_TIM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
new file mode 100644 (file)
index 0000000..52d7a46
--- /dev/null
@@ -0,0 +1,440 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_tim_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of TIM HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_TIM_EX_H\r
+#define STM32L4xx_HAL_TIM_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup TIMEx\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  TIM Hall sensor Configuration Structure definition\r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.\r
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.\r
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.\r
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+} TIM_HallSensor_InitTypeDef;\r
+\r
+/**\r
+  * @brief  TIM Break/Break2 input configuration\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t Source;         /*!< Specifies the source of the timer break input.\r
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */\r
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.\r
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */\r
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.\r
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity\r
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */\r
+}\r
+TIMEx_BreakInputConfigTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIMEx_Remap TIM Extended Remapping\r
+  * @{\r
+  */\r
+#define TIM_TIM1_ETR_ADC1_NONE      0x00000000U                                           /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/\r
+#define TIM_TIM1_ETR_ADC1_AWD1      TIM1_OR1_ETR_ADC1_RMP_0                               /* !< TIM1_ETR is connected to ADC1 AWD1 */\r
+#define TIM_TIM1_ETR_ADC1_AWD2      TIM1_OR1_ETR_ADC1_RMP_1                               /* !< TIM1_ETR is connected to ADC1 AWD2 */\r
+#define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */\r
+#if defined (ADC3)\r
+#define TIM_TIM1_ETR_ADC3_NONE      0x00000000U                                           /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/\r
+#define TIM_TIM1_ETR_ADC3_AWD1      TIM1_OR1_ETR_ADC3_RMP_0                               /* !< TIM1_ETR is connected to ADC3 AWD1 */\r
+#define TIM_TIM1_ETR_ADC3_AWD2      TIM1_OR1_ETR_ADC3_RMP_1                               /* !< TIM1_ETR is connected to ADC3 AWD2 */\r
+#define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */\r
+#endif /* ADC3 */\r
+#define TIM_TIM1_TI1_GPIO           0x00000000U                                           /* !< TIM1 TI1 is connected to GPIO */\r
+#define TIM_TIM1_TI1_COMP1          TIM1_OR1_TI1_RMP                                      /* !< TIM1 TI1 is connected to COMP1 */\r
+#define TIM_TIM1_ETR_GPIO           0x00000000U                                           /* !< TIM1_ETR is connected to GPIO */\r
+#define TIM_TIM1_ETR_COMP1          TIM1_OR2_ETRSEL_0                                     /* !< TIM1_ETR is connected to COMP1 output */\r
+#if defined(COMP2)\r
+#define TIM_TIM1_ETR_COMP2          TIM1_OR2_ETRSEL_1                                     /* !< TIM1_ETR is connected to COMP2 output */\r
+#endif /* COMP2 */\r
+\r
+#if defined (USB_OTG_FS)\r
+#define TIM_TIM2_ITR1_TIM8_TRGO     0x00000000U                                           /* !< TIM2_ITR1 is connected to TIM8_TRGO */\r
+#define TIM_TIM2_ITR1_OTG_FS_SOF    TIM2_OR1_ITR1_RMP                                     /* !< TIM2_ITR1 is connected to OTG_FS SOF */\r
+#else\r
+#if defined(STM32L471xx)\r
+#define TIM_TIM2_ITR1_TIM8_TRGO     0x00000000U                                           /* !< TIM2_ITR1 is connected to TIM8_TRGO */\r
+#define TIM_TIM2_ITR1_NONE          TIM2_OR1_ITR1_RMP                                     /* !< No internal trigger on TIM2_ITR1 */\r
+#else\r
+#define TIM_TIM2_ITR1_NONE          0x00000000U                                           /* !< No internal trigger on TIM2_ITR1 */\r
+#define TIM_TIM2_ITR1_USB_SOF       TIM2_OR1_ITR1_RMP                                     /* !< TIM2_ITR1 is connected to USB SOF */\r
+#endif /* STM32L471xx */\r
+#endif /* USB_OTG_FS */\r
+#define TIM_TIM2_ETR_GPIO           0x00000000U                                           /* !< TIM2_ETR is connected to GPIO */\r
+#define TIM_TIM2_ETR_LSE            TIM2_OR1_ETR1_RMP                                     /* !< TIM2_ETR is connected to LSE */\r
+#define TIM_TIM2_ETR_COMP1          TIM2_OR2_ETRSEL_0                                     /* !< TIM2_ETR is connected to COMP1 output */\r
+#if defined(COMP2)\r
+#define TIM_TIM2_ETR_COMP2          TIM2_OR2_ETRSEL_1                                     /* !< TIM2_ETR is connected to COMP2 output */\r
+#endif /* COMP2 */\r
+#define TIM_TIM2_TI4_GPIO           0x00000000U                                           /* !< TIM2 TI4 is connected to GPIO */\r
+#define TIM_TIM2_TI4_COMP1          TIM2_OR1_TI4_RMP_0                                    /* !< TIM2 TI4 is connected to COMP1 output */\r
+#if defined(COMP2)\r
+#define TIM_TIM2_TI4_COMP2          TIM2_OR1_TI4_RMP_1                                    /* !< TIM2 TI4 is connected to COMP2 output */\r
+#define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */\r
+#endif /* COMP2 */\r
+\r
+#if defined (TIM3)\r
+#define TIM_TIM3_TI1_GPIO           0x00000000U                                           /* !< TIM3 TI1 is connected to GPIO */\r
+#define TIM_TIM3_TI1_COMP1          TIM3_OR1_TI1_RMP_0                                    /* !< TIM3 TI1 is connected to COMP1 output */\r
+#define TIM_TIM3_TI1_COMP2          TIM3_OR1_TI1_RMP_1                                    /* !< TIM3 TI1 is connected to COMP2 output */\r
+#define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */\r
+#define TIM_TIM3_ETR_GPIO           0x00000000U                                           /* !< TIM3_ETR is connected to GPIO */\r
+#define TIM_TIM3_ETR_COMP1          TIM3_OR2_ETRSEL_0                                     /* !< TIM3_ETR is connected to COMP1 output */\r
+#endif /* TIM3 */\r
+\r
+#if defined (TIM8)\r
+#if defined(ADC2) && defined(ADC3)\r
+#define TIM_TIM8_ETR_ADC2_NONE      0x00000000U                                           /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/\r
+#define TIM_TIM8_ETR_ADC2_AWD1      TIM8_OR1_ETR_ADC2_RMP_0                               /* !< TIM8_ETR is connected to ADC2 AWD1 */\r
+#define TIM_TIM8_ETR_ADC2_AWD2      TIM8_OR1_ETR_ADC2_RMP_1                               /* !< TIM8_ETR is connected to ADC2 AWD2 */\r
+#define TIM_TIM8_ETR_ADC2_AWD3      (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0)   /* !< TIM8_ETR is connected to ADC2 AWD3 */\r
+#define TIM_TIM8_ETR_ADC3_NONE      0x00000000U                                           /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/\r
+#define TIM_TIM8_ETR_ADC3_AWD1      TIM8_OR1_ETR_ADC3_RMP_0                               /* !< TIM8_ETR is connected to ADC3 AWD1 */\r
+#define TIM_TIM8_ETR_ADC3_AWD2      TIM8_OR1_ETR_ADC3_RMP_1                               /* !< TIM8_ETR is connected to ADC3 AWD2 */\r
+#define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */\r
+#endif /* ADC2 && ADC3 */\r
+\r
+#define TIM_TIM8_TI1_GPIO           0x00000000U                                           /* !< TIM8 TI1 is connected to GPIO */\r
+#define TIM_TIM8_TI1_COMP2          TIM8_OR1_TI1_RMP                                      /* !< TIM8 TI1 is connected to COMP1 */\r
+#define TIM_TIM8_ETR_GPIO           0x00000000U                                           /* !< TIM8_ETR is connected to GPIO */\r
+#define TIM_TIM8_ETR_COMP1          TIM8_OR2_ETRSEL_0                                     /* !< TIM8_ETR is connected to COMP1 output */\r
+#define TIM_TIM8_ETR_COMP2          TIM8_OR2_ETRSEL_1                                     /* !< TIM8_ETR is connected to COMP2 output */\r
+#endif /* TIM8 */\r
+\r
+#define TIM_TIM15_TI1_GPIO          0x00000000U                                           /* !< TIM15 TI1 is connected to GPIO */\r
+#define TIM_TIM15_TI1_LSE           TIM15_OR1_TI1_RMP                                     /* !< TIM15 TI1 is connected to LSE */\r
+#define TIM_TIM15_ENCODERMODE_NONE  0x00000000U                                           /* !< No redirection */\r
+#define TIM_TIM15_ENCODERMODE_TIM2  TIM15_OR1_ENCODER_MODE_0                              /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
+#if defined (TIM3)\r
+#define TIM_TIM15_ENCODERMODE_TIM3  TIM15_OR1_ENCODER_MODE_1                              /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
+#endif /* TIM3 */\r
+#if defined (TIM4)\r
+#define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
+#endif /* TIM4 */\r
+\r
+#define TIM_TIM16_TI1_GPIO          0x00000000U                                           /* !< TIM16 TI1 is connected to GPIO */\r
+#define TIM_TIM16_TI1_LSI           TIM16_OR1_TI1_RMP_0                                   /* !< TIM16 TI1 is connected to LSI */\r
+#define TIM_TIM16_TI1_LSE           TIM16_OR1_TI1_RMP_1                                   /* !< TIM16 TI1 is connected to LSE */\r
+#define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */\r
+#if defined (TIM16_OR1_TI1_RMP_2)\r
+#define TIM_TIM16_TI1_MSI           TIM16_OR1_TI1_RMP_2                                   /* !< TIM16 TI1 is connected to MSI */\r
+#define TIM_TIM16_TI1_HSE_32        (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to HSE div 32 */\r
+#define TIM_TIM16_TI1_MCO           (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1)           /* !< TIM16 TI1 is connected to MCO */\r
+#endif /* TIM16_OR1_TI1_RMP_2 */\r
+\r
+#if defined (TIM17)\r
+#define TIM_TIM17_TI1_GPIO          0x00000000U                                           /* !< TIM17 TI1 is connected to GPIO */\r
+#define TIM_TIM17_TI1_MSI           TIM17_OR1_TI1_RMP_0                                   /* !< TIM17 TI1 is connected to MSI */\r
+#define TIM_TIM17_TI1_HSE_32        TIM17_OR1_TI1_RMP_1                                   /* !< TIM17 TI1 is connected to HSE div 32 */\r
+#define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */\r
+#endif /* TIM17 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Break_Input TIM Extended Break input\r
+  * @{\r
+  */\r
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */\r
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source\r
+  * @{\r
+  */\r
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */\r
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */\r
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */\r
+#if defined (DFSDM1_Channel0)\r
+#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */\r
+#endif /* DFSDM1_Channel0 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling\r
+  * @{\r
+  */\r
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */\r
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity\r
+  * @{\r
+  */\r
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */\r
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported macro -----------------------------------------------------*/\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros\r
+  * @{\r
+  */\r
+#define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))\r
+\r
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \\r
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))\r
+\r
+#if defined (DFSDM1_Channel0)\r
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\r
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \\r
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \\r
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))\r
+#else\r
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\r
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \\r
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))\r
+#endif /* DFSDM1_Channel0 */\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \\r
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \\r
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of private macro ------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+  *  @brief    Timer Hall Sensor functions\r
+  * @{\r
+  */\r
+/*  Timer Hall Sensor functions  **********************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);\r
+\r
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);\r
+\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+  *  @brief   Timer Complementary Output Compare functions\r
+  * @{\r
+  */\r
+/*  Timer Complementary Output Compare functions  *****************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+  *  @brief    Timer Complementary PWM functions\r
+  * @{\r
+  */\r
+/*  Timer Complementary PWM functions  ****************************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+  *  @brief    Timer Complementary One Pulse functions\r
+  * @{\r
+  */\r
+/*  Timer Complementary One Pulse functions  **********************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+  *  @brief    Peripheral Control functions\r
+  * @{\r
+  */\r
+/* Extended Control functions  ************************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
+                                              uint32_t  CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
+                                                 uint32_t  CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
+                                                  uint32_t  CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,\r
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
+  * @brief    Extended Callbacks functions\r
+  * @{\r
+  */\r
+/* Extended Callback **********************************************************/\r
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
+  * @brief    Extended Peripheral State functions\r
+  * @{\r
+  */\r
+/* Extended Peripheral State functions  ***************************************/\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions----------------------------------------------------------*/\r
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions\r
+  * @{\r
+  */\r
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);\r
+/**\r
+  * @}\r
+  */\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32L4xx_HAL_TIM_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
new file mode 100644 (file)
index 0000000..723130c
--- /dev/null
@@ -0,0 +1,1686 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_uart.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of UART HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_UART_H\r
+#define STM32L4xx_HAL_UART_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup UART\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Types UART Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief UART Init Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.\r
+                                           The baud rate register is computed using the following formula:\r
+                                           LPUART:\r
+                                           =======\r
+                                              Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))\r
+                                           where lpuart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable)\r
+                                           UART:\r
+                                           =====\r
+                                           - If oversampling is 16 or in LIN mode,\r
+                                              Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))\r
+                                           - If oversampling is 8,\r
+                                              Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]\r
+                                              Baud Rate Register[3] =  0\r
+                                              Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1\r
+                                           where uart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable) */\r
+\r
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r
+                                           This parameter can be a value of @ref UARTEx_Word_Length. */\r
+\r
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\r
+                                           This parameter can be a value of @ref UART_Stop_Bits. */\r
+\r
+  uint32_t Parity;                    /*!< Specifies the parity mode.\r
+                                           This parameter can be a value of @ref UART_Parity\r
+                                           @note When parity is enabled, the computed parity is inserted\r
+                                                 at the MSB position of the transmitted data (9th bit when\r
+                                                 the word length is set to 9 data bits; 8th bit when the\r
+                                                 word length is set to 8 data bits). */\r
+\r
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+                                           This parameter can be a value of @ref UART_Mode. */\r
+\r
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled\r
+                                           or disabled.\r
+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control. */\r
+\r
+  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).\r
+                                           This parameter can be a value of @ref UART_Over_Sampling. */\r
+\r
+  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.\r
+                                           Selecting the single sample method increases the receiver tolerance to clock\r
+                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */\r
+\r
+#if defined(USART_PRESC_PRESCALER)\r
+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the UART clock source.\r
+                                           This parameter can be a value of @ref UART_ClockPrescaler. */\r
+#endif /* USART_PRESC_PRESCALER */\r
+\r
+} UART_InitTypeDef;\r
+\r
+/**\r
+  * @brief  UART Advanced Features initialization structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several\r
+                                       Advanced Features may be initialized at the same time .\r
+                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */\r
+\r
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.\r
+                                       This parameter can be a value of @ref UART_Tx_Inv. */\r
+\r
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.\r
+                                       This parameter can be a value of @ref UART_Rx_Inv. */\r
+\r
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic\r
+                                       vs negative/inverted logic).\r
+                                       This parameter can be a value of @ref UART_Data_Inv. */\r
+\r
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.\r
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */\r
+\r
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.\r
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */\r
+\r
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.\r
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */\r
+\r
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.\r
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */\r
+\r
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate\r
+                                       detection is carried out.\r
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */\r
+\r
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.\r
+                                       This parameter can be a value of @ref UART_MSB_First. */\r
+} UART_AdvFeatureInitTypeDef;\r
+\r
+\r
+\r
+/**\r
+  * @brief HAL UART State definition\r
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).\r
+  *        - gState contains UART state information related to global Handle management\r
+  *          and also information related to Tx operations.\r
+  *          gState value coding follow below described bitmap :\r
+  *          b7-b6  Error information\r
+  *             00 : No Error\r
+  *             01 : (Not Used)\r
+  *             10 : Timeout\r
+  *             11 : Error\r
+  *          b5     Peripheral initialization status\r
+  *             0  : Reset (Peripheral not initialized)\r
+  *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)\r
+  *          b4-b3  (not used)\r
+  *             xx : Should be set to 00\r
+  *          b2     Intrinsic process state\r
+  *             0  : Ready\r
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)\r
+  *          b1     (not used)\r
+  *             x  : Should be set to 0\r
+  *          b0     Tx state\r
+  *             0  : Ready (no Tx operation ongoing)\r
+  *             1  : Busy (Tx operation ongoing)\r
+  *        - RxState contains information related to Rx operations.\r
+  *          RxState value coding follow below described bitmap :\r
+  *          b7-b6  (not used)\r
+  *             xx : Should be set to 00\r
+  *          b5     Peripheral initialization status\r
+  *             0  : Reset (Peripheral not initialized)\r
+  *             1  : Init done (Peripheral not initialized)\r
+  *          b4-b2  (not used)\r
+  *            xxx : Should be set to 000\r
+  *          b1     Rx state\r
+  *             0  : Ready (no Rx operation ongoing)\r
+  *             1  : Busy (Rx operation ongoing)\r
+  *          b0     (not used)\r
+  *             x  : Should be set to 0.\r
+  */\r
+typedef uint32_t HAL_UART_StateTypeDef;\r
+\r
+/**\r
+  * @brief UART clock sources definition\r
+  */\r
+typedef enum\r
+{\r
+  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r
+  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r
+  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r
+  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r
+  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */\r
+  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */\r
+} UART_ClockSourceTypeDef;\r
+\r
+/**\r
+  * @brief  UART handle Structure definition\r
+  */\r
+typedef struct __UART_HandleTypeDef\r
+{\r
+  USART_TypeDef            *Instance;                /*!< UART registers base address        */\r
+\r
+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */\r
+\r
+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */\r
+\r
+  uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */\r
+\r
+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */\r
+\r
+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */\r
+\r
+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */\r
+\r
+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */\r
+\r
+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */\r
+\r
+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.\r
+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */\r
+\r
+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */\r
+\r
+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */\r
+#endif /*USART_CR1_FIFOEN */\r
+\r
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler   */\r
+\r
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler   */\r
+\r
+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */\r
+\r
+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */\r
+\r
+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */\r
+\r
+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management\r
+                                                          and also related to Tx operations.\r
+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations.\r
+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */\r
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */\r
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */\r
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */\r
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */\r
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */\r
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */\r
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */\r
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */\r
+#if defined(USART_CR1_FIFOEN)\r
+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */\r
+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */\r
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */\r
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+} UART_HandleTypeDef;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  HAL UART Callback ID enumeration definition\r
+  */\r
+typedef enum\r
+{\r
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */\r
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */\r
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */\r
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */\r
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */\r
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */\r
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */\r
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */\r
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */\r
+#if defined(USART_CR1_FIFOEN)\r
+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */\r
+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */\r
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */\r
+\r
+} HAL_UART_CallbackIDTypeDef;\r
+\r
+/**\r
+  * @brief  HAL UART Callback pointer definition\r
+  */\r
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */\r
+\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Constants UART Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup UART_State_Definition UART State Code Definition\r
+  * @{\r
+  */\r
+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized\r
+                                                          Value is allowed for gState and RxState */\r
+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use\r
+                                                          Value is allowed for gState and RxState */\r
+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing\r
+                                                          Value is allowed for gState only */\r
+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing\r
+                                                          Value is allowed for gState only */\r
+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing\r
+                                                          Value is allowed for RxState only */\r
+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing\r
+                                                          Not to be used for neither gState nor RxState.\r
+                                                          Value is result of combination (Or) between gState and RxState values */\r
+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state\r
+                                                          Value is allowed for gState only */\r
+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error\r
+                                                          Value is allowed for gState only */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Error_Definition   UART Error Definition\r
+  * @{\r
+  */\r
+#define  HAL_UART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                */\r
+#define  HAL_UART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error            */\r
+#define  HAL_UART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error             */\r
+#define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */\r
+#define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */\r
+#define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+#define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits\r
+  * @{\r
+  */\r
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */\r
+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */\r
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */\r
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Parity  UART Parity\r
+  * @{\r
+  */\r
+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */\r
+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */\r
+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r
+  * @{\r
+  */\r
+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */\r
+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */\r
+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */\r
+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Mode UART Transfer Mode\r
+  * @{\r
+  */\r
+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */\r
+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */\r
+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_State  UART State\r
+  * @{\r
+  */\r
+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */\r
+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Over_Sampling UART Over Sampling\r
+  * @{\r
+  */\r
+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */\r
+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method\r
+  * @{\r
+  */\r
+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */\r
+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(USART_PRESC_PRESCALER)\r
+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler\r
+  * @{\r
+  */\r
+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */\r
+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */\r
+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */\r
+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */\r
+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */\r
+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */\r
+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */\r
+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */\r
+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */\r
+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */\r
+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */\r
+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* USART_PRESC_PRESCALER */\r
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection on start bit            */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection on falling edge         */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection on 0x7F frame detection */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection on 0x55 frame detection */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut\r
+  * @{\r
+  */\r
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                 /*!< UART receiver timeout disable */\r
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN             /*!< UART receiver timeout enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_LIN    UART Local Interconnection Network mode\r
+  * @{\r
+  */\r
+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */\r
+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection\r
+  * @{\r
+  */\r
+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */\r
+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_DMA_Tx    UART DMA Tx\r
+  * @{\r
+  */\r
+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */\r
+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_DMA_Rx   UART DMA Rx\r
+  * @{\r
+  */\r
+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */\r
+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection\r
+  * @{\r
+  */\r
+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */\r
+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods\r
+  * @{\r
+  */\r
+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */\r
+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Request_Parameters UART Request Parameters\r
+  * @{\r
+  */\r
+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */\r
+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */\r
+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */\r
+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */\r
+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */\r
+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */\r
+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */\r
+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */\r
+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */\r
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */\r
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */\r
+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */\r
+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */\r
+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */\r
+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */\r
+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */\r
+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */\r
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received first disable */\r
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received first enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */\r
+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable\r
+  * @{\r
+  */\r
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */\r
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register\r
+  * @{\r
+  */\r
+#define UART_CR2_ADDRESS_LSB_POS             24U                                /*!< UART address-matching LSB position in CR2 register */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection\r
+  * @{\r
+  */\r
+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                         */\r
+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                       */\r
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity\r
+  * @{\r
+  */\r
+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */\r
+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register\r
+  * @{\r
+  */\r
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB position in CR1 register */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register\r
+  * @{\r
+  */\r
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB position in CR1 register */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask\r
+  * @{\r
+  */\r
+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value\r
+  * @{\r
+  */\r
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Flags     UART Status Flags\r
+  *        Elements values convention: 0xXXXX\r
+  *           - 0xXXXX  : Flag mask in the ISR register\r
+  * @{\r
+  */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */\r
+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */\r
+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */\r
+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */\r
+#endif /* USART_CR1_FIFOEN */\r
+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */\r
+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */\r
+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */\r
+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */\r
+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */\r
+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */\r
+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */\r
+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */\r
+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */\r
+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */\r
+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */\r
+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */\r
+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */\r
+#else\r
+#define UART_FLAG_TXE                       USART_ISR_TXE           /*!< UART transmit data register empty         */\r
+#endif /* USART_CR1_FIFOEN */\r
+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */\r
+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */\r
+#else\r
+#define UART_FLAG_RXNE                      USART_ISR_RXNE          /*!< UART read data register not empty         */\r
+#endif /* USART_CR1_FIFOEN */\r
+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */\r
+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */\r
+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */\r
+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */\r
+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition\r
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb\r
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r
+  *           - XX  : Interrupt source register (2bits)\r
+  *                 - 01: CR1 register\r
+  *                 - 10: CR2 register\r
+  *                 - 11: CR3 register\r
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)\r
+  *        Elements values convention: 000000000XXYYYYYb\r
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r
+  *           - XX  : Interrupt source register (2bits)\r
+  *                 - 01: CR1 register\r
+  *                 - 10: CR2 register\r
+  *                 - 11: CR3 register\r
+  *        Elements values convention: 0000ZZZZ00000000b\r
+  *           - ZZZZ  : Flag position in the ISR register(4bits)\r
+  * @{\r
+  */\r
+#define UART_IT_PE                          0x0028U                  /*!< UART parity error interruption                 */\r
+#define UART_IT_TXE                         0x0727U                  /*!< UART transmit data register empty interruption */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define UART_IT_TXFNF                       0x0727U                  /*!< UART TX FIFO not full interruption             */\r
+#endif /* USART_CR1_FIFOEN */\r
+#define UART_IT_TC                          0x0626U                  /*!< UART transmission complete interruption        */\r
+#define UART_IT_RXNE                        0x0525U                  /*!< UART read data register not empty interruption */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define UART_IT_RXFNE                       0x0525U                  /*!< UART RXFIFO not empty interruption             */\r
+#endif /* USART_CR1_FIFOEN */\r
+#define UART_IT_IDLE                        0x0424U                  /*!< UART idle interruption                         */\r
+#define UART_IT_LBD                         0x0846U                  /*!< UART LIN break detection interruption          */\r
+#define UART_IT_CTS                         0x096AU                  /*!< UART CTS interruption                          */\r
+#define UART_IT_CM                          0x112EU                  /*!< UART character match interruption              */\r
+#define UART_IT_WUF                         0x1476U                  /*!< UART wake-up from stop mode interruption       */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define UART_IT_RXFF                        0x183FU                  /*!< UART RXFIFO full interruption                  */\r
+#define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */\r
+#define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */\r
+#define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+#define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */\r
+\r
+#define UART_IT_ORE                         0x0300U                  /*!< UART overrun error interruption */\r
+#define UART_IT_NE                          0x0200U                  /*!< UART noise error interruption   */\r
+#define UART_IT_FE                          0x0100U                  /*!< UART frame error interruption   */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags\r
+  * @{\r
+  */\r
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */\r
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */\r
+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */\r
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */\r
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */\r
+#endif /* USART_CR1_FIFOEN */\r
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */\r
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */\r
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */\r
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */\r
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Macros UART Exported Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Reset UART handle states.\r
+  * @param  __HANDLE__ UART handle.\r
+  * @retval None\r
+  */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\r
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\r
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\r
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \\r
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \\r
+                                                     } while(0U)\r
+#else\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\r
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\r
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\r
+                                                     } while(0U)\r
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/** @brief  Flush the UART Data registers.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \\r
+  do{                \\r
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \\r
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \\r
+  }  while(0U)\r
+\r
+/** @brief  Clear the specified UART pending flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __FLAG__ specifies the flag to check.\r
+  *          This parameter can be any combination of the following values:\r
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag\r
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag\r
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag\r
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag\r
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag\r
+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag\r
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag\r
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag\r
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag\r
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag\r
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r
+\r
+/** @brief  Clear the UART PE pending flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)\r
+\r
+/** @brief  Clear the UART FE pending flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)\r
+\r
+/** @brief  Clear the UART NE pending flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)\r
+\r
+/** @brief  Clear the UART ORE pending flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)\r
+\r
+/** @brief  Clear the UART IDLE pending flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/** @brief  Clear the UART TX FIFO empty clear flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/** @brief  Check whether the specified UART flag is set or not.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __FLAG__ specifies the flag to check.\r
+  *        This parameter can be one of the following values:\r
+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag\r
+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag\r
+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag\r
+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag\r
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag\r
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag\r
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag\r
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)\r
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag\r
+  *            @arg @ref UART_FLAG_CMF   Character match flag\r
+  *            @arg @ref UART_FLAG_BUSY  Busy flag\r
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag\r
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag\r
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag\r
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag\r
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag\r
+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag\r
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag\r
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag\r
+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag\r
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag\r
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag\r
+  *            @arg @ref UART_FLAG_NE    Noise Error flag\r
+  *            @arg @ref UART_FLAG_FE    Framing Error flag\r
+  *            @arg @ref UART_FLAG_PE    Parity Error flag\r
+  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+  */\r
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief  Enable the specified UART interrupt.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
+  *            @arg @ref UART_IT_CM    Character match interrupt\r
+  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
+  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+\r
+/** @brief  Disable the specified UART interrupt.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
+  *            @arg @ref UART_IT_CM    Character match interrupt\r
+  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
+  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+/** @brief  Check whether the specified UART interrupt has occurred or not.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __INTERRUPT__ specifies the UART interrupt to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
+  *            @arg @ref UART_IT_CM    Character match interrupt\r
+  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
+  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)\r
+  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+  */\r
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\\r
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)\r
+\r
+/** @brief  Check whether the specified UART interrupt source is enabled or not.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
+  *            @arg @ref UART_IT_CM    Character match interrupt\r
+  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
+  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)\r
+  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+  */\r
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \\r
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \\r
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)\r
+\r
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r
+  *                       to clear the corresponding interrupt\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag\r
+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag\r
+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag\r
+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag\r
+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag\r
+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag\r
+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag\r
+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag\r
+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag\r
+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag\r
+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))\r
+\r
+/** @brief  Set a specific UART request flag.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __REQ__ specifies the request flag to set\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request\r
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request\r
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request\r
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request\r
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))\r
+\r
+/** @brief  Enable the UART one bit sample method.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r
+\r
+/** @brief  Disable the UART one bit sample method.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)\r
+\r
+/** @brief  Enable UART.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief  Disable UART.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/** @brief  Enable CTS flow control.\r
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,\r
+  *         without need to call HAL_UART_Init() function.\r
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \\r
+  do{                                                      \\r
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \\r
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \\r
+  } while(0U)\r
+\r
+/** @brief  Disable CTS flow control.\r
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,\r
+  *         without need to call HAL_UART_Init() function.\r
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \\r
+  do{                                                       \\r
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \\r
+  } while(0U)\r
+\r
+/** @brief  Enable RTS flow control.\r
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,\r
+  *         without need to call HAL_UART_Init() function.\r
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \\r
+  do{                                                     \\r
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\r
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \\r
+  } while(0U)\r
+\r
+/** @brief  Disable RTS flow control.\r
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,\r
+  *         without need to call HAL_UART_Init() function.\r
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None\r
+  */\r
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \\r
+  do{                                                      \\r
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\r
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \\r
+  } while(0U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup UART_Private_Macros   UART Private Macros\r
+  * @{\r
+  */\r
+#if defined(USART_PRESC_PRESCALER)\r
+/** @brief  Get UART clok division factor from clock prescaler value.\r
+  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
+  * @retval UART clock division factor\r
+  */\r
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \\r
+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \\r
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)\r
+\r
+/** @brief  BRR division operation to set BRR register with LPUART.\r
+  * @param  __PCLK__ LPUART clock.\r
+  * @param  __BAUD__ Baud rate set by the user.\r
+  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
+  * @retval Division result\r
+  */\r
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\\r
+                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))\r
+\r
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.\r
+  * @param  __PCLK__ UART clock.\r
+  * @param  __BAUD__ Baud rate set by the user.\r
+  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
+  * @retval Division result\r
+  */\r
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\\r
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))\r
+\r
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.\r
+  * @param  __PCLK__ UART clock.\r
+  * @param  __BAUD__ Baud rate set by the user.\r
+  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
+  * @retval Division result\r
+  */\r
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\\r
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))\r
+#else\r
+\r
+/** @brief  BRR division operation to set BRR register with LPUART.\r
+  * @param  __PCLK__ LPUART clock.\r
+  * @param  __BAUD__ Baud rate set by the user.\r
+  * @retval Division result\r
+  */\r
+#define UART_DIV_LPUART(__PCLK__, __BAUD__)      (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__))\r
+\r
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.\r
+  * @param  __PCLK__ UART clock.\r
+  * @param  __BAUD__ Baud rate set by the user.\r
+  * @retval Division result\r
+  */\r
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))\r
+\r
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.\r
+  * @param  __PCLK__ UART clock.\r
+  * @param  __BAUD__ Baud rate set by the user.\r
+  * @retval Division result\r
+  */\r
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))\r
+#endif /* USART_PRESC_PRESCALER */\r
+\r
+/** @brief  Check whether or not UART instance is Low Power UART.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)\r
+  */\r
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))\r
+\r
+/** @brief  Check UART Baud rate.\r
+  * @param  __BAUDRATE__ Baudrate specified by the user.\r
+  *         The maximum Baud Rate is derived from the maximum clock on L4\r
+  *         divided by the smallest oversampling used on the USART (i.e. 8)\r
+  *          (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise)\r
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)\r
+  */\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U)\r
+#else\r
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U)\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/** @brief  Check UART assertion time.\r
+  * @param  __TIME__ 5-bit value assertion time.\r
+  * @retval Test result (TRUE or FALSE).\r
+  */\r
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)\r
+\r
+/** @brief  Check UART deassertion time.\r
+  * @param  __TIME__ 5-bit value deassertion time.\r
+  * @retval Test result (TRUE or FALSE).\r
+  */\r
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)\r
+\r
+/**\r
+  * @brief Ensure that UART frame number of stop bits is valid.\r
+  * @param __STOPBITS__ UART frame number of stop bits.\r
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)\r
+  */\r
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \\r
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \\r
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \\r
+                                        ((__STOPBITS__) == UART_STOPBITS_2))\r
+\r
+/**\r
+  * @brief Ensure that LPUART frame number of stop bits is valid.\r
+  * @param __STOPBITS__ LPUART frame number of stop bits.\r
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)\r
+  */\r
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \\r
+                                          ((__STOPBITS__) == UART_STOPBITS_2))\r
+\r
+/**\r
+  * @brief Ensure that UART frame parity is valid.\r
+  * @param __PARITY__ UART frame parity.\r
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)\r
+  */\r
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \\r
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \\r
+                                    ((__PARITY__) == UART_PARITY_ODD))\r
+\r
+/**\r
+  * @brief Ensure that UART hardware flow control is valid.\r
+  * @param __CONTROL__ UART hardware flow control.\r
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)\r
+  */\r
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\\r
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \\r
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \\r
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \\r
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))\r
+\r
+/**\r
+  * @brief Ensure that UART communication mode is valid.\r
+  * @param __MODE__ UART communication mode.\r
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+  */\r
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))\r
+\r
+/**\r
+  * @brief Ensure that UART state is valid.\r
+  * @param __STATE__ UART state.\r
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)\r
+  */\r
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \\r
+                                  ((__STATE__) == UART_STATE_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART oversampling is valid.\r
+  * @param __SAMPLING__ UART oversampling.\r
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)\r
+  */\r
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \\r
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))\r
+\r
+/**\r
+  * @brief Ensure that UART frame sampling is valid.\r
+  * @param __ONEBIT__ UART frame sampling.\r
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)\r
+  */\r
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \\r
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART auto Baud rate detection mode is valid.\r
+  * @param __MODE__ UART auto Baud rate detection mode.\r
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \\r
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \\r
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \\r
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))\r
+\r
+/**\r
+  * @brief Ensure that UART receiver timeout setting is valid.\r
+  * @param __TIMEOUT__ UART receiver timeout setting.\r
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)\r
+  */\r
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \\r
+                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART LIN state is valid.\r
+  * @param __LIN__ UART LIN state.\r
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)\r
+  */\r
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \\r
+                                     ((__LIN__) == UART_LIN_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART LIN break detection length is valid.\r
+  * @param __LENGTH__ UART LIN break detection length.\r
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)\r
+  */\r
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \\r
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))\r
+\r
+/**\r
+  * @brief Ensure that UART DMA TX state is valid.\r
+  * @param __DMATX__ UART DMA TX state.\r
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)\r
+  */\r
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \\r
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART DMA RX state is valid.\r
+  * @param __DMARX__ UART DMA RX state.\r
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)\r
+  */\r
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \\r
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART half-duplex state is valid.\r
+  * @param __HDSEL__ UART half-duplex state.\r
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)\r
+  */\r
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \\r
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART wake-up method is valid.\r
+  * @param __WAKEUP__ UART wake-up method .\r
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)\r
+  */\r
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \\r
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))\r
+\r
+/**\r
+  * @brief Ensure that UART request parameter is valid.\r
+  * @param __PARAM__ UART request parameter.\r
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)\r
+  */\r
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \\r
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \\r
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \\r
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \\r
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))\r
+\r
+/**\r
+  * @brief Ensure that UART advanced features initialization is valid.\r
+  * @param __INIT__ UART advanced features initialization.\r
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \\r
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \\r
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \\r
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \\r
+                                                            UART_ADVFEATURE_SWAP_INIT              | \\r
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \\r
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \\r
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \\r
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))\r
+\r
+/**\r
+  * @brief Ensure that UART frame TX inversion setting is valid.\r
+  * @param __TXINV__ UART frame TX inversion setting.\r
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \\r
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART frame RX inversion setting is valid.\r
+  * @param __RXINV__ UART frame RX inversion setting.\r
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \\r
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART frame data inversion setting is valid.\r
+  * @param __DATAINV__ UART frame data inversion setting.\r
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \\r
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.\r
+  * @param __SWAP__ UART frame RX/TX pins swap setting.\r
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \\r
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART frame overrun setting is valid.\r
+  * @param __OVERRUN__ UART frame overrun setting.\r
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)\r
+  */\r
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \\r
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART auto Baud rate state is valid.\r
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.\r
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \\r
+                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.\r
+  * @param __DMA__ UART DMA enabling or disabling on error setting.\r
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \\r
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))\r
+\r
+/**\r
+  * @brief Ensure that UART frame MSB first setting is valid.\r
+  * @param __MSBFIRST__ UART frame MSB first setting.\r
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \\r
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART stop mode state is valid.\r
+  * @param __STOPMODE__ UART stop mode state.\r
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)\r
+  */\r
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \\r
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART mute mode state is valid.\r
+  * @param __MUTE__ UART mute mode state.\r
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)\r
+  */\r
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \\r
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))\r
+\r
+/**\r
+  * @brief Ensure that UART wake-up selection is valid.\r
+  * @param __WAKE__ UART wake-up selection.\r
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)\r
+  */\r
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \\r
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \\r
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))\r
+\r
+/**\r
+  * @brief Ensure that UART driver enable polarity is valid.\r
+  * @param __POLARITY__ UART driver enable polarity.\r
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)\r
+  */\r
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \\r
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))\r
+\r
+#if defined(USART_PRESC_PRESCALER)\r
+/**\r
+  * @brief Ensure that UART Prescaler is valid.\r
+  * @param __CLOCKPRESCALER__ UART Prescaler value.\r
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)\r
+  */\r
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \\r
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))\r
+#endif /* USART_PRESC_PRESCALER */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Include UART HAL Extended module */\r
+#include "stm32l4xx_hal_uart_ex.h"\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup UART_Exported_Functions UART Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  * @{\r
+  */\r
+\r
+/* Initialization and de-initialization functions  ****************************/\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r
+\r
+/* Callbacks Register/UnRegister functions  ***********************************/\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,\r
+                                            pUART_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r
+  * @{\r
+  */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r
+/* Transfer Abort functions */\r
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);\r
+\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+  * @{\r
+  */\r
+\r
+/* Peripheral Control functions  ************************************************/\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
+  * @{\r
+  */\r
+\r
+/* Peripheral State and Errors functions  **************************************************/\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions -----------------------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions UART Private Functions\r
+  * @{\r
+  */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,\r
+                                              uint32_t Tickstart, uint32_t Timeout);\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_UART_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h
new file mode 100644 (file)
index 0000000..b9835b5
--- /dev/null
@@ -0,0 +1,734 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_uart_ex.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of UART HAL Extended module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_UART_EX_H\r
+#define STM32L4xx_HAL_UART_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup UARTEx\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  UART wake up from stop mode parameters\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).\r
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.\r
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must\r
+                                    be filled up. */\r
+\r
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.\r
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */\r
+\r
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */\r
+} UART_WakeUpTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup UARTEx_Word_Length UARTEx Word Length\r
+  * @{\r
+  */\r
+#define UART_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long UART frame */\r
+#define UART_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long UART frame */\r
+#define UART_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long UART frame */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length\r
+  * @{\r
+  */\r
+#define UART_ADDRESS_DETECT_4B              0x00000000U      /*!< 4-bit long wake-up address */\r
+#define UART_ADDRESS_DETECT_7B              USART_CR2_ADDM7  /*!< 7-bit long wake-up address */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode\r
+  * @brief    UART FIFO mode\r
+  * @{\r
+  */\r
+#define UART_FIFOMODE_DISABLE        0x00000000U       /*!< FIFO mode disable */\r
+#define UART_FIFOMODE_ENABLE         USART_CR1_FIFOEN  /*!< FIFO mode enable  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level\r
+  * @brief    UART TXFIFO threshold level\r
+  * @{\r
+  */\r
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level\r
+  * @brief    UART RXFIFO threshold level\r
+  * @{\r
+  */\r
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */\r
+/**\r
+  * @}\r
+  */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup UARTEx_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group1\r
+  * @{\r
+  */\r
+\r
+/* Initialization and de-initialization functions  ****************************/\r
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,\r
+                                   uint32_t DeassertionTime);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group2\r
+  * @{\r
+  */\r
+\r
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);\r
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group3\r
+  * @{\r
+  */\r
+\r
+/* Peripheral Control functions  **********************************************/\r
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);\r
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);\r
+#if defined(USART_CR3_UCESM)\r
+HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);\r
+#endif /* USART_CR3_UCESM */\r
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r
+#if defined(USART_CR1_FIFOEN)\r
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);\r
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros\r
+  * @{\r
+  */\r
+\r
+/** @brief  Report the UART clock source.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @param  __CLOCKSOURCE__ output variable.\r
+  * @retval UART clocking source, written in __CLOCKSOURCE__.\r
+  */\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \\r
+    || defined (STM32L496xx) || defined (STM32L4A6xx) \\r
+    || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
+  do {                                                        \\r
+    if((__HANDLE__)->Instance == USART1)                      \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == USART2)                 \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == USART3)                 \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART3CLKSOURCE_PCLK1:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == UART4)                  \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \\r
+      {                                                       \\r
+        case RCC_UART4CLKSOURCE_PCLK1:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_UART4CLKSOURCE_HSI:                          \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_UART4CLKSOURCE_LSE:                          \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == UART5)                  \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \\r
+      {                                                       \\r
+        case RCC_UART5CLKSOURCE_PCLK1:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_UART5CLKSOURCE_HSI:                          \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_UART5CLKSOURCE_LSE:                          \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == LPUART1)                \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
+      {                                                       \\r
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else                                                      \\r
+    {                                                         \\r
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
+    }                                                         \\r
+  } while(0U)\r
+#elif defined (STM32L412xx) || defined (STM32L422xx) \\r
+   || defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)\r
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
+  do {                                                        \\r
+    if((__HANDLE__)->Instance == USART1)                      \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == USART2)                 \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == USART3)                 \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART3CLKSOURCE_PCLK1:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == LPUART1)                \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
+      {                                                       \\r
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else                                                      \\r
+    {                                                         \\r
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
+    }                                                         \\r
+  } while(0U)\r
+#elif defined (STM32L432xx) || defined (STM32L442xx)\r
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
+  do {                                                        \\r
+    if((__HANDLE__)->Instance == USART1)                      \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == USART2)                 \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == LPUART1)                \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
+      {                                                       \\r
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else                                                      \\r
+    {                                                         \\r
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
+    }                                                         \\r
+  } while(0U)\r
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
+  do {                                                        \\r
+    if((__HANDLE__)->Instance == USART1)                      \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART1CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == USART2)                 \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART2CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == USART3)                 \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \\r
+      {                                                       \\r
+        case RCC_USART3CLKSOURCE_PCLK1:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_HSI:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_USART3CLKSOURCE_LSE:                         \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == UART4)                  \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \\r
+      {                                                       \\r
+        case RCC_UART4CLKSOURCE_PCLK1:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_UART4CLKSOURCE_HSI:                          \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_UART4CLKSOURCE_LSE:                          \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else if((__HANDLE__)->Instance == LPUART1)                \\r
+    {                                                         \\r
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
+      {                                                       \\r
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
+          break;                                              \\r
+        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
+          break;                                              \\r
+        default:                                              \\r
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
+          break;                                              \\r
+      }                                                       \\r
+    }                                                         \\r
+    else                                                      \\r
+    {                                                         \\r
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
+    }                                                         \\r
+  } while(0U)\r
+#endif /* STM32L471xx ||  STM32L475xx ||  STM32L476xx ||  STM32L485xx ||  STM32L486xx ||\r
+        * STM32L496xx ||  STM32L4A6xx ||\r
+        * STM32L4R5xx ||  STM32L4R7xx ||  STM32L4R9xx ||  STM32L4S5xx ||  STM32L4S7xx ||  STM32L4S9xx\r
+        */\r
+\r
+/** @brief  Report the UART mask to apply to retrieve the received data\r
+  *         according to the word length and to the parity bits activation.\r
+  * @note   If PCE = 1, the parity bit is not included in the data extracted\r
+  *         by the reception API().\r
+  *         This masking operation is not carried out in the case of\r
+  *         DMA transfers.\r
+  * @param  __HANDLE__ specifies the UART Handle.\r
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.\r
+  */\r
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \\r
+  do {                                                                \\r
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \\r
+    {                                                                 \\r
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \\r
+      {                                                               \\r
+        (__HANDLE__)->Mask = 0x01FFU ;                                \\r
+      }                                                               \\r
+      else                                                            \\r
+      {                                                               \\r
+        (__HANDLE__)->Mask = 0x00FFU ;                                \\r
+      }                                                               \\r
+    }                                                                 \\r
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \\r
+    {                                                                 \\r
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \\r
+      {                                                               \\r
+        (__HANDLE__)->Mask = 0x00FFU ;                                \\r
+      }                                                               \\r
+      else                                                            \\r
+      {                                                               \\r
+        (__HANDLE__)->Mask = 0x007FU ;                                \\r
+      }                                                               \\r
+    }                                                                 \\r
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \\r
+    {                                                                 \\r
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \\r
+      {                                                               \\r
+        (__HANDLE__)->Mask = 0x007FU ;                                \\r
+      }                                                               \\r
+      else                                                            \\r
+      {                                                               \\r
+        (__HANDLE__)->Mask = 0x003FU ;                                \\r
+      }                                                               \\r
+    }                                                                 \\r
+    else                                                              \\r
+    {                                                                 \\r
+      (__HANDLE__)->Mask = 0x0000U;                                   \\r
+    }                                                                 \\r
+  } while(0U)\r
+\r
+/**\r
+  * @brief Ensure that UART frame length is valid.\r
+  * @param __LENGTH__ UART frame length.\r
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)\r
+  */\r
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \\r
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \\r
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))\r
+\r
+/**\r
+  * @brief Ensure that UART wake-up address length is valid.\r
+  * @param __ADDRESS__ UART wake-up address length.\r
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)\r
+  */\r
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \\r
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/**\r
+  * @brief Ensure that UART TXFIFO threshold level is valid.\r
+  * @param __THRESHOLD__ UART TXFIFO threshold level.\r
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
+  */\r
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \\r
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \\r
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \\r
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \\r
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \\r
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))\r
+\r
+/**\r
+  * @brief Ensure that UART RXFIFO threshold level is valid.\r
+  * @param __THRESHOLD__ UART RXFIFO threshold level.\r
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
+  */\r
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \\r
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \\r
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \\r
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \\r
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \\r
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_UART_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h
new file mode 100644 (file)
index 0000000..ac9c7bd
--- /dev/null
@@ -0,0 +1,652 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_ll_usb.h\r
+  * @author  MCD Application Team\r
+  * @brief   Header file of USB Low Layer HAL module.\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_LL_USB_H\r
+#define STM32L4xx_LL_USB_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+#if defined (USB) || defined (USB_OTG_FS)\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup USB_LL\r
+  * @{\r
+  */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/**\r
+  * @brief  USB Mode definition\r
+  */\r
+#if defined (USB_OTG_FS)\r
+\r
+typedef enum\r
+{\r
+  USB_DEVICE_MODE  = 0,\r
+  USB_HOST_MODE    = 1,\r
+  USB_DRD_MODE     = 2\r
+} USB_ModeTypeDef;\r
+\r
+/**\r
+  * @brief  URB States definition\r
+  */\r
+typedef enum\r
+{\r
+  URB_IDLE = 0,\r
+  URB_DONE,\r
+  URB_NOTREADY,\r
+  URB_NYET,\r
+  URB_ERROR,\r
+  URB_STALL\r
+} USB_OTG_URBStateTypeDef;\r
+\r
+/**\r
+  * @brief  Host channel States  definition\r
+  */\r
+typedef enum\r
+{\r
+  HC_IDLE = 0,\r
+  HC_XFRC,\r
+  HC_HALTED,\r
+  HC_NAK,\r
+  HC_NYET,\r
+  HC_STALL,\r
+  HC_XACTERR,\r
+  HC_BBLERR,\r
+  HC_DATATGLERR\r
+} USB_OTG_HCStateTypeDef;\r
+\r
+/**\r
+  * @brief  USB OTG Initialization Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t dev_endpoints;           /*!< Device Endpoints number.\r
+                                         This parameter depends on the used USB core.\r
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r
+\r
+  uint32_t Host_channels;           /*!< Host Channels number.\r
+                                         This parameter Depends on the used USB core.\r
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r
+\r
+  uint32_t speed;                   /*!< USB Core speed.\r
+                                         This parameter can be any value of @ref USB_Core_Speed_                */\r
+\r
+  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */\r
+\r
+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */\r
+\r
+  uint32_t phy_itface;              /*!< Select the used PHY interface.\r
+                                         This parameter can be any value of @ref USB_Core_PHY_                  */\r
+\r
+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */\r
+\r
+  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */\r
+\r
+  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */\r
+\r
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */\r
+\r
+  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */\r
+\r
+  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */\r
+\r
+  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */\r
+} USB_OTG_CfgTypeDef;\r
+\r
+typedef struct\r
+{\r
+  uint8_t   num;                  /*!< Endpoint number\r
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\r
+\r
+  uint8_t   is_in;                /*!< Endpoint direction\r
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
+\r
+  uint8_t   is_stall;             /*!< Endpoint stall condition\r
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
+\r
+  uint8_t   type;                 /*!< Endpoint type\r
+                                       This parameter can be any value of @ref USB_EP_Type_                     */\r
+\r
+  uint8_t   data_pid_start;       /*!< Initial data PID\r
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
+\r
+  uint8_t   even_odd_frame;       /*!< IFrame parity\r
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
+\r
+  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number\r
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\r
+\r
+  uint32_t  maxpacket;            /*!< Endpoint Max packet size\r
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */\r
+\r
+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */\r
+\r
+  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */\r
+\r
+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */\r
+\r
+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */\r
+} USB_OTG_EPTypeDef;\r
+\r
+typedef struct\r
+{\r
+  uint8_t   dev_addr ;          /*!< USB device address.\r
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */\r
+\r
+  uint8_t   ch_num;             /*!< Host channel number.\r
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\r
+\r
+  uint8_t   ep_num;             /*!< Endpoint number.\r
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\r
+\r
+  uint8_t   ep_is_in;           /*!< Endpoint direction\r
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
+\r
+  uint8_t   speed;              /*!< USB Host speed.\r
+                                     This parameter can be any value of @ref USB_Core_Speed_                    */\r
+\r
+  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */\r
+\r
+  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */\r
+\r
+  uint8_t   ep_type;            /*!< Endpoint Type.\r
+                                     This parameter can be any value of @ref USB_EP_Type_                       */\r
+\r
+  uint16_t  max_packet;         /*!< Endpoint Max packet size.\r
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */\r
+\r
+  uint8_t   data_pid;           /*!< Initial data PID.\r
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
+\r
+  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */\r
+\r
+  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */\r
+\r
+  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */\r
+\r
+  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.\r
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
+\r
+  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag\r
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
+\r
+  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */\r
+\r
+  uint32_t  ErrCnt;             /*!< Host channel error count.*/\r
+\r
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.\r
+                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */\r
+\r
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.\r
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef   */\r
+} USB_OTG_HCTypeDef;\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+\r
+typedef enum\r
+{\r
+  USB_DEVICE_MODE  = 0\r
+} USB_ModeTypeDef;\r
+\r
+/**\r
+  * @brief  USB Initialization Structure definition\r
+  */\r
+typedef struct\r
+{\r
+  uint32_t dev_endpoints;           /*!< Device Endpoints number.\r
+                                         This parameter depends on the used USB core.\r
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r
+\r
+  uint32_t speed;                   /*!< USB Core speed.\r
+                                         This parameter can be any value of @ref USB_Core_Speed                 */\r
+\r
+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */\r
+\r
+  uint32_t phy_itface;              /*!< Select the used PHY interface.\r
+                                         This parameter can be any value of @ref USB_Core_PHY                   */\r
+\r
+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */\r
+\r
+  uint32_t low_power_enable;        /*!< Enable or disable Low Power mode                                       */\r
+\r
+  uint32_t lpm_enable;              /*!< Enable or disable Battery charging.                                    */\r
+\r
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */\r
+} USB_CfgTypeDef;\r
+\r
+typedef struct\r
+{\r
+  uint8_t   num;             /*!< Endpoint number\r
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 15    */\r
+\r
+  uint8_t   is_in;           /*!< Endpoint direction\r
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r
+\r
+  uint8_t   is_stall;        /*!< Endpoint stall condition\r
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r
+\r
+  uint8_t   type;            /*!< Endpoint type\r
+                                  This parameter can be any value of @ref USB_EP_Type                       */\r
+\r
+  uint8_t   data_pid_start;  /*!< Initial data PID\r
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r
+\r
+  uint16_t  pmaadress;       /*!< PMA Address\r
+                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */\r
+\r
+  uint16_t  pmaaddr0;        /*!< PMA Address0\r
+                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */\r
+\r
+  uint16_t  pmaaddr1;        /*!< PMA Address1\r
+                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */\r
+\r
+  uint8_t   doublebuffer;    /*!< Double buffer enable\r
+                                  This parameter can be 0 or 1                                              */\r
+\r
+  uint16_t  tx_fifo_num;     /*!< This parameter is not required by USB Device FS peripheral, it is used\r
+                                  only by USB OTG FS peripheral\r
+                                  This parameter is added to ensure compatibility across USB peripherals    */\r
+\r
+  uint32_t  maxpacket;       /*!< Endpoint Max packet size\r
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 64KB  */\r
+\r
+  uint8_t   *xfer_buff;      /*!< Pointer to transfer buffer                                                */\r
+\r
+  uint32_t  xfer_len;        /*!< Current transfer length                                                   */\r
+\r
+  uint32_t  xfer_count;      /*!< Partial transfer length in case of multi packet transfer                  */\r
+\r
+} USB_EPTypeDef;\r
+#endif /* defined (USB) */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PCD_Exported_Constants PCD Exported Constants\r
+  * @{\r
+  */\r
+\r
+#if defined (USB_OTG_FS)\r
+/** @defgroup USB_OTG_CORE VERSION ID\r
+  * @{\r
+  */\r
+#define USB_OTG_CORE_ID_300A          0x4F54300AU\r
+#define USB_OTG_CORE_ID_310A          0x4F54310AU\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_Core_Mode_ USB Core Mode\r
+  * @{\r
+  */\r
+#define USB_OTG_MODE_DEVICE                    0U\r
+#define USB_OTG_MODE_HOST                      1U\r
+#define USB_OTG_MODE_DRD                       2U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL Device Speed\r
+  * @{\r
+  */\r
+#define USBD_FS_SPEED               2U\r
+#define USBH_FS_SPEED               1U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed\r
+  * @{\r
+  */\r
+#define USB_OTG_SPEED_FULL                     3U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY\r
+  * @{\r
+  */\r
+#define USB_OTG_ULPI_PHY                       1U\r
+#define USB_OTG_EMBEDDED_PHY                   2U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value\r
+  * @{\r
+  */\r
+#ifndef USBD_FS_TRDT_VALUE\r
+#define USBD_FS_TRDT_VALUE           5U\r
+#define USBD_DEFAULT_TRDT_VALUE      9U\r
+#endif /* USBD_HS_TRDT_VALUE */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS\r
+  * @{\r
+  */\r
+#define USB_OTG_FS_MAX_PACKET_SIZE             64U\r
+#define USB_OTG_MAX_EP0_SIZE                   64U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency\r
+  * @{\r
+  */\r
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)\r
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)\r
+#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2U << 1)\r
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval\r
+  * @{\r
+  */\r
+#define DCFG_FRAME_INTERVAL_80                 0U\r
+#define DCFG_FRAME_INTERVAL_85                 1U\r
+#define DCFG_FRAME_INTERVAL_90                 2U\r
+#define DCFG_FRAME_INTERVAL_95                 3U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS\r
+  * @{\r
+  */\r
+#define DEP0CTL_MPS_64                         0U\r
+#define DEP0CTL_MPS_32                         1U\r
+#define DEP0CTL_MPS_16                         2U\r
+#define DEP0CTL_MPS_8                          3U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed\r
+  * @{\r
+  */\r
+#define EP_SPEED_LOW                           0U\r
+#define EP_SPEED_FULL                          1U\r
+#define EP_SPEED_HIGH                          2U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type\r
+  * @{\r
+  */\r
+#define EP_TYPE_CTRL                           0U\r
+#define EP_TYPE_ISOC                           1U\r
+#define EP_TYPE_BULK                           2U\r
+#define EP_TYPE_INTR                           3U\r
+#define EP_TYPE_MSK                            3U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines\r
+  * @{\r
+  */\r
+#define STS_GOUT_NAK                           1U\r
+#define STS_DATA_UPDT                          2U\r
+#define STS_XFER_COMP                          3U\r
+#define STS_SETUP_COMP                         4U\r
+#define STS_SETUP_UPDT                         6U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines\r
+  * @{\r
+  */\r
+#define HCFG_30_60_MHZ                         0U\r
+#define HCFG_48_MHZ                            1U\r
+#define HCFG_6_MHZ                             2U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines\r
+  * @{\r
+  */\r
+#define HPRT0_PRTSPD_HIGH_SPEED                0U\r
+#define HPRT0_PRTSPD_FULL_SPEED                1U\r
+#define HPRT0_PRTSPD_LOW_SPEED                 2U\r
+/**\r
+  * @}\r
+  */\r
+\r
+#define HCCHAR_CTRL                            0U\r
+#define HCCHAR_ISOC                            1U\r
+#define HCCHAR_BULK                            2U\r
+#define HCCHAR_INTR                            3U\r
+\r
+#define HC_PID_DATA0                           0U\r
+#define HC_PID_DATA2                           1U\r
+#define HC_PID_DATA1                           2U\r
+#define HC_PID_SETUP                           3U\r
+\r
+#define GRXSTS_PKTSTS_IN                       2U\r
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3U\r
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U\r
+#define GRXSTS_PKTSTS_CH_HALTED                7U\r
+\r
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)\r
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)\r
+\r
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))\r
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\r
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\r
+#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))\r
+\r
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))\r
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS\r
+  * @{\r
+  */\r
+#define DEP0CTL_MPS_64                         0U\r
+#define DEP0CTL_MPS_32                         1U\r
+#define DEP0CTL_MPS_16                         2U\r
+#define DEP0CTL_MPS_8                          3U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type\r
+  * @{\r
+  */\r
+#define EP_TYPE_CTRL                           0U\r
+#define EP_TYPE_ISOC                           1U\r
+#define EP_TYPE_BULK                           2U\r
+#define EP_TYPE_INTR                           3U\r
+#define EP_TYPE_MSK                            3U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USB_LL Device Speed\r
+  * @{\r
+  */\r
+#define USBD_FS_SPEED                          2U\r
+/**\r
+  * @}\r
+  */\r
+\r
+#define BTABLE_ADDRESS                         0x000U\r
+#define PMA_ACCESS                             1U\r
+#endif /* defined (USB) */\r
+#if defined (USB_OTG_FS)\r
+#define EP_ADDR_MSK                            0xFU\r
+#endif /* defined (USB_OTG_FS) */\r
+#if defined (USB)\r
+#define EP_ADDR_MSK                            0x7U\r
+#endif /* defined (USB) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros\r
+  * @{\r
+  */\r
+#if defined (USB_OTG_FS)\r
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))\r
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))\r
+\r
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))\r
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))\r
+#endif /* defined (USB_OTG_FS) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions\r
+  * @{\r
+  */\r
+#if defined (USB_OTG_FS)\r
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode);\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);\r
+void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);\r
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);\r
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);\r
+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);\r
+uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);\r
+void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);\r
+\r
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);\r
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);\r
+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,\r
+                              uint8_t ch_num,\r
+                              uint8_t epnum,\r
+                              uint8_t dev_address,\r
+                              uint8_t speed,\r
+                              uint8_t ep_type,\r
+                              uint16_t mps);\r
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);\r
+uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);\r
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);\r
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);\r
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);\r
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);\r
+void             *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);\r
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);\r
+HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);\r
+HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);\r
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);\r
+uint32_t          USB_ReadInterrupts(USB_TypeDef *USBx);\r
+uint32_t          USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);\r
+uint32_t          USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);\r
+uint32_t          USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);\r
+uint32_t          USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);\r
+void              USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);\r
+\r
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);\r
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);\r
+void USB_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);\r
+void USB_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);\r
+#endif /* defined (USB) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* defined (USB) || defined (USB_OTG_FS) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32L4xx_LL_USB_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
new file mode 100644 (file)
index 0000000..1f8e5c5
--- /dev/null
@@ -0,0 +1,758 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal.c\r
+  * @author  MCD Application Team\r
+  * @brief   HAL module driver.\r
+  *          This is the common part of the HAL initialization\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                     ##### How to use this driver #####\r
+  ==============================================================================\r
+    [..]\r
+    The common HAL driver contains a set of generic and common APIs that can be\r
+    used by the PPP peripheral drivers and the user to start using the HAL.\r
+    [..]\r
+    The HAL contains two APIs' categories:\r
+         (+) Common HAL APIs\r
+         (+) Services HAL APIs\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup HAL HAL\r
+  * @brief HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/**\r
+ * @brief STM32L4xx HAL Driver version number\r
+   */\r
+#define STM32L4XX_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */\r
+#define STM32L4XX_HAL_VERSION_SUB1   (0x0AU) /*!< [23:16] sub1 version */\r
+#define STM32L4XX_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */\r
+#define STM32L4XX_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\r
+#define STM32L4XX_HAL_VERSION        ((STM32L4XX_HAL_VERSION_MAIN  << 24U)\\r
+                                      |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\\r
+                                      |(STM32L4XX_HAL_VERSION_SUB2 << 8U)\\r
+                                      |(STM32L4XX_HAL_VERSION_RC))\r
+\r
+#if defined(VREFBUF)\r
+#define VREFBUF_TIMEOUT_VALUE     10U   /* 10 ms (to be confirmed) */\r
+#endif /* VREFBUF */\r
+\r
+/* ------------ SYSCFG registers bit address in the alias region ------------ */\r
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)\r
+/* ---  MEMRMP Register ---*/\r
+/* Alias word address of FB_MODE bit */\r
+#define MEMRMP_OFFSET             SYSCFG_OFFSET\r
+#define FB_MODE_BitNumber         8U\r
+#define FB_MODE_BB                (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U))\r
+\r
+/* --- SCSR Register ---*/\r
+/* Alias word address of SRAM2ER bit */\r
+#define SCSR_OFFSET               (SYSCFG_OFFSET + 0x18U)\r
+#define BRER_BitNumber            0U\r
+#define SCSR_SRAM2ER_BB           (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U))\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Variables HAL Exported Variables\r
+  * @{\r
+  */\r
+__IO uint32_t uwTick;\r
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */\r
+uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Functions HAL Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions\r
+ *  @brief    Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+              ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Initialize the Flash interface, the NVIC allocation and initial time base\r
+          clock configuration.\r
+      (+) De-initialize common part of the HAL.\r
+      (+) Configure the time base source to have 1ms time base with a dedicated\r
+          Tick interrupt priority.\r
+        (++) SysTick timer is used by default as source of time base, but user\r
+             can eventually implement his proper time base source (a general purpose\r
+             timer for example or other time source), keeping in mind that Time base\r
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and\r
+             handled in milliseconds basis.\r
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically\r
+             at the beginning of the program after reset by HAL_Init() or at any time\r
+             when clock is configured, by HAL_RCC_ClockConfig().\r
+        (++) Source of time base is configured  to generate interrupts at regular\r
+             time intervals. Care must be taken if HAL_Delay() is called from a\r
+             peripheral ISR process, the Tick interrupt line must have higher priority\r
+            (numerically lower) than the peripheral interrupt. Otherwise the caller\r
+            ISR process will be blocked.\r
+       (++) functions affecting time base configurations are declared as __weak\r
+             to make  override possible  in case of other  implementations in user file.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Configure the Flash prefetch, the Instruction and Data caches,\r
+  *         the time base source, NVIC and any required global low level hardware\r
+  *         by calling the HAL_MspInit() callback function to be optionally defined in user file\r
+  *         stm32l4xx_hal_msp.c.\r
+  *\r
+  * @note   HAL_Init() function is called at the beginning of program after reset and before\r
+  *         the clock configuration.\r
+  *\r
+  * @note   In the default implementation the System Timer (Systick) is used as source of time base.\r
+  *         The Systick configuration is based on MSI clock, as MSI is the clock\r
+  *         used after a system Reset and the NVIC configuration is set to Priority group 4.\r
+  *         Once done, time base tick starts incrementing: the tick variable counter is incremented\r
+  *         each 1ms in the SysTick_Handler() interrupt handler.\r
+  *\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_Init(void)\r
+{\r
+  HAL_StatusTypeDef  status = HAL_OK;\r
+\r
+  /* Configure Flash prefetch, Instruction cache, Data cache */\r
+  /* Default configuration at reset is:                      */\r
+  /* - Prefetch disabled                                     */\r
+  /* - Instruction cache enabled                             */\r
+  /* - Data cache enabled                                    */\r
+#if (INSTRUCTION_CACHE_ENABLE == 0)\r
+   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
+#endif /* INSTRUCTION_CACHE_ENABLE */\r
+\r
+#if (DATA_CACHE_ENABLE == 0)\r
+   __HAL_FLASH_DATA_CACHE_DISABLE();\r
+#endif /* DATA_CACHE_ENABLE */\r
+\r
+#if (PREFETCH_ENABLE != 0)\r
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\r
+#endif /* PREFETCH_ENABLE */\r
+\r
+  /* Set Interrupt Group Priority */\r
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
+\r
+  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */\r
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Init the low level hardware */\r
+    HAL_MspInit();\r
+  }\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief De-initialize common part of the HAL and stop the source of time base.\r
+  * @note This function is optional.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DeInit(void)\r
+{\r
+  /* Reset of all peripherals */\r
+  __HAL_RCC_APB1_FORCE_RESET();\r
+  __HAL_RCC_APB1_RELEASE_RESET();\r
+\r
+  __HAL_RCC_APB2_FORCE_RESET();\r
+  __HAL_RCC_APB2_RELEASE_RESET();\r
+\r
+  __HAL_RCC_AHB1_FORCE_RESET();\r
+  __HAL_RCC_AHB1_RELEASE_RESET();\r
+\r
+  __HAL_RCC_AHB2_FORCE_RESET();\r
+  __HAL_RCC_AHB2_RELEASE_RESET();\r
+\r
+  __HAL_RCC_AHB3_FORCE_RESET();\r
+  __HAL_RCC_AHB3_RELEASE_RESET();\r
+\r
+  /* De-Init the low level hardware */\r
+  HAL_MspDeInit();\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initialize the MSP.\r
+  * @retval None\r
+  */\r
+__weak void HAL_MspInit(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitialize the MSP.\r
+  * @retval None\r
+  */\r
+__weak void HAL_MspDeInit(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief This function configures the source of the time base:\r
+  *        The time source is configured to have 1ms time base with a dedicated\r
+  *        Tick interrupt priority.\r
+  * @note This function is called  automatically at the beginning of program after\r
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().\r
+  * @note In the default implementation, SysTick timer is the source of time base.\r
+  *       It is used to generate interrupts at regular time intervals.\r
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,\r
+  *       The SysTick interrupt must have higher priority (numerically lower)\r
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
+  *       The function is declared as __weak  to be overwritten  in case of other\r
+  *       implementation  in user file.\r
+  * @param TickPriority  Tick interrupt priority.\r
+  * @retval HAL status\r
+  */\r
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+  HAL_StatusTypeDef  status = HAL_OK;\r
+\r
+  if (uwTickFreq != 0U)\r
+  {\r
+    /*Configure the SysTick to have interrupt in 1ms time basis*/\r
+    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)\r
+    {\r
+      /* Configure the SysTick IRQ priority */\r
+      if (TickPriority < (1UL << __NVIC_PRIO_BITS))\r
+      {\r
+        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\r
+        uwTickPrio = TickPriority;\r
+      }\r
+      else\r
+      {\r
+        status = HAL_ERROR;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions\r
+ *  @brief    HAL Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### HAL Control functions #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Provide a tick value in millisecond\r
+      (+) Provide a blocking delay in millisecond\r
+      (+) Suspend the time base source interrupt\r
+      (+) Resume the time base source interrupt\r
+      (+) Get the HAL API driver version\r
+      (+) Get the device identifier\r
+      (+) Get the device revision identifier\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief This function is called to increment a global variable "uwTick"\r
+  *        used as application time base.\r
+  * @note In the default implementation, this variable is incremented each 1ms\r
+  *       in SysTick ISR.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+  *      implementations in user file.\r
+  * @retval None\r
+  */\r
+__weak void HAL_IncTick(void)\r
+{\r
+  uwTick += uwTickFreq;\r
+}\r
+\r
+/**\r
+  * @brief Provide a tick value in millisecond.\r
+  * @note This function is declared as __weak to be overwritten in case of other\r
+  *       implementations in user file.\r
+  * @retval tick value\r
+  */\r
+__weak uint32_t HAL_GetTick(void)\r
+{\r
+  return uwTick;\r
+}\r
+\r
+/**\r
+  * @brief This function returns a tick priority.\r
+  * @retval tick priority\r
+  */\r
+uint32_t HAL_GetTickPrio(void)\r
+{\r
+  return uwTickPrio;\r
+}\r
+\r
+/**\r
+  * @brief Set new tick Freq.\r
+  * @param Freq tick frequency\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)\r
+{\r
+  HAL_StatusTypeDef status  = HAL_OK;\r
+  assert_param(IS_TICKFREQ(Freq));\r
+\r
+  if (uwTickFreq != Freq)\r
+  {\r
+    /* Apply the new tick Freq  */\r
+    status = HAL_InitTick(uwTickPrio);\r
+    if (status == HAL_OK)\r
+    {\r
+      uwTickFreq = Freq;\r
+    }\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief Return tick frequency.\r
+  * @retval tick period in Hz\r
+  */\r
+uint32_t HAL_GetTickFreq(void)\r
+{\r
+  return uwTickFreq;\r
+}\r
+\r
+/**\r
+  * @brief This function provides minimum delay (in milliseconds) based\r
+  *        on variable incremented.\r
+  * @note In the default implementation , SysTick timer is the source of time base.\r
+  *       It is used to generate interrupts at regular time intervals where uwTick\r
+  *       is incremented.\r
+  * @note This function is declared as __weak to be overwritten in case of other\r
+  *       implementations in user file.\r
+  * @param Delay  specifies the delay time length, in milliseconds.\r
+  * @retval None\r
+  */\r
+__weak void HAL_Delay(uint32_t Delay)\r
+{\r
+  uint32_t tickstart = HAL_GetTick();\r
+  uint32_t wait = Delay;\r
+\r
+  /* Add a period to guaranty minimum wait */\r
+  if (wait < HAL_MAX_DELAY)\r
+  {\r
+    wait += (uint32_t)(uwTickFreq);\r
+  }\r
+\r
+  while((HAL_GetTick() - tickstart) < wait)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Suspend Tick increment.\r
+  * @note In the default implementation , SysTick timer is the source of time base. It is\r
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
+  *       is called, the SysTick interrupt will be disabled and so Tick increment\r
+  *       is suspended.\r
+  * @note This function is declared as __weak to be overwritten in case of other\r
+  *       implementations in user file.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SuspendTick(void)\r
+{\r
+  /* Disable SysTick Interrupt */\r
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+  * @brief Resume Tick increment.\r
+  * @note In the default implementation , SysTick timer is the source of time base. It is\r
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
+  *       is called, the SysTick interrupt will be enabled and so Tick increment\r
+  *       is resumed.\r
+  * @note This function is declared as __weak to be overwritten in case of other\r
+  *       implementations in user file.\r
+  * @retval None\r
+  */\r
+__weak void HAL_ResumeTick(void)\r
+{\r
+  /* Enable SysTick Interrupt */\r
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+  * @brief  Return the HAL revision.\r
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r
+  */\r
+uint32_t HAL_GetHalVersion(void)\r
+{\r
+  return STM32L4XX_HAL_VERSION;\r
+}\r
+\r
+/**\r
+  * @brief  Return the device revision identifier.\r
+  * @retval Device revision identifier\r
+  */\r
+uint32_t HAL_GetREVID(void)\r
+{\r
+  return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);\r
+}\r
+\r
+/**\r
+  * @brief  Return the device identifier.\r
+  * @retval Device identifier\r
+  */\r
+uint32_t HAL_GetDEVID(void)\r
+{\r
+  return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);\r
+}\r
+\r
+/**\r
+  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)\r
+  * @retval Device identifier\r
+  */\r
+uint32_t HAL_GetUIDw0(void)\r
+{\r
+  return(READ_REG(*((uint32_t *)UID_BASE)));\r
+}\r
+\r
+/**\r
+  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)\r
+  * @retval Device identifier\r
+  */\r
+uint32_t HAL_GetUIDw1(void)\r
+{\r
+  return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));\r
+}\r
+\r
+/**\r
+  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)\r
+  * @retval Device identifier\r
+  */\r
+uint32_t HAL_GetUIDw2(void)\r
+{\r
+  return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions\r
+ *  @brief    HAL Debug functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### HAL Debug functions #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Enable/Disable Debug module during SLEEP mode\r
+      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes\r
+      (+) Enable/Disable Debug module during STANDBY mode\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Enable the Debug Module during SLEEP mode.\r
+  * @retval None\r
+  */\r
+void HAL_DBGMCU_EnableDBGSleepMode(void)\r
+{\r
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+  * @brief  Disable the Debug Module during SLEEP mode.\r
+  * @retval None\r
+  */\r
+void HAL_DBGMCU_DisableDBGSleepMode(void)\r
+{\r
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+  * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.\r
+  * @retval None\r
+  */\r
+void HAL_DBGMCU_EnableDBGStopMode(void)\r
+{\r
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+  * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.\r
+  * @retval None\r
+  */\r
+void HAL_DBGMCU_DisableDBGStopMode(void)\r
+{\r
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+  * @brief  Enable the Debug Module during STANDBY mode.\r
+  * @retval None\r
+  */\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void)\r
+{\r
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+  * @brief  Disable the Debug Module during STANDBY mode.\r
+  * @retval None\r
+  */\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void)\r
+{\r
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions\r
+ *  @brief    HAL SYSCFG configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### HAL SYSCFG configuration functions #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Start a hardware SRAM2 erase operation\r
+      (+) Enable/Disable the Internal FLASH Bank Swapping\r
+      (+) Configure the Voltage reference buffer\r
+      (+) Enable/Disable the Voltage reference buffer\r
+      (+) Enable/Disable the I/O analog switch voltage booster\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Start a hardware SRAM2 erase operation.\r
+  * @note   As long as SRAM2 is not erased the SRAM2ER bit will be set.\r
+  *         This bit is automatically reset at the end of the SRAM2 erase operation.\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_SRAM2Erase(void)\r
+{\r
+  /* unlock the write protection of the SRAM2ER bit */\r
+  SYSCFG->SKR = 0xCA;\r
+  SYSCFG->SKR = 0x53;\r
+  /* Starts a hardware SRAM2 erase operation*/\r
+  *(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL;\r
+}\r
+\r
+/**\r
+  * @brief  Enable the Internal FLASH Bank Swapping.\r
+  *\r
+  * @note   This function can be used only for STM32L4xx devices.\r
+  *\r
+  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)\r
+  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)\r
+  *\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_EnableMemorySwappingBank(void)\r
+{\r
+  *(__IO uint32_t *)FB_MODE_BB = 0x00000001UL;\r
+}\r
+\r
+/**\r
+  * @brief  Disable the Internal FLASH Bank Swapping.\r
+  *\r
+  * @note   This function can be used only for STM32L4xx devices.\r
+  *\r
+  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)\r
+  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)\r
+  *\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_DisableMemorySwappingBank(void)\r
+{\r
+\r
+  *(__IO uint32_t *)FB_MODE_BB = 0x00000000UL;\r
+}\r
+\r
+#if defined(VREFBUF)\r
+/**\r
+  * @brief Configure the internal voltage reference buffer voltage scale.\r
+  * @param VoltageScaling  specifies the output voltage to achieve\r
+  *          This parameter can be one of the following values:\r
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.\r
+  *                                                This requires VDDA equal to or higher than 2.4 V.\r
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.\r
+  *                                                This requires VDDA equal to or higher than 2.8 V.\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));\r
+\r
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);\r
+}\r
+\r
+/**\r
+  * @brief Configure the internal voltage reference buffer high impedance mode.\r
+  * @param Mode  specifies the high impedance mode\r
+  *          This parameter can be one of the following values:\r
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.\r
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));\r
+\r
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);\r
+}\r
+\r
+/**\r
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));\r
+\r
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);\r
+}\r
+\r
+/**\r
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).\r
+  * @retval HAL_OK/HAL_TIMEOUT\r
+  */\r
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)\r
+{\r
+  uint32_t  tickstart;\r
+\r
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\r
+\r
+  /* Get Start Tick*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait for VRR bit  */\r
+  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)\r
+  {\r
+    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).\r
+  *\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_DisableVREFBUF(void)\r
+{\r
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\r
+}\r
+#endif /* VREFBUF */\r
+\r
+/**\r
+  * @brief  Enable the I/O analog switch voltage booster\r
+  *\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)\r
+{\r
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);\r
+}\r
+\r
+/**\r
+  * @brief  Disable the I/O analog switch voltage booster\r
+  *\r
+  * @retval None\r
+  */\r
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)\r
+{\r
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
new file mode 100644 (file)
index 0000000..8080ad0
--- /dev/null
@@ -0,0 +1,523 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_cortex.c\r
+  * @author  MCD Application Team\r
+  * @brief   CORTEX HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the CORTEX:\r
+  *           + Initialization and Configuration functions\r
+  *           + Peripheral Control functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                        ##### How to use this driver #####\r
+  ==============================================================================\r
+\r
+    [..]\r
+    *** How to configure Interrupts using CORTEX HAL driver ***\r
+    ===========================================================\r
+    [..]\r
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).\r
+    The Cortex-M4 exceptions are managed by CMSIS functions.\r
+\r
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.\r
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().\r
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r
+\r
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.\r
+         The pending IRQ priority will be managed only by the sub priority.\r
+\r
+     -@- IRQ priority order (sorted by highest to lowest priority):\r
+        (+@) Lowest pre-emption priority\r
+        (+@) Lowest sub priority\r
+        (+@) Lowest hardware priority (IRQ number)\r
+\r
+    [..]\r
+    *** How to configure SysTick using CORTEX HAL driver ***\r
+    ========================================================\r
+    [..]\r
+    Setup SysTick Timer for time base.\r
+\r
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r
+       is a CMSIS function that:\r
+        (++) Configures the SysTick Reload register with value passed as function parameter.\r
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r
+        (++) Resets the SysTick Counter register.\r
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
+        (++) Enables the SysTick Interrupt.\r
+        (++) Starts the SysTick Counter.\r
+\r
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r
+       inside the stm32l4xx_hal_cortex.h file.\r
+\r
+   (+) You can change the SysTick IRQ priority by calling the\r
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function\r
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
+\r
+   (+) To adjust the SysTick time base, use the following formula:\r
+\r
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)\r
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
+       (++) Reload Value should not exceed 0xFFFFFF\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+\r
+  The table below gives the allowed values of the pre-emption priority and subpriority according\r
+  to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.\r
+\r
+    ==========================================================================================================================\r
+      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description\r
+    ==========================================================================================================================\r
+     NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority\r
+                           |                                   |                             | 4 bits for subpriority\r
+    --------------------------------------------------------------------------------------------------------------------------\r
+     NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority\r
+                           |                                   |                             | 3 bits for subpriority\r
+    --------------------------------------------------------------------------------------------------------------------------\r
+     NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority\r
+                           |                                   |                             | 2 bits for subpriority\r
+    --------------------------------------------------------------------------------------------------------------------------\r
+     NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority\r
+                           |                                   |                             | 1 bit for subpriority\r
+    --------------------------------------------------------------------------------------------------------------------------\r
+     NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority\r
+                           |                                   |                             | 0 bit for subpriority\r
+    ==========================================================================================================================\r
+\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup CORTEX\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup CORTEX_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group1\r
+ *  @brief    Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+              ##### Initialization and Configuration functions #####\r
+  ==============================================================================\r
+    [..]\r
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r
+      SysTick functionalities\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+\r
+/**\r
+  * @brief  Set the priority grouping field (pre-emption priority and subpriority)\r
+  *         using the required unlock sequence.\r
+  * @param  PriorityGroup: The priority grouping bits length.\r
+  *         This parameter can be one of the following values:\r
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,\r
+  *                                    4 bits for subpriority\r
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,\r
+  *                                    3 bits for subpriority\r
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,\r
+  *                                    2 bits for subpriority\r
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,\r
+  *                                    1 bit  for subpriority\r
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,\r
+  *                                    0 bit  for subpriority\r
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.\r
+  *         The pending IRQ priority will be managed only by the subpriority.\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+\r
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
+  NVIC_SetPriorityGrouping(PriorityGroup);\r
+}\r
+\r
+/**\r
+  * @brief  Set the priority of an interrupt.\r
+  * @param  IRQn: External interrupt number.\r
+  *         This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.\r
+  *         This parameter can be a value between 0 and 15\r
+  *         A lower priority value indicates a higher priority\r
+  * @param  SubPriority: the subpriority level for the IRQ channel.\r
+  *         This parameter can be a value between 0 and 15\r
+  *         A lower priority value indicates a higher priority.\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t prioritygroup = 0x00;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
+\r
+  prioritygroup = NVIC_GetPriorityGrouping();\r
+\r
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
+}\r
+\r
+/**\r
+  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.\r
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+  *         function should be called before.\r
+  * @param  IRQn External interrupt number.\r
+  *         This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+  /* Enable interrupt */\r
+  NVIC_EnableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.\r
+  * @param  IRQn External interrupt number.\r
+  *         This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+  /* Disable interrupt */\r
+  NVIC_DisableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+  * @brief  Initiate a system reset request to reset the MCU.\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_SystemReset(void)\r
+{\r
+  /* System Reset */\r
+  NVIC_SystemReset();\r
+}\r
+\r
+/**\r
+  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):\r
+  *         Counter is in free running mode to generate periodic interrupts.\r
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.\r
+  * @retval status:  - 0  Function succeeded.\r
+  *                  - 1  Function failed.\r
+  */\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
+{\r
+   return SysTick_Config(TicksNumb);\r
+}\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group2\r
+ *  @brief   Cortex control functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+                      ##### Peripheral Control functions #####\r
+  ==============================================================================\r
+    [..]\r
+      This subsection provides a set of functions allowing to control the CORTEX\r
+      (NVIC, SYSTICK, MPU) functionalities.\r
+\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Get the priority grouping field from the NVIC Interrupt Controller.\r
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
+  */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
+{\r
+  /* Get the PRIGROUP[10:8] field value */\r
+  return NVIC_GetPriorityGrouping();\r
+}\r
+\r
+/**\r
+  * @brief  Get the priority of an interrupt.\r
+  * @param  IRQn: External interrupt number.\r
+  *         This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @param   PriorityGroup: the priority grouping bits length.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,\r
+  *                                      4 bits for subpriority\r
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,\r
+  *                                      3 bits for subpriority\r
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,\r
+  *                                      2 bits for subpriority\r
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,\r
+  *                                      1 bit for subpriority\r
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,\r
+  *                                      0 bit for subpriority\r
+  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).\r
+  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ /* Get priority for Cortex-M system or device specific interrupts */\r
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
+}\r
+\r
+/**\r
+  * @brief  Set Pending bit of an external interrupt.\r
+  * @param  IRQn External interrupt number\r
+  *         This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+  /* Set interrupt pending */\r
+  NVIC_SetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+  * @brief  Get Pending Interrupt (read the pending register in the NVIC\r
+  *         and return the pending bit for the specified interrupt).\r
+  * @param  IRQn External interrupt number.\r
+  *          This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @retval status: - 0  Interrupt status is not pending.\r
+  *                 - 1  Interrupt status is pending.\r
+  */\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+  /* Return 1 if pending else 0 */\r
+  return NVIC_GetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+  * @brief  Clear the pending bit of an external interrupt.\r
+  * @param  IRQn External interrupt number.\r
+  *         This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @retval None\r
+  */\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+  /* Clear pending interrupt */\r
+  NVIC_ClearPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+  * @brief Get active interrupt (read the active register in NVIC and return the active bit).\r
+  * @param IRQn External interrupt number\r
+  *         This parameter can be an enumerator of IRQn_Type enumeration\r
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
+  * @retval status: - 0  Interrupt status is not pending.\r
+  *                 - 1  Interrupt status is pending.\r
+  */\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  /* Return 1 if active else 0 */\r
+  return NVIC_GetActive(IRQn);\r
+}\r
+\r
+/**\r
+  * @brief  Configure the SysTick clock source.\r
+  * @param  CLKSource: specifies the SysTick clock source.\r
+  *          This parameter can be one of the following values:\r
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
+  * @retval None\r
+  */\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
+  {\r
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
+  }\r
+  else\r
+  {\r
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Handle SYSTICK interrupt request.\r
+  * @retval None\r
+  */\r
+void HAL_SYSTICK_IRQHandler(void)\r
+{\r
+  HAL_SYSTICK_Callback();\r
+}\r
+\r
+/**\r
+  * @brief  SYSTICK callback.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SYSTICK_Callback(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SYSTICK_Callback could be implemented in the user file\r
+   */\r
+}\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+  * @brief  Disable the MPU.\r
+  * @retval None\r
+  */\r
+void HAL_MPU_Disable(void)\r
+{\r
+  /* Make sure outstanding transfers are done */\r
+  __DMB();\r
+\r
+  /* Disable fault exceptions */\r
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+\r
+  /* Disable the MPU and clear the control register*/\r
+  MPU->CTRL = 0U;\r
+}\r
+\r
+/**\r
+  * @brief  Enable the MPU.\r
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,\r
+  *          NMI, FAULTMASK and privileged accessto the default memory\r
+  *          This parameter can be one of the following values:\r
+  *            @arg MPU_HFNMI_PRIVDEF_NONE\r
+  *            @arg MPU_HARDFAULT_NMI\r
+  *            @arg MPU_PRIVILEGED_DEFAULT\r
+  *            @arg MPU_HFNMI_PRIVDEF\r
+  * @retval None\r
+  */\r
+void HAL_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+  /* Enable the MPU */\r
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+\r
+  /* Enable fault exceptions */\r
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+\r
+  /* Ensure MPU settings take effects */\r
+  __DSB();\r
+  __ISB();\r
+}\r
+\r
+/**\r
+  * @brief  Initialize and configure the Region and the memory to be protected.\r
+  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains\r
+  *                the initialization and configuration information.\r
+  * @retval None\r
+  */\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
+\r
+  /* Set the Region number */\r
+  MPU->RNR = MPU_Init->Number;\r
+\r
+  if ((MPU_Init->Enable) != RESET)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
+\r
+    MPU->RBAR = MPU_Init->BaseAddress;\r
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |\r
+                ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |\r
+                ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |\r
+                ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |\r
+                ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |\r
+                ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |\r
+                ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |\r
+                ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |\r
+                ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);\r
+  }\r
+  else\r
+  {\r
+    MPU->RBAR = 0x00;\r
+    MPU->RASR = 0x00;\r
+  }\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c
new file mode 100644 (file)
index 0000000..5675a39
--- /dev/null
@@ -0,0 +1,3590 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_dfsdm.c\r
+  * @author  MCD Application Team\r
+  * @brief   This file provides firmware functions to manage the following\r
+  *          functionalities of the Digital Filter for Sigma-Delta Modulators\r
+  *          (DFSDM) peripherals:\r
+  *           + Initialization and configuration of channels and filters\r
+  *           + Regular channels configuration\r
+  *           + Injected channels configuration\r
+  *           + Regular/Injected Channels DMA Configuration\r
+  *           + Interrupts and flags management\r
+  *           + Analog watchdog feature\r
+  *           + Short-circuit detector feature\r
+  *           + Extremes detector feature\r
+  *           + Clock absence detector feature\r
+  *           + Break generation on analog watchdog or short-circuit event\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                     ##### How to use this driver #####\r
+  ==============================================================================\r
+  [..]\r
+    *** Channel initialization ***\r
+    ==============================\r
+    [..]\r
+      (#) User has first to initialize channels (before filters initialization).\r
+      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :\r
+        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().\r
+        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
+        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().\r
+        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global\r
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+      (#) Configure the output clock, input, serial interface, analog watchdog,\r
+          offset and data right bit shift parameters for this channel using the\r
+          HAL_DFSDM_ChannelInit() function.\r
+\r
+    *** Channel clock absence detector ***\r
+    ======================================\r
+    [..]\r
+      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or\r
+          HAL_DFSDM_ChannelCkabStart_IT().\r
+      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock\r
+          absence.\r
+      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if\r
+          clock absence is detected.\r
+      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or\r
+          HAL_DFSDM_ChannelCkabStop_IT().\r
+      (#) Please note that the same mode (polling or interrupt) has to be used\r
+          for all channels because the channels are sharing the same interrupt.\r
+      (#) Please note also that in interrupt mode, if clock absence detector is\r
+          stopped for one channel, interrupt will be disabled for all channels.\r
+\r
+    *** Channel short circuit detector ***\r
+    ======================================\r
+    [..]\r
+      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or\r
+          or HAL_DFSDM_ChannelScdStart_IT().\r
+      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short\r
+          circuit.\r
+      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if\r
+          short circuit is detected.\r
+      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or\r
+          or HAL_DFSDM_ChannelScdStop_IT().\r
+      (#) Please note that the same mode (polling or interrupt) has to be used\r
+          for all channels because the channels are sharing the same interrupt.\r
+      (#) Please note also that in interrupt mode, if short circuit detector is\r
+          stopped for one channel, interrupt will be disabled for all channels.\r
+\r
+    *** Channel analog watchdog value ***\r
+    =====================================\r
+    [..]\r
+      (#) Get analog watchdog filter value of a channel using\r
+          HAL_DFSDM_ChannelGetAwdValue().\r
+\r
+    *** Channel offset value ***\r
+    =====================================\r
+    [..]\r
+      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().\r
+\r
+    *** Filter initialization ***\r
+    =============================\r
+    [..]\r
+      (#) After channel initialization, user has to init filters.\r
+      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :\r
+        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global\r
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+            Please note that DFSDMz_FLT0 global interrupt could be already\r
+            enabled if interrupt is used for channel.\r
+        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it\r
+            with DFSDMz filter handle using __HAL_LINKDMA().\r
+      (#) Configure the regular conversion, injected conversion and filter\r
+          parameters for this filter using the HAL_DFSDM_FilterInit() function.\r
+\r
+    *** Filter regular channel conversion ***\r
+    =========================================\r
+    [..]\r
+      (#) Select regular channel and enable/disable continuous mode using\r
+          HAL_DFSDM_FilterConfigRegChannel().\r
+      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),\r
+          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or\r
+          HAL_DFSDM_FilterRegularMsbStart_DMA().\r
+      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect\r
+          the end of regular conversion.\r
+      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called\r
+          at the end of regular conversion.\r
+      (#) Get value of regular conversion and corresponding channel using\r
+          HAL_DFSDM_FilterGetRegularValue().\r
+      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and\r
+          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the\r
+          half transfer and at the transfer complete. Please note that\r
+          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA\r
+          circular mode.\r
+      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),\r
+          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().\r
+\r
+    *** Filter injected channels conversion ***\r
+    ===========================================\r
+    [..]\r
+      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().\r
+      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),\r
+          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or\r
+          HAL_DFSDM_FilterInjectedMsbStart_DMA().\r
+      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect\r
+          the end of injected conversion.\r
+      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called\r
+          at the end of injected conversion.\r
+      (#) Get value of injected conversion and corresponding channel using\r
+          HAL_DFSDM_FilterGetInjectedValue().\r
+      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and\r
+          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the\r
+          half transfer and at the transfer complete. Please note that\r
+          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA\r
+          circular mode.\r
+      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),\r
+          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().\r
+\r
+    *** Filter analog watchdog ***\r
+    ==============================\r
+    [..]\r
+      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().\r
+      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.\r
+      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().\r
+\r
+    *** Filter extreme detector ***\r
+    ===============================\r
+    [..]\r
+      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().\r
+      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().\r
+      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().\r
+      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().\r
+\r
+    *** Filter conversion time ***\r
+    ==============================\r
+    [..]\r
+      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().\r
+\r
+    *** Callback registration ***\r
+    =============================\r
+    [..]\r
+    The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1\r
+    allows the user to configure dynamically the driver callbacks.\r
+    Use functions HAL_DFSDM_Channel_RegisterCallback(),\r
+    HAL_DFSDM_Filter_RegisterCallback() or\r
+    HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.\r
+\r
+    [..]\r
+    Function HAL_DFSDM_Channel_RegisterCallback() allows to register\r
+    following callbacks:\r
+      (+) CkabCallback      : DFSDM channel clock absence detection callback.\r
+      (+) ScdCallback       : DFSDM channel short circuit detection callback.\r
+      (+) MspInitCallback   : DFSDM channel MSP init callback.\r
+      (+) MspDeInitCallback : DFSDM channel MSP de-init callback.\r
+    [..]\r
+    This function takes as parameters the HAL peripheral handle, the Callback ID\r
+    and a pointer to the user callback function.\r
+\r
+    [..]\r
+    Function HAL_DFSDM_Filter_RegisterCallback() allows to register\r
+    following callbacks:\r
+      (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.\r
+      (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.\r
+      (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.\r
+      (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.\r
+      (+) ErrorCallback           : DFSDM filter error callback.\r
+      (+) MspInitCallback         : DFSDM filter MSP init callback.\r
+      (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.\r
+    [..]\r
+    This function takes as parameters the HAL peripheral handle, the Callback ID\r
+    and a pointer to the user callback function.\r
+\r
+    [..]\r
+    For specific DFSDM filter analog watchdog callback use dedicated register callback:\r
+    HAL_DFSDM_Filter_RegisterAwdCallback().\r
+\r
+    [..]\r
+    Use functions HAL_DFSDM_Channel_UnRegisterCallback() or\r
+    HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default\r
+    weak function.\r
+\r
+    [..]\r
+    HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
+    and the Callback ID.\r
+    [..]\r
+    This function allows to reset following callbacks:\r
+      (+) CkabCallback      : DFSDM channel clock absence detection callback.\r
+      (+) ScdCallback       : DFSDM channel short circuit detection callback.\r
+      (+) MspInitCallback   : DFSDM channel MSP init callback.\r
+      (+) MspDeInitCallback : DFSDM channel MSP de-init callback.\r
+\r
+    [..]\r
+    HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
+    and the Callback ID.\r
+    [..]\r
+    This function allows to reset following callbacks:\r
+      (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.\r
+      (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.\r
+      (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.\r
+      (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.\r
+      (+) ErrorCallback           : DFSDM filter error callback.\r
+      (+) MspInitCallback         : DFSDM filter MSP init callback.\r
+      (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.\r
+\r
+    [..]\r
+    For specific DFSDM filter analog watchdog callback use dedicated unregister callback:\r
+    HAL_DFSDM_Filter_UnRegisterAwdCallback().\r
+\r
+    [..]\r
+    By default, after the call of init function and if the state is RESET\r
+    all callbacks are reset to the corresponding legacy weak functions:\r
+    examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().\r
+    Exception done for MspInit and MspDeInit callbacks that are respectively\r
+    reset to the legacy weak functions in the init and de-init only when these\r
+    callbacks are null (not registered beforehand).\r
+    If not, MspInit or MspDeInit are not null, the init and de-init keep and use\r
+    the user MspInit/MspDeInit callbacks (registered beforehand)\r
+\r
+    [..]\r
+    Callbacks can be registered/unregistered in READY state only.\r
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered\r
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used\r
+    during the init/de-init.\r
+    In that case first register the MspInit/MspDeInit user callbacks using\r
+    HAL_DFSDM_Channel_RegisterCallback() or\r
+    HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.\r
+\r
+    [..]\r
+    When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or\r
+    not defined, the callback registering feature is not available\r
+    and weak callbacks are used.\r
+\r
+    @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+#ifdef HAL_DFSDM_MODULE_ENABLED\r
+\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
+    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+\r
+/** @defgroup DFSDM DFSDM\r
+  * @brief DFSDM HAL driver module\r
+  * @{\r
+  */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Define DFSDM Private Define\r
+ * @{\r
+ */\r
+#define DFSDM_FLTCR1_MSB_RCH_OFFSET     8\r
+#define DFSDM_MSB_MASK                  0xFFFF0000U\r
+#define DFSDM_LSB_MASK                  0x0000FFFFU\r
+#define DFSDM_CKAB_TIMEOUT              5000U\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define DFSDM1_CHANNEL_NUMBER           4U\r
+#else /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+#define DFSDM1_CHANNEL_NUMBER           8U\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Variables DFSDM Private Variables\r
+  * @{\r
+  */\r
+static __IO uint32_t                v_dfsdm1ChannelCounter = 0;\r
+static DFSDM_Channel_HandleTypeDef *a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Functions DFSDM Private Functions\r
+  * @{\r
+  */\r
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);\r
+static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance);\r
+static void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+static void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+static void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+static void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+static void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+static void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);\r
+static void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+static void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);\r
+static void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r
+ *  @brief    Channel initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+        ##### Channel initialization and de-initialization functions #####\r
+  ==============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Initialize the DFSDM channel.\r
+      (+) De-initialize the DFSDM channel.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initialize the DFSDM channel according to the specified parameters\r
+  *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  /* Check DFSDM Channel handle */\r
+  if (hdfsdm_channel == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));\r
+  assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));\r
+  assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));\r
+  assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));\r
+  assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));\r
+  assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));\r
+  assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));\r
+  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));\r
+  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));\r
+  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));\r
+\r
+  /* Check that channel has not been already initialized */\r
+  if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  /* Reset callback pointers to the weak predefined callbacks */\r
+  hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;\r
+  hdfsdm_channel->ScdCallback  = HAL_DFSDM_ChannelScdCallback;\r
+\r
+  /* Call MSP init function */\r
+  if (hdfsdm_channel->MspInitCallback == NULL)\r
+  {\r
+    hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;\r
+  }\r
+  hdfsdm_channel->MspInitCallback(hdfsdm_channel);\r
+#else\r
+  /* Call MSP init function */\r
+  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);\r
+#endif\r
+\r
+  /* Update the channel counter */\r
+  v_dfsdm1ChannelCounter++;\r
+\r
+  /* Configure output serial clock and enable global DFSDM interface only for first channel */\r
+  if (v_dfsdm1ChannelCounter == 1U)\r
+  {\r
+    assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));\r
+    /* Set the output serial clock source */\r
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);\r
+    DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;\r
+\r
+    /* Reset clock divider */\r
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);\r
+    if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)\r
+    {\r
+      assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));\r
+      /* Set the output clock divider */\r
+      DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<\r
+                                             DFSDM_CHCFGR1_CKOUTDIV_Pos);\r
+    }\r
+\r
+    /* enable the DFSDM global interface */\r
+    DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;\r
+  }\r
+\r
+  /* Set channel input parameters */\r
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |\r
+                                         DFSDM_CHCFGR1_CHINSEL);\r
+  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |\r
+                                        hdfsdm_channel->Init.Input.DataPacking |\r
+                                        hdfsdm_channel->Init.Input.Pins);\r
+\r
+  /* Set serial interface parameters */\r
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);\r
+  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |\r
+                                        hdfsdm_channel->Init.SerialInterface.SpiClock);\r
+\r
+  /* Set analog watchdog parameters */\r
+  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);\r
+  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |\r
+                                         ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));\r
+\r
+  /* Set channel offset and right bit shift */\r
+  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);\r
+  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |\r
+                                        (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));\r
+\r
+  /* Enable DFSDM channel */\r
+  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;\r
+\r
+  /* Set DFSDM Channel to ready state */\r
+  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;\r
+\r
+  /* Store channel handle in DFSDM channel handle table */\r
+  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  De-initialize the DFSDM channel.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  /* Check DFSDM Channel handle */\r
+  if (hdfsdm_channel == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check that channel has not been already deinitialized */\r
+  if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Disable the DFSDM channel */\r
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);\r
+\r
+  /* Update the channel counter */\r
+  v_dfsdm1ChannelCounter--;\r
+\r
+  /* Disable global DFSDM at deinit of last channel */\r
+  if (v_dfsdm1ChannelCounter == 0U)\r
+  {\r
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);\r
+  }\r
+\r
+  /* Call MSP deinit function */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  if (hdfsdm_channel->MspDeInitCallback == NULL)\r
+  {\r
+    hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;\r
+  }\r
+  hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);\r
+#else\r
+  HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);\r
+#endif\r
+\r
+  /* Set DFSDM Channel in reset state */\r
+  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;\r
+\r
+  /* Reset channel handle in DFSDM channel handle table */\r
+  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initialize the DFSDM channel MSP.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_channel);\r
+\r
+  /* NOTE : This function should not be modified, when the function is needed,\r
+            the HAL_DFSDM_ChannelMspInit could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  De-initialize the DFSDM channel MSP.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_channel);\r
+\r
+  /* NOTE : This function should not be modified, when the function is needed,\r
+            the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.\r
+   */\r
+}\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  Register a user DFSDM channel callback\r
+  *         to be used instead of the weak predefined callback.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @param  CallbackID ID of the callback to be registered.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.\r
+  * @param  pCallback pointer to the callback function.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
+                                                     HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,\r
+                                                     pDFSDM_Channel_CallbackTypeDef      pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* update return status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)\r
+    {\r
+      switch (CallbackID)\r
+      {\r
+        case HAL_DFSDM_CHANNEL_CKAB_CB_ID :\r
+          hdfsdm_channel->CkabCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_CHANNEL_SCD_CB_ID :\r
+          hdfsdm_channel->ScdCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
+          hdfsdm_channel->MspInitCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
+          hdfsdm_channel->MspDeInitCallback = pCallback;\r
+          break;\r
+        default :\r
+          /* update return status */\r
+          status = HAL_ERROR;\r
+          break;\r
+      }\r
+    }\r
+    else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)\r
+    {\r
+      switch (CallbackID)\r
+      {\r
+        case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
+          hdfsdm_channel->MspInitCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
+          hdfsdm_channel->MspDeInitCallback = pCallback;\r
+          break;\r
+        default :\r
+          /* update return status */\r
+          status = HAL_ERROR;\r
+          break;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* update return status */\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister a user DFSDM channel callback.\r
+  *         DFSDM channel callback is redirected to the weak predefined callback.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @param  CallbackID ID of the callback to be unregistered.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.\r
+  *           @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
+                                                       HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_DFSDM_CHANNEL_CKAB_CB_ID :\r
+        hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;\r
+        break;\r
+      case HAL_DFSDM_CHANNEL_SCD_CB_ID :\r
+        hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;\r
+        break;\r
+      case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
+        hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;\r
+        break;\r
+      case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
+        hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;\r
+        break;\r
+      default :\r
+        /* update return status */\r
+        status = HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
+        hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;\r
+        break;\r
+      case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
+        hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;\r
+        break;\r
+      default :\r
+        /* update return status */\r
+        status = HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* update return status */\r
+    status = HAL_ERROR;\r
+  }\r
+  return status;\r
+}\r
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r
+ *  @brief    Channel operation functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+                   ##### Channel operation functions #####\r
+  ==============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Manage clock absence detector feature.\r
+      (+) Manage short circuit detector feature.\r
+      (+) Get analog watchdog value.\r
+      (+) Modify offset value.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  This function allows to start clock absence detection in polling mode.\r
+  * @note   Same mode has to be used for all channels.\r
+  * @note   If clock is not available on this channel during 5 seconds,\r
+  *         clock absence detection will not be activated and function\r
+  *         will return HAL_TIMEOUT error.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t channel;\r
+  uint32_t tickstart;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Get channel number from channel instance */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+\r
+    /* Get timeout */\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Clear clock absence flag */\r
+    while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)\r
+    {\r
+      DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
+\r
+      /* Check the Timeout */\r
+      if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT)\r
+      {\r
+        /* Set timeout status */\r
+        status = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      /* Start clock absence detection */\r
+      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r
+    }\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to poll for the clock absence detection.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @param  Timeout Timeout value in milliseconds.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+                                               uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+  uint32_t channel;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    return HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Get channel number from channel instance */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+\r
+    /* Get timeout */\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait clock absence detection */\r
+    while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)\r
+    {\r
+      /* Check the Timeout */\r
+      if (Timeout != HAL_MAX_DELAY)\r
+      {\r
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+        {\r
+          /* Return timeout status */\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+\r
+    /* Clear clock absence detection flag */\r
+    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
+\r
+    /* Return function status */\r
+    return HAL_OK;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop clock absence detection in polling mode.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t channel;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop clock absence detection */\r
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r
+\r
+    /* Clear clock absence flag */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start clock absence detection in interrupt mode.\r
+  * @note   Same mode has to be used for all channels.\r
+  * @note   If clock is not available on this channel during 5 seconds,\r
+  *         clock absence detection will not be activated and function\r
+  *         will return HAL_TIMEOUT error.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t channel;\r
+  uint32_t tickstart;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Get channel number from channel instance */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+\r
+    /* Get timeout */\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Clear clock absence flag */\r
+    while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)\r
+    {\r
+      DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
+\r
+      /* Check the Timeout */\r
+      if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT)\r
+      {\r
+        /* Set timeout status */\r
+        status = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      /* Activate clock absence detection interrupt */\r
+      DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;\r
+\r
+      /* Start clock absence detection */\r
+      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r
+    }\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Clock absence detection callback.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_channel);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop clock absence detection in interrupt mode.\r
+  * @note   Interrupt will be disabled for all channels\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t channel;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop clock absence detection */\r
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r
+\r
+    /* Clear clock absence flag */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
+\r
+    /* Disable clock absence detection interrupt */\r
+    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start short circuit detection in polling mode.\r
+  * @note   Same mode has to be used for all channels\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @param  Threshold Short circuit detector threshold.\r
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r
+  * @param  BreakSignal Break signals assigned to short circuit event.\r
+  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+                                            uint32_t Threshold,\r
+                                            uint32_t BreakSignal)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r
+  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Configure threshold and break signals */\r
+    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r
+    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \\r
+                                           Threshold);\r
+\r
+    /* Start short circuit detection */\r
+    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to poll for the short circuit detection.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @param  Timeout Timeout value in milliseconds.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+                                              uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+  uint32_t channel;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    return HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Get channel number from channel instance */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+\r
+    /* Get timeout */\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait short circuit detection */\r
+    while (((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)\r
+    {\r
+      /* Check the Timeout */\r
+      if (Timeout != HAL_MAX_DELAY)\r
+      {\r
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+        {\r
+          /* Return timeout status */\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+\r
+    /* Clear short circuit detection flag */\r
+    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
+\r
+    /* Return function status */\r
+    return HAL_OK;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop short circuit detection in polling mode.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t channel;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop short circuit detection */\r
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r
+\r
+    /* Clear short circuit detection flag */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start short circuit detection in interrupt mode.\r
+  * @note   Same mode has to be used for all channels\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @param  Threshold Short circuit detector threshold.\r
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r
+  * @param  BreakSignal Break signals assigned to short circuit event.\r
+  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+                                               uint32_t Threshold,\r
+                                               uint32_t BreakSignal)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r
+  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Activate short circuit detection interrupt */\r
+    DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;\r
+\r
+    /* Configure threshold and break signals */\r
+    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r
+    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \\r
+                                           Threshold);\r
+\r
+    /* Start short circuit detection */\r
+    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Short circuit detection callback.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_channel);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_ChannelScdCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop short circuit detection in interrupt mode.\r
+  * @note   Interrupt will be disabled for all channels\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t channel;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop short circuit detection */\r
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r
+\r
+    /* Clear short circuit detection flag */\r
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
+    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
+\r
+    /* Disable short circuit detection interrupt */\r
+    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get channel analog watchdog value.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval Channel analog watchdog value.\r
+  */\r
+int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  return (int16_t) hdfsdm_channel->Instance->CHWDATAR;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to modify channel offset value.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @param  Offset DFSDM channel offset.\r
+  *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+                                                int32_t Offset)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
+  assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));\r
+\r
+  /* Check DFSDM channel state */\r
+  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Modify channel offset */\r
+    hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);\r
+    hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r
+ *  @brief    Channel state function\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+                   ##### Channel state function #####\r
+  ==============================================================================\r
+    [..]  This section provides function allowing to:\r
+      (+) Get channel handle state.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  This function allows to get the current DFSDM channel handle state.\r
+  * @param  hdfsdm_channel DFSDM channel handle.\r
+  * @retval DFSDM channel state.\r
+  */\r
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
+{\r
+  /* Return DFSDM channel handle state */\r
+  return hdfsdm_channel->State;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r
+ *  @brief    Filter initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+        ##### Filter initialization and de-initialization functions #####\r
+  ==============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Initialize the DFSDM filter.\r
+      (+) De-initialize the DFSDM filter.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initialize the DFSDM filter according to the specified parameters\r
+  *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Check DFSDM Channel handle */\r
+  if (hdfsdm_filter == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));\r
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));\r
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));\r
+  assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));\r
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));\r
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));\r
+  assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));\r
+  assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));\r
+  assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));\r
+\r
+  /* Check parameters compatibility */\r
+  if ((hdfsdm_filter->Instance == DFSDM1_Filter0) &&\r
+      ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) ||\r
+       (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Initialize DFSDM filter variables with default values */\r
+  hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;\r
+  hdfsdm_filter->InjectedChannelsNbr = 1;\r
+  hdfsdm_filter->InjConvRemaining    = 1;\r
+  hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  /* Reset callback pointers to the weak predefined callbacks */\r
+  hdfsdm_filter->AwdCallback             = HAL_DFSDM_FilterAwdCallback;\r
+  hdfsdm_filter->RegConvCpltCallback     = HAL_DFSDM_FilterRegConvCpltCallback;\r
+  hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;\r
+  hdfsdm_filter->InjConvCpltCallback     = HAL_DFSDM_FilterInjConvCpltCallback;\r
+  hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;\r
+  hdfsdm_filter->ErrorCallback           = HAL_DFSDM_FilterErrorCallback;\r
+\r
+  /* Call MSP init function */\r
+  if (hdfsdm_filter->MspInitCallback == NULL)\r
+  {\r
+    hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;\r
+  }\r
+  hdfsdm_filter->MspInitCallback(hdfsdm_filter);\r
+#else\r
+  /* Call MSP init function */\r
+  HAL_DFSDM_FilterMspInit(hdfsdm_filter);\r
+#endif\r
+\r
+  /* Set regular parameters */\r
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r
+  if (hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;\r
+  }\r
+  else\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);\r
+  }\r
+\r
+  if (hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;\r
+  }\r
+  else\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);\r
+  }\r
+\r
+  /* Set injected parameters */\r
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);\r
+  if (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)\r
+  {\r
+    assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));\r
+    assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));\r
+    hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);\r
+  }\r
+\r
+  if (hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;\r
+  }\r
+  else\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);\r
+  }\r
+\r
+  if (hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;\r
+  }\r
+  else\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);\r
+  }\r
+\r
+  /* Set filter parameters */\r
+  hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);\r
+  hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |\r
+                                      ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |\r
+                                      (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));\r
+\r
+  /* Store regular and injected triggers and injected scan mode*/\r
+  hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;\r
+  hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;\r
+  hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;\r
+  hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;\r
+\r
+  /* Enable DFSDM filter */\r
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+\r
+  /* Set DFSDM filter to ready state */\r
+  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  De-initializes the DFSDM filter.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Check DFSDM filter handle */\r
+  if (hdfsdm_filter == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Disable the DFSDM filter */\r
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+\r
+  /* Call MSP deinit function */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  if (hdfsdm_filter->MspDeInitCallback == NULL)\r
+  {\r
+    hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;\r
+  }\r
+  hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);\r
+#else\r
+  HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);\r
+#endif\r
+\r
+  /* Set DFSDM filter in reset state */\r
+  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the DFSDM filter MSP.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+\r
+  /* NOTE : This function should not be modified, when the function is needed,\r
+            the HAL_DFSDM_FilterMspInit could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  De-initializes the DFSDM filter MSP.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+\r
+  /* NOTE : This function should not be modified, when the function is needed,\r
+            the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.\r
+   */\r
+}\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  Register a user DFSDM filter callback\r
+  *         to be used instead of the weak predefined callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  CallbackID ID of the callback to be registered.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.\r
+  * @param  pCallback pointer to the callback function.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
+                                                    HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,\r
+                                                    pDFSDM_Filter_CallbackTypeDef      pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* update the error code */\r
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+    /* update return status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
+    {\r
+      switch (CallbackID)\r
+      {\r
+        case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :\r
+          hdfsdm_filter->RegConvCpltCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :\r
+          hdfsdm_filter->RegConvHalfCpltCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :\r
+          hdfsdm_filter->InjConvCpltCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :\r
+          hdfsdm_filter->InjConvHalfCpltCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_FILTER_ERROR_CB_ID :\r
+          hdfsdm_filter->ErrorCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
+          hdfsdm_filter->MspInitCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
+          hdfsdm_filter->MspDeInitCallback = pCallback;\r
+          break;\r
+        default :\r
+          /* update the error code */\r
+          hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+          /* update return status */\r
+          status = HAL_ERROR;\r
+          break;\r
+      }\r
+    }\r
+    else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)\r
+    {\r
+      switch (CallbackID)\r
+      {\r
+        case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
+          hdfsdm_filter->MspInitCallback = pCallback;\r
+          break;\r
+        case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
+          hdfsdm_filter->MspDeInitCallback = pCallback;\r
+          break;\r
+        default :\r
+          /* update the error code */\r
+          hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+          /* update return status */\r
+          status = HAL_ERROR;\r
+          break;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* update the error code */\r
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+      /* update return status */\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister a user DFSDM filter callback.\r
+  *         DFSDM filter callback is redirected to the weak predefined callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  CallbackID ID of the callback to be unregistered.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.\r
+  *           @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
+                                                      HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :\r
+        hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;\r
+        break;\r
+      case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :\r
+        hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;\r
+        break;\r
+      case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :\r
+        hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;\r
+        break;\r
+      case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :\r
+        hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;\r
+        break;\r
+      case HAL_DFSDM_FILTER_ERROR_CB_ID :\r
+        hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;\r
+        break;\r
+      case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
+        hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;\r
+        break;\r
+      case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
+        hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;\r
+        break;\r
+      default :\r
+        /* update the error code */\r
+        hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+        /* update return status */\r
+        status = HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
+        hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;\r
+        break;\r
+      case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
+        hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;\r
+        break;\r
+      default :\r
+        /* update the error code */\r
+        hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+        /* update return status */\r
+        status = HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* update the error code */\r
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+    /* update return status */\r
+    status = HAL_ERROR;\r
+  }\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register a user DFSDM filter analog watchdog callback\r
+  *         to be used instead of the weak predefined callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  pCallback pointer to the DFSDM filter analog watchdog callback function.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,\r
+                                                       pDFSDM_Filter_AwdCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* update the error code */\r
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+    /* update return status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
+    {\r
+      hdfsdm_filter->AwdCallback = pCallback;\r
+    }\r
+    else\r
+    {\r
+      /* update the error code */\r
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+      /* update return status */\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister a user DFSDM filter analog watchdog callback.\r
+  *         DFSDM filter AWD callback is redirected to the weak predefined callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
+  {\r
+    hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;\r
+  }\r
+  else\r
+  {\r
+    /* update the error code */\r
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
+    /* update return status */\r
+    status = HAL_ERROR;\r
+  }\r
+  return status;\r
+}\r
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r
+ *  @brief    Filter control functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+                    ##### Filter control functions #####\r
+  ==============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Select channel and enable/disable continuous mode for regular conversion.\r
+      (+) Select channels for injected conversion.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  This function allows to select channel and to enable/disable\r
+  *         continuous mode for regular conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Channel for regular conversion.\r
+  *         This parameter can be a value of @ref DFSDM_Channel_Selection.\r
+  * @param  ContinuousMode Enable/disable continuous mode for regular conversion.\r
+  *         This parameter can be a value of @ref DFSDM_ContinuousMode.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                   uint32_t                    Channel,\r
+                                                   uint32_t                    ContinuousMode)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));\r
+  assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r
+  {\r
+    /* Configure channel and continuous mode for regular conversion */\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);\r
+    if (ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)\r
+    {\r
+      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)(((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |\r
+                                                    DFSDM_FLTCR1_RCONT);\r
+    }\r
+    else\r
+    {\r
+      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);\r
+    }\r
+    /* Store continuous mode information */\r
+    hdfsdm_filter->RegularContMode = ContinuousMode;\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to select channels for injected conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Channels for injected conversion.\r
+  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                   uint32_t                    Channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r
+  {\r
+    /* Configure channel for injected conversion */\r
+    hdfsdm_filter->Instance->FLTJCHGR = (uint32_t)(Channel & DFSDM_LSB_MASK);\r
+    /* Store number of injected channels */\r
+    hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);\r
+    /* Update number of injected channels remaining */\r
+    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+                                      hdfsdm_filter->InjectedChannelsNbr : 1U;\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r
+ *  @brief    Filter operation functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+                    ##### Filter operation functions #####\r
+  ==============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Start conversion of regular/injected channel.\r
+      (+) Poll for the end of regular/injected conversion.\r
+      (+) Stop conversion of regular/injected channel.\r
+      (+) Start conversion of regular/injected channel and enable interrupt.\r
+      (+) Call the callback functions at the end of regular/injected conversions.\r
+      (+) Stop conversion of regular/injected channel and disable interrupt.\r
+      (+) Start conversion of regular/injected channel and enable DMA transfer.\r
+      (+) Stop conversion of regular/injected channel and disable DMA transfer.\r
+      (+) Start analog watchdog and enable interrupt.\r
+      (+) Call the callback function when analog watchdog occurs.\r
+      (+) Stop analog watchdog and disable interrupt.\r
+      (+) Start extreme detector.\r
+      (+) Stop extreme detector.\r
+      (+) Get result of regular channel conversion.\r
+      (+) Get result of injected channel conversion.\r
+      (+) Get extreme detector maximum and minimum values.\r
+      (+) Get conversion time.\r
+      (+) Handle DFSDM interrupt request.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  This function allows to start regular conversion in polling mode.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if injected conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+  {\r
+    /* Start regular conversion */\r
+    DFSDM_RegConvStart(hdfsdm_filter);\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to poll for the end of regular conversion.\r
+  * @note   This function should be called only if regular conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Timeout Timeout value in milliseconds.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                       uint32_t                    Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    return HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Get timeout */\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait end of regular conversion */\r
+    while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)\r
+    {\r
+      /* Check the Timeout */\r
+      if (Timeout != HAL_MAX_DELAY)\r
+      {\r
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+        {\r
+          /* Return timeout status */\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+    /* Check if overrun occurs */\r
+    if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)\r
+    {\r
+      /* Update error code and call error callback */\r
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+      hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
+#else\r
+      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+#endif\r
+\r
+      /* Clear regular overrun flag */\r
+      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r
+    }\r
+    /* Update DFSDM filter state only if not continuous conversion and SW trigger */\r
+    if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+    {\r
+      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
+                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
+    }\r
+    /* Return function status */\r
+    return HAL_OK;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop regular conversion in polling mode.\r
+  * @note   This function should be called only if regular conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop regular conversion */\r
+    DFSDM_RegConvStop(hdfsdm_filter);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start regular conversion in interrupt mode.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if injected conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+  {\r
+    /* Enable interrupts for regular conversions */\r
+    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r
+\r
+    /* Start regular conversion */\r
+    DFSDM_RegConvStart(hdfsdm_filter);\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop regular conversion in interrupt mode.\r
+  * @note   This function should be called only if regular conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Disable interrupts for regular conversions */\r
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r
+\r
+    /* Stop regular conversion */\r
+    DFSDM_RegConvStop(hdfsdm_filter);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start regular conversion in DMA mode.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if injected conversion is ongoing.\r
+  *         Please note that data on buffer will contain signed regular conversion\r
+  *         value on 24 most significant bits and corresponding channel on 3 least\r
+  *         significant bits.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  pData The destination buffer address.\r
+  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                   int32_t                    *pData,\r
+                                                   uint32_t                    Length)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check destination address and length */\r
+  if ((pData == NULL) || (Length == 0U))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check that DMA is enabled for regular conversion */\r
+  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check parameters compatibility */\r
+  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\r
+           (Length != 1U))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check DFSDM filter state */\r
+  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+  {\r
+    /* Set callbacks on DMA handler */\r
+    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r
+    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r
+    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \\r
+                                                   DFSDM_DMARegularHalfConvCplt : NULL;\r
+\r
+    /* Start DMA in interrupt mode */\r
+    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \\r
+                         (uint32_t) pData, Length) != HAL_OK)\r
+    {\r
+      /* Set DFSDM filter in error state */\r
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+      status = HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      /* Start regular conversion */\r
+      DFSDM_RegConvStart(hdfsdm_filter);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start regular conversion in DMA mode and to get\r
+  *         only the 16 most significant bits of conversion.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if injected conversion is ongoing.\r
+  *         Please note that data on buffer will contain signed 16 most significant\r
+  *         bits of regular conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  pData The destination buffer address.\r
+  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                      int16_t                    *pData,\r
+                                                      uint32_t                    Length)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check destination address and length */\r
+  if ((pData == NULL) || (Length == 0U))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check that DMA is enabled for regular conversion */\r
+  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check parameters compatibility */\r
+  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\r
+           (Length != 1U))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check DFSDM filter state */\r
+  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
+  {\r
+    /* Set callbacks on DMA handler */\r
+    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r
+    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r
+    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \\r
+                                                   DFSDM_DMARegularHalfConvCplt : NULL;\r
+\r
+    /* Start DMA in interrupt mode */\r
+    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \\r
+                         (uint32_t) pData, Length) != HAL_OK)\r
+    {\r
+      /* Set DFSDM filter in error state */\r
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+      status = HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      /* Start regular conversion */\r
+      DFSDM_RegConvStart(hdfsdm_filter);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop regular conversion in DMA mode.\r
+  * @note   This function should be called only if regular conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop current DMA transfer */\r
+    if (HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)\r
+    {\r
+      /* Set DFSDM filter in error state */\r
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+      status = HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      /* Stop regular conversion */\r
+      DFSDM_RegConvStop(hdfsdm_filter);\r
+    }\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get regular conversion value.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Corresponding channel of regular conversion.\r
+  * @retval Regular conversion value\r
+  */\r
+int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                        uint32_t                   *Channel)\r
+{\r
+  uint32_t reg;\r
+  int32_t  value;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(Channel != (void *)0);\r
+\r
+  /* Get value of data register for regular channel */\r
+  reg = hdfsdm_filter->Instance->FLTRDATAR;\r
+\r
+  /* Extract channel and regular conversion value */\r
+  *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);\r
+  /* Regular conversion value is a signed value located on 24 MSB of register */\r
+  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
+  reg &= DFSDM_FLTRDATAR_RDATA;\r
+  value = ((int32_t)reg) / 256;\r
+\r
+  /* return regular conversion value */\r
+  return value;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start injected conversion in polling mode.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if regular conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+  {\r
+    /* Start injected conversion */\r
+    DFSDM_InjConvStart(hdfsdm_filter);\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to poll for the end of injected conversion.\r
+  * @note   This function should be called only if injected conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Timeout Timeout value in milliseconds.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                       uint32_t                    Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    return HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Get timeout */\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait end of injected conversions */\r
+    while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)\r
+    {\r
+      /* Check the Timeout */\r
+      if (Timeout != HAL_MAX_DELAY)\r
+      {\r
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+        {\r
+          /* Return timeout status */\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+    /* Check if overrun occurs */\r
+    if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)\r
+    {\r
+      /* Update error code and call error callback */\r
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+      hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
+#else\r
+      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+#endif\r
+\r
+      /* Clear injected overrun flag */\r
+      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r
+    }\r
+\r
+    /* Update remaining injected conversions */\r
+    hdfsdm_filter->InjConvRemaining--;\r
+    if (hdfsdm_filter->InjConvRemaining == 0U)\r
+    {\r
+      /* Update DFSDM filter state only if trigger is software */\r
+      if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+      {\r
+        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
+                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
+      }\r
+\r
+      /* end of injected sequence, reset the value */\r
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+                                        hdfsdm_filter->InjectedChannelsNbr : 1U;\r
+    }\r
+\r
+    /* Return function status */\r
+    return HAL_OK;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop injected conversion in polling mode.\r
+  * @note   This function should be called only if injected conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop injected conversion */\r
+    DFSDM_InjConvStop(hdfsdm_filter);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start injected conversion in interrupt mode.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if regular conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+  {\r
+    /* Enable interrupts for injected conversions */\r
+    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r
+\r
+    /* Start injected conversion */\r
+    DFSDM_InjConvStart(hdfsdm_filter);\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop injected conversion in interrupt mode.\r
+  * @note   This function should be called only if injected conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Disable interrupts for injected conversions */\r
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r
+\r
+    /* Stop injected conversion */\r
+    DFSDM_InjConvStop(hdfsdm_filter);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start injected conversion in DMA mode.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if regular conversion is ongoing.\r
+  *         Please note that data on buffer will contain signed injected conversion\r
+  *         value on 24 most significant bits and corresponding channel on 3 least\r
+  *         significant bits.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  pData The destination buffer address.\r
+  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                    int32_t                    *pData,\r
+                                                    uint32_t                    Length)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check destination address and length */\r
+  if ((pData == NULL) || (Length == 0U))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check that DMA is enabled for injected conversion */\r
+  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check parameters compatibility */\r
+  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\r
+           (Length > hdfsdm_filter->InjConvRemaining))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check DFSDM filter state */\r
+  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+  {\r
+    /* Set callbacks on DMA handler */\r
+    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r
+    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r
+    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \\r
+                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;\r
+\r
+    /* Start DMA in interrupt mode */\r
+    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \\r
+                         (uint32_t) pData, Length) != HAL_OK)\r
+    {\r
+      /* Set DFSDM filter in error state */\r
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+      status = HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      /* Start injected conversion */\r
+      DFSDM_InjConvStart(hdfsdm_filter);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start injected conversion in DMA mode and to get\r
+  *         only the 16 most significant bits of conversion.\r
+  * @note   This function should be called only when DFSDM filter instance is\r
+  *         in idle state or if regular conversion is ongoing.\r
+  *         Please note that data on buffer will contain signed 16 most significant\r
+  *         bits of injected conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  pData The destination buffer address.\r
+  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                                       int16_t                    *pData,\r
+                                                       uint32_t                    Length)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check destination address and length */\r
+  if ((pData == NULL) || (Length == 0U))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check that DMA is enabled for injected conversion */\r
+  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check parameters compatibility */\r
+  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\r
+           (Length > hdfsdm_filter->InjConvRemaining))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
+           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Check DFSDM filter state */\r
+  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
+           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
+  {\r
+    /* Set callbacks on DMA handler */\r
+    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r
+    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r
+    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \\r
+                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;\r
+\r
+    /* Start DMA in interrupt mode */\r
+    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \\r
+                         (uint32_t) pData, Length) != HAL_OK)\r
+    {\r
+      /* Set DFSDM filter in error state */\r
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+      status = HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      /* Start injected conversion */\r
+      DFSDM_InjConvStart(hdfsdm_filter);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop injected conversion in DMA mode.\r
+  * @note   This function should be called only if injected conversion is ongoing.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
+      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Stop current DMA transfer */\r
+    if (HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)\r
+    {\r
+      /* Set DFSDM filter in error state */\r
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
+      status = HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      /* Stop regular conversion */\r
+      DFSDM_InjConvStop(hdfsdm_filter);\r
+    }\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get injected conversion value.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Corresponding channel of injected conversion.\r
+  * @retval Injected conversion value\r
+  */\r
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                         uint32_t                   *Channel)\r
+{\r
+  uint32_t reg;\r
+  int32_t  value;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(Channel != (void *)0);\r
+\r
+  /* Get value of data register for injected channel */\r
+  reg = hdfsdm_filter->Instance->FLTJDATAR;\r
+\r
+  /* Extract channel and injected conversion value */\r
+  *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);\r
+  /* Injected conversion value is a signed value located on 24 MSB of register */\r
+  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
+  reg &= DFSDM_FLTJDATAR_JDATA;\r
+  value = ((int32_t)reg) / 256;\r
+\r
+  /* return regular conversion value */\r
+  return value;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start filter analog watchdog in interrupt mode.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  awdParam DFSDM filter analog watchdog parameters.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,\r
+                                              DFSDM_Filter_AwdParamTypeDef *awdParam)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));\r
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));\r
+  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));\r
+  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));\r
+  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));\r
+  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Set analog watchdog data source */\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r
+    hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;\r
+\r
+    /* Set thresholds and break signals */\r
+    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r
+    hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \\r
+                                          awdParam->HighBreakSignal);\r
+    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r
+    hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \\r
+                                          awdParam->LowBreakSignal);\r
+\r
+    /* Set channels and interrupt for analog watchdog */\r
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);\r
+    hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \\r
+                                        DFSDM_FLTCR2_AWDIE);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop filter analog watchdog in interrupt mode.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Reset channels for analog watchdog and deactivate interrupt */\r
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);\r
+\r
+    /* Clear all analog watchdog flags */\r
+    hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);\r
+\r
+    /* Reset thresholds and break signals */\r
+    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r
+    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r
+\r
+    /* Reset analog watchdog data source */\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to start extreme detector feature.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Channels where extreme detector is enabled.\r
+  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                           uint32_t                    Channel)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Set channels for extreme detector */\r
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r
+    hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to stop extreme detector feature.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  __IO uint32_t     reg1;\r
+  __IO uint32_t     reg2;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Check DFSDM filter state */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
+      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
+  {\r
+    /* Return error status */\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Reset channels for extreme detector */\r
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r
+\r
+    /* Clear extreme detector values */\r
+    reg1 = hdfsdm_filter->Instance->FLTEXMAX;\r
+    reg2 = hdfsdm_filter->Instance->FLTEXMIN;\r
+    UNUSED(reg1); /* To avoid GCC warning */\r
+    UNUSED(reg2); /* To avoid GCC warning */\r
+  }\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get extreme detector maximum value.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Corresponding channel.\r
+  * @retval Extreme detector maximum value\r
+  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.\r
+  */\r
+int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                       uint32_t                   *Channel)\r
+{\r
+  uint32_t reg;\r
+  int32_t  value;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(Channel != (void *)0);\r
+\r
+  /* Get value of extreme detector maximum register */\r
+  reg = hdfsdm_filter->Instance->FLTEXMAX;\r
+\r
+  /* Extract channel and extreme detector maximum value */\r
+  *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);\r
+  /* Extreme detector maximum value is a signed value located on 24 MSB of register */\r
+  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
+  reg &= DFSDM_FLTEXMAX_EXMAX;\r
+  value = ((int32_t)reg) / 256;\r
+\r
+  /* return extreme detector maximum value */\r
+  return value;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get extreme detector minimum value.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Corresponding channel.\r
+  * @retval Extreme detector minimum value\r
+  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.\r
+  */\r
+int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                       uint32_t                   *Channel)\r
+{\r
+  uint32_t reg;\r
+  int32_t  value;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+  assert_param(Channel != (void *)0);\r
+\r
+  /* Get value of extreme detector minimum register */\r
+  reg = hdfsdm_filter->Instance->FLTEXMIN;\r
+\r
+  /* Extract channel and extreme detector minimum value */\r
+  *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);\r
+  /* Extreme detector minimum value is a signed value located on 24 MSB of register */\r
+  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
+  reg &= DFSDM_FLTEXMIN_EXMIN;\r
+  value = ((int32_t)reg) / 256;\r
+\r
+  /* return extreme detector minimum value */\r
+  return value;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get conversion time value.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval Conversion time value\r
+  * @note   To get time in second, this value has to be divided by DFSDM clock frequency.\r
+  */\r
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  uint32_t reg;\r
+  uint32_t value;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
+\r
+  /* Get value of conversion timer register */\r
+  reg = hdfsdm_filter->Instance->FLTCNVTIMR;\r
+\r
+  /* Extract conversion time value */\r
+  value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);\r
+\r
+  /* return extreme detector minimum value */\r
+  return value;\r
+}\r
+\r
+/**\r
+  * @brief  This function handles the DFSDM interrupts.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Get FTLISR and FLTCR2 register values */\r
+  const uint32_t temp_fltisr = hdfsdm_filter->Instance->FLTISR;\r
+  const uint32_t temp_fltcr2 = hdfsdm_filter->Instance->FLTCR2;\r
+\r
+  /* Check if overrun occurs during regular conversion */\r
+  if (((temp_fltisr & DFSDM_FLTISR_ROVRF) != 0U) && \\r
+      ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U))\r
+  {\r
+    /* Clear regular overrun flag */\r
+    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r
+\r
+    /* Update error code */\r
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r
+\r
+    /* Call error callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+    hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
+#else\r
+    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+#endif\r
+  }\r
+  /* Check if overrun occurs during injected conversion */\r
+  else if (((temp_fltisr & DFSDM_FLTISR_JOVRF) != 0U) && \\r
+           ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U))\r
+  {\r
+    /* Clear injected overrun flag */\r
+    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r
+\r
+    /* Update error code */\r
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r
+\r
+    /* Call error callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+    hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
+#else\r
+    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+#endif\r
+  }\r
+  /* Check if end of regular conversion */\r
+  else if (((temp_fltisr & DFSDM_FLTISR_REOCF) != 0U) && \\r
+           ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))\r
+  {\r
+    /* Call regular conversion complete callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+    hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);\r
+#else\r
+    HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r
+#endif\r
+\r
+    /* End of conversion if mode is not continuous and software trigger */\r
+    if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
+        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+    {\r
+      /* Disable interrupts for regular conversions */\r
+      hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);\r
+\r
+      /* Update DFSDM filter state */\r
+      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
+                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
+    }\r
+  }\r
+  /* Check if end of injected conversion */\r
+  else if (((temp_fltisr & DFSDM_FLTISR_JEOCF) != 0U) && \\r
+           ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))\r
+  {\r
+    /* Call injected conversion complete callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+    hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);\r
+#else\r
+    HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r
+#endif\r
+\r
+    /* Update remaining injected conversions */\r
+    hdfsdm_filter->InjConvRemaining--;\r
+    if (hdfsdm_filter->InjConvRemaining == 0U)\r
+    {\r
+      /* End of conversion if trigger is software */\r
+      if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+      {\r
+        /* Disable interrupts for injected conversions */\r
+        hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);\r
+\r
+        /* Update DFSDM filter state */\r
+        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
+                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
+      }\r
+      /* end of injected sequence, reset the value */\r
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+                                        hdfsdm_filter->InjectedChannelsNbr : 1U;\r
+    }\r
+  }\r
+  /* Check if analog watchdog occurs */\r
+  else if (((temp_fltisr & DFSDM_FLTISR_AWDF) != 0U) && \\r
+           ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U))\r
+  {\r
+    uint32_t reg;\r
+    uint32_t threshold;\r
+    uint32_t channel = 0;\r
+\r
+    /* Get channel and threshold */\r
+    reg = hdfsdm_filter->Instance->FLTAWSR;\r
+    threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;\r
+    if (threshold == DFSDM_AWD_HIGH_THRESHOLD)\r
+    {\r
+      reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;\r
+    }\r
+    while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U)))\r
+    {\r
+      channel++;\r
+      reg = reg >> 1;\r
+    }\r
+    /* Clear analog watchdog flag */\r
+    hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \\r
+                                        (1UL << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \\r
+                                        (1UL << channel);\r
+\r
+    /* Call analog watchdog callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+    hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);\r
+#else\r
+    HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);\r
+#endif\r
+  }\r
+  /* Check if clock absence occurs */\r
+  else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\r
+           ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \\r
+           ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U))\r
+  {\r
+    uint32_t reg;\r
+    uint32_t channel = 0;\r
+\r
+    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);\r
+\r
+    while (channel < DFSDM1_CHANNEL_NUMBER)\r
+    {\r
+      /* Check if flag is set and corresponding channel is enabled */\r
+      if (((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL))\r
+      {\r
+        /* Check clock absence has been enabled for this channel */\r
+        if ((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)\r
+        {\r
+          /* Clear clock absence flag */\r
+          hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
+\r
+          /* Call clock absence callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+          a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);\r
+#else\r
+          HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);\r
+#endif\r
+        }\r
+      }\r
+      channel++;\r
+      reg = reg >> 1;\r
+    }\r
+  }\r
+  /* Check if short circuit detection occurs */\r
+  else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\r
+           ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \\r
+           ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U))\r
+  {\r
+    uint32_t reg;\r
+    uint32_t channel = 0;\r
+\r
+    /* Get channel */\r
+    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);\r
+    while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U)))\r
+    {\r
+      channel++;\r
+      reg = reg >> 1;\r
+    }\r
+\r
+    /* Clear short circuit detection flag */\r
+    hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
+\r
+    /* Call short circuit detection callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+    a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);\r
+#else\r
+    HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);\r
+#endif\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Regular conversion complete callback.\r
+  * @note   In interrupt mode, user has to read conversion value in this function\r
+  *         using HAL_DFSDM_FilterGetRegularValue.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Half regular conversion complete callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Injected conversion complete callback.\r
+  * @note   In interrupt mode, user has to read conversion value in this function\r
+  *         using HAL_DFSDM_FilterGetInjectedValue.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Half injected conversion complete callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Filter analog watchdog callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @param  Channel Corresponding channel.\r
+  * @param  Threshold Low or high threshold has been reached.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+                                        uint32_t Channel, uint32_t Threshold)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+  UNUSED(Channel);\r
+  UNUSED(Threshold);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Error callback.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hdfsdm_filter);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r
+ *  @brief    Filter state functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+                     ##### Filter state functions #####\r
+  ==============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Get the DFSDM filter state.\r
+      (+) Get the DFSDM filter error.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  This function allows to get the current DFSDM filter handle state.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval DFSDM filter state.\r
+  */\r
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Return DFSDM filter handle state */\r
+  return hdfsdm_filter->State;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get the current DFSDM filter error.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval DFSDM filter error code.\r
+  */\r
+uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  return hdfsdm_filter->ErrorCode;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  DMA half transfer complete callback for regular conversion.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Get DFSDM filter handle */\r
+  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  /* Call regular half conversion complete callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);\r
+#else\r
+  HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  DMA transfer complete callback for regular conversion.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Get DFSDM filter handle */\r
+  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  /* Call regular conversion complete callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);\r
+#else\r
+  HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  DMA half transfer complete callback for injected conversion.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Get DFSDM filter handle */\r
+  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  /* Call injected half conversion complete callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);\r
+#else\r
+  HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  DMA transfer complete callback for injected conversion.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Get DFSDM filter handle */\r
+  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  /* Call injected conversion complete callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);\r
+#else\r
+  HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  DMA error callback.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Get DFSDM filter handle */\r
+  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  /* Update error code */\r
+  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;\r
+\r
+  /* Call error callback */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+  hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
+#else\r
+  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get the number of injected channels.\r
+  * @param  Channels bitfield of injected channels.\r
+  * @retval Number of injected channels.\r
+  */\r
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)\r
+{\r
+  uint32_t nbChannels = 0;\r
+  uint32_t tmp;\r
+\r
+  /* Get the number of channels from bitfield */\r
+  tmp = (uint32_t)(Channels & DFSDM_LSB_MASK);\r
+  while (tmp != 0U)\r
+  {\r
+    if ((tmp & 1U) != 0U)\r
+    {\r
+      nbChannels++;\r
+    }\r
+    tmp = (uint32_t)(tmp >> 1);\r
+  }\r
+  return nbChannels;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to get the channel number from channel instance.\r
+  * @param  Instance DFSDM channel instance.\r
+  * @retval Channel number.\r
+  */\r
+static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)\r
+{\r
+  uint32_t channel;\r
+\r
+  /* Get channel from instance */\r
+  if (Instance == DFSDM1_Channel0)\r
+  {\r
+    channel = 0;\r
+  }\r
+  else if (Instance == DFSDM1_Channel1)\r
+  {\r
+    channel = 1;\r
+  }\r
+  else if (Instance == DFSDM1_Channel2)\r
+  {\r
+    channel = 2;\r
+  }\r
+  else if (Instance == DFSDM1_Channel3)\r
+  {\r
+    channel = 3;\r
+  }\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
+    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+  else if (Instance == DFSDM1_Channel4)\r
+  {\r
+    channel = 4;\r
+  }\r
+  else if (Instance == DFSDM1_Channel5)\r
+  {\r
+    channel = 5;\r
+  }\r
+  else if (Instance == DFSDM1_Channel6)\r
+  {\r
+    channel = 6;\r
+  }\r
+  else if (Instance == DFSDM1_Channel7)\r
+  {\r
+    channel = 7;\r
+  }\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+  else\r
+  {\r
+    channel = 0;\r
+  }\r
+\r
+  return channel;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to really start regular conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Check regular trigger */\r
+  if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+  {\r
+    /* Software start of regular conversion */\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
+  }\r
+  else /* synchronous trigger */\r
+  {\r
+    /* Disable DFSDM filter */\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+\r
+    /* Set RSYNC bit in DFSDM_FLTCR1 register */\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;\r
+\r
+    /* Enable DFSDM  filter */\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+\r
+    /* If injected conversion was in progress, restart it */\r
+    if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)\r
+    {\r
+      if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+      {\r
+        hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
+      }\r
+      /* Update remaining injected conversions */\r
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+                                        hdfsdm_filter->InjectedChannelsNbr : 1U;\r
+    }\r
+  }\r
+  /* Update DFSDM filter state */\r
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\r
+                         HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to really stop regular conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Disable DFSDM filter */\r
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+\r
+  /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */\r
+  if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r
+  }\r
+\r
+  /* Enable DFSDM filter */\r
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+\r
+  /* If injected conversion was in progress, restart it */\r
+  if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)\r
+  {\r
+    if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+    {\r
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
+    }\r
+    /* Update remaining injected conversions */\r
+    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+                                      hdfsdm_filter->InjectedChannelsNbr : 1U;\r
+  }\r
+\r
+  /* Update DFSDM filter state */\r
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
+                         HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to really start injected conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Check injected trigger */\r
+  if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
+  {\r
+    /* Software start of injected conversion */\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
+  }\r
+  else /* external or synchronous trigger */\r
+  {\r
+    /* Disable DFSDM filter */\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+\r
+    if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
+    {\r
+      /* Set JSYNC bit in DFSDM_FLTCR1 register */\r
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;\r
+    }\r
+    else /* external trigger */\r
+    {\r
+      /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r
+      hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;\r
+    }\r
+\r
+    /* Enable DFSDM filter */\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+\r
+    /* If regular conversion was in progress, restart it */\r
+    if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \\r
+        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+    {\r
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
+    }\r
+  }\r
+  /* Update DFSDM filter state */\r
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\r
+                         HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;\r
+}\r
+\r
+/**\r
+  * @brief  This function allows to really stop injected conversion.\r
+  * @param  hdfsdm_filter DFSDM filter handle.\r
+  * @retval None\r
+  */\r
+static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
+{\r
+  /* Disable DFSDM filter */\r
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
+\r
+  /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */\r
+  if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);\r
+  }\r
+  else if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)\r
+  {\r
+    /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+\r
+  /* Enable DFSDM filter */\r
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
+\r
+  /* If regular conversion was in progress, restart it */\r
+  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \\r
+      (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
+  {\r
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
+  }\r
+\r
+  /* Update remaining injected conversions */\r
+  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
+                                    hdfsdm_filter->InjectedChannelsNbr : 1U;\r
+\r
+  /* Update DFSDM filter state */\r
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
+                         HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* HAL_DFSDM_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
new file mode 100644 (file)
index 0000000..7746d0e
--- /dev/null
@@ -0,0 +1,1175 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_dma.c\r
+  * @author  MCD Application Team\r
+  * @brief   DMA HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Direct Memory Access (DMA) peripheral:\r
+  *           + Initialization and de-initialization functions\r
+  *           + IO operation functions\r
+  *           + Peripheral State and errors functions\r
+  @verbatim\r
+  ==============================================================================\r
+                        ##### How to use this driver #####\r
+  ==============================================================================\r
+  [..]\r
+   (#) Enable and configure the peripheral to be connected to the DMA Channel\r
+       (except for internal SRAM / FLASH memories: no initialization is\r
+       necessary). Please refer to the Reference manual for connection between peripherals\r
+       and DMA requests.\r
+\r
+   (#) For a given Channel, program the required configuration through the following parameters:\r
+       Channel request, Transfer Direction, Source and Destination data formats,\r
+       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode\r
+       using HAL_DMA_Init() function.\r
+\r
+       Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX\r
+       thanks to:\r
+      (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;\r
+      (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();\r
+\r
+   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error\r
+       detection.\r
+\r
+   (#) Use HAL_DMA_Abort() function to abort the current transfer\r
+\r
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
+\r
+     *** Polling mode IO operation ***\r
+     =================================\r
+     [..]\r
+       (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source\r
+           address and destination address and the Length of data to be transferred\r
+       (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this\r
+           case a fixed Timeout can be configured by User depending from his application.\r
+\r
+     *** Interrupt mode IO operation ***\r
+     ===================================\r
+     [..]\r
+       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
+       (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()\r
+       (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of\r
+           Source address and destination address and the Length of data to be transferred.\r
+           In this case the DMA interrupt is configured\r
+       (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
+       (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can\r
+              add his own function to register callbacks with HAL_DMA_RegisterCallback().\r
+\r
+     *** DMA HAL driver macros list ***\r
+     =============================================\r
+     [..]\r
+       Below the list of macros in DMA HAL driver.\r
+\r
+       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.\r
+       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.\r
+       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.\r
+       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.\r
+       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.\r
+       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.\r
+       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.\r
+\r
+     [..]\r
+      (@) You can refer to the DMA HAL driver header file for more useful macros\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DMA DMA\r
+  * @brief DMA HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup DMA_Private_Functions DMA Private Functions\r
+  * @{\r
+  */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+#if defined(DMAMUX1)\r
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);\r
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);\r
+#endif /* DMAMUX1 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ *  @brief   Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+             ##### Initialization and de-initialization functions  #####\r
+ ===============================================================================\r
+    [..]\r
+    This section provides functions allowing to initialize the DMA Channel source\r
+    and destination addresses, incrementation and data sizes, transfer direction,\r
+    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.\r
+    [..]\r
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
+    reference manual.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initialize the DMA according to the specified\r
+  *         parameters in the DMA_InitTypeDef and initialize the associated handle.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified DMA Channel.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
+{\r
+  uint32_t tmp;\r
+\r
+  /* Check the DMA handle allocation */\r
+  if(hdma == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
+\r
+  assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));\r
+\r
+  /* Compute the channel index */\r
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
+  {\r
+    /* DMA1 */\r
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
+    hdma->DmaBaseAddress = DMA1;\r
+  }\r
+  else\r
+  {\r
+    /* DMA2 */\r
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;\r
+    hdma->DmaBaseAddress = DMA2;\r
+  }\r
+\r
+  /* Change DMA peripheral state */\r
+  hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+  /* Get the CR register value */\r
+  tmp = hdma->Instance->CCR;\r
+\r
+  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */\r
+  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |\r
+                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |\r
+                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));\r
+\r
+  /* Prepare the DMA Channel configuration */\r
+  tmp |=  hdma->Init.Direction        |\r
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |\r
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
+          hdma->Init.Mode                | hdma->Init.Priority;\r
+\r
+  /* Write to DMA Channel CR register */\r
+  hdma->Instance->CCR = tmp;\r
+\r
+#if defined(DMAMUX1)\r
+  /* Initialize parameters for DMAMUX channel :\r
+     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask\r
+  */\r
+  DMA_CalcDMAMUXChannelBaseAndMask(hdma);\r
+\r
+  if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+  {\r
+    /* if memory to memory force the request to 0*/\r
+    hdma->Init.Request = DMA_REQUEST_MEM2MEM;\r
+  }\r
+\r
+  /* Set peripheral request  to DMAMUX channel */\r
+  hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);\r
+\r
+  /* Clear the DMAMUX synchro overrun flag */\r
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+  if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))\r
+  {\r
+    /* Initialize parameters for DMAMUX request generator :\r
+       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask\r
+    */\r
+    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);\r
+\r
+    /* Reset the DMAMUX request generator register*/\r
+    hdma->DMAmuxRequestGen->RGCR = 0U;\r
+\r
+    /* Clear the DMAMUX request generator overrun flag */\r
+    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+  }\r
+  else\r
+  {\r
+    hdma->DMAmuxRequestGen = 0U;\r
+    hdma->DMAmuxRequestGenStatus = 0U;\r
+    hdma->DMAmuxRequestGenStatusMask = 0U;\r
+  }\r
+#endif /* DMAMUX1 */\r
+\r
+#if !defined (DMAMUX1)\r
+\r
+  /* Set request selection */\r
+  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)\r
+  {\r
+    /* Write to DMA channel selection register */\r
+    if (DMA1 == hdma->DmaBaseAddress)\r
+    {\r
+      /* Reset request selection for DMA1 Channelx */\r
+      DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
+\r
+      /* Configure request selection for DMA1 Channelx */\r
+      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));\r
+    }\r
+    else /* DMA2 */\r
+    {\r
+      /* Reset request selection for DMA2 Channelx */\r
+      DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
+\r
+      /* Configure request selection for DMA2 Channelx */\r
+      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));\r
+    }\r
+  }\r
+\r
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */\r
+       /* STM32L496xx || STM32L4A6xx                                              */\r
+\r
+  /* Initialise the error code */\r
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+  /* Initialize the DMA state*/\r
+  hdma->State = HAL_DMA_STATE_READY;\r
+\r
+  /* Allocate lock resource and initialize it */\r
+  hdma->Lock = HAL_UNLOCKED;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitialize the DMA peripheral.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA Channel.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
+{\r
+\r
+  /* Check the DMA handle allocation */\r
+  if (NULL == hdma )\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+  /* Disable the selected DMA Channelx */\r
+  __HAL_DMA_DISABLE(hdma);\r
+\r
+  /* Compute the channel index */\r
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
+  {\r
+    /* DMA1 */\r
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
+    hdma->DmaBaseAddress = DMA1;\r
+  }\r
+  else\r
+  {\r
+    /* DMA2 */\r
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;\r
+    hdma->DmaBaseAddress = DMA2;\r
+  }\r
+\r
+  /* Reset DMA Channel control register */\r
+  hdma->Instance->CCR = 0U;\r
+\r
+  /* Clear all flags */\r
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+#if !defined (DMAMUX1)\r
+\r
+  /* Reset DMA channel selection register */\r
+  if (DMA1 == hdma->DmaBaseAddress)\r
+  {\r
+    /* DMA1 */\r
+    DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
+  }\r
+  else\r
+  {\r
+    /* DMA2 */\r
+    DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
+  }\r
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */\r
+       /* STM32L496xx || STM32L4A6xx                                              */\r
+\r
+#if defined(DMAMUX1)\r
+\r
+  /* Initialize parameters for DMAMUX channel :\r
+     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */\r
+\r
+  DMA_CalcDMAMUXChannelBaseAndMask(hdma);\r
+\r
+  /* Reset the DMAMUX channel that corresponds to the DMA channel */\r
+  hdma->DMAmuxChannel->CCR = 0U;\r
+\r
+  /* Clear the DMAMUX synchro overrun flag */\r
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+  /* Reset Request generator parameters if any */\r
+  if(((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))\r
+  {\r
+    /* Initialize parameters for DMAMUX request generator :\r
+       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask\r
+    */\r
+    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);\r
+\r
+    /* Reset the DMAMUX request generator register*/\r
+    hdma->DMAmuxRequestGen->RGCR = 0U;\r
+\r
+    /* Clear the DMAMUX request generator overrun flag */\r
+    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+  }\r
+\r
+  hdma->DMAmuxRequestGen = 0U;\r
+  hdma->DMAmuxRequestGenStatus = 0U;\r
+  hdma->DMAmuxRequestGenStatusMask = 0U;\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+  /* Clean callbacks */\r
+  hdma->XferCpltCallback = NULL;\r
+  hdma->XferHalfCpltCallback = NULL;\r
+  hdma->XferErrorCallback = NULL;\r
+  hdma->XferAbortCallback = NULL;\r
+\r
+  /* Initialise the error code */\r
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+  /* Initialize the DMA state */\r
+  hdma->State = HAL_DMA_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hdma);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions\r
+ *  @brief   Input and Output operation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      #####  IO operation functions  #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Configure the source, destination address and data length and Start DMA transfer\r
+      (+) Configure the source, destination address and data length and\r
+          Start DMA transfer with interrupt\r
+      (+) Abort DMA transfer\r
+      (+) Poll for transfer complete\r
+      (+) Handle DMA interrupt request\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Start the DMA Transfer.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA Channel.\r
+  * @param  SrcAddress The source memory Buffer address\r
+  * @param  DstAddress The destination memory Buffer address\r
+  * @param  DataLength The length of data to be transferred from source to destination\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hdma);\r
+\r
+  if(HAL_DMA_STATE_READY == hdma->State)\r
+  {\r
+    /* Change DMA peripheral state */\r
+    hdma->State = HAL_DMA_STATE_BUSY;\r
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+    /* Disable the peripheral */\r
+    __HAL_DMA_DISABLE(hdma);\r
+\r
+    /* Configure the source, destination address and the data length & clear flags*/\r
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+    /* Enable the Peripheral */\r
+    __HAL_DMA_ENABLE(hdma);\r
+  }\r
+  else\r
+  {\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hdma);\r
+    status = HAL_BUSY;\r
+  }\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Start the DMA Transfer with interrupt enabled.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA Channel.\r
+  * @param  SrcAddress The source memory Buffer address\r
+  * @param  DstAddress The destination memory Buffer address\r
+  * @param  DataLength The length of data to be transferred from source to destination\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hdma);\r
+\r
+  if(HAL_DMA_STATE_READY == hdma->State)\r
+  {\r
+    /* Change DMA peripheral state */\r
+    hdma->State = HAL_DMA_STATE_BUSY;\r
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+    /* Disable the peripheral */\r
+    __HAL_DMA_DISABLE(hdma);\r
+\r
+    /* Configure the source, destination address and the data length & clear flags*/\r
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+    /* Enable the transfer complete interrupt */\r
+    /* Enable the transfer Error interrupt */\r
+    if(NULL != hdma->XferHalfCpltCallback )\r
+    {\r
+      /* Enable the Half transfer complete interrupt as well */\r
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+    }\r
+    else\r
+    {\r
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));\r
+    }\r
+\r
+#ifdef DMAMUX1\r
+\r
+    /* Check if DMAMUX Synchronization is enabled*/\r
+    if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)\r
+    {\r
+      /* Enable DMAMUX sync overrun IT*/\r
+      hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;\r
+    }\r
+\r
+    if(hdma->DMAmuxRequestGen != 0U)\r
+    {\r
+      /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/\r
+      /* enable the request gen overrun IT*/\r
+      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;\r
+    }\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+    /* Enable the Peripheral */\r
+    __HAL_DMA_ENABLE(hdma);\r
+  }\r
+  else\r
+  {\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hdma);\r
+\r
+    /* Remain BUSY */\r
+    status = HAL_BUSY;\r
+  }\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Abort the DMA Transfer.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA Channel.\r
+    * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check the DMA peripheral state */\r
+  if(hdma->State != HAL_DMA_STATE_BUSY)\r
+  {\r
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hdma);\r
+\r
+    return HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Disable DMA IT */\r
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+\r
+#if defined(DMAMUX1)\r
+    /* disable the DMAMUX sync overrun IT*/\r
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
+#endif /* DMAMUX1 */\r
+\r
+    /* Disable the channel */\r
+    __HAL_DMA_DISABLE(hdma);\r
+\r
+    /* Clear all flags */\r
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+#if defined(DMAMUX1)\r
+    /* Clear the DMAMUX synchro overrun flag */\r
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+    if(hdma->DMAmuxRequestGen != 0U)\r
+    {\r
+      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/\r
+      /* disable the request gen overrun IT*/\r
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
+\r
+      /* Clear the DMAMUX request generator overrun flag */\r
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+    }\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+    /* Change the DMA state */\r
+    hdma->State = HAL_DMA_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hdma);\r
+\r
+    return status;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Aborts the DMA Transfer in Interrupt mode.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *                 the configuration information for the specified DMA Channel.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if(HAL_DMA_STATE_BUSY != hdma->State)\r
+  {\r
+    /* no transfer ongoing */\r
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+\r
+    status = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Disable DMA IT */\r
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+\r
+    /* Disable the channel */\r
+    __HAL_DMA_DISABLE(hdma);\r
+\r
+#if defined(DMAMUX1)\r
+    /* disable the DMAMUX sync overrun IT*/\r
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
+\r
+    /* Clear all flags */\r
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+    /* Clear the DMAMUX synchro overrun flag */\r
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+    if(hdma->DMAmuxRequestGen != 0U)\r
+    {\r
+      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/\r
+      /* disable the request gen overrun IT*/\r
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
+\r
+      /* Clear the DMAMUX request generator overrun flag */\r
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+    }\r
+\r
+#else\r
+    /* Clear all flags */\r
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+#endif /* DMAMUX1 */\r
+\r
+    /* Change the DMA state */\r
+    hdma->State = HAL_DMA_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hdma);\r
+\r
+    /* Call User Abort callback */\r
+    if(hdma->XferAbortCallback != NULL)\r
+    {\r
+      hdma->XferAbortCallback(hdma);\r
+    }\r
+  }\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Polling for transfer complete.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *                  the configuration information for the specified DMA Channel.\r
+  * @param  CompleteLevel Specifies the DMA level complete.\r
+  * @param  Timeout       Timeout duration.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r
+{\r
+  uint32_t temp;\r
+  uint32_t tickstart;\r
+\r
+  if(HAL_DMA_STATE_BUSY != hdma->State)\r
+  {\r
+    /* no transfer ongoing */\r
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+    __HAL_UNLOCK(hdma);\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Polling mode not supported in circular mode */\r
+  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)\r
+  {\r
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Get the level transfer complete flag */\r
+  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)\r
+  {\r
+    /* Transfer Complete flag */\r
+    temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);\r
+  }\r
+  else\r
+  {\r
+    /* Half Transfer Complete flag */\r
+    temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);\r
+  }\r
+\r
+  /* Get tick */\r
+  tickstart = HAL_GetTick();\r
+\r
+  while((hdma->DmaBaseAddress->ISR & temp) == 0U)\r
+  {\r
+    if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)\r
+    {\r
+      /* When a DMA transfer error occurs */\r
+      /* A hardware clear of its EN bits is performed */\r
+      /* Clear all flags */\r
+      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+      /* Update error code */\r
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
+\r
+      /* Change the DMA state */\r
+      hdma->State= HAL_DMA_STATE_READY;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hdma);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+    /* Check for the Timeout */\r
+    if(Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if(((HAL_GetTick() - tickstart) > Timeout) ||  (Timeout == 0U))\r
+      {\r
+        /* Update error code */\r
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+\r
+        /* Change the DMA state */\r
+        hdma->State = HAL_DMA_STATE_READY;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hdma);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+  }\r
+\r
+#if defined(DMAMUX1)\r
+  /*Check for DMAMUX Request generator (if used) overrun status */\r
+  if(hdma->DMAmuxRequestGen != 0U)\r
+  {\r
+    /* if using DMAMUX request generator Check for DMAMUX request generator overrun */\r
+    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)\r
+    {\r
+      /* Disable the request gen overrun interrupt */\r
+      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;\r
+\r
+      /* Clear the DMAMUX request generator overrun flag */\r
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+\r
+      /* Update error code */\r
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;\r
+    }\r
+  }\r
+\r
+  /* Check for DMAMUX Synchronization overrun */\r
+  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)\r
+  {\r
+    /* Clear the DMAMUX synchro overrun flag */\r
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+    /* Update error code */\r
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;\r
+  }\r
+#endif /* DMAMUX1 */\r
+\r
+  if(HAL_DMA_FULL_TRANSFER == CompleteLevel)\r
+  {\r
+    /* Clear the transfer complete flag */\r
+    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));\r
+\r
+    /* The selected Channelx EN bit is cleared (DMA is disabled and\r
+    all transfers are complete) */\r
+    hdma->State = HAL_DMA_STATE_READY;\r
+  }\r
+  else\r
+  {\r
+    /* Clear the half transfer complete flag */\r
+    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hdma);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handle DMA interrupt request.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA Channel.\r
+  * @retval None\r
+  */\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+  uint32_t flag_it = hdma->DmaBaseAddress->ISR;\r
+  uint32_t source_it = hdma->Instance->CCR;\r
+\r
+  /* Half Transfer Complete Interrupt management ******************************/\r
+  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))\r
+  {\r
+      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
+      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
+      {\r
+        /* Disable the half transfer interrupt */\r
+        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
+      }\r
+      /* Clear the half transfer complete flag */\r
+      hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);\r
+\r
+      /* DMA peripheral state is not updated in Half Transfer */\r
+      /* but in Transfer Complete case */\r
+\r
+      if(hdma->XferHalfCpltCallback != NULL)\r
+      {\r
+        /* Half transfer callback */\r
+        hdma->XferHalfCpltCallback(hdma);\r
+      }\r
+  }\r
+\r
+  /* Transfer Complete Interrupt management ***********************************/\r
+  else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))\r
+  {\r
+    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
+    {\r
+      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r
+      /* Disable the transfer complete and error interrupt */\r
+      /* if the DMA mode is not CIRCULAR  */\r
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);\r
+\r
+      /* Change the DMA state */\r
+      hdma->State = HAL_DMA_STATE_READY;\r
+    }\r
+    /* Clear the transfer complete flag */\r
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hdma);\r
+\r
+    if(hdma->XferCpltCallback != NULL)\r
+    {\r
+      /* Transfer complete callback */\r
+      hdma->XferCpltCallback(hdma);\r
+    }\r
+  }\r
+\r
+  /* Transfer Error Interrupt management **************************************/\r
+  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) !=  0U))\r
+  {\r
+    /* When a DMA transfer error occurs */\r
+    /* A hardware clear of its EN bits is performed */\r
+    /* Disable ALL DMA IT */\r
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+\r
+    /* Clear all flags */\r
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+    /* Update error code */\r
+    hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
+\r
+    /* Change the DMA state */\r
+    hdma->State = HAL_DMA_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hdma);\r
+\r
+    if (hdma->XferErrorCallback != NULL)\r
+    {\r
+      /* Transfer error callback */\r
+      hdma->XferErrorCallback(hdma);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Nothing To Do */\r
+  }\r
+  return;\r
+}\r
+\r
+/**\r
+  * @brief  Register callbacks\r
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\r
+  *                               the configuration information for the specified DMA Channel.\r
+  * @param  CallbackID           User Callback identifer\r
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
+  * @param  pCallback            pointer to private callbacsk function which has pointer to\r
+  *                               a DMA_HandleTypeDef structure as parameter.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hdma);\r
+\r
+  if(HAL_DMA_STATE_READY == hdma->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+     case  HAL_DMA_XFER_CPLT_CB_ID:\r
+           hdma->XferCpltCallback = pCallback;\r
+           break;\r
+\r
+     case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+           hdma->XferHalfCpltCallback = pCallback;\r
+           break;\r
+\r
+     case  HAL_DMA_XFER_ERROR_CB_ID:\r
+           hdma->XferErrorCallback = pCallback;\r
+           break;\r
+\r
+     case  HAL_DMA_XFER_ABORT_CB_ID:\r
+           hdma->XferAbortCallback = pCallback;\r
+           break;\r
+\r
+     default:\r
+           status = HAL_ERROR;\r
+           break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hdma);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister callbacks\r
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\r
+  *                               the configuration information for the specified DMA Channel.\r
+  * @param  CallbackID           User Callback identifer\r
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+    /* Process locked */\r
+  __HAL_LOCK(hdma);\r
+\r
+  if(HAL_DMA_STATE_READY == hdma->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+     case  HAL_DMA_XFER_CPLT_CB_ID:\r
+           hdma->XferCpltCallback = NULL;\r
+           break;\r
+\r
+     case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+           hdma->XferHalfCpltCallback = NULL;\r
+           break;\r
+\r
+     case  HAL_DMA_XFER_ERROR_CB_ID:\r
+           hdma->XferErrorCallback = NULL;\r
+           break;\r
+\r
+     case  HAL_DMA_XFER_ABORT_CB_ID:\r
+           hdma->XferAbortCallback = NULL;\r
+           break;\r
+\r
+    case   HAL_DMA_XFER_ALL_CB_ID:\r
+           hdma->XferCpltCallback = NULL;\r
+           hdma->XferHalfCpltCallback = NULL;\r
+           hdma->XferErrorCallback = NULL;\r
+           hdma->XferAbortCallback = NULL;\r
+           break;\r
+\r
+    default:\r
+           status = HAL_ERROR;\r
+           break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hdma);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+\r
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ *  @brief    Peripheral State and Errors functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+            ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides functions allowing to\r
+      (+) Check the DMA state\r
+      (+) Get error code\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Return the DMA handle state.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA Channel.\r
+  * @retval HAL state\r
+  */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Return DMA handle state */\r
+  return hdma->State;\r
+}\r
+\r
+/**\r
+  * @brief  Return the DMA error code.\r
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified DMA Channel.\r
+  * @retval DMA Error Code\r
+  */\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
+{\r
+  return hdma->ErrorCode;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup DMA_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Sets the DMA Transfer parameter.\r
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r
+  *                     the configuration information for the specified DMA Channel.\r
+  * @param  SrcAddress The source memory Buffer address\r
+  * @param  DstAddress The destination memory Buffer address\r
+  * @param  DataLength The length of data to be transferred from source to destination\r
+  * @retval HAL status\r
+  */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+#if defined(DMAMUX1)\r
+  /* Clear the DMAMUX synchro overrun flag */\r
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+  if(hdma->DMAmuxRequestGen != 0U)\r
+  {\r
+    /* Clear the DMAMUX request generator overrun flag */\r
+    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+  }\r
+#endif\r
+\r
+  /* Clear all flags */\r
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
+\r
+  /* Configure DMA Channel data length */\r
+  hdma->Instance->CNDTR = DataLength;\r
+\r
+  /* Memory to Peripheral */\r
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+  {\r
+    /* Configure DMA Channel destination address */\r
+    hdma->Instance->CPAR = DstAddress;\r
+\r
+    /* Configure DMA Channel source address */\r
+    hdma->Instance->CMAR = SrcAddress;\r
+  }\r
+  /* Peripheral to Memory */\r
+  else\r
+  {\r
+    /* Configure DMA Channel source address */\r
+    hdma->Instance->CPAR = SrcAddress;\r
+\r
+    /* Configure DMA Channel destination address */\r
+    hdma->Instance->CMAR = DstAddress;\r
+  }\r
+}\r
+\r
+#if defined(DMAMUX1)\r
+\r
+/**\r
+  * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on channel number\r
+  * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains\r
+  *                     the configuration information for the specified DMA Channel.\r
+  * @retval None\r
+  */\r
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)\r
+{\r
+  uint32_t channel_number;\r
+\r
+  /* check if instance is not outside the DMA channel range */\r
+  if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)\r
+  {\r
+    /* DMA1 */\r
+    hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));\r
+  }\r
+  else\r
+  {\r
+    /* DMA2 */\r
+    hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));\r
+  }\r
+\r
+  channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;\r
+  hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;\r
+  hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1CU);\r
+}\r
+\r
+/**\r
+  * @brief  Updates the DMA handle with the DMAMUX  request generator params\r
+  * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains\r
+  *                     the configuration information for the specified DMA Channel.\r
+  * @retval None\r
+  */\r
+\r
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)\r
+{\r
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;\r
+\r
+  /* DMA Channels are connected to DMAMUX1 request generator blocks*/\r
+  hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));\r
+\r
+  hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;\r
+\r
+  /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/\r
+  hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);\r
+}\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
new file mode 100644 (file)
index 0000000..fae98f1
--- /dev/null
@@ -0,0 +1,309 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_dma_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   DMA Extension HAL module driver\r
+  *         This file provides firmware functions to manage the following\r
+  *         functionalities of the DMA Extension peripheral:\r
+  *           + Extended features functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                        ##### How to use this driver #####\r
+  ==============================================================================\r
+  [..]\r
+  The DMA Extension HAL driver can be used as follows:\r
+\r
+   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
+   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
+       to respectively enable/disable the request generator.\r
+\r
+   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from\r
+       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.\r
+       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be\r
+       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project\r
+      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)\r
+\r
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r
+     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for\r
+          the AHB memory port on the fly (DMA_CM0ARx or DMA_CM1ARx) when the channel is enabled.\r
+\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+#if defined(DMAMUX1)\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DMAEx DMAEx\r
+  * @brief DMA Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions\r
+ *  @brief   Extended features functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                #####  Extended features functions  #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+\r
+    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
+    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
+       to respectively enable/disable the request generator.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+\r
+/**\r
+  * @brief  Configure the DMAMUX synchronization parameters for a given DMA channel (instance).\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified DMA channel.\r
+  * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+  assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));\r
+\r
+  assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));\r
+  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));\r
+  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));\r
+  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));\r
+\r
+  /*Check if the DMA state is ready */\r
+  if(hdma->State == HAL_DMA_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hdma);\r
+\r
+    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/\r
+    MODIFY_REG( hdma->DMAmuxChannel->CCR, \\r
+               (~DMAMUX_CxCR_DMAREQ_ID) , \\r
+               ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \\r
+               pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \\r
+                 ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));\r
+\r
+    /* Process UnLocked */\r
+    __HAL_UNLOCK(hdma);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    /*DMA State not Ready*/\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configure the DMAMUX request generator block used by the given DMA channel (instance).\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified DMA channel.\r
+  * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :\r
+  *         contains the request generator parameters.\r
+  *\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+  assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));\r
+\r
+  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));\r
+  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));\r
+\r
+  /* check if the DMA state is ready\r
+     and DMA is using a DMAMUX request generator block\r
+  */\r
+  if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hdma);\r
+\r
+    /* Set the request generator new parameters */\r
+    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \\r
+                                  ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \\r
+                                  pRequestGeneratorConfig->Polarity;\r
+   /* Process UnLocked */\r
+   __HAL_UNLOCK(hdma);\r
+\r
+   return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+   return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+  * @brief  Enable the DMAMUX request generator block used by the given DMA channel (instance).\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified DMA channel.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+  /* check if the DMA state is ready\r
+     and DMA is using a DMAMUX request generator block\r
+  */\r
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))\r
+  {\r
+\r
+    /* Enable the request generator*/\r
+    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;\r
+\r
+   return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+   return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+  * @brief  Disable the DMAMUX request generator block used by the given DMA channel (instance).\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified DMA channel.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+  /* check if the DMA state is ready\r
+     and DMA is using a DMAMUX request generator block\r
+  */\r
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))\r
+  {\r
+\r
+    /* Disable the request generator*/\r
+    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Handles DMAMUX interrupt request.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified DMA channel.\r
+  * @retval None\r
+  */\r
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+  /* Check for DMAMUX Synchronization overrun */\r
+  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)\r
+  {\r
+    /* Disable the synchro overrun interrupt */\r
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
+\r
+    /* Clear the DMAMUX synchro overrun flag */\r
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+    /* Update error code */\r
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;\r
+\r
+    if(hdma->XferErrorCallback != NULL)\r
+    {\r
+      /* Transfer error callback */\r
+      hdma->XferErrorCallback(hdma);\r
+    }\r
+  }\r
+\r
+  if(hdma->DMAmuxRequestGen != 0)\r
+  {\r
+   /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */\r
+    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)\r
+    {\r
+      /* Disable the request gen overrun interrupt */\r
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
+\r
+      /* Clear the DMAMUX request generator overrun flag */\r
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+\r
+      /* Update error code */\r
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;\r
+\r
+      if(hdma->XferErrorCallback != NULL)\r
+      {\r
+        /* Transfer error callback */\r
+        hdma->XferErrorCallback(hdma);\r
+      }\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
new file mode 100644 (file)
index 0000000..74405ed
--- /dev/null
@@ -0,0 +1,643 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_exti.c\r
+  * @author  MCD Application Team\r
+  * @brief   EXTI HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:\r
+  *           + Initialization and de-initialization functions\r
+  *           + IO operation functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                    ##### EXTI Peripheral features #####\r
+  ==============================================================================\r
+  [..]\r
+    (+) Each Exti line can be configured within this driver.\r
+\r
+    (+) Exti line can be configured in 3 different modes\r
+        (++) Interrupt\r
+        (++) Event\r
+        (++) Both of them\r
+\r
+    (+) Configurable Exti lines can be configured with 3 different triggers\r
+        (++) Rising\r
+        (++) Falling\r
+        (++) Both of them\r
+\r
+    (+) When set in interrupt mode, configurable Exti lines have two different\r
+        interrupts pending registers which allow to distinguish which transition\r
+        occurs:\r
+        (++) Rising edge pending interrupt\r
+        (++) Falling\r
+\r
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can\r
+        be selected through multiplexer.\r
+\r
+                     ##### How to use this driver #####\r
+  ==============================================================================\r
+  [..]\r
+\r
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().\r
+        (++) Choose the interrupt line number by setting "Line" member from\r
+             EXTI_ConfigTypeDef structure.\r
+        (++) Configure the interrupt and/or event mode using "Mode" member from\r
+             EXTI_ConfigTypeDef structure.\r
+        (++) For configurable lines, configure rising and/or falling trigger\r
+             "Trigger" member from EXTI_ConfigTypeDef structure.\r
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"\r
+             member from GPIO_InitTypeDef structure.\r
+\r
+    (#) Get current Exti configuration of a dedicated line using\r
+        HAL_EXTI_GetConfigLine().\r
+        (++) Provide exiting handle as parameter.\r
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.\r
+\r
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().\r
+        (++) Provide exiting handle as parameter.\r
+\r
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().\r
+        (++) Provide exiting handle as first parameter.\r
+        (++) Provide which callback will be registered using one value from\r
+             EXTI_CallbackIDTypeDef.\r
+        (++) Provide callback function pointer.\r
+\r
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().\r
+\r
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().\r
+\r
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup EXTI\r
+  * @{\r
+  */\r
+/** MISRA C:2012 deviation rule has been granted for following rule:\r
+  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out\r
+  * of bounds [0,3] in following API :\r
+  * HAL_EXTI_SetConfigLine\r
+  * HAL_EXTI_GetConfigLine\r
+  * HAL_EXTI_ClearConfigLine\r
+  */\r
+\r
+#ifdef HAL_EXTI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines ------------------------------------------------------------*/\r
+/** @defgroup EXTI_Private_Constants EXTI Private Constants\r
+  * @{\r
+  */\r
+#define EXTI_MODE_OFFSET                    0x08u   /* 0x20: offset between MCU IMR/EMR registers */\r
+#define EXTI_CONFIG_OFFSET                  0x08u   /* 0x20: offset between MCU Rising/Falling configuration registers */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup EXTI_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup EXTI_Exported_Functions_Group1\r
+ *  @brief    Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+              ##### Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Set configuration of a dedicated Exti line.\r
+  * @param  hexti Exti handle.\r
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.\r
+  * @retval HAL Status.\r
+  */\r
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\r
+{\r
+  __IO uint32_t *regaddr;\r
+  uint32_t regval;\r
+  uint32_t linepos;\r
+  uint32_t maskline;\r
+  uint32_t offset;\r
+\r
+  /* Check null pointer */\r
+  if ((hexti == NULL) || (pExtiConfig == NULL))\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));\r
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));\r
+\r
+  /* Assign line number to handle */\r
+  hexti->Line = pExtiConfig->Line;\r
+\r
+  /* Compute line register offset and line mask */\r
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);\r
+  maskline = (1uL << linepos);\r
+\r
+  /* Configure triggers for configurable lines */\r
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)\r
+  {\r
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));\r
+\r
+    /* Configure rising trigger */\r
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
+    regval = *regaddr;\r
+\r
+    /* Mask or set line */\r
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)\r
+    {\r
+      regval |= maskline;\r
+    }\r
+    else\r
+    {\r
+      regval &= ~maskline;\r
+    }\r
+\r
+    /* Store rising trigger mode */\r
+    *regaddr = regval;\r
+\r
+    /* Configure falling trigger */\r
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
+    regval = *regaddr;\r
+\r
+    /* Mask or set line */\r
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)\r
+    {\r
+      regval |= maskline;\r
+    }\r
+    else\r
+    {\r
+      regval &= ~maskline;\r
+    }\r
+\r
+    /* Store falling trigger mode */\r
+    *regaddr = regval;\r
+\r
+    /* Configure gpio port selection in case of gpio exti line */\r
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)\r
+    {\r
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));\r
+      assert_param(IS_EXTI_GPIO_PIN(linepos));\r
+\r
+      regval = SYSCFG->EXTICR[linepos >> 2u];\r
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\r
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\r
+      SYSCFG->EXTICR[linepos >> 2u] = regval;\r
+    }\r
+  }\r
+\r
+  /* Configure interrupt mode : read current mode */\r
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));\r
+  regval = *regaddr;\r
+\r
+  /* Mask or set line */\r
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)\r
+  {\r
+    regval |= maskline;\r
+  }\r
+  else\r
+  {\r
+    regval &= ~maskline;\r
+  }\r
+\r
+  /* Store interrupt mode */\r
+  *regaddr = regval;\r
+\r
+  /* The event mode cannot be configured if the line does not support it */\r
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));\r
+\r
+  /* Configure event mode : read current mode */\r
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));\r
+  regval = *regaddr;\r
+\r
+  /* Mask or set line */\r
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)\r
+  {\r
+    regval |= maskline;\r
+  }\r
+  else\r
+  {\r
+    regval &= ~maskline;\r
+  }\r
+\r
+  /* Store event mode */\r
+  *regaddr = regval;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Get configuration of a dedicated Exti line.\r
+  * @param  hexti Exti handle.\r
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.\r
+  * @retval HAL Status.\r
+  */\r
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\r
+{\r
+  __IO uint32_t *regaddr;\r
+  uint32_t regval;\r
+  uint32_t linepos;\r
+  uint32_t maskline;\r
+  uint32_t offset;\r
+\r
+  /* Check null pointer */\r
+  if ((hexti == NULL) || (pExtiConfig == NULL))\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameter */\r
+  assert_param(IS_EXTI_LINE(hexti->Line));\r
+\r
+  /* Store handle line number to configuration structure */\r
+  pExtiConfig->Line = hexti->Line;\r
+\r
+  /* Compute line register offset and line mask */\r
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);\r
+  maskline = (1uL << linepos);\r
+\r
+  /* 1] Get core mode : interrupt */\r
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));\r
+  regval = *regaddr;\r
+\r
+  /* Check if selected line is enable */\r
+  if ((regval & maskline) != 0x00u)\r
+  {\r
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;\r
+  }\r
+  else\r
+  {\r
+    pExtiConfig->Mode = EXTI_MODE_NONE;\r
+  }\r
+\r
+  /* Get event mode */\r
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));\r
+  regval = *regaddr;\r
+\r
+  /* Check if selected line is enable */\r
+  if ((regval & maskline) != 0x00u)\r
+  {\r
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;\r
+  }\r
+\r
+  /* 2] Get trigger for configurable lines : rising */\r
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)\r
+  {\r
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
+    regval = *regaddr;\r
+\r
+    /* Check if configuration of selected line is enable */\r
+    if ((regval & maskline) != 0x00u)\r
+    {\r
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;\r
+    }\r
+    else\r
+    {\r
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;\r
+    }\r
+\r
+    /* Get falling configuration */\r
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
+    regval = *regaddr;\r
+\r
+    /* Check if configuration of selected line is enable */\r
+    if ((regval & maskline) != 0x00u)\r
+    {\r
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;\r
+    }\r
+\r
+    /* Get Gpio port selection for gpio lines */\r
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)\r
+    {\r
+      assert_param(IS_EXTI_GPIO_PIN(linepos));\r
+\r
+      regval = SYSCFG->EXTICR[linepos >> 2u];\r
+      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);\r
+    }\r
+    else\r
+    {\r
+      pExtiConfig->GPIOSel = 0x00u;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;\r
+    pExtiConfig->GPIOSel = 0x00u;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Clear whole configuration of a dedicated Exti line.\r
+  * @param  hexti Exti handle.\r
+  * @retval HAL Status.\r
+  */\r
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)\r
+{\r
+  __IO uint32_t *regaddr;\r
+  uint32_t regval;\r
+  uint32_t linepos;\r
+  uint32_t maskline;\r
+  uint32_t offset;\r
+\r
+  /* Check null pointer */\r
+  if (hexti == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameter */\r
+  assert_param(IS_EXTI_LINE(hexti->Line));\r
+\r
+  /* compute line register offset and line mask */\r
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
+  linepos = (hexti->Line & EXTI_PIN_MASK);\r
+  maskline = (1uL << linepos);\r
+\r
+  /* 1] Clear interrupt mode */\r
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));\r
+  regval = (*regaddr & ~maskline);\r
+  *regaddr = regval;\r
+\r
+  /* 2] Clear event mode */\r
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));\r
+  regval = (*regaddr & ~maskline);\r
+  *regaddr = regval;\r
+\r
+  /* 3] Clear triggers in case of configurable lines */\r
+  if ((hexti->Line & EXTI_CONFIG) != 0x00u)\r
+  {\r
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
+    regval = (*regaddr & ~maskline);\r
+    *regaddr = regval;\r
+\r
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
+    regval = (*regaddr & ~maskline);\r
+    *regaddr = regval;\r
+\r
+    /* Get Gpio port selection for gpio lines */\r
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)\r
+    {\r
+      assert_param(IS_EXTI_GPIO_PIN(linepos));\r
+\r
+      regval = SYSCFG->EXTICR[linepos >> 2u];\r
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\r
+      SYSCFG->EXTICR[linepos >> 2u] = regval;\r
+    }\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Register callback for a dedicated Exti line.\r
+  * @param  hexti Exti handle.\r
+  * @param  CallbackID User callback identifier.\r
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.\r
+  * @param  pPendingCbfn function pointer to be stored as callback.\r
+  * @retval HAL Status.\r
+  */\r
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  switch (CallbackID)\r
+  {\r
+    case  HAL_EXTI_COMMON_CB_ID:\r
+      hexti->PendingCallback = pPendingCbfn;\r
+      break;\r
+\r
+    default:\r
+      status = HAL_ERROR;\r
+      break;\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Store line number as handle private field.\r
+  * @param  hexti Exti handle.\r
+  * @param  ExtiLine Exti line number.\r
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.\r
+  * @retval HAL Status.\r
+  */\r
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_LINE(ExtiLine));\r
+\r
+  /* Check null pointer */\r
+  if (hexti == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Store line number as handle private field */\r
+    hexti->Line = ExtiLine;\r
+\r
+    return HAL_OK;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup EXTI_Exported_Functions_Group2\r
+ *  @brief EXTI IO functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                       ##### IO operation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Handle EXTI interrupt request.\r
+  * @param  hexti Exti handle.\r
+  * @retval none.\r
+  */\r
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)\r
+{\r
+  __IO uint32_t *regaddr;\r
+  uint32_t regval;\r
+  uint32_t maskline;\r
+  uint32_t offset;\r
+\r
+  /* Compute line register offset and line mask */\r
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\r
+\r
+  /* Get pending bit  */\r
+  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));\r
+  regval = (*regaddr & maskline);\r
+\r
+  if (regval != 0x00u)\r
+  {\r
+    /* Clear pending bit */\r
+    *regaddr = maskline;\r
+\r
+    /* Call callback */\r
+    if (hexti->PendingCallback != NULL)\r
+    {\r
+      hexti->PendingCallback();\r
+    }\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Get interrupt pending bit of a dedicated line.\r
+  * @param  hexti Exti handle.\r
+  * @param  Edge Specify which pending edge as to be checked.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING\r
+  *         This parameter is kept for compatibility with other series.\r
+  * @retval 1 if interrupt is pending else 0.\r
+  */\r
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\r
+{\r
+  __IO uint32_t *regaddr;\r
+  uint32_t regval;\r
+  uint32_t linepos;\r
+  uint32_t maskline;\r
+  uint32_t offset;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_EXTI_LINE(hexti->Line));\r
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\r
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));\r
+\r
+  /* Compute line register offset and line mask */\r
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
+  linepos = (hexti->Line & EXTI_PIN_MASK);\r
+  maskline = (1uL << linepos);\r
+\r
+  /* Get pending bit */\r
+  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));\r
+\r
+  /* return 1 if bit is set else 0 */\r
+  regval = ((*regaddr & maskline) >> linepos);\r
+  return regval;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Clear interrupt pending bit of a dedicated line.\r
+  * @param  hexti Exti handle.\r
+  * @param  Edge Specify which pending edge as to be clear.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING\r
+  *         This parameter is kept for compatibility with other series.\r
+  * @retval None.\r
+  */\r
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\r
+{\r
+  __IO uint32_t *regaddr;\r
+  uint32_t maskline;\r
+  uint32_t offset;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_EXTI_LINE(hexti->Line));\r
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\r
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));\r
+\r
+  /* compute line register offset and line mask */\r
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\r
+\r
+  /* Get pending register address */\r
+  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));\r
+\r
+  /* Clear Pending bit */\r
+  *regaddr =  maskline;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Generate a software interrupt for a dedicated line.\r
+  * @param  hexti Exti handle.\r
+  * @retval None.\r
+  */\r
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)\r
+{\r
+  __IO uint32_t *regaddr;\r
+  uint32_t maskline;\r
+  uint32_t offset;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_EXTI_LINE(hexti->Line));\r
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\r
+\r
+  /* compute line register offset and line mask */\r
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\r
+\r
+  regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));\r
+  *regaddr = maskline;\r
+}\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_EXTI_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
new file mode 100644 (file)
index 0000000..a746962
--- /dev/null
@@ -0,0 +1,769 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_flash.c\r
+  * @author  MCD Application Team\r
+  * @brief   FLASH HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the internal FLASH memory:\r
+  *           + Program operations functions\r
+  *           + Memory Control functions\r
+  *           + Peripheral Errors functions\r
+  *\r
+ @verbatim\r
+  ==============================================================================\r
+                        ##### FLASH peripheral features #####\r
+  ==============================================================================\r
+\r
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses\r
+       to the Flash memory. It implements the erase and program Flash memory operations\r
+       and the read and write protection mechanisms.\r
+\r
+  [..] The Flash memory interface accelerates code execution with a system of instruction\r
+       prefetch and cache lines.\r
+\r
+  [..] The FLASH main features are:\r
+      (+) Flash memory read operations\r
+      (+) Flash memory program/erase operations\r
+      (+) Read / write protections\r
+      (+) Option bytes programming\r
+      (+) Prefetch on I-Code\r
+      (+) 32 cache lines of 4*64 bits on I-Code\r
+      (+) 8 cache lines of 4*64 bits on D-Code\r
+      (+) Error code correction (ECC) : Data in flash are 72-bits word\r
+          (8 bits added per double word)\r
+\r
+\r
+                        ##### How to use this driver #####\r
+ ==============================================================================\r
+    [..]\r
+      This driver provides functions and macros to configure and program the FLASH\r
+      memory of all STM32L4xx devices.\r
+\r
+      (#) Flash Memory IO Programming functions:\r
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and\r
+                HAL_FLASH_Lock() functions\r
+           (++) Program functions: double word and fast program (full row programming)\r
+           (++) There Two modes of programming :\r
+            (+++) Polling mode using HAL_FLASH_Program() function\r
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function\r
+\r
+      (#) Interrupts and flags management functions :\r
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\r
+           (++) Callback functions are called when the flash operations are finished :\r
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise\r
+                HAL_FLASH_OperationErrorCallback()\r
+           (++) Get error flag status by calling HAL_GetError()\r
+\r
+      (#) Option bytes management functions :\r
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and\r
+                HAL_FLASH_OB_Lock() functions\r
+           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.\r
+                In this case, a reset is generated\r
+\r
+    [..]\r
+      In addition to these functions, this driver includes a set of macros allowing\r
+      to handle the following operations:\r
+       (+) Set the latency\r
+       (+) Enable/Disable the prefetch buffer\r
+       (+) Enable/Disable the Instruction cache and the Data cache\r
+       (+) Reset the Instruction cache and the Data cache\r
+       (+) Enable/Disable the Flash power-down during low-power run and sleep modes\r
+       (+) Enable/Disable the Flash interrupts\r
+       (+) Monitor the Flash flags status\r
+\r
+ @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup FLASH FLASH\r
+  * @brief FLASH HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define FLASH_NB_DOUBLE_WORDS_IN_ROW  64\r
+#else\r
+#define FLASH_NB_DOUBLE_WORDS_IN_ROW  32\r
+#endif\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
+ * @{\r
+ */\r
+/**\r
+  * @brief  Variable used for Program/Erase sectors under interruption\r
+  */\r
+FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \\r
+                               .ErrorCode = HAL_FLASH_ERROR_NONE, \\r
+                               .ProcedureOnGoing = FLASH_PROC_NONE, \\r
+                               .Address = 0U, \\r
+                               .Bank = FLASH_BANK_1, \\r
+                               .Page = 0U, \\r
+                               .NbPagesToErase = 0U, \\r
+                               .CacheToReactivate = FLASH_CACHE_DISABLED};\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup FLASH_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\r
+static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions\r
+ *  @brief   Programming operation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                  ##### Programming operation functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to manage the FLASH\r
+    program operations.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Program double word or fast program of a row at a specified address.\r
+  * @param  TypeProgram:  Indicate the way to program at a specified address.\r
+  *                           This parameter can be a value of @ref FLASH_Type_Program\r
+  * @param  Address:  specifies the address to be programmed.\r
+  * @param  Data: specifies the data to be programmed\r
+  *                This parameter is the data for the double word program and the address where\r
+  *                are stored the data for the row fast program\r
+  *\r
+  * @retval HAL_StatusTypeDef HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t prog_bit = 0;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(&pFlash);\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+  /* Wait for last operation to be completed */\r
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+    /* Deactivate the data cache if they are activated to avoid data misbehavior */\r
+    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+    {\r
+      /* Disable data cache  */\r
+      __HAL_FLASH_DATA_CACHE_DISABLE();\r
+      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
+    }\r
+    else\r
+    {\r
+      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
+    }\r
+\r
+    if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)\r
+    {\r
+      /* Program double-word (64-bit) at a specified address */\r
+      FLASH_Program_DoubleWord(Address, Data);\r
+      prog_bit = FLASH_CR_PG;\r
+    }\r
+    else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))\r
+    {\r
+      /* Fast program a 32 row double-word (64-bit) at a specified address */\r
+      FLASH_Program_Fast(Address, (uint32_t)Data);\r
+\r
+      /* If it is the last row, the bit will be cleared at the end of the operation */\r
+      if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)\r
+      {\r
+        prog_bit = FLASH_CR_FSTPG;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Nothing to do */\r
+    }\r
+\r
+    /* Wait for last operation to be completed */\r
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+    /* If the program operation is completed, disable the PG or FSTPG Bit */\r
+    if (prog_bit != 0U)\r
+    {\r
+      CLEAR_BIT(FLASH->CR, prog_bit);\r
+    }\r
+\r
+    /* Flush the caches to be sure of the data consistency */\r
+    FLASH_FlushCaches();\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(&pFlash);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.\r
+  * @param  TypeProgram:  Indicate the way to program at a specified address.\r
+  *                           This parameter can be a value of @ref FLASH_Type_Program\r
+  * @param  Address:  specifies the address to be programmed.\r
+  * @param  Data: specifies the data to be programmed\r
+  *                This parameter is the data for the double word program and the address where\r
+  *                are stored the data for the row fast program\r
+  *\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(&pFlash);\r
+\r
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+  /* Deactivate the data cache if they are activated to avoid data misbehavior */\r
+  if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+  {\r
+    /* Disable data cache  */\r
+    __HAL_FLASH_DATA_CACHE_DISABLE();\r
+    pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
+  }\r
+  else\r
+  {\r
+    pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
+  }\r
+\r
+  /* Set internal variables used by the IRQ handler */\r
+  if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)\r
+  {\r
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;\r
+  }\r
+  else\r
+  {\r
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r
+  }\r
+  pFlash.Address = Address;\r
+\r
+  /* Enable End of Operation and Error interrupts */\r
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);\r
+\r
+  if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)\r
+  {\r
+    /* Program double-word (64-bit) at a specified address */\r
+    FLASH_Program_DoubleWord(Address, Data);\r
+  }\r
+  else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))\r
+  {\r
+    /* Fast program a 32 row double-word (64-bit) at a specified address */\r
+    FLASH_Program_Fast(Address, (uint32_t)Data);\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief Handle FLASH interrupt request.\r
+  * @retval None\r
+  */\r
+void HAL_FLASH_IRQHandler(void)\r
+{\r
+  uint32_t tmp_page;\r
+  uint32_t error;\r
+  FLASH_ProcedureTypeDef procedure;\r
+\r
+  /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */\r
+  CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);\r
+#endif\r
+\r
+  /* Disable the FSTPG Bit only if it is the last row programmed */\r
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)\r
+  {\r
+    CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);\r
+  }\r
+\r
+  /* Check FLASH operation error flags */\r
+  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);\r
+  error |= (FLASH->ECCR & FLASH_FLAG_ECCC);\r
+\r
+  if (error !=0U)\r
+  {\r
+    /*Save the error code*/\r
+    pFlash.ErrorCode |= error;\r
+\r
+    /* Clear error programming flags */\r
+    __HAL_FLASH_CLEAR_FLAG(error);\r
+\r
+    /* Flush the caches to be sure of the data consistency */\r
+    FLASH_FlushCaches() ;\r
+\r
+    /* FLASH error interrupt user callback */\r
+    procedure = pFlash.ProcedureOnGoing;\r
+    if(procedure == FLASH_PROC_PAGE_ERASE)\r
+    {\r
+       HAL_FLASH_OperationErrorCallback(pFlash.Page);\r
+    }\r
+    else if(procedure == FLASH_PROC_MASS_ERASE)\r
+    {\r
+        HAL_FLASH_OperationErrorCallback(pFlash.Bank);\r
+    }\r
+    else if((procedure == FLASH_PROC_PROGRAM) ||\r
+            (procedure == FLASH_PROC_PROGRAM_LAST))\r
+    {\r
+       HAL_FLASH_OperationErrorCallback(pFlash.Address);\r
+    }\r
+    else\r
+    {\r
+       HAL_FLASH_OperationErrorCallback(0U);\r
+    }\r
+\r
+    /*Stop the procedure ongoing*/\r
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+  }\r
+\r
+  /* Check FLASH End of Operation flag  */\r
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0U)\r
+  {\r
+    /* Clear FLASH End of Operation pending bit */\r
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+\r
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)\r
+    {\r
+      /* Nb of pages to erased can be decreased */\r
+      pFlash.NbPagesToErase--;\r
+\r
+      /* Check if there are still pages to erase*/\r
+      if(pFlash.NbPagesToErase != 0U)\r
+      {\r
+        /* Indicate user which page has been erased*/\r
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);\r
+\r
+        /* Increment page number */\r
+        pFlash.Page++;\r
+        tmp_page = pFlash.Page;\r
+        FLASH_PageErase(tmp_page, pFlash.Bank);\r
+      }\r
+      else\r
+      {\r
+        /* No more pages to Erase */\r
+        /* Reset Address and stop Erase pages procedure */\r
+        pFlash.Page = 0xFFFFFFFFU;\r
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+\r
+        /* Flush the caches to be sure of the data consistency */\r
+        FLASH_FlushCaches() ;\r
+\r
+        /* FLASH EOP interrupt user callback */\r
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Flush the caches to be sure of the data consistency */\r
+      FLASH_FlushCaches() ;\r
+\r
+      procedure = pFlash.ProcedureOnGoing;\r
+      if(procedure == FLASH_PROC_MASS_ERASE)\r
+      {\r
+        /* MassErase ended. Return the selected bank */\r
+        /* FLASH EOP interrupt user callback */\r
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);\r
+      }\r
+      else if((procedure == FLASH_PROC_PROGRAM) ||\r
+              (procedure == FLASH_PROC_PROGRAM_LAST))\r
+      {\r
+        /* Program ended. Return the selected address */\r
+        /* FLASH EOP interrupt user callback */\r
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
+      }\r
+      else\r
+      {\r
+        /* Nothing to do */\r
+      }\r
+\r
+      /*Clear the procedure ongoing*/\r
+      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+    }\r
+  }\r
+\r
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r
+  {\r
+    /* Disable End of Operation and Error interrupts */\r
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(&pFlash);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  FLASH end of operation interrupt callback.\r
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
+  *                  Mass Erase: Bank number which has been requested to erase\r
+  *                  Page Erase: Page which has been erased\r
+  *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)\r
+  *                  Program: Address which was selected for data program\r
+  * @retval None\r
+  */\r
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(ReturnValue);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  FLASH operation error interrupt callback.\r
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
+  *                 Mass Erase: Bank number which has been requested to erase\r
+  *                 Page Erase: Page number which returned an error\r
+  *                 Program: Address which was selected for data program\r
+  * @retval None\r
+  */\r
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(ReturnValue);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions\r
+ *  @brief   Management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to control the FLASH\r
+    memory operations.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Unlock the FLASH control register access.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)\r
+  {\r
+    /* Authorize the FLASH Registers access */\r
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);\r
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);\r
+\r
+    /* Verify Flash is unlocked */\r
+    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)\r
+    {\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Lock the FLASH control register access.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void)\r
+{\r
+  /* Set the LOCK Bit to lock the FLASH Registers access */\r
+  SET_BIT(FLASH->CR, FLASH_CR_LOCK);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Unlock the FLASH Option Bytes Registers access.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r
+{\r
+  if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)\r
+  {\r
+    /* Authorizes the Option Byte register programming */\r
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);\r
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Lock the FLASH Option Bytes Registers access.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r
+{\r
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r
+  SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Launch the option byte loading.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r
+{\r
+  /* Set the bit to force the option byte reloading */\r
+  SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);\r
+\r
+  /* Wait for last operation to be completed */\r
+  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ *  @brief   Peripheral Errors functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                ##### Peripheral Errors functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection permits to get in run-time Errors of the FLASH peripheral.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Get the specific FLASH error flag.\r
+  * @retval FLASH_ErrorCode: The returned value can be:\r
+  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)\r
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag\r
+  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag\r
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag\r
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag\r
+  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag\r
+  *            @arg HAL_FLASH_ERROR_NONE: No error set\r
+  *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error\r
+  *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error\r
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error\r
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error\r
+  *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error\r
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error\r
+  *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error\r
+  *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error\r
+  *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error\r
+  *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error\r
+  *            @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)\r
+  *            @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected\r
+  */\r
+uint32_t HAL_FLASH_GetError(void)\r
+{\r
+   return pFlash.ErrorCode;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup FLASH_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Wait for a FLASH operation to complete.\r
+  * @param  Timeout: maximum flash operation timeout\r
+  * @retval HAL_StatusTypeDef HAL Status\r
+  */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{\r
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
+     flag will be set */\r
+\r
+  uint32_t tickstart = HAL_GetTick();\r
+  uint32_t error;\r
+\r
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))\r
+  {\r
+    if(Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if((HAL_GetTick() - tickstart) >= Timeout)\r
+      {\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+  }\r
+\r
+  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);\r
+  error |= (FLASH->ECCR & FLASH_FLAG_ECCD);\r
+\r
+  if(error != 0u)\r
+  {\r
+    /*Save the error code*/\r
+    pFlash.ErrorCode |= error;\r
+\r
+    /* Clear error programming flags */\r
+    __HAL_FLASH_CLEAR_FLAG(error);\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check FLASH End of Operation flag  */\r
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))\r
+  {\r
+    /* Clear FLASH End of Operation pending bit */\r
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+  }\r
+\r
+  /* If there is an error flag set */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Program double-word (64-bit) at a specified address.\r
+  * @param  Address: specifies the address to be programmed.\r
+  * @param  Data: specifies the data to be programmed.\r
+  * @retval None\r
+  */\r
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+\r
+  /* Set PG bit */\r
+  SET_BIT(FLASH->CR, FLASH_CR_PG);\r
+\r
+  /* Program first word */\r
+  *(__IO uint32_t*)Address = (uint32_t)Data;\r
+\r
+  /* Barrier to ensure programming is performed in 2 steps, in right order\r
+    (independently of compiler optimization behavior) */\r
+  __ISB();\r
+\r
+  /* Program second word */\r
+  *(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32);\r
+}\r
+\r
+/**\r
+  * @brief  Fast program a row double-word (64-bit) at a specified address.\r
+  * @param  Address: specifies the address to be programmed.\r
+  * @param  DataAddress: specifies the address where the data are stored.\r
+  * @retval None\r
+  */\r
+static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)\r
+{\r
+  uint32_t primask_bit;\r
+  uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);\r
+  __IO uint32_t *dest_addr = (__IO uint32_t*)Address;\r
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));\r
+\r
+  /* Set FSTPG bit */\r
+  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);\r
+\r
+  /* Disable interrupts to avoid any interruption during the loop */\r
+  primask_bit = __get_PRIMASK();\r
+  __disable_irq();\r
+\r
+  /* Program the double word of the row */\r
+  do\r
+  {\r
+    *dest_addr = *src_addr;\r
+    dest_addr++;\r
+    src_addr++;\r
+    row_index--;\r
+  } while (row_index != 0U);\r
+\r
+  /* Re-enable the interrupts */\r
+  __set_PRIMASK(primask_bit);\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
new file mode 100644 (file)
index 0000000..5a30708
--- /dev/null
@@ -0,0 +1,1308 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_flash_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   Extended FLASH HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the FLASH extended peripheral:\r
+  *           + Extended programming operations functions\r
+  *\r
+ @verbatim\r
+ ==============================================================================\r
+                   ##### Flash Extended features #####\r
+  ==============================================================================\r
+\r
+  [..] Comparing to other previous devices, the FLASH interface for STM32L4xx\r
+       devices contains the following additional features\r
+\r
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\r
+           capability (RWW)\r
+       (+) Dual bank memory organization\r
+       (+) PCROP protection for all banks\r
+\r
+                        ##### How to use this driver #####\r
+ ==============================================================================\r
+  [..] This driver provides functions to configure and program the FLASH memory\r
+       of all STM32L4xx devices. It includes\r
+      (#) Flash Memory Erase functions:\r
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and\r
+                HAL_FLASH_Lock() functions\r
+           (++) Erase function: Erase page, erase all sectors\r
+           (++) There are two modes of erase :\r
+             (+++) Polling Mode using HAL_FLASHEx_Erase()\r
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\r
+\r
+      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :\r
+        (++) Set/Reset the write protection\r
+        (++) Set the Read protection Level\r
+        (++) Program the user Option Bytes\r
+        (++) Configure the PCROP protection\r
+\r
+      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :\r
+        (++) Get the value of a write protection area\r
+        (++) Know if the read protection is activated\r
+        (++) Get the value of the user Option Bytes\r
+        (++) Get the value of a PCROP area\r
+\r
+ @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup FLASHEx FLASHEx\r
+  * @brief FLASH Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions\r
+ * @{\r
+ */\r
+static void              FLASH_MassErase(uint32_t Banks);\r
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);\r
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);\r
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);\r
+static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);\r
+static uint32_t          FLASH_OB_GetRDP(void);\r
+static uint32_t          FLASH_OB_GetUser(void);\r
+static void              FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions -------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\r
+ *  @brief   Extended IO operation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                ##### Extended programming operation functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to manage the Extended FLASH\r
+    programming operations Operations.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages.\r
+  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
+  *         contains the configuration information for the erasing.\r
+  *\r
+  * @param[out]  PageError  : pointer to variable that contains the configuration\r
+  *         information on faulty page in case of error (0xFFFFFFFF means that all\r
+  *         the pages have been correctly erased)\r
+  *\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t page_index;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(&pFlash);\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+  /* Wait for last operation to be completed */\r
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+  if (status == HAL_OK)\r
+  {\r
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+    /* Deactivate the cache if they are activated to avoid data misbehavior */\r
+    if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)\r
+    {\r
+      /* Disable instruction cache  */\r
+      __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
+\r
+      if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+      {\r
+        /* Disable data cache  */\r
+        __HAL_FLASH_DATA_CACHE_DISABLE();\r
+        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;\r
+      }\r
+      else\r
+      {\r
+        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;\r
+      }\r
+    }\r
+    else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+    {\r
+      /* Disable data cache  */\r
+      __HAL_FLASH_DATA_CACHE_DISABLE();\r
+      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
+    }\r
+    else\r
+    {\r
+      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
+    }\r
+\r
+    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+    {\r
+      /* Mass erase to be done */\r
+      FLASH_MassErase(pEraseInit->Banks);\r
+\r
+      /* Wait for last operation to be completed */\r
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+      /* If the erase operation is completed, disable the MER1 and MER2 Bits */\r
+      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));\r
+#else\r
+      /* If the erase operation is completed, disable the MER1 Bit */\r
+      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));\r
+#endif\r
+    }\r
+    else\r
+    {\r
+      /*Initialization of PageError variable*/\r
+      *PageError = 0xFFFFFFFFU;\r
+\r
+      for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)\r
+      {\r
+        FLASH_PageErase(page_index, pEraseInit->Banks);\r
+\r
+        /* Wait for last operation to be completed */\r
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+        /* If the erase operation is completed, disable the PER Bit */\r
+        CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));\r
+\r
+        if (status != HAL_OK)\r
+        {\r
+          /* In case of error, stop erase procedure and return the faulty address */\r
+          *PageError = page_index;\r
+          break;\r
+        }\r
+      }\r
+    }\r
+\r
+    /* Flush the caches to be sure of the data consistency */\r
+    FLASH_FlushCaches();\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(&pFlash);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.\r
+  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
+  *         contains the configuration information for the erasing.\r
+  *\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(&pFlash);\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+  /* Deactivate the cache if they are activated to avoid data misbehavior */\r
+  if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)\r
+  {\r
+    /* Disable instruction cache  */\r
+    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
+\r
+    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+    {\r
+      /* Disable data cache  */\r
+      __HAL_FLASH_DATA_CACHE_DISABLE();\r
+      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;\r
+    }\r
+    else\r
+    {\r
+      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;\r
+    }\r
+  }\r
+  else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+  {\r
+    /* Disable data cache  */\r
+    __HAL_FLASH_DATA_CACHE_DISABLE();\r
+    pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
+  }\r
+  else\r
+  {\r
+    pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
+  }\r
+\r
+  /* Enable End of Operation and Error interrupts */\r
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);\r
+\r
+  pFlash.Bank = pEraseInit->Banks;\r
+\r
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+  {\r
+    /* Mass erase to be done */\r
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;\r
+    FLASH_MassErase(pEraseInit->Banks);\r
+  }\r
+  else\r
+  {\r
+    /* Erase by page to be done */\r
+    pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;\r
+    pFlash.NbPagesToErase = pEraseInit->NbPages;\r
+    pFlash.Page = pEraseInit->Page;\r
+\r
+    /*Erase 1st page and wait for IT */\r
+    FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Program Option bytes.\r
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that\r
+  *         contains the configuration information for the programming.\r
+  *\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(&pFlash);\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r
+\r
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+\r
+  /* Write protection configuration */\r
+  if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)\r
+  {\r
+    /* Configure of Write protection on the selected area */\r
+    if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)\r
+    {\r
+      status = HAL_ERROR;\r
+    }\r
+\r
+  }\r
+\r
+  /* Read protection configuration */\r
+  if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)\r
+  {\r
+    /* Configure the Read protection level */\r
+    if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)\r
+    {\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+\r
+  /* User Configuration */\r
+  if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)\r
+  {\r
+    /* Configure the user option bytes */\r
+    if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)\r
+    {\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+\r
+  /* PCROP Configuration */\r
+  if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)\r
+  {\r
+    if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)\r
+    {\r
+      /* Configure the Proprietary code readout protection */\r
+      if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)\r
+      {\r
+        status = HAL_ERROR;\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(&pFlash);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Get the Option bytes configuration.\r
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that contains the\r
+  *                  configuration information.\r
+  * @note   The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate\r
+  *         which area is requested for the WRP and PCROP, else no information will be returned\r
+  *\r
+  * @retval None\r
+  */\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+  pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||\r
+     (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))\r
+#else\r
+  if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))\r
+#endif\r
+  {\r
+    pOBInit->OptionType |= OPTIONBYTE_WRP;\r
+    /* Get write protection on the selected area */\r
+    FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));\r
+  }\r
+\r
+  /* Get Read protection level */\r
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();\r
+\r
+  /* Get the user option bytes */\r
+  pOBInit->USERConfig = FLASH_OB_GetUser();\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))\r
+#else\r
+  if(pOBInit->PCROPConfig == FLASH_BANK_1)\r
+#endif\r
+  {\r
+    pOBInit->OptionType |= OPTIONBYTE_PCROP;\r
+    /* Get the Proprietary code readout protection */\r
+    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined (FLASH_CFGR_LVEN)\r
+/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions\r
+ *  @brief   Extended specific configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                ##### Extended specific configuration functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to manage the Extended FLASH\r
+    specific configurations.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Configuration of the LVE pin of the Flash (managed by power controller\r
+  *         or forced to low in order to use an external SMPS)\r
+  * @param  ConfigLVE: Configuration of the LVE pin,\r
+  *              This parameter can be one of the following values:\r
+  *                @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller\r
+  *                @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used)\r
+  *\r
+  * @note   Before enforcing the LVE pin to low, the SOC should be in low voltage\r
+  *         range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON.\r
+  *\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE)\r
+{\r
+  HAL_StatusTypeDef status;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(&pFlash);\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_LVE_PIN(ConfigLVE));\r
+\r
+  /* Wait for last operation to be completed */\r
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+  if (status == HAL_OK)\r
+  {\r
+    /* Check that the voltage scaling is range 2 */\r
+    if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2)\r
+    {\r
+      /* Configure the LVEN bit */\r
+      MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE);\r
+\r
+      /* Check that the bit has been correctly configured */\r
+      if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE)\r
+      {\r
+        status = HAL_ERROR;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Not allow to force Flash LVE pin if not in voltage range 2 */\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(&pFlash);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* FLASH_CFGR_LVEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup FLASHEx_Private_Functions\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Mass erase of FLASH memory.\r
+  * @param  Banks: Banks to be erased\r
+  *          This parameter can be one of the following values:\r
+  *            @arg FLASH_BANK_1: Bank1 to be erased\r
+  *            @arg FLASH_BANK_2: Bank2 to be erased\r
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\r
+  * @retval None\r
+  */\r
+static void FLASH_MassErase(uint32_t Banks)\r
+{\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)\r
+#endif\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_FLASH_BANK(Banks));\r
+\r
+    /* Set the Mass Erase Bit for the bank 1 if requested */\r
+    if((Banks & FLASH_BANK_1) != 0U)\r
+    {\r
+      SET_BIT(FLASH->CR, FLASH_CR_MER1);\r
+    }\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+    /* Set the Mass Erase Bit for the bank 2 if requested */\r
+    if((Banks & FLASH_BANK_2) != 0U)\r
+    {\r
+      SET_BIT(FLASH->CR, FLASH_CR_MER2);\r
+    }\r
+#endif\r
+  }\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  else\r
+  {\r
+    SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));\r
+  }\r
+#endif\r
+\r
+  /* Proceed to erase all sectors */\r
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
+}\r
+\r
+/**\r
+  * @brief  Erase the specified FLASH memory page.\r
+  * @param  Page: FLASH page to erase\r
+  *         This parameter must be a value between 0 and (max number of pages in the bank - 1)\r
+  * @param  Banks: Bank(s) where the page will be erased\r
+  *          This parameter can be one of the following values:\r
+  *            @arg FLASH_BANK_1: Page in bank 1 to be erased\r
+  *            @arg FLASH_BANK_2: Page in bank 2 to be erased\r
+  * @retval None\r
+  */\r
+void FLASH_PageErase(uint32_t Page, uint32_t Banks)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_PAGE(Page));\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)\r
+  {\r
+    CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);\r
+  }\r
+  else\r
+#endif\r
+  {\r
+    assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));\r
+\r
+    if((Banks & FLASH_BANK_1) != 0U)\r
+    {\r
+      CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);\r
+    }\r
+    else\r
+    {\r
+      SET_BIT(FLASH->CR, FLASH_CR_BKER);\r
+    }\r
+  }\r
+#else\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(Banks);\r
+#endif\r
+\r
+  /* Proceed to erase the page */\r
+  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));\r
+  SET_BIT(FLASH->CR, FLASH_CR_PER);\r
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
+}\r
+\r
+/**\r
+  * @brief  Flush the instruction and data caches.\r
+  * @retval None\r
+  */\r
+void FLASH_FlushCaches(void)\r
+{\r
+  FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;\r
+\r
+  /* Flush instruction cache  */\r
+  if((cache == FLASH_CACHE_ICACHE_ENABLED) ||\r
+     (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))\r
+  {\r
+    /* Reset instruction cache */\r
+    __HAL_FLASH_INSTRUCTION_CACHE_RESET();\r
+    /* Enable instruction cache */\r
+    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();\r
+  }\r
+\r
+  /* Flush data cache */\r
+  if((cache == FLASH_CACHE_DCACHE_ENABLED) ||\r
+     (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))\r
+  {\r
+    /* Reset data cache */\r
+    __HAL_FLASH_DATA_CACHE_RESET();\r
+    /* Enable data cache */\r
+    __HAL_FLASH_DATA_CACHE_ENABLE();\r
+  }\r
+\r
+  /* Reset internal variable */\r
+  pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the write protection of the desired pages.\r
+  *\r
+  * @note   When the memory read protection level is selected (RDP level = 1),\r
+  *         it is not possible to program or erase Flash memory if the CPU debug\r
+  *         features are connected (JTAG or single wire) or boot code is being\r
+  *         executed from RAM or System flash, even if WRP is not activated.\r
+  * @note   To configure the WRP options, the option lock bit OPTLOCK must be\r
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
+  * @note   To validate the WRP options, the option bytes must be reloaded\r
+  *         through the call of the HAL_FLASH_OB_Launch() function.\r
+  *\r
+  * @param  WRPArea: specifies the area to be configured.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A\r
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B\r
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A  (don't apply for STM32L43x/STM32L44x devices)\r
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B  (don't apply for STM32L43x/STM32L44x devices)\r
+  *\r
+  * @param  WRPStartOffset: specifies the start page of the write protected area\r
+  *          This parameter can be page number between 0 and (max number of pages in the bank - 1)\r
+  *\r
+  * @param  WRDPEndOffset: specifies the end page of the write protected area\r
+  *          This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)\r
+  *\r
+  * @retval HAL Status\r
+  */\r
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)\r
+{\r
+  HAL_StatusTypeDef status;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_OB_WRPAREA(WRPArea));\r
+  assert_param(IS_FLASH_PAGE(WRPStartOffset));\r
+  assert_param(IS_FLASH_PAGE(WRDPEndOffset));\r
+\r
+  /* Wait for last operation to be completed */\r
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+    /* Configure the write protected area */\r
+    if(WRPArea == OB_WRPAREA_BANK1_AREAA)\r
+    {\r
+      MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),\r
+                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
+    }\r
+    else if(WRPArea == OB_WRPAREA_BANK1_AREAB)\r
+    {\r
+      MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),\r
+                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
+    }\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+    else if(WRPArea == OB_WRPAREA_BANK2_AREAA)\r
+    {\r
+      MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),\r
+                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
+    }\r
+    else if(WRPArea == OB_WRPAREA_BANK2_AREAB)\r
+    {\r
+      MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),\r
+                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
+    }\r
+#endif\r
+    else\r
+    {\r
+      /* Nothing to do */\r
+    }\r
+\r
+    /* Set OPTSTRT Bit */\r
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+    /* Wait for last operation to be completed */\r
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Set the read protection level.\r
+  *\r
+  * @note   To configure the RDP level, the option lock bit OPTLOCK must be\r
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
+  * @note   To validate the RDP level, the option bytes must be reloaded\r
+  *         through the call of the HAL_FLASH_OB_Launch() function.\r
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible\r
+  *         to go back to level 1 or 0 !!!\r
+  *\r
+  * @param  RDPLevel: specifies the read protection level.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg OB_RDP_LEVEL_0: No protection\r
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r
+  *            @arg OB_RDP_LEVEL_2: Full chip protection\r
+  *\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)\r
+{\r
+  HAL_StatusTypeDef status;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));\r
+\r
+  /* Wait for last operation to be completed */\r
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+    /* Configure the RDP level in the option bytes register */\r
+    MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);\r
+\r
+    /* Set OPTSTRT Bit */\r
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+    /* Wait for last operation to be completed */\r
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Program the FLASH User Option Byte.\r
+  *\r
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must\r
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
+  * @note   To validate the user option bytes, the option bytes must be reloaded\r
+  *         through the call of the HAL_FLASH_OB_Launch() function.\r
+  *\r
+  * @param  UserType: The FLASH User Option Bytes to be modified\r
+  * @param  UserConfig: The FLASH User Option Bytes values:\r
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),\r
+  *         IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),\r
+  *         DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).\r
+  *\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)\r
+{\r
+  uint32_t optr_reg_val = 0;\r
+  uint32_t optr_reg_mask = 0;\r
+  HAL_StatusTypeDef status;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_OB_USER_TYPE(UserType));\r
+\r
+  /* Wait for last operation to be completed */\r
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+    if((UserType & OB_USER_BOR_LEV) != 0U)\r
+    {\r
+      /* BOR level option byte should be modified */\r
+      assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));\r
+\r
+      /* Set value and mask for BOR level option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);\r
+      optr_reg_mask |= FLASH_OPTR_BOR_LEV;\r
+    }\r
+\r
+    if((UserType & OB_USER_nRST_STOP) != 0U)\r
+    {\r
+      /* nRST_STOP option byte should be modified */\r
+      assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));\r
+\r
+      /* Set value and mask for nRST_STOP option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);\r
+      optr_reg_mask |= FLASH_OPTR_nRST_STOP;\r
+    }\r
+\r
+    if((UserType & OB_USER_nRST_STDBY) != 0U)\r
+    {\r
+      /* nRST_STDBY option byte should be modified */\r
+      assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));\r
+\r
+      /* Set value and mask for nRST_STDBY option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);\r
+      optr_reg_mask |= FLASH_OPTR_nRST_STDBY;\r
+    }\r
+\r
+    if((UserType & OB_USER_nRST_SHDW) != 0U)\r
+    {\r
+      /* nRST_SHDW option byte should be modified */\r
+      assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));\r
+\r
+      /* Set value and mask for nRST_SHDW option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);\r
+      optr_reg_mask |= FLASH_OPTR_nRST_SHDW;\r
+    }\r
+\r
+    if((UserType & OB_USER_IWDG_SW) != 0U)\r
+    {\r
+      /* IWDG_SW option byte should be modified */\r
+      assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));\r
+\r
+      /* Set value and mask for IWDG_SW option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);\r
+      optr_reg_mask |= FLASH_OPTR_IWDG_SW;\r
+    }\r
+\r
+    if((UserType & OB_USER_IWDG_STOP) != 0U)\r
+    {\r
+      /* IWDG_STOP option byte should be modified */\r
+      assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));\r
+\r
+      /* Set value and mask for IWDG_STOP option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);\r
+      optr_reg_mask |= FLASH_OPTR_IWDG_STOP;\r
+    }\r
+\r
+    if((UserType & OB_USER_IWDG_STDBY) != 0U)\r
+    {\r
+      /* IWDG_STDBY option byte should be modified */\r
+      assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));\r
+\r
+      /* Set value and mask for IWDG_STDBY option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);\r
+      optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;\r
+    }\r
+\r
+    if((UserType & OB_USER_WWDG_SW) != 0U)\r
+    {\r
+      /* WWDG_SW option byte should be modified */\r
+      assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));\r
+\r
+      /* Set value and mask for WWDG_SW option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);\r
+      optr_reg_mask |= FLASH_OPTR_WWDG_SW;\r
+    }\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+    if((UserType & OB_USER_BFB2) != 0U)\r
+    {\r
+      /* BFB2 option byte should be modified */\r
+      assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));\r
+\r
+      /* Set value and mask for BFB2 option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);\r
+      optr_reg_mask |= FLASH_OPTR_BFB2;\r
+    }\r
+\r
+    if((UserType & OB_USER_DUALBANK) != 0U)\r
+    {\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+      /* DUALBANK option byte should be modified */\r
+      assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M));\r
+\r
+      /* Set value and mask for DUALBANK option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M);\r
+      optr_reg_mask |= FLASH_OPTR_DB1M;\r
+#else\r
+      /* DUALBANK option byte should be modified */\r
+      assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));\r
+\r
+      /* Set value and mask for DUALBANK option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);\r
+      optr_reg_mask |= FLASH_OPTR_DUALBANK;\r
+#endif\r
+    }\r
+#endif\r
+\r
+    if((UserType & OB_USER_nBOOT1) != 0U)\r
+    {\r
+      /* nBOOT1 option byte should be modified */\r
+      assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));\r
+\r
+      /* Set value and mask for nBOOT1 option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);\r
+      optr_reg_mask |= FLASH_OPTR_nBOOT1;\r
+    }\r
+\r
+    if((UserType & OB_USER_SRAM2_PE) != 0U)\r
+    {\r
+      /* SRAM2_PE option byte should be modified */\r
+      assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));\r
+\r
+      /* Set value and mask for SRAM2_PE option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);\r
+      optr_reg_mask |= FLASH_OPTR_SRAM2_PE;\r
+    }\r
+\r
+    if((UserType & OB_USER_SRAM2_RST) != 0U)\r
+    {\r
+      /* SRAM2_RST option byte should be modified */\r
+      assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));\r
+\r
+      /* Set value and mask for SRAM2_RST option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);\r
+      optr_reg_mask |= FLASH_OPTR_SRAM2_RST;\r
+    }\r
+\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
+    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+    if((UserType & OB_USER_nSWBOOT0) != 0U)\r
+    {\r
+      /* nSWBOOT0 option byte should be modified */\r
+      assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));\r
+\r
+      /* Set value and mask for nSWBOOT0 option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);\r
+      optr_reg_mask |= FLASH_OPTR_nSWBOOT0;\r
+    }\r
+\r
+    if((UserType & OB_USER_nBOOT0) != 0U)\r
+    {\r
+      /* nBOOT0 option byte should be modified */\r
+      assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));\r
+\r
+      /* Set value and mask for nBOOT0 option byte */\r
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);\r
+      optr_reg_mask |= FLASH_OPTR_nBOOT0;\r
+    }\r
+#endif\r
+\r
+    /* Configure the option bytes register */\r
+    MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);\r
+\r
+    /* Set OPTSTRT Bit */\r
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+    /* Wait for last operation to be completed */\r
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the Proprietary code readout protection of the desired addresses.\r
+  *\r
+  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be\r
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
+  * @note   To validate the PCROP options, the option bytes must be reloaded\r
+  *         through the call of the HAL_FLASH_OB_Launch() function.\r
+  *\r
+  * @param  PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).\r
+  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2\r
+  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE\r
+  *\r
+  * @param  PCROPStartAddr: specifies the start address of the Proprietary code readout protection\r
+  *          This parameter can be an address between begin and end of the bank\r
+  *\r
+  * @param  PCROPEndAddr: specifies the end address of the Proprietary code readout protection\r
+  *          This parameter can be an address between PCROPStartAddr and end of the bank\r
+  *\r
+  * @retval HAL Status\r
+  */\r
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t reg_value;\r
+  uint32_t bank1_addr;\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  uint32_t bank2_addr;\r
+#endif\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));\r
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));\r
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));\r
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));\r
+\r
+  /* Wait for last operation to be completed */\r
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+    /* Get the information about the bank swapping */\r
+    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)\r
+    {\r
+      bank1_addr = FLASH_BASE;\r
+      bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
+    }\r
+    else\r
+    {\r
+      bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
+      bank2_addr = FLASH_BASE;\r
+    }\r
+#else\r
+    bank1_addr = FLASH_BASE;\r
+#endif\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+    if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)\r
+    {\r
+      /* Configure the Proprietary code readout protection */\r
+      if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
+      {\r
+        reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);\r
+        MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);\r
+\r
+        reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);\r
+        MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);\r
+      }\r
+      else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
+      {\r
+        reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);\r
+        MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);\r
+\r
+        reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);\r
+        MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);\r
+      }\r
+      else\r
+      {\r
+        /* Nothing to do */\r
+      }\r
+    }\r
+    else\r
+#endif\r
+    {\r
+      /* Configure the Proprietary code readout protection */\r
+      if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
+      {\r
+        reg_value = ((PCROPStartAddr - bank1_addr) >> 3);\r
+        MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);\r
+\r
+        reg_value = ((PCROPEndAddr - bank1_addr) >> 3);\r
+        MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);\r
+      }\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+      else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
+      {\r
+        reg_value = ((PCROPStartAddr - bank2_addr) >> 3);\r
+        MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);\r
+\r
+        reg_value = ((PCROPEndAddr - bank2_addr) >> 3);\r
+        MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);\r
+      }\r
+#endif\r
+      else\r
+      {\r
+        /* Nothing to do */\r
+      }\r
+    }\r
+\r
+    MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));\r
+\r
+    /* Set OPTSTRT Bit */\r
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+    /* Wait for last operation to be completed */\r
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Return the FLASH Write Protection Option Bytes value.\r
+  *\r
+  * @param[in]  WRPArea: specifies the area to be returned.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A\r
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B\r
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)\r
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)\r
+  *\r
+  * @param[out]  WRPStartOffset: specifies the address where to copied the start page\r
+  *                         of the write protected area\r
+  *\r
+  * @param[out]  WRDPEndOffset: specifies the address where to copied the end page of\r
+  *                        the write protected area\r
+  *\r
+  * @retval None\r
+  */\r
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)\r
+{\r
+  /* Get the configuration of the write protected area */\r
+  if(WRPArea == OB_WRPAREA_BANK1_AREAA)\r
+  {\r
+    *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);\r
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);\r
+  }\r
+  else if(WRPArea == OB_WRPAREA_BANK1_AREAB)\r
+  {\r
+    *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);\r
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);\r
+  }\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  else if(WRPArea == OB_WRPAREA_BANK2_AREAA)\r
+  {\r
+    *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);\r
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);\r
+  }\r
+  else if(WRPArea == OB_WRPAREA_BANK2_AREAB)\r
+  {\r
+    *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);\r
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);\r
+  }\r
+#endif\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Return the FLASH Read Protection level.\r
+  * @retval FLASH ReadOut Protection Status:\r
+  *         This return value can be one of the following values:\r
+  *            @arg OB_RDP_LEVEL_0: No protection\r
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r
+  *            @arg OB_RDP_LEVEL_2: Full chip protection\r
+  */\r
+static uint32_t FLASH_OB_GetRDP(void)\r
+{\r
+  uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);\r
+\r
+  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))\r
+  {\r
+    return (OB_RDP_LEVEL_1);\r
+  }\r
+  else\r
+  {\r
+    return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Return the FLASH User Option Byte value.\r
+  * @retval The FLASH User Option Bytes values:\r
+  *      For STM32L47x/STM32L48x devices :\r
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),\r
+  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),\r
+  *         BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).\r
+  *      For STM32L43x/STM32L44x devices :\r
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),\r
+  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),\r
+  *         nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).\r
+  */\r
+static uint32_t FLASH_OB_GetUser(void)\r
+{\r
+  uint32_t user_config = READ_REG(FLASH->OPTR);\r
+  CLEAR_BIT(user_config, FLASH_OPTR_RDP);\r
+\r
+  return user_config;\r
+}\r
+\r
+/**\r
+  * @brief  Return the FLASH Write Protection Option Bytes value.\r
+  *\r
+  * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).\r
+  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2\r
+  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE\r
+  *\r
+  * @param PCROPStartAddr [out]: specifies the address where to copied the start address\r
+  *                         of the Proprietary code readout protection\r
+  *\r
+  * @param PCROPEndAddr [out]: specifies the address where to copied the end address of\r
+  *                       the Proprietary code readout protection\r
+  *\r
+  * @retval None\r
+  */\r
+static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t bank1_addr;\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  uint32_t bank2_addr;\r
+#endif\r
+\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  /* Get the information about the bank swapping */\r
+  if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)\r
+  {\r
+    bank1_addr = FLASH_BASE;\r
+    bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
+  }\r
+  else\r
+  {\r
+    bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
+    bank2_addr = FLASH_BASE;\r
+  }\r
+#else\r
+  bank1_addr = FLASH_BASE;\r
+#endif\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)\r
+  {\r
+    if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
+    {\r
+      reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);\r
+      *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;\r
+\r
+      reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);\r
+      *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;\r
+    }\r
+    else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
+    {\r
+      reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);\r
+      *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;\r
+\r
+      reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);\r
+      *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;;\r
+    }\r
+    else\r
+    {\r
+      /* Nothing to do */\r
+    }\r
+  }\r
+  else\r
+#endif\r
+  {\r
+    if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
+    {\r
+      reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);\r
+      *PCROPStartAddr = (reg_value << 3) + bank1_addr;\r
+\r
+      reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);\r
+      *PCROPEndAddr = (reg_value << 3) + bank1_addr + 0x7U;\r
+    }\r
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
+    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
+    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+    else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
+    {\r
+      reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);\r
+      *PCROPStartAddr = (reg_value << 3) + bank2_addr;\r
+\r
+      reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);\r
+      *PCROPEndAddr = (reg_value << 3) + bank2_addr + 0x7U;\r
+    }\r
+#endif\r
+    else\r
+    {\r
+      /* Nothing to do */\r
+    }\r
+  }\r
+\r
+  *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);\r
+}\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
new file mode 100644 (file)
index 0000000..7d32ef7
--- /dev/null
@@ -0,0 +1,256 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_flash_ramfunc.c\r
+  * @author  MCD Application Team\r
+  * @brief   FLASH RAMFUNC driver.\r
+  *          This file provides a Flash firmware functions which should be\r
+  *          executed from internal SRAM\r
+  *            + FLASH HalfPage Programming\r
+  *            + FLASH Power Down in Run mode\r
+  *\r
+  *  @verbatim\r
+  ==============================================================================\r
+                   ##### Flash RAM functions #####\r
+  ==============================================================================\r
+\r
+    *** ARM Compiler ***\r
+    --------------------\r
+    [..] RAM functions are defined using the toolchain options.\r
+         Functions that are executed in RAM should reside in a separate\r
+         source module. Using the 'Options for File' dialog you can simply change\r
+         the 'Code / Const' area of a module to a memory space in physical RAM.\r
+         Available memory areas are declared in the 'Target' tab of the\r
+         Options for Target' dialog.\r
+\r
+    *** ICCARM Compiler ***\r
+    -----------------------\r
+    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
+\r
+    *** GNU Compiler ***\r
+    --------------------\r
+    [..] RAM functions are defined using a specific toolchain attribute\r
+         "__attribute__((section(".RamFunc")))".\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC\r
+  * @brief FLASH functions executed from RAM\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+extern FLASH_ProcessTypeDef pFlash;\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions -------------------------------------------------------*/\r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions\r
+ *  @brief   Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### ramfunc functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions that should be executed from RAM.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief   Enable the Power down in Run Mode\r
+  * @note    This function should be called and executed from SRAM memory\r
+  * @retval None\r
+  */\r
+__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)\r
+{\r
+  /* Enable the Power Down in Run mode*/\r
+  __HAL_FLASH_POWER_DOWN_ENABLE();\r
+\r
+  return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+  * @brief   Disable the Power down in Run Mode\r
+  * @note    This function should be called and executed from SRAM memory\r
+  * @retval None\r
+  */\r
+__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)\r
+{\r
+  /* Disable the Power Down in Run mode*/\r
+  __HAL_FLASH_POWER_DOWN_DISABLE();\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+/**\r
+  * @brief  Program the FLASH DBANK User Option Byte.\r
+  *\r
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must\r
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
+  * @note   To modify the DBANK option byte, no PCROP region should be defined.\r
+  *         To deactivate PCROP, user should perform RDP changing\r
+  *\r
+  * @param  DBankConfig: The FLASH DBANK User Option Byte value.\r
+  *          This parameter  can be one of the following values:\r
+  *            @arg OB_DBANK_128_BITS: Single-bank with 128-bits data\r
+  *            @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data\r
+  *\r
+  * @retval HAL status\r
+  */\r
+__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)\r
+{\r
+  register uint32_t count, reg;\r
+  HAL_StatusTypeDef status = HAL_ERROR;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(&pFlash);\r
+\r
+  /* Check if the PCROP is disabled */\r
+  reg = FLASH->PCROP1SR;\r
+  if (reg > FLASH->PCROP1ER)\r
+  {\r
+    reg = FLASH->PCROP2SR;\r
+    if (reg > FLASH->PCROP2ER)\r
+    {\r
+      /* Disable Flash prefetch */\r
+      __HAL_FLASH_PREFETCH_BUFFER_DISABLE();\r
+\r
+      if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)\r
+      {\r
+        /* Disable Flash instruction cache */\r
+        __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
+\r
+        /* Flush Flash instruction cache */\r
+        __HAL_FLASH_INSTRUCTION_CACHE_RESET();\r
+      }\r
+\r
+      if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+      {\r
+        /* Disable Flash data cache */\r
+        __HAL_FLASH_DATA_CACHE_DISABLE();\r
+\r
+        /* Flush Flash data cache */\r
+        __HAL_FLASH_DATA_CACHE_RESET();\r
+      }\r
+\r
+      /* Disable WRP zone 1 of 1st bank if needed */\r
+      reg = FLASH->WRP1AR;\r
+      if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=\r
+          ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))\r
+      {\r
+        MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);\r
+      }\r
+\r
+      /* Disable WRP zone 2 of 1st bank if needed */\r
+      reg = FLASH->WRP1BR;\r
+      if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=\r
+          ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))\r
+      {\r
+        MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);\r
+      }\r
+\r
+      /* Disable WRP zone 1 of 2nd bank if needed */\r
+      reg = FLASH->WRP2AR;\r
+      if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=\r
+          ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))\r
+      {\r
+        MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);\r
+      }\r
+\r
+      /* Disable WRP zone 2 of 2nd bank if needed */\r
+      reg = FLASH->WRP2BR;\r
+      if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=\r
+          ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))\r
+      {\r
+        MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);\r
+      }\r
+\r
+      /* Modify the DBANK user option byte */\r
+      MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);\r
+\r
+      /* Set OPTSTRT Bit */\r
+      SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+      /* Wait for last operation to be completed */\r
+      /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */\r
+      count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);\r
+      do\r
+      {\r
+        if (count == 0U)\r
+        {\r
+          break;\r
+        }\r
+        count--;\r
+      } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);\r
+\r
+      /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
+      CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+      /* Set the bit to force the option byte reloading */\r
+      SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);\r
+    }\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(&pFlash);\r
+\r
+  return status;\r
+}\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
new file mode 100644 (file)
index 0000000..851121a
--- /dev/null
@@ -0,0 +1,557 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_gpio.c\r
+  * @author  MCD Application Team\r
+  * @brief   GPIO HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
+  *           + Initialization and de-initialization functions\r
+  *           + IO operation functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                    ##### GPIO Peripheral features #####\r
+  ==============================================================================\r
+  [..]\r
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually\r
+        configured by software in several modes:\r
+        (++) Input mode\r
+        (++) Analog mode\r
+        (++) Output mode\r
+        (++) Alternate function mode\r
+        (++) External interrupt/event lines\r
+\r
+    (+) During and just after reset, the alternate functions and external interrupt\r
+        lines are not active and the I/O ports are configured in input floating mode.\r
+\r
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be\r
+        activated or not.\r
+\r
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
+        type and the IO speed can be selected depending on the VDD value.\r
+\r
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a\r
+        multiplexer that allows only one peripheral alternate function (AF) connected\r
+       to an IO pin at a time. In this way, there can be no conflict between peripherals\r
+       sharing the same IO pin.\r
+\r
+    (+) All ports have external interrupt/event capability. To use external interrupt\r
+        lines, the port must be configured in input mode. All available GPIO pins are\r
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
+\r
+    (+) The external interrupt/event controller consists of up to 39 edge detectors\r
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each\r
+        input line can be independently configured to select the type (interrupt or event)\r
+        and the corresponding trigger event (rising or falling or both). Each line can\r
+        also be masked independently.\r
+\r
+                     ##### How to use this driver #####\r
+  ==============================================================================\r
+  [..]\r
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().\r
+\r
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef\r
+             structure.\r
+        (++) In case of Output or alternate function mode selection: the speed is\r
+             configured through "Speed" member from GPIO_InitTypeDef structure.\r
+        (++) In alternate mode is selection, the alternate function connected to the IO\r
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.\r
+        (++) Analog mode is required when a pin is to be used as ADC channel\r
+             or DAC output.\r
+        (++) In case of external interrupt/event selection the "Mode" member from\r
+             GPIO_InitTypeDef structure select the type (interrupt or event) and\r
+             the corresponding trigger event (rising or falling or both).\r
+\r
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority\r
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
+        HAL_NVIC_EnableIRQ().\r
+\r
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
+\r
+    (#) To set/reset the level of a pin configured in output mode use\r
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
+\r
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
+\r
+    (#) During and just after reset, the alternate functions are not\r
+        active and the GPIO pins are configured in input floating mode (except JTAG\r
+        pins).\r
+\r
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose\r
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has\r
+        priority over the GPIO function.\r
+\r
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as\r
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.\r
+        The HSE has priority over the GPIO function.\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO GPIO\r
+  * @brief GPIO HAL module driver\r
+  * @{\r
+  */\r
+/** MISRA C:2012 deviation rule has been granted for following rules:\r
+  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of\r
+  * range of the shift operator in following API :\r
+  * HAL_GPIO_Init\r
+  * HAL_GPIO_DeInit\r
+  */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Defines GPIO Private Defines\r
+  * @{\r
+  */\r
+#define GPIO_MODE             (0x00000003u)\r
+#define ANALOG_MODE           (0x00000008u)\r
+#define EXTI_MODE             (0x10000000u)\r
+#define GPIO_MODE_IT          (0x00010000u)\r
+#define GPIO_MODE_EVT         (0x00020000u)\r
+#define RISING_EDGE           (0x00100000u)\r
+#define FALLING_EDGE          (0x00200000u)\r
+#define GPIO_OUTPUT_TYPE      (0x00000010u)\r
+\r
+#define GPIO_NUMBER           (16u)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions\r
+ *  @brief    Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+              ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains\r
+  *         the configuration information for the specified GPIO peripheral.\r
+  * @retval None\r
+  */\r
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
+{\r
+  uint32_t position = 0x00u;\r
+  uint32_t iocurrent;\r
+  uint32_t temp;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r
+\r
+  /* Configure the port pins */\r
+  while (((GPIO_Init->Pin) >> position) != 0x00u)\r
+  {\r
+    /* Get current io position */\r
+    iocurrent = (GPIO_Init->Pin) & (1uL << position);\r
+\r
+    if (iocurrent != 0x00u)\r
+    {\r
+      /*--------------------- GPIO Mode Configuration ------------------------*/\r
+      /* In case of Alternate function mode selection */\r
+      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+      {\r
+        /* Check the Alternate function parameters */\r
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));\r
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r
+\r
+        /* Configure Alternate function mapped with the current IO */\r
+        temp = GPIOx->AFR[position >> 3u];\r
+        temp &= ~(0xFu << ((position & 0x07u) * 4u));\r
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));\r
+        GPIOx->AFR[position >> 3u] = temp;\r
+      }\r
+\r
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r
+      temp = GPIOx->MODER;\r
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));\r
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));\r
+      GPIOx->MODER = temp;\r
+\r
+      /* In case of Output or Alternate function mode selection */\r
+      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r
+         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+      {\r
+        /* Check the Speed parameter */\r
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
+        /* Configure the IO Speed */\r
+        temp = GPIOx->OSPEEDR;\r
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));\r
+        temp |= (GPIO_Init->Speed << (position * 2u));\r
+        GPIOx->OSPEEDR = temp;\r
+\r
+        /* Configure the IO Output Type */\r
+        temp = GPIOx->OTYPER;\r
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;\r
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);\r
+        GPIOx->OTYPER = temp;\r
+      }\r
+\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+\r
+      /* In case of Analog mode, check if ADC control mode is selected */\r
+      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)\r
+      {\r
+        /* Configure the IO Output Type */\r
+        temp = GPIOx->ASCR;\r
+        temp &= ~(GPIO_ASCR_ASC0 << position) ;\r
+        temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);\r
+        GPIOx->ASCR = temp;\r
+      }\r
+\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
+\r
+      /* Activate the Pull-up or Pull down resistor for the current IO */\r
+      temp = GPIOx->PUPDR;\r
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));\r
+      temp |= ((GPIO_Init->Pull) << (position * 2u));\r
+      GPIOx->PUPDR = temp;\r
+\r
+      /*--------------------- EXTI Mode Configuration ------------------------*/\r
+      /* Configure the External Interrupt or event for the current IO */\r
+      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r
+      {\r
+        /* Enable SYSCFG Clock */\r
+        __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+        temp = SYSCFG->EXTICR[position >> 2u];\r
+        temp &= ~(0x0FuL << (4u * (position & 0x03u)));\r
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));\r
+        SYSCFG->EXTICR[position >> 2u] = temp;\r
+\r
+        /* Clear EXTI line configuration */\r
+        temp = EXTI->IMR1;\r
+        temp &= ~(iocurrent);\r
+        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
+        {\r
+          temp |= iocurrent;\r
+        }\r
+        EXTI->IMR1 = temp;\r
+\r
+        temp = EXTI->EMR1;\r
+        temp &= ~(iocurrent);\r
+        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
+        {\r
+          temp |= iocurrent;\r
+        }\r
+        EXTI->EMR1 = temp;\r
+\r
+        /* Clear Rising Falling edge configuration */\r
+        temp = EXTI->RTSR1;\r
+        temp &= ~(iocurrent);\r
+        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
+        {\r
+          temp |= iocurrent;\r
+        }\r
+        EXTI->RTSR1 = temp;\r
+\r
+        temp = EXTI->FTSR1;\r
+        temp &= ~(iocurrent);\r
+        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
+        {\r
+          temp |= iocurrent;\r
+        }\r
+        EXTI->FTSR1 = temp;\r
+      }\r
+    }\r
+\r
+    position++;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.\r
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
+  * @param  GPIO_Pin: specifies the port bit to be written.\r
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)\r
+{\r
+  uint32_t position = 0x00u;\r
+  uint32_t iocurrent;\r
+  uint32_t tmp;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+  /* Configure the port pins */\r
+  while ((GPIO_Pin >> position) != 0x00u)\r
+  {\r
+    /* Get current io position */\r
+    iocurrent = (GPIO_Pin) & (1uL << position);\r
+\r
+    if (iocurrent != 0x00u)\r
+    {\r
+      /*------------------------- EXTI Mode Configuration --------------------*/\r
+      /* Clear the External Interrupt or Event for the current IO */\r
+\r
+      tmp = SYSCFG->EXTICR[position >> 2u];\r
+      tmp &= (0x0FuL << (4u * (position & 0x03u)));\r
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))\r
+      {\r
+        /* Clear EXTI line configuration */\r
+        EXTI->IMR1 &= ~(iocurrent);\r
+        EXTI->EMR1 &= ~(iocurrent);\r
+\r
+        /* Clear Rising Falling edge configuration */\r
+        EXTI->RTSR1 &= ~(iocurrent);\r
+        EXTI->FTSR1 &= ~(iocurrent);\r
+\r
+        tmp = 0x0FuL << (4u * (position & 0x03u));\r
+        SYSCFG->EXTICR[position >> 2u] &= ~tmp;\r
+      }\r
+\r
+      /*------------------------- GPIO Mode Configuration --------------------*/\r
+      /* Configure IO in Analog Mode */\r
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));\r
+\r
+      /* Configure the default Alternate Function in current IO */\r
+      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;\r
+\r
+      /* Configure the default value for IO Speed */\r
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));\r
+\r
+      /* Configure the default value IO Output Type */\r
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;\r
+\r
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));\r
+\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+      /* Deactivate the Control bit of Analog mode for the current IO */\r
+      GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
+    }\r
+\r
+    position++;\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions\r
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                       ##### IO operation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Read the specified input port pin.\r
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
+  * @param  GPIO_Pin: specifies the port bit to read.\r
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval The input port pin value.\r
+  */\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  GPIO_PinState bitstatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00u)\r
+  {\r
+    bitstatus = GPIO_PIN_SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = GPIO_PIN_RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Set or clear the selected data port bit.\r
+  *\r
+  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify\r
+  *         accesses. In this way, there is no risk of an IRQ occurring between\r
+  *         the read and the modify access.\r
+  *\r
+  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
+  * @param  GPIO_Pin specifies the port bit to be written.\r
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @param  PinState specifies the value to be written to the selected bit.\r
+  *         This parameter can be one of the GPIO_PinState enum values:\r
+  *            @arg GPIO_PIN_RESET: to clear the port pin\r
+  *            @arg GPIO_PIN_SET: to set the port pin\r
+  * @retval None\r
+  */\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+  assert_param(IS_GPIO_PIN_ACTION(PinState));\r
+\r
+  if(PinState != GPIO_PIN_RESET)\r
+  {\r
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;\r
+  }\r
+  else\r
+  {\r
+    GPIOx->BRR = (uint32_t)GPIO_Pin;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Toggle the specified GPIO pin.\r
+  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
+  * @param  GPIO_Pin specifies the pin to be toggled.\r
+  * @retval None\r
+  */\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+  if ((GPIOx->ODR & GPIO_Pin) != 0x00u)\r
+  {\r
+    GPIOx->BRR = (uint32_t)GPIO_Pin;\r
+  }\r
+  else\r
+  {\r
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;\r
+  }\r
+}\r
+\r
+/**\r
+* @brief  Lock GPIO Pins configuration registers.\r
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+  * @note   The configuration of the locked GPIO pins can no longer be modified\r
+  *         until the next reset.\r
+  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
+  * @param  GPIO_Pin specifies the port bits to be locked.\r
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+  /* Apply lock key write sequence */\r
+  tmp |= GPIO_Pin;\r
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+  GPIOx->LCKR = tmp;\r
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
+  GPIOx->LCKR = GPIO_Pin;\r
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+  GPIOx->LCKR = tmp;\r
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */\r
+  tmp = GPIOx->LCKR;\r
+\r
+  /* Read again in order to confirm lock is active */\r
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)\r
+  {\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Handle EXTI interrupt request.\r
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.\r
+  * @retval None\r
+  */\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
+{\r
+  /* EXTI line interrupt detected */\r
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)\r
+  {\r
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  EXTI line detection callback.\r
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.\r
+  * @retval None\r
+  */\r
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(GPIO_Pin);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
new file mode 100644 (file)
index 0000000..75be2ea
--- /dev/null
@@ -0,0 +1,6502 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_i2c.c\r
+  * @author  MCD Application Team\r
+  * @brief   I2C HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:\r
+  *           + Initialization and de-initialization functions\r
+  *           + IO operation functions\r
+  *           + Peripheral State and Errors functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                        ##### How to use this driver #####\r
+  ==============================================================================\r
+    [..]\r
+    The I2C HAL driver can be used as follows:\r
+\r
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:\r
+        I2C_HandleTypeDef  hi2c;\r
+\r
+    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:\r
+        (##) Enable the I2Cx interface clock\r
+        (##) I2C pins configuration\r
+            (+++) Enable the clock for the I2C GPIOs\r
+            (+++) Configure I2C pins as alternate function open-drain\r
+        (##) NVIC configuration if you need to use interrupt process\r
+            (+++) Configure the I2Cx interrupt priority\r
+            (+++) Enable the NVIC I2C IRQ Channel\r
+        (##) DMA Configuration if you need to use DMA process\r
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel\r
+            (+++) Enable the DMAx interface clock using\r
+            (+++) Configure the DMA handle parameters\r
+            (+++) Configure the DMA Tx or Rx channel\r
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\r
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on\r
+                  the DMA Tx or Rx channel\r
+\r
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,\r
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.\r
+\r
+    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware\r
+        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.\r
+\r
+    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()\r
+\r
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\r
+\r
+    *** Polling mode IO operation ***\r
+    =================================\r
+    [..]\r
+      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()\r
+      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()\r
+      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()\r
+      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()\r
+\r
+    *** Polling mode IO MEM operation ***\r
+    =====================================\r
+    [..]\r
+      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()\r
+      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()\r
+\r
+\r
+    *** Interrupt mode IO operation ***\r
+    ===================================\r
+    [..]\r
+      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()\r
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
+      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()\r
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
+      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()\r
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
+      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()\r
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
+           This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+\r
+    *** Interrupt mode or DMA mode IO sequential operation ***\r
+    ==========================================================\r
+    [..]\r
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition\r
+          when a direction change during transfer\r
+    [..]\r
+      (+) A specific option field manage the different steps of a sequential transfer\r
+      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:\r
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode\r
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address\r
+                            and data to transfer without a final stop condition\r
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address\r
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface\r
+                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()\r
+                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())\r
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address\r
+                            and with new data to transfer if the direction change or manage only the new data to transfer\r
+                            if no direction change and without a final stop condition in both cases\r
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address\r
+                            and with new data to transfer if the direction change or manage only the new data to transfer\r
+                            if no direction change and with a final stop condition in both cases\r
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential\r
+                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).\r
+                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).\r
+                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit\r
+                              without stopping the communication and so generate a restart condition.\r
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential\r
+                            interface.\r
+                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).\r
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.\r
+\r
+      (+) Differents sequential I2C interfaces are listed below:\r
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()\r
+            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()\r
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()\r
+            or using @ref HAL_I2C_Master_Seq_Receive_DMA()\r
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
+      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
+      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()\r
+      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can\r
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).\r
+      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()\r
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()\r
+            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()\r
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()\r
+            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()\r
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
+      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
+           This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+    *** Interrupt mode IO MEM operation ***\r
+    =======================================\r
+    [..]\r
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using\r
+          @ref HAL_I2C_Mem_Write_IT()\r
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\r
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using\r
+          @ref HAL_I2C_Mem_Read_IT()\r
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\r
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+\r
+    *** DMA mode IO operation ***\r
+    ==============================\r
+    [..]\r
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using\r
+          @ref HAL_I2C_Master_Transmit_DMA()\r
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using\r
+          @ref HAL_I2C_Master_Receive_DMA()\r
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using\r
+          @ref HAL_I2C_Slave_Transmit_DMA()\r
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using\r
+          @ref HAL_I2C_Slave_Receive_DMA()\r
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
+           This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+    *** DMA mode IO MEM operation ***\r
+    =================================\r
+    [..]\r
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using\r
+          @ref HAL_I2C_Mem_Write_DMA()\r
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\r
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using\r
+          @ref HAL_I2C_Mem_Read_DMA()\r
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\r
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+\r
+\r
+     *** I2C HAL driver macros list ***\r
+     ==================================\r
+     [..]\r
+       Below the list of most used macros in I2C HAL driver.\r
+\r
+      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral\r
+      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral\r
+      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode\r
+      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not\r
+      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag\r
+      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt\r
+      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\r
+\r
+     *** Callback registration ***\r
+     =============================================\r
+    [..]\r
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1\r
+     allows the user to configure dynamically the driver callbacks.\r
+     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()\r
+     to register an interrupt callback.\r
+    [..]\r
+     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:\r
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\r
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.\r
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.\r
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.\r
+       (+) ListenCpltCallback   : callback for end of listen mode.\r
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.\r
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.\r
+       (+) ErrorCallback        : callback for error detection.\r
+       (+) AbortCpltCallback    : callback for abort completion process.\r
+       (+) MspInitCallback      : callback for Msp Init.\r
+       (+) MspDeInitCallback    : callback for Msp DeInit.\r
+     This function takes as parameters the HAL peripheral handle, the Callback ID\r
+     and a pointer to the user callback function.\r
+    [..]\r
+     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().\r
+    [..]\r
+     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default\r
+     weak function.\r
+     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
+     and the Callback ID.\r
+     This function allows to reset following callbacks:\r
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\r
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.\r
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.\r
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.\r
+       (+) ListenCpltCallback   : callback for end of listen mode.\r
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.\r
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.\r
+       (+) ErrorCallback        : callback for error detection.\r
+       (+) AbortCpltCallback    : callback for abort completion process.\r
+       (+) MspInitCallback      : callback for Msp Init.\r
+       (+) MspDeInitCallback    : callback for Msp DeInit.\r
+    [..]\r
+     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().\r
+    [..]\r
+     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET\r
+     all callbacks are set to the corresponding weak functions:\r
+     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().\r
+     Exception done for MspInit and MspDeInit functions that are\r
+     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when\r
+     these callbacks are null (not registered beforehand).\r
+     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()\r
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\r
+    [..]\r
+     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.\r
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered\r
+     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,\r
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\r
+     Then, the user first registers the MspInit/MspDeInit user callbacks\r
+     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()\r
+     or @ref HAL_I2C_Init() function.\r
+    [..]\r
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or\r
+     not defined, the callback registration feature is not available and all callbacks\r
+     are set to the corresponding weak functions.\r
+\r
+     [..]\r
+       (@) You can refer to the I2C HAL driver header file for more useful macros\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2C I2C\r
+  * @brief I2C HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Define I2C Private Define\r
+  * @{\r
+  */\r
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */\r
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */\r
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */\r
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */\r
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */\r
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */\r
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */\r
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */\r
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */\r
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */\r
+\r
+#define MAX_NBYTE_SIZE      255U\r
+#define SlaveAddr_SHIFT     7U\r
+#define SlaveAddr_MSK       0x06U\r
+\r
+/* Private define for @ref PreviousState usage */\r
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */\r
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */\r
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */\r
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */\r
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */\r
+\r
+\r
+/* Private define to centralize the enable/disable of Interrupts */\r
+#define I2C_XFER_TX_IT          (0x00000001U)\r
+#define I2C_XFER_RX_IT          (0x00000002U)\r
+#define I2C_XFER_LISTEN_IT      (0x00000004U)\r
+\r
+#define I2C_XFER_ERROR_IT       (0x00000011U)\r
+#define I2C_XFER_CPLT_IT        (0x00000012U)\r
+#define I2C_XFER_RELOAD_IT      (0x00000012U)\r
+\r
+/* Private define Sequential Transfer Options default/reset value */\r
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+  * @{\r
+  */\r
+/* Private functions to handle DMA transfer */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);\r
+\r
+/* Private functions to handle IT transfer */\r
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);\r
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);\r
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);\r
+\r
+/* Private functions to handle IT transfer */\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
+\r
+/* Private functions for I2C transfer IRQ handler */\r
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+\r
+/* Private functions to handle flags during polling transfer */\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+\r
+/* Private functions to centralize the enable/disable of Interrupts */\r
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
+\r
+/* Private function to flush TXDR register */\r
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);\r
+\r
+/* Private function to handle  start, restart or stop a transfer */\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\r
+\r
+/* Private function to Convert Specific options */\r
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Functions I2C Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ *  @brief    Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+              ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+    [..]  This subsection provides a set of functions allowing to initialize and\r
+          deinitialize the I2Cx peripheral:\r
+\r
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures\r
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+      (+) Call the function HAL_I2C_Init() to configure the selected device with\r
+          the selected configuration:\r
+        (++) Clock Timing\r
+        (++) Own Address 1\r
+        (++) Addressing mode (Master, Slave)\r
+        (++) Dual Addressing mode\r
+        (++) Own Address 2\r
+        (++) Own Address 2 Mask\r
+        (++) General call mode\r
+        (++) Nostretch mode\r
+\r
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration\r
+          of the selected I2Cx peripheral.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initializes the I2C according to the specified parameters\r
+  *         in the I2C_InitTypeDef and initialize the associated handle.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Check the I2C handle allocation */\r
+  if (hi2c == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\r
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\r
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\r
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\r
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));\r
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\r
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    hi2c->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    /* Init the I2C Callback settings */\r
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\r
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\r
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */\r
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */\r
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */\r
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */\r
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */\r
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */\r
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */\r
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */\r
+\r
+    if (hi2c->MspInitCallback == NULL)\r
+    {\r
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */\r
+    }\r
+\r
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+    hi2c->MspInitCallback(hi2c);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+    HAL_I2C_MspInit(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+  /* Disable the selected I2C peripheral */\r
+  __HAL_I2C_DISABLE(hi2c);\r
+\r
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/\r
+  /* Configure I2Cx: Frequency range */\r
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;\r
+\r
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r
+  /* Disable Own Address1 before set the Own Address1 configuration */\r
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;\r
+\r
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */\r
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\r
+  {\r
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);\r
+  }\r
+  else /* I2C_ADDRESSINGMODE_10BIT */\r
+  {\r
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);\r
+  }\r
+\r
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/\r
+  /* Configure I2Cx: Addressing Master mode */\r
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+  {\r
+    hi2c->Instance->CR2 = (I2C_CR2_ADD10);\r
+  }\r
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */\r
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);\r
+\r
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\r
+  /* Disable Own Address2 before set the Own Address2 configuration */\r
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;\r
+\r
+  /* Configure I2Cx: Dual mode and Own Address2 */\r
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));\r
+\r
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/\r
+  /* Configure I2Cx: Generalcall and NoStretch mode */\r
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);\r
+\r
+  /* Enable the selected I2C peripheral */\r
+  __HAL_I2C_ENABLE(hi2c);\r
+\r
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+  hi2c->State = HAL_I2C_STATE_READY;\r
+  hi2c->PreviousState = I2C_STATE_NONE;\r
+  hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitialize the I2C peripheral.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Check the I2C handle allocation */\r
+  if (hi2c == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+\r
+  hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+  /* Disable the I2C Peripheral Clock */\r
+  __HAL_I2C_DISABLE(hi2c);\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+  if (hi2c->MspDeInitCallback == NULL)\r
+  {\r
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */\r
+  }\r
+\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+  hi2c->MspDeInitCallback(hi2c);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+  HAL_I2C_MspDeInit(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+\r
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+  hi2c->State = HAL_I2C_STATE_RESET;\r
+  hi2c->PreviousState = I2C_STATE_NONE;\r
+  hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hi2c);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Initialize the I2C MSP.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief DeInitialize the I2C MSP.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  Register a User I2C Callback\r
+  *         To be used instead of the weak predefined callback\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  CallbackID ID of the callback to be registered\r
+  *         This parameter can be one of the following values:\r
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\r
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\r
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\r
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\r
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\r
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\r
+  * @param  pCallback pointer to the Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+  /* Process locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if (HAL_I2C_STATE_READY == hi2c->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\r
+        hi2c->MasterTxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\r
+        hi2c->MasterRxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\r
+        hi2c->SlaveTxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\r
+        hi2c->SlaveRxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :\r
+        hi2c->ListenCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\r
+        hi2c->MemTxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\r
+        hi2c->MemRxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_ERROR_CB_ID :\r
+        hi2c->ErrorCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_ABORT_CB_ID :\r
+        hi2c->AbortCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_MSPINIT_CB_ID :\r
+        hi2c->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_MSPDEINIT_CB_ID :\r
+        hi2c->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (HAL_I2C_STATE_RESET == hi2c->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_I2C_MSPINIT_CB_ID :\r
+        hi2c->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_I2C_MSPDEINIT_CB_ID :\r
+        hi2c->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hi2c);\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister an I2C Callback\r
+  *         I2C callback is redirected to the weak predefined callback\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  CallbackID ID of the callback to be unregistered\r
+  *         This parameter can be one of the following values:\r
+  *         This parameter can be one of the following values:\r
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\r
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\r
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\r
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\r
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\r
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\r
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if (HAL_I2C_STATE_READY == hi2c->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\r
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\r
+        break;\r
+\r
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\r
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\r
+        break;\r
+\r
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\r
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */\r
+        break;\r
+\r
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\r
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */\r
+        break;\r
+\r
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :\r
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */\r
+        break;\r
+\r
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\r
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */\r
+        break;\r
+\r
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\r
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */\r
+        break;\r
+\r
+      case HAL_I2C_ERROR_CB_ID :\r
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */\r
+        break;\r
+\r
+      case HAL_I2C_ABORT_CB_ID :\r
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */\r
+        break;\r
+\r
+      case HAL_I2C_MSPINIT_CB_ID :\r
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */\r
+        break;\r
+\r
+      case HAL_I2C_MSPDEINIT_CB_ID :\r
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (HAL_I2C_STATE_RESET == hi2c->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_I2C_MSPINIT_CB_ID :\r
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */\r
+        break;\r
+\r
+      case HAL_I2C_MSPDEINIT_CB_ID :\r
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hi2c);\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register the Slave Address Match I2C Callback\r
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pCallback pointer to the Address Match Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+  /* Process locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if (HAL_I2C_STATE_READY == hi2c->State)\r
+  {\r
+    hi2c->AddrCallback = pCallback;\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hi2c);\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister the Slave Address Match I2C Callback\r
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if (HAL_I2C_STATE_READY == hi2c->State)\r
+  {\r
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hi2c);\r
+  return status;\r
+}\r
+\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ *  @brief   Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### IO operation functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to manage the I2C data\r
+    transfers.\r
+\r
+    (#) There are two modes of transfer:\r
+       (++) Blocking mode : The communication is performed in the polling mode.\r
+            The status of all data processing is returned by the same function\r
+            after finishing transfer.\r
+       (++) No-Blocking mode : The communication is performed using Interrupts\r
+            or DMA. These functions return the status of the transfer startup.\r
+            The end of the data processing will be indicated through the\r
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when\r
+            using DMA mode.\r
+\r
+    (#) Blocking mode functions are :\r
+        (++) HAL_I2C_Master_Transmit()\r
+        (++) HAL_I2C_Master_Receive()\r
+        (++) HAL_I2C_Slave_Transmit()\r
+        (++) HAL_I2C_Slave_Receive()\r
+        (++) HAL_I2C_Mem_Write()\r
+        (++) HAL_I2C_Mem_Read()\r
+        (++) HAL_I2C_IsDeviceReady()\r
+\r
+    (#) No-Blocking mode functions with Interrupt are :\r
+        (++) HAL_I2C_Master_Transmit_IT()\r
+        (++) HAL_I2C_Master_Receive_IT()\r
+        (++) HAL_I2C_Slave_Transmit_IT()\r
+        (++) HAL_I2C_Slave_Receive_IT()\r
+        (++) HAL_I2C_Mem_Write_IT()\r
+        (++) HAL_I2C_Mem_Read_IT()\r
+        (++) HAL_I2C_Master_Seq_Transmit_IT()\r
+        (++) HAL_I2C_Master_Seq_Receive_IT()\r
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()\r
+        (++) HAL_I2C_Slave_Seq_Receive_IT()\r
+        (++) HAL_I2C_EnableListen_IT()\r
+        (++) HAL_I2C_DisableListen_IT()\r
+        (++) HAL_I2C_Master_Abort_IT()\r
+\r
+    (#) No-Blocking mode functions with DMA are :\r
+        (++) HAL_I2C_Master_Transmit_DMA()\r
+        (++) HAL_I2C_Master_Receive_DMA()\r
+        (++) HAL_I2C_Slave_Transmit_DMA()\r
+        (++) HAL_I2C_Slave_Receive_DMA()\r
+        (++) HAL_I2C_Mem_Write_DMA()\r
+        (++) HAL_I2C_Mem_Read_DMA()\r
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()\r
+        (++) HAL_I2C_Master_Seq_Receive_DMA()\r
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()\r
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()\r
+\r
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+        (++) HAL_I2C_MasterTxCpltCallback()\r
+        (++) HAL_I2C_MasterRxCpltCallback()\r
+        (++) HAL_I2C_SlaveTxCpltCallback()\r
+        (++) HAL_I2C_SlaveRxCpltCallback()\r
+        (++) HAL_I2C_MemTxCpltCallback()\r
+        (++) HAL_I2C_MemRxCpltCallback()\r
+        (++) HAL_I2C_AddrCallback()\r
+        (++) HAL_I2C_ListenCpltCallback()\r
+        (++) HAL_I2C_ErrorCallback()\r
+        (++) HAL_I2C_AbortCpltCallback()\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Transmits in master mode an amount of data in blocking mode.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr  = pData;\r
+    hi2c->XferCount = Size;\r
+    hi2c->XferISR   = NULL;\r
+\r
+    /* Send Slave Address */\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+    }\r
+\r
+    while (hi2c->XferCount > 0U)\r
+    {\r
+      /* Wait until TXIS flag is set */\r
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Write data to TXDR */\r
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferCount--;\r
+      hi2c->XferSize--;\r
+\r
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+      {\r
+        /* Wait until TCR flag is set */\r
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+        {\r
+          hi2c->XferSize = MAX_NBYTE_SIZE;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+        else\r
+        {\r
+          hi2c->XferSize = hi2c->XferCount;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+      }\r
+    }\r
+\r
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+    /* Wait until STOPF flag is set */\r
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Clear STOP Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+    /* Clear Configuration Register 2 */\r
+    I2C_RESET_CR2(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Receives in master mode an amount of data in blocking mode.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr  = pData;\r
+    hi2c->XferCount = Size;\r
+    hi2c->XferISR   = NULL;\r
+\r
+    /* Send Slave Address */\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+    }\r
+\r
+    while (hi2c->XferCount > 0U)\r
+    {\r
+      /* Wait until RXNE flag is set */\r
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Read data from RXDR */\r
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferSize--;\r
+      hi2c->XferCount--;\r
+\r
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+      {\r
+        /* Wait until TCR flag is set */\r
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+        {\r
+          hi2c->XferSize = MAX_NBYTE_SIZE;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+        else\r
+        {\r
+          hi2c->XferSize = hi2c->XferCount;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+      }\r
+    }\r
+\r
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+    /* Wait until STOPF flag is set */\r
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Clear STOP Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+    /* Clear Configuration Register 2 */\r
+    I2C_RESET_CR2(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Transmits in slave mode an amount of data in blocking mode.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr  = pData;\r
+    hi2c->XferCount = Size;\r
+    hi2c->XferISR   = NULL;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Wait until ADDR flag is set */\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Clear ADDR flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+    /* If 10bit addressing mode is selected */\r
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+    {\r
+      /* Wait until ADDR flag is set */\r
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+      {\r
+        /* Disable Address Acknowledge */\r
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Clear ADDR flag */\r
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+    }\r
+\r
+    /* Wait until DIR flag is set Transmitter mode */\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    while (hi2c->XferCount > 0U)\r
+    {\r
+      /* Wait until TXIS flag is set */\r
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+      {\r
+        /* Disable Address Acknowledge */\r
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Write data to TXDR */\r
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferCount--;\r
+    }\r
+\r
+    /* Wait until STOP flag is set */\r
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+      {\r
+        /* Normal use case for Transmitter mode */\r
+        /* A NACK is generated to confirm the end of transfer */\r
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+      }\r
+      else\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+\r
+    /* Clear STOP flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+    /* Wait until BUSY flag is reset */\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Disable Address Acknowledge */\r
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Receive in slave mode an amount of data in blocking mode\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr  = pData;\r
+    hi2c->XferCount = Size;\r
+    hi2c->XferISR   = NULL;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Wait until ADDR flag is set */\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Clear ADDR flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+    /* Wait until DIR flag is reset Receiver mode */\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    while (hi2c->XferCount > 0U)\r
+    {\r
+      /* Wait until RXNE flag is set */\r
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+      {\r
+        /* Disable Address Acknowledge */\r
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+        /* Store Last receive data if any */\r
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r
+        {\r
+          /* Read data from RXDR */\r
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+          /* Increment Buffer pointer */\r
+          hi2c->pBuffPtr++;\r
+\r
+          hi2c->XferCount--;\r
+        }\r
+\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Read data from RXDR */\r
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferCount--;\r
+    }\r
+\r
+    /* Wait until STOP flag is set */\r
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Clear STOP flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+    /* Wait until BUSY flag is reset */\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Disable Address Acknowledge */\r
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Disable Address Acknowledge */\r
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t xfermode;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_IT;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    /* Send Slave Address */\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+\r
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+    /* possible to enable all of these */\r
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t xfermode;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_IT;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    /* Send Slave Address */\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+\r
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+    /* possible to enable all of these */\r
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+\r
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+    /* possible to enable all of these */\r
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+\r
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+    /* possible to enable all of these */\r
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t xfermode;\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    if (hi2c->XferSize > 0U)\r
+    {\r
+      if (hi2c->hdmatx != NULL)\r
+      {\r
+        /* Set the I2C DMA transfer complete callback */\r
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+\r
+        /* Set the DMA error callback */\r
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+        /* Set the unused DMA callbacks to NULL */\r
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+        hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+        /* Enable the DMA channel */\r
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      if (dmaxferstatus == HAL_OK)\r
+      {\r
+        /* Send Slave Address */\r
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
+\r
+        /* Update XferCount value */\r
+        hi2c->XferCount -= hi2c->XferSize;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                  to avoid the risk of I2C interrupt handle execution before current\r
+                  process unlock */\r
+        /* Enable ERR and NACK interrupts */\r
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+        /* Enable DMA Request */\r
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Update Transfer ISR function pointer */\r
+      hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+      /* Send Slave Address */\r
+      /* Set NBYTES to write and generate START condition */\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+      /* possible to enable all of these */\r
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t xfermode;\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    if (hi2c->XferSize > 0U)\r
+    {\r
+      if (hi2c->hdmarx != NULL)\r
+      {\r
+        /* Set the I2C DMA transfer complete callback */\r
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+\r
+        /* Set the DMA error callback */\r
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+        /* Set the unused DMA callbacks to NULL */\r
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+        hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+        /* Enable the DMA channel */\r
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      if (dmaxferstatus == HAL_OK)\r
+      {\r
+        /* Send Slave Address */\r
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+        /* Update XferCount value */\r
+        hi2c->XferCount -= hi2c->XferSize;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                  to avoid the risk of I2C interrupt handle execution before current\r
+                  process unlock */\r
+        /* Enable ERR and NACK interrupts */\r
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+        /* Enable DMA Request */\r
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Update Transfer ISR function pointer */\r
+      hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+      /* Send Slave Address */\r
+      /* Set NBYTES to read and generate START condition */\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+      /* possible to enable all of these */\r
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
+\r
+    if (hi2c->hdmatx != NULL)\r
+    {\r
+      /* Set the I2C DMA transfer complete callback */\r
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+      /* Set the unused DMA callbacks to NULL */\r
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+      hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the DMA channel */\r
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (dmaxferstatus == HAL_OK)\r
+    {\r
+      /* Enable Address Acknowledge */\r
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+      /* Enable DMA Request */\r
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
+\r
+    if (hi2c->hdmarx != NULL)\r
+    {\r
+      /* Set the I2C DMA transfer complete callback */\r
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+      /* Set the unused DMA callbacks to NULL */\r
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+      hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the DMA channel */\r
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (dmaxferstatus == HAL_OK)\r
+    {\r
+      /* Enable Address Acknowledge */\r
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+      /* Enable DMA Request */\r
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+/**\r
+  * @brief  Write an amount of data in blocking mode to a specific memory address\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MEM;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr  = pData;\r
+    hi2c->XferCount = Size;\r
+    hi2c->XferISR   = NULL;\r
+\r
+    /* Send Slave Address and Memory Address */\r
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+    }\r
+\r
+    do\r
+    {\r
+      /* Wait until TXIS flag is set */\r
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Write data to TXDR */\r
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferCount--;\r
+      hi2c->XferSize--;\r
+\r
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+      {\r
+        /* Wait until TCR flag is set */\r
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+        {\r
+          hi2c->XferSize = MAX_NBYTE_SIZE;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+        else\r
+        {\r
+          hi2c->XferSize = hi2c->XferCount;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+      }\r
+\r
+    }\r
+    while (hi2c->XferCount > 0U);\r
+\r
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+    /* Wait until STOPF flag is reset */\r
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Clear STOP Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+    /* Clear Configuration Register 2 */\r
+    I2C_RESET_CR2(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Read an amount of data in blocking mode from a specific memory address\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MEM;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr  = pData;\r
+    hi2c->XferCount = Size;\r
+    hi2c->XferISR   = NULL;\r
+\r
+    /* Send Slave Address and Memory Address */\r
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Send Slave Address */\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+    }\r
+\r
+    do\r
+    {\r
+      /* Wait until RXNE flag is set */\r
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Read data from RXDR */\r
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferSize--;\r
+      hi2c->XferCount--;\r
+\r
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+      {\r
+        /* Wait until TCR flag is set */\r
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+        {\r
+          hi2c->XferSize = MAX_NBYTE_SIZE;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+        else\r
+        {\r
+          hi2c->XferSize = hi2c->XferCount;\r
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+      }\r
+    }\r
+    while (hi2c->XferCount > 0U);\r
+\r
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+    /* Wait until STOPF flag is reset */\r
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Clear STOP Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+    /* Clear Configuration Register 2 */\r
+    I2C_RESET_CR2(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+/**\r
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t tickstart;\r
+  uint32_t xfermode;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_IT;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    /* Send Slave Address and Memory Address */\r
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+    {\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+\r
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+    /* possible to enable all of these */\r
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t tickstart;\r
+  uint32_t xfermode;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_IT;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    /* Send Slave Address and Memory Address */\r
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+    {\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+\r
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+    /* possible to enable all of these */\r
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+/**\r
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t tickstart;\r
+  uint32_t xfermode;\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    /* Send Slave Address and Memory Address */\r
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+    {\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+      return HAL_ERROR;\r
+    }\r
+\r
+\r
+    if (hi2c->hdmatx != NULL)\r
+    {\r
+      /* Set the I2C DMA transfer complete callback */\r
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+      /* Set the unused DMA callbacks to NULL */\r
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+      hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the DMA channel */\r
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_READY;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (dmaxferstatus == HAL_OK)\r
+    {\r
+      /* Send Slave Address */\r
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+\r
+      /* Update XferCount value */\r
+      hi2c->XferCount -= hi2c->XferSize;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR and NACK interrupts */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+      /* Enable DMA Request */\r
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_READY;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be read\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+  uint32_t tickstart;\r
+  uint32_t xfermode;\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Init tickstart for timeout management*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
+\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = I2C_AUTOEND_MODE;\r
+    }\r
+\r
+    /* Send Slave Address and Memory Address */\r
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+    {\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (hi2c->hdmarx != NULL)\r
+    {\r
+      /* Set the I2C DMA transfer complete callback */\r
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+      /* Set the unused DMA callbacks to NULL */\r
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+      hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the DMA channel */\r
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_READY;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (dmaxferstatus == HAL_OK)\r
+    {\r
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+      /* Update XferCount value */\r
+      hi2c->XferCount -= hi2c->XferSize;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR and NACK interrupts */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+      /* Enable DMA Request */\r
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_READY;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Checks if target device is ready for communication.\r
+  * @note   This function is used with Memory devices\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  Trials Number of trials\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  __IO uint32_t I2C_Trials = 0UL;\r
+\r
+  FlagStatus tmp1;\r
+  FlagStatus tmp2;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+    {\r
+      return HAL_BUSY;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_BUSY;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    do\r
+    {\r
+      /* Generate Start */\r
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);\r
+\r
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+      /* Wait until STOPF flag is set or a NACK flag is set*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);\r
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+      while ((tmp1 == RESET) && (tmp2 == RESET))\r
+      {\r
+        if (Timeout != HAL_MAX_DELAY)\r
+        {\r
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+          {\r
+            /* Update I2C state */\r
+            hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+            /* Update I2C error code */\r
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+\r
+            /* Process Unlocked */\r
+            __HAL_UNLOCK(hi2c);\r
+\r
+            return HAL_ERROR;\r
+          }\r
+        }\r
+\r
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);\r
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\r
+      }\r
+\r
+      /* Check if the NACKF flag has not been set */\r
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)\r
+      {\r
+        /* Wait until STOPF flag is reset */\r
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        /* Clear STOP Flag */\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+        /* Device is ready */\r
+        hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_OK;\r
+      }\r
+      else\r
+      {\r
+        /* Wait until STOPF flag is reset */\r
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        /* Clear NACK Flag */\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+        /* Clear STOP Flag, auto generated with autoend*/\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+      }\r
+\r
+      /* Check if the maximum allowed number of trials has been reached */\r
+      if (I2C_Trials == Trials)\r
+      {\r
+        /* Generate Stop */\r
+        hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+\r
+        /* Wait until STOPF flag is reset */\r
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        /* Clear STOP Flag */\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+      }\r
+\r
+      /* Increment Trials */\r
+      I2C_Trials++;\r
+    }\r
+    while (I2C_Trials < Trials);\r
+\r
+    /* Update I2C state */\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Update I2C error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  uint32_t xfermode;\r
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Master_ISR_IT;\r
+\r
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = hi2c->XferOptions;\r
+    }\r
+\r
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+    /* Mean Previous state is same as current state */\r
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+    {\r
+      xferrequest = I2C_NO_STARTSTOP;\r
+    }\r
+    else\r
+    {\r
+      /* Convert OTHER_xxx XferOptions if any */\r
+      I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+      /* Update xfermode accordingly if no reload is necessary */\r
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+      {\r
+        xfermode = hi2c->XferOptions;\r
+      }\r
+    }\r
+\r
+    /* Send Slave Address and set NBYTES to write */\r
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  uint32_t xfermode;\r
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
+\r
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = hi2c->XferOptions;\r
+    }\r
+\r
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+    /* Mean Previous state is same as current state */\r
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+    {\r
+      xferrequest = I2C_NO_STARTSTOP;\r
+    }\r
+    else\r
+    {\r
+      /* Convert OTHER_xxx XferOptions if any */\r
+      I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+      /* Update xfermode accordingly if no reload is necessary */\r
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+      {\r
+        xfermode = hi2c->XferOptions;\r
+      }\r
+    }\r
+\r
+    if (hi2c->XferSize > 0U)\r
+    {\r
+      if (hi2c->hdmatx != NULL)\r
+      {\r
+        /* Set the I2C DMA transfer complete callback */\r
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+\r
+        /* Set the DMA error callback */\r
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+        /* Set the unused DMA callbacks to NULL */\r
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+        hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+        /* Enable the DMA channel */\r
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      if (dmaxferstatus == HAL_OK)\r
+      {\r
+        /* Send Slave Address and set NBYTES to write */\r
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+        /* Update XferCount value */\r
+        hi2c->XferCount -= hi2c->XferSize;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                  to avoid the risk of I2C interrupt handle execution before current\r
+                  process unlock */\r
+        /* Enable ERR and NACK interrupts */\r
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+        /* Enable DMA Request */\r
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Update Transfer ISR function pointer */\r
+      hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+      /* Send Slave Address */\r
+      /* Set NBYTES to write and generate START condition */\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+      /* possible to enable all of these */\r
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  uint32_t xfermode;\r
+  uint32_t xferrequest = I2C_GENERATE_START_READ;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Master_ISR_IT;\r
+\r
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = hi2c->XferOptions;\r
+    }\r
+\r
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+    /* Mean Previous state is same as current state */\r
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+    {\r
+      xferrequest = I2C_NO_STARTSTOP;\r
+    }\r
+    else\r
+    {\r
+      /* Convert OTHER_xxx XferOptions if any */\r
+      I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+      /* Update xfermode accordingly if no reload is necessary */\r
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+      {\r
+        xfermode = hi2c->XferOptions;\r
+      }\r
+    }\r
+\r
+    /* Send Slave Address and set NBYTES to read */\r
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  uint32_t xfermode;\r
+  uint32_t xferrequest = I2C_GENERATE_START_READ;\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
+\r
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+      xfermode = I2C_RELOAD_MODE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+      xfermode = hi2c->XferOptions;\r
+    }\r
+\r
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+    /* Mean Previous state is same as current state */\r
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+    {\r
+      xferrequest = I2C_NO_STARTSTOP;\r
+    }\r
+    else\r
+    {\r
+      /* Convert OTHER_xxx XferOptions if any */\r
+      I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+      /* Update xfermode accordingly if no reload is necessary */\r
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+      {\r
+        xfermode = hi2c->XferOptions;\r
+      }\r
+    }\r
+\r
+    if (hi2c->XferSize > 0U)\r
+    {\r
+      if (hi2c->hdmarx != NULL)\r
+      {\r
+        /* Set the I2C DMA transfer complete callback */\r
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+\r
+        /* Set the DMA error callback */\r
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+        /* Set the unused DMA callbacks to NULL */\r
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+        hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+        /* Enable the DMA channel */\r
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      if (dmaxferstatus == HAL_OK)\r
+      {\r
+        /* Send Slave Address and set NBYTES to read */\r
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+        /* Update XferCount value */\r
+        hi2c->XferCount -= hi2c->XferSize;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                  to avoid the risk of I2C interrupt handle execution before current\r
+                  process unlock */\r
+        /* Enable ERR and NACK interrupts */\r
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+        /* Enable DMA Request */\r
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+      }\r
+      else\r
+      {\r
+        /* Update I2C state */\r
+        hi2c->State     = HAL_I2C_STATE_READY;\r
+        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+        /* Update I2C error code */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Update Transfer ISR function pointer */\r
+      hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+      /* Send Slave Address */\r
+      /* Set NBYTES to read and generate START condition */\r
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Note : The I2C interrupts must be enabled after unlocking current process\r
+                to avoid the risk of I2C interrupt handle execution before current\r
+                process unlock */\r
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+      /* possible to enable all of these */\r
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+    }\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+    /* and then toggle the HAL slave RX state to TX state */\r
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+    {\r
+      /* Disable associated Interrupts */\r
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+      /* Abort DMA Xfer if any */\r
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+      {\r
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+        if (hi2c->hdmarx != NULL)\r
+        {\r
+          /* Set the I2C DMA Abort callback :\r
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+          /* Abort DMA RX */\r
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+          {\r
+            /* Call Directly XferAbortCallback function in case of error */\r
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+          }\r
+        }\r
+      }\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\r
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
+\r
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r
+    {\r
+      /* Clear ADDR flag after prepare the transfer parameters */\r
+      /* This action will generate an acknowledge to the Master */\r
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+    }\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+    to avoid the risk of I2C interrupt handle execution before current\r
+    process unlock */\r
+    /* REnable ADDR interrupt */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r
+\r
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+    /* and then toggle the HAL slave RX state to TX state */\r
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+    {\r
+      /* Disable associated Interrupts */\r
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+      {\r
+        /* Abort DMA Xfer if any */\r
+        if (hi2c->hdmarx != NULL)\r
+        {\r
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+          /* Set the I2C DMA Abort callback :\r
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+          /* Abort DMA RX */\r
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+          {\r
+            /* Call Directly XferAbortCallback function in case of error */\r
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+          }\r
+        }\r
+      }\r
+    }\r
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+    {\r
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+      {\r
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+        /* Abort DMA Xfer if any */\r
+        if (hi2c->hdmatx != NULL)\r
+        {\r
+          /* Set the I2C DMA Abort callback :\r
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+          /* Abort DMA TX */\r
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+          {\r
+            /* Call Directly XferAbortCallback function in case of error */\r
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+          }\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Nothing to do */\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\r
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
+\r
+    if (hi2c->hdmatx != NULL)\r
+    {\r
+      /* Set the I2C DMA transfer complete callback */\r
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+      /* Set the unused DMA callbacks to NULL */\r
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+      hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the DMA channel */\r
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (dmaxferstatus == HAL_OK)\r
+    {\r
+      /* Update XferCount value */\r
+      hi2c->XferCount -= hi2c->XferSize;\r
+\r
+      /* Reset XferSize */\r
+      hi2c->XferSize = 0;\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r
+    {\r
+      /* Clear ADDR flag after prepare the transfer parameters */\r
+      /* This action will generate an acknowledge to the Master */\r
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+    }\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+    to avoid the risk of I2C interrupt handle execution before current\r
+    process unlock */\r
+    /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+    /* Enable DMA Request */\r
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+    /* and then toggle the HAL slave TX state to RX state */\r
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+    {\r
+      /* Disable associated Interrupts */\r
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+      {\r
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+        /* Abort DMA Xfer if any */\r
+        if (hi2c->hdmatx != NULL)\r
+        {\r
+          /* Set the I2C DMA Abort callback :\r
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+          /* Abort DMA TX */\r
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+          {\r
+            /* Call Directly XferAbortCallback function in case of error */\r
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+          }\r
+        }\r
+      }\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\r
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
+\r
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r
+    {\r
+      /* Clear ADDR flag after prepare the transfer parameters */\r
+      /* This action will generate an acknowledge to the Master */\r
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+    }\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+    to avoid the risk of I2C interrupt handle execution before current\r
+    process unlock */\r
+    /* REnable ADDR interrupt */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA\r
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  pData Pointer to data buffer\r
+  * @param  Size Amount of data to be sent\r
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+  HAL_StatusTypeDef dmaxferstatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r
+\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+    /* and then toggle the HAL slave TX state to RX state */\r
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+    {\r
+      /* Disable associated Interrupts */\r
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+      {\r
+        /* Abort DMA Xfer if any */\r
+        if (hi2c->hdmatx != NULL)\r
+        {\r
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+          /* Set the I2C DMA Abort callback :\r
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+          /* Abort DMA TX */\r
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+          {\r
+            /* Call Directly XferAbortCallback function in case of error */\r
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+          }\r
+        }\r
+      }\r
+    }\r
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+    {\r
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+      {\r
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+        /* Abort DMA Xfer if any */\r
+        if (hi2c->hdmarx != NULL)\r
+        {\r
+          /* Set the I2C DMA Abort callback :\r
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+          /* Abort DMA RX */\r
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+          {\r
+            /* Call Directly XferAbortCallback function in case of error */\r
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+          }\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Nothing to do */\r
+    }\r
+\r
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\r
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+    /* Enable Address Acknowledge */\r
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+    /* Prepare transfer parameters */\r
+    hi2c->pBuffPtr    = pData;\r
+    hi2c->XferCount   = Size;\r
+    hi2c->XferSize    = hi2c->XferCount;\r
+    hi2c->XferOptions = XferOptions;\r
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
+\r
+    if (hi2c->hdmarx != NULL)\r
+    {\r
+      /* Set the I2C DMA transfer complete callback */\r
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+      /* Set the unused DMA callbacks to NULL */\r
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+      hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the DMA channel */\r
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (dmaxferstatus == HAL_OK)\r
+    {\r
+      /* Update XferCount value */\r
+      hi2c->XferCount -= hi2c->XferSize;\r
+\r
+      /* Reset XferSize */\r
+      hi2c->XferSize = 0;\r
+    }\r
+    else\r
+    {\r
+      /* Update I2C state */\r
+      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
+      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
+\r
+      /* Update I2C error code */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r
+    {\r
+      /* Clear ADDR flag after prepare the transfer parameters */\r
+      /* This action will generate an acknowledge to the Master */\r
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+    }\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+    to avoid the risk of I2C interrupt handle execution before current\r
+    process unlock */\r
+    /* REnable ADDR interrupt */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+    /* Enable DMA Request */\r
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enable the Address listen mode with Interrupt.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)\r
+{\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    hi2c->State = HAL_I2C_STATE_LISTEN;\r
+    hi2c->XferISR = I2C_Slave_ISR_IT;\r
+\r
+    /* Enable the Address Match interrupt */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Disable the Address listen mode with Interrupt.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */\r
+  uint32_t tmp;\r
+\r
+  /* Disable Address listen mode only if a transfer is not ongoing */\r
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)\r
+  {\r
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;\r
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode = HAL_I2C_MODE_NONE;\r
+    hi2c->XferISR = NULL;\r
+\r
+    /* Disable the Address Match interrupt */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)\r
+{\r
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    /* Disable Interrupts */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+    /* Set State at HAL_I2C_STATE_ABORT */\r
+    hi2c->State = HAL_I2C_STATE_ABORT;\r
+\r
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */\r
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */\r
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Note : The I2C interrupts must be enabled after unlocking current process\r
+              to avoid the risk of I2C interrupt handle execution before current\r
+              process unlock */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    /* Wrong usage of abort function */\r
+    /* This function should be used only in case of abort monitored by master device */\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */\r
+\r
+/**\r
+  * @brief  This function handles I2C event interrupt request.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Get current IT Flags and IT sources value */\r
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
+\r
+  /* I2C events treatment -------------------------------------*/\r
+  if (hi2c->XferISR != NULL)\r
+  {\r
+    hi2c->XferISR(hi2c, itflags, itsources);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles I2C error interrupt request.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
+  uint32_t tmperror;\r
+\r
+  /* I2C Bus error interrupt occurred ------------------------------------*/\r
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
+  {\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;\r
+\r
+    /* Clear BERR flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\r
+  }\r
+\r
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/\r
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
+  {\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;\r
+\r
+    /* Clear OVR flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\r
+  }\r
+\r
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/\r
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
+  {\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;\r
+\r
+    /* Clear ARLO flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\r
+  }\r
+\r
+  /* Store current volatile hi2c->ErrorCode, misra rule */\r
+  tmperror = hi2c->ErrorCode;\r
+\r
+  /* Call the Error Callback in case of Error detected */\r
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)\r
+  {\r
+    I2C_ITError(hi2c, tmperror);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Master Tx Transfer completed callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Master Rx Transfer completed callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/** @brief  Slave Tx Transfer completed callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Slave Rx Transfer completed callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Slave Address Match callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION\r
+  * @param  AddrMatchCode Address Match Code\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+  UNUSED(TransferDirection);\r
+  UNUSED(AddrMatchCode);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_AddrCallback() could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Listen Complete callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Memory Tx Transfer completed callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Memory Rx Transfer completed callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  I2C error callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_ErrorCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  I2C abort callback.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval None\r
+  */\r
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hi2c);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
+ *  @brief   Peripheral State, Mode and Error functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+            ##### Peripheral State, Mode and Error functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection permit to get in run-time the status of the peripheral\r
+    and the data flow.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Return the I2C handle state.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @retval HAL state\r
+  */\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Return I2C handle state */\r
+  return hi2c->State;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *         the configuration information for I2C module\r
+  * @retval HAL mode\r
+  */\r
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)\r
+{\r
+  return hi2c->Mode;\r
+}\r
+\r
+/**\r
+* @brief  Return the I2C error code.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *              the configuration information for the specified I2C.\r
+* @retval I2C Error Code\r
+*/\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\r
+{\r
+  return hi2c->ErrorCode;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup I2C_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @param  ITSources Interrupt sources enabled.\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+  uint16_t devaddress;\r
+  uint32_t tmpITFlags = ITFlags;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+  {\r
+    /* Clear NACK Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+    /* Set corresponding Error Code */\r
+    /* No need to generate STOP, it is automatically done */\r
+    /* Error callback will be send during stop flag treatment */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+    /* Flush TX register */\r
+    I2C_Flush_TXDR(hi2c);\r
+  }\r
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))\r
+  {\r
+    /* Remove RXNE flag on temporary variable as read done */\r
+    tmpITFlags &= ~I2C_FLAG_RXNE;\r
+\r
+    /* Read data from RXDR */\r
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+    /* Increment Buffer pointer */\r
+    hi2c->pBuffPtr++;\r
+\r
+    hi2c->XferSize--;\r
+    hi2c->XferCount--;\r
+  }\r
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))\r
+  {\r
+    /* Write data to TXDR */\r
+    hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+    /* Increment Buffer pointer */\r
+    hi2c->pBuffPtr++;\r
+\r
+    hi2c->XferSize--;\r
+    hi2c->XferCount--;\r
+  }\r
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+  {\r
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+    {\r
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+\r
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+      {\r
+        hi2c->XferSize = MAX_NBYTE_SIZE;\r
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+      }\r
+      else\r
+      {\r
+        hi2c->XferSize = hi2c->XferCount;\r
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+        {\r
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);\r
+        }\r
+        else\r
+        {\r
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Call TxCpltCallback() if no stop mode is set */\r
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+      {\r
+        /* Call I2C Master Sequential complete process */\r
+        I2C_ITMasterSeqCplt(hi2c);\r
+      }\r
+      else\r
+      {\r
+        /* Wrong size Status regarding TCR flag event */\r
+        /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+      }\r
+    }\r
+  }\r
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+  {\r
+    if (hi2c->XferCount == 0U)\r
+    {\r
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+      {\r
+        /* Generate a stop condition in case of no transfer option */\r
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)\r
+        {\r
+          /* Generate Stop */\r
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+        }\r
+        else\r
+        {\r
+          /* Call I2C Master Sequential complete process */\r
+          I2C_ITMasterSeqCplt(hi2c);\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Wrong size Status regarding TC flag event */\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+\r
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+  {\r
+    /* Call I2C Master complete process */\r
+    I2C_ITMasterCplt(hi2c, tmpITFlags);\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hi2c);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @param  ITSources Interrupt sources enabled.\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+  uint32_t tmpoptions = hi2c->XferOptions;\r
+  uint32_t tmpITFlags = ITFlags;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+  {\r
+    /* Check that I2C transfer finished */\r
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
+    /* Mean XferCount == 0*/\r
+    /* So clear Flag NACKF only */\r
+    if (hi2c->XferCount == 0U)\r
+    {\r
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */\r
+      {\r
+        /* Call I2C Listen complete process */\r
+        I2C_ITListenCplt(hi2c, tmpITFlags);\r
+      }\r
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))\r
+      {\r
+        /* Clear NACK Flag */\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+        /* Flush TX register */\r
+        I2C_Flush_TXDR(hi2c);\r
+\r
+        /* Last Byte is Transmitted */\r
+        /* Call I2C Slave Sequential complete process */\r
+        I2C_ITSlaveSeqCplt(hi2c);\r
+      }\r
+      else\r
+      {\r
+        /* Clear NACK Flag */\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
+      /* Clear NACK Flag */\r
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+      /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))\r
+      {\r
+        /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+        I2C_ITError(hi2c, hi2c->ErrorCode);\r
+      }\r
+    }\r
+  }\r
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))\r
+  {\r
+    if (hi2c->XferCount > 0U)\r
+    {\r
+      /* Remove RXNE flag on temporary variable as read done */\r
+      tmpITFlags &= ~I2C_FLAG_RXNE;\r
+\r
+      /* Read data from RXDR */\r
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferSize--;\r
+      hi2c->XferCount--;\r
+    }\r
+\r
+    if ((hi2c->XferCount == 0U) && \\r
+        (tmpoptions != I2C_NO_OPTION_FRAME))\r
+    {\r
+      /* Call I2C Slave Sequential complete process */\r
+      I2C_ITSlaveSeqCplt(hi2c);\r
+    }\r
+  }\r
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))\r
+  {\r
+    I2C_ITAddrCplt(hi2c, tmpITFlags);\r
+  }\r
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))\r
+  {\r
+    /* Write data to TXDR only if XferCount not reach "0" */\r
+    /* A TXIS flag can be set, during STOP treatment      */\r
+    /* Check if all Datas have already been sent */\r
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */\r
+    if (hi2c->XferCount > 0U)\r
+    {\r
+      /* Write data to TXDR */\r
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+      /* Increment Buffer pointer */\r
+      hi2c->pBuffPtr++;\r
+\r
+      hi2c->XferCount--;\r
+      hi2c->XferSize--;\r
+    }\r
+    else\r
+    {\r
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))\r
+      {\r
+        /* Last Byte is Transmitted */\r
+        /* Call I2C Slave Sequential complete process */\r
+        I2C_ITSlaveSeqCplt(hi2c);\r
+      }\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+\r
+  /* Check if STOPF is set */\r
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+  {\r
+    /* Call I2C Slave complete process */\r
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hi2c);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @param  ITSources Interrupt sources enabled.\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+  uint16_t devaddress;\r
+  uint32_t xfermode;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+  {\r
+    /* Clear NACK Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+    /* Set corresponding Error Code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+    /* No need to generate STOP, it is automatically done */\r
+    /* But enable STOP interrupt, to treat it */\r
+    /* Error callback will be send during stop flag treatment */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+\r
+    /* Flush TX register */\r
+    I2C_Flush_TXDR(hi2c);\r
+  }\r
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+  {\r
+    /* Disable TC interrupt */\r
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);\r
+\r
+    if (hi2c->XferCount != 0U)\r
+    {\r
+      /* Recover Slave address */\r
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+\r
+      /* Prepare the new XferSize to transfer */\r
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+      {\r
+        hi2c->XferSize = MAX_NBYTE_SIZE;\r
+        xfermode = I2C_RELOAD_MODE;\r
+      }\r
+      else\r
+      {\r
+        hi2c->XferSize = hi2c->XferCount;\r
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+        {\r
+          xfermode = hi2c->XferOptions;\r
+        }\r
+        else\r
+        {\r
+          xfermode = I2C_AUTOEND_MODE;\r
+        }\r
+      }\r
+\r
+      /* Set the new XferSize in Nbytes register */\r
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+\r
+      /* Update XferCount value */\r
+      hi2c->XferCount -= hi2c->XferSize;\r
+\r
+      /* Enable DMA Request */\r
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+      {\r
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+      }\r
+      else\r
+      {\r
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Call TxCpltCallback() if no stop mode is set */\r
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+      {\r
+        /* Call I2C Master Sequential complete process */\r
+        I2C_ITMasterSeqCplt(hi2c);\r
+      }\r
+      else\r
+      {\r
+        /* Wrong size Status regarding TCR flag event */\r
+        /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+      }\r
+    }\r
+  }\r
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+  {\r
+    if (hi2c->XferCount == 0U)\r
+    {\r
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+      {\r
+        /* Generate a stop condition in case of no transfer option */\r
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)\r
+        {\r
+          /* Generate Stop */\r
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+        }\r
+        else\r
+        {\r
+          /* Call I2C Master Sequential complete process */\r
+          I2C_ITMasterSeqCplt(hi2c);\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Wrong size Status regarding TC flag event */\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+    }\r
+  }\r
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+  {\r
+    /* Call I2C Master complete process */\r
+    I2C_ITMasterCplt(hi2c, ITFlags);\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hi2c);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @param  ITSources Interrupt sources enabled.\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+  uint32_t tmpoptions = hi2c->XferOptions;\r
+  uint32_t treatdmanack = 0U;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hi2c);\r
+\r
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+  {\r
+    /* Check that I2C transfer finished */\r
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
+    /* Mean XferCount == 0 */\r
+    /* So clear Flag NACKF only */\r
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||\r
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))\r
+    {\r
+      /* Split check of hdmarx, for MISRA compliance */\r
+      if (hi2c->hdmarx != NULL)\r
+      {\r
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)\r
+        {\r
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)\r
+          {\r
+            treatdmanack = 1U;\r
+          }\r
+        }\r
+      }\r
+\r
+      /* Split check of hdmatx, for MISRA compliance  */\r
+      if (hi2c->hdmatx != NULL)\r
+      {\r
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)\r
+        {\r
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)\r
+          {\r
+            treatdmanack = 1U;\r
+          }\r
+        }\r
+      }\r
+\r
+      if (treatdmanack == 1U)\r
+      {\r
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */\r
+        {\r
+          /* Call I2C Listen complete process */\r
+          I2C_ITListenCplt(hi2c, ITFlags);\r
+        }\r
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))\r
+        {\r
+          /* Clear NACK Flag */\r
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+          /* Flush TX register */\r
+          I2C_Flush_TXDR(hi2c);\r
+\r
+          /* Last Byte is Transmitted */\r
+          /* Call I2C Slave Sequential complete process */\r
+          I2C_ITSlaveSeqCplt(hi2c);\r
+        }\r
+        else\r
+        {\r
+          /* Clear NACK Flag */\r
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
+        /* Clear NACK Flag */\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+        /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))\r
+        {\r
+          /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+          I2C_ITError(hi2c, hi2c->ErrorCode);\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Only Clear NACK Flag, no DMA treatment is pending */\r
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+    }\r
+  }\r
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))\r
+  {\r
+    I2C_ITAddrCplt(hi2c, ITFlags);\r
+  }\r
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+  {\r
+    /* Call I2C Slave complete process */\r
+    I2C_ITSlaveCplt(hi2c, ITFlags);\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hi2c);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Master sends target device address followed by internal memory address for write request.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart Tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+  /* Wait until TXIS flag is set */\r
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* If Memory address size is 8Bit */\r
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+  {\r
+    /* Send Memory Address */\r
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+  }\r
+  /* If Memory address size is 16Bit */\r
+  else\r
+  {\r
+    /* Send MSB of Memory Address */\r
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
+\r
+    /* Wait until TXIS flag is set */\r
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Send LSB of Memory Address */\r
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+  }\r
+\r
+  /* Wait until TCR flag is set */\r
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Master sends target device address followed by internal memory address for read request.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  DevAddress Target device address: The device 7 bits address value\r
+  *         in datasheet must be shifted to the left before calling the interface\r
+  * @param  MemAddress Internal memory address\r
+  * @param  MemAddSize Size of internal memory address\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart Tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+  /* Wait until TXIS flag is set */\r
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* If Memory address size is 8Bit */\r
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+  {\r
+    /* Send Memory Address */\r
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+  }\r
+  /* If Memory address size is 16Bit */\r
+  else\r
+  {\r
+    /* Send MSB of Memory Address */\r
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
+\r
+    /* Wait until TXIS flag is set */\r
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Send LSB of Memory Address */\r
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+  }\r
+\r
+  /* Wait until TC flag is set */\r
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  I2C Address complete process callback.\r
+  * @param  hi2c I2C handle.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+  uint8_t transferdirection;\r
+  uint16_t slaveaddrcode;\r
+  uint16_t ownadd1code;\r
+  uint16_t ownadd2code;\r
+\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(ITFlags);\r
+\r
+  /* In case of Listen state, need to inform upper layer of address match code event */\r
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+  {\r
+    transferdirection = I2C_GET_DIR(hi2c);\r
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);\r
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);\r
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);\r
+\r
+    /* If 10bits addressing mode is selected */\r
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+    {\r
+      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))\r
+      {\r
+        slaveaddrcode = ownadd1code;\r
+        hi2c->AddrEventCount++;\r
+        if (hi2c->AddrEventCount == 2U)\r
+        {\r
+          /* Reset Address Event counter */\r
+          hi2c->AddrEventCount = 0U;\r
+\r
+          /* Clear ADDR flag */\r
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+          /* Process Unlocked */\r
+          __HAL_UNLOCK(hi2c);\r
+\r
+          /* Call Slave Addr callback */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#else\r
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+        }\r
+      }\r
+      else\r
+      {\r
+        slaveaddrcode = ownadd2code;\r
+\r
+        /* Disable ADDR Interrupts */\r
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        /* Call Slave Addr callback */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#else\r
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+      }\r
+    }\r
+    /* else 7 bits addressing mode is selected */\r
+    else\r
+    {\r
+      /* Disable ADDR Interrupts */\r
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Call Slave Addr callback */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#else\r
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  /* Else clear address flag only */\r
+  else\r
+  {\r
+    /* Clear ADDR flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  I2C Master sequential complete process.\r
+  * @param  hi2c I2C handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Reset I2C handle mode */\r
+  hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+  /* No Generate Stop, to permit restart mode */\r
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */\r
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
+  {\r
+    hi2c->State         = HAL_I2C_STATE_READY;\r
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\r
+    hi2c->XferISR       = NULL;\r
+\r
+    /* Disable Interrupts */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->MasterTxCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_MasterTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
+  else\r
+  {\r
+    hi2c->State         = HAL_I2C_STATE_READY;\r
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\r
+    hi2c->XferISR       = NULL;\r
+\r
+    /* Disable Interrupts */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->MasterRxCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_MasterRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  I2C Slave sequential complete process.\r
+  * @param  hi2c I2C handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Reset I2C handle mode */\r
+  hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+  {\r
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */\r
+    hi2c->State         = HAL_I2C_STATE_LISTEN;\r
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\r
+\r
+    /* Disable Interrupts */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->SlaveTxCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+  {\r
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */\r
+    hi2c->State         = HAL_I2C_STATE_LISTEN;\r
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\r
+\r
+    /* Disable Interrupts */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->SlaveRxCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  I2C Master complete process.\r
+  * @param  hi2c I2C handle.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+  uint32_t tmperror;\r
+\r
+  /* Clear STOP Flag */\r
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+  /* Clear Configuration Register 2 */\r
+  I2C_RESET_CR2(hi2c);\r
+\r
+  /* Reset handle parameters */\r
+  hi2c->PreviousState = I2C_STATE_NONE;\r
+  hi2c->XferISR       = NULL;\r
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r
+\r
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)\r
+  {\r
+    /* Clear NACK Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+    /* Set acknowledge error code */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+  }\r
+\r
+  /* Flush TX register */\r
+  I2C_Flush_TXDR(hi2c);\r
+\r
+  /* Disable Interrupts */\r
+  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r
+\r
+  /* Store current volatile hi2c->ErrorCode, misra rule */\r
+  tmperror = hi2c->ErrorCode;\r
+\r
+  /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))\r
+  {\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+    I2C_ITError(hi2c, hi2c->ErrorCode);\r
+  }\r
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */\r
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
+  {\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
+    {\r
+      hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+      hi2c->MemTxCpltCallback(hi2c);\r
+#else\r
+      HAL_I2C_MemTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+    }\r
+    else\r
+    {\r
+      hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+      hi2c->MasterTxCpltCallback(hi2c);\r
+#else\r
+      HAL_I2C_MasterTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+  {\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
+    {\r
+      hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+      hi2c->MemRxCpltCallback(hi2c);\r
+#else\r
+      HAL_I2C_MemRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+    }\r
+    else\r
+    {\r
+      hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+      hi2c->MasterRxCpltCallback(hi2c);\r
+#else\r
+      HAL_I2C_MasterRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  I2C Slave complete process.\r
+  * @param  hi2c I2C handle.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);\r
+  uint32_t tmpITFlags = ITFlags;\r
+\r
+  /* Clear STOP Flag */\r
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+  /* Disable all interrupts */\r
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r
+\r
+  /* Disable Address Acknowledge */\r
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+  /* Clear Configuration Register 2 */\r
+  I2C_RESET_CR2(hi2c);\r
+\r
+  /* Flush TX register */\r
+  I2C_Flush_TXDR(hi2c);\r
+\r
+  /* If a DMA is ongoing, Update handle size context */\r
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)\r
+  {\r
+    if (hi2c->hdmatx != NULL)\r
+    {\r
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);\r
+    }\r
+  }\r
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)\r
+  {\r
+    if (hi2c->hdmarx != NULL)\r
+    {\r
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Do nothing */\r
+  }\r
+\r
+  /* Store Last receive data if any */\r
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)\r
+  {\r
+    /* Remove RXNE flag on temporary variable as read done */\r
+    tmpITFlags &= ~I2C_FLAG_RXNE;\r
+\r
+    /* Read data from RXDR */\r
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+    /* Increment Buffer pointer */\r
+    hi2c->pBuffPtr++;\r
+\r
+    if ((hi2c->XferSize > 0U))\r
+    {\r
+      hi2c->XferSize--;\r
+      hi2c->XferCount--;\r
+    }\r
+  }\r
+\r
+  /* All data are not transferred, so set error code accordingly */\r
+  if (hi2c->XferCount != 0U)\r
+  {\r
+    /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+  }\r
+\r
+  hi2c->PreviousState = I2C_STATE_NONE;\r
+  hi2c->Mode = HAL_I2C_MODE_NONE;\r
+  hi2c->XferISR = NULL;\r
+\r
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+  {\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+    I2C_ITError(hi2c, hi2c->ErrorCode);\r
+\r
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)\r
+    {\r
+      /* Call I2C Listen complete process */\r
+      I2C_ITListenCplt(hi2c, tmpITFlags);\r
+    }\r
+  }\r
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+  {\r
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */\r
+    I2C_ITSlaveSeqCplt(hi2c);\r
+\r
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->ListenCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_ListenCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+  /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+  {\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->SlaveRxCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->SlaveTxCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  I2C Listen complete process.\r
+  * @param  hi2c I2C handle.\r
+  * @param  ITFlags Interrupt flags to handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+  /* Reset handle parameters */\r
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+  hi2c->PreviousState = I2C_STATE_NONE;\r
+  hi2c->State = HAL_I2C_STATE_READY;\r
+  hi2c->Mode = HAL_I2C_MODE_NONE;\r
+  hi2c->XferISR = NULL;\r
+\r
+  /* Store Last receive data if any */\r
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)\r
+  {\r
+    /* Read data from RXDR */\r
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+    /* Increment Buffer pointer */\r
+    hi2c->pBuffPtr++;\r
+\r
+    if ((hi2c->XferSize > 0U))\r
+    {\r
+      hi2c->XferSize--;\r
+      hi2c->XferCount--;\r
+\r
+      /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+    }\r
+  }\r
+\r
+  /* Disable all Interrupts*/\r
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+\r
+  /* Clear NACK Flag */\r
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hi2c);\r
+\r
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+  hi2c->ListenCpltCallback(hi2c);\r
+#else\r
+  HAL_I2C_ListenCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  I2C interrupts error process.\r
+  * @param  hi2c I2C handle.\r
+  * @param  ErrorCode Error code to handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)\r
+{\r
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;\r
+\r
+  /* Reset handle parameters */\r
+  hi2c->Mode          = HAL_I2C_MODE_NONE;\r
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r
+  hi2c->XferCount     = 0U;\r
+\r
+  /* Set new error code */\r
+  hi2c->ErrorCode |= ErrorCode;\r
+\r
+  /* Disable Interrupts */\r
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||\r
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||\r
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))\r
+  {\r
+    /* Disable all interrupts, except interrupts related to LISTEN state */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+\r
+    /* keep HAL_I2C_STATE_LISTEN if set */\r
+    hi2c->State         = HAL_I2C_STATE_LISTEN;\r
+    hi2c->PreviousState = I2C_STATE_NONE;\r
+    hi2c->XferISR       = I2C_Slave_ISR_IT;\r
+  }\r
+  else\r
+  {\r
+    /* Disable all interrupts */\r
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+\r
+    /* If state is an abort treatment on goind, don't change state */\r
+    /* This change will be do later */\r
+    if (hi2c->State != HAL_I2C_STATE_ABORT)\r
+    {\r
+      /* Set HAL_I2C_STATE_READY */\r
+      hi2c->State         = HAL_I2C_STATE_READY;\r
+    }\r
+    hi2c->PreviousState = I2C_STATE_NONE;\r
+    hi2c->XferISR       = NULL;\r
+  }\r
+\r
+  /* Abort DMA TX transfer if any */\r
+  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+  {\r
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+    if (hi2c->hdmatx != NULL)\r
+    {\r
+      /* Set the I2C DMA Abort callback :\r
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Abort DMA TX */\r
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+      {\r
+        /* Call Directly XferAbortCallback function in case of error */\r
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+      }\r
+    }\r
+  }\r
+  /* Abort DMA RX transfer if any */\r
+  else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+  {\r
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+    if (hi2c->hdmarx != NULL)\r
+    {\r
+      /* Set the I2C DMA Abort callback :\r
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      /* Abort DMA RX */\r
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+      {\r
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */\r
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+      }\r
+    }\r
+  }\r
+  else if (hi2c->State == HAL_I2C_STATE_ABORT)\r
+  {\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->AbortCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_AbortCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->ErrorCallback(hi2c);\r
+#else\r
+    HAL_I2C_ErrorCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  I2C Tx data register flush process.\r
+  * @param  hi2c I2C handle.\r
+  * @retval None\r
+  */\r
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* If a pending TXIS flag is set */\r
+  /* Write a dummy data in TXDR to clear it */\r
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)\r
+  {\r
+    hi2c->Instance->TXDR = 0x00U;\r
+  }\r
+\r
+  /* Flush TX register if not empty */\r
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)\r
+  {\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  DMA I2C master transmit process complete callback.\r
+  * @param  hdma DMA handle\r
+  * @retval None\r
+  */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Disable DMA Request */\r
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+  /* If last transfer, enable STOP interrupt */\r
+  if (hi2c->XferCount == 0U)\r
+  {\r
+    /* Enable STOP interrupt */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+  }\r
+  /* else prepare a new DMA transfer and enable TCReload interrupt */\r
+  else\r
+  {\r
+    /* Update Buffer pointer */\r
+    hi2c->pBuffPtr += hi2c->XferSize;\r
+\r
+    /* Set the XferSize to transfer */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+    }\r
+\r
+    /* Enable the DMA channel */\r
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)\r
+    {\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
+    }\r
+    else\r
+    {\r
+      /* Enable TC interrupts */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  DMA I2C slave transmit process complete callback.\r
+  * @param  hdma DMA handle\r
+  * @retval None\r
+  */\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+  uint32_t tmpoptions = hi2c->XferOptions;\r
+\r
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))\r
+  {\r
+    /* Disable DMA Request */\r
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+    /* Last Byte is Transmitted */\r
+    /* Call I2C Slave Sequential complete process */\r
+    I2C_ITSlaveSeqCplt(hi2c);\r
+  }\r
+  else\r
+  {\r
+    /* No specific action, Master fully manage the generation of STOP condition */\r
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
+    /* So STOP condition should be manage through Interrupt treatment */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief DMA I2C master receive process complete callback.\r
+  * @param  hdma DMA handle\r
+  * @retval None\r
+  */\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Disable DMA Request */\r
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+  /* If last transfer, enable STOP interrupt */\r
+  if (hi2c->XferCount == 0U)\r
+  {\r
+    /* Enable STOP interrupt */\r
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+  }\r
+  /* else prepare a new DMA transfer and enable TCReload interrupt */\r
+  else\r
+  {\r
+    /* Update Buffer pointer */\r
+    hi2c->pBuffPtr += hi2c->XferSize;\r
+\r
+    /* Set the XferSize to transfer */\r
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+    {\r
+      hi2c->XferSize = MAX_NBYTE_SIZE;\r
+    }\r
+    else\r
+    {\r
+      hi2c->XferSize = hi2c->XferCount;\r
+    }\r
+\r
+    /* Enable the DMA channel */\r
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)\r
+    {\r
+      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
+    }\r
+    else\r
+    {\r
+      /* Enable TC interrupts */\r
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  DMA I2C slave receive process complete callback.\r
+  * @param  hdma DMA handle\r
+  * @retval None\r
+  */\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+  uint32_t tmpoptions = hi2c->XferOptions;\r
+\r
+  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \\r
+      (tmpoptions != I2C_NO_OPTION_FRAME))\r
+  {\r
+    /* Disable DMA Request */\r
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+    /* Call I2C Slave Sequential complete process */\r
+    I2C_ITSlaveSeqCplt(hi2c);\r
+  }\r
+  else\r
+  {\r
+    /* No specific action, Master fully manage the generation of STOP condition */\r
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
+    /* So STOP condition should be manage through Interrupt treatment */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  DMA I2C communication error callback.\r
+  * @param hdma DMA handle\r
+  * @retval None\r
+  */\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Disable Acknowledge */\r
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+  /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
+}\r
+\r
+/**\r
+  * @brief DMA I2C communication abort callback\r
+  *        (To be called at end of DMA Abort procedure).\r
+  * @param hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)\r
+{\r
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Reset AbortCpltCallback */\r
+  hi2c->hdmatx->XferAbortCallback = NULL;\r
+  hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+  /* Check if come from abort from user */\r
+  if (hi2c->State == HAL_I2C_STATE_ABORT)\r
+  {\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->AbortCpltCallback(hi2c);\r
+#else\r
+    HAL_I2C_AbortCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+    hi2c->ErrorCallback(hi2c);\r
+#else\r
+    HAL_I2C_ErrorCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles I2C Communication Timeout.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  Flag Specifies the I2C flag to check.\r
+  * @param  Status The new Flag status (SET or RESET).\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart Tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)\r
+  {\r
+    /* Check for the Timeout */\r
+    if (Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+      {\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+        hi2c->State = HAL_I2C_STATE_READY;\r
+        hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart Tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)\r
+  {\r
+    /* Check if a NACK is detected */\r
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Check for the Timeout */\r
+    if (Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+      {\r
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+        hi2c->State = HAL_I2C_STATE_READY;\r
+        hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart Tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+  {\r
+    /* Check if a NACK is detected */\r
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Check for the Timeout */\r
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+    {\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+      hi2c->State = HAL_I2C_STATE_READY;\r
+      hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart Tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\r
+  {\r
+    /* Check if a NACK is detected */\r
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    /* Check if a STOPF is detected */\r
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+    {\r
+      /* Check if an RXNE is pending */\r
+      /* Store Last receive data if any */\r
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))\r
+      {\r
+        /* Return HAL_OK */\r
+        /* The Reading of data from RXDR will be done in caller function */\r
+        return HAL_OK;\r
+      }\r
+      else\r
+      {\r
+        /* Clear STOP Flag */\r
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+        /* Clear Configuration Register 2 */\r
+        I2C_RESET_CR2(hi2c);\r
+\r
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+        hi2c->State = HAL_I2C_STATE_READY;\r
+        hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hi2c);\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+\r
+    /* Check for the Timeout */\r
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+    {\r
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+      hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+      /* Process Unlocked */\r
+      __HAL_UNLOCK(hi2c);\r
+\r
+      return HAL_ERROR;\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart Tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r
+  {\r
+    /* Wait until STOP Flag is reset */\r
+    /* AutoEnd should be initiate after AF */\r
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+    {\r
+      /* Check for the Timeout */\r
+      if (Timeout != HAL_MAX_DELAY)\r
+      {\r
+        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+        {\r
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+          hi2c->State = HAL_I2C_STATE_READY;\r
+          hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+          /* Process Unlocked */\r
+          __HAL_UNLOCK(hi2c);\r
+\r
+          return HAL_ERROR;\r
+        }\r
+      }\r
+    }\r
+\r
+    /* Clear NACKF Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+    /* Clear STOP Flag */\r
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+    /* Flush TX register */\r
+    I2C_Flush_TXDR(hi2c);\r
+\r
+    /* Clear Configuration Register 2 */\r
+    I2C_RESET_CR2(hi2c);\r
+\r
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+    hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_ERROR;\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).\r
+  * @param  hi2c I2C handle.\r
+  * @param  DevAddress Specifies the slave address to be programmed.\r
+  * @param  Size Specifies the number of bytes to be programmed.\r
+  *   This parameter must be a value between 0 and 255.\r
+  * @param  Mode New state of the I2C START condition generation.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .\r
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.\r
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.\r
+  * @param  Request New state of the I2C START condition generation.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.\r
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).\r
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.\r
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.\r
+  * @retval None\r
+  */\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+  assert_param(IS_TRANSFER_MODE(Mode));\r
+  assert_param(IS_TRANSFER_REQUEST(Request));\r
+\r
+  /* update CR2 register */\r
+  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \\r
+             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));\r
+}\r
+\r
+/**\r
+  * @brief  Manage the enabling of Interrupts.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r
+  * @retval None\r
+  */\r
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
+{\r
+  uint32_t tmpisr = 0U;\r
+\r
+  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \\r
+      (hi2c->XferISR == I2C_Slave_ISR_DMA))\r
+  {\r
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+    {\r
+      /* Enable ERR, STOP, NACK and ADDR interrupts */\r
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+    }\r
+\r
+    if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
+    {\r
+      /* Enable ERR and NACK interrupts */\r
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
+    }\r
+\r
+    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+    {\r
+      /* Enable STOP interrupts */\r
+      tmpisr |= I2C_IT_STOPI;\r
+    }\r
+\r
+    if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
+    {\r
+      /* Enable TC interrupts */\r
+      tmpisr |= I2C_IT_TCI;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+    {\r
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */\r
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+    }\r
+\r
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
+    {\r
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */\r
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;\r
+    }\r
+\r
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
+    {\r
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */\r
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;\r
+    }\r
+\r
+    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+    {\r
+      /* Enable STOP interrupts */\r
+      tmpisr |= I2C_IT_STOPI;\r
+    }\r
+  }\r
+\r
+  /* Enable interrupts only at the end */\r
+  /* to avoid the risk of I2C interrupt handle execution before */\r
+  /* all interrupts requested done */\r
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);\r
+}\r
+\r
+/**\r
+  * @brief  Manage the disabling of Interrupts.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2C.\r
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r
+  * @retval None\r
+  */\r
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
+{\r
+  uint32_t tmpisr = 0U;\r
+\r
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
+  {\r
+    /* Disable TC and TXI interrupts */\r
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;\r
+\r
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)\r
+    {\r
+      /* Disable NACK and STOP interrupts */\r
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+    }\r
+  }\r
+\r
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
+  {\r
+    /* Disable TC and RXI interrupts */\r
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;\r
+\r
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)\r
+    {\r
+      /* Disable NACK and STOP interrupts */\r
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+    }\r
+  }\r
+\r
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+  {\r
+    /* Disable ADDR, NACK and STOP interrupts */\r
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+  }\r
+\r
+  if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
+  {\r
+    /* Enable ERR and NACK interrupts */\r
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
+  }\r
+\r
+  if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+  {\r
+    /* Enable STOP interrupts */\r
+    tmpisr |= I2C_IT_STOPI;\r
+  }\r
+\r
+  if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
+  {\r
+    /* Enable TC interrupts */\r
+    tmpisr |= I2C_IT_TCI;\r
+  }\r
+\r
+  /* Disable interrupts only at the end */\r
+  /* to avoid a breaking situation like at "t" time */\r
+  /* all disable interrupts request are not done */\r
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);\r
+}\r
+\r
+/**\r
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.\r
+  * @param  hi2c I2C handle.\r
+  * @retval None\r
+  */\r
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* if user set XferOptions to I2C_OTHER_FRAME            */\r
+  /* it request implicitly to generate a restart condition */\r
+  /* set XferOptions to I2C_FIRST_FRAME                    */\r
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)\r
+  {\r
+    hi2c->XferOptions = I2C_FIRST_FRAME;\r
+  }\r
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */\r
+  /* it request implicitly to generate a restart condition    */\r
+  /* then generate a stop condition at the end of transfer    */\r
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */\r
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)\r
+  {\r
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;\r
+  }\r
+  else\r
+  {\r
+    /* Nothing to do */\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
new file mode 100644 (file)
index 0000000..54d74c7
--- /dev/null
@@ -0,0 +1,339 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_i2c_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   I2C Extended HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of I2C Extended peripheral:\r
+  *           + Extended features functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+               ##### I2C peripheral Extended features  #####\r
+  ==============================================================================\r
+\r
+  [..] Comparing to other previous devices, the I2C interface for STM32L4xx\r
+       devices contains the following additional features\r
+\r
+       (+) Possibility to disable or enable Analog Noise Filter\r
+       (+) Use of a configured Digital Noise Filter\r
+       (+) Disable or enable wakeup from Stop mode(s)\r
+       (+) Disable or enable Fast Mode Plus\r
+\r
+                     ##### How to use this driver #####\r
+  ==============================================================================\r
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature\r
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()\r
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()\r
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :\r
+          (++) HAL_I2CEx_EnableWakeUp()\r
+          (++) HAL_I2CEx_DisableWakeUp()\r
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :\r
+          (++) HAL_I2CEx_EnableFastModePlus()\r
+          (++) HAL_I2CEx_DisableFastModePlus()\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2CEx I2CEx\r
+  * @brief I2C Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions\r
+  * @brief    Extended features functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Extended features functions #####\r
+ ===============================================================================\r
+    [..] This section provides functions allowing to:\r
+      (+) Configure Noise Filters\r
+      (+) Configure Wake Up Feature\r
+      (+) Configure Fast Mode Plus\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Configure I2C Analog noise filter.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2Cx peripheral.\r
+  * @param  AnalogFilter New state of the Analog filter.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+    /* Disable the selected I2C peripheral */\r
+    __HAL_I2C_DISABLE(hi2c);\r
+\r
+    /* Reset I2Cx ANOFF bit */\r
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);\r
+\r
+    /* Set analog filter bit*/\r
+    hi2c->Instance->CR1 |= AnalogFilter;\r
+\r
+    __HAL_I2C_ENABLE(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configure I2C Digital noise filter.\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2Cx peripheral.\r
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\r
+{\r
+  uint32_t tmpreg;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+    /* Disable the selected I2C peripheral */\r
+    __HAL_I2C_DISABLE(hi2c);\r
+\r
+    /* Get the old register value */\r
+    tmpreg = hi2c->Instance->CR1;\r
+\r
+    /* Reset I2Cx DNF bits [11:8] */\r
+    tmpreg &= ~(I2C_CR1_DNF);\r
+\r
+    /* Set I2Cx DNF coefficient */\r
+    tmpreg |= DigitalFilter << 8U;\r
+\r
+    /* Store the new register value */\r
+    hi2c->Instance->CR1 = tmpreg;\r
+\r
+    __HAL_I2C_ENABLE(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enable I2C wakeup from Stop mode(s).\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2Cx peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+    /* Disable the selected I2C peripheral */\r
+    __HAL_I2C_DISABLE(hi2c);\r
+\r
+    /* Enable wakeup from stop mode */\r
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;\r
+\r
+    __HAL_I2C_ENABLE(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Disable I2C wakeup from Stop mode(s).\r
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified I2Cx peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));\r
+\r
+  if (hi2c->State == HAL_I2C_STATE_READY)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+    /* Disable the selected I2C peripheral */\r
+    __HAL_I2C_DISABLE(hi2c);\r
+\r
+    /* Enable wakeup from stop mode */\r
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);\r
+\r
+    __HAL_I2C_ENABLE(hi2c);\r
+\r
+    hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+    /* Process Unlocked */\r
+    __HAL_UNLOCK(hi2c);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Enable the I2C fast mode plus driving capability.\r
+  * @param ConfigFastModePlus Selects the pin.\r
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected\r
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.\r
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled\r
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.\r
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled\r
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.\r
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled\r
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.\r
+  * @retval None\r
+  */\r
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)\r
+{\r
+  /* Check the parameter */\r
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
+\r
+  /* Enable SYSCFG clock */\r
+  __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+  /* Enable fast mode plus driving capability for selected pin */\r
+  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);\r
+}\r
+\r
+/**\r
+  * @brief Disable the I2C fast mode plus driving capability.\r
+  * @param ConfigFastModePlus Selects the pin.\r
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected\r
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.\r
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled\r
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.\r
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled\r
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.\r
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled\r
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.\r
+  * @retval None\r
+  */\r
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)\r
+{\r
+  /* Check the parameter */\r
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
+\r
+  /* Enable SYSCFG clock */\r
+  __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+  /* Disable fast mode plus driving capability for selected pin */\r
+  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
new file mode 100644 (file)
index 0000000..756b6d4
--- /dev/null
@@ -0,0 +1,2452 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pcd.c\r
+  * @author  MCD Application Team\r
+  * @brief   PCD HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the USB Peripheral Controller:\r
+  *           + Initialization and de-initialization functions\r
+  *           + IO operation functions\r
+  *           + Peripheral Control functions\r
+  *           + Peripheral State functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                    ##### How to use this driver #####\r
+  ==============================================================================\r
+    [..]\r
+      The PCD HAL driver can be used as follows:\r
+\r
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:\r
+         PCD_HandleTypeDef  hpcd;\r
+\r
+     (#) Fill parameters of Init structure in HCD handle\r
+\r
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)\r
+\r
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:\r
+         (##) Enable the PCD/USB Low Level interface clock using\r
+              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral\r
+\r
+         (##) Initialize the related GPIO clocks\r
+         (##) Configure PCD pin-out\r
+         (##) Configure PCD NVIC interrupt\r
+\r
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:\r
+         (##) hpcd.pData = pdev;\r
+\r
+     (#)Enable PCD transmission and reception:\r
+         (##) HAL_PCD_Start();\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PCD PCD\r
+  * @brief PCD HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+\r
+#if defined (USB) || defined (USB_OTG_FS)\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PCD_Private_Macros PCD Private Macros\r
+  * @{\r
+  */\r
+#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))\r
+#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup PCD_Private_Functions PCD Private Functions\r
+  * @{\r
+  */\r
+#if defined (USB_OTG_FS)\r
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);\r
+#endif /* defined (USB) */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Functions PCD Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ *  @brief    Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+            ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initializes the PCD according to the specified\r
+  *         parameters in the PCD_InitTypeDef and initialize the associated handle.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)\r
+{\r
+#if defined (USB_OTG_FS)\r
+  USB_OTG_GlobalTypeDef *USBx;\r
+#endif /* defined (USB_OTG_FS) */\r
+  uint8_t i;\r
+\r
+  /* Check the PCD handle allocation */\r
+  if (hpcd == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));\r
+\r
+#if defined (USB_OTG_FS)\r
+  USBx = hpcd->Instance;\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    hpcd->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->SOFCallback = HAL_PCD_SOFCallback;\r
+    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;\r
+    hpcd->ResetCallback = HAL_PCD_ResetCallback;\r
+    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;\r
+    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;\r
+    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;\r
+    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;\r
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;\r
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;\r
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;\r
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;\r
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;\r
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;\r
+\r
+    if (hpcd->MspInitCallback == NULL)\r
+    {\r
+      hpcd->MspInitCallback = HAL_PCD_MspInit;\r
+    }\r
+\r
+    /* Init the low level hardware */\r
+    hpcd->MspInitCallback(hpcd);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+    HAL_PCD_MspInit(hpcd);\r
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */\r
+  }\r
+\r
+  hpcd->State = HAL_PCD_STATE_BUSY;\r
+\r
+#if defined (USB_OTG_FS)\r
+  /* Disable DMA mode for FS instance */\r
+  if ((USBx->CID & (0x1U << 8)) == 0U)\r
+  {\r
+    hpcd->Init.dma_enable = 0U;\r
+  }\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+  /* Disable the Interrupts */\r
+  __HAL_PCD_DISABLE(hpcd);\r
+\r
+  /*Init the Core (common init.) */\r
+  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)\r
+  {\r
+    hpcd->State = HAL_PCD_STATE_ERROR;\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Force Device Mode*/\r
+  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);\r
+\r
+  /* Init endpoints structures */\r
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\r
+  {\r
+    /* Init ep structure */\r
+    hpcd->IN_ep[i].is_in = 1U;\r
+    hpcd->IN_ep[i].num = i;\r
+    hpcd->IN_ep[i].tx_fifo_num = i;\r
+    /* Control until ep is activated */\r
+    hpcd->IN_ep[i].type = EP_TYPE_CTRL;\r
+    hpcd->IN_ep[i].maxpacket = 0U;\r
+    hpcd->IN_ep[i].xfer_buff = 0U;\r
+    hpcd->IN_ep[i].xfer_len = 0U;\r
+  }\r
+\r
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\r
+  {\r
+    hpcd->OUT_ep[i].is_in = 0U;\r
+    hpcd->OUT_ep[i].num = i;\r
+    /* Control until ep is activated */\r
+    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;\r
+    hpcd->OUT_ep[i].maxpacket = 0U;\r
+    hpcd->OUT_ep[i].xfer_buff = 0U;\r
+    hpcd->OUT_ep[i].xfer_len = 0U;\r
+  }\r
+\r
+  /* Init Device */\r
+  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)\r
+  {\r
+    hpcd->State = HAL_PCD_STATE_ERROR;\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  hpcd->USB_Address = 0U;\r
+  hpcd->State = HAL_PCD_STATE_READY;\r
+  \r
+  /* Activate LPM */\r
+  if (hpcd->Init.lpm_enable == 1U)\r
+  {\r
+    (void)HAL_PCDEx_ActivateLPM(hpcd);\r
+  }\r
+  \r
+  (void)USB_DevDisconnect(hpcd->Instance);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the PCD peripheral.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Check the PCD handle allocation */\r
+  if (hpcd == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  hpcd->State = HAL_PCD_STATE_BUSY;\r
+\r
+  /* Stop Device */\r
+  (void)HAL_PCD_Stop(hpcd);\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+  if (hpcd->MspDeInitCallback == NULL)\r
+  {\r
+    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */\r
+  }\r
+\r
+  /* DeInit the low level hardware */\r
+  hpcd->MspDeInitCallback(hpcd);\r
+#else\r
+  /* DeInit the low level hardware: CLOCK, NVIC.*/\r
+  HAL_PCD_MspDeInit(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+  hpcd->State = HAL_PCD_STATE_RESET;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the PCD MSP.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes PCD MSP.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+/**\r
+  * @brief  Register a User USB PCD Callback\r
+  *         To be used instead of the weak predefined callback\r
+  * @param  hpcd USB PCD handle\r
+  * @param  CallbackID ID of the callback to be registered\r
+  *         This parameter can be one of the following values:\r
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID\r
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID\r
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID\r
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID\r
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID\r
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID\r
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID\r
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID\r
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID\r
+  * @param  pCallback pointer to the Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+    return HAL_ERROR;\r
+  }\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_PCD_SOF_CB_ID :\r
+        hpcd->SOFCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_SETUPSTAGE_CB_ID :\r
+        hpcd->SetupStageCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_RESET_CB_ID :\r
+        hpcd->ResetCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_SUSPEND_CB_ID :\r
+        hpcd->SuspendCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_RESUME_CB_ID :\r
+        hpcd->ResumeCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_CONNECT_CB_ID :\r
+        hpcd->ConnectCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_DISCONNECT_CB_ID :\r
+        hpcd->DisconnectCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_MSPINIT_CB_ID :\r
+        hpcd->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_MSPDEINIT_CB_ID :\r
+        hpcd->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (hpcd->State == HAL_PCD_STATE_RESET)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_PCD_MSPINIT_CB_ID :\r
+        hpcd->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_PCD_MSPDEINIT_CB_ID :\r
+        hpcd->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister an USB PCD Callback\r
+  *         USB PCD callabck is redirected to the weak predefined callback\r
+  * @param  hpcd USB PCD handle\r
+  * @param  CallbackID ID of the callback to be unregistered\r
+  *         This parameter can be one of the following values:\r
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID\r
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID\r
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID\r
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID\r
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID\r
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID\r
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID\r
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID\r
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  /* Setup Legacy weak Callbacks  */\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_PCD_SOF_CB_ID :\r
+        hpcd->SOFCallback = HAL_PCD_SOFCallback;\r
+        break;\r
+\r
+      case HAL_PCD_SETUPSTAGE_CB_ID :\r
+        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;\r
+        break;\r
+\r
+      case HAL_PCD_RESET_CB_ID :\r
+        hpcd->ResetCallback = HAL_PCD_ResetCallback;\r
+        break;\r
+\r
+      case HAL_PCD_SUSPEND_CB_ID :\r
+        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;\r
+        break;\r
+\r
+      case HAL_PCD_RESUME_CB_ID :\r
+        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;\r
+        break;\r
+\r
+      case HAL_PCD_CONNECT_CB_ID :\r
+        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;\r
+        break;\r
+\r
+      case HAL_PCD_DISCONNECT_CB_ID :\r
+        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;\r
+        break;\r
+\r
+      case HAL_PCD_MSPINIT_CB_ID :\r
+        hpcd->MspInitCallback = HAL_PCD_MspInit;\r
+        break;\r
+\r
+      case HAL_PCD_MSPDEINIT_CB_ID :\r
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (hpcd->State == HAL_PCD_STATE_RESET)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_PCD_MSPINIT_CB_ID :\r
+        hpcd->MspInitCallback = HAL_PCD_MspInit;\r
+        break;\r
+\r
+      case HAL_PCD_MSPDEINIT_CB_ID :\r
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register USB PCD Data OUT Stage Callback\r
+  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->DataOutStageCallback = pCallback;\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister the USB PCD Data OUT Stage Callback\r
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register USB PCD Data IN Stage Callback\r
+  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->DataInStageCallback = pCallback;\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister the USB PCD Data IN Stage Callback\r
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register USB PCD Iso OUT incomplete Callback\r
+  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->ISOOUTIncompleteCallback = pCallback;\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister the USB PCD Iso OUT incomplete Callback\r
+  *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register USB PCD Iso IN incomplete Callback\r
+  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->ISOINIncompleteCallback = pCallback;\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister the USB PCD Iso IN incomplete Callback\r
+  *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register USB PCD BCD Callback\r
+  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @param  pCallback pointer to the USB PCD BCD Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->BCDCallback = pCallback;\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister the USB PCD BCD Callback\r
+  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Register USB PCD LPM Callback\r
+  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @param  pCallback pointer to the USB PCD LPM Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->LPMCallback = pCallback;\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  UnRegister the USB PCD LPM Callback\r
+  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if (hpcd->State == HAL_PCD_STATE_READY)\r
+  {\r
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return status;\r
+}\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions\r
+ *  @brief   Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### IO operation functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to manage the PCD data\r
+    transfers.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Start the USB device\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)\r
+{\r
+#if defined (USB_OTG_FS)\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+  __HAL_LOCK(hpcd);\r
+#if defined (USB_OTG_FS)\r
+  if (hpcd->Init.battery_charging_enable == 1U)\r
+  {\r
+    /* Enable USB Transceiver */\r
+    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\r
+  }\r
+#endif /* defined (USB_OTG_FS) */\r
+  (void)USB_DevConnect(hpcd->Instance);\r
+  __HAL_PCD_ENABLE(hpcd);\r
+  __HAL_UNLOCK(hpcd);\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stop the USB device.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)\r
+{\r
+  __HAL_LOCK(hpcd);\r
+  __HAL_PCD_DISABLE(hpcd);\r
+\r
+  if (USB_StopDevice(hpcd->Instance) != HAL_OK)\r
+  {\r
+    __HAL_UNLOCK(hpcd);\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  (void)USB_DevDisconnect(hpcd->Instance);\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return HAL_OK;\r
+}\r
+#if defined (USB_OTG_FS)\r
+/**\r
+  * @brief  Handles PCD interrupt request.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t i, ep_intr, epint, epnum = 0U;\r
+  uint32_t fifoemptymsk, temp;\r
+  USB_OTG_EPTypeDef *ep;\r
+\r
+  /* ensure that we are in device mode */\r
+  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)\r
+  {\r
+    /* avoid spurious interrupt */\r
+    if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))\r
+    {\r
+      return;\r
+    }\r
+\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))\r
+    {\r
+      /* incorrect mode, acknowledge the interrupt */\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);\r
+    }\r
+\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))\r
+    {\r
+      epnum = 0U;\r
+\r
+      /* Read in the device interrupt bits */\r
+      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);\r
+\r
+      while (ep_intr != 0U)\r
+      {\r
+        if ((ep_intr & 0x1U) != 0U)\r
+        {\r
+          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);\r
+\r
+          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)\r
+          {\r
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);\r
+            (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);\r
+          }\r
+\r
+          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)\r
+          {\r
+            /* Class B setup phase done for previous decoded setup */\r
+            (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);\r
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);\r
+          }\r
+\r
+          if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)\r
+          {\r
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);\r
+          }\r
+\r
+          /* Clear Status Phase Received interrupt */\r
+          if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\r
+          {\r
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\r
+          }\r
+\r
+          /* Clear OUT NAK interrupt */\r
+          if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)\r
+          {\r
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);\r
+          }\r
+        }\r
+        epnum++;\r
+        ep_intr >>= 1U;\r
+      }\r
+    }\r
+\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))\r
+    {\r
+      /* Read in the device interrupt bits */\r
+      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);\r
+\r
+      epnum = 0U;\r
+\r
+      while (ep_intr != 0U)\r
+      {\r
+        if ((ep_intr & 0x1U) != 0U) /* In ITR */\r
+        {\r
+          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);\r
+\r
+          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)\r
+          {\r
+            fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));\r
+            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
+\r
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+            hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);\r
+#else\r
+            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+          }\r
+          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)\r
+          {\r
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);\r
+          }\r
+          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)\r
+          {\r
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);\r
+          }\r
+          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)\r
+          {\r
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);\r
+          }\r
+          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)\r
+          {\r
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);\r
+          }\r
+          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)\r
+          {\r
+            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);\r
+          }\r
+        }\r
+        epnum++;\r
+        ep_intr >>= 1U;\r
+      }\r
+    }\r
+\r
+    /* Handle Resume Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))\r
+    {\r
+      /* Clear the Remote Wake-up Signaling */\r
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r
+\r
+      if (hpcd->LPM_State == LPM_L1)\r
+      {\r
+        hpcd->LPM_State = LPM_L0;\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+        hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);\r
+#else\r
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+      }\r
+      else\r
+      {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+        hpcd->ResumeCallback(hpcd);\r
+#else\r
+        HAL_PCD_ResumeCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+      }\r
+\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);\r
+    }\r
+\r
+    /* Handle Suspend Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))\r
+    {\r
+      if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
+      {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+        hpcd->SuspendCallback(hpcd);\r
+#else\r
+        HAL_PCD_SuspendCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+      }\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);\r
+    }\r
+    \r
+    /* Handle LPM Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))\r
+    {\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);\r
+\r
+      if (hpcd->LPM_State == LPM_L0)\r
+      {\r
+        hpcd->LPM_State = LPM_L1;\r
+        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+        hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);\r
+#else\r
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+      }\r
+      else\r
+      {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+        hpcd->SuspendCallback(hpcd);\r
+#else\r
+        HAL_PCD_SuspendCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+      }\r
+    }\r
+    \r
+    /* Handle Reset Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))\r
+    {\r
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r
+      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);\r
+\r
+      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\r
+      {\r
+        USBx_INEP(i)->DIEPINT = 0xFB7FU;\r
+        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
+        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r
+        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
+      }\r
+      USBx_DEVICE->DAINTMSK |= 0x10001U;\r
+\r
+      if (hpcd->Init.use_dedicated_ep1 != 0U)\r
+      {\r
+        USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |\r
+                                   USB_OTG_DOEPMSK_XFRCM |\r
+                                   USB_OTG_DOEPMSK_EPDM;\r
+\r
+        USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |\r
+                                  USB_OTG_DIEPMSK_XFRCM |\r
+                                  USB_OTG_DIEPMSK_EPDM;\r
+      }\r
+      else\r
+      {\r
+        USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |\r
+                                USB_OTG_DOEPMSK_XFRCM |\r
+                                USB_OTG_DOEPMSK_EPDM |\r
+                                USB_OTG_DOEPMSK_OTEPSPRM |\r
+                                USB_OTG_DOEPMSK_NAKM;\r
+\r
+        USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |\r
+                                USB_OTG_DIEPMSK_XFRCM |\r
+                                USB_OTG_DIEPMSK_EPDM;\r
+      }\r
+\r
+      /* Set Default Address to 0 */\r
+      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\r
+\r
+      /* setup EP0 to receive SETUP packets */\r
+      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);\r
+\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);\r
+    }\r
+\r
+    /* Handle Enumeration done Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))\r
+    {\r
+      (void)USB_ActivateSetup(hpcd->Instance);\r
+      hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);\r
+\r
+      /* Set USB Turnaround time */\r
+      (void)USB_SetTurnaroundTime(hpcd->Instance,\r
+                                  HAL_RCC_GetHCLKFreq(),\r
+                                  (uint8_t)hpcd->Init.speed);\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->ResetCallback(hpcd);\r
+#else\r
+      HAL_PCD_ResetCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);\r
+    }\r
+\r
+    /* Handle RxQLevel Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))\r
+    {\r
+      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+\r
+      temp = USBx->GRXSTSP;\r
+\r
+      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];\r
+\r
+      if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)\r
+      {\r
+        if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)\r
+        {\r
+          (void)USB_ReadPacket(USBx, ep->xfer_buff,\r
+                               (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));\r
+\r
+          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+        }\r
+      }\r
+      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)\r
+      {\r
+        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);\r
+        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+      }\r
+      else\r
+      {\r
+        /* ... */\r
+      }\r
+      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+    }\r
+\r
+    /* Handle SOF Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->SOFCallback(hpcd);\r
+#else\r
+      HAL_PCD_SOFCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);\r
+    }\r
+\r
+    /* Handle Incomplete ISO IN Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);\r
+#else\r
+      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);\r
+    }\r
+\r
+    /* Handle Incomplete ISO OUT Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);\r
+#else\r
+      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r
+    }\r
+\r
+    /* Handle Connection event Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->ConnectCallback(hpcd);\r
+#else\r
+      HAL_PCD_ConnectCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);\r
+    }\r
+\r
+    /* Handle Disconnection event Interrupt */\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))\r
+    {\r
+      temp = hpcd->Instance->GOTGINT;\r
+\r
+      if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)\r
+      {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+        hpcd->DisconnectCallback(hpcd);\r
+#else\r
+        HAL_PCD_DisconnectCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+      }\r
+      hpcd->Instance->GOTGINT |= temp;\r
+    }\r
+  }\r
+}\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+/**\r
+  * @brief  This function handles PCD interrupt request.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r
+{\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))\r
+  {\r
+    /* servicing of the endpoint correct transfer interrupt */\r
+    /* clear of the CTR flag into the sub */\r
+    (void)PCD_EP_ISR_Handler(hpcd);\r
+  }\r
+\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))\r
+  {\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->ResetCallback(hpcd);\r
+#else\r
+    HAL_PCD_ResetCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+    (void)HAL_PCD_SetAddress(hpcd, 0U);\r
+  }\r
+\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))\r
+  {\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);\r
+  }\r
+\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))\r
+  {\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);\r
+  }\r
+\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))\r
+  {\r
+    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);\r
+    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);\r
+\r
+    if (hpcd->LPM_State == LPM_L1)\r
+    {\r
+      hpcd->LPM_State = LPM_L0;\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);\r
+#else\r
+      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->ResumeCallback(hpcd);\r
+#else\r
+    HAL_PCD_ResumeCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);\r
+  }\r
+\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))\r
+  {\r
+    /* Force low-power mode in the macrocell */\r
+    hpcd->Instance->CNTR |= USB_CNTR_FSUSP;\r
+\r
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);\r
+\r
+    hpcd->Instance->CNTR |= USB_CNTR_LPMODE;\r
+\r
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U)\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->SuspendCallback(hpcd);\r
+#else\r
+      HAL_PCD_SuspendCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+\r
+  /* Handle LPM Interrupt */\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))\r
+  {\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);\r
+    if (hpcd->LPM_State == LPM_L0)\r
+    {\r
+      /* Force suspend and low-power mode before going to L1 state*/\r
+      hpcd->Instance->CNTR |= USB_CNTR_LPMODE;\r
+      hpcd->Instance->CNTR |= USB_CNTR_FSUSP;\r
+\r
+      hpcd->LPM_State = LPM_L1;\r
+      hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);\r
+#else\r
+      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+    else\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->SuspendCallback(hpcd);\r
+#else\r
+      HAL_PCD_SuspendCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))\r
+  {\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->SOFCallback(hpcd);\r
+#else\r
+    HAL_PCD_SOFCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))\r
+  {\r
+    /* clear ESOF flag in ISTR */\r
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);\r
+  }\r
+}\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @brief  Data OUT stage callback.\r
+  * @param  hpcd PCD handle\r
+  * @param  epnum endpoint number\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+  UNUSED(epnum);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Data IN stage callback\r
+  * @param  hpcd PCD handle\r
+  * @param  epnum endpoint number\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+  UNUSED(epnum);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_DataInStageCallback could be implemented in the user file\r
+   */\r
+}\r
+/**\r
+  * @brief  Setup stage callback\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_SetupStageCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  USB Start Of Frame callback.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_SOFCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  USB Reset callback.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_ResetCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Suspend event callback.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_SuspendCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Resume event callback.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_ResumeCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Incomplete ISO OUT callback.\r
+  * @param  hpcd PCD handle\r
+  * @param  epnum endpoint number\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+  UNUSED(epnum);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Incomplete ISO IN callback.\r
+  * @param  hpcd PCD handle\r
+  * @param  epnum endpoint number\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+  UNUSED(epnum);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Connection event callback.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_ConnectCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Disconnection event callback.\r
+  * @param  hpcd PCD handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCD_DisconnectCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions\r
+ *  @brief   management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to control the PCD data\r
+    transfers.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Connect the USB device\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)\r
+{\r
+#if defined (USB_OTG_FS)\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+  __HAL_LOCK(hpcd);\r
+#if defined (USB_OTG_FS)\r
+  if (hpcd->Init.battery_charging_enable == 1U)\r
+  {\r
+    /* Enable USB Transceiver */\r
+    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\r
+  }\r
+#endif /* defined (USB_OTG_FS) */\r
+  (void)USB_DevConnect(hpcd->Instance);\r
+  __HAL_UNLOCK(hpcd);\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Disconnect the USB device.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)\r
+{\r
+#if defined (USB_OTG_FS)\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+\r
+#endif /* defined (USB_OTG_FS) */\r
+  __HAL_LOCK(hpcd);\r
+  (void)USB_DevDisconnect(hpcd->Instance);\r
+#if defined (USB_OTG_FS)\r
+  if (hpcd->Init.battery_charging_enable == 1U)\r
+  {\r
+    /* Disable USB Transceiver */\r
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+  }\r
+#endif /* defined (USB_OTG_FS) */\r
+  __HAL_UNLOCK(hpcd);\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Set the USB Device address.\r
+  * @param  hpcd PCD handle\r
+  * @param  address new device address\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)\r
+{\r
+  __HAL_LOCK(hpcd);\r
+  hpcd->USB_Address = address;\r
+  (void)USB_SetDevAddress(hpcd->Instance, address);\r
+  __HAL_UNLOCK(hpcd);\r
+  return HAL_OK;\r
+}\r
+/**\r
+  * @brief  Open and configure an endpoint.\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @param  ep_mps endpoint max packet size\r
+  * @param  ep_type endpoint type\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)\r
+{\r
+  HAL_StatusTypeDef  ret = HAL_OK;\r
+  PCD_EPTypeDef *ep;\r
+\r
+  if ((ep_addr & 0x80U) == 0x80U)\r
+  {\r
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
+    ep->is_in = 1U;\r
+  }\r
+  else\r
+  {\r
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
+    ep->is_in = 0U;\r
+  }\r
+\r
+  ep->num = ep_addr & EP_ADDR_MSK;\r
+  ep->maxpacket = ep_mps;\r
+  ep->type = ep_type;\r
+\r
+  if (ep->is_in != 0U)\r
+  {\r
+    /* Assign a Tx FIFO */\r
+    ep->tx_fifo_num = ep->num;\r
+  }\r
+  /* Set initial data PID. */\r
+  if (ep_type == EP_TYPE_BULK)\r
+  {\r
+    ep->data_pid_start = 0U;\r
+  }\r
+\r
+  __HAL_LOCK(hpcd);\r
+  (void)USB_ActivateEndpoint(hpcd->Instance, ep);\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return ret;\r
+}\r
+\r
+/**\r
+  * @brief  Deactivate an endpoint.\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+  PCD_EPTypeDef *ep;\r
+\r
+  if ((ep_addr & 0x80U) == 0x80U)\r
+  {\r
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
+    ep->is_in = 1U;\r
+  }\r
+  else\r
+  {\r
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
+    ep->is_in = 0U;\r
+  }\r
+  ep->num   = ep_addr & EP_ADDR_MSK;\r
+\r
+  __HAL_LOCK(hpcd);\r
+  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);\r
+  __HAL_UNLOCK(hpcd);\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Receive an amount of data.\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @param  pBuf pointer to the reception buffer\r
+  * @param  len amount of data to be received\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
+{\r
+  PCD_EPTypeDef *ep;\r
+\r
+  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
+\r
+  /*setup and start the Xfer */\r
+  ep->xfer_buff = pBuf;\r
+  ep->xfer_len = len;\r
+  ep->xfer_count = 0U;\r
+  ep->is_in = 0U;\r
+  ep->num = ep_addr & EP_ADDR_MSK;\r
+\r
+  if ((ep_addr & EP_ADDR_MSK) == 0U)\r
+  {\r
+    (void)USB_EP0StartXfer(hpcd->Instance, ep);\r
+  }\r
+  else\r
+  {\r
+    (void)USB_EPStartXfer(hpcd->Instance, ep);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Get Received Data Size\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @retval Data Size\r
+  */\r
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;\r
+}\r
+/**\r
+  * @brief  Send an amount of data\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @param  pBuf pointer to the transmission buffer\r
+  * @param  len amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
+{\r
+  PCD_EPTypeDef *ep;\r
+\r
+  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
+\r
+  /*setup and start the Xfer */\r
+  ep->xfer_buff = pBuf;\r
+  ep->xfer_len = len;\r
+  ep->xfer_count = 0U;\r
+  ep->is_in = 1U;\r
+  ep->num = ep_addr & EP_ADDR_MSK;\r
+\r
+  if ((ep_addr & EP_ADDR_MSK) == 0U)\r
+  {\r
+    (void)USB_EP0StartXfer(hpcd->Instance, ep);\r
+  }\r
+  else\r
+  {\r
+    (void)USB_EPStartXfer(hpcd->Instance, ep);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Set a STALL condition over an endpoint\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+  PCD_EPTypeDef *ep;\r
+\r
+  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if ((0x80U & ep_addr) == 0x80U)\r
+  {\r
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
+    ep->is_in = 1U;\r
+  }\r
+  else\r
+  {\r
+    ep = &hpcd->OUT_ep[ep_addr];\r
+    ep->is_in = 0U;\r
+  }\r
+\r
+  ep->is_stall = 1U;\r
+  ep->num = ep_addr & EP_ADDR_MSK;\r
+\r
+  __HAL_LOCK(hpcd);\r
+\r
+  (void)USB_EPSetStall(hpcd->Instance, ep);\r
+  if ((ep_addr & EP_ADDR_MSK) == 0U)\r
+  {\r
+    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);\r
+  }\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Clear a STALL condition over in an endpoint\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+  PCD_EPTypeDef *ep;\r
+\r
+  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if ((0x80U & ep_addr) == 0x80U)\r
+  {\r
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
+    ep->is_in = 1U;\r
+  }\r
+  else\r
+  {\r
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
+    ep->is_in = 0U;\r
+  }\r
+\r
+  ep->is_stall = 0U;\r
+  ep->num = ep_addr & EP_ADDR_MSK;\r
+\r
+  __HAL_LOCK(hpcd);\r
+  (void)USB_EPClearStall(hpcd->Instance, ep);\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Flush an endpoint\r
+  * @param  hpcd PCD handle\r
+  * @param  ep_addr endpoint address\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+  __HAL_LOCK(hpcd);\r
+\r
+  if ((ep_addr & 0x80U) == 0x80U)\r
+  {\r
+    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);\r
+  }\r
+  else\r
+  {\r
+    (void)USB_FlushRxFifo(hpcd->Instance);\r
+  }\r
+\r
+  __HAL_UNLOCK(hpcd);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Activate remote wakeup signalling\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
+{\r
+  return (USB_ActivateRemoteWakeup(hpcd->Instance));\r
+}\r
+\r
+/**\r
+  * @brief  De-activate remote wakeup signalling.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
+{\r
+  return (USB_DeActivateRemoteWakeup(hpcd->Instance));\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions\r
+ *  @brief   Peripheral State functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Peripheral State functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection permits to get in run-time the status of the peripheral\r
+    and the data flow.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Return the PCD handle state.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL state\r
+  */\r
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)\r
+{\r
+  return hpcd->State;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup PCD_Private_Functions\r
+  * @{\r
+  */\r
+#if defined (USB_OTG_FS)\r
+/**\r
+  * @brief  Check FIFO for the next packet to be loaded.\r
+  * @param  hpcd PCD handle\r
+  * @param  epnum endpoint number\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  USB_OTG_EPTypeDef *ep;\r
+  uint32_t len;\r
+  uint32_t len32b;\r
+  uint32_t fifoemptymsk;\r
+\r
+  ep = &hpcd->IN_ep[epnum];\r
+\r
+  if (ep->xfer_count > ep->xfer_len)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  len = ep->xfer_len - ep->xfer_count;\r
+\r
+  if (len > ep->maxpacket)\r
+  {\r
+    len = ep->maxpacket;\r
+  }\r
+\r
+  len32b = (len + 3U) / 4U;\r
+\r
+  while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&\r
+         (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))\r
+  {\r
+    /* Write the FIFO */\r
+    len = ep->xfer_len - ep->xfer_count;\r
+\r
+    if (len > ep->maxpacket)\r
+    {\r
+      len = ep->maxpacket;\r
+    }\r
+    len32b = (len + 3U) / 4U;\r
+\r
+    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len);\r
+\r
+    ep->xfer_buff  += len;\r
+    ep->xfer_count += len;\r
+  }\r
+\r
+  if (ep->xfer_len <= ep->xfer_count)\r
+  {\r
+    fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));\r
+    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  process EP OUT transfer complete interrupt.\r
+  * @param  hpcd PCD handle\r
+  * @param  epnum endpoint number\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\r
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;\r
+\r
+  if (gSNPSiD == USB_OTG_CORE_ID_310A)\r
+  {\r
+    /* StupPktRcvd = 1 this is a setup packet */\r
+    if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)\r
+    {\r
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\r
+    }\r
+    else\r
+    {\r
+      if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\r
+      {\r
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\r
+      }\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);\r
+#else\r
+      HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  else\r
+  {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);\r
+#else\r
+    HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  process EP OUT setup packet received interrupt.\r
+  * @param  hpcd PCD handle\r
+  * @param  epnum endpoint number\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\r
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;\r
+\r
+\r
+  if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&\r
+      ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))\r
+  {\r
+    CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\r
+  }\r
+\r
+  /* Inform the upper layer that a setup packet is available */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+  hpcd->SetupStageCallback(hpcd);\r
+#else\r
+  HAL_PCD_SetupStageCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+  return HAL_OK;\r
+}\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+/**\r
+  * @brief  This function handles PCD Endpoint interrupt request.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)\r
+{\r
+  PCD_EPTypeDef *ep;\r
+  uint16_t count;\r
+  uint16_t wIstr;\r
+  uint16_t wEPVal;\r
+  uint8_t epindex;\r
+\r
+  /* stay in loop while pending interrupts */\r
+  while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)\r
+  {\r
+    wIstr = hpcd->Instance->ISTR;\r
+    /* extract highest priority endpoint number */\r
+    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);\r
+\r
+    if (epindex == 0U)\r
+    {\r
+      /* Decode and service control endpoint interrupt */\r
+\r
+      /* DIR bit = origin of the interrupt */\r
+      if ((wIstr & USB_ISTR_DIR) == 0U)\r
+      {\r
+        /* DIR = 0 */\r
+\r
+        /* DIR = 0      => IN  int */\r
+        /* DIR = 0 implies that (EP_CTR_TX = 1) always  */\r
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);\r
+        ep = &hpcd->IN_ep[0];\r
+\r
+        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);\r
+        ep->xfer_buff += ep->xfer_count;\r
+\r
+        /* TX COMPLETE */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+        hpcd->DataInStageCallback(hpcd, 0U);\r
+#else\r
+        HAL_PCD_DataInStageCallback(hpcd, 0U);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+        if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))\r
+        {\r
+          hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);\r
+          hpcd->USB_Address = 0U;\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* DIR = 1 */\r
+\r
+        /* DIR = 1 & CTR_RX       => SETUP or OUT int */\r
+        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */\r
+        ep = &hpcd->OUT_ep[0];\r
+        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);\r
+\r
+        if ((wEPVal & USB_EP_SETUP) != 0U)\r
+        {\r
+          /* Get SETUP Packet*/\r
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);\r
+\r
+          USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,\r
+                      ep->pmaadress, (uint16_t)ep->xfer_count);\r
+\r
+          /* SETUP bit kept frozen while CTR_RX = 1*/\r
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);\r
+\r
+          /* Process SETUP Packet*/\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+          hpcd->SetupStageCallback(hpcd);\r
+#else\r
+          HAL_PCD_SetupStageCallback(hpcd);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+        }\r
+\r
+        else if ((wEPVal & USB_EP_CTR_RX) != 0U)\r
+        {\r
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);\r
+\r
+          /* Get Control Data OUT Packet*/\r
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);\r
+\r
+          if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))\r
+          {\r
+            USB_ReadPMA(hpcd->Instance, ep->xfer_buff,\r
+                        ep->pmaadress, (uint16_t)ep->xfer_count);\r
+\r
+            ep->xfer_buff += ep->xfer_count;\r
+\r
+            /* Process Control Data OUT Packet*/\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+            hpcd->DataOutStageCallback(hpcd, 0U);\r
+#else\r
+            HAL_PCD_DataOutStageCallback(hpcd, 0U);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+          }\r
+\r
+          PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);\r
+          PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Decode and service non control endpoints interrupt  */\r
+\r
+      /* process related endpoint register */\r
+      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);\r
+      if ((wEPVal & USB_EP_CTR_RX) != 0U)\r
+      {\r
+        /* clear int flag */\r
+        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);\r
+        ep = &hpcd->OUT_ep[epindex];\r
+\r
+        /* OUT double Buffering*/\r
+        if (ep->doublebuffer == 0U)\r
+        {\r
+          count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);\r
+          if (count != 0U)\r
+          {\r
+            USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);\r
+          }\r
+        }\r
+        else\r
+        {\r
+          if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)\r
+          {\r
+            /*read from endpoint BUF0Addr buffer*/\r
+            count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);\r
+            if (count != 0U)\r
+            {\r
+              USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);\r
+            }\r
+          }\r
+          else\r
+          {\r
+            /*read from endpoint BUF1Addr buffer*/\r
+            count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);\r
+            if (count != 0U)\r
+            {\r
+              USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);\r
+            }\r
+          }\r
+          /* free EP OUT Buffer */\r
+          PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);\r
+        }\r
+        /*multi-packet on the NON control OUT endpoint*/\r
+        ep->xfer_count += count;\r
+        ep->xfer_buff += count;\r
+\r
+        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))\r
+        {\r
+          /* RX COMPLETE */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+          hpcd->DataOutStageCallback(hpcd, ep->num);\r
+#else\r
+          HAL_PCD_DataOutStageCallback(hpcd, ep->num);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+        }\r
+        else\r
+        {\r
+          (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);\r
+        }\r
+\r
+      } /* if((wEPVal & EP_CTR_RX) */\r
+\r
+      if ((wEPVal & USB_EP_CTR_TX) != 0U)\r
+      {\r
+        ep = &hpcd->IN_ep[epindex];\r
+\r
+        /* clear int flag */\r
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);\r
+\r
+        /*multi-packet on the NON control IN endpoint*/\r
+        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);\r
+        ep->xfer_buff += ep->xfer_count;\r
+\r
+        /* Zero Length Packet? */\r
+        if (ep->xfer_len == 0U)\r
+        {\r
+          /* TX COMPLETE */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+          hpcd->DataInStageCallback(hpcd, ep->num);\r
+#else\r
+          HAL_PCD_DataInStageCallback(hpcd, ep->num);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+        }\r
+        else\r
+        {\r
+          (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);\r
+        }\r
+      }\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* defined (USB) || defined (USB_OTG_FS) */\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
new file mode 100644 (file)
index 0000000..b4a4842
--- /dev/null
@@ -0,0 +1,566 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pcd_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   PCD Extended HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the USB Peripheral Controller:\r
+  *           + Extended features functions\r
+  *\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PCDEx PCDEx\r
+  * @brief PCD Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+\r
+#if defined (USB) || defined (USB_OTG_FS)\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r
+  * @brief    PCDEx control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                 ##### Extended features functions #####\r
+ ===============================================================================\r
+    [..]  This section provides functions allowing to:\r
+      (+) Update FIFO configuration\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+#if defined (USB_OTG_FS)\r
+/**\r
+  * @brief  Set Tx FIFO\r
+  * @param  hpcd PCD handle\r
+  * @param  fifo The number of Tx fifo\r
+  * @param  size Fifo size\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)\r
+{\r
+  uint8_t i;\r
+  uint32_t Tx_Offset;\r
+\r
+  /*  TXn min size = 16 words. (n  : Transmit FIFO index)\r
+      When a TxFIFO is not used, the Configuration should be as follows:\r
+          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r
+         --> Txm can use the space allocated for Txn.\r
+         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r
+         --> Txn should be configured with the minimum space of 16 words\r
+     The FIFO is used optimally when used TxFIFOs are allocated in the top\r
+         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.\r
+     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */\r
+\r
+  Tx_Offset = hpcd->Instance->GRXFSIZ;\r
+\r
+  if (fifo == 0U)\r
+  {\r
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;\r
+  }\r
+  else\r
+  {\r
+    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;\r
+    for (i = 0U; i < (fifo - 1U); i++)\r
+    {\r
+      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);\r
+    }\r
+\r
+    /* Multiply Tx_Size by 2 to get higher performance */\r
+    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Set Rx FIFO\r
+  * @param  hpcd PCD handle\r
+  * @param  size Size of Rx fifo\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)\r
+{\r
+  hpcd->Instance->GRXFSIZ = size;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Activate LPM feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+\r
+  hpcd->lpm_active = 1U;\r
+  hpcd->LPM_State = LPM_L0;\r
+  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;\r
+  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Deactivate LPM feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+\r
+  hpcd->lpm_active = 0U;\r
+  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;\r
+  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Handle BatteryCharging Process.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Enable DCD : Data Contact Detect */\r
+  USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;\r
+\r
+  /* Wait Detect flag or a timeout is happen*/\r
+  while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)\r
+  {\r
+    /* Check for the Timeout */\r
+    if ((HAL_GetTick() - tickstart) > 1000U)\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);\r
+#else\r
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+      return;\r
+    }\r
+  }\r
+\r
+  /* Right response got */\r
+  HAL_Delay(200U);\r
+\r
+  /* Check Detect flag*/\r
+  if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)\r
+  {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
+#else\r
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /*Primary detection: checks if connected to Standard Downstream Port\r
+  (without charging capability) */\r
+  USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;\r
+  HAL_Delay(50U);\r
+  USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;\r
+  HAL_Delay(50U);\r
+\r
+  if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)\r
+  {\r
+    /* Case of Standard Downstream Port */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
+#else\r
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+    /* start secondary detection to check connection to Charging Downstream\r
+    Port or Dedicated Charging Port */\r
+    USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;\r
+    HAL_Delay(50U);\r
+    USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;\r
+    HAL_Delay(50U);\r
+\r
+    if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)\r
+    {\r
+      /* case Dedicated Charging Port  */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
+#else\r
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+    else\r
+    {\r
+      /* case Charging Downstream Port  */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
+#else\r
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+\r
+  /* Battery Charging capability discovery finished */\r
+  (void)HAL_PCDEx_DeActivateBCD(hpcd);\r
+\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
+#else\r
+  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  Activate BatteryCharging feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);\r
+\r
+  /* Power Down USB tranceiver  */\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+\r
+  /* Enable Battery charging */\r
+  USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;\r
+\r
+  hpcd->battery_charging_active = 1U;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Deactivate BatteryCharging feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);\r
+\r
+  /* Disable Battery charging */\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);\r
+\r
+  hpcd->battery_charging_active = 0U;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+#endif /* defined (USB_OTG_FS) */\r
+#if defined (USB)\r
+/**\r
+  * @brief  Configure PMA for EP\r
+  * @param  hpcd  Device instance\r
+  * @param  ep_addr endpoint address\r
+  * @param  ep_kind endpoint Kind\r
+  *                  USB_SNG_BUF: Single Buffer used\r
+  *                  USB_DBL_BUF: Double Buffer used\r
+  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint\r
+  *                   this parameter is 16-bit value providing the address\r
+  *                   in PMA allocated to endpoint.\r
+  *                   In case of double buffer endpoint this parameter\r
+  *                   is a 32-bit value providing the endpoint buffer 0 address\r
+  *                   in the LSB part of 32-bit value and endpoint buffer 1 address\r
+  *                   in the MSB part of 32-bit value.\r
+  * @retval HAL status\r
+  */\r
+\r
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,\r
+                                       uint16_t ep_addr,\r
+                                       uint16_t ep_kind,\r
+                                       uint32_t pmaadress)\r
+{\r
+  PCD_EPTypeDef *ep;\r
+\r
+  /* initialize ep structure*/\r
+  if ((0x80U & ep_addr) == 0x80U)\r
+  {\r
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
+  }\r
+  else\r
+  {\r
+    ep = &hpcd->OUT_ep[ep_addr];\r
+  }\r
+\r
+  /* Here we check if the endpoint is single or double Buffer*/\r
+  if (ep_kind == PCD_SNG_BUF)\r
+  {\r
+    /* Single Buffer */\r
+    ep->doublebuffer = 0U;\r
+    /* Configure the PMA */\r
+    ep->pmaadress = (uint16_t)pmaadress;\r
+  }\r
+  else /* USB_DBL_BUF */\r
+  {\r
+    /* Double Buffer Endpoint */\r
+    ep->doublebuffer = 1U;\r
+    /* Configure the PMA */\r
+    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);\r
+    ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Activate BatteryCharging feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_TypeDef *USBx = hpcd->Instance;\r
+  hpcd->battery_charging_active = 1U;\r
+\r
+  /* Enable DCD : Data Contact Detect */\r
+  USBx->BCDR &= ~(USB_BCDR_PDEN);\r
+  USBx->BCDR &= ~(USB_BCDR_SDEN);\r
+  USBx->BCDR |= USB_BCDR_DCDEN;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Deactivate BatteryCharging feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_TypeDef *USBx = hpcd->Instance;\r
+  hpcd->battery_charging_active = 0U;\r
+\r
+  USBx->BCDR &= ~(USB_BCDR_BCDEN);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handle BatteryCharging Process.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_TypeDef *USBx = hpcd->Instance;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Wait Detect flag or a timeout is happen*/\r
+  while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)\r
+  {\r
+    /* Check for the Timeout */\r
+    if ((HAL_GetTick() - tickstart) > 1000U)\r
+    {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);\r
+#else\r
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+\r
+      return;\r
+    }\r
+  }\r
+\r
+  HAL_Delay(200U);\r
+\r
+  /* Data Pin Contact ? Check Detect flag */\r
+  if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)\r
+  {\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
+#else\r
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+  }\r
+  /* Primary detection: checks if connected to Standard Downstream Port\r
+  (without charging capability) */\r
+  USBx->BCDR &= ~(USB_BCDR_DCDEN);\r
+  HAL_Delay(50U);\r
+  USBx->BCDR |= (USB_BCDR_PDEN);\r
+  HAL_Delay(50U);\r
+\r
+  /* If Charger detect ? */\r
+  if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)\r
+  {\r
+    /* Start secondary detection to check connection to Charging Downstream\r
+    Port or Dedicated Charging Port */\r
+    USBx->BCDR &= ~(USB_BCDR_PDEN);\r
+    HAL_Delay(50U);\r
+    USBx->BCDR |= (USB_BCDR_SDEN);\r
+    HAL_Delay(50U);\r
+\r
+    /* If CDP ? */\r
+    if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)\r
+    {\r
+      /* Dedicated Downstream Port DCP */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
+#else\r
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+    else\r
+    {\r
+      /* Charging Downstream Port CDP */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
+#else\r
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  else /* NO */\r
+  {\r
+    /* Standard Downstream Port */\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
+#else\r
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Battery Charging capability discovery finished Start Enumeration */\r
+  (void)HAL_PCDEx_DeActivateBCD(hpcd);\r
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
+  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
+#else\r
+  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Activate LPM feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+\r
+  USB_TypeDef *USBx = hpcd->Instance;\r
+  hpcd->lpm_active = 1U;\r
+  hpcd->LPM_State = LPM_L0;\r
+\r
+  USBx->LPMCSR |= USB_LPMCSR_LMPEN;\r
+  USBx->LPMCSR |= USB_LPMCSR_LPMACK;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Deactivate LPM feature.\r
+  * @param  hpcd PCD handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+  USB_TypeDef *USBx = hpcd->Instance;\r
+\r
+  hpcd->lpm_active = 0U;\r
+\r
+  USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);\r
+  USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @brief  Send LPM message to user layer callback.\r
+  * @param  hpcd PCD handle\r
+  * @param  msg LPM message\r
+  * @retval HAL status\r
+  */\r
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+  UNUSED(msg);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Send BatteryCharging message to user layer callback.\r
+  * @param  hpcd PCD handle\r
+  * @param  msg LPM message\r
+  * @retval HAL status\r
+  */\r
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hpcd);\r
+  UNUSED(msg);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* defined (USB) || defined (USB_OTG_FS) */\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
new file mode 100644 (file)
index 0000000..ba44650
--- /dev/null
@@ -0,0 +1,661 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pwr.c\r
+  * @author  MCD Application Team\r
+  * @brief   PWR HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Power Controller (PWR) peripheral:\r
+  *           + Initialization/de-initialization functions\r
+  *           + Peripheral Control functions\r
+  *\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWR PWR\r
+  * @brief PWR HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Private_Defines PWR Private Defines\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
+  * @{\r
+  */\r
+#define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */\r
+#define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */\r
+#define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */\r
+#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  *  @brief    Initialization and de-initialization functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+              ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+    [..]\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+  __HAL_RCC_PWR_FORCE_RESET();\r
+  __HAL_RCC_PWR_RELEASE_RESET();\r
+}\r
+\r
+/**\r
+  * @brief Enable access to the backup domain\r
+  *        (RTC registers, RTC backup data registers).\r
+  * @note  After reset, the backup domain is protected against\r
+  *        possible unwanted write accesses.\r
+  * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.\r
+  *        In order to set or modify the RTC clock, the backup domain access must be\r
+  *        disabled.\r
+  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the\r
+  *        back-up domain.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+  * @brief Disable access to the backup domain\r
+  *        (RTC registers, RTC backup data registers).\r
+  * @retval None\r
+  */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
+  *  @brief Low Power modes configuration functions\r
+  *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+                 ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+\r
+     [..]\r
+     *** PVD configuration ***\r
+    =========================\r
+    [..]\r
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a\r
+          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).\r
+\r
+      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower\r
+          than the PVD threshold. This event is internally connected to the EXTI\r
+          line16 and can generate an interrupt if enabled. This is done through\r
+          __HAL_PVD_EXTI_ENABLE_IT() macro.\r
+      (+) The PVD is stopped in Standby mode.\r
+\r
+\r
+    *** WakeUp pin configuration ***\r
+    ================================\r
+    [..]\r
+      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.\r
+          The polarity of these pins can be set to configure event detection on high\r
+          level (rising edge) or low level (falling edge).\r
+\r
+\r
+\r
+    *** Low Power modes configuration ***\r
+    =====================================\r
+    [..]\r
+      The devices feature 8 low-power modes:\r
+      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.\r
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.\r
+      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.\r
+      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.\r
+      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.\r
+      (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.\r
+      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.\r
+      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.\r
+      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.\r
+\r
+\r
+   *** Low-power run mode ***\r
+   ==========================\r
+    [..]\r
+      (+) Entry: (from main run mode)\r
+        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.\r
+\r
+      (+) Exit:\r
+        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only\r
+             then can the system clock frequency be increased above 2 MHz.\r
+\r
+\r
+   *** Sleep mode / Low-power sleep mode ***\r
+   =========================================\r
+    [..]\r
+      (+) Entry:\r
+          The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API\r
+          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.\r
+          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).\r
+          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).\r
+          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.\r
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+\r
+      (+) WFI Exit:\r
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt\r
+             controller (NVIC) or any wake-up event.\r
+\r
+      (+) WFE Exit:\r
+        (++) Any wake-up event such as an EXTI line configured in event mode.\r
+\r
+         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,\r
+             the MCU is in Low-power Run mode.\r
+\r
+   *** Stop 0, Stop 1 and Stop 2 modes ***\r
+   ===============================\r
+    [..]\r
+      (+) Entry:\r
+          The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:\r
+          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().\r
+          (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.\r
+      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):\r
+          (++) PWR_MAINREGULATOR_ON\r
+          (++) PWR_LOWPOWERREGULATOR_ON\r
+      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):\r
+          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction\r
+          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction\r
+\r
+      (+) WFI Exit:\r
+          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.\r
+          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts\r
+               when programmed in wakeup mode.\r
+      (+) WFE Exit:\r
+          (++) Any EXTI Line (Internal or External) configured in Event mode.\r
+\r
+       [..]\r
+          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode\r
+          depending on the LPR bit setting.\r
+          When exiting Stop 2 mode, the MCU is in Run mode.\r
+\r
+   *** Standby mode ***\r
+   ====================\r
+     [..]\r
+      The Standby mode offers two options:\r
+      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).\r
+        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers\r
+        and Standby circuitry.\r
+      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).\r
+        SRAM and register contents are lost except for the RTC registers, RTC backup registers\r
+        and Standby circuitry.\r
+\r
+      (++) Entry:\r
+          (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.\r
+                SRAM1 and register contents are lost except for registers in the Backup domain and\r
+                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.\r
+                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API\r
+                to set RRS bit.\r
+\r
+      (++) Exit:\r
+          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,\r
+                external reset in NRST pin, IWDG reset.\r
+\r
+      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.\r
+\r
+\r
+    *** Shutdown mode ***\r
+   ======================\r
+     [..]\r
+      In Shutdown mode,\r
+        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.\r
+        SRAM and registers contents are lost except for backup domain registers.\r
+\r
+      (+) Entry:\r
+          The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.\r
+\r
+      (+) Exit:\r
+          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,\r
+               external reset in NRST pin.\r
+\r
+         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.\r
+\r
+\r
+   *** Auto-wakeup (AWU) from low-power mode ***\r
+   =============================================\r
+    [..]\r
+      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC\r
+      Wakeup event, a tamper event or a time-stamp event, without depending on\r
+      an external interrupt (Auto-wakeup mode).\r
+\r
+      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes\r
+\r
+\r
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to\r
+             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
+\r
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it\r
+             is necessary to configure the RTC to detect the tamper or time stamp event using the\r
+             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
+\r
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
+              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+\r
+\r
+/**\r
+  * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).\r
+  * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD\r
+  *        configuration information.\r
+  * @note Refer to the electrical characteristics of your device datasheet for\r
+  *         more details about the voltage thresholds corresponding to each\r
+  *         detection level.\r
+  * @retval None\r
+  */\r
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+\r
+  /* Set PLS bits according to PVDLevel value */\r
+  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);\r
+\r
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
+\r
+  /* Configure interrupt mode */\r
+  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+  {\r
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+  }\r
+\r
+  /* Configure event mode */\r
+  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+  {\r
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+  }\r
+\r
+  /* Configure the edge */\r
+  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+  {\r
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+  }\r
+\r
+  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+  {\r
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enable the Power Voltage Detector (PVD).\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+  SET_BIT(PWR->CR2, PWR_CR2_PVDE);\r
+}\r
+\r
+/**\r
+  * @brief Disable the Power Voltage Detector (PVD).\r
+  * @retval None\r
+  */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+  * @brief Enable the WakeUp PINx functionality.\r
+  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r
+  *         This parameter can be one of the following legacy values which set the default polarity\r
+  *         i.e. detection on high level (rising edge):\r
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5\r
+  *\r
+  *         or one of the following value where the user can explicitly specify the enabled pin and\r
+  *         the chosen polarity:\r
+  *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW\r
+  *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW\r
+  *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW\r
+  *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
+  *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW\r
+  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
+{\r
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
+\r
+  /* Specifies the Wake-Up pin polarity for the event detection\r
+    (rising or falling edge) */\r
+  MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));\r
+\r
+  /* Enable wake-up pin */\r
+  SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));\r
+\r
+\r
+}\r
+\r
+/**\r
+  * @brief Disable the WakeUp PINx functionality.\r
+  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5\r
+  * @retval None\r
+  */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+\r
+  CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enter Sleep or Low-power Sleep mode.\r
+  * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.\r
+  * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)\r
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)\r
+  * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet\r
+  *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set\r
+  *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the\r
+  *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.\r
+  *        Additionally, the clock frequency must be reduced below 2 MHz.\r
+  *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must\r
+  *        be done before calling HAL_PWR_EnterSLEEPMode() API.\r
+  * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in\r
+  *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.\r
+  * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.\r
+  *           This parameter can be one of the following values:\r
+  *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction\r
+  *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction\r
+  * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as\r
+  *        the interrupt wake up source.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_REGULATOR(Regulator));\r
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+  /* Set Regulator parameter */\r
+  if (Regulator == PWR_MAINREGULATOR_ON)\r
+  {\r
+    /* If in low-power run mode at this point, exit it */\r
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))\r
+    {\r
+      if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)\r
+      {\r
+        return ;\r
+      }\r
+    }\r
+    /* Regulator now in main mode. */\r
+  }\r
+  else\r
+  {\r
+    /* If in run mode, first move to low-power run mode.\r
+       The system clock frequency must be below 2 MHz at this point. */\r
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)\r
+    {\r
+      HAL_PWREx_EnableLowPowerRunMode();\r
+    }\r
+  }\r
+\r
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+  /* Select SLEEP mode entry -------------------------------------------------*/\r
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+  {\r
+    /* Request Wait For Interrupt */\r
+    __WFI();\r
+  }\r
+  else\r
+  {\r
+    /* Request Wait For Event */\r
+    __SEV();\r
+    __WFE();\r
+    __WFE();\r
+  }\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enter Stop mode\r
+  * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running\r
+  *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.\r
+  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.\r
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
+  *        only to the peripheral requesting it.\r
+  *        SRAM1, SRAM2 and register contents are preserved.\r
+  *        The BOR is available.\r
+  *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).\r
+  * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,\r
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+  * @note  When the voltage regulator operates in low power mode (Stop 1), an additional\r
+  *         startup delay is incurred when waking up.\r
+  *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption\r
+  *         is higher although the startup time is reduced.\r
+  * @param Regulator: Specifies the regulator state in Stop mode.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)\r
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)\r
+  * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.\r
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_REGULATOR(Regulator));\r
+\r
+  if(Regulator == PWR_LOWPOWERREGULATOR_ON)\r
+  {\r
+    HAL_PWREx_EnterSTOP1Mode(STOPEntry);\r
+  }\r
+  else\r
+  {\r
+    HAL_PWREx_EnterSTOP0Mode(STOPEntry);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Enter Standby mode.\r
+  * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched\r
+  *        off. The voltage regulator is disabled, except when SRAM2 content is preserved\r
+  *        in which case the regulator is in low-power mode.\r
+  *        SRAM1 and register contents are lost except for registers in the Backup domain and\r
+  *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.\r
+  *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API\r
+  *        to set RRS bit.\r
+  *        The BOR is available.\r
+  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.\r
+  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and\r
+  *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the\r
+  *        same.\r
+  *        These states are effective in Standby mode only if APC bit is set through\r
+  *        HAL_PWREx_EnablePullUpPullDownConfig() API.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+  /* Set Stand-by mode */\r
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);\r
+\r
+  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+  __force_stores();\r
+#endif\r
+  /* Request Wait For Interrupt */\r
+  __WFI();\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.\r
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+  *       re-enters SLEEP mode when an interruption handling is over.\r
+  *       Setting this bit is useful when the processor is expected to run only on\r
+  *       interruptions handling.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.\r
+  * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+  *       re-enters SLEEP mode when an interruption handling is over.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Enable CORTEX M4 SEVONPEND bit.\r
+  * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes\r
+  *       WFE to wake up when an interrupt moves from inactive to pended.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+  /* Set SEVONPEND bit of Cortex System Control Register */\r
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable CORTEX M4 SEVONPEND bit.\r
+  * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes\r
+  *       WFE to wake up when an interrupt moves from inactive to pended.\r
+  * @retval None\r
+  */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+  /* Clear SEVONPEND bit of Cortex System Control Register */\r
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+  * @brief PWR PVD interrupt callback\r
+  * @retval None\r
+  */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+  /* NOTE : This function should not be modified; when the callback is needed,\r
+            the HAL_PWR_PVDCallback can be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
new file mode 100644 (file)
index 0000000..9adf448
--- /dev/null
@@ -0,0 +1,1446 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_pwr_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   Extended PWR HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Power Controller (PWR) peripheral:\r
+  *           + Extended Initialization and de-initialization functions\r
+  *           + Extended Peripheral Control functions\r
+  *\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWREx PWREx\r
+  * @brief PWR Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)\r
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */\r
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */\r
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)\r
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x00000003) /* PH0/PH1 */\r
+#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000FFFF) /* PH0..PH15 */\r
+#endif\r
+\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define PWR_PORTI_AVAILABLE_PINS   ((uint32_t)0x00000FFF) /* PI0..PI11 */\r
+#endif\r
+\r
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask\r
+  * @{\r
+  */\r
+#define PVM_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVM threshold crossing */\r
+#define PVM_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVM threshold crossing        */\r
+#define PVM_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVM trigger                 */\r
+#define PVM_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVM trigger                */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value\r
+  * @{\r
+  */\r
+#define PWR_FLAG_SETTING_DELAY_US                      50UL   /*!< Time out value for REGLPF and VOSF flags setting */\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions\r
+  *  @brief   Extended Peripheral Control functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+              ##### Extended Peripheral Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+    [..]\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+\r
+/**\r
+  * @brief Return Voltage Scaling Range.\r
+  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2\r
+  *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)\r
+  */\r
+uint32_t HAL_PWREx_GetVoltageRange(void)\r
+{\r
+#if defined(PWR_CR5_R1MODE)\r
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
+    {\r
+      return PWR_REGULATOR_VOLTAGE_SCALE2;\r
+    }\r
+    else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)\r
+    {\r
+      /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */\r
+      return PWR_REGULATOR_VOLTAGE_SCALE1;\r
+    }\r
+    else\r
+    {\r
+      return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;\r
+    }\r
+#else\r
+  return  (PWR->CR1 & PWR_CR1_VOS);\r
+#endif\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Configure the main internal regulator output voltage.\r
+  * @param  VoltageScaling: specifies the regulator output voltage to achieve\r
+  *         a tradeoff between performance and power consumption.\r
+  *          This parameter can be one of the following values:\r
+  @if STM32L4S9xx\r
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,\r
+  *                                                typical output voltage at 1.2 V,\r
+  *                                                system frequency up to 120 MHz.\r
+  @endif\r
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,\r
+  *                                                typical output voltage at 1.2 V,\r
+  *                                                system frequency up to 80 MHz.\r
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,\r
+  *                                                typical output voltage at 1.0 V,\r
+  *                                                system frequency up to 26 MHz.\r
+  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to\r
+  *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.\r
+  *        When moving from Range 2 to Range 1, the system frequency can be increased to\r
+  *        a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For\r
+  *        some devices, the system frequency can be increased up to 120 MHz.\r
+  * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be\r
+  *        cleared before returning the status. If the flag is not cleared within\r
+  *        50 microseconds, HAL_TIMEOUT status is reported.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r
+{\r
+  uint32_t wait_loop_index;\r
+\r
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));\r
+\r
+#if defined(PWR_CR5_R1MODE)\r
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)\r
+  {\r
+    /* If current range is range 2 */\r
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
+    {\r
+      /* Make sure Range 1 Boost is enabled */\r
+      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+\r
+      /* Set Range 1 */\r
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+      /* Wait until VOSF is cleared */\r
+      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;\r
+      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
+      {\r
+        wait_loop_index--;\r
+      }\r
+      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
+      {\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+    /* If current range is range 1 normal or boost mode */\r
+    else\r
+    {\r
+      /* Enable Range 1 Boost (no issue if bit already reset) */\r
+      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+    }\r
+  }\r
+  else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)\r
+  {\r
+    /* If current range is range 2 */\r
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
+    {\r
+      /* Make sure Range 1 Boost is disabled */\r
+      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+\r
+      /* Set Range 1 */\r
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+      /* Wait until VOSF is cleared */\r
+      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;\r
+      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
+      {\r
+        wait_loop_index--;\r
+      }\r
+      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
+      {\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+     /* If current range is range 1 normal or boost mode */\r
+    else\r
+    {\r
+      /* Disable Range 1 Boost (no issue if bit already set) */\r
+      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Set Range 2 */\r
+    MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);\r
+    /* No need to wait for VOSF to be cleared for this transition */\r
+    /* PWR_CR5_R1MODE bit setting has no effect in Range 2        */\r
+  }\r
+\r
+#else\r
+\r
+  /* If Set Range 1 */\r
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)\r
+  {\r
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)\r
+    {\r
+      /* Set Range 1 */\r
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+      /* Wait until VOSF is cleared */\r
+      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;\r
+      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
+      {\r
+        wait_loop_index--;\r
+      }\r
+      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
+      {\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+  }\r
+  else\r
+  {\r
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)\r
+    {\r
+      /* Set Range 2 */\r
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);\r
+      /* No need to wait for VOSF to be cleared for this transition */\r
+    }\r
+  }\r
+#endif\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enable battery charging.\r
+  *        When VDD is present, charge the external battery on VBAT thru an internal resistor.\r
+  * @param  ResistorSelection: specifies the resistor impedance.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor\r
+  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)\r
+{\r
+  assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));\r
+\r
+  /* Specify resistor selection */\r
+  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);\r
+\r
+  /* Enable battery charging */\r
+  SET_BIT(PWR->CR4, PWR_CR4_VBE);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable battery charging.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableBatteryCharging(void)\r
+{\r
+  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);\r
+}\r
+\r
+\r
+#if defined(PWR_CR2_USV)\r
+/**\r
+  * @brief Enable VDDUSB supply.\r
+  * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableVddUSB(void)\r
+{\r
+  SET_BIT(PWR->CR2, PWR_CR2_USV);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable VDDUSB supply.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableVddUSB(void)\r
+{\r
+  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);\r
+}\r
+#endif /* PWR_CR2_USV */\r
+\r
+#if defined(PWR_CR2_IOSV)\r
+/**\r
+  * @brief Enable VDDIO2 supply.\r
+  * @note  Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableVddIO2(void)\r
+{\r
+  SET_BIT(PWR->CR2, PWR_CR2_IOSV);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable VDDIO2 supply.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableVddIO2(void)\r
+{\r
+  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);\r
+}\r
+#endif /* PWR_CR2_IOSV */\r
+\r
+\r
+/**\r
+  * @brief Enable Internal Wake-up Line.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableInternalWakeUpLine(void)\r
+{\r
+  SET_BIT(PWR->CR3, PWR_CR3_EIWF);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable Internal Wake-up Line.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableInternalWakeUpLine(void)\r
+{\r
+  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Enable GPIO pull-up state in Standby and Shutdown modes.\r
+  * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in\r
+  *        pull-up state in Standby and Shutdown modes.\r
+  * @note  This state is effective in Standby and Shutdown modes only if APC bit\r
+  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.\r
+  * @note  The configuration is lost when exiting the Shutdown mode due to the\r
+  *        power-on reset, maintained when exiting the Standby mode.\r
+  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding\r
+  *        PDy bit of PWR_PDCRx register is cleared unless it is reserved.\r
+  * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input\r
+  *        parameter at the same time are set.\r
+  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H\r
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+  * @param  GPIONumber: Specify the I/O pins numbers.\r
+  *         This parameter can be one of the following values:\r
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+  *         I/O pins are available) or the logical OR of several of them to set\r
+  *         several bits for a given port in a single API call.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  assert_param(IS_PWR_GPIO(GPIO));\r
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+  switch (GPIO)\r
+  {\r
+    case PWR_GPIO_A:\r
+       SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
+       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
+       break;\r
+    case PWR_GPIO_B:\r
+       SET_BIT(PWR->PUCRB, GPIONumber);\r
+       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
+       break;\r
+    case PWR_GPIO_C:\r
+       SET_BIT(PWR->PUCRC, GPIONumber);\r
+       CLEAR_BIT(PWR->PDCRC, GPIONumber);\r
+       break;\r
+#if defined(GPIOD)\r
+    case PWR_GPIO_D:\r
+       SET_BIT(PWR->PUCRD, GPIONumber);\r
+       CLEAR_BIT(PWR->PDCRD, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOE)\r
+    case PWR_GPIO_E:\r
+       SET_BIT(PWR->PUCRE, GPIONumber);\r
+       CLEAR_BIT(PWR->PDCRE, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOF)\r
+    case PWR_GPIO_F:\r
+       SET_BIT(PWR->PUCRF, GPIONumber);\r
+       CLEAR_BIT(PWR->PDCRF, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOG)\r
+    case PWR_GPIO_G:\r
+       SET_BIT(PWR->PUCRG, GPIONumber);\r
+       CLEAR_BIT(PWR->PDCRG, GPIONumber);\r
+       break;\r
+#endif\r
+    case PWR_GPIO_H:\r
+       SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
+       CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
+#else\r
+       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#endif\r
+       break;\r
+#if defined(GPIOI)\r
+    case PWR_GPIO_I:\r
+       SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+       CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+       break;\r
+#endif\r
+    default:\r
+      status = HAL_ERROR;\r
+      break;\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.\r
+  * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O\r
+  *        in pull-up state in Standby and Shutdown modes.\r
+  * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input\r
+  *        parameter at the same time are reset.\r
+  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H\r
+  *          (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+  * @param  GPIONumber: Specify the I/O pins numbers.\r
+  *         This parameter can be one of the following values:\r
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+  *         I/O pins are available) or the logical OR of several of them to reset\r
+  *         several bits for a given port in a single API call.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  assert_param(IS_PWR_GPIO(GPIO));\r
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+  switch (GPIO)\r
+  {\r
+    case PWR_GPIO_A:\r
+       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
+       break;\r
+    case PWR_GPIO_B:\r
+       CLEAR_BIT(PWR->PUCRB, GPIONumber);\r
+       break;\r
+    case PWR_GPIO_C:\r
+       CLEAR_BIT(PWR->PUCRC, GPIONumber);\r
+       break;\r
+#if defined(GPIOD)\r
+    case PWR_GPIO_D:\r
+       CLEAR_BIT(PWR->PUCRD, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOE)\r
+    case PWR_GPIO_E:\r
+       CLEAR_BIT(PWR->PUCRE, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOF)\r
+    case PWR_GPIO_F:\r
+       CLEAR_BIT(PWR->PUCRF, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOG)\r
+    case PWR_GPIO_G:\r
+       CLEAR_BIT(PWR->PUCRG, GPIONumber);\r
+       break;\r
+#endif\r
+    case PWR_GPIO_H:\r
+       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+       break;\r
+#if defined(GPIOI)\r
+    case PWR_GPIO_I:\r
+       CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+       break;\r
+#endif\r
+    default:\r
+       status = HAL_ERROR;\r
+       break;\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Enable GPIO pull-down state in Standby and Shutdown modes.\r
+  * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in\r
+  *        pull-down state in Standby and Shutdown modes.\r
+  * @note  This state is effective in Standby and Shutdown modes only if APC bit\r
+  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.\r
+  * @note  The configuration is lost when exiting the Shutdown mode due to the\r
+  *        power-on reset, maintained when exiting the Standby mode.\r
+  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding\r
+  *        PUy bit of PWR_PUCRx register is cleared unless it is reserved.\r
+  * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input\r
+  *        parameter at the same time are set.\r
+  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H\r
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+  * @param  GPIONumber: Specify the I/O pins numbers.\r
+  *         This parameter can be one of the following values:\r
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+  *         I/O pins are available) or the logical OR of several of them to set\r
+  *         several bits for a given port in a single API call.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  assert_param(IS_PWR_GPIO(GPIO));\r
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+  switch (GPIO)\r
+  {\r
+    case PWR_GPIO_A:\r
+       SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
+       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
+       break;\r
+    case PWR_GPIO_B:\r
+       SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
+       CLEAR_BIT(PWR->PUCRB, GPIONumber);\r
+       break;\r
+    case PWR_GPIO_C:\r
+       SET_BIT(PWR->PDCRC, GPIONumber);\r
+       CLEAR_BIT(PWR->PUCRC, GPIONumber);\r
+       break;\r
+#if defined(GPIOD)\r
+    case PWR_GPIO_D:\r
+       SET_BIT(PWR->PDCRD, GPIONumber);\r
+       CLEAR_BIT(PWR->PUCRD, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOE)\r
+    case PWR_GPIO_E:\r
+       SET_BIT(PWR->PDCRE, GPIONumber);\r
+       CLEAR_BIT(PWR->PUCRE, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOF)\r
+    case PWR_GPIO_F:\r
+       SET_BIT(PWR->PDCRF, GPIONumber);\r
+       CLEAR_BIT(PWR->PUCRF, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOG)\r
+    case PWR_GPIO_G:\r
+       SET_BIT(PWR->PDCRG, GPIONumber);\r
+       CLEAR_BIT(PWR->PUCRG, GPIONumber);\r
+       break;\r
+#endif\r
+    case PWR_GPIO_H:\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
+       SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
+#else\r
+       SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#endif\r
+       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+       break;\r
+#if defined(GPIOI)\r
+    case PWR_GPIO_I:\r
+       SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+       CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+       break;\r
+#endif\r
+    default:\r
+      status = HAL_ERROR;\r
+      break;\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable GPIO pull-down state in Standby and Shutdown modes.\r
+  * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O\r
+  *        in pull-down state in Standby and Shutdown modes.\r
+  * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input\r
+  *        parameter at the same time are reset.\r
+  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H\r
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+  * @param  GPIONumber: Specify the I/O pins numbers.\r
+  *         This parameter can be one of the following values:\r
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+  *         I/O pins are available) or the logical OR of several of them to reset\r
+  *         several bits for a given port in a single API call.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  assert_param(IS_PWR_GPIO(GPIO));\r
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+  switch (GPIO)\r
+  {\r
+    case PWR_GPIO_A:\r
+       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
+       break;\r
+    case PWR_GPIO_B:\r
+       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
+       break;\r
+    case PWR_GPIO_C:\r
+       CLEAR_BIT(PWR->PDCRC, GPIONumber);\r
+       break;\r
+#if defined(GPIOD)\r
+    case PWR_GPIO_D:\r
+       CLEAR_BIT(PWR->PDCRD, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOE)\r
+    case PWR_GPIO_E:\r
+       CLEAR_BIT(PWR->PDCRE, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOF)\r
+    case PWR_GPIO_F:\r
+       CLEAR_BIT(PWR->PDCRF, GPIONumber);\r
+       break;\r
+#endif\r
+#if defined(GPIOG)\r
+    case PWR_GPIO_G:\r
+       CLEAR_BIT(PWR->PDCRG, GPIONumber);\r
+       break;\r
+#endif\r
+    case PWR_GPIO_H:\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
+       CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
+#else\r
+       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#endif\r
+       break;\r
+#if defined(GPIOI)\r
+    case PWR_GPIO_I:\r
+       CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+       break;\r
+#endif\r
+    default:\r
+      status = HAL_ERROR;\r
+      break;\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Enable pull-up and pull-down configuration.\r
+  * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in\r
+  *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.\r
+  * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding\r
+  *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).\r
+  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there\r
+  *        is no conflict when setting PUy or PDy bit.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnablePullUpPullDownConfig(void)\r
+{\r
+  SET_BIT(PWR->CR3, PWR_CR3_APC);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable pull-up and pull-down configuration.\r
+  * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in\r
+  *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisablePullUpPullDownConfig(void)\r
+{\r
+  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Enable SRAM2 content retention in Standby mode.\r
+  * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in\r
+  *         Standby mode and its content is kept.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableSRAM2ContentRetention(void)\r
+{\r
+  SET_BIT(PWR->CR3, PWR_CR3_RRS);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable SRAM2 content retention in Standby mode.\r
+  * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode\r
+  *        and its content is lost.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableSRAM2ContentRetention(void)\r
+{\r
+  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);\r
+}\r
+\r
+\r
+#if defined(PWR_CR3_ENULP)\r
+/**\r
+  * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.\r
+  * @note  All the other modes are not affected by this bit.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableBORPVD_ULP(void)\r
+{\r
+  SET_BIT(PWR->CR3, PWR_CR3_ENULP);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.\r
+  * @note  All the other modes are not affected by this bit\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableBORPVD_ULP(void)\r
+{\r
+  CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);\r
+}\r
+#endif /* PWR_CR3_ENULP */\r
+\r
+\r
+#if defined(PWR_CR4_EXT_SMPS_ON)\r
+/**\r
+  * @brief Enable the CFLDO working @ 0.95V.\r
+  * @note  When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the\r
+  *        internal CFLDO can be reduced to 0.95V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableExtSMPS_0V95(void)\r
+{\r
+  SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\r
+}\r
+\r
+/**\r
+  * @brief Disable the CFLDO working @ 0.95V\r
+  * @note  Before SMPS is switched off, the regulated voltage of the\r
+  *        internal CFLDO shall be set to 1.00V.\r
+  *        1.00V. is also default operating Range 2 voltage.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableExtSMPS_0V95(void)\r
+{\r
+  CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\r
+}\r
+#endif /* PWR_CR4_EXT_SMPS_ON */\r
+\r
+\r
+#if defined(PWR_CR1_RRSTP)\r
+/**\r
+  * @brief Enable SRAM3 content retention in Stop 2 mode.\r
+  * @note  When RRSTP bit is set, SRAM3 is powered by the low-power regulator in\r
+  *        Stop 2 mode and its content is kept.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableSRAM3ContentRetention(void)\r
+{\r
+  SET_BIT(PWR->CR1, PWR_CR1_RRSTP);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable SRAM3 content retention in Stop 2 mode.\r
+  * @note  When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode\r
+  *        and its content is lost.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableSRAM3ContentRetention(void)\r
+{\r
+  CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);\r
+}\r
+#endif /* PWR_CR1_RRSTP */\r
+\r
+#if defined(PWR_CR3_DSIPDEN)\r
+/**\r
+  * @brief Enable pull-down activation on DSI pins.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableDSIPinsPDActivation(void)\r
+{\r
+  SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Disable pull-down activation on DSI pins.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisableDSIPinsPDActivation(void)\r
+{\r
+  CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\r
+}\r
+#endif /* PWR_CR3_DSIPDEN */\r
+\r
+#if defined(PWR_CR2_PVME1)\r
+/**\r
+  * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnablePVM1(void)\r
+{\r
+  SET_BIT(PWR->CR2, PWR_PVM_1);\r
+}\r
+\r
+/**\r
+  * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisablePVM1(void)\r
+{\r
+  CLEAR_BIT(PWR->CR2, PWR_PVM_1);\r
+}\r
+#endif /* PWR_CR2_PVME1 */\r
+\r
+\r
+#if defined(PWR_CR2_PVME2)\r
+/**\r
+  * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnablePVM2(void)\r
+{\r
+  SET_BIT(PWR->CR2, PWR_PVM_2);\r
+}\r
+\r
+/**\r
+  * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisablePVM2(void)\r
+{\r
+  CLEAR_BIT(PWR->CR2, PWR_PVM_2);\r
+}\r
+#endif /* PWR_CR2_PVME2 */\r
+\r
+\r
+/**\r
+  * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnablePVM3(void)\r
+{\r
+  SET_BIT(PWR->CR2, PWR_PVM_3);\r
+}\r
+\r
+/**\r
+  * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisablePVM3(void)\r
+{\r
+  CLEAR_BIT(PWR->CR2, PWR_PVM_3);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enable the Power Voltage Monitoring 4:  VDDA versus 2.2V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnablePVM4(void)\r
+{\r
+  SET_BIT(PWR->CR2, PWR_PVM_4);\r
+}\r
+\r
+/**\r
+  * @brief Disable the Power Voltage Monitoring 4:  VDDA versus 2.2V.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_DisablePVM4(void)\r
+{\r
+  CLEAR_BIT(PWR->CR2, PWR_PVM_4);\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+  * @brief Configure the Peripheral Voltage Monitoring (PVM).\r
+  * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the\r
+  *        PVM configuration information.\r
+  * @note The API configures a single PVM according to the information contained\r
+  *       in the input structure. To configure several PVMs, the API must be singly\r
+  *       called for each PVM used.\r
+  * @note Refer to the electrical characteristics of your device datasheet for\r
+  *         more details about the voltage thresholds corresponding to each\r
+  *         detection level and to each monitored supply.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));\r
+  assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));\r
+\r
+\r
+  /* Configure EXTI 35 to 38 interrupts if so required:\r
+     scan thru PVMType to detect which PVMx is set and\r
+     configure the corresponding EXTI line accordingly. */\r
+  switch (sConfigPVM->PVMType)\r
+  {\r
+#if defined(PWR_CR2_PVME1)\r
+    case PWR_PVM_1:\r
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+      __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();\r
+      __HAL_PWR_PVM1_EXTI_DISABLE_IT();\r
+      __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();\r
+      __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();\r
+\r
+      /* Configure interrupt mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+      {\r
+        __HAL_PWR_PVM1_EXTI_ENABLE_IT();\r
+      }\r
+\r
+      /* Configure event mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+      {\r
+        __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();\r
+      }\r
+\r
+      /* Configure the edge */\r
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();\r
+      }\r
+\r
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();\r
+      }\r
+      break;\r
+#endif /* PWR_CR2_PVME1 */\r
+\r
+#if defined(PWR_CR2_PVME2)\r
+    case PWR_PVM_2:\r
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+      __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();\r
+      __HAL_PWR_PVM2_EXTI_DISABLE_IT();\r
+      __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();\r
+      __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();\r
+\r
+      /* Configure interrupt mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+      {\r
+        __HAL_PWR_PVM2_EXTI_ENABLE_IT();\r
+      }\r
+\r
+      /* Configure event mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+      {\r
+        __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();\r
+      }\r
+\r
+      /* Configure the edge */\r
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();\r
+      }\r
+\r
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();\r
+      }\r
+      break;\r
+#endif /* PWR_CR2_PVME2 */\r
+\r
+    case PWR_PVM_3:\r
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+      __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();\r
+      __HAL_PWR_PVM3_EXTI_DISABLE_IT();\r
+      __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();\r
+      __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();\r
+\r
+      /* Configure interrupt mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+      {\r
+        __HAL_PWR_PVM3_EXTI_ENABLE_IT();\r
+      }\r
+\r
+      /* Configure event mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+      {\r
+        __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();\r
+      }\r
+\r
+      /* Configure the edge */\r
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();\r
+      }\r
+\r
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();\r
+      }\r
+      break;\r
+\r
+    case PWR_PVM_4:\r
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+      __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();\r
+      __HAL_PWR_PVM4_EXTI_DISABLE_IT();\r
+      __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();\r
+      __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();\r
+\r
+      /* Configure interrupt mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+      {\r
+        __HAL_PWR_PVM4_EXTI_ENABLE_IT();\r
+      }\r
+\r
+      /* Configure event mode */\r
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+      {\r
+        __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();\r
+      }\r
+\r
+      /* Configure the edge */\r
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();\r
+      }\r
+\r
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+      {\r
+        __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();\r
+      }\r
+      break;\r
+\r
+    default:\r
+      status = HAL_ERROR;\r
+      break;\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+\r
+\r
+/**\r
+  * @brief Enter Low-power Run mode\r
+  * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.\r
+  * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the\r
+  *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.\r
+  *        Additionally, the clock frequency must be reduced below 2 MHz.\r
+  *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must\r
+  *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnableLowPowerRunMode(void)\r
+{\r
+  /* Set Regulator parameter */\r
+  SET_BIT(PWR->CR1, PWR_CR1_LPR);\r
+}\r
+\r
+\r
+/**\r
+  * @brief Exit Low-power Run mode.\r
+  * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that\r
+  *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode\r
+  *        returns HAL_TIMEOUT status). The system clock frequency can then be\r
+  *        increased above 2 MHz.\r
+  * @retval HAL Status\r
+  */\r
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)\r
+{\r
+  uint32_t wait_loop_index;\r
+\r
+  /* Clear LPR bit */\r
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);\r
+\r
+  /* Wait until REGLPF is reset */\r
+  wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;\r
+  while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))\r
+  {\r
+    wait_loop_index--;\r
+  }\r
+  if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))\r
+  {\r
+    return HAL_TIMEOUT;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enter Stop 0 mode.\r
+  * @note  In Stop 0 mode, main and low voltage regulators are ON.\r
+  * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.\r
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
+  *        only to the peripheral requesting it.\r
+  *        SRAM1, SRAM2 and register contents are preserved.\r
+  *        The BOR is available.\r
+  * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,\r
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+  * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption\r
+  *         is higher although the startup time is reduced.\r
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction\r
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+  /* Stop 0 mode with Main Regulator */\r
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);\r
+\r
+  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+  /* Select Stop mode entry --------------------------------------------------*/\r
+  if(STOPEntry == PWR_STOPENTRY_WFI)\r
+  {\r
+    /* Request Wait For Interrupt */\r
+    __WFI();\r
+  }\r
+  else\r
+  {\r
+    /* Request Wait For Event */\r
+    __SEV();\r
+    __WFE();\r
+    __WFE();\r
+  }\r
+\r
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enter Stop 1 mode.\r
+  * @note  In Stop 1 mode, only low power voltage regulator is ON.\r
+  * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.\r
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
+  *        only to the peripheral requesting it.\r
+  *        SRAM1, SRAM2 and register contents are preserved.\r
+  *        The BOR is available.\r
+  * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,\r
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+  * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.\r
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction\r
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+  /* Stop 1 mode with Low-Power Regulator */\r
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);\r
+\r
+  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+  /* Select Stop mode entry --------------------------------------------------*/\r
+  if(STOPEntry == PWR_STOPENTRY_WFI)\r
+  {\r
+    /* Request Wait For Interrupt */\r
+    __WFI();\r
+  }\r
+  else\r
+  {\r
+    /* Request Wait For Event */\r
+    __SEV();\r
+    __WFE();\r
+    __WFE();\r
+  }\r
+\r
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+}\r
+\r
+\r
+/**\r
+  * @brief Enter Stop 2 mode.\r
+  * @note  In Stop 2 mode, only low power voltage regulator is ON.\r
+  * @note  In Stop 2 mode, all I/O pins keep the same state as in Run mode.\r
+  * @note  All clocks in the VCORE domain are stopped, the PLL, the MSI,\r
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability\r
+  *        (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after\r
+  *        receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only\r
+  *        to the peripheral requesting it.\r
+  *        SRAM1, SRAM2 and register contents are preserved.\r
+  *        The BOR is available.\r
+  *        The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.\r
+  *        Otherwise, Stop 1 mode is entered.\r
+  * @note  When exiting Stop 2 mode by issuing an interrupt or a wakeup event,\r
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction\r
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)\r
+{\r
+  /* Check the parameter */\r
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+  /* Set Stop mode 2 */\r
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);\r
+\r
+  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+  /* Select Stop mode entry --------------------------------------------------*/\r
+  if(STOPEntry == PWR_STOPENTRY_WFI)\r
+  {\r
+    /* Request Wait For Interrupt */\r
+    __WFI();\r
+  }\r
+  else\r
+  {\r
+    /* Request Wait For Event */\r
+    __SEV();\r
+    __WFE();\r
+    __WFE();\r
+  }\r
+\r
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+}\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+  * @brief Enter Shutdown mode.\r
+  * @note  In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched\r
+  *        off. The voltage regulator is disabled and Vcore domain is powered off.\r
+  *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.\r
+  *        The BOR is not available.\r
+  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_EnterSHUTDOWNMode(void)\r
+{\r
+\r
+  /* Set Shutdown mode */\r
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);\r
+\r
+  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+  __force_stores();\r
+#endif\r
+  /* Request Wait For Interrupt */\r
+  __WFI();\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+  * @brief This function handles the PWR PVD/PVMx interrupt request.\r
+  * @note This API should be called under the PVD_PVM_IRQHandler().\r
+  * @retval None\r
+  */\r
+void HAL_PWREx_PVD_PVM_IRQHandler(void)\r
+{\r
+  /* Check PWR exti flag */\r
+  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U)\r
+  {\r
+    /* PWR PVD interrupt user callback */\r
+    HAL_PWR_PVDCallback();\r
+\r
+    /* Clear PVD exti pending bit */\r
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+  }\r
+  /* Next, successively check PVMx exti flags */\r
+#if defined(PWR_CR2_PVME1)\r
+  if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U)\r
+  {\r
+    /* PWR PVM1 interrupt user callback */\r
+    HAL_PWREx_PVM1Callback();\r
+\r
+    /* Clear PVM1 exti pending bit */\r
+    __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();\r
+  }\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+  if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U)\r
+  {\r
+    /* PWR PVM2 interrupt user callback */\r
+    HAL_PWREx_PVM2Callback();\r
+\r
+    /* Clear PVM2 exti pending bit */\r
+    __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();\r
+  }\r
+#endif /* PWR_CR2_PVME2 */\r
+  if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U)\r
+  {\r
+    /* PWR PVM3 interrupt user callback */\r
+    HAL_PWREx_PVM3Callback();\r
+\r
+    /* Clear PVM3 exti pending bit */\r
+    __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();\r
+  }\r
+  if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U)\r
+  {\r
+    /* PWR PVM4 interrupt user callback */\r
+    HAL_PWREx_PVM4Callback();\r
+\r
+    /* Clear PVM4 exti pending bit */\r
+    __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();\r
+  }\r
+}\r
+\r
+\r
+#if defined(PWR_CR2_PVME1)\r
+/**\r
+  * @brief PWR PVM1 interrupt callback\r
+  * @retval None\r
+  */\r
+__weak void HAL_PWREx_PVM1Callback(void)\r
+{\r
+  /* NOTE : This function should not be modified; when the callback is needed,\r
+            HAL_PWREx_PVM1Callback() API can be implemented in the user file\r
+   */\r
+}\r
+#endif /* PWR_CR2_PVME1 */\r
+\r
+#if defined(PWR_CR2_PVME2)\r
+/**\r
+  * @brief PWR PVM2 interrupt callback\r
+  * @retval None\r
+  */\r
+__weak void HAL_PWREx_PVM2Callback(void)\r
+{\r
+  /* NOTE : This function should not be modified; when the callback is needed,\r
+            HAL_PWREx_PVM2Callback() API can be implemented in the user file\r
+   */\r
+}\r
+#endif /* PWR_CR2_PVME2 */\r
+\r
+/**\r
+  * @brief PWR PVM3 interrupt callback\r
+  * @retval None\r
+  */\r
+__weak void HAL_PWREx_PVM3Callback(void)\r
+{\r
+  /* NOTE : This function should not be modified; when the callback is needed,\r
+            HAL_PWREx_PVM3Callback() API can be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief PWR PVM4 interrupt callback\r
+  * @retval None\r
+  */\r
+__weak void HAL_PWREx_PVM4Callback(void)\r
+{\r
+  /* NOTE : This function should not be modified; when the callback is needed,\r
+            HAL_PWREx_PVM4Callback() API can be implemented in the user file\r
+   */\r
+}\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
new file mode 100644 (file)
index 0000000..536d163
--- /dev/null
@@ -0,0 +1,2814 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_qspi.c\r
+  * @author  MCD Application Team\r
+  * @brief   QSPI HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the QuadSPI interface (QSPI).\r
+  *           + Initialization and de-initialization functions\r
+  *           + Indirect functional mode management\r
+  *           + Memory-mapped functional mode management\r
+  *           + Auto-polling functional mode management\r
+  *           + Interrupts and flags management\r
+  *           + DMA channel configuration for indirect functional mode\r
+  *           + Errors management and abort functionality\r
+  *\r
+  *\r
+  @verbatim\r
+ ===============================================================================\r
+                        ##### How to use this driver #####\r
+ ===============================================================================\r
+  [..]\r
+    *** Initialization ***\r
+    ======================\r
+    [..]\r
+      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :\r
+        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().\r
+        (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().\r
+        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
+        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().\r
+        (++) If interrupt mode is used, enable and configure QuadSPI global\r
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel\r
+            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),\r
+            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure\r
+            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+      (#) Configure the flash size, the clock prescaler, the fifo threshold, the\r
+          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.\r
+\r
+    *** Indirect functional mode ***\r
+    ================================\r
+    [..]\r
+      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()\r
+          functions :\r
+         (++) Instruction phase : the mode used and if present the instruction opcode.\r
+         (++) Address phase : the mode used and if present the size and the address value.\r
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate\r
+             bytes values.\r
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+         (++) Data phase : the mode used and if present the number of bytes.\r
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay\r
+             if activated.\r
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+      (#) If no data is required for the command, it is sent directly to the memory :\r
+         (++) In polling mode, the output of the function is done when the transfer is complete.\r
+         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.\r
+      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or\r
+          HAL_QSPI_Transmit_IT() after the command configuration :\r
+         (++) In polling mode, the output of the function is done when the transfer is complete.\r
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold\r
+             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
+         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and\r
+             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
+      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or\r
+          HAL_QSPI_Receive_IT() after the command configuration :\r
+         (++) In polling mode, the output of the function is done when the transfer is complete.\r
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold\r
+             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
+         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and\r
+             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
+\r
+    *** Auto-polling functional mode ***\r
+    ====================================\r
+    [..]\r
+      (#) Configure the command sequence and the auto-polling functional mode using the\r
+          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :\r
+         (++) Instruction phase : the mode used and if present the instruction opcode.\r
+         (++) Address phase : the mode used and if present the size and the address value.\r
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate\r
+             bytes values.\r
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+         (++) Data phase : the mode used.\r
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay\r
+             if activated.\r
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),\r
+             the polling interval and the automatic stop activation.\r
+      (#) After the configuration :\r
+         (++) In polling mode, the output of the function is done when the status match is reached. The\r
+             automatic stop is activated to avoid an infinite loop.\r
+         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.\r
+\r
+    *** Memory-mapped functional mode ***\r
+    =====================================\r
+    [..]\r
+      (#) Configure the command sequence and the memory-mapped functional mode using the\r
+          HAL_QSPI_MemoryMapped() functions :\r
+         (++) Instruction phase : the mode used and if present the instruction opcode.\r
+         (++) Address phase : the mode used and the size.\r
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate\r
+             bytes values.\r
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+         (++) Data phase : the mode used.\r
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay\r
+             if activated.\r
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+         (++) The timeout activation and the timeout period.\r
+      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on\r
+          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.\r
+\r
+    *** Errors management and abort functionality ***\r
+    =================================================\r
+    [..]\r
+      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.\r
+      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and\r
+          flushes the fifo :\r
+         (++) In polling mode, the output of the function is done when the transfer\r
+              complete bit is set and the busy bit cleared.\r
+         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when\r
+              the transfer complete bit is set.\r
+\r
+    *** Control functions ***\r
+    =========================\r
+    [..]\r
+      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.\r
+      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.\r
+      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.\r
+      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold\r
+      (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.\r
+\r
+    *** Callback registration ***\r
+    =============================================\r
+    [..]\r
+      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1\r
+      allows the user to configure dynamically the driver callbacks.\r
+\r
+      Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,\r
+      it allows to register following callbacks:\r
+        (+) ErrorCallback : callback when error occurs.\r
+        (+) AbortCpltCallback : callback when abort is completed.\r
+        (+) FifoThresholdCallback : callback when the fifo threshold is reached.\r
+        (+) CmdCpltCallback : callback when a command without data is completed.\r
+        (+) RxCpltCallback : callback when a reception transfer is completed.\r
+        (+) TxCpltCallback : callback when a transmission transfer is completed.\r
+        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.\r
+        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.\r
+        (+) StatusMatchCallback : callback when a status match occurs.\r
+        (+) TimeOutCallback : callback when the timeout perioed expires.\r
+        (+) MspInitCallback    : QSPI MspInit.\r
+        (+) MspDeInitCallback  : QSPI MspDeInit.\r
+      This function takes as parameters the HAL peripheral handle, the Callback ID\r
+      and a pointer to the user callback function.\r
+\r
+      Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default\r
+      weak (surcharged) function. It allows to reset following callbacks:\r
+        (+) ErrorCallback : callback when error occurs.\r
+        (+) AbortCpltCallback : callback when abort is completed.\r
+        (+) FifoThresholdCallback : callback when the fifo threshold is reached.\r
+        (+) CmdCpltCallback : callback when a command without data is completed.\r
+        (+) RxCpltCallback : callback when a reception transfer is completed.\r
+        (+) TxCpltCallback : callback when a transmission transfer is completed.\r
+        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.\r
+        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.\r
+        (+) StatusMatchCallback : callback when a status match occurs.\r
+        (+) TimeOutCallback : callback when the timeout perioed expires.\r
+        (+) MspInitCallback    : QSPI MspInit.\r
+        (+) MspDeInitCallback  : QSPI MspDeInit.\r
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.\r
+\r
+      By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET\r
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.\r
+      Exception done for MspInit and MspDeInit callbacks that are respectively\r
+      reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init\r
+      and @ref  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).\r
+      If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit\r
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)\r
+\r
+      Callbacks can be registered/unregistered in READY state only.\r
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered\r
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used\r
+      during the Init/DeInit.\r
+      In that case first register the MspInit/MspDeInit user callbacks\r
+      using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit\r
+      or @ref HAL_QSPI_Init function.\r
+\r
+      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or\r
+      not defined, the callback registering feature is not available\r
+      and weak (surcharged) callbacks are used.\r
+\r
+    *** Workarounds linked to Silicon Limitation ***\r
+    ====================================================\r
+    [..]\r
+      (#) Workarounds Implemented inside HAL Driver\r
+         (++) Extra data written in the FIFO at the end of a read transfer\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                       opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+#if defined(QUADSPI)\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup QSPI QSPI\r
+  * @brief QSPI HAL module driver\r
+  * @{\r
+  */\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup QSPI_Private_Constants QSPI Private Constants\r
+  * @{\r
+  */\r
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U                     /*!<Indirect write mode*/\r
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/\r
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/\r
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup QSPI_Private_Macros QSPI Private Macros\r
+  * @{\r
+  */\r
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \\r
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \\r
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \\r
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);\r
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions\r
+  *  @brief    Initialization and Configuration functions\r
+  *\r
+@verbatim\r
+===============================================================================\r
+            ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to :\r
+      (+) Initialize the QuadSPI.\r
+      (+) De-initialize the QuadSPI.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Initialize the QSPI mode according to the specified parameters\r
+  *        in the QSPI_InitTypeDef and initialize the associated handle.\r
+  * @param hqspi : QSPI handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Check the QSPI handle allocation */\r
+  if(hqspi == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));\r
+  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));\r
+  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));\r
+  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));\r
+  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));\r
+  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));\r
+  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));\r
+#if defined(QUADSPI_CR_DFM)\r
+  assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));\r
+\r
+  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )\r
+  {\r
+    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r
+  }\r
+#endif\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    hqspi->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+    /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */\r
+    hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;\r
+    hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;\r
+    hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;\r
+    hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;\r
+    hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;\r
+    hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;\r
+    hqspi->RxHalfCpltCallback    = HAL_QSPI_RxHalfCpltCallback;\r
+    hqspi->TxHalfCpltCallback    = HAL_QSPI_TxHalfCpltCallback;\r
+    hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;\r
+    hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;\r
+\r
+    if(hqspi->MspInitCallback == NULL)\r
+    {\r
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;\r
+    }\r
+\r
+    /* Init the low level hardware */\r
+    hqspi->MspInitCallback(hqspi);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK */\r
+    HAL_QSPI_MspInit(hqspi);\r
+#endif\r
+\r
+    /* Configure the default timeout for the QSPI memory access */\r
+    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);\r
+  }\r
+\r
+  /* Configure QSPI FIFO Threshold */\r
+  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,\r
+             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));\r
+\r
+  /* Wait till BUSY flag reset */\r
+  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+    /* Configure QSPI Clock Prescaler and Sample Shift */\r
+#if defined(QUADSPI_CR_DFM)\r
+    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),\r
+               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |\r
+                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));\r
+#else\r
+    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),\r
+               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |\r
+                hqspi->Init.SampleShifting));\r
+#endif\r
+\r
+    /* Configure QSPI Flash Size, CS High Time and Clock Mode */\r
+    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),\r
+               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |\r
+                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));\r
+\r
+    /* Enable the QSPI peripheral */\r
+    __HAL_QSPI_ENABLE(hqspi);\r
+\r
+    /* Set QSPI error code to none */\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    /* Initialize the QSPI state */\r
+    hqspi->State = HAL_QSPI_STATE_READY;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief De-Initialize the QSPI peripheral.\r
+  * @param hqspi : QSPI handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Check the QSPI handle allocation */\r
+  if(hqspi == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  /* Disable the QSPI Peripheral Clock */\r
+  __HAL_QSPI_DISABLE(hqspi);\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+  if(hqspi->MspDeInitCallback == NULL)\r
+  {\r
+    hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;\r
+  }\r
+\r
+  /* DeInit the low level hardware */\r
+  hqspi->MspDeInitCallback(hqspi);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+  HAL_QSPI_MspDeInit(hqspi);\r
+#endif\r
+\r
+  /* Set QSPI error code to none */\r
+  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+  /* Initialize the QSPI state */\r
+  hqspi->State = HAL_QSPI_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Initialize the QSPI MSP.\r
+  * @param hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_QSPI_MspInit can be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief DeInitialize the QSPI MSP.\r
+  * @param hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_QSPI_MspDeInit can be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions\r
+  *  @brief QSPI Transmit/Receive functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### IO operation functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to :\r
+      (+) Handle the interrupts.\r
+      (+) Handle the command sequence.\r
+      (+) Transmit data in blocking, interrupt or DMA mode.\r
+      (+) Receive data in blocking, interrupt or DMA mode.\r
+      (+) Manage the auto-polling functional mode.\r
+      (+) Manage the memory-mapped functional mode.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Handle QSPI interrupt request.\r
+  * @param hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  __IO uint32_t *data_reg;\r
+  uint32_t flag = READ_REG(hqspi->Instance->SR);\r
+  uint32_t itsource = READ_REG(hqspi->Instance->CR);\r
+\r
+  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/\r
+  if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))\r
+  {\r
+    data_reg = &hqspi->Instance->DR;\r
+\r
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
+    {\r
+      /* Transmission process */\r
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)\r
+      {\r
+        if (hqspi->TxXferCount > 0U)\r
+        {\r
+          /* Fill the FIFO until the threshold is reached */\r
+          *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;\r
+          hqspi->pTxBuffPtr++;\r
+          hqspi->TxXferCount--;\r
+        }\r
+        else\r
+        {\r
+          /* No more data available for the transfer */\r
+          /* Disable the QSPI FIFO Threshold Interrupt */\r
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r
+          break;\r
+        }\r
+      }\r
+    }\r
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
+    {\r
+      /* Receiving Process */\r
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)\r
+      {\r
+        if (hqspi->RxXferCount > 0U)\r
+        {\r
+          /* Read the FIFO until the threshold is reached */\r
+          *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);\r
+          hqspi->pRxBuffPtr++;\r
+          hqspi->RxXferCount--;\r
+        }\r
+        else\r
+        {\r
+          /* All data have been received for the transfer */\r
+          /* Disable the QSPI FIFO Threshold Interrupt */\r
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r
+          break;\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Nothing to do */\r
+    }\r
+\r
+    /* FIFO Threshold callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+    hqspi->FifoThresholdCallback(hqspi);\r
+#else\r
+    HAL_QSPI_FifoThresholdCallback(hqspi);\r
+#endif\r
+  }\r
+\r
+  /* QSPI Transfer Complete interrupt occurred -------------------------------*/\r
+  else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))\r
+  {\r
+    /* Clear interrupt */\r
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);\r
+\r
+    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */\r
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
+\r
+    /* Transfer complete callback */\r
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
+    {\r
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
+      {\r
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+\r
+        /* Disable the DMA channel */\r
+        __HAL_DMA_DISABLE(hqspi->hdma);\r
+      }\r
+\r
+#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
+      /* Clear Busy bit */\r
+      HAL_QSPI_Abort_IT(hqspi);\r
+#endif\r
+\r
+      /* Change state of QSPI */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+      /* TX Complete callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+      hqspi->TxCpltCallback(hqspi);\r
+#else\r
+      HAL_QSPI_TxCpltCallback(hqspi);\r
+#endif\r
+    }\r
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
+    {\r
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
+      {\r
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+\r
+        /* Disable the DMA channel */\r
+        __HAL_DMA_DISABLE(hqspi->hdma);\r
+      }\r
+      else\r
+      {\r
+        data_reg = &hqspi->Instance->DR;\r
+        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)\r
+        {\r
+          if (hqspi->RxXferCount > 0U)\r
+          {\r
+            /* Read the last data received in the FIFO until it is empty */\r
+            *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);\r
+            hqspi->pRxBuffPtr++;\r
+            hqspi->RxXferCount--;\r
+          }\r
+          else\r
+          {\r
+            /* All data have been received for the transfer */\r
+            break;\r
+          }\r
+        }\r
+      }\r
+\r
+#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
+      /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
+      HAL_QSPI_Abort_IT(hqspi);\r
+#endif\r
+\r
+      /* Change state of QSPI */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+      /* RX Complete callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+      hqspi->RxCpltCallback(hqspi);\r
+#else\r
+      HAL_QSPI_RxCpltCallback(hqspi);\r
+#endif\r
+    }\r
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY)\r
+    {\r
+      /* Change state of QSPI */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+      /* Command Complete callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+      hqspi->CmdCpltCallback(hqspi);\r
+#else\r
+      HAL_QSPI_CmdCpltCallback(hqspi);\r
+#endif\r
+    }\r
+    else if(hqspi->State == HAL_QSPI_STATE_ABORT)\r
+    {\r
+      /* Reset functional mode configuration to indirect write mode by default */\r
+      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);\r
+\r
+      /* Change state of QSPI */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)\r
+      {\r
+        /* Abort called by the user */\r
+\r
+        /* Abort Complete callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+        hqspi->AbortCpltCallback(hqspi);\r
+#else\r
+        HAL_QSPI_AbortCpltCallback(hqspi);\r
+#endif\r
+      }\r
+      else\r
+      {\r
+        /* Abort due to an error (eg :  DMA error) */\r
+\r
+        /* Error callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+        hqspi->ErrorCallback(hqspi);\r
+#else\r
+        HAL_QSPI_ErrorCallback(hqspi);\r
+#endif\r
+      }\r
+    }\r
+    else\r
+    {\r
+     /* Nothing to do */\r
+    }\r
+  }\r
+\r
+  /* QSPI Status Match interrupt occurred ------------------------------------*/\r
+  else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))\r
+  {\r
+    /* Clear interrupt */\r
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);\r
+\r
+    /* Check if the automatic poll mode stop is activated */\r
+    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)\r
+    {\r
+      /* Disable the QSPI Transfer Error and Status Match Interrupts */\r
+      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r
+\r
+      /* Change state of QSPI */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+    }\r
+\r
+    /* Status match callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+    hqspi->StatusMatchCallback(hqspi);\r
+#else\r
+    HAL_QSPI_StatusMatchCallback(hqspi);\r
+#endif\r
+  }\r
+\r
+  /* QSPI Transfer Error interrupt occurred ----------------------------------*/\r
+  else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))\r
+  {\r
+    /* Clear interrupt */\r
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);\r
+\r
+    /* Disable all the QSPI Interrupts */\r
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
+\r
+    /* Set error code */\r
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;\r
+\r
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
+    {\r
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+\r
+      /* Disable the DMA channel */\r
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r
+      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)\r
+      {\r
+        /* Set error code to DMA */\r
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
+\r
+        /* Change state of QSPI */\r
+        hqspi->State = HAL_QSPI_STATE_READY;\r
+        \r
+        /* Error callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+        hqspi->ErrorCallback(hqspi);\r
+#else\r
+        HAL_QSPI_ErrorCallback(hqspi);\r
+#endif\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Change state of QSPI */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+      /* Error callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+      hqspi->ErrorCallback(hqspi);\r
+#else\r
+      HAL_QSPI_ErrorCallback(hqspi);\r
+#endif\r
+    }\r
+  }\r
+\r
+  /* QSPI Timeout interrupt occurred -----------------------------------------*/\r
+  else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))\r
+  {\r
+    /* Clear interrupt */\r
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);\r
+\r
+    /* Timeout callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+    hqspi->TimeOutCallback(hqspi);\r
+#else\r
+    HAL_QSPI_TimeOutCallback(hqspi);\r
+#endif\r
+  }\r
+\r
+   else\r
+  {\r
+   /* Nothing to do */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Set the command configuration.\r
+  * @param hqspi : QSPI handle\r
+  * @param cmd : structure that contains the command configuration information\r
+  * @param Timeout : Timeout duration\r
+  * @note   This function is used only in Indirect Read or Write Modes\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+  {\r
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    /* Update QSPI state */\r
+    hqspi->State = HAL_QSPI_STATE_BUSY;\r
+\r
+    /* Wait till BUSY flag reset */\r
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      /* Call the configuration function */\r
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+\r
+      if (cmd->DataMode == QSPI_DATA_NONE)\r
+      {\r
+        /* When there is no data phase, the transfer start as soon as the configuration is done\r
+        so wait until TC flag is set to go back in idle state */\r
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
+\r
+        if (status == HAL_OK)\r
+        {\r
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+          /* Update QSPI state */\r
+          hqspi->State = HAL_QSPI_STATE_READY;\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Update QSPI state */\r
+        hqspi->State = HAL_QSPI_STATE_READY;\r
+      }\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief Set the command configuration in interrupt mode.\r
+  * @param hqspi : QSPI handle\r
+  * @param cmd : structure that contains the command configuration information\r
+  * @note   This function is used only in Indirect Read or Write Modes\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+  {\r
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    /* Update QSPI state */\r
+    hqspi->State = HAL_QSPI_STATE_BUSY;\r
+\r
+    /* Wait till BUSY flag reset */\r
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      if (cmd->DataMode == QSPI_DATA_NONE)\r
+      {\r
+        /* Clear interrupt */\r
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
+      }\r
+\r
+      /* Call the configuration function */\r
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+\r
+      if (cmd->DataMode == QSPI_DATA_NONE)\r
+      {\r
+        /* When there is no data phase, the transfer start as soon as the configuration is done\r
+        so activate TC and TE interrupts */\r
+        /* Process unlocked */\r
+        __HAL_UNLOCK(hqspi);\r
+\r
+        /* Enable the QSPI Transfer Error Interrupt */\r
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);\r
+      }\r
+      else\r
+      {\r
+        /* Update QSPI state */\r
+        hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+        /* Process unlocked */\r
+        __HAL_UNLOCK(hqspi);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+  }\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief Transmit an amount of data in blocking mode.\r
+  * @param hqspi : QSPI handle\r
+  * @param pData : pointer to data buffer\r
+  * @param Timeout : Timeout duration\r
+  * @note   This function is used only in Indirect Write Mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t tickstart = HAL_GetTick();\r
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    if(pData != NULL )\r
+    {\r
+      /* Update state */\r
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+\r
+      /* Configure counters and size of the handle */\r
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->pTxBuffPtr = pData;\r
+\r
+      /* Configure QSPI: CCR register with functional as indirect write */\r
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+\r
+      while(hqspi->TxXferCount > 0U)\r
+      {\r
+        /* Wait until FT flag is set to send data */\r
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);\r
+\r
+        if (status != HAL_OK)\r
+        {\r
+          break;\r
+        }\r
+\r
+        *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;\r
+        hqspi->pTxBuffPtr++;\r
+        hqspi->TxXferCount--;\r
+      }\r
+\r
+      if (status == HAL_OK)\r
+      {\r
+        /* Wait until TC flag is set to go back in idle state */\r
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
+\r
+        if (status == HAL_OK)\r
+        {\r
+          /* Clear Transfer Complete bit */\r
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
+          /* Clear Busy bit */\r
+          status = HAL_QSPI_Abort(hqspi);\r
+#endif\r
+        }\r
+      }\r
+\r
+      /* Update QSPI state */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+    }\r
+    else\r
+    {\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  return status;\r
+}\r
+\r
+\r
+/**\r
+  * @brief Receive an amount of data in blocking mode.\r
+  * @param hqspi : QSPI handle\r
+  * @param pData : pointer to data buffer\r
+  * @param Timeout : Timeout duration\r
+  * @note   This function is used only in Indirect Read Mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t tickstart = HAL_GetTick();\r
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    if(pData != NULL )\r
+    {\r
+      /* Update state */\r
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+\r
+      /* Configure counters and size of the handle */\r
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->pRxBuffPtr = pData;\r
+\r
+      /* Configure QSPI: CCR register with functional as indirect read */\r
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+      /* Start the transfer by re-writing the address in AR register */\r
+      WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+\r
+      while(hqspi->RxXferCount > 0U)\r
+      {\r
+        /* Wait until FT or TC flag is set to read received data */\r
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);\r
+\r
+        if  (status != HAL_OK)\r
+        {\r
+          break;\r
+        }\r
+\r
+        *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);\r
+        hqspi->pRxBuffPtr++;\r
+        hqspi->RxXferCount--;\r
+      }\r
+\r
+      if (status == HAL_OK)\r
+      {\r
+        /* Wait until TC flag is set to go back in idle state */\r
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
+\r
+        if  (status == HAL_OK)\r
+        {\r
+          /* Clear Transfer Complete bit */\r
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
+          /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
+          status = HAL_QSPI_Abort(hqspi);\r
+#endif\r
+        }\r
+      }\r
+\r
+      /* Update QSPI state */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+    }\r
+    else\r
+    {\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Send an amount of data in non-blocking mode with interrupt.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  pData : pointer to data buffer\r
+  * @note   This function is used only in Indirect Write Mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    if(pData != NULL )\r
+    {\r
+      /* Update state */\r
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+\r
+      /* Configure counters and size of the handle */\r
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->pTxBuffPtr = pData;\r
+\r
+      /* Clear interrupt */\r
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
+\r
+      /* Configure QSPI: CCR register with functional as indirect write */\r
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+\r
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
+    }\r
+    else\r
+    {\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+      status = HAL_ERROR;\r
+\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Receive an amount of data in non-blocking mode with interrupt.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  pData : pointer to data buffer\r
+  * @note   This function is used only in Indirect Read Mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    if(pData != NULL )\r
+    {\r
+      /* Update state */\r
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+\r
+      /* Configure counters and size of the handle */\r
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
+      hqspi->pRxBuffPtr = pData;\r
+\r
+      /* Clear interrupt */\r
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
+\r
+      /* Configure QSPI: CCR register with functional as indirect read */\r
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+      /* Start the transfer by re-writing the address in AR register */\r
+      WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+\r
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
+    }\r
+    else\r
+    {\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+      status = HAL_ERROR;\r
+\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Send an amount of data in non-blocking mode with DMA.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  pData : pointer to data buffer\r
+  * @note   This function is used only in Indirect Write Mode\r
+  * @note   If DMA peripheral access is configured as halfword, the number\r
+  *         of data and the fifo threshold should be aligned on halfword\r
+  * @note   If DMA peripheral access is configured as word, the number\r
+  *         of data and the fifo threshold should be aligned on word\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    /* Clear the error code */\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    if(pData != NULL )\r
+    {\r
+      /* Configure counters of the handle */\r
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r
+      {\r
+        hqspi->TxXferCount = data_size;\r
+      }\r
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r
+      {\r
+        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))\r
+        {\r
+          /* The number of data or the fifo threshold is not aligned on halfword\r
+          => no transfer possible with DMA peripheral access configured as halfword */\r
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+          status = HAL_ERROR;\r
+\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+        }\r
+        else\r
+        {\r
+          hqspi->TxXferCount = (data_size >> 1U);\r
+        }\r
+      }\r
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r
+      {\r
+        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))\r
+        {\r
+          /* The number of data or the fifo threshold is not aligned on word\r
+          => no transfer possible with DMA peripheral access configured as word */\r
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+          status = HAL_ERROR;\r
+\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+        }\r
+        else\r
+        {\r
+          hqspi->TxXferCount = (data_size >> 2U);\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Nothing to do */\r
+      }\r
+\r
+      if (status == HAL_OK)\r
+      {\r
+        /* Update state */\r
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+\r
+        /* Clear interrupt */\r
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r
+\r
+        /* Configure size and pointer of the handle */\r
+        hqspi->TxXferSize = hqspi->TxXferCount;\r
+        hqspi->pTxBuffPtr = pData;\r
+\r
+        /* Configure QSPI: CCR register with functional mode as indirect write */\r
+        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+\r
+        /* Set the QSPI DMA transfer complete callback */\r
+        hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;\r
+\r
+        /* Set the QSPI DMA Half transfer complete callback */\r
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;\r
+\r
+        /* Set the DMA error callback */\r
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
+\r
+        /* Clear the DMA abort callback */\r
+        hqspi->hdma->XferAbortCallback = NULL;\r
+\r
+        /* Configure the direction of the DMA */\r
+        hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;\r
+        MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);\r
+\r
+        /* Enable the QSPI transmit DMA Channel */\r
+        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)\r
+        {\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+          \r
+          /* Enable the QSPI transfer error Interrupt */\r
+          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r
+          \r
+          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
+          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+        }\r
+        else\r
+        {\r
+          status = HAL_ERROR;\r
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
+          hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+        }\r
+     }\r
+    }\r
+    else\r
+    {\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+      status = HAL_ERROR;\r
+\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Receive an amount of data in non-blocking mode with DMA.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  pData : pointer to data buffer.\r
+  * @note   This function is used only in Indirect Read Mode\r
+  * @note   If DMA peripheral access is configured as halfword, the number\r
+  *         of data and the fifo threshold should be aligned on halfword\r
+  * @note   If DMA peripheral access is configured as word, the number\r
+  *         of data and the fifo threshold should be aligned on word\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    /* Clear the error code */\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    if(pData != NULL )\r
+    {\r
+      /* Configure counters of the handle */\r
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r
+      {\r
+        hqspi->RxXferCount = data_size;\r
+      }\r
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r
+      {\r
+        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))\r
+        {\r
+          /* The number of data or the fifo threshold is not aligned on halfword\r
+             => no transfer possible with DMA peripheral access configured as halfword */\r
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+          status = HAL_ERROR;\r
+\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+        }\r
+        else\r
+        {\r
+          hqspi->RxXferCount = (data_size >> 1U);\r
+        }\r
+      }\r
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r
+      {\r
+        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))\r
+        {\r
+          /* The number of data or the fifo threshold is not aligned on word\r
+             => no transfer possible with DMA peripheral access configured as word */\r
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+          status = HAL_ERROR;\r
+\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+        }\r
+        else\r
+        {\r
+          hqspi->RxXferCount = (data_size >> 2U);\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Nothing to do */\r
+      }\r
+\r
+      if (status == HAL_OK)\r
+      {\r
+        /* Update state */\r
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+\r
+        /* Clear interrupt */\r
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r
+\r
+        /* Configure size and pointer of the handle */\r
+        hqspi->RxXferSize = hqspi->RxXferCount;\r
+        hqspi->pRxBuffPtr = pData;\r
+\r
+        /* Set the QSPI DMA transfer complete callback */\r
+        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;\r
+\r
+        /* Set the QSPI DMA Half transfer complete callback */\r
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;\r
+\r
+        /* Set the DMA error callback */\r
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
+\r
+        /* Clear the DMA abort callback */\r
+        hqspi->hdma->XferAbortCallback = NULL;\r
+\r
+        /* Configure the direction of the DMA */\r
+        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;\r
+        MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);\r
+\r
+        /* Enable the DMA Channel */\r
+        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)\r
+        {\r
+          /* Configure QSPI: CCR register with functional as indirect read */\r
+          MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+          /* Start the transfer by re-writing the address in AR register */\r
+          WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+          \r
+          /* Enable the QSPI transfer error Interrupt */\r
+          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r
+          \r
+          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
+          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+        }\r
+        else\r
+        {\r
+          status = HAL_ERROR;\r
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
+          hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+          /* Process unlocked */\r
+          __HAL_UNLOCK(hqspi);\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
+      status = HAL_ERROR;\r
+\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  cmd : structure that contains the command configuration information.\r
+  * @param  cfg : structure that contains the polling configuration information.\r
+  * @param  Timeout : Timeout duration\r
+  * @note   This function is used only in Automatic Polling Mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+  {\r
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    /* Update state */\r
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
+\r
+    /* Wait till BUSY flag reset */\r
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      /* Configure QSPI: PSMAR register with the status match value */\r
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
+\r
+      /* Configure QSPI: PSMKR register with the status mask value */\r
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
+\r
+      /* Configure QSPI: PIR register with the interval value */\r
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
+\r
+      /* Configure QSPI: CR register with Match mode and Automatic stop enabled\r
+      (otherwise there will be an infinite loop in blocking mode) */\r
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),\r
+               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));\r
+\r
+      /* Call the configuration function */\r
+      cmd->NbData = cfg->StatusBytesSize;\r
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
+\r
+      /* Wait until SM flag is set to go back in idle state */\r
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);\r
+\r
+      if (status == HAL_OK)\r
+      {\r
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r
+\r
+        /* Update state */\r
+        hqspi->State = HAL_QSPI_STATE_READY;\r
+      }\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  cmd : structure that contains the command configuration information.\r
+  * @param  cfg : structure that contains the polling configuration information.\r
+  * @note   This function is used only in Automatic Polling Mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+  {\r
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
+  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    /* Update state */\r
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
+\r
+    /* Wait till BUSY flag reset */\r
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      /* Configure QSPI: PSMAR register with the status match value */\r
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
+\r
+      /* Configure QSPI: PSMKR register with the status mask value */\r
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
+\r
+      /* Configure QSPI: PIR register with the interval value */\r
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
+\r
+      /* Configure QSPI: CR register with Match mode and Automatic stop mode */\r
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),\r
+               (cfg->MatchMode | cfg->AutomaticStop));\r
+\r
+      /* Clear interrupt */\r
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);\r
+\r
+      /* Call the configuration function */\r
+      cmd->NbData = cfg->StatusBytesSize;\r
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
+\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+\r
+      /* Enable the QSPI Transfer Error and status match Interrupt */\r
+      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r
+\r
+    }\r
+    else\r
+    {\r
+      /* Process unlocked */\r
+      __HAL_UNLOCK(hqspi);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+  }\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the Memory Mapped mode.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  cmd : structure that contains the command configuration information.\r
+  * @param  cfg : structure that contains the memory mapped configuration information.\r
+  * @note   This function is used only in Memory mapped Mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)\r
+{\r
+  HAL_StatusTypeDef status;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+  {\r
+  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+  {\r
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+  }\r
+\r
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+    /* Update state */\r
+    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;\r
+\r
+    /* Wait till BUSY flag reset */\r
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      /* Configure QSPI: CR register with timeout counter enable */\r
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);\r
+\r
+    if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)\r
+      {\r
+        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));\r
+\r
+        /* Configure QSPI: LPTR register with the low-power timeout value */\r
+        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);\r
+\r
+        /* Clear interrupt */\r
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);\r
+\r
+        /* Enable the QSPI TimeOut Interrupt */\r
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);\r
+      }\r
+\r
+      /* Call the configuration function */\r
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Transfer Error callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_QSPI_ErrorCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Abort completed callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_QSPI_AbortCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Command completed callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_QSPI_CmdCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Rx Transfer completed callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_QSPI_RxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Tx Transfer completed callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_QSPI_TxCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Rx Half Transfer completed callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Tx Half Transfer completed callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  FIFO Threshold callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Status Match callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_QSPI_StatusMatchCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Timeout callback.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hqspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_QSPI_TimeOutCallback could be implemented in the user file\r
+   */\r
+}\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  Register a User QSPI Callback\r
+  *         To be used instead of the weak (surcharged) predefined callback\r
+  * @param hqspi : QSPI handle\r
+  * @param CallbackId : ID of the callback to be registered\r
+  *        This parameter can be one of the following values:\r
+  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID\r
+  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID\r
+  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID\r
+  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID\r
+  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID\r
+  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID\r
+  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID\r
+  * @param pCallback : pointer to the Callback function\r
+  * @retval status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if(pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    switch (CallbackId)\r
+    {\r
+    case  HAL_QSPI_ERROR_CB_ID :\r
+      hqspi->ErrorCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_ABORT_CB_ID :\r
+      hqspi->AbortCpltCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :\r
+      hqspi->FifoThresholdCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_CMD_CPLT_CB_ID :\r
+      hqspi->CmdCpltCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_RX_CPLT_CB_ID :\r
+      hqspi->RxCpltCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_TX_CPLT_CB_ID :\r
+      hqspi->TxCpltCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_RX_HALF_CPLT_CB_ID :\r
+      hqspi->RxHalfCpltCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_TX_HALF_CPLT_CB_ID :\r
+      hqspi->TxHalfCpltCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_STATUS_MATCH_CB_ID :\r
+      hqspi->StatusMatchCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_TIMEOUT_CB_ID :\r
+      hqspi->TimeOutCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_MSP_INIT_CB_ID :\r
+      hqspi->MspInitCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
+      hqspi->MspDeInitCallback = pCallback;\r
+      break;\r
+    default :\r
+      /* Update the error code */\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
+      /* update return status */\r
+      status =  HAL_ERROR;\r
+      break;\r
+    }\r
+  }\r
+  else if (hqspi->State == HAL_QSPI_STATE_RESET)\r
+  {\r
+    switch (CallbackId)\r
+    {\r
+    case HAL_QSPI_MSP_INIT_CB_ID :\r
+      hqspi->MspInitCallback = pCallback;\r
+      break;\r
+    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
+      hqspi->MspDeInitCallback = pCallback;\r
+      break;\r
+    default :\r
+      /* Update the error code */\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
+      /* update return status */\r
+      status =  HAL_ERROR;\r
+      break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
+    /* update return status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hqspi);\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister a User QSPI Callback\r
+  *         QSPI Callback is redirected to the weak (surcharged) predefined callback\r
+  * @param hqspi : QSPI handle\r
+  * @param CallbackId : ID of the callback to be unregistered\r
+  *        This parameter can be one of the following values:\r
+  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID\r
+  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID\r
+  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID\r
+  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID\r
+  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID\r
+  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID\r
+  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID\r
+  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID\r
+  * @retval status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    switch (CallbackId)\r
+    {\r
+    case  HAL_QSPI_ERROR_CB_ID :\r
+      hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;\r
+      break;\r
+    case HAL_QSPI_ABORT_CB_ID :\r
+      hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;\r
+      break;\r
+    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :\r
+      hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;\r
+      break;\r
+    case HAL_QSPI_CMD_CPLT_CB_ID :\r
+      hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;\r
+      break;\r
+    case HAL_QSPI_RX_CPLT_CB_ID :\r
+      hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;\r
+      break;\r
+    case HAL_QSPI_TX_CPLT_CB_ID :\r
+      hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;\r
+      break;\r
+    case HAL_QSPI_RX_HALF_CPLT_CB_ID :\r
+      hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;\r
+      break;\r
+    case HAL_QSPI_TX_HALF_CPLT_CB_ID :\r
+      hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;\r
+      break;\r
+    case HAL_QSPI_STATUS_MATCH_CB_ID :\r
+      hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;\r
+      break;\r
+    case HAL_QSPI_TIMEOUT_CB_ID :\r
+      hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;\r
+      break;\r
+    case HAL_QSPI_MSP_INIT_CB_ID :\r
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;\r
+      break;\r
+    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
+      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;\r
+      break;\r
+    default :\r
+      /* Update the error code */\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
+      /* update return status */\r
+      status =  HAL_ERROR;\r
+      break;\r
+    }\r
+  }\r
+  else if (hqspi->State == HAL_QSPI_STATE_RESET)\r
+  {\r
+    switch (CallbackId)\r
+    {\r
+    case HAL_QSPI_MSP_INIT_CB_ID :\r
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;\r
+      break;\r
+    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
+      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;\r
+      break;\r
+    default :\r
+      /* Update the error code */\r
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
+      /* update return status */\r
+      status =  HAL_ERROR;\r
+      break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
+    /* update return status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hqspi);\r
+  return status;\r
+}\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions\r
+  *  @brief   QSPI control and State functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+                  ##### Peripheral Control and State functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to :\r
+      (+) Check in run-time the state of the driver.\r
+      (+) Check the error code set during last operation.\r
+      (+) Abort any operation.\r
+\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Return the QSPI handle state.\r
+  * @param  hqspi : QSPI handle\r
+  * @retval HAL state\r
+  */\r
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  /* Return QSPI handle state */\r
+  return hqspi->State;\r
+}\r
+\r
+/**\r
+* @brief  Return the QSPI error code.\r
+* @param  hqspi : QSPI handle\r
+* @retval QSPI Error Code\r
+*/\r
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  return hqspi->ErrorCode;\r
+}\r
+\r
+/**\r
+* @brief  Abort the current transmission.\r
+* @param  hqspi : QSPI handle\r
+* @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t tickstart = HAL_GetTick();\r
+\r
+  /* Check if the state is in one of the busy states */\r
+  if (((uint32_t)hqspi->State & 0x2U) != 0U)\r
+  {\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+\r
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
+    {\r
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+\r
+      /* Abort DMA channel */\r
+      status = HAL_DMA_Abort(hqspi->hdma);\r
+      if(status != HAL_OK)\r
+      {\r
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
+      }\r
+    }\r
+\r
+    /* Configure QSPI: CR register with Abort request */\r
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
+\r
+    /* Wait until TC flag is set to go back in idle state */\r
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+      /* Wait until BUSY flag is reset */\r
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
+    }\r
+\r
+    if (status == HAL_OK)\r
+    {\r
+      /* Reset functional mode configuration to indirect write mode by default */\r
+      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);\r
+\r
+      /* Update state */\r
+      hqspi->State = HAL_QSPI_STATE_READY;\r
+    }\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+* @brief  Abort the current transmission (non-blocking function)\r
+* @param  hqspi : QSPI handle\r
+* @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check if the state is in one of the busy states */\r
+  if (((uint32_t)hqspi->State & 0x2U) != 0U)\r
+  {\r
+    /* Process unlocked */\r
+    __HAL_UNLOCK(hqspi);\r
+\r
+    /* Update QSPI state */\r
+    hqspi->State = HAL_QSPI_STATE_ABORT;\r
+\r
+    /* Disable all interrupts */\r
+    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));\r
+\r
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
+    {\r
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+\r
+      /* Abort DMA channel */\r
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r
+      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)\r
+      {\r
+        /* Change state of QSPI */\r
+        hqspi->State = HAL_QSPI_STATE_READY;\r
+        \r
+        /* Abort Complete callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+        hqspi->AbortCpltCallback(hqspi);\r
+#else\r
+        HAL_QSPI_AbortCpltCallback(hqspi);\r
+#endif\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Clear interrupt */\r
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+      /* Enable the QSPI Transfer Complete Interrupt */\r
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+\r
+      /* Configure QSPI: CR register with Abort request */\r
+      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
+    }\r
+  }\r
+  return status;\r
+}\r
+\r
+/** @brief Set QSPI timeout.\r
+  * @param  hqspi : QSPI handle.\r
+  * @param  Timeout : Timeout for the QSPI memory access.\r
+  * @retval None\r
+  */\r
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)\r
+{\r
+  hqspi->Timeout = Timeout;\r
+}\r
+\r
+/** @brief Set QSPI Fifo threshold.\r
+  * @param  hqspi : QSPI handle.\r
+  * @param  Threshold : Threshold of the Fifo (value between 1 and 16).\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    /* Synchronize init structure with new FIFO threshold value */\r
+    hqspi->Init.FifoThreshold = Threshold;\r
+\r
+    /* Configure QSPI FIFO Threshold */\r
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,\r
+               ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/** @brief Get QSPI Fifo threshold.\r
+  * @param  hqspi : QSPI handle.\r
+  * @retval Fifo threshold (value between 1 and 16)\r
+  */\r
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)\r
+{\r
+  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);\r
+}\r
+\r
+#if defined(QUADSPI_CR_DFM)\r
+/** @brief  Set FlashID.\r
+  * @param  hqspi : QSPI handle.\r
+  * @param  FlashID : Index of the flash memory to be accessed.\r
+  *                   This parameter can be a value of @ref QSPI_Flash_Select.\r
+  * @note   The FlashID is ignored when dual flash mode is enabled.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Check the parameter */\r
+  assert_param(IS_QSPI_FLASH_ID(FlashID));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hqspi);\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_READY)\r
+  {\r
+    /* Synchronize init structure with new FlashID value */\r
+    hqspi->Init.FlashID = FlashID;\r
+\r
+    /* Configure QSPI FlashID */\r
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);\r
+  }\r
+  else\r
+  {\r
+    status = HAL_BUSY;\r
+  }\r
+\r
+  /* Process unlocked */\r
+  __HAL_UNLOCK(hqspi);\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup QSPI_Private_Functions QSPI Private Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  DMA QSPI receive process complete callback.\r
+  * @param  hdma : DMA handle\r
+  * @retval None\r
+  */\r
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
+  hqspi->RxXferCount = 0U;\r
+\r
+  /* Enable the QSPI transfer complete Interrupt */\r
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+}\r
+\r
+/**\r
+  * @brief  DMA QSPI transmit process complete callback.\r
+  * @param  hdma : DMA handle\r
+  * @retval None\r
+  */\r
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
+  hqspi->TxXferCount = 0U;\r
+\r
+  /* Enable the QSPI transfer complete Interrupt */\r
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+}\r
+\r
+/**\r
+  * @brief  DMA QSPI receive process half complete callback.\r
+  * @param  hdma : DMA handle\r
+  * @retval None\r
+  */\r
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+  hqspi->RxHalfCpltCallback(hqspi);\r
+#else\r
+  HAL_QSPI_RxHalfCpltCallback(hqspi);\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  DMA QSPI transmit process half complete callback.\r
+  * @param  hdma : DMA handle\r
+  * @retval None\r
+  */\r
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+  hqspi->TxHalfCpltCallback(hqspi);\r
+#else\r
+  HAL_QSPI_TxHalfCpltCallback(hqspi);\r
+#endif\r
+}\r
+\r
+/**\r
+  * @brief  DMA QSPI communication error callback.\r
+  * @param  hdma : DMA handle\r
+  * @retval None\r
+  */\r
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);\r
+\r
+  hqspi->RxXferCount = 0U;\r
+  hqspi->TxXferCount = 0U;\r
+  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;\r
+\r
+  /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+  CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+\r
+  /* Abort the QSPI */\r
+  (void)HAL_QSPI_Abort_IT(hqspi);\r
+\r
+}\r
+\r
+/**\r
+  * @brief  DMA QSPI abort complete callback.\r
+  * @param  hdma : DMA handle\r
+  * @retval None\r
+  */\r
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);\r
+\r
+  hqspi->RxXferCount = 0U;\r
+  hqspi->TxXferCount = 0U;\r
+\r
+  if(hqspi->State == HAL_QSPI_STATE_ABORT)\r
+  {\r
+    /* DMA Abort called by QSPI abort */\r
+    /* Clear interrupt */\r
+    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+    /* Enable the QSPI Transfer Complete Interrupt */\r
+    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
+\r
+    /* Configure QSPI: CR register with Abort request */\r
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
+  }\r
+  else\r
+  {\r
+    /* DMA Abort called due to a transfer error interrupt */\r
+    /* Change state of QSPI */\r
+    hqspi->State = HAL_QSPI_STATE_READY;\r
+\r
+    /* Error callback */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+    hqspi->ErrorCallback(hqspi);\r
+#else\r
+    HAL_QSPI_ErrorCallback(hqspi);\r
+#endif\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Wait for a flag state until timeout.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  Flag : Flag checked\r
+  * @param  State : Value of the flag expected\r
+  * @param  Tickstart : Tick start value\r
+  * @param  Timeout : Duration of the timeout\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,\r
+                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+  /* Wait until flag is in expected state */\r
+  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)\r
+  {\r
+    /* Check for the Timeout */\r
+    if (Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+      {\r
+        hqspi->State     = HAL_QSPI_STATE_ERROR;\r
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the communication registers.\r
+  * @param  hqspi : QSPI handle\r
+  * @param  cmd : structure that contains the command configuration information\r
+  * @param  FunctionalMode : functional mode to configured\r
+  *           This parameter can be one of the following values:\r
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode\r
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode\r
+  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode\r
+  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode\r
+  * @retval None\r
+  */\r
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)\r
+{\r
+  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));\r
+\r
+  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
+  {\r
+    /* Configure QSPI: DLR register with the number of data to read or write */\r
+    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));\r
+  }\r
+\r
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+  {\r
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+    {\r
+      /* Configure QSPI: ABR register with alternate bytes value */\r
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
+\r
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+      {\r
+        /*---- Command with instruction, address and alternate bytes ----*/\r
+        /* Configure QSPI: CCR register with all communications parameters */\r
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
+                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |\r
+                                         cmd->Instruction | FunctionalMode));\r
+\r
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+        {\r
+          /* Configure QSPI: AR register with address value */\r
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /*---- Command with instruction and alternate bytes ----*/\r
+        /* Configure QSPI: CCR register with all communications parameters */\r
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
+                                         cmd->AddressMode | cmd->InstructionMode |\r
+                                         cmd->Instruction | FunctionalMode));\r
+      }\r
+    }\r
+    else\r
+    {\r
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+      {\r
+        /*---- Command with instruction and address ----*/\r
+        /* Configure QSPI: CCR register with all communications parameters */\r
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r
+\r
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+        {\r
+          /* Configure QSPI: AR register with address value */\r
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /*---- Command with only instruction ----*/\r
+        /* Configure QSPI: CCR register with all communications parameters */\r
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                         cmd->AlternateByteMode | cmd->AddressMode |\r
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r
+      }\r
+    }\r
+  }\r
+  else\r
+  {\r
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+    {\r
+      /* Configure QSPI: ABR register with alternate bytes value */\r
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
+\r
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+      {\r
+        /*---- Command with address and alternate bytes ----*/\r
+        /* Configure QSPI: CCR register with all communications parameters */\r
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
+                                         cmd->AddressSize | cmd->AddressMode |\r
+                                         cmd->InstructionMode | FunctionalMode));\r
+\r
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+        {\r
+          /* Configure QSPI: AR register with address value */\r
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /*---- Command with only alternate bytes ----*/\r
+        /* Configure QSPI: CCR register with all communications parameters */\r
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r
+      }\r
+    }\r
+    else\r
+    {\r
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+      {\r
+        /*---- Command with only address ----*/\r
+        /* Configure QSPI: CCR register with all communications parameters */\r
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                         cmd->AlternateByteMode | cmd->AddressSize |\r
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r
+\r
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+        {\r
+          /* Configure QSPI: AR register with address value */\r
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /*---- Command with only data phase ----*/\r
+        if (cmd->DataMode != QSPI_DATA_NONE)\r
+        {\r
+          /* Configure QSPI: CCR register with all communications parameters */\r
+          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+                                           cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
+                                           cmd->AlternateByteMode | cmd->AddressMode |\r
+                                           cmd->InstructionMode | FunctionalMode));\r
+        }\r
+      }\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
new file mode 100644 (file)
index 0000000..9709d06
--- /dev/null
@@ -0,0 +1,1869 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_rcc.c\r
+  * @author  MCD Application Team\r
+  * @brief   RCC HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:\r
+  *           + Initialization and de-initialization functions\r
+  *           + Peripheral Control functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                      ##### RCC specific features #####\r
+  ==============================================================================\r
+    [..]\r
+      After reset the device is running from Multiple Speed Internal oscillator\r
+      (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache\r
+      and I-Cache are disabled, and all peripherals are off except internal\r
+      SRAM, Flash and JTAG.\r
+\r
+      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:\r
+          all peripherals mapped on these busses are running at MSI speed.\r
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+      (+) All GPIOs are in analog mode, except the JTAG pins which\r
+          are assigned to be used for debug purpose.\r
+\r
+    [..]\r
+      Once the device started from reset, the user application has to:\r
+      (+) Configure the clock source to be used to drive the System clock\r
+          (if the application needs higher frequency/performance)\r
+      (+) Configure the System clock frequency and Flash settings\r
+      (+) Configure the AHB and APB busses prescalers\r
+      (+) Enable the clock for the peripheral(s) to be used\r
+      (+) Configure the clock source(s) for peripherals which clocks are not\r
+          derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC RCC\r
+  * @brief RCC HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Constants RCC Private Constants\r
+ * @{\r
+ */\r
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT\r
+#define HSI_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
+#define MSI_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+#define LSI_TIMEOUT_VALUE          17U   /* 17 ms (16 ms starting time + 1) */\r
+#else\r
+#define LSI_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+#define HSI48_TIMEOUT_VALUE        2U    /* 2 ms (minimum Tick + 1) */\r
+#define PLL_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
+#define CLOCKSWITCH_TIMEOUT_VALUE  5000U /* 5 s    */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Macros RCC Private Macros\r
+  * @{\r
+  */\r
+#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()\r
+#define MCO1_GPIO_PORT        GPIOA\r
+#define MCO1_PIN              GPIO_PIN_8\r
+\r
+#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \\r
+            (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup RCC_Private_Functions RCC Private Functions\r
+  * @{\r
+  */\r
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+static uint32_t          RCC_GetSysClockFreqFromPLLSource(void);\r
+#endif\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  *  @brief    Initialization and Configuration functions\r
+  *\r
+  @verbatim\r
+ ===============================================================================\r
+           ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+    [..]\r
+      This section provides functions allowing to configure the internal and external oscillators\r
+      (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1\r
+       and APB2).\r
+\r
+    [..] Internal/external clock and PLL configuration\r
+         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through\r
+             the PLL as System clock source.\r
+\r
+         (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.\r
+             It can be used to generate the clock for the USB OTG FS (48 MHz).\r
+             The number of flash wait states is automatically adjusted when MSI range is updated with\r
+             HAL_RCC_OscConfig() and the MSI is used as System clock source.\r
+\r
+         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC\r
+             clock source.\r
+\r
+         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or\r
+             through the PLL as System clock source. Can be used also optionally as RTC clock source.\r
+\r
+         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.\r
+\r
+         (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:\r
+           (++) The first output is used to generate the high speed system clock (up to 80MHz).\r
+           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
+                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
+           (++) The third output is used to generate an accurate clock to achieve\r
+                high-quality audio performance on SAI interface.\r
+\r
+         (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:\r
+           (++) The first output is used to generate SAR ADC1 clock.\r
+           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
+                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
+           (++) The Third output is used to generate an accurate clock to achieve\r
+                high-quality audio performance on SAI interface.\r
+\r
+         (+) PLLSAI2 (clocked by HSI, HSE or MSI) providing up to two independent output clocks:\r
+           (++) The first output is used to generate SAR ADC2 clock.\r
+           (++) The second  output is used to generate an accurate clock to achieve\r
+                high-quality audio performance on SAI interface.\r
+\r
+         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs\r
+            (HSE used directly or through PLL as System clock source), the System clock\r
+             is automatically switched to HSI and an interrupt is generated if enabled.\r
+             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)\r
+             exception vector.\r
+\r
+         (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or\r
+             main PLL clock (through a configurable prescaler) on PA8 pin.\r
+\r
+    [..] System, AHB and APB busses clocks configuration\r
+         (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
+             HSE and main PLL.\r
+             The AHB clock (HCLK) is derived from System clock through configurable\r
+             prescaler and used to clock the CPU, memory and peripherals mapped\r
+             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\r
+             from AHB clock through configurable prescalers and used to clock\r
+             the peripherals mapped on these busses. You can use\r
+             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.\r
+\r
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+\r
+           (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or\r
+                from an external clock mapped on the SAI_CKIN pin.\r
+                You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.\r
+           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r
+                divided by 2 to 31.\r
+                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function\r
+                to configure this clock.\r
+           (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz\r
+                to work correctly, while the SDMMC1 and RNG peripherals require a frequency\r
+                equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1\r
+                through PLLQ divider. You have to enable the peripheral clock and use\r
+                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.\r
+           (+@) IWDG clock which is always the LSI clock.\r
+\r
+\r
+         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.\r
+             The clock source frequency should be adapted depending on the device voltage range\r
+             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.\r
+\r
+  @endverbatim\r
+\r
+           Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices\r
+           +--------------------------------------------------------+\r
+           | Latency         |     HCLK clock frequency (MHz)       |\r
+           |                 |--------------------------------------|\r
+           |                 |  voltage range 1  | voltage range 2  |\r
+           |                 |       1.2 V       |     1.0 V        |\r
+           |-----------------|-------------------|------------------|\r
+           |0WS(1 CPU cycles)|   0 < HCLK <= 20  |  0 < HCLK <= 8   |\r
+           |-----------------|-------------------|------------------|\r
+           |1WS(2 CPU cycles)|  20 < HCLK <= 40  |  8 < HCLK <= 16  |\r
+           |-----------------|-------------------|------------------|\r
+           |2WS(3 CPU cycles)|  40 < HCLK <= 60  | 16 < HCLK <= 26  |\r
+           |-----------------|-------------------|------------------|\r
+           |3WS(4 CPU cycles)|  60 < HCLK <= 80  | 16 < HCLK <= 26  |\r
+           |-----------------|-------------------|------------------|\r
+           |4WS(5 CPU cycles)|  80 < HCLK <= 100 | 16 < HCLK <= 26  |\r
+           |-----------------|-------------------|------------------|\r
+           |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26  |\r
+           +--------------------------------------------------------+\r
+\r
+           Table 2. HCLK clock frequency for other STM32L4 devices\r
+           +-------------------------------------------------------+\r
+           | Latency         |    HCLK clock frequency (MHz)       |\r
+           |                 |-------------------------------------|\r
+           |                 | voltage range 1  | voltage range 2  |\r
+           |                 |      1.2 V       |     1.0 V        |\r
+           |-----------------|------------------|------------------|\r
+           |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |\r
+           |-----------------|------------------|------------------|\r
+           |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |\r
+           |-----------------|------------------|------------------|\r
+           |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |\r
+           |-----------------|------------------|------------------|\r
+           |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |\r
+           |-----------------|------------------|------------------|\r
+           |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |\r
+           +-------------------------------------------------------+\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Reset the RCC clock configuration to the default reset state.\r
+  * @note   The default reset state of the clock configuration is given below:\r
+  *            - MSI ON and used as system clock source\r
+  *            - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF\r
+  *            - AHB, APB1 and APB2 prescalers set to 1.\r
+  *            - CSS, MCO1 OFF\r
+  *            - All interrupts disabled\r
+  *            - All interrupt and reset flags cleared\r
+  * @note   This function does not modify the configuration of the\r
+  *            - Peripheral clock sources\r
+  *            - LSI, LSE and RTC clocks (Backup domain)\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Reset to default System clock */\r
+  /* Set MSION bit */\r
+  SET_BIT(RCC->CR, RCC_CR_MSION);\r
+\r
+  /* Insure MSIRDY bit is set before writing default MSIRANGE value */\r
+  /* Get start tick */\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait till MSI is ready */\r
+  while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
+  {\r
+    if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+\r
+  /* Set MSIRANGE default value */\r
+  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);\r
+\r
+  /* Reset CFGR register (MSI is selected as system clock source) */\r
+  CLEAR_REG(RCC->CFGR);\r
+\r
+  /* Update the SystemCoreClock global variable for MSI as system clock source */\r
+  SystemCoreClock = MSI_VALUE;\r
+\r
+  /* Configure the source of time base considering new system clock settings  */\r
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Insure MSI selected as system clock source */\r
+  /* Get start tick */\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait till system clock source is ready */\r
+  while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)\r
+  {\r
+    if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+\r
+  /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);\r
+\r
+#elif defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);\r
+\r
+#else\r
+\r
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON);\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+  /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */\r
+  /* Get start tick */\r
+  tickstart = HAL_GetTick();\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)\r
+\r
+#elif defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)\r
+\r
+#else\r
+\r
+  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
+\r
+#endif\r
+  {\r
+    if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+\r
+  /* Reset PLLCFGR register */\r
+  CLEAR_REG(RCC->PLLCFGR);\r
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+  /* Reset PLLSAI1CFGR register */\r
+  CLEAR_REG(RCC->PLLSAI1CFGR);\r
+  SET_BIT(RCC->PLLSAI1CFGR,  RCC_PLLSAI1CFGR_PLLSAI1N_4 );\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+  /* Reset PLLSAI2CFGR register */\r
+  CLEAR_REG(RCC->PLLSAI2CFGR);\r
+  SET_BIT(RCC->PLLSAI2CFGR,  RCC_PLLSAI2CFGR_PLLSAI2N_4 );\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+  /* Reset HSEBYP bit */\r
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
+\r
+  /* Disable all interrupts */\r
+  CLEAR_REG(RCC->CIER);\r
+\r
+  /* Clear all interrupt flags */\r
+  WRITE_REG(RCC->CICR, 0xFFFFFFFFU);\r
+\r
+  /* Clear all reset flags */\r
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initialize the RCC Oscillators according to the specified parameters in the\r
+  *         RCC_OscInitTypeDef.\r
+  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that\r
+  *         contains the configuration information for the RCC Oscillators.\r
+  * @note   The PLL is not disabled when used as system clock.\r
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
+  *         supported by this macro. User should request a transition to LSE Off\r
+  *         first and then LSE On or LSE Bypass.\r
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+  *         supported by this macro. User should request a transition to HSE Off\r
+  *         first and then HSE On or HSE Bypass.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef status;\r
+  uint32_t sysclk_source, pll_config;\r
+\r
+  /* Check Null pointer */\r
+  if(RCC_OscInitStruct == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
+\r
+  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();\r
+  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();\r
+\r
+  /*----------------------------- MSI Configuration --------------------------*/\r
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));\r
+    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));\r
+    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));\r
+\r
+    /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */\r
+    if((sysclk_source == RCC_CFGR_SWS_MSI) ||\r
+       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))\r
+    {\r
+      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+       /* Otherwise, just the calibration and MSI range change are allowed */\r
+      else\r
+      {\r
+        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
+           must be correctly programmed according to the frequency of the CPU clock\r
+           (HCLK) and the supply voltage of the device. */\r
+        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())\r
+        {\r
+          /* First increase number of wait states update if necessary */\r
+          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
+          {\r
+            return HAL_ERROR;\r
+          }\r
+\r
+          /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
+          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
+          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
+          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
+        }\r
+        else\r
+        {\r
+          /* Else, keep current flash latency while decreasing applies */\r
+          /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
+          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
+          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
+          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
+\r
+          /* Decrease number of wait states update if necessary */\r
+          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
+          {\r
+            return HAL_ERROR;\r
+          }\r
+        }\r
+\r
+        /* Update the SystemCoreClock global variable */\r
+        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);\r
+\r
+        /* Configure the source of time base considering new system clocks settings*/\r
+        status = HAL_InitTick(uwTickPrio);\r
+        if(status != HAL_OK)\r
+        {\r
+          return status;\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Check the MSI State */\r
+      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)\r
+      {\r
+        /* Enable the Internal High Speed oscillator (MSI). */\r
+        __HAL_RCC_MSI_ENABLE();\r
+\r
+        /* Get timeout */\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till MSI is ready */\r
+        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+         /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
+        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
+         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
+        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
+\r
+      }\r
+      else\r
+      {\r
+        /* Disable the Internal High Speed oscillator (MSI). */\r
+        __HAL_RCC_MSI_DISABLE();\r
+\r
+        /* Get timeout */\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till MSI is ready */\r
+        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+      }\r
+    }\r
+  }\r
+  /*------------------------------- HSE Configuration ------------------------*/\r
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
+\r
+    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */\r
+    if((sysclk_source == RCC_CFGR_SWS_HSE) ||\r
+       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))\r
+    {\r
+      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Set the new HSE configuration ---------------------------------------*/\r
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
+\r
+      /* Check the HSE State */\r
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
+      {\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till HSE is ready */\r
+        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till HSE is disabled */\r
+        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+      }\r
+    }\r
+  }\r
+  /*----------------------------- HSI Configuration --------------------------*/\r
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
+    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
+\r
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\r
+    if((sysclk_source == RCC_CFGR_SWS_HSI) ||\r
+       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))\r
+    {\r
+      /* When HSI is used as system clock it will not be disabled */\r
+      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Otherwise, just the calibration is allowed */\r
+      else\r
+      {\r
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Check the HSI State */\r
+      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)\r
+      {\r
+        /* Enable the Internal High Speed oscillator (HSI). */\r
+        __HAL_RCC_HSI_ENABLE();\r
+\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till HSI is ready */\r
+        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+\r
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+      }\r
+      else\r
+      {\r
+        /* Disable the Internal High Speed oscillator (HSI). */\r
+        __HAL_RCC_HSI_DISABLE();\r
+\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till HSI is disabled */\r
+        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+      }\r
+    }\r
+  }\r
+  /*------------------------------ LSI Configuration -------------------------*/\r
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
+\r
+    /* Check the LSI State */\r
+    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)\r
+    {\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+      uint32_t csr_temp = RCC->CSR;\r
+\r
+      /* Check LSI division factor */\r
+      assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv));\r
+\r
+      if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPREDIV))\r
+      {\r
+        if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \\r
+            ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION))\r
+        {\r
+           /* If LSIRDY is set while LSION is not enabled,\r
+              LSIPREDIV can't be updated  */\r
+          return HAL_ERROR;\r
+        }\r
+\r
+        /* Turn off LSI before changing RCC_CSR_LSIPREDIV */\r
+        if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION)\r
+        {\r
+          __HAL_RCC_LSI_DISABLE();\r
+\r
+          /* Get Start Tick*/\r
+          tickstart = HAL_GetTick();\r
+\r
+          /* Wait till LSI is disabled */\r
+          while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)\r
+          {\r
+            if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
+            {\r
+              return HAL_TIMEOUT;\r
+            }\r
+          }\r
+        }\r
+\r
+        /* Set LSI division factor */\r
+        MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);\r
+      }\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+\r
+      /* Enable the Internal Low Speed oscillator (LSI). */\r
+      __HAL_RCC_LSI_ENABLE();\r
+\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till LSI is ready */\r
+      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
+        {\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Disable the Internal Low Speed oscillator (LSI). */\r
+      __HAL_RCC_LSI_DISABLE();\r
+\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till LSI is disabled */\r
+      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
+        {\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+  }\r
+  /*------------------------------ LSE Configuration -------------------------*/\r
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
+  {\r
+    FlagStatus       pwrclkchanged = RESET;\r
+\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
+\r
+    /* Update LSE configuration in Backup Domain control register    */\r
+    /* Requires to enable write access to Backup Domain of necessary */\r
+    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))\r
+    {\r
+      __HAL_RCC_PWR_CLK_ENABLE();\r
+      pwrclkchanged = SET;\r
+    }\r
+\r
+    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
+    {\r
+      /* Enable write access to Backup domain */\r
+      SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+\r
+      /* Wait for Backup domain Write protection disable */\r
+      tickstart = HAL_GetTick();\r
+\r
+      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
+      {\r
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+        {\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+\r
+    /* Set the new LSE configuration -----------------------------------------*/\r
+#if defined(RCC_BDCR_LSESYSDIS)\r
+    if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)\r
+    {\r
+      /* Set LSESYSDIS bit according to LSE propagation option (enabled or disabled) */\r
+      MODIFY_REG(RCC->BDCR, RCC_BDCR_LSESYSDIS, (RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSDIS));\r
+\r
+      if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)\r
+      {\r
+        /* LSE oscillator bypass enable */\r
+        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\r
+        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
+      }\r
+      else\r
+      {\r
+        /* LSE oscillator enable */\r
+        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
+      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\r
+    }\r
+#else\r
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
+#endif /* RCC_BDCR_LSESYSDIS */\r
+\r
+    /* Check the LSE State */\r
+    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)\r
+    {\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till LSE is ready */\r
+      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
+        {\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till LSE is disabled */\r
+      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
+        {\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+\r
+#if defined(RCC_BDCR_LSESYSDIS)\r
+      /* By default, stop disabling LSE propagation */\r
+      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);\r
+#endif /* RCC_BDCR_LSESYSDIS */\r
+    }\r
+\r
+    /* Restore clock configuration if changed */\r
+    if(pwrclkchanged == SET)\r
+    {\r
+      __HAL_RCC_PWR_CLK_DISABLE();\r
+    }\r
+  }\r
+#if defined(RCC_HSI48_SUPPORT)\r
+  /*------------------------------ HSI48 Configuration -----------------------*/\r
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));\r
+\r
+    /* Check the LSI State */\r
+    if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)\r
+    {\r
+      /* Enable the Internal Low Speed oscillator (HSI48). */\r
+      __HAL_RCC_HSI48_ENABLE();\r
+\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till HSI48 is ready */\r
+      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)\r
+        {\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Disable the Internal Low Speed oscillator (HSI48). */\r
+      __HAL_RCC_HSI48_DISABLE();\r
+\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till HSI48 is disabled */\r
+      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)\r
+        {\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+  }\r
+#endif /* RCC_HSI48_SUPPORT */\r
+  /*-------------------------------- PLL Configuration -----------------------*/\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
+\r
+  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)\r
+  {\r
+    /* Check if the PLL is used as system clock or not */\r
+    if(sysclk_source != RCC_CFGR_SWS_PLL)\r
+    {\r
+      if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)\r
+      {\r
+        /* Check the parameters */\r
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
+#if defined(RCC_PLLP_SUPPORT)\r
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
+#endif /* RCC_PLLP_SUPPORT */\r
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r
+\r
+        /* Disable the main PLL. */\r
+        __HAL_RCC_PLL_DISABLE();\r
+\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till PLL is ready */\r
+        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+\r
+        /* Configure the main PLL clock source, multiplication and division factors. */\r
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
+                             RCC_OscInitStruct->PLL.PLLM,\r
+                             RCC_OscInitStruct->PLL.PLLN,\r
+#if defined(RCC_PLLP_SUPPORT)\r
+                             RCC_OscInitStruct->PLL.PLLP,\r
+#endif\r
+                             RCC_OscInitStruct->PLL.PLLQ,\r
+                             RCC_OscInitStruct->PLL.PLLR);\r
+\r
+        /* Enable the main PLL. */\r
+        __HAL_RCC_PLL_ENABLE();\r
+\r
+        /* Enable PLL System Clock output. */\r
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);\r
+\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till PLL is ready */\r
+        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Disable the main PLL. */\r
+        __HAL_RCC_PLL_DISABLE();\r
+\r
+        /* Disable all PLL outputs to save power if no PLLs on */\r
+#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY)\r
+        if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U)\r
+        {\r
+          MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
+        }\r
+#elif defined(RCC_PLLSAI1_SUPPORT)\r
+        if(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)\r
+        {\r
+          MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
+        }\r
+#else\r
+        MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
+#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);\r
+#elif defined(RCC_PLLSAI1_SUPPORT)\r
+        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);\r
+#else\r
+        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK);\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till PLL is disabled */\r
+        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+          {\r
+            return HAL_TIMEOUT;\r
+          }\r
+        }\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Check if there is a request to disable the PLL used as System clock source */\r
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      else\r
+      {\r
+        pll_config = RCC->PLLCFGR;\r
+        /* Do not return HAL_ERROR if request repeats the current configuration */\r
+        if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||\r
+           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||\r
+           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||\r
+#if defined(RCC_PLLP_SUPPORT)\r
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
+           (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||\r
+#else\r
+           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||\r
+#endif\r
+#endif\r
+           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||\r
+           (READ_BIT(pll_config, RCC_PLLCFGR_PLLR)    != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+      }\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initialize the CPU, AHB and APB busses clocks according to the specified\r
+  *         parameters in the RCC_ClkInitStruct.\r
+  * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that\r
+  *         contains the configuration information for the RCC peripheral.\r
+  * @param  FLatency  FLASH Latency\r
+  *          This parameter can be one of the following values:\r
+  *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle\r
+  *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle\r
+  *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycles\r
+  *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycles\r
+  *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycles\r
+  @if STM32L4S9xx\r
+  *            @arg FLASH_LATENCY_5   FLASH 5 Latency cycles\r
+  *            @arg FLASH_LATENCY_6   FLASH 6 Latency cycles\r
+  *            @arg FLASH_LATENCY_7   FLASH 7 Latency cycles\r
+  *            @arg FLASH_LATENCY_8   FLASH 8 Latency cycles\r
+  *            @arg FLASH_LATENCY_9   FLASH 9 Latency cycles\r
+  *            @arg FLASH_LATENCY_10  FLASH 10 Latency cycles\r
+  *            @arg FLASH_LATENCY_11  FLASH 11 Latency cycles\r
+  *            @arg FLASH_LATENCY_12  FLASH 12 Latency cycles\r
+  *            @arg FLASH_LATENCY_13  FLASH 13 Latency cycles\r
+  *            @arg FLASH_LATENCY_14  FLASH 14 Latency cycles\r
+  *            @arg FLASH_LATENCY_15  FLASH 15 Latency cycles\r
+  @endif\r
+  *\r
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
+  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function\r
+  *\r
+  * @note   The MSI is used by default as system clock source after\r
+  *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,\r
+  *         the MSI frequency is set to its default value 4 MHz.\r
+  *\r
+  * @note   The HSI can be selected as system clock source after\r
+  *         from STOP modes or in case of failure of the HSE used directly or indirectly\r
+  *         as system clock (if the Clock Security System CSS is enabled).\r
+  *\r
+  * @note   A switch from one clock source to another occurs only if the target\r
+  *         clock source is ready (clock stable after startup delay or PLL locked).\r
+  *         If a clock source which is not yet ready is selected, the switch will\r
+  *         occur when the clock source is ready.\r
+  *\r
+  * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is\r
+  *         currently used as system clock source.\r
+  *\r
+  * @note   Depending on the device voltage range, the software has to set correctly\r
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r
+  *         (for more details refer to section above "Initialization/de-initialization functions")\r
+  * @retval None\r
+  */\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)\r
+{\r
+  uint32_t tickstart;\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+  uint32_t hpre = RCC_SYSCLK_DIV1;\r
+#endif\r
+  HAL_StatusTypeDef status;\r
+\r
+  /* Check Null pointer */\r
+  if(RCC_ClkInitStruct == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
+  assert_param(IS_FLASH_LATENCY(FLatency));\r
+\r
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
+    must be correctly programmed according to the frequency of the CPU clock\r
+    (HCLK) and the supply voltage of the device. */\r
+\r
+  /* Increasing the number of wait states because of higher CPU frequency */\r
+  if(FLatency > __HAL_FLASH_GET_LATENCY())\r
+  {\r
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+    __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+    /* Check that the new number of wait states is taken into account to access the Flash\r
+    memory by reading the FLASH_ACR register */\r
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+  }\r
+\r
+  /*------------------------- SYSCLK Configuration ---------------------------*/\r
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
+  {\r
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
+\r
+    /* PLL is selected as System Clock Source */\r
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+    {\r
+      /* Check the PLL ready flag */\r
+      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+      /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */\r
+      /* Compute target PLL output frequency */\r
+      if(RCC_GetSysClockFreqFromPLLSource() > 80000000U)\r
+      {\r
+        if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)\r
+        {\r
+          /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */\r
+          MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
+          hpre = RCC_SYSCLK_DIV2;\r
+        }\r
+        else if((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))\r
+        {\r
+          /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */\r
+          MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
+          hpre = RCC_SYSCLK_DIV2;\r
+        }\r
+        else\r
+        {\r
+          /* nothing to do */\r
+        }\r
+      }\r
+#endif\r
+    }\r
+    else\r
+    {\r
+      /* HSE is selected as System Clock Source */\r
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+      {\r
+        /* Check the HSE ready flag */\r
+        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+      }\r
+      /* MSI is selected as System Clock Source */\r
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)\r
+      {\r
+        /* Check the MSI ready flag */\r
+        if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+      }\r
+      /* HSI is selected as System Clock Source */\r
+      else\r
+      {\r
+        /* Check the HSI ready flag */\r
+        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)\r
+        {\r
+          return HAL_ERROR;\r
+        }\r
+      }\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+      /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */\r
+      if(HAL_RCC_GetSysClockFreq() > 80000000U)\r
+      {\r
+        /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */\r
+        MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
+        hpre = RCC_SYSCLK_DIV2;\r
+      }\r
+#endif\r
+\r
+    }\r
+\r
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);\r
+\r
+    /* Get Start Tick*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))\r
+    {\r
+      if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+      {\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+  }\r
+\r
+  /*-------------------------- HCLK Configuration --------------------------*/\r
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+  {\r
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+  }\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+  else\r
+  {\r
+    /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */\r
+    if(hpre == RCC_SYSCLK_DIV2)\r
+    {\r
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);\r
+    }\r
+  }\r
+#endif\r
+\r
+  /* Decreasing the number of wait states because of lower CPU frequency */\r
+  if(FLatency < __HAL_FLASH_GET_LATENCY())\r
+  {\r
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+    __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+    /* Check that the new number of wait states is taken into account to access the Flash\r
+    memory by reading the FLASH_ACR register */\r
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+  }\r
+\r
+  /*-------------------------- PCLK1 Configuration ---------------------------*/\r
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+  {\r
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
+  }\r
+\r
+  /*-------------------------- PCLK2 Configuration ---------------------------*/\r
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+  {\r
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));\r
+  }\r
+\r
+  /* Update the SystemCoreClock global variable */\r
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);\r
+\r
+  /* Configure the source of time base considering new system clocks settings*/\r
+  status = HAL_InitTick(uwTickPrio);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\r
+ *  @brief   RCC clocks control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to:\r
+\r
+    (+) Ouput clock to MCO pin.\r
+    (+) Retrieve current clock frequencies.\r
+    (+) Enable the Clock Security System.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Select the clock source to output on MCO pin(PA8).\r
+  * @note   PA8 should be configured in alternate function mode.\r
+  * @param  RCC_MCOx  specifies the output direction for the clock source.\r
+  *          For STM32L4xx family this parameter can have only one value:\r
+  *            @arg @ref RCC_MCO1  Clock source to output on MCO1 pin(PA8).\r
+  * @param  RCC_MCOSource  specifies the clock source to output.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO\r
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee\r
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source\r
+  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48\r
+  @endif\r
+  * @param  RCC_MCODiv  specifies the MCO prescaler.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock\r
+  *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock\r
+  *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock\r
+  *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock\r
+  *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock\r
+  * @retval None\r
+  */\r
+void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_MCO(RCC_MCOx));\r
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
+  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
+\r
+  /* Prevent unused argument(s) compilation warning if no assert_param check */\r
+  UNUSED(RCC_MCOx);\r
+\r
+  /* MCO Clock Enable */\r
+  __MCO1_CLK_ENABLE();\r
+\r
+  /* Configue the MCO1 pin in alternate function mode */\r
+  GPIO_InitStruct.Pin = MCO1_PIN;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+  HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+  /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */\r
+  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv ));\r
+}\r
+\r
+/**\r
+  * @brief  Return the SYSCLK frequency.\r
+  *\r
+  * @note   The system frequency computed by this function is not the real\r
+  *         frequency in the chip. It is calculated based on the predefined\r
+  *         constant and the selected clock source:\r
+  * @note     If SYSCLK source is MSI, function returns values based on MSI\r
+  *             Value as defined by the MSI range.\r
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),\r
+  *           HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.\r
+  * @note     (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value\r
+  *               16 MHz) but the real value may vary depending on the variations\r
+  *               in voltage and temperature.\r
+  * @note     (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value\r
+  *                8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+  *                frequency of the crystal used. Otherwise, this function may\r
+  *                have wrong result.\r
+  *\r
+  * @note   The result of this function could be not correct when using fractional\r
+  *         value for HSE crystal.\r
+  *\r
+  * @note   This function can be used by the user application to compute the\r
+  *         baudrate for the communication peripherals or configure other parameters.\r
+  *\r
+  * @note   Each time SYSCLK changes, this function must be called to update the\r
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+  *\r
+  *\r
+  * @retval SYSCLK frequency\r
+  */\r
+uint32_t HAL_RCC_GetSysClockFreq(void)\r
+{\r
+  uint32_t msirange = 0U, sysclockfreq = 0U;\r
+  uint32_t pllvco, pllsource, pllr, pllm;    /* no init needed */\r
+  uint32_t sysclk_source, pll_oscsource;\r
+\r
+  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();\r
+  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();\r
+\r
+  if((sysclk_source == RCC_CFGR_SWS_MSI) ||\r
+     ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))\r
+  {\r
+    /* MSI or PLL with MSI source used as system clock source */\r
+\r
+    /* Get SYSCLK source */\r
+    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)\r
+    { /* MSISRANGE from RCC_CSR applies */\r
+      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;\r
+    }\r
+    else\r
+    { /* MSIRANGE from RCC_CR applies */\r
+      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;\r
+    }\r
+    /*MSI frequency range in HZ*/\r
+    msirange = MSIRangeTable[msirange];\r
+\r
+    if(sysclk_source == RCC_CFGR_SWS_MSI)\r
+    {\r
+      /* MSI used as system clock source */\r
+      sysclockfreq = msirange;\r
+    }\r
+  }\r
+  else if(sysclk_source == RCC_CFGR_SWS_HSI)\r
+  {\r
+    /* HSI used as system clock source */\r
+    sysclockfreq = HSI_VALUE;\r
+  }\r
+  else if(sysclk_source == RCC_CFGR_SWS_HSE)\r
+  {\r
+    /* HSE used as system clock source */\r
+    sysclockfreq = HSE_VALUE;\r
+  }\r
+  else\r
+  {\r
+    /* unexpected case: sysclockfreq at 0 */\r
+  }\r
+\r
+  if(sysclk_source == RCC_CFGR_SWS_PLL)\r
+  {\r
+    /* PLL used as system clock  source */\r
+\r
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM\r
+    SYSCLK = PLL_VCO / PLLR\r
+    */\r
+    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
+\r
+    switch (pllsource)\r
+    {\r
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\r
+      pllvco = HSI_VALUE;\r
+      break;\r
+\r
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\r
+      pllvco = HSE_VALUE;\r
+      break;\r
+\r
+    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */\r
+    default:\r
+      pllvco = msirange;\r
+      break;\r
+    }\r
+    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;\r
+    pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;\r
+    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;\r
+    sysclockfreq = pllvco / pllr;\r
+  }\r
+\r
+  return sysclockfreq;\r
+}\r
+\r
+/**\r
+  * @brief  Return the HCLK frequency.\r
+  * @note   Each time HCLK changes, this function must be called to update the\r
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+  *\r
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.\r
+  * @retval HCLK frequency in Hz\r
+  */\r
+uint32_t HAL_RCC_GetHCLKFreq(void)\r
+{\r
+  return SystemCoreClock;\r
+}\r
+\r
+/**\r
+  * @brief  Return the PCLK1 frequency.\r
+  * @note   Each time PCLK1 changes, this function must be called to update the\r
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+  * @retval PCLK1 frequency in Hz\r
+  */\r
+uint32_t HAL_RCC_GetPCLK1Freq(void)\r
+{\r
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
+  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));\r
+}\r
+\r
+/**\r
+  * @brief  Return the PCLK2 frequency.\r
+  * @note   Each time PCLK2 changes, this function must be called to update the\r
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
+  * @retval PCLK2 frequency in Hz\r
+  */\r
+uint32_t HAL_RCC_GetPCLK2Freq(void)\r
+{\r
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
+  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));\r
+}\r
+\r
+/**\r
+  * @brief  Configure the RCC_OscInitStruct according to the internal\r
+  *         RCC configuration registers.\r
+  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that\r
+  *         will be configured.\r
+  * @retval None\r
+  */\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(RCC_OscInitStruct != (void *)NULL);\r
+\r
+  /* Set all possible values for the Oscillator type parameter ---------------*/\r
+#if defined(RCC_HSI48_SUPPORT)\r
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \\r
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;\r
+#else\r
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \\r
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+  /* Get the HSE configuration -----------------------------------------------*/\r
+  if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
+  {\r
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
+  }\r
+  else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON)\r
+  {\r
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
+  }\r
+\r
+   /* Get the MSI configuration -----------------------------------------------*/\r
+  if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION)\r
+  {\r
+    RCC_OscInitStruct->MSIState = RCC_MSI_ON;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->MSIState = RCC_MSI_OFF;\r
+  }\r
+\r
+  RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos;\r
+  RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);\r
+\r
+  /* Get the HSI configuration -----------------------------------------------*/\r
+  if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION)\r
+  {\r
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
+  }\r
+\r
+  RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;\r
+\r
+  /* Get the LSE configuration -----------------------------------------------*/\r
+  if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
+  {\r
+#if defined(RCC_BDCR_LSESYSDIS)\r
+    if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)\r
+    {\r
+      RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;\r
+    }\r
+    else\r
+#endif /* RCC_BDCR_LSESYSDIS */\r
+    {\r
+      RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
+    }\r
+  }\r
+  else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
+  {\r
+#if defined(RCC_BDCR_LSESYSDIS)\r
+    if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)\r
+    {\r
+      RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;\r
+    }\r
+    else\r
+#endif /* RCC_BDCR_LSESYSDIS */\r
+    {\r
+      RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
+  }\r
+\r
+  /* Get the LSI configuration -----------------------------------------------*/\r
+  if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)\r
+  {\r
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
+  }\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+\r
+  /* Get the LSI configuration -----------------------------------------------*/\r
+  if((RCC->CSR & RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)\r
+  {\r
+    RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1;\r
+  }\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+\r
+#if defined(RCC_HSI48_SUPPORT)\r
+  /* Get the HSI48 configuration ---------------------------------------------*/\r
+  if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)\r
+  {\r
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;\r
+  }\r
+#else\r
+  RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;\r
+#endif /* RCC_HSI48_SUPPORT */\r
+\r
+  /* Get the PLL configuration -----------------------------------------------*/\r
+  if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)\r
+  {\r
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
+  }\r
+  RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
+  RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;\r
+  RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
+  RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);\r
+  RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U);\r
+#if defined(RCC_PLLP_SUPPORT)\r
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
+  RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
+#else\r
+  if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
+  {\r
+    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;\r
+  }\r
+  else\r
+  {\r
+    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;\r
+  }\r
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
+#endif /* RCC_PLLP_SUPPORT */\r
+}\r
+\r
+/**\r
+  * @brief  Configure the RCC_ClkInitStruct according to the internal\r
+  *         RCC configuration registers.\r
+  * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that\r
+  *         will be configured.\r
+  * @param  pFLatency  Pointer on the Flash Latency.\r
+  * @retval None\r
+  */\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(RCC_ClkInitStruct != (void  *)NULL);\r
+  assert_param(pFLatency != (void *)NULL);\r
+\r
+  /* Set all possible values for the Clock type parameter --------------------*/\r
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
+\r
+  /* Get the SYSCLK configuration --------------------------------------------*/\r
+  RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);\r
+\r
+  /* Get the HCLK configuration ----------------------------------------------*/\r
+  RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);\r
+\r
+  /* Get the APB1 configuration ----------------------------------------------*/\r
+  RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);\r
+\r
+  /* Get the APB2 configuration ----------------------------------------------*/\r
+  RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);\r
+\r
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/\r
+  *pFLatency = __HAL_FLASH_GET_LATENCY();\r
+}\r
+\r
+/**\r
+  * @brief  Enable the Clock Security System.\r
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator\r
+  *         is automatically disabled and an interrupt is generated to inform the\r
+  *         software about the failure (Clock Security System Interrupt, CSSI),\r
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to\r
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.\r
+  * @note   The Clock Security System can only be cleared by reset.\r
+  * @retval None\r
+  */\r
+void HAL_RCC_EnableCSS(void)\r
+{\r
+  SET_BIT(RCC->CR, RCC_CR_CSSON) ;\r
+}\r
+\r
+/**\r
+  * @brief Handle the RCC Clock Security System interrupt request.\r
+  * @note This API should be called under the NMI_Handler().\r
+  * @retval None\r
+  */\r
+void HAL_RCC_NMI_IRQHandler(void)\r
+{\r
+  /* Check RCC CSSF interrupt flag  */\r
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
+  {\r
+    /* RCC Clock Security System interrupt user callback */\r
+    HAL_RCC_CSSCallback();\r
+\r
+    /* Clear RCC CSS pending bit */\r
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  RCC Clock Security System interrupt callback.\r
+  * @retval none\r
+  */\r
+__weak void HAL_RCC_CSSCallback(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_RCC_CSSCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup RCC_Private_Functions\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Update number of Flash wait states in line with MSI range and current\r
+            voltage range.\r
+  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)\r
+{\r
+  uint32_t vos;\r
+  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */\r
+\r
+  if(__HAL_RCC_PWR_IS_CLK_ENABLED())\r
+  {\r
+    vos = HAL_PWREx_GetVoltageRange();\r
+  }\r
+  else\r
+  {\r
+    __HAL_RCC_PWR_CLK_ENABLE();\r
+    vos = HAL_PWREx_GetVoltageRange();\r
+    __HAL_RCC_PWR_CLK_DISABLE();\r
+  }\r
+\r
+  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)\r
+  {\r
+    if(msirange > RCC_MSIRANGE_8)\r
+    {\r
+      /* MSI > 16Mhz */\r
+      if(msirange > RCC_MSIRANGE_10)\r
+      {\r
+        /* MSI 48Mhz */\r
+        latency = FLASH_LATENCY_2; /* 2WS */\r
+      }\r
+      else\r
+      {\r
+        /* MSI 24Mhz or 32Mhz */\r
+        latency = FLASH_LATENCY_1; /* 1WS */\r
+      }\r
+    }\r
+    /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */\r
+  }\r
+  else\r
+  {\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+    if(msirange >= RCC_MSIRANGE_8)\r
+    {\r
+      /* MSI >= 16Mhz */\r
+      latency = FLASH_LATENCY_2; /* 2WS */\r
+    }\r
+    else\r
+    {\r
+      if(msirange == RCC_MSIRANGE_7)\r
+      {\r
+        /* MSI 8Mhz */\r
+        latency = FLASH_LATENCY_1; /* 1WS */\r
+      }\r
+      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */\r
+    }\r
+#else\r
+    if(msirange > RCC_MSIRANGE_8)\r
+    {\r
+      /* MSI > 16Mhz */\r
+      latency = FLASH_LATENCY_3; /* 3WS */\r
+    }\r
+    else\r
+    {\r
+      if(msirange == RCC_MSIRANGE_8)\r
+      {\r
+        /* MSI 16Mhz */\r
+        latency = FLASH_LATENCY_2; /* 2WS */\r
+      }\r
+      else if(msirange == RCC_MSIRANGE_7)\r
+      {\r
+        /* MSI 8Mhz */\r
+        latency = FLASH_LATENCY_1; /* 1WS */\r
+      }\r
+      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */\r
+    }\r
+#endif\r
+  }\r
+\r
+  __HAL_FLASH_SET_LATENCY(latency);\r
+\r
+  /* Check that the new number of wait states is taken into account to access the Flash\r
+     memory by reading the FLASH_ACR register */\r
+  if(__HAL_FLASH_GET_LATENCY() != latency)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+/**\r
+  * @brief  Compute SYSCLK frequency based on PLL SYSCLK source.\r
+  * @retval SYSCLK frequency\r
+  */\r
+static uint32_t RCC_GetSysClockFreqFromPLLSource(void)\r
+{\r
+  uint32_t msirange = 0U;\r
+  uint32_t pllvco, pllsource, pllr, pllm, sysclockfreq;  /* no init needed */\r
+\r
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)\r
+  {\r
+    /* Get MSI range source */\r
+    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)\r
+    { /* MSISRANGE from RCC_CSR applies */\r
+      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;\r
+    }\r
+    else\r
+    { /* MSIRANGE from RCC_CR applies */\r
+      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;\r
+    }\r
+    /*MSI frequency range in HZ*/\r
+    msirange = MSIRangeTable[msirange];\r
+  }\r
+\r
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM\r
+     SYSCLK = PLL_VCO / PLLR\r
+   */\r
+  pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
+\r
+  switch (pllsource)\r
+  {\r
+  case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\r
+    pllvco = HSI_VALUE;\r
+    break;\r
+\r
+  case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\r
+    pllvco = HSE_VALUE;\r
+    break;\r
+\r
+  case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */\r
+  default:\r
+    pllvco = msirange;\r
+    break;\r
+  }\r
+  pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;\r
+  pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;\r
+  pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;\r
+  sysclockfreq = pllvco / pllr;\r
+\r
+  return sysclockfreq;\r
+}\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
new file mode 100644 (file)
index 0000000..2dc8462
--- /dev/null
@@ -0,0 +1,3538 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_rcc_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   Extended RCC HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities RCC extended peripheral:\r
+  *           + Extended Peripheral Control functions\r
+  *           + Extended Clock management functions\r
+  *           + Extended Clock Recovery System Control functions\r
+  *\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCCEx RCCEx\r
+  * @brief RCC Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants\r
+ * @{\r
+ */\r
+#define PLLSAI1_TIMEOUT_VALUE     2U    /* 2 ms (minimum Tick + 1) */\r
+#define PLLSAI2_TIMEOUT_VALUE     2U    /* 2 ms (minimum Tick + 1) */\r
+#define PLL_TIMEOUT_VALUE         2U    /* 2 ms (minimum Tick + 1) */\r
+\r
+#define DIVIDER_P_UPDATE          0U\r
+#define DIVIDER_Q_UPDATE          1U\r
+#define DIVIDER_R_UPDATE          2U\r
+\r
+#define __LSCO_CLK_ENABLE()       __HAL_RCC_GPIOA_CLK_ENABLE()\r
+#define LSCO_GPIO_PORT            GPIOA\r
+#define LSCO_PIN                  GPIO_PIN_2\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions\r
+ * @{\r
+ */\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider);\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider);\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+#if defined(SAI1)\r
+\r
+static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency);\r
+\r
+#endif /* SAI1 */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions\r
+ *  @brief  Extended Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                ##### Extended Peripheral Control functions  #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to control the RCC Clocks\r
+    frequencies.\r
+    [..]\r
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
+        select the RTC clock source; in this case the Backup domain will be reset in\r
+        order to modify the RTC Clock source, as consequence RTC registers (including\r
+        the backup registers) are set to their reset values.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initialize the RCC extended peripherals clocks according to the specified\r
+  *         parameters in the RCC_PeriphCLKInitTypeDef.\r
+  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+  *         contains a field PeriphClockSelection which can be a combination of the following values:\r
+  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock\r
+  @if STM32L462xx\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)\r
+  @endif\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock\r
+  @if STM32L462xx\r
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock (only for devices with SAI1)\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
+  @endif\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock\r
+  @if STM32L462xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
+  @endif\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
+  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
+  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
+  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral kernel clock (only for devices with DFSDM1)\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO  DFSDM1 peripheral audio clock (only for devices with DFSDM1)\r
+  *            @arg @ref RCC_PERIPHCLK_LTDC  LTDC peripheral clock (only for devices with LTDC)\r
+  *            @arg @ref RCC_PERIPHCLK_DSI  DSI peripheral clock (only for devices with DSI)\r
+  *            @arg @ref RCC_PERIPHCLK_OSPI  OctoSPI peripheral clock (only for devices with OctoSPI)\r
+  @endif\r
+  *\r
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\r
+  *         the RTC clock source: in this case the access to Backup domain is enabled.\r
+  *\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r
+{\r
+  uint32_t tmpregister, tickstart;     /* no init needed */\r
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */\r
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
+\r
+#if defined(SAI1)\r
+\r
+  /*-------------------------- SAI1 clock source configuration ---------------------*/\r
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));\r
+\r
+    switch(PeriphClkInit->Sai1ClockSelection)\r
+    {\r
+    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/\r
+      /* Enable SAI Clock output generated form System PLL . */\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);\r
+#else\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+      /* SAI1 clock source config set later after clock selection check */\r
+      break;\r
+\r
+    case RCC_SAI1CLKSOURCE_PLLSAI1:  /* PLLSAI1 is used as clock source for SAI1*/\r
+      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */\r
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);\r
+      /* SAI1 clock source config set later after clock selection check */\r
+      break;\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+    case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/\r
+      /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */\r
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);\r
+      /* SAI1 clock source config set later after clock selection check */\r
+      break;\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+    case RCC_SAI1CLKSOURCE_PIN:      /* External clock is used as source of SAI1 clock*/\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+    case RCC_SAI1CLKSOURCE_HSI:      /* HSI is used as source of SAI1 clock*/\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+      /* SAI1 clock source config set later after clock selection check */\r
+      break;\r
+\r
+    default:\r
+      ret = HAL_ERROR;\r
+      break;\r
+    }\r
+\r
+    if(ret == HAL_OK)\r
+    {\r
+      /* Set the source of SAI1 clock*/\r
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r
+    }\r
+    else\r
+    {\r
+      /* set overall return value */\r
+      status = ret;\r
+    }\r
+  }\r
+\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+\r
+  /*-------------------------- SAI2 clock source configuration ---------------------*/\r
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));\r
+\r
+    switch(PeriphClkInit->Sai2ClockSelection)\r
+    {\r
+    case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/\r
+      /* Enable SAI Clock output generated form System PLL . */\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);\r
+      /* SAI2 clock source config set later after clock selection check */\r
+      break;\r
+\r
+    case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/\r
+      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */\r
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);\r
+      /* SAI2 clock source config set later after clock selection check */\r
+      break;\r
+\r
+    case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/\r
+      /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */\r
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);\r
+      /* SAI2 clock source config set later after clock selection check */\r
+      break;\r
+\r
+    case RCC_SAI2CLKSOURCE_PIN:      /* External clock is used as source of SAI2 clock*/\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+    case RCC_SAI2CLKSOURCE_HSI:      /* HSI is used as source of SAI2 clock*/\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+      /* SAI2 clock source config set later after clock selection check */\r
+      break;\r
+\r
+    default:\r
+      ret = HAL_ERROR;\r
+      break;\r
+    }\r
+\r
+    if(ret == HAL_OK)\r
+    {\r
+      /* Set the source of SAI2 clock*/\r
+      __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r
+    }\r
+    else\r
+    {\r
+      /* set overall return value */\r
+      status = ret;\r
+    }\r
+  }\r
+#endif /* SAI2 */\r
+\r
+  /*-------------------------- RTC clock source configuration ----------------------*/\r
+  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)\r
+  {\r
+    FlagStatus       pwrclkchanged = RESET;\r
+\r
+    /* Check for RTC Parameters used to output RTCCLK */\r
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
+\r
+    /* Enable Power Clock */\r
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)\r
+    {\r
+      __HAL_RCC_PWR_CLK_ENABLE();\r
+      pwrclkchanged = SET;\r
+    }\r
+\r
+    /* Enable write access to Backup domain */\r
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+\r
+    /* Wait for Backup domain Write protection disable */\r
+    tickstart = HAL_GetTick();\r
+\r
+    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)\r
+    {\r
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+      {\r
+        ret = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+\r
+    if(ret == HAL_OK)\r
+    {\r
+      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */\r
+      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);\r
+\r
+      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))\r
+      {\r
+        /* Store the content of BDCR register before the reset of Backup Domain */\r
+        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));\r
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
+        __HAL_RCC_BACKUPRESET_FORCE();\r
+        __HAL_RCC_BACKUPRESET_RELEASE();\r
+        /* Restore the Content of BDCR register */\r
+        RCC->BDCR = tmpregister;\r
+      }\r
+\r
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r
+      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))\r
+      {\r
+        /* Get Start Tick*/\r
+        tickstart = HAL_GetTick();\r
+\r
+        /* Wait till LSE is ready */\r
+        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)\r
+        {\r
+          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
+          {\r
+            ret = HAL_TIMEOUT;\r
+            break;\r
+          }\r
+        }\r
+      }\r
+\r
+      if(ret == HAL_OK)\r
+      {\r
+        /* Apply new RTC clock source selection */\r
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r
+      }\r
+      else\r
+      {\r
+        /* set overall return value */\r
+        status = ret;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* set overall return value */\r
+      status = ret;\r
+    }\r
+\r
+    /* Restore clock configuration if changed */\r
+    if(pwrclkchanged == SET)\r
+    {\r
+      __HAL_RCC_PWR_CLK_DISABLE();\r
+    }\r
+  }\r
+\r
+  /*-------------------------- USART1 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r
+\r
+    /* Configure the USART1 clock source */\r
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r
+  }\r
+\r
+  /*-------------------------- USART2 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r
+\r
+    /* Configure the USART2 clock source */\r
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r
+  }\r
+\r
+#if defined(USART3)\r
+\r
+  /*-------------------------- USART3 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r
+\r
+    /* Configure the USART3 clock source */\r
+    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r
+  }\r
+\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+\r
+  /*-------------------------- UART4 clock source configuration --------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r
+\r
+    /* Configure the UART4 clock source */\r
+    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r
+  }\r
+\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+\r
+  /*-------------------------- UART5 clock source configuration --------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r
+\r
+    /* Configure the UART5 clock source */\r
+    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r
+  }\r
+\r
+#endif /* UART5 */\r
+\r
+  /*-------------------------- LPUART1 clock source configuration ------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));\r
+\r
+    /* Configure the LPUAR1 clock source */\r
+    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);\r
+  }\r
+\r
+  /*-------------------------- LPTIM1 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))\r
+  {\r
+    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r
+  }\r
+\r
+  /*-------------------------- LPTIM2 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))\r
+  {\r
+    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));\r
+    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);\r
+  }\r
+\r
+  /*-------------------------- I2C1 clock source configuration ---------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r
+\r
+    /* Configure the I2C1 clock source */\r
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r
+  }\r
+\r
+#if defined(I2C2)\r
+\r
+  /*-------------------------- I2C2 clock source configuration ---------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r
+\r
+    /* Configure the I2C2 clock source */\r
+    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r
+  }\r
+\r
+#endif /* I2C2 */\r
+\r
+  /*-------------------------- I2C3 clock source configuration ---------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r
+\r
+    /* Configure the I2C3 clock source */\r
+    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r
+  }\r
+\r
+#if defined(I2C4)\r
+\r
+  /*-------------------------- I2C4 clock source configuration ---------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r
+\r
+    /* Configure the I2C4 clock source */\r
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r
+  }\r
+\r
+#endif /* I2C4 */\r
+\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+\r
+  /*-------------------------- USB clock source configuration ----------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))\r
+  {\r
+    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));\r
+    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);\r
+\r
+    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)\r
+    {\r
+      /* Enable PLL48M1CLK output */\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
+    }\r
+    else\r
+    {\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+      if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)\r
+      {\r
+        /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */\r
+        ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);\r
+\r
+        if(ret != HAL_OK)\r
+        {\r
+          /* set overall return value */\r
+          status = ret;\r
+        }\r
+      }\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+    }\r
+  }\r
+\r
+#endif /* USB_OTG_FS || USB */\r
+\r
+#if defined(SDMMC1)\r
+\r
+  /*-------------------------- SDMMC1 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))\r
+  {\r
+    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r
+    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r
+\r
+    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)   /* PLL "Q" ? */\r
+    {\r
+      /* Enable PLL48M1CLK output */\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
+    }\r
+#if defined(RCC_CCIPR2_SDMMCSEL)\r
+    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */\r
+    {\r
+      /* Enable PLLSAI3CLK output */\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);\r
+    }\r
+#endif\r
+    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)\r
+    {\r
+      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */\r
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);\r
+\r
+      if(ret != HAL_OK)\r
+      {\r
+        /* set overall return value */\r
+        status = ret;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* nothing to do */\r
+    }\r
+  }\r
+\r
+#endif /* SDMMC1 */\r
+\r
+  /*-------------------------- RNG clock source configuration ----------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))\r
+  {\r
+    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));\r
+    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);\r
+\r
+    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)\r
+    {\r
+      /* Enable PLL48M1CLK output */\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
+    }\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)\r
+    {\r
+      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */\r
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);\r
+\r
+      if(ret != HAL_OK)\r
+      {\r
+        /* set overall return value */\r
+        status = ret;\r
+      }\r
+    }\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+    else\r
+    {\r
+      /* nothing to do */\r
+    }\r
+  }\r
+\r
+  /*-------------------------- ADC clock source configuration ----------------------*/\r
+#if !defined(STM32L412xx) && !defined(STM32L422xx)\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));\r
+\r
+    /* Configure the ADC interface clock source */\r
+    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)\r
+    {\r
+      /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */\r
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);\r
+\r
+      if(ret != HAL_OK)\r
+      {\r
+        /* set overall return value */\r
+        status = ret;\r
+      }\r
+    }\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+\r
+    else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)\r
+    {\r
+      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */\r
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);\r
+\r
+      if(ret != HAL_OK)\r
+      {\r
+        /* set overall return value */\r
+        status = ret;\r
+      }\r
+    }\r
+\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
+\r
+  }\r
+#endif /* !STM32L412xx && !STM32L422xx */\r
+\r
+#if defined(SWPMI1)\r
+\r
+  /*-------------------------- SWPMI1 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));\r
+\r
+    /* Configure the SWPMI1 clock source */\r
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);\r
+  }\r
+\r
+#endif /* SWPMI1 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+\r
+  /*-------------------------- DFSDM1 clock source configuration -------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\r
+\r
+    /* Configure the DFSDM1 interface clock source */\r
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\r
+  }\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+  /*-------------------------- DFSDM1 audio clock source configuration -------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));\r
+\r
+    /* Configure the DFSDM1 interface audio clock source */\r
+    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);\r
+  }\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+\r
+  /*-------------------------- LTDC clock source configuration --------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection));\r
+\r
+    /* Disable the PLLSAI2 */\r
+    __HAL_RCC_PLLSAI2_DISABLE();\r
+\r
+    /* Get Start Tick*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait till PLLSAI2 is ready */\r
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
+    {\r
+      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
+      {\r
+        ret = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+\r
+    if(ret == HAL_OK)\r
+    {\r
+      /* Configure the LTDC clock source */\r
+      __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection);\r
+\r
+      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */\r
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);\r
+    }\r
+\r
+    if(ret != HAL_OK)\r
+    {\r
+      /* set overall return value */\r
+      status = ret;\r
+    }\r
+  }\r
+\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+\r
+  /*-------------------------- DSI clock source configuration ---------------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));\r
+\r
+    /* Configure the DSI clock source */\r
+    __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);\r
+\r
+    if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2)\r
+    {\r
+      /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */\r
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE);\r
+\r
+      if(ret != HAL_OK)\r
+      {\r
+        /* set overall return value */\r
+        status = ret;\r
+      }\r
+    }\r
+  }\r
+\r
+#endif /* DSI */\r
+\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+\r
+  /*-------------------------- OctoSPIx clock source configuration ----------------*/\r
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection));\r
+\r
+    /* Configure the OctoSPI clock source */\r
+    __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);\r
+\r
+    if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL)\r
+    {\r
+      /* Enable PLL48M1CLK output */\r
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
+    }\r
+  }\r
+\r
+#endif /* OCTOSPI1 || OCTOSPI2 */\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.\r
+  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+  *         returns the configuration information for the Extended Peripherals\r
+  *         clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART,\r
+  *         USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r
+{\r
+  /* Set all possible values for the extended clock type parameter------------*/\r
+\r
+#if defined(STM32L412xx) || defined(STM32L422xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 |                                               RCC_PERIPHCLK_USB    | \\r
+                                                                RCC_PERIPHCLK_RNG    |                                                                      \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L431xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                                               \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L432xx) || defined(STM32L442xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 |                                                                      \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   |                        RCC_PERIPHCLK_I2C3   |                        \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \\r
+                                                                RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L433xx) || defined(STM32L443xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L451xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  |                        \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                                               \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    |                        RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L452xx) || defined(STM32L462xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  |                        \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    |                        RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L471xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3                          | \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2                          | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L496xx) || defined(STM32L4A6xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_RTC ;\r
+\r
+#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC                           | RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI;\r
+\r
+#elif defined(STM32L4R7xx) || defined(STM32L4S7xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC                           | RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI  | RCC_PERIPHCLK_LTDC;\r
+\r
+#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)\r
+\r
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC                           | RCC_PERIPHCLK_DFSDM1 | \\r
+                                        RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI  | RCC_PERIPHCLK_LTDC   | RCC_PERIPHCLK_DSI;\r
+\r
+#endif /* STM32L431xx */\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+  /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/\r
+\r
+  PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos;\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U;\r
+#else\r
+  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+  PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
+  PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U;\r
+  PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U;\r
+  PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U;\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+  /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/\r
+\r
+  PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+  PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U;\r
+#else\r
+  PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
+  PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;\r
+  PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U;\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+  PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U;\r
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
+  PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U;\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+  /* Get the USART1 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();\r
+  /* Get the USART2 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();\r
+\r
+#if defined(USART3)\r
+  /* Get the USART3 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+  /* Get the UART4 clock source ----------------------------------------------*/\r
+  PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+  /* Get the UART5 clock source ----------------------------------------------*/\r
+  PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();\r
+#endif /* UART5 */\r
+\r
+  /* Get the LPUART1 clock source --------------------------------------------*/\r
+  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();\r
+\r
+  /* Get the I2C1 clock source -----------------------------------------------*/\r
+  PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();\r
+\r
+#if defined(I2C2)\r
+   /* Get the I2C2 clock source ----------------------------------------------*/\r
+  PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();\r
+#endif /* I2C2 */\r
+\r
+  /* Get the I2C3 clock source -----------------------------------------------*/\r
+  PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();\r
+\r
+#if defined(I2C4)\r
+  /* Get the I2C4 clock source -----------------------------------------------*/\r
+  PeriphClkInit->I2c4ClockSelection    = __HAL_RCC_GET_I2C4_SOURCE();\r
+#endif /* I2C4 */\r
+\r
+  /* Get the LPTIM1 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();\r
+\r
+  /* Get the LPTIM2 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Lptim2ClockSelection  = __HAL_RCC_GET_LPTIM2_SOURCE();\r
+\r
+#if defined(SAI1)\r
+  /* Get the SAI1 clock source -----------------------------------------------*/\r
+  PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();\r
+#endif /* SAI1 */\r
+\r
+#if defined(SAI2)\r
+  /* Get the SAI2 clock source -----------------------------------------------*/\r
+  PeriphClkInit->Sai2ClockSelection    = __HAL_RCC_GET_SAI2_SOURCE();\r
+#endif /* SAI2 */\r
+\r
+  /* Get the RTC clock source ------------------------------------------------*/\r
+  PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();\r
+\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+  /* Get the USB clock source ------------------------------------------------*/\r
+  PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();\r
+#endif /* USB_OTG_FS || USB */\r
+\r
+#if defined(SDMMC1)\r
+  /* Get the SDMMC1 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Sdmmc1ClockSelection   = __HAL_RCC_GET_SDMMC1_SOURCE();\r
+#endif /* SDMMC1 */\r
+\r
+  /* Get the RNG clock source ------------------------------------------------*/\r
+  PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();\r
+\r
+#if !defined(STM32L412xx) && !defined(STM32L422xx)\r
+  /* Get the ADC clock source ------------------------------------------------*/\r
+  PeriphClkInit->AdcClockSelection     = __HAL_RCC_GET_ADC_SOURCE();\r
+#endif /* !STM32L412xx && !STM32L422xx */\r
+\r
+#if defined(SWPMI1)\r
+  /* Get the SWPMI1 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Swpmi1ClockSelection  = __HAL_RCC_GET_SWPMI1_SOURCE();\r
+#endif /* SWPMI1 */\r
+\r
+#if defined(DFSDM1_Filter0)\r
+  /* Get the DFSDM1 clock source ---------------------------------------------*/\r
+  PeriphClkInit->Dfsdm1ClockSelection  = __HAL_RCC_GET_DFSDM1_SOURCE();\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+  /* Get the DFSDM1 audio clock source ---------------------------------------*/\r
+  PeriphClkInit->Dfsdm1AudioClockSelection  = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+#if defined(LTDC)\r
+  /* Get the LTDC clock source -----------------------------------------------*/\r
+  PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+  /* Get the DSI clock source ------------------------------------------------*/\r
+  PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();\r
+#endif /* DSI */\r
+\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+  /* Get the OctoSPIclock source --------------------------------------------*/\r
+  PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();\r
+#endif /* OCTOSPI1 || OCTOSPI2 */\r
+}\r
+\r
+/**\r
+  * @brief  Return the peripheral clock frequency for peripherals with clock source from PLLSAIs\r
+  * @note   Return 0 if peripheral clock identifier not managed by this API\r
+  * @param  PeriphClk  Peripheral clock identifier\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock\r
+  @if STM32L462xx\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)\r
+  @endif\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock\r
+  @if STM32L462xx\r
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock (only for devices with SAI1)\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock\r
+  @if STM32L443xx\r
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
+  @endif\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
+  @endif\r
+  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock\r
+  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock\r
+  @if STM32L462xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)\r
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
+  @endif\r
+  @if STM32L486xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)\r
+  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)\r
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
+  @endif\r
+  @if STM32L4A6xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)\r
+  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)\r
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
+  @endif\r
+  @if STM32L4S9xx\r
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
+  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral kernel clock (only for devices with DFSDM1)\r
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO  DFSDM1 peripheral audio clock (only for devices with DFSDM1)\r
+  *            @arg @ref RCC_PERIPHCLK_LTDC  LTDC peripheral clock (only for devices with LTDC)\r
+  *            @arg @ref RCC_PERIPHCLK_DSI  DSI peripheral clock (only for devices with DSI)\r
+  *            @arg @ref RCC_PERIPHCLK_OSPI  OctoSPI peripheral clock (only for devices with OctoSPI)\r
+  @endif\r
+  * @retval Frequency in Hz\r
+  */\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
+{\r
+  uint32_t frequency = 0U;\r
+  uint32_t srcclk, pll_oscsource, pllvco, plln;    /* no init needed */\r
+#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)\r
+  uint32_t pllp;  /* no init needed */\r
+#endif\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));\r
+\r
+  if(PeriphClk == RCC_PERIPHCLK_RTC)\r
+  {\r
+    /* Get the current RTC source */\r
+    srcclk = __HAL_RCC_GET_RTC_SOURCE();\r
+\r
+    switch(srcclk)\r
+    {\r
+    case RCC_RTCCLKSOURCE_LSE:\r
+      /* Check if LSE is ready */\r
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+      {\r
+        frequency = LSE_VALUE;\r
+      }\r
+      break;\r
+    case RCC_RTCCLKSOURCE_LSI:\r
+      /* Check if LSI is ready */\r
+      if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))\r
+      {\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+        if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))\r
+        {\r
+          frequency = LSI_VALUE/128U;\r
+        }\r
+        else\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+        {\r
+          frequency = LSI_VALUE;\r
+        }\r
+      }\r
+      break;\r
+    case RCC_RTCCLKSOURCE_HSE_DIV32:\r
+      /* Check if HSE is ready */\r
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))\r
+      {\r
+        frequency = HSE_VALUE / 32U;\r
+      }\r
+      break;\r
+    default:\r
+      /* No clock source, frequency default init at 0 */\r
+      break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Other external peripheral clock source than RTC */\r
+    pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();\r
+\r
+    /* Compute PLL clock input */\r
+    switch(pll_oscsource)\r
+    {\r
+    case RCC_PLLSOURCE_MSI:   /* MSI ? */\r
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
+      {\r
+        /*MSI frequency range in HZ*/\r
+        pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
+      }\r
+      else\r
+      {\r
+        pllvco = 0U;\r
+      }\r
+      break;\r
+    case RCC_PLLSOURCE_HSI:   /* HSI ? */\r
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+      {\r
+        pllvco = HSI_VALUE;\r
+      }\r
+      else\r
+      {\r
+        pllvco = 0U;\r
+      }\r
+      break;\r
+    case RCC_PLLSOURCE_HSE:   /* HSE ? */\r
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))\r
+      {\r
+        pllvco = HSE_VALUE;\r
+      }\r
+      else\r
+      {\r
+        pllvco = 0U;\r
+      }\r
+      break;\r
+    default:\r
+      /* No source */\r
+      pllvco = 0U;\r
+      break;\r
+    }\r
+\r
+    switch(PeriphClk)\r
+    {\r
+#if defined(SAI1)\r
+\r
+    case RCC_PERIPHCLK_SAI1:\r
+      frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);\r
+      break;\r
+\r
+#endif\r
+\r
+#if defined(SAI2)\r
+\r
+    case RCC_PERIPHCLK_SAI2:\r
+      frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco);\r
+      break;\r
+\r
+#endif\r
+\r
+#if defined(USB_OTG_FS) || defined(USB)\r
+\r
+    case RCC_PERIPHCLK_USB:\r
+\r
+#endif /* USB_OTG_FS || USB */\r
+\r
+    case RCC_PERIPHCLK_RNG:\r
+\r
+#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL)\r
+\r
+    case RCC_PERIPHCLK_SDMMC1:\r
+\r
+#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */\r
+      {\r
+        srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_CCIPR_CLK48SEL:   /* MSI ? */\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
+          {\r
+            /*MSI frequency range in HZ*/\r
+            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
+          }\r
+          break;\r
+        case RCC_CCIPR_CLK48SEL_1:  /* PLL ? */\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
+          {\r
+            if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))\r
+            {\r
+              /* f(PLL Source) * PLLN / PLLM */\r
+              plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
+              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+              /* f(PLL48M1CLK) = f(VCO input) / PLLQ */\r
+              frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));\r
+            }\r
+          }\r
+          break;\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+        case RCC_CCIPR_CLK48SEL_0:  /* PLLSAI1 ? */\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))\r
+          {\r
+            if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))\r
+            {\r
+              plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+              /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
+              /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */\r
+              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
+#else\r
+              /* f(PLL Source) * PLLSAI1N / PLLM */\r
+              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+#endif\r
+              /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */\r
+              frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));\r
+            }\r
+          }\r
+          break;\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#if defined(RCC_HSI48_SUPPORT)\r
+        case 0U:\r
+          if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */\r
+          {\r
+            frequency = HSI48_VALUE;\r
+          }\r
+          break;\r
+#endif /* RCC_HSI48_SUPPORT */\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        } /* switch(srcclk) */\r
+        break;\r
+      }\r
+\r
+#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)\r
+\r
+    case RCC_PERIPHCLK_SDMMC1:\r
+\r
+      if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL))  /* PLL "P" ? */\r
+      {\r
+        if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
+        {\r
+          if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN))\r
+          {\r
+            /* f(PLL Source) * PLLN / PLLM */\r
+            plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
+            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+            /* f(PLLSAI3CLK) = f(VCO input) / PLLP */\r
+            pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
+            if(pllp == 0U)\r
+            {\r
+              if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
+              {\r
+                pllp = 17U;\r
+              }\r
+              else\r
+              {\r
+                pllp = 7U;\r
+              }\r
+            }\r
+            frequency = (pllvco / pllp);\r
+          }\r
+        }\r
+      }\r
+      else  /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */\r
+      {\r
+        srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_CCIPR_CLK48SEL:   /* MSI ? */\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
+          {\r
+            /*MSI frequency range in HZ*/\r
+            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
+          }\r
+          break;\r
+        case RCC_CCIPR_CLK48SEL_1:  /* PLL "Q" ? */\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
+          {\r
+            if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))\r
+            {\r
+              /* f(PLL Source) * PLLN / PLLM */\r
+              plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
+              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+              /* f(PLL48M1CLK) = f(VCO input) / PLLQ */\r
+              frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));\r
+            }\r
+          }\r
+          break;\r
+        case RCC_CCIPR_CLK48SEL_0:  /* PLLSAI1 ? */\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))\r
+          {\r
+            if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))\r
+            {\r
+              /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */\r
+              plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
+              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
+              /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */\r
+              frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));\r
+            }\r
+          }\r
+          break;\r
+        case 0U:\r
+          if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */\r
+          {\r
+            frequency = HSI48_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        } /* switch(srcclk) */\r
+      }\r
+      break;\r
+\r
+#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */\r
+\r
+    case RCC_PERIPHCLK_USART1:\r
+      {\r
+        /* Get the current USART1 source */\r
+        srcclk = __HAL_RCC_GET_USART1_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_USART1CLKSOURCE_PCLK2:\r
+          frequency = HAL_RCC_GetPCLK2Freq();\r
+          break;\r
+        case RCC_USART1CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_USART1CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_USART1CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+    case RCC_PERIPHCLK_USART2:\r
+      {\r
+        /* Get the current USART2 source */\r
+        srcclk = __HAL_RCC_GET_USART2_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_USART2CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_USART2CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_USART2CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_USART2CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#if defined(USART3)\r
+\r
+    case RCC_PERIPHCLK_USART3:\r
+      {\r
+        /* Get the current USART3 source */\r
+        srcclk = __HAL_RCC_GET_USART3_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_USART3CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_USART3CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_USART3CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_USART3CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* USART3 */\r
+\r
+#if defined(UART4)\r
+\r
+    case RCC_PERIPHCLK_UART4:\r
+      {\r
+        /* Get the current UART4 source */\r
+        srcclk = __HAL_RCC_GET_UART4_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_UART4CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_UART4CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_UART4CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_UART4CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* UART4 */\r
+\r
+#if defined(UART5)\r
+\r
+    case RCC_PERIPHCLK_UART5:\r
+      {\r
+        /* Get the current UART5 source */\r
+        srcclk = __HAL_RCC_GET_UART5_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_UART5CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_UART5CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_UART5CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_UART5CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* UART5 */\r
+\r
+    case RCC_PERIPHCLK_LPUART1:\r
+      {\r
+        /* Get the current LPUART1 source */\r
+        srcclk = __HAL_RCC_GET_LPUART1_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_LPUART1CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_LPUART1CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_LPUART1CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_LPUART1CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+    case RCC_PERIPHCLK_ADC:\r
+      {\r
+        srcclk = __HAL_RCC_GET_ADC_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_ADCCLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+        case RCC_ADCCLKSOURCE_PLLSAI1:\r
+          if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U)\r
+          {\r
+            plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+            /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
+            /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */\r
+            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
+#else\r
+            /* f(PLL Source) * PLLSAI1N / PLLM */\r
+            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+#endif\r
+            /* f(PLLADC1CLK) = f(VCOSAI1 input) / PLLSAI1R */\r
+            frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U));\r
+          }\r
+          break;\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
+        case RCC_ADCCLKSOURCE_PLLSAI2:\r
+          if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U)\r
+          {\r
+            plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+            /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */\r
+            /* f(PLLSAI2 Source) * PLLSAI2N / PLLSAI2M */\r
+            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));\r
+#else\r
+            /* f(PLL Source) * PLLSAI2N / PLLM */\r
+            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+#endif\r
+            /* f(PLLADC2CLK) = f(VCOSAI2 input) / PLLSAI2R */\r
+            frequency = (pllvco / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U));\r
+          }\r
+          break;\r
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#if defined(DFSDM1_Filter0)\r
+\r
+    case RCC_PERIPHCLK_DFSDM1:\r
+      {\r
+        /* Get the current DFSDM1 source */\r
+        srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();\r
+\r
+        if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2)\r
+        {\r
+          frequency = HAL_RCC_GetPCLK2Freq();\r
+        }\r
+        else\r
+        {\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+\r
+    case RCC_PERIPHCLK_DFSDM1AUDIO:\r
+      {\r
+        /* Get the current DFSDM1 audio source */\r
+        srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_DFSDM1AUDIOCLKSOURCE_SAI1:\r
+          frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);\r
+          break;\r
+        case RCC_DFSDM1AUDIOCLKSOURCE_MSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
+          {\r
+            /*MSI frequency range in HZ*/\r
+            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
+          }\r
+          break;\r
+        case RCC_DFSDM1AUDIOCLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#endif /* DFSDM1_Filter0 */\r
+\r
+    case RCC_PERIPHCLK_I2C1:\r
+      {\r
+        /* Get the current I2C1 source */\r
+        srcclk = __HAL_RCC_GET_I2C1_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_I2C1CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_I2C1CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_I2C1CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#if defined(I2C2)\r
+\r
+    case RCC_PERIPHCLK_I2C2:\r
+      {\r
+        /* Get the current I2C2 source */\r
+        srcclk = __HAL_RCC_GET_I2C2_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_I2C2CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_I2C2CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_I2C2CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* I2C2 */\r
+\r
+    case RCC_PERIPHCLK_I2C3:\r
+      {\r
+        /* Get the current I2C3 source */\r
+        srcclk = __HAL_RCC_GET_I2C3_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_I2C3CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_I2C3CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_I2C3CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#if defined(I2C4)\r
+\r
+    case RCC_PERIPHCLK_I2C4:\r
+      {\r
+        /* Get the current I2C4 source */\r
+        srcclk = __HAL_RCC_GET_I2C4_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_I2C4CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_I2C4CLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_I2C4CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* I2C4 */\r
+\r
+    case RCC_PERIPHCLK_LPTIM1:\r
+      {\r
+        /* Get the current LPTIM1 source */\r
+        srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_LPTIM1CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_LPTIM1CLKSOURCE_LSI:\r
+          if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))\r
+          {\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+            if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))\r
+            {\r
+              frequency = LSI_VALUE/128U;\r
+            }\r
+            else\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+            {\r
+              frequency = LSI_VALUE;\r
+            }\r
+          }\r
+          break;\r
+        case RCC_LPTIM1CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_LPTIM1CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+    case RCC_PERIPHCLK_LPTIM2:\r
+      {\r
+        /* Get the current LPTIM2 source */\r
+       srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_LPTIM2CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_LPTIM2CLKSOURCE_LSI:\r
+          if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))\r
+          {\r
+#if defined(RCC_CSR_LSIPREDIV)\r
+            if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))\r
+            {\r
+              frequency = LSI_VALUE/128U;\r
+            }\r
+            else\r
+#endif /* RCC_CSR_LSIPREDIV */\r
+            {\r
+              frequency = LSI_VALUE;\r
+            }\r
+          }\r
+          break;\r
+        case RCC_LPTIM2CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        case RCC_LPTIM2CLKSOURCE_LSE:\r
+          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
+          {\r
+            frequency = LSE_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#if defined(SWPMI1)\r
+\r
+    case RCC_PERIPHCLK_SWPMI1:\r
+      {\r
+        /* Get the current SWPMI1 source */\r
+        srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_SWPMI1CLKSOURCE_PCLK1:\r
+          frequency = HAL_RCC_GetPCLK1Freq();\r
+          break;\r
+        case RCC_SWPMI1CLKSOURCE_HSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+          {\r
+            frequency = HSI_VALUE;\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* SWPMI1 */\r
+\r
+#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
+\r
+    case RCC_PERIPHCLK_OSPI:\r
+      {\r
+        /* Get the current OctoSPI clock source */\r
+        srcclk = __HAL_RCC_GET_OSPI_SOURCE();\r
+\r
+        switch(srcclk)\r
+        {\r
+        case RCC_OSPICLKSOURCE_SYSCLK:\r
+          frequency = HAL_RCC_GetSysClockFreq();\r
+          break;\r
+        case RCC_OSPICLKSOURCE_MSI:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
+          {\r
+            /*MSI frequency range in HZ*/\r
+            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
+          }\r
+          break;\r
+        case RCC_OSPICLKSOURCE_PLL:\r
+          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
+          {\r
+            if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))\r
+            {\r
+              /* f(PLL Source) * PLLN / PLLM */\r
+              plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
+              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+              /* f(PLL48M1CLK) = f(VCO input) / PLLQ */\r
+              frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));\r
+            }\r
+          }\r
+          break;\r
+        default:\r
+          /* No clock source, frequency default init at 0 */\r
+          break;\r
+        }\r
+\r
+        break;\r
+      }\r
+\r
+#endif /* OCTOSPI1 || OCTOSPI2 */\r
+\r
+    default:\r
+      break;\r
+    }\r
+  }\r
+\r
+  return(frequency);\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions\r
+ *  @brief  Extended Clock management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                ##### Extended clock management functions  #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to control the\r
+    activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,\r
+    Low speed clock output and clock after wake-up from STOP mode.\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+/**\r
+  * @brief  Enable PLLSAI1.\r
+  * @param  PLLSAI1Init  pointer to an RCC_PLLSAI1InitTypeDef structure that\r
+  *         contains the configuration information for the PLLSAI1\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */\r
+  assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source));\r
+  assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M));\r
+  assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));\r
+  assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));\r
+  assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));\r
+  assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));\r
+  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));\r
+\r
+  /* Disable the PLLSAI1 */\r
+  __HAL_RCC_PLLSAI1_DISABLE();\r
+\r
+  /* Get Start Tick*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait till PLLSAI1 is ready to be updated */\r
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)\r
+  {\r
+    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
+    {\r
+      status = HAL_TIMEOUT;\r
+      break;\r
+    }\r
+  }\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+    /* Configure the PLLSAI1 Multiplication factor N */\r
+    /* Configure the PLLSAI1 Division factors M, P, Q and R */\r
+    __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);\r
+#else\r
+    /* Configure the PLLSAI1 Multiplication factor N */\r
+    /* Configure the PLLSAI1 Division factors P, Q and R */\r
+    __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+    /* Configure the PLLSAI1 Clock output(s) */\r
+    __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);\r
+\r
+    /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/\r
+    __HAL_RCC_PLLSAI1_ENABLE();\r
+\r
+    /* Get Start Tick*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait till PLLSAI1 is ready */\r
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)\r
+    {\r
+      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
+      {\r
+        status = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Disable PLLSAI1.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Disable the PLLSAI1 */\r
+  __HAL_RCC_PLLSAI1_DISABLE();\r
+\r
+  /* Get Start Tick*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait till PLLSAI1 is ready */\r
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)\r
+  {\r
+    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
+    {\r
+      status = HAL_TIMEOUT;\r
+      break;\r
+    }\r
+  }\r
+\r
+  /* Disable the PLLSAI1 Clock outputs */\r
+  __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN);\r
+\r
+  /* Reset PLL source to save power if no PLLs on */\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+  if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI2RDY)) == 0U)\r
+  {\r
+    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
+  }\r
+#else\r
+  if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
+  {\r
+    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
+  }\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+  return status;\r
+}\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+/**\r
+  * @brief  Enable PLLSAI2.\r
+  * @param  PLLSAI2Init  pointer to an RCC_PLLSAI2InitTypeDef structure that\r
+  *         contains the configuration information for the PLLSAI2\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */\r
+  assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source));\r
+  assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M));\r
+  assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));\r
+  assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+  assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q));\r
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
+  assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));\r
+  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));\r
+\r
+  /* Disable the PLLSAI2 */\r
+  __HAL_RCC_PLLSAI2_DISABLE();\r
+\r
+  /* Get Start Tick*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait till PLLSAI2 is ready to be updated */\r
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
+  {\r
+    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
+    {\r
+      status = HAL_TIMEOUT;\r
+      break;\r
+    }\r
+  }\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+    /* Configure the PLLSAI2 Multiplication factor N */\r
+    /* Configure the PLLSAI2 Division factors M, P, Q and R */\r
+    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);\r
+#elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+    /* Configure the PLLSAI2 Multiplication factor N */\r
+    /* Configure the PLLSAI2 Division factors M, P and R */\r
+    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);\r
+#elif defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+    /* Configure the PLLSAI2 Multiplication factor N */\r
+    /* Configure the PLLSAI2 Division factors P, Q and R */\r
+    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);\r
+#else\r
+    /* Configure the PLLSAI2 Multiplication factor N */\r
+    /* Configure the PLLSAI2 Division factors P and R */\r
+    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
+    /* Configure the PLLSAI2 Clock output(s) */\r
+    __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);\r
+\r
+    /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/\r
+    __HAL_RCC_PLLSAI2_ENABLE();\r
+\r
+    /* Get Start Tick*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait till PLLSAI2 is ready */\r
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)\r
+    {\r
+      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
+      {\r
+        status = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Disable PLLISAI2.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Disable the PLLSAI2 */\r
+  __HAL_RCC_PLLSAI2_DISABLE();\r
+\r
+  /* Get Start Tick*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait till PLLSAI2 is ready */\r
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
+  {\r
+    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
+    {\r
+      status = HAL_TIMEOUT;\r
+      break;\r
+    }\r
+  }\r
+\r
+  /* Disable the PLLSAI2 Clock outputs */\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN);\r
+#else\r
+  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN);\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
+\r
+  /* Reset PLL source to save power if no PLLs on */\r
+  if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY)) == 0U)\r
+  {\r
+    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+/**\r
+  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock.\r
+  * @param  WakeUpClk  Wakeup clock\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI oscillator selection\r
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI oscillator selection\r
+  * @note   This function shall not be called after the Clock Security System on HSE has been\r
+  *         enabled.\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)\r
+{\r
+  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));\r
+\r
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);\r
+}\r
+\r
+/**\r
+  * @brief  Configure the MSI range after standby mode.\r
+  * @note   After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).\r
+  * @param  MSIRange  MSI range\r
+  *         This parameter can be one of the following values:\r
+  *            @arg @ref RCC_MSIRANGE_4  Range 4 around 1 MHz\r
+  *            @arg @ref RCC_MSIRANGE_5  Range 5 around 2 MHz\r
+  *            @arg @ref RCC_MSIRANGE_6  Range 6 around 4 MHz (reset value)\r
+  *            @arg @ref RCC_MSIRANGE_7  Range 7 around 8 MHz\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)\r
+{\r
+  assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));\r
+\r
+  __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);\r
+}\r
+\r
+/**\r
+  * @brief  Enable the LSE Clock Security System.\r
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled\r
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC\r
+  *         clock with HAL_RCCEx_PeriphCLKConfig().\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_EnableLSECSS(void)\r
+{\r
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
+}\r
+\r
+/**\r
+  * @brief  Disable the LSE Clock Security System.\r
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_DisableLSECSS(void)\r
+{\r
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
+\r
+  /* Disable LSE CSS IT if any */\r
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);\r
+}\r
+\r
+/**\r
+  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.\r
+  * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_EnableLSECSS_IT(void)\r
+{\r
+  /* Enable LSE CSS */\r
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
+\r
+  /* Enable LSE CSS IT */\r
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);\r
+\r
+  /* Enable IT on EXTI Line 19 */\r
+  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();\r
+  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();\r
+}\r
+\r
+/**\r
+  * @brief Handle the RCC LSE Clock Security System interrupt request.\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_LSECSS_IRQHandler(void)\r
+{\r
+  /* Check RCC LSE CSSF flag  */\r
+  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))\r
+  {\r
+    /* RCC LSE Clock Security System interrupt user callback */\r
+    HAL_RCCEx_LSECSS_Callback();\r
+\r
+    /* Clear RCC LSE CSS pending bit */\r
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  RCCEx LSE Clock Security System interrupt callback.\r
+  * @retval none\r
+  */\r
+__weak void HAL_RCCEx_LSECSS_Callback(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).\r
+  * @param  LSCOSource  specifies the Low Speed clock source to output.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source\r
+  *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStruct;\r
+  FlagStatus       pwrclkchanged = RESET;\r
+  FlagStatus       backupchanged = RESET;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_LSCOSOURCE(LSCOSource));\r
+\r
+  /* LSCO Pin Clock Enable */\r
+  __LSCO_CLK_ENABLE();\r
+\r
+  /* Configue the LSCO pin in analog mode */\r
+  GPIO_InitStruct.Pin = LSCO_PIN;\r
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;\r
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\r
+  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+  HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+  /* Update LSCOSEL clock source in Backup Domain control register */\r
+  if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
+  {\r
+    __HAL_RCC_PWR_CLK_ENABLE();\r
+    pwrclkchanged = SET;\r
+  }\r
+  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
+  {\r
+    HAL_PWR_EnableBkUpAccess();\r
+    backupchanged = SET;\r
+  }\r
+\r
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);\r
+\r
+  if(backupchanged == SET)\r
+  {\r
+    HAL_PWR_DisableBkUpAccess();\r
+  }\r
+  if(pwrclkchanged == SET)\r
+  {\r
+    __HAL_RCC_PWR_CLK_DISABLE();\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Disable the Low Speed clock output.\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_DisableLSCO(void)\r
+{\r
+  FlagStatus       pwrclkchanged = RESET;\r
+  FlagStatus       backupchanged = RESET;\r
+\r
+  /* Update LSCOEN bit in Backup Domain control register */\r
+  if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
+  {\r
+    __HAL_RCC_PWR_CLK_ENABLE();\r
+    pwrclkchanged = SET;\r
+  }\r
+  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
+  {\r
+    /* Enable access to the backup domain */\r
+    HAL_PWR_EnableBkUpAccess();\r
+    backupchanged = SET;\r
+  }\r
+\r
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);\r
+\r
+  /* Restore previous configuration */\r
+  if(backupchanged == SET)\r
+  {\r
+    /* Disable access to the backup domain */\r
+    HAL_PWR_DisableBkUpAccess();\r
+  }\r
+  if(pwrclkchanged == SET)\r
+  {\r
+    __HAL_RCC_PWR_CLK_DISABLE();\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enable the PLL-mode of the MSI.\r
+  * @note   Prior to enable the PLL-mode of the MSI for automatic hardware\r
+  *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_EnableMSIPLLMode(void)\r
+{\r
+  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;\r
+}\r
+\r
+/**\r
+  * @brief  Disable the PLL-mode of the MSI.\r
+  * @note   PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_DisableMSIPLLMode(void)\r
+{\r
+  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#if defined(CRS)\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions\r
+ *  @brief  Extended Clock Recovery System Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                ##### Extended Clock Recovery System Control functions  #####\r
+ ===============================================================================\r
+    [..]\r
+      For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:\r
+\r
+      (#) In System clock config, HSI48 needs to be enabled\r
+\r
+      (#) Enable CRS clock in IP MSP init which will use CRS functions\r
+\r
+      (#) Call CRS functions as follows:\r
+          (##) Prepare synchronization configuration necessary for HSI48 calibration\r
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)\r
+                        and also HSI48 oscillator smooth trimming.\r
+              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate\r
+                        directly reload value with target and sychronization frequencies values\r
+          (##) Call function HAL_RCCEx_CRSConfig which\r
+              (+++) Resets CRS registers to their default values.\r
+              (+++) Configures CRS registers with synchronization configuration\r
+              (+++) Enables automatic calibration and frequency error counter feature\r
+           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the\r
+           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be\r
+           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock\r
+           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs\r
+           should be used as SYNC signal.\r
+\r
+          (##) A polling function is provided to wait for complete synchronization\r
+              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()\r
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue\r
+                        application if synchronization is OK\r
+\r
+      (#) User can retrieve information related to synchronization in calling function\r
+            HAL_RCCEx_CRSGetSynchronizationInfo()\r
+\r
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration\r
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.\r
+           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),\r
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be\r
+           incremented), while when it is detected during the upcounting phase it means that the actual frequency\r
+           is higher (and that the TRIM value should be decremented).\r
+\r
+      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go\r
+          through CRS Handler (CRS_IRQn/CRS_IRQHandler)\r
+              (++) Call function HAL_RCCEx_CRSConfig()\r
+              (++) Enable CRS_IRQn (thanks to NVIC functions)\r
+              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)\r
+              (++) Implement CRS status management in the following user callbacks called from\r
+                   HAL_RCCEx_CRS_IRQHandler():\r
+                   (+++) HAL_RCCEx_CRS_SyncOkCallback()\r
+                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()\r
+                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()\r
+                   (+++) HAL_RCCEx_CRS_ErrorCallback()\r
+\r
+      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().\r
+          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+  * @brief  Start automatic synchronization for polling mode\r
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)\r
+{\r
+  uint32_t value;  /* no init needed */\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));\r
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));\r
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));\r
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));\r
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));\r
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));\r
+\r
+  /* CONFIGURATION */\r
+\r
+  /* Before configuration, reset CRS registers to their default values*/\r
+  __HAL_RCC_CRS_FORCE_RESET();\r
+  __HAL_RCC_CRS_RELEASE_RESET();\r
+\r
+  /* Set the SYNCDIV[2:0] bits according to Prescaler value */\r
+  /* Set the SYNCSRC[1:0] bits according to Source value */\r
+  /* Set the SYNCSPOL bit according to Polarity value */\r
+  value = (pInit->Prescaler | pInit->Source | pInit->Polarity);\r
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */\r
+  value |= pInit->ReloadValue;\r
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */\r
+  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);\r
+  WRITE_REG(CRS->CFGR, value);\r
+\r
+  /* Adjust HSI48 oscillator smooth trimming */\r
+  /* Set the TRIM[6:0] bits for STM32L412xx/L422xx or TRIM[5:0] bits otherwise\r
+     according to RCC_CRS_HSI48CalibrationValue value */\r
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));\r
+\r
+  /* START AUTOMATIC SYNCHRONIZATION*/\r
+\r
+  /* Enable Automatic trimming & Frequency error counter */\r
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);\r
+}\r
+\r
+/**\r
+  * @brief  Generate the software synchronization event\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)\r
+{\r
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);\r
+}\r
+\r
+/**\r
+  * @brief  Return synchronization info\r
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)\r
+{\r
+  /* Check the parameter */\r
+  assert_param(pSynchroInfo != (void *)NULL);\r
+\r
+  /* Get the reload value */\r
+  pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));\r
+\r
+  /* Get HSI48 oscillator smooth trimming */\r
+  pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);\r
+\r
+  /* Get Frequency error capture */\r
+  pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);\r
+\r
+  /* Get Frequency error direction */\r
+  pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));\r
+}\r
+\r
+/**\r
+* @brief Wait for CRS Synchronization status.\r
+* @param Timeout  Duration of the timeout\r
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization\r
+*        frequency.\r
+* @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.\r
+* @retval Combination of Synchronization status\r
+*          This parameter can be a combination of the following values:\r
+*            @arg @ref RCC_CRS_TIMEOUT\r
+*            @arg @ref RCC_CRS_SYNCOK\r
+*            @arg @ref RCC_CRS_SYNCWARN\r
+*            @arg @ref RCC_CRS_SYNCERR\r
+*            @arg @ref RCC_CRS_SYNCMISS\r
+*            @arg @ref RCC_CRS_TRIMOVF\r
+*/\r
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)\r
+{\r
+  uint32_t crsstatus = RCC_CRS_NONE;\r
+  uint32_t tickstart;\r
+\r
+  /* Get timeout */\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait for CRS flag or timeout detection */\r
+  do\r
+  {\r
+    if(Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+      {\r
+        crsstatus = RCC_CRS_TIMEOUT;\r
+      }\r
+    }\r
+    /* Check CRS SYNCOK flag  */\r
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))\r
+    {\r
+      /* CRS SYNC event OK */\r
+      crsstatus |= RCC_CRS_SYNCOK;\r
+\r
+      /* Clear CRS SYNC event OK bit */\r
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);\r
+    }\r
+\r
+    /* Check CRS SYNCWARN flag  */\r
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))\r
+    {\r
+      /* CRS SYNC warning */\r
+      crsstatus |= RCC_CRS_SYNCWARN;\r
+\r
+      /* Clear CRS SYNCWARN bit */\r
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);\r
+    }\r
+\r
+    /* Check CRS TRIM overflow flag  */\r
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))\r
+    {\r
+      /* CRS SYNC Error */\r
+      crsstatus |= RCC_CRS_TRIMOVF;\r
+\r
+      /* Clear CRS Error bit */\r
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);\r
+    }\r
+\r
+    /* Check CRS Error flag  */\r
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))\r
+    {\r
+      /* CRS SYNC Error */\r
+      crsstatus |= RCC_CRS_SYNCERR;\r
+\r
+      /* Clear CRS Error bit */\r
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);\r
+    }\r
+\r
+    /* Check CRS SYNC Missed flag  */\r
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))\r
+    {\r
+      /* CRS SYNC Missed */\r
+      crsstatus |= RCC_CRS_SYNCMISS;\r
+\r
+      /* Clear CRS SYNC Missed bit */\r
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);\r
+    }\r
+\r
+    /* Check CRS Expected SYNC flag  */\r
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))\r
+    {\r
+      /* frequency error counter reached a zero value */\r
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);\r
+    }\r
+  } while(RCC_CRS_NONE == crsstatus);\r
+\r
+  return crsstatus;\r
+}\r
+\r
+/**\r
+  * @brief Handle the Clock Recovery System interrupt request.\r
+  * @retval None\r
+  */\r
+void HAL_RCCEx_CRS_IRQHandler(void)\r
+{\r
+  uint32_t crserror = RCC_CRS_NONE;\r
+  /* Get current IT flags and IT sources values */\r
+  uint32_t itflags = READ_REG(CRS->ISR);\r
+  uint32_t itsources = READ_REG(CRS->CR);\r
+\r
+  /* Check CRS SYNCOK flag  */\r
+  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))\r
+  {\r
+    /* Clear CRS SYNC event OK flag */\r
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);\r
+\r
+    /* user callback */\r
+    HAL_RCCEx_CRS_SyncOkCallback();\r
+  }\r
+  /* Check CRS SYNCWARN flag  */\r
+  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))\r
+  {\r
+    /* Clear CRS SYNCWARN flag */\r
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);\r
+\r
+    /* user callback */\r
+    HAL_RCCEx_CRS_SyncWarnCallback();\r
+  }\r
+  /* Check CRS Expected SYNC flag  */\r
+  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))\r
+  {\r
+    /* frequency error counter reached a zero value */\r
+    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);\r
+\r
+    /* user callback */\r
+    HAL_RCCEx_CRS_ExpectedSyncCallback();\r
+  }\r
+  /* Check CRS Error flags  */\r
+  else\r
+  {\r
+    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))\r
+    {\r
+      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)\r
+      {\r
+        crserror |= RCC_CRS_SYNCERR;\r
+      }\r
+      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)\r
+      {\r
+        crserror |= RCC_CRS_SYNCMISS;\r
+      }\r
+      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)\r
+      {\r
+        crserror |= RCC_CRS_TRIMOVF;\r
+      }\r
+\r
+      /* Clear CRS Error flags */\r
+      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);\r
+\r
+      /* user error callback */\r
+      HAL_RCCEx_CRS_ErrorCallback(crserror);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.\r
+  * @retval none\r
+  */\r
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.\r
+  * @retval none\r
+  */\r
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.\r
+  * @retval none\r
+  */\r
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)\r
+{\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  RCCEx Clock Recovery System Error interrupt callback.\r
+  * @param  Error Combination of Error status.\r
+  *         This parameter can be a combination of the following values:\r
+  *           @arg @ref RCC_CRS_SYNCERR\r
+  *           @arg @ref RCC_CRS_SYNCMISS\r
+  *           @arg @ref RCC_CRS_TRIMOVF\r
+  * @retval none\r
+  */\r
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(Error);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* CRS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup RCCEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+#if defined(RCC_PLLSAI1_SUPPORT)\r
+\r
+/**\r
+  * @brief  Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).\r
+  * @param  PllSai1  pointer to an RCC_PLLSAI1InitTypeDef structure that\r
+  *         contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s)\r
+  * @param  Divider  divider parameter to be updated\r
+  *\r
+  * @note   PLLSAI1 is temporary disable to apply new parameters\r
+  *\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */\r
+  /* P, Q and R dividers are verified in each specific divider case below */\r
+  assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source));\r
+  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));\r
+  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));\r
+  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));\r
+\r
+  /* Check that PLLSAI1 clock source and divider M can be applied */\r
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)\r
+  {\r
+    /* PLL clock source and divider M already set, check that no request for change  */\r
+    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)\r
+       ||\r
+       (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)\r
+#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+       ||\r
+       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)\r
+#endif\r
+      )\r
+    {\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Check PLLSAI1 clock source availability */\r
+    switch(PllSai1->PLLSAI1Source)\r
+    {\r
+    case RCC_PLLSOURCE_MSI:\r
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))\r
+      {\r
+        status = HAL_ERROR;\r
+      }\r
+      break;\r
+    case RCC_PLLSOURCE_HSI:\r
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))\r
+      {\r
+        status = HAL_ERROR;\r
+      }\r
+      break;\r
+    case RCC_PLLSOURCE_HSE:\r
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))\r
+      {\r
+        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))\r
+        {\r
+          status = HAL_ERROR;\r
+        }\r
+      }\r
+      break;\r
+    default:\r
+      status = HAL_ERROR;\r
+      break;\r
+    }\r
+\r
+    if(status == HAL_OK)\r
+    {\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+      /* Set PLLSAI1 clock source */\r
+      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);\r
+#else\r
+      /* Set PLLSAI1 clock source and divider M */\r
+      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);\r
+#endif\r
+    }\r
+  }\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+    /* Disable the PLLSAI1 */\r
+    __HAL_RCC_PLLSAI1_DISABLE();\r
+\r
+    /* Get Start Tick*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait till PLLSAI1 is ready to be updated */\r
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)\r
+    {\r
+      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
+      {\r
+        status = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+\r
+    if(status == HAL_OK)\r
+    {\r
+      if(Divider == DIVIDER_P_UPDATE)\r
+      {\r
+        assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+\r
+        /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) |\r
+                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
+#else\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) |\r
+                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
+\r
+#else\r
+        /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));\r
+#else\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));\r
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
+\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+      }\r
+      else if(Divider == DIVIDER_Q_UPDATE)\r
+      {\r
+        assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+        /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |\r
+                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
+#else\r
+        /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos));\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+      }\r
+      else\r
+      {\r
+        assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+        /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |\r
+                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
+#else\r
+        /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI1CFGR,\r
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,\r
+                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
+                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));\r
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
+      }\r
+\r
+      /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/\r
+      __HAL_RCC_PLLSAI1_ENABLE();\r
+\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till PLLSAI1 is ready */\r
+      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
+        {\r
+          status = HAL_TIMEOUT;\r
+          break;\r
+        }\r
+      }\r
+\r
+      if(status == HAL_OK)\r
+      {\r
+        /* Configure the PLLSAI1 Clock output(s) */\r
+        __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);\r
+      }\r
+    }\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+#endif /* RCC_PLLSAI1_SUPPORT */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+/**\r
+  * @brief  Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).\r
+  * @param  PllSai2  pointer to an RCC_PLLSAI2InitTypeDef structure that\r
+  *         contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s)\r
+  * @param  Divider  divider parameter to be updated\r
+  *\r
+  * @note   PLLSAI2 is temporary disable to apply new parameters\r
+  *\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */\r
+  /* P, Q and R dividers are verified in each specific divider case below */\r
+  assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source));\r
+  assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));\r
+  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));\r
+  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));\r
+\r
+  /* Check that PLLSAI2 clock source and divider M can be applied */\r
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)\r
+  {\r
+    /* PLL clock source and divider M already set, check that no request for change  */\r
+    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)\r
+       ||\r
+       (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)\r
+#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+       ||\r
+       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)\r
+#endif\r
+      )\r
+    {\r
+      status = HAL_ERROR;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Check PLLSAI2 clock source availability */\r
+    switch(PllSai2->PLLSAI2Source)\r
+    {\r
+    case RCC_PLLSOURCE_MSI:\r
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))\r
+      {\r
+        status = HAL_ERROR;\r
+      }\r
+      break;\r
+    case RCC_PLLSOURCE_HSI:\r
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))\r
+      {\r
+        status = HAL_ERROR;\r
+      }\r
+      break;\r
+    case RCC_PLLSOURCE_HSE:\r
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))\r
+      {\r
+        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))\r
+        {\r
+          status = HAL_ERROR;\r
+        }\r
+      }\r
+      break;\r
+    default:\r
+      status = HAL_ERROR;\r
+      break;\r
+    }\r
+\r
+    if(status == HAL_OK)\r
+    {\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+      /* Set PLLSAI2 clock source */\r
+      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);\r
+#else\r
+      /* Set PLLSAI2 clock source and divider M */\r
+      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);\r
+#endif\r
+    }\r
+  }\r
+\r
+  if(status == HAL_OK)\r
+  {\r
+    /* Disable the PLLSAI2 */\r
+    __HAL_RCC_PLLSAI2_DISABLE();\r
+\r
+    /* Get Start Tick*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    /* Wait till PLLSAI2 is ready to be updated */\r
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
+    {\r
+      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
+      {\r
+        status = HAL_TIMEOUT;\r
+        break;\r
+      }\r
+    }\r
+\r
+    if(status == HAL_OK)\r
+    {\r
+      if(Divider == DIVIDER_P_UPDATE)\r
+      {\r
+        assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+\r
+        /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/\r
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) |\r
+                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
+#else\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) |\r
+                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\r
+\r
+#else\r
+        /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/\r
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));\r
+#else\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos));\r
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\r
+\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
+      }\r
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
+      else if(Divider == DIVIDER_Q_UPDATE)\r
+      {\r
+        assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q));\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+        /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) |\r
+                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
+#else\r
+        /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos));\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
+      }\r
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
+      else\r
+      {\r
+        assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+        /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |\r
+                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
+#else\r
+        /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/\r
+        MODIFY_REG(RCC->PLLSAI2CFGR,\r
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,\r
+                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
+                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));\r
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
+      }\r
+\r
+      /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/\r
+      __HAL_RCC_PLLSAI2_ENABLE();\r
+\r
+      /* Get Start Tick*/\r
+      tickstart = HAL_GetTick();\r
+\r
+      /* Wait till PLLSAI2 is ready */\r
+      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)\r
+      {\r
+        if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
+        {\r
+          status = HAL_TIMEOUT;\r
+          break;\r
+        }\r
+      }\r
+\r
+      if(status == HAL_OK)\r
+      {\r
+        /* Configure the PLLSAI2 Clock output(s) */\r
+        __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);\r
+      }\r
+    }\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+#if defined(SAI1)\r
+\r
+static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency)\r
+{\r
+  uint32_t frequency = 0U;\r
+  uint32_t srcclk = 0U;\r
+  uint32_t pllvco, plln;    /* no init needed */\r
+#if defined(RCC_PLLP_SUPPORT)\r
+  uint32_t pllp = 0U;\r
+#endif /* RCC_PLLP_SUPPORT */\r
+\r
+  /* Handle SAIs */\r
+  if(PeriphClk == RCC_PERIPHCLK_SAI1)\r
+  {\r
+    srcclk = __HAL_RCC_GET_SAI1_SOURCE();\r
+    if(srcclk == RCC_SAI1CLKSOURCE_PIN)\r
+    {\r
+      frequency = EXTERNAL_SAI1_CLOCK_VALUE;\r
+    }\r
+    /* Else, PLL clock output to check below */\r
+  }\r
+#if defined(SAI2)\r
+  else\r
+  {\r
+    if(PeriphClk == RCC_PERIPHCLK_SAI2)\r
+    {\r
+      srcclk = __HAL_RCC_GET_SAI2_SOURCE();\r
+      if(srcclk == RCC_SAI2CLKSOURCE_PIN)\r
+      {\r
+        frequency = EXTERNAL_SAI2_CLOCK_VALUE;\r
+      }\r
+      /* Else, PLL clock output to check below */\r
+    }\r
+  }\r
+#endif /* SAI2 */\r
+\r
+  if(frequency == 0U)\r
+  {\r
+    pllvco = InputFrequency;\r
+\r
+#if defined(SAI2)\r
+    if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))\r
+    {\r
+      if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U)\r
+      {\r
+        /* f(PLL Source) / PLLM */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+        /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */\r
+        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
+        pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
+#endif\r
+        if(pllp == 0U)\r
+        {\r
+          if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
+          {\r
+            pllp = 17U;\r
+          }\r
+          else\r
+          {\r
+            pllp = 7U;\r
+          }\r
+        }\r
+        frequency = (pllvco * plln) / pllp;\r
+      }\r
+    }\r
+    else if(srcclk == 0U)  /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */\r
+    {\r
+      if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)\r
+      {\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+        /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
+        /* f(PLLSAI1 Source) / PLLSAI1M */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
+#else\r
+        /* f(PLL Source) / PLLM */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+#endif\r
+        /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */\r
+        plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+        pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;\r
+#endif\r
+        if(pllp == 0U)\r
+        {\r
+          if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)\r
+          {\r
+            pllp = 17U;\r
+          }\r
+          else\r
+          {\r
+            pllp = 7U;\r
+          }\r
+        }\r
+        frequency = (pllvco * plln) / pllp;\r
+      }\r
+    }\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+    else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI))\r
+    {\r
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+      {\r
+        frequency = HSI_VALUE;\r
+      }\r
+    }\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#else\r
+    if(srcclk == RCC_SAI1CLKSOURCE_PLL)\r
+    {\r
+      if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U)\r
+      {\r
+        /* f(PLL Source) / PLLM */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+        /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */\r
+        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
+        pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
+#endif\r
+        if(pllp == 0U)\r
+        {\r
+          if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
+          {\r
+            pllp = 17U;\r
+          }\r
+          else\r
+          {\r
+            pllp = 7U;\r
+          }\r
+        }\r
+        frequency = (pllvco * plln) / pllp;\r
+      }\r
+      else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+      {\r
+        /* HSI automatically selected as clock source if PLLs not enabled */\r
+        frequency = HSI_VALUE;\r
+      }\r
+      else\r
+      {\r
+        /* No clock source, frequency default init at 0 */\r
+      }\r
+    }\r
+    else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)\r
+    {\r
+      if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)\r
+      {\r
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
+        /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
+        /* f(PLLSAI1 Source) / PLLSAI1M */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
+#else\r
+        /* f(PLL Source) / PLLM */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+#endif\r
+        /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */\r
+        plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
+        pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;\r
+#endif\r
+        if(pllp == 0U)\r
+        {\r
+          if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)\r
+          {\r
+            pllp = 17U;\r
+          }\r
+          else\r
+          {\r
+            pllp = 7U;\r
+          }\r
+        }\r
+        frequency = (pllvco * plln) / pllp;\r
+      }\r
+      else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
+      {\r
+        /* HSI automatically selected as clock source if PLLs not enabled */\r
+        frequency = HSI_VALUE;\r
+      }\r
+      else\r
+      {\r
+        /* No clock source, frequency default init at 0 */\r
+      }\r
+    }\r
+#endif /* SAI2 */\r
+\r
+#if defined(RCC_PLLSAI2_SUPPORT)\r
+\r
+    else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))\r
+    {\r
+      if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U)\r
+      {\r
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
+        /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */\r
+        /* f(PLLSAI2 Source) / PLLSAI2M */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));\r
+#else\r
+        /* f(PLL Source) / PLLM */\r
+        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
+#endif\r
+        /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */\r
+        plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;\r
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
+        pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos;\r
+#endif\r
+        if(pllp == 0U)\r
+        {\r
+          if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U)\r
+          {\r
+            pllp = 17U;\r
+          }\r
+          else\r
+          {\r
+            pllp = 7U;\r
+          }\r
+        }\r
+        frequency = (pllvco * plln) / pllp;\r
+      }\r
+    }\r
+\r
+#endif /* RCC_PLLSAI2_SUPPORT */\r
+\r
+    else\r
+    {\r
+      /* No clock source, frequency default init at 0 */\r
+    }\r
+  }\r
+\r
+\r
+  return frequency;\r
+}\r
+\r
+#endif /* SAI1 */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
new file mode 100644 (file)
index 0000000..3be342c
--- /dev/null
@@ -0,0 +1,4273 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_spi.c\r
+  * @author  MCD Application Team\r
+  * @brief   SPI HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:\r
+  *           + Initialization and de-initialization functions\r
+  *           + IO operation functions\r
+  *           + Peripheral Control functions\r
+  *           + Peripheral State functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                        ##### How to use this driver #####\r
+  ==============================================================================\r
+    [..]\r
+      The SPI HAL driver can be used as follows:\r
+\r
+      (#) Declare a SPI_HandleTypeDef handle structure, for example:\r
+          SPI_HandleTypeDef  hspi;\r
+\r
+      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\r
+          (##) Enable the SPIx interface clock\r
+          (##) SPI pins configuration\r
+              (+++) Enable the clock for the SPI GPIOs\r
+              (+++) Configure these SPI pins as alternate function push-pull\r
+          (##) NVIC configuration if you need to use interrupt process\r
+              (+++) Configure the SPIx interrupt priority\r
+              (+++) Enable the NVIC SPI IRQ handle\r
+          (##) DMA Configuration if you need to use DMA process\r
+              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel\r
+              (+++) Enable the DMAx clock\r
+              (+++) Configure the DMA handle parameters\r
+              (+++) Configure the DMA Tx or Rx Stream/Channel\r
+              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle\r
+              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel\r
+\r
+      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\r
+          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\r
+\r
+      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+              by calling the customized HAL_SPI_MspInit() API.\r
+     [..]\r
+       Circular mode restriction:\r
+      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r
+          (##) Master 2Lines RxOnly\r
+          (##) Master 1Line Rx\r
+      (#) The CRC feature is not managed when the DMA circular mode is enabled\r
+      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\r
+          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\r
+     [..]\r
+       Master Receive mode restriction:\r
+      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or\r
+          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI\r
+          does not initiate a new transfer the following procedure has to be respected:\r
+          (##) HAL_SPI_DeInit()\r
+          (##) HAL_SPI_Init()\r
+     [..]\r
+       Callback registration:\r
+\r
+      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U\r
+          allows the user to configure dynamically the driver callbacks.\r
+          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.\r
+\r
+          Function HAL_SPI_RegisterCallback() allows to register following callbacks:\r
+            (+) TxCpltCallback        : SPI Tx Completed callback\r
+            (+) RxCpltCallback        : SPI Rx Completed callback\r
+            (+) TxRxCpltCallback      : SPI TxRx Completed callback\r
+            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback\r
+            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback\r
+            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback\r
+            (+) ErrorCallback         : SPI Error callback\r
+            (+) AbortCpltCallback     : SPI Abort callback\r
+            (+) MspInitCallback       : SPI Msp Init callback\r
+            (+) MspDeInitCallback     : SPI Msp DeInit callback\r
+          This function takes as parameters the HAL peripheral handle, the Callback ID\r
+          and a pointer to the user callback function.\r
+\r
+\r
+      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default\r
+          weak function.\r
+          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
+          and the Callback ID.\r
+          This function allows to reset following callbacks:\r
+            (+) TxCpltCallback        : SPI Tx Completed callback\r
+            (+) RxCpltCallback        : SPI Rx Completed callback\r
+            (+) TxRxCpltCallback      : SPI TxRx Completed callback\r
+            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback\r
+            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback\r
+            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback\r
+            (+) ErrorCallback         : SPI Error callback\r
+            (+) AbortCpltCallback     : SPI Abort callback\r
+            (+) MspInitCallback       : SPI Msp Init callback\r
+            (+) MspDeInitCallback     : SPI Msp DeInit callback\r
+\r
+       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET\r
+       all callbacks are set to the corresponding weak functions:\r
+       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().\r
+       Exception done for MspInit and MspDeInit functions that are\r
+       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when\r
+       these callbacks are null (not registered beforehand).\r
+       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()\r
+       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\r
+\r
+       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.\r
+       Exception done MspInit/MspDeInit functions that can be registered/unregistered\r
+       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,\r
+       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\r
+       Then, the user first registers the MspInit/MspDeInit user callbacks\r
+       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()\r
+       or HAL_SPI_Init() function.\r
+\r
+       When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or\r
+       not defined, the callback registering feature is not available\r
+       and weak (surcharged) callbacks are used.\r
+\r
+     [..]\r
+       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,\r
+       the following table resume the max SPI frequency reached with data size 8bits/16bits,\r
+         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.\r
+\r
+  @endverbatim\r
+\r
+  Additional table :\r
+\r
+       DataSize = SPI_DATASIZE_8BIT:\r
+       +----------------------------------------------------------------------------------------------+\r
+       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\r
+       | Process | Tranfert mode  |---------------------|----------------------|----------------------|\r
+       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\r
+       |==============================================================================================|\r
+       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\r
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |\r
+       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\r
+       |=========|================|==========|==========|===========|==========|===========|==========|\r
+       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |\r
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |\r
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |\r
+       |=========|================|==========|==========|===========|==========|===========|==========|\r
+       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |\r
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |\r
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |\r
+       +----------------------------------------------------------------------------------------------+\r
+\r
+       DataSize = SPI_DATASIZE_16BIT:\r
+       +----------------------------------------------------------------------------------------------+\r
+       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\r
+       | Process | Tranfert mode  |---------------------|----------------------|----------------------|\r
+       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\r
+       |==============================================================================================|\r
+       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\r
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |\r
+       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\r
+       |=========|================|==========|==========|===========|==========|===========|==========|\r
+       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |\r
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |\r
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |\r
+       |=========|================|==========|==========|===========|==========|===========|==========|\r
+       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |\r
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |\r
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
+       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |\r
+       +----------------------------------------------------------------------------------------------+\r
+       @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),\r
+             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).\r
+       @note\r
+            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()\r
+            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()\r
+            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()\r
+\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SPI SPI\r
+  * @brief SPI HAL module driver\r
+  * @{\r
+  */\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup SPI_Private_Constants SPI Private Constants\r
+  * @{\r
+  */\r
+#define SPI_DEFAULT_TIMEOUT 100U\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup SPI_Private_Functions SPI Private Functions\r
+  * @{\r
+  */\r
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\r
+                                                       uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r
+                                                       uint32_t Timeout, uint32_t Tickstart);\r
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+#if (USE_SPI_CRC != 0U)\r
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+#endif /* USE_SPI_CRC */\r
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\r
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Functions SPI Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ *  @brief    Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+              ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+    [..]  This subsection provides a set of functions allowing to initialize and\r
+          de-initialize the SPIx peripheral:\r
+\r
+      (+) User must implement HAL_SPI_MspInit() function in which he configures\r
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+      (+) Call the function HAL_SPI_Init() to configure the selected device with\r
+          the selected configuration:\r
+        (++) Mode\r
+        (++) Direction\r
+        (++) Data Size\r
+        (++) Clock Polarity and Phase\r
+        (++) NSS Management\r
+        (++) BaudRate Prescaler\r
+        (++) FirstBit\r
+        (++) TIMode\r
+        (++) CRC Calculation\r
+        (++) CRC Polynomial if CRC enabled\r
+        (++) CRC Length, used only with Data8 and Data16\r
+        (++) FIFO reception threshold\r
+\r
+      (+) Call the function HAL_SPI_DeInit() to restore the default configuration\r
+          of the selected SPIx peripheral.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initialize the SPI according to the specified parameters\r
+  *         in the SPI_InitTypeDef and initialize the associated handle.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\r
+{\r
+  uint32_t frxth;\r
+\r
+  /* Check the SPI handle allocation */\r
+  if (hspi == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
+  assert_param(IS_SPI_MODE(hspi->Init.Mode));\r
+  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\r
+  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\r
+  assert_param(IS_SPI_NSS(hspi->Init.NSS));\r
+  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));\r
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\r
+  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\r
+  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\r
+  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)\r
+  {\r
+    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\r
+    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\r
+  }\r
+#if (USE_SPI_CRC != 0U)\r
+  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\r
+    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));\r
+  }\r
+#else\r
+  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
+#endif /* USE_SPI_CRC */\r
+\r
+  if (hspi->State == HAL_SPI_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    hspi->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+    /* Init the SPI Callback settings */\r
+    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */\r
+    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */\r
+    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */\r
+    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */\r
+    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */\r
+    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\r
+    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */\r
+    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */\r
+\r
+    if (hspi->MspInitCallback == NULL)\r
+    {\r
+      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */\r
+    }\r
+\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+    hspi->MspInitCallback(hspi);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+    HAL_SPI_MspInit(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  hspi->State = HAL_SPI_STATE_BUSY;\r
+\r
+  /* Disable the selected SPI peripheral */\r
+  __HAL_SPI_DISABLE(hspi);\r
+\r
+  /* Align by default the rs fifo threshold on the data size */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    frxth = SPI_RXFIFO_THRESHOLD_HF;\r
+  }\r
+  else\r
+  {\r
+    frxth = SPI_RXFIFO_THRESHOLD_QF;\r
+  }\r
+\r
+  /* CRC calculation is valid only for 16Bit and 8 Bit */\r
+  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))\r
+  {\r
+    /* CRC must be disabled */\r
+    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
+  }\r
+\r
+  /* Align the CRC Length on the data size */\r
+  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)\r
+  {\r
+    /* CRC Length aligned on the data size : value set by default */\r
+    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+    {\r
+      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;\r
+    }\r
+    else\r
+    {\r
+      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;\r
+    }\r
+  }\r
+\r
+  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/\r
+  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,\r
+  Communication speed, First bit and CRC calculation state */\r
+  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |\r
+                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\r
+                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Configure : CRC Length */\r
+  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+  {\r
+    hspi->Instance->CR1 |= SPI_CR1_CRCL;\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */\r
+  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |\r
+                                  hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/\r
+  /* Configure : CRC Polynomial */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+#if defined(SPI_I2SCFGR_I2SMOD)\r
+  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */\r
+  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);\r
+#endif /* SPI_I2SCFGR_I2SMOD */\r
+\r
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+  hspi->State     = HAL_SPI_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  De-Initialize the SPI peripheral.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Check the SPI handle allocation */\r
+  if (hspi == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check SPI Instance parameter */\r
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
+\r
+  hspi->State = HAL_SPI_STATE_BUSY;\r
+\r
+  /* Disable the SPI Peripheral Clock */\r
+  __HAL_SPI_DISABLE(hspi);\r
+\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  if (hspi->MspDeInitCallback == NULL)\r
+  {\r
+    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */\r
+  }\r
+\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+  hspi->MspDeInitCallback(hspi);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+  HAL_SPI_MspDeInit(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+\r
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+  hspi->State = HAL_SPI_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hspi);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initialize the SPI MSP.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_MspInit should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  De-Initialize the SPI MSP.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_MspDeInit should be implemented in the user file\r
+   */\r
+}\r
+\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+/**\r
+  * @brief  Register a User SPI Callback\r
+  *         To be used instead of the weak predefined callback\r
+  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified SPI.\r
+  * @param  CallbackID ID of the callback to be registered\r
+  * @param  pCallback pointer to the Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    /* Update the error code */\r
+    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+  /* Process locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  if (HAL_SPI_STATE_READY == hspi->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_SPI_TX_COMPLETE_CB_ID :\r
+        hspi->TxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_RX_COMPLETE_CB_ID :\r
+        hspi->RxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_TX_RX_COMPLETE_CB_ID :\r
+        hspi->TxRxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\r
+        hspi->TxHalfCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\r
+        hspi->RxHalfCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\r
+        hspi->TxRxHalfCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_ERROR_CB_ID :\r
+        hspi->ErrorCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_ABORT_CB_ID :\r
+        hspi->AbortCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_MSPINIT_CB_ID :\r
+        hspi->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_MSPDEINIT_CB_ID :\r
+        hspi->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (HAL_SPI_STATE_RESET == hspi->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_SPI_MSPINIT_CB_ID :\r
+        hspi->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_SPI_MSPDEINIT_CB_ID :\r
+        hspi->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hspi);\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister an SPI Callback\r
+  *         SPI callback is redirected to the weak predefined callback\r
+  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified SPI.\r
+  * @param  CallbackID ID of the callback to be unregistered\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  if (HAL_SPI_STATE_READY == hspi->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_SPI_TX_COMPLETE_CB_ID :\r
+        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */\r
+        break;\r
+\r
+      case HAL_SPI_RX_COMPLETE_CB_ID :\r
+        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */\r
+        break;\r
+\r
+      case HAL_SPI_TX_RX_COMPLETE_CB_ID :\r
+        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */\r
+        break;\r
+\r
+      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\r
+        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */\r
+        break;\r
+\r
+      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\r
+        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */\r
+        break;\r
+\r
+      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\r
+        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\r
+        break;\r
+\r
+      case HAL_SPI_ERROR_CB_ID :\r
+        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */\r
+        break;\r
+\r
+      case HAL_SPI_ABORT_CB_ID :\r
+        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */\r
+        break;\r
+\r
+      case HAL_SPI_MSPINIT_CB_ID :\r
+        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */\r
+        break;\r
+\r
+      case HAL_SPI_MSPDEINIT_CB_ID :\r
+        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (HAL_SPI_STATE_RESET == hspi->State)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_SPI_MSPINIT_CB_ID :\r
+        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */\r
+        break;\r
+\r
+      case HAL_SPI_MSPDEINIT_CB_ID :\r
+        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */\r
+        break;\r
+\r
+      default :\r
+        /* Update the error code */\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
+\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Update the error code */\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
+\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(hspi);\r
+  return status;\r
+}\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\r
+ *  @brief   Data transfers functions\r
+ *\r
+@verbatim\r
+  ==============================================================================\r
+                      ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..]\r
+    This subsection provides a set of functions allowing to manage the SPI\r
+    data transfers.\r
+\r
+    [..] The SPI supports master and slave mode :\r
+\r
+    (#) There are two modes of transfer:\r
+       (++) Blocking mode: The communication is performed in polling mode.\r
+            The HAL status of all data processing is returned by the same function\r
+            after finishing transfer.\r
+       (++) No-Blocking mode: The communication is performed using Interrupts\r
+            or DMA, These APIs return the HAL status.\r
+            The end of the data processing will be indicated through the\r
+            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\r
+            using DMA mode.\r
+            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\r
+            will be executed respectively at the end of the transmit or Receive process\r
+            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\r
+        exist for 1Line (simplex) and 2Lines (full duplex) modes.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Transmit an amount of data in blocking mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pData pointer to data buffer\r
+  * @param  Size amount of data to be sent\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+  uint16_t initial_TxXferCount;\r
+\r
+  /* Check Direction parameter */\r
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  /* Init tickstart for timeout management*/\r
+  tickstart = HAL_GetTick();\r
+  initial_TxXferCount = Size;\r
+\r
+  if (hspi->State != HAL_SPI_STATE_READY)\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pTxBuffPtr  = (uint8_t *)pData;\r
+  hspi->TxXferSize  = Size;\r
+  hspi->TxXferCount = Size;\r
+\r
+  /*Init field not used in handle to zero */\r
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r
+  hspi->RxXferSize  = 0U;\r
+  hspi->RxXferCount = 0U;\r
+  hspi->TxISR       = NULL;\r
+  hspi->RxISR       = NULL;\r
+\r
+  /* Configure communication direction : 1Line */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+  {\r
+    SPI_1LINE_TX(hspi);\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+  /* Transmit data in 16 Bit mode */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
+    {\r
+      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+      hspi->pTxBuffPtr += sizeof(uint16_t);\r
+      hspi->TxXferCount--;\r
+    }\r
+    /* Transmit data in 16 Bit mode */\r
+    while (hspi->TxXferCount > 0U)\r
+    {\r
+      /* Wait until TXE flag is set to send data */\r
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r
+      {\r
+        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+        hspi->pTxBuffPtr += sizeof(uint16_t);\r
+        hspi->TxXferCount--;\r
+      }\r
+      else\r
+      {\r
+        /* Timeout management */\r
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
+        {\r
+          errorcode = HAL_TIMEOUT;\r
+          goto error;\r
+        }\r
+      }\r
+    }\r
+  }\r
+  /* Transmit data in 8 Bit mode */\r
+  else\r
+  {\r
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
+    {\r
+      if (hspi->TxXferCount > 1U)\r
+      {\r
+        /* write on the data register in packing mode */\r
+        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+        hspi->pTxBuffPtr += sizeof(uint16_t);\r
+        hspi->TxXferCount -= 2U;\r
+      }\r
+      else\r
+      {\r
+        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\r
+        hspi->pTxBuffPtr ++;\r
+        hspi->TxXferCount--;\r
+      }\r
+    }\r
+    while (hspi->TxXferCount > 0U)\r
+    {\r
+      /* Wait until TXE flag is set to send data */\r
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r
+      {\r
+        if (hspi->TxXferCount > 1U)\r
+        {\r
+          /* write on the data register in packing mode */\r
+          hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+          hspi->pTxBuffPtr += sizeof(uint16_t);\r
+          hspi->TxXferCount -= 2U;\r
+        }\r
+        else\r
+        {\r
+          *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\r
+          hspi->pTxBuffPtr++;\r
+          hspi->TxXferCount--;\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Timeout management */\r
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
+        {\r
+          errorcode = HAL_TIMEOUT;\r
+          goto error;\r
+        }\r
+      }\r
+    }\r
+  }\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Enable CRC Transmission */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Check the end of the transaction */\r
+  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+  }\r
+\r
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+  {\r
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+  }\r
+\r
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+  {\r
+    errorcode = HAL_ERROR;\r
+  }\r
+\r
+error:\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Receive an amount of data in blocking mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pData pointer to data buffer\r
+  * @param  Size amount of data to be received\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint32_t tickstart;\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
+  {\r
+    hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
+    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);\r
+  }\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  /* Init tickstart for timeout management*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  if (hspi->State != HAL_SPI_STATE_READY)\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pRxBuffPtr  = (uint8_t *)pData;\r
+  hspi->RxXferSize  = Size;\r
+  hspi->RxXferCount = Size;\r
+\r
+  /*Init field not used in handle to zero */\r
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r
+  hspi->TxXferSize  = 0U;\r
+  hspi->TxXferCount = 0U;\r
+  hspi->RxISR       = NULL;\r
+  hspi->TxISR       = NULL;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SPI_RESET_CRC(hspi);\r
+    /* this is done to handle the CRCNEXT before the latest data */\r
+    hspi->RxXferCount--;\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Set the Rx Fifo threshold */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 16bit */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+  else\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 8bit */\r
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+\r
+  /* Configure communication direction: 1Line */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+  {\r
+    SPI_1LINE_RX(hspi);\r
+  }\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+  /* Receive data in 8 Bit mode */\r
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)\r
+  {\r
+    /* Transfer loop */\r
+    while (hspi->RxXferCount > 0U)\r
+    {\r
+      /* Check the RXNE flag */\r
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r
+      {\r
+        /* read the received data */\r
+        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
+        hspi->pRxBuffPtr += sizeof(uint8_t);\r
+        hspi->RxXferCount--;\r
+      }\r
+      else\r
+      {\r
+        /* Timeout management */\r
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
+        {\r
+          errorcode = HAL_TIMEOUT;\r
+          goto error;\r
+        }\r
+      }\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Transfer loop */\r
+    while (hspi->RxXferCount > 0U)\r
+    {\r
+      /* Check the RXNE flag */\r
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r
+      {\r
+        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
+        hspi->pRxBuffPtr += sizeof(uint16_t);\r
+        hspi->RxXferCount--;\r
+      }\r
+      else\r
+      {\r
+        /* Timeout management */\r
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
+        {\r
+          errorcode = HAL_TIMEOUT;\r
+          goto error;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Handle the CRC Transmission */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    /* freeze the CRC before the latest data */\r
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+\r
+    /* Read the latest data */\r
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* the latest data has not been received */\r
+      errorcode = HAL_TIMEOUT;\r
+      goto error;\r
+    }\r
+\r
+    /* Receive last data in 16 Bit mode */\r
+    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+    {\r
+      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
+    }\r
+    /* Receive last data in 8 Bit mode */\r
+    else\r
+    {\r
+      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
+    }\r
+\r
+    /* Wait the CRC data */\r
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+      errorcode = HAL_TIMEOUT;\r
+      goto error;\r
+    }\r
+\r
+    /* Read CRC to Flush DR and RXNE flag */\r
+    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
+    {\r
+      /* Read 16bit CRC */\r
+      READ_REG(hspi->Instance->DR);\r
+    }\r
+    else\r
+    {\r
+      /* Read 8bit CRC */\r
+      READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+\r
+      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+      {\r
+        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          /* Error on the CRC reception */\r
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+          errorcode = HAL_TIMEOUT;\r
+          goto error;\r
+        }\r
+        /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
+        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+      }\r
+    }\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Check the end of the transaction */\r
+  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Check if CRC error occurred */\r
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+  {\r
+    errorcode = HAL_ERROR;\r
+  }\r
+\r
+error :\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Transmit and Receive an amount of data in blocking mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pTxData pointer to transmission data buffer\r
+  * @param  pRxData pointer to reception data buffer\r
+  * @param  Size amount of data to be sent and received\r
+  * @param  Timeout Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\r
+                                          uint32_t Timeout)\r
+{\r
+  uint16_t             initial_TxXferCount;\r
+  uint16_t             initial_RxXferCount;\r
+  uint32_t             tmp_mode;\r
+  HAL_SPI_StateTypeDef tmp_state;\r
+  uint32_t             tickstart;\r
+#if (USE_SPI_CRC != 0U)\r
+  uint32_t             spi_cr1;\r
+  uint32_t             spi_cr2;\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Variable used to alternate Rx and Tx during transfer */\r
+  uint32_t             txallowed = 1U;\r
+  HAL_StatusTypeDef    errorcode = HAL_OK;\r
+\r
+  /* Check Direction parameter */\r
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  /* Init tickstart for timeout management*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Init temporary variables */\r
+  tmp_state           = hspi->State;\r
+  tmp_mode            = hspi->Init.Mode;\r
+  initial_TxXferCount = Size;\r
+  initial_RxXferCount = Size;\r
+#if (USE_SPI_CRC != 0U)\r
+  spi_cr1             = READ_REG(hspi->Instance->CR1);\r
+  spi_cr2             = READ_REG(hspi->Instance->CR2);\r
+#endif /* USE_SPI_CRC */\r
+\r
+  if (!((tmp_state == HAL_SPI_STATE_READY) || \\r
+        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
+  {\r
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r
+  hspi->RxXferCount = Size;\r
+  hspi->RxXferSize  = Size;\r
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r
+  hspi->TxXferCount = Size;\r
+  hspi->TxXferSize  = Size;\r
+\r
+  /*Init field not used in handle to zero */\r
+  hspi->RxISR       = NULL;\r
+  hspi->TxISR       = NULL;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Set the Rx Fifo threshold */\r
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))\r
+  {\r
+    /* Set fiforxthreshold according the reception data length: 16bit */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+  else\r
+  {\r
+    /* Set fiforxthreshold according the reception data length: 8bit */\r
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+  /* Transmit and Receive data in 16 Bit mode */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
+    {\r
+      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+      hspi->pTxBuffPtr += sizeof(uint16_t);\r
+      hspi->TxXferCount--;\r
+    }\r
+    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r
+    {\r
+      /* Check TXE flag */\r
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\r
+      {\r
+        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+        hspi->pTxBuffPtr += sizeof(uint16_t);\r
+        hspi->TxXferCount--;\r
+        /* Next Data is a reception (Rx). Tx not allowed */\r
+        txallowed = 0U;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+        /* Enable CRC Transmission */\r
+        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+        {\r
+          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
+          if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
+          {\r
+            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
+          }\r
+          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+        }\r
+#endif /* USE_SPI_CRC */\r
+      }\r
+\r
+      /* Check RXNE flag */\r
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\r
+      {\r
+        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
+        hspi->pRxBuffPtr += sizeof(uint16_t);\r
+        hspi->RxXferCount--;\r
+        /* Next Data is a Transmission (Tx). Tx is allowed */\r
+        txallowed = 1U;\r
+      }\r
+      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))\r
+      {\r
+        errorcode = HAL_TIMEOUT;\r
+        goto error;\r
+      }\r
+    }\r
+  }\r
+  /* Transmit and Receive data in 8 Bit mode */\r
+  else\r
+  {\r
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
+    {\r
+      if (hspi->TxXferCount > 1U)\r
+      {\r
+        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+        hspi->pTxBuffPtr += sizeof(uint16_t);\r
+        hspi->TxXferCount -= 2U;\r
+      }\r
+      else\r
+      {\r
+        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
+        hspi->pTxBuffPtr++;\r
+        hspi->TxXferCount--;\r
+      }\r
+    }\r
+    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r
+    {\r
+      /* Check TXE flag */\r
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\r
+      {\r
+        if (hspi->TxXferCount > 1U)\r
+        {\r
+          hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+          hspi->pTxBuffPtr += sizeof(uint16_t);\r
+          hspi->TxXferCount -= 2U;\r
+        }\r
+        else\r
+        {\r
+          *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
+          hspi->pTxBuffPtr++;\r
+          hspi->TxXferCount--;\r
+        }\r
+        /* Next Data is a reception (Rx). Tx not allowed */\r
+        txallowed = 0U;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+        /* Enable CRC Transmission */\r
+        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+        {\r
+          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
+          if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
+          {\r
+            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
+          }\r
+          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+        }\r
+#endif /* USE_SPI_CRC */\r
+      }\r
+\r
+      /* Wait until RXNE flag is reset */\r
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\r
+      {\r
+        if (hspi->RxXferCount > 1U)\r
+        {\r
+          *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
+          hspi->pRxBuffPtr += sizeof(uint16_t);\r
+          hspi->RxXferCount -= 2U;\r
+          if (hspi->RxXferCount <= 1U)\r
+          {\r
+            /* Set RX Fifo threshold before to switch on 8 bit data size */\r
+            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+          }\r
+        }\r
+        else\r
+        {\r
+          (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
+          hspi->pRxBuffPtr++;\r
+          hspi->RxXferCount--;\r
+        }\r
+        /* Next Data is a Transmission (Tx). Tx is allowed */\r
+        txallowed = 1U;\r
+      }\r
+      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))\r
+      {\r
+        errorcode = HAL_TIMEOUT;\r
+        goto error;\r
+      }\r
+    }\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Read CRC from DR to close CRC calculation process */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    /* Wait until TXE flag */\r
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
+    {\r
+      /* Error on the CRC reception */\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+      errorcode = HAL_TIMEOUT;\r
+      goto error;\r
+    }\r
+    /* Read CRC */\r
+    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
+    {\r
+      /* Read 16bit CRC */\r
+      READ_REG(hspi->Instance->DR);\r
+    }\r
+    else\r
+    {\r
+      /* Read 8bit CRC */\r
+      READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+\r
+      if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+      {\r
+        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
+        {\r
+          /* Error on the CRC reception */\r
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+          errorcode = HAL_TIMEOUT;\r
+          goto error;\r
+        }\r
+        /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
+        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Check if CRC error occurred */\r
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+    /* Clear CRC Flag */\r
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+\r
+    errorcode = HAL_ERROR;\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Check the end of the transaction */\r
+  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+  }\r
+\r
+error :\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pData pointer to data buffer\r
+  * @param  Size amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+  /* Check Direction parameter */\r
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  if ((pData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  if (hspi->State != HAL_SPI_STATE_READY)\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pTxBuffPtr  = (uint8_t *)pData;\r
+  hspi->TxXferSize  = Size;\r
+  hspi->TxXferCount = Size;\r
+\r
+  /* Init field not used in handle to zero */\r
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r
+  hspi->RxXferSize  = 0U;\r
+  hspi->RxXferCount = 0U;\r
+  hspi->RxISR       = NULL;\r
+\r
+  /* Set the function for IT treatment */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    hspi->TxISR = SPI_TxISR_16BIT;\r
+  }\r
+  else\r
+  {\r
+    hspi->TxISR = SPI_TxISR_8BIT;\r
+  }\r
+\r
+  /* Configure communication direction : 1Line */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+  {\r
+    SPI_1LINE_TX(hspi);\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Enable TXE and ERR interrupt */\r
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
+\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+error :\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pData pointer to data buffer\r
+  * @param  Size amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r
+  {\r
+    hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
+    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);\r
+  }\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  if (hspi->State != HAL_SPI_STATE_READY)\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pRxBuffPtr  = (uint8_t *)pData;\r
+  hspi->RxXferSize  = Size;\r
+  hspi->RxXferCount = Size;\r
+\r
+  /* Init field not used in handle to zero */\r
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r
+  hspi->TxXferSize  = 0U;\r
+  hspi->TxXferCount = 0U;\r
+  hspi->TxISR       = NULL;\r
+\r
+  /* Check the data size to adapt Rx threshold and the set the function for IT treatment */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 16 bit */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+    hspi->RxISR = SPI_RxISR_16BIT;\r
+  }\r
+  else\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 8 bit */\r
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+    hspi->RxISR = SPI_RxISR_8BIT;\r
+  }\r
+\r
+  /* Configure communication direction : 1Line */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+  {\r
+    SPI_1LINE_RX(hspi);\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    hspi->CRCSize = 1U;\r
+    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+    {\r
+      hspi->CRCSize = 2U;\r
+    }\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+  else\r
+  {\r
+    hspi->CRCSize = 0U;\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Enable TXE and ERR interrupt */\r
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+  /* Note : The SPI must be enabled after unlocking current process\r
+            to avoid the risk of SPI interrupt handle execution before current\r
+            process unlock */\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+error :\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pTxData pointer to transmission data buffer\r
+  * @param  pRxData pointer to reception data buffer\r
+  * @param  Size amount of data to be sent and received\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+  uint32_t             tmp_mode;\r
+  HAL_SPI_StateTypeDef tmp_state;\r
+  HAL_StatusTypeDef    errorcode = HAL_OK;\r
+\r
+  /* Check Direction parameter */\r
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  /* Init temporary variables */\r
+  tmp_state           = hspi->State;\r
+  tmp_mode            = hspi->Init.Mode;\r
+\r
+  if (!((tmp_state == HAL_SPI_STATE_READY) || \\r
+        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
+  {\r
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r
+  hspi->TxXferSize  = Size;\r
+  hspi->TxXferCount = Size;\r
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r
+  hspi->RxXferSize  = Size;\r
+  hspi->RxXferCount = Size;\r
+\r
+  /* Set the function for IT treatment */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    hspi->RxISR     = SPI_2linesRxISR_16BIT;\r
+    hspi->TxISR     = SPI_2linesTxISR_16BIT;\r
+  }\r
+  else\r
+  {\r
+    hspi->RxISR     = SPI_2linesRxISR_8BIT;\r
+    hspi->TxISR     = SPI_2linesTxISR_8BIT;\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    hspi->CRCSize = 1U;\r
+    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+    {\r
+      hspi->CRCSize = 2U;\r
+    }\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+  else\r
+  {\r
+    hspi->CRCSize = 0U;\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Check if packing mode is enabled and if there is more than 2 data to receive */\r
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 16 bit */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+  else\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 8 bit */\r
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+\r
+  /* Enable TXE, RXNE and ERR interrupt */\r
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+error :\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pData pointer to data buffer\r
+  * @param  Size amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+  /* Check tx dma handle */\r
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
+\r
+  /* Check Direction parameter */\r
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  if (hspi->State != HAL_SPI_STATE_READY)\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pTxBuffPtr  = (uint8_t *)pData;\r
+  hspi->TxXferSize  = Size;\r
+  hspi->TxXferCount = Size;\r
+\r
+  /* Init field not used in handle to zero */\r
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r
+  hspi->TxISR       = NULL;\r
+  hspi->RxISR       = NULL;\r
+  hspi->RxXferSize  = 0U;\r
+  hspi->RxXferCount = 0U;\r
+\r
+  /* Configure communication direction : 1Line */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+  {\r
+    SPI_1LINE_TX(hspi);\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Set the SPI TxDMA Half transfer complete callback */\r
+  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\r
+\r
+  /* Set the SPI TxDMA transfer complete callback */\r
+  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\r
+\r
+  /* Set the DMA error callback */\r
+  hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
+\r
+  /* Set the DMA AbortCpltCallback */\r
+  hspi->hdmatx->XferAbortCallback = NULL;\r
+\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+  /* Packing mode is enabled only if the DMA setting is HALWORD */\r
+  if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r
+  {\r
+    /* Check the even/odd of the data size + crc if enabled */\r
+    if ((hspi->TxXferCount & 0x1U) == 0U)\r
+    {\r
+      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+      hspi->TxXferCount = (hspi->TxXferCount >> 1U);\r
+    }\r
+    else\r
+    {\r
+      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+      hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r
+    }\r
+  }\r
+\r
+  /* Enable the Tx DMA Stream/Channel */\r
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))\r
+  {\r
+    /* Update SPI error code */\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
+    errorcode = HAL_ERROR;\r
+\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+    goto error;\r
+  }\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+  /* Enable the SPI Error Interrupt Bit */\r
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
+\r
+  /* Enable Tx DMA Request */\r
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+error :\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Receive an amount of data in non-blocking mode with DMA.\r
+  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pData pointer to data buffer\r
+  * @note   When the CRC feature is enabled the pData Length must be Size + 1.\r
+  * @param  Size amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+  /* Check rx dma handle */\r
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\r
+\r
+  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r
+  {\r
+    hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+\r
+    /* Check tx dma handle */\r
+    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
+\r
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
+    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);\r
+  }\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  if (hspi->State != HAL_SPI_STATE_READY)\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pRxBuffPtr  = (uint8_t *)pData;\r
+  hspi->RxXferSize  = Size;\r
+  hspi->RxXferCount = Size;\r
+\r
+  /*Init field not used in handle to zero */\r
+  hspi->RxISR       = NULL;\r
+  hspi->TxISR       = NULL;\r
+  hspi->TxXferSize  = 0U;\r
+  hspi->TxXferCount = 0U;\r
+\r
+  /* Configure communication direction : 1Line */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+  {\r
+    SPI_1LINE_RX(hspi);\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 16bit */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+  else\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 8bit */\r
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+\r
+    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+    {\r
+      /* Set RX Fifo threshold according the reception data length: 16bit */\r
+      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+\r
+      if ((hspi->RxXferCount & 0x1U) == 0x0U)\r
+      {\r
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+        hspi->RxXferCount = hspi->RxXferCount >> 1U;\r
+      }\r
+      else\r
+      {\r
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Set the SPI RxDMA Half transfer complete callback */\r
+  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
+\r
+  /* Set the SPI Rx DMA transfer complete callback */\r
+  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
+\r
+  /* Set the DMA error callback */\r
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
+\r
+  /* Set the DMA AbortCpltCallback */\r
+  hspi->hdmarx->XferAbortCallback = NULL;\r
+\r
+  /* Enable the Rx DMA Stream/Channel  */\r
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))\r
+  {\r
+    /* Update SPI error code */\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
+    errorcode = HAL_ERROR;\r
+\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+    goto error;\r
+  }\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+\r
+  /* Enable the SPI Error Interrupt Bit */\r
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
+\r
+  /* Enable Rx DMA Request */\r
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
+\r
+error:\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  pTxData pointer to transmission data buffer\r
+  * @param  pRxData pointer to reception data buffer\r
+  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1\r
+  * @param  Size amount of data to be sent\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r
+                                              uint16_t Size)\r
+{\r
+  uint32_t             tmp_mode;\r
+  HAL_SPI_StateTypeDef tmp_state;\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+\r
+  /* Check rx & tx dma handles */\r
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\r
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
+\r
+  /* Check Direction parameter */\r
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  /* Init temporary variables */\r
+  tmp_state           = hspi->State;\r
+  tmp_mode            = hspi->Init.Mode;\r
+\r
+  if (!((tmp_state == HAL_SPI_STATE_READY) ||\r
+        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
+  {\r
+    errorcode = HAL_BUSY;\r
+    goto error;\r
+  }\r
+\r
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+  {\r
+    errorcode = HAL_ERROR;\r
+    goto error;\r
+  }\r
+\r
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
+  {\r
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+  }\r
+\r
+  /* Set the transaction information */\r
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r
+  hspi->TxXferSize  = Size;\r
+  hspi->TxXferCount = Size;\r
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r
+  hspi->RxXferSize  = Size;\r
+  hspi->RxXferCount = Size;\r
+\r
+  /* Init field not used in handle to zero */\r
+  hspi->RxISR       = NULL;\r
+  hspi->TxISR       = NULL;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Reset CRC Calculation */\r
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+  {\r
+    SPI_RESET_CRC(hspi);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  /* Reset the threshold bit */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);\r
+\r
+  /* The packing mode management is enabled by the DMA settings according the spi data size */\r
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+  {\r
+    /* Set fiforxthreshold according the reception data length: 16bit */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+  }\r
+  else\r
+  {\r
+    /* Set RX Fifo threshold according the reception data length: 8bit */\r
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+\r
+    if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+    {\r
+      if ((hspi->TxXferSize & 0x1U) == 0x0U)\r
+      {\r
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+        hspi->TxXferCount = hspi->TxXferCount >> 1U;\r
+      }\r
+      else\r
+      {\r
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+        hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r
+      }\r
+    }\r
+\r
+    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+    {\r
+      /* Set RX Fifo threshold according the reception data length: 16bit */\r
+      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+\r
+      if ((hspi->RxXferCount & 0x1U) == 0x0U)\r
+      {\r
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+        hspi->RxXferCount = hspi->RxXferCount >> 1U;\r
+      }\r
+      else\r
+      {\r
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */\r
+  if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r
+  {\r
+    /* Set the SPI Rx DMA Half transfer complete callback */\r
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
+    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;\r
+  }\r
+  else\r
+  {\r
+    /* Set the SPI Tx/Rx DMA Half transfer complete callback */\r
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r
+    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;\r
+  }\r
+\r
+  /* Set the DMA error callback */\r
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
+\r
+  /* Set the DMA AbortCpltCallback */\r
+  hspi->hdmarx->XferAbortCallback = NULL;\r
+\r
+  /* Enable the Rx DMA Stream/Channel  */\r
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))\r
+  {\r
+    /* Update SPI error code */\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
+    errorcode = HAL_ERROR;\r
+\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+    goto error;\r
+  }\r
+\r
+  /* Enable Rx DMA Request */\r
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
+\r
+  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r
+  is performed in DMA reception complete callback  */\r
+  hspi->hdmatx->XferHalfCpltCallback = NULL;\r
+  hspi->hdmatx->XferCpltCallback     = NULL;\r
+  hspi->hdmatx->XferErrorCallback    = NULL;\r
+  hspi->hdmatx->XferAbortCallback    = NULL;\r
+\r
+  /* Enable the Tx DMA Stream/Channel  */\r
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))\r
+  {\r
+    /* Update SPI error code */\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
+    errorcode = HAL_ERROR;\r
+\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+    goto error;\r
+  }\r
+\r
+  /* Check if the SPI is already enabled */\r
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+  {\r
+    /* Enable SPI peripheral */\r
+    __HAL_SPI_ENABLE(hspi);\r
+  }\r
+  /* Enable the SPI Error Interrupt Bit */\r
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
+\r
+  /* Enable Tx DMA Request */\r
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+error :\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing transfer (blocking mode).\r
+  * @param  hspi SPI handle.\r
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r
+  *         started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable SPI Interrupts (depending of transfer direction)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+  * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)\r
+{\r
+  HAL_StatusTypeDef errorcode;\r
+  __IO uint32_t count, resetcount;\r
+\r
+  /* Initialized local variable  */\r
+  errorcode = HAL_OK;\r
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
+  count = resetcount;\r
+\r
+  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r
+\r
+  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r
+  {\r
+    hspi->TxISR = SPI_AbortTx_ISR;\r
+    /* Wait HAL_SPI_STATE_ABORT state */\r
+    do\r
+    {\r
+      if (count == 0U)\r
+      {\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+        break;\r
+      }\r
+      count--;\r
+    }\r
+    while (hspi->State != HAL_SPI_STATE_ABORT);\r
+    /* Reset Timeout Counter */\r
+    count = resetcount;\r
+  }\r
+\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
+  {\r
+    hspi->RxISR = SPI_AbortRx_ISR;\r
+    /* Wait HAL_SPI_STATE_ABORT state */\r
+    do\r
+    {\r
+      if (count == 0U)\r
+      {\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+        break;\r
+      }\r
+      count--;\r
+    }\r
+    while (hspi->State != HAL_SPI_STATE_ABORT);\r
+    /* Reset Timeout Counter */\r
+    count = resetcount;\r
+  }\r
+\r
+  /* Disable the SPI DMA Tx request if enabled */\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
+  {\r
+    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */\r
+    if (hspi->hdmatx != NULL)\r
+    {\r
+      /* Set the SPI DMA Abort callback :\r
+      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r
+      hspi->hdmatx->XferAbortCallback = NULL;\r
+\r
+      /* Abort DMA Tx Handle linked to SPI Peripheral */\r
+      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)\r
+      {\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+\r
+      /* Disable Tx DMA Request */\r
+      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));\r
+\r
+      if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+      {\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+\r
+      /* Disable SPI Peripheral */\r
+      __HAL_SPI_DISABLE(hspi);\r
+\r
+      /* Empty the FRLVL fifo */\r
+      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+      {\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Disable the SPI DMA Rx request if enabled */\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
+  {\r
+    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */\r
+    if (hspi->hdmarx != NULL)\r
+    {\r
+      /* Set the SPI DMA Abort callback :\r
+      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r
+      hspi->hdmarx->XferAbortCallback = NULL;\r
+\r
+      /* Abort DMA Rx Handle linked to SPI Peripheral */\r
+      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)\r
+      {\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+\r
+      /* Disable peripheral */\r
+      __HAL_SPI_DISABLE(hspi);\r
+\r
+      /* Control the BSY flag */\r
+      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+      {\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+\r
+      /* Empty the FRLVL fifo */\r
+      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+      {\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+\r
+      /* Disable Rx DMA Request */\r
+      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));\r
+    }\r
+  }\r
+  /* Reset Tx and Rx transfer counters */\r
+  hspi->RxXferCount = 0U;\r
+  hspi->TxXferCount = 0U;\r
+\r
+  /* Check error during Abort procedure */\r
+  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r
+  {\r
+    /* return HAL_Error in case of error during Abort procedure */\r
+    errorcode = HAL_ERROR;\r
+  }\r
+  else\r
+  {\r
+    /* Reset errorCode */\r
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+  }\r
+\r
+  /* Clear the Error flags in the SR register */\r
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+  __HAL_SPI_CLEAR_FREFLAG(hspi);\r
+\r
+  /* Restore hspi->state to ready */\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing transfer (Interrupt mode).\r
+  * @param  hspi SPI handle.\r
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r
+  *         started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable SPI Interrupts (depending of transfer direction)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  *           - At abort completion, call user abort complete callback\r
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
+  * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)\r
+{\r
+  HAL_StatusTypeDef errorcode;\r
+  uint32_t abortcplt ;\r
+  __IO uint32_t count, resetcount;\r
+\r
+  /* Initialized local variable  */\r
+  errorcode = HAL_OK;\r
+  abortcplt = 1U;\r
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
+  count = resetcount;\r
+\r
+  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r
+\r
+  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r
+  {\r
+    hspi->TxISR = SPI_AbortTx_ISR;\r
+    /* Wait HAL_SPI_STATE_ABORT state */\r
+    do\r
+    {\r
+      if (count == 0U)\r
+      {\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+        break;\r
+      }\r
+      count--;\r
+    }\r
+    while (hspi->State != HAL_SPI_STATE_ABORT);\r
+    /* Reset Timeout Counter */\r
+    count = resetcount;\r
+  }\r
+\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
+  {\r
+    hspi->RxISR = SPI_AbortRx_ISR;\r
+    /* Wait HAL_SPI_STATE_ABORT state */\r
+    do\r
+    {\r
+      if (count == 0U)\r
+      {\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+        break;\r
+      }\r
+      count--;\r
+    }\r
+    while (hspi->State != HAL_SPI_STATE_ABORT);\r
+    /* Reset Timeout Counter */\r
+    count = resetcount;\r
+  }\r
+\r
+  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised\r
+     before any call to DMA Abort functions */\r
+  /* DMA Tx Handle is valid */\r
+  if (hspi->hdmatx != NULL)\r
+  {\r
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r
+       Otherwise, set it to NULL */\r
+    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
+    {\r
+      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;\r
+    }\r
+    else\r
+    {\r
+      hspi->hdmatx->XferAbortCallback = NULL;\r
+    }\r
+  }\r
+  /* DMA Rx Handle is valid */\r
+  if (hspi->hdmarx != NULL)\r
+  {\r
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r
+       Otherwise, set it to NULL */\r
+    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
+    {\r
+      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;\r
+    }\r
+    else\r
+    {\r
+      hspi->hdmarx->XferAbortCallback = NULL;\r
+    }\r
+  }\r
+\r
+  /* Disable the SPI DMA Tx request if enabled */\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
+  {\r
+    /* Abort the SPI DMA Tx Stream/Channel */\r
+    if (hspi->hdmatx != NULL)\r
+    {\r
+      /* Abort DMA Tx Handle linked to SPI Peripheral */\r
+      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\r
+      {\r
+        hspi->hdmatx->XferAbortCallback = NULL;\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+      else\r
+      {\r
+        abortcplt = 0U;\r
+      }\r
+    }\r
+  }\r
+  /* Disable the SPI DMA Rx request if enabled */\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
+  {\r
+    /* Abort the SPI DMA Rx Stream/Channel */\r
+    if (hspi->hdmarx != NULL)\r
+    {\r
+      /* Abort DMA Rx Handle linked to SPI Peripheral */\r
+      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)\r
+      {\r
+        hspi->hdmarx->XferAbortCallback = NULL;\r
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+      }\r
+      else\r
+      {\r
+        abortcplt = 0U;\r
+      }\r
+    }\r
+  }\r
+\r
+  if (abortcplt == 1U)\r
+  {\r
+    /* Reset Tx and Rx transfer counters */\r
+    hspi->RxXferCount = 0U;\r
+    hspi->TxXferCount = 0U;\r
+\r
+    /* Check error during Abort procedure */\r
+    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r
+    {\r
+      /* return HAL_Error in case of error during Abort procedure */\r
+      errorcode = HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      /* Reset errorCode */\r
+      hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+    }\r
+\r
+    /* Clear the Error flags in the SR register */\r
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+    __HAL_SPI_CLEAR_FREFLAG(hspi);\r
+\r
+    /* Restore hspi->State to Ready */\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+\r
+    /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+    hspi->AbortCpltCallback(hspi);\r
+#else\r
+    HAL_SPI_AbortCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Pause the DMA Transfer.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified SPI module.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  /* Disable the SPI DMA Tx & Rx requests */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Resume the DMA Transfer.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified SPI module.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Process Locked */\r
+  __HAL_LOCK(hspi);\r
+\r
+  /* Enable the SPI DMA Tx & Rx requests */\r
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(hspi);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stop the DMA Transfer.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified SPI module.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\r
+{\r
+  HAL_StatusTypeDef errorcode = HAL_OK;\r
+  /* The Lock is not implemented on this API to allow the user application\r
+     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\r
+     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r
+     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\r
+     */\r
+\r
+  /* Abort the SPI DMA tx Stream/Channel  */\r
+  if (hspi->hdmatx != NULL)\r
+  {\r
+    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
+      errorcode = HAL_ERROR;\r
+    }\r
+  }\r
+  /* Abort the SPI DMA rx Stream/Channel  */\r
+  if (hspi->hdmarx != NULL)\r
+  {\r
+    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
+      errorcode = HAL_ERROR;\r
+    }\r
+  }\r
+\r
+  /* Disable the SPI DMA Tx & Rx requests */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+  return errorcode;\r
+}\r
+\r
+/**\r
+  * @brief  Handle SPI interrupt request.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified SPI module.\r
+  * @retval None\r
+  */\r
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\r
+{\r
+  uint32_t itsource = hspi->Instance->CR2;\r
+  uint32_t itflag   = hspi->Instance->SR;\r
+\r
+  /* SPI in mode Receiver ----------------------------------------------------*/\r
+  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&\r
+      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))\r
+  {\r
+    hspi->RxISR(hspi);\r
+    return;\r
+  }\r
+\r
+  /* SPI in mode Transmitter -------------------------------------------------*/\r
+  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))\r
+  {\r
+    hspi->TxISR(hspi);\r
+    return;\r
+  }\r
+\r
+  /* SPI in Error Treatment --------------------------------------------------*/\r
+  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))\r
+  {\r
+    /* SPI Overrun error interrupt occurred ----------------------------------*/\r
+    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)\r
+    {\r
+      if (hspi->State != HAL_SPI_STATE_BUSY_TX)\r
+      {\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);\r
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+      }\r
+      else\r
+      {\r
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+        return;\r
+      }\r
+    }\r
+\r
+    /* SPI Mode Fault error interrupt occurred -------------------------------*/\r
+    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);\r
+      __HAL_SPI_CLEAR_MODFFLAG(hspi);\r
+    }\r
+\r
+    /* SPI Frame error interrupt occurred ------------------------------------*/\r
+    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);\r
+      __HAL_SPI_CLEAR_FREFLAG(hspi);\r
+    }\r
+\r
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+    {\r
+      /* Disable all interrupts */\r
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);\r
+\r
+      hspi->State = HAL_SPI_STATE_READY;\r
+      /* Disable the SPI DMA requests if enabled */\r
+      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))\r
+      {\r
+        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\r
+\r
+        /* Abort the SPI DMA Rx channel */\r
+        if (hspi->hdmarx != NULL)\r
+        {\r
+          /* Set the SPI DMA Abort callback :\r
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
+          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r
+          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))\r
+          {\r
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+          }\r
+        }\r
+        /* Abort the SPI DMA Tx channel */\r
+        if (hspi->hdmatx != NULL)\r
+        {\r
+          /* Set the SPI DMA Abort callback :\r
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
+          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r
+          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))\r
+          {\r
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+          }\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+        hspi->ErrorCallback(hspi);\r
+#else\r
+        HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+      }\r
+    }\r
+    return;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Tx Transfer completed callback.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_TxCpltCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Rx Transfer completed callback.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_RxCpltCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Tx and Rx Transfer completed callback.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_TxRxCpltCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Tx Half Transfer completed callback.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Rx Half Transfer completed callback.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Tx and Rx Half Transfer callback.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  SPI error callback.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_ErrorCallback should be implemented in the user file\r
+   */\r
+  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\r
+            and user can use HAL_SPI_GetError() API to check the latest error occurred\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  SPI Abort Complete callback.\r
+  * @param  hspi SPI handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(hspi);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_SPI_AbortCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r
+  * @brief   SPI control functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to control the SPI.\r
+     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\r
+     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Return the SPI handle state.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval SPI state\r
+  */\r
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Return SPI handle state */\r
+  return hspi->State;\r
+}\r
+\r
+/**\r
+  * @brief  Return the SPI error code.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval SPI error code in bitmap format\r
+  */\r
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Return SPI ErrorCode */\r
+  return hspi->ErrorCode;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup SPI_Private_Functions\r
+  * @brief   Private functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  DMA SPI transmit process complete callback.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA module.\r
+  * @retval None\r
+  */\r
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+  uint32_t tickstart;\r
+\r
+  /* Init tickstart for timeout management*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* DMA Normal Mode */\r
+  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
+  {\r
+    /* Disable ERR interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
+\r
+    /* Disable Tx DMA Request */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+    /* Check the end of the transaction */\r
+    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+    }\r
+\r
+    /* Clear overrun flag in 2 Lines communication mode because received data is not read */\r
+    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+    {\r
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+    }\r
+\r
+    hspi->TxXferCount = 0U;\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+\r
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+    {\r
+      /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+      hspi->ErrorCallback(hspi);\r
+#else\r
+      HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+      return;\r
+    }\r
+  }\r
+  /* Call user Tx complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->TxCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_TxCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI receive process complete callback.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA module.\r
+  * @retval None\r
+  */\r
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+  uint32_t tickstart;\r
+\r
+  /* Init tickstart for timeout management*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* DMA Normal Mode */\r
+  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
+  {\r
+    /* Disable ERR interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+    /* CRC handling */\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      /* Wait until RXNE flag */\r
+      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+      {\r
+        /* Error on the CRC reception */\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+      }\r
+      /* Read CRC */\r
+      if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+      {\r
+        /* Read 16bit CRC */\r
+        READ_REG(hspi->Instance->DR);\r
+      }\r
+      else\r
+      {\r
+        /* Read 8bit CRC */\r
+        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+\r
+        if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+        {\r
+          if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+          {\r
+            /* Error on the CRC reception */\r
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+          }\r
+          /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
+          READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+        }\r
+      }\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+    /* Check the end of the transaction */\r
+    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+    {\r
+      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
+    }\r
+\r
+    hspi->RxXferCount = 0U;\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+    /* Check if CRC error occurred */\r
+    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+    {\r
+      /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+      hspi->ErrorCallback(hspi);\r
+#else\r
+      HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+      return;\r
+    }\r
+  }\r
+  /* Call user Rx complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->RxCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_RxCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI transmit receive process complete callback.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA module.\r
+  * @retval None\r
+  */\r
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+  uint32_t tickstart;\r
+\r
+  /* Init tickstart for timeout management*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* DMA Normal Mode */\r
+  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
+  {\r
+    /* Disable ERR interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+    /* CRC handling */\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))\r
+      {\r
+        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,\r
+                                          tickstart) != HAL_OK)\r
+        {\r
+          /* Error on the CRC reception */\r
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+        }\r
+        /* Read CRC to Flush DR and RXNE flag */\r
+        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+      }\r
+      else\r
+      {\r
+        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+        {\r
+          /* Error on the CRC reception */\r
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+        }\r
+        /* Read CRC to Flush DR and RXNE flag */\r
+        READ_REG(hspi->Instance->DR);\r
+      }\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    /* Check the end of the transaction */\r
+    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+    }\r
+\r
+    /* Disable Rx/Tx DMA Request */\r
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+    hspi->TxXferCount = 0U;\r
+    hspi->RxXferCount = 0U;\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+    /* Check if CRC error occurred */\r
+    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+    {\r
+      /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+      hspi->ErrorCallback(hspi);\r
+#else\r
+      HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+      return;\r
+    }\r
+  }\r
+  /* Call user TxRx complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->TxRxCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_TxRxCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI half transmit process complete callback.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA module.\r
+  * @retval None\r
+  */\r
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Call user Tx half complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->TxHalfCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_TxHalfCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI half receive process complete callback\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA module.\r
+  * @retval None\r
+  */\r
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Call user Rx half complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->RxHalfCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_RxHalfCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI half transmit receive process complete callback.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA module.\r
+  * @retval None\r
+  */\r
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Call user TxRx half complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->TxRxHalfCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_TxRxHalfCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI communication error callback.\r
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified DMA module.\r
+  * @retval None\r
+  */\r
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Stop the disable DMA transfer on SPI side */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+  /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->ErrorCallback(hspi);\r
+#else\r
+  HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error\r
+  *         (To be called at end of DMA Abort procedure following error occurrence).\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+  hspi->RxXferCount = 0U;\r
+  hspi->TxXferCount = 0U;\r
+\r
+  /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->ErrorCallback(hspi);\r
+#else\r
+  HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI Tx communication abort callback, when initiated by user\r
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).\r
+  * @note   When this callback is executed, User Abort complete call back is called only if no\r
+  *         Abort still ongoing for Rx DMA Handle.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  hspi->hdmatx->XferAbortCallback = NULL;\r
+\r
+  /* Disable Tx DMA Request */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  /* Disable SPI Peripheral */\r
+  __HAL_SPI_DISABLE(hspi);\r
+\r
+  /* Empty the FRLVL fifo */\r
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  /* Check if an Abort process is still ongoing */\r
+  if (hspi->hdmarx != NULL)\r
+  {\r
+    if (hspi->hdmarx->XferAbortCallback != NULL)\r
+    {\r
+      return;\r
+    }\r
+  }\r
+\r
+  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r
+  hspi->RxXferCount = 0U;\r
+  hspi->TxXferCount = 0U;\r
+\r
+  /* Check no error during Abort procedure */\r
+  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r
+  {\r
+    /* Reset errorCode */\r
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+  }\r
+\r
+  /* Clear the Error flags in the SR register */\r
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+  __HAL_SPI_CLEAR_FREFLAG(hspi);\r
+\r
+  /* Restore hspi->State to Ready */\r
+  hspi->State  = HAL_SPI_STATE_READY;\r
+\r
+  /* Call user Abort complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->AbortCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_AbortCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA SPI Rx communication abort callback, when initiated by user\r
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).\r
+  * @note   When this callback is executed, User Abort complete call back is called only if no\r
+  *         Abort still ongoing for Tx DMA Handle.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+  /* Disable SPI Peripheral */\r
+  __HAL_SPI_DISABLE(hspi);\r
+\r
+  hspi->hdmarx->XferAbortCallback = NULL;\r
+\r
+  /* Disable Rx DMA Request */\r
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
+\r
+  /* Control the BSY flag */\r
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  /* Empty the FRLVL fifo */\r
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  /* Check if an Abort process is still ongoing */\r
+  if (hspi->hdmatx != NULL)\r
+  {\r
+    if (hspi->hdmatx->XferAbortCallback != NULL)\r
+    {\r
+      return;\r
+    }\r
+  }\r
+\r
+  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r
+  hspi->RxXferCount = 0U;\r
+  hspi->TxXferCount = 0U;\r
+\r
+  /* Check no error during Abort procedure */\r
+  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r
+  {\r
+    /* Reset errorCode */\r
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+  }\r
+\r
+  /* Clear the Error flags in the SR register */\r
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+  __HAL_SPI_CLEAR_FREFLAG(hspi);\r
+\r
+  /* Restore hspi->State to Ready */\r
+  hspi->State  = HAL_SPI_STATE_READY;\r
+\r
+  /* Call user Abort complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+  hspi->AbortCpltCallback(hspi);\r
+#else\r
+  HAL_SPI_AbortCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Receive data in packing mode */\r
+  if (hspi->RxXferCount > 1U)\r
+  {\r
+    *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
+    hspi->pRxBuffPtr += sizeof(uint16_t);\r
+    hspi->RxXferCount -= 2U;\r
+    if (hspi->RxXferCount == 1U)\r
+    {\r
+      /* Set RX Fifo threshold according the reception data length: 8bit */\r
+      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+    }\r
+  }\r
+  /* Receive data in 8 Bit mode */\r
+  else\r
+  {\r
+    *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);\r
+    hspi->pRxBuffPtr++;\r
+    hspi->RxXferCount--;\r
+  }\r
+\r
+  /* Check end of the reception */\r
+  if (hspi->RxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;\r
+      return;\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    /* Disable RXNE  and ERR interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+    if (hspi->TxXferCount == 0U)\r
+    {\r
+      SPI_CloseRxTx_ISR(hspi);\r
+    }\r
+  }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Read 8bit CRC to flush Data Regsiter */\r
+  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+\r
+  hspi->CRCSize--;\r
+\r
+  /* Check end of the reception */\r
+  if (hspi->CRCSize == 0U)\r
+  {\r
+    /* Disable RXNE and ERR interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+    if (hspi->TxXferCount == 0U)\r
+    {\r
+      SPI_CloseRxTx_ISR(hspi);\r
+    }\r
+  }\r
+}\r
+#endif /* USE_SPI_CRC */\r
+\r
+/**\r
+  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Transmit data in packing Bit mode */\r
+  if (hspi->TxXferCount >= 2U)\r
+  {\r
+    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+    hspi->pTxBuffPtr += sizeof(uint16_t);\r
+    hspi->TxXferCount -= 2U;\r
+  }\r
+  /* Transmit data in 8 Bit mode */\r
+  else\r
+  {\r
+    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
+    hspi->pTxBuffPtr++;\r
+    hspi->TxXferCount--;\r
+  }\r
+\r
+  /* Check the end of the transmission */\r
+  if (hspi->TxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      /* Set CRC Next Bit to send CRC */\r
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+      /* Disable TXE interrupt */\r
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+      return;\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    /* Disable TXE interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+\r
+    if (hspi->RxXferCount == 0U)\r
+    {\r
+      SPI_CloseRxTx_ISR(hspi);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Receive data in 16 Bit mode */\r
+  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
+  hspi->pRxBuffPtr += sizeof(uint16_t);\r
+  hspi->RxXferCount--;\r
+\r
+  if (hspi->RxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;\r
+      return;\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    /* Disable RXNE interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+    if (hspi->TxXferCount == 0U)\r
+    {\r
+      SPI_CloseRxTx_ISR(hspi);\r
+    }\r
+  }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Read 16bit CRC to flush Data Regsiter */\r
+  READ_REG(hspi->Instance->DR);\r
+\r
+  /* Disable RXNE interrupt */\r
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+  SPI_CloseRxTx_ISR(hspi);\r
+}\r
+#endif /* USE_SPI_CRC */\r
+\r
+/**\r
+  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Transmit data in 16 Bit mode */\r
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+  hspi->pTxBuffPtr += sizeof(uint16_t);\r
+  hspi->TxXferCount--;\r
+\r
+  /* Enable CRC Transmission */\r
+  if (hspi->TxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      /* Set CRC Next Bit to send CRC */\r
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+      /* Disable TXE interrupt */\r
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+      return;\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+\r
+    /* Disable TXE interrupt */\r
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+\r
+    if (hspi->RxXferCount == 0U)\r
+    {\r
+      SPI_CloseRxTx_ISR(hspi);\r
+    }\r
+  }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+  * @brief  Manage the CRC 8-bit receive in Interrupt context.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Read 8bit CRC to flush Data Register */\r
+  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
+\r
+  hspi->CRCSize--;\r
+\r
+  if (hspi->CRCSize == 0U)\r
+  {\r
+    SPI_CloseRx_ISR(hspi);\r
+  }\r
+}\r
+#endif /* USE_SPI_CRC */\r
+\r
+/**\r
+  * @brief  Manage the receive 8-bit in Interrupt context.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);\r
+  hspi->pRxBuffPtr++;\r
+  hspi->RxXferCount--;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Enable CRC Transmission */\r
+  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+  {\r
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  if (hspi->RxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      hspi->RxISR =  SPI_RxISR_8BITCRC;\r
+      return;\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+    SPI_CloseRx_ISR(hspi);\r
+  }\r
+}\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+/**\r
+  * @brief  Manage the CRC 16-bit receive in Interrupt context.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Read 16bit CRC to flush Data Register */\r
+  READ_REG(hspi->Instance->DR);\r
+\r
+  /* Disable RXNE and ERR interrupt */\r
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+  SPI_CloseRx_ISR(hspi);\r
+}\r
+#endif /* USE_SPI_CRC */\r
+\r
+/**\r
+  * @brief  Manage the 16-bit receive in Interrupt context.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
+  hspi->pRxBuffPtr += sizeof(uint16_t);\r
+  hspi->RxXferCount--;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Enable CRC Transmission */\r
+  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+  {\r
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+\r
+  if (hspi->RxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      hspi->RxISR = SPI_RxISR_16BITCRC;\r
+      return;\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+    SPI_CloseRx_ISR(hspi);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Handle the data 8-bit transmit in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
+  hspi->pTxBuffPtr++;\r
+  hspi->TxXferCount--;\r
+\r
+  if (hspi->TxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      /* Enable CRC Transmission */\r
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+    SPI_CloseTx_ISR(hspi);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Handle the data 16-bit transmit in Interrupt mode.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Transmit data in 16 Bit mode */\r
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+  hspi->pTxBuffPtr += sizeof(uint16_t);\r
+  hspi->TxXferCount--;\r
+\r
+  if (hspi->TxXferCount == 0U)\r
+  {\r
+#if (USE_SPI_CRC != 0U)\r
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+    {\r
+      /* Enable CRC Transmission */\r
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+    }\r
+#endif /* USE_SPI_CRC */\r
+    SPI_CloseTx_ISR(hspi);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Handle SPI Communication Timeout.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *              the configuration information for SPI module.\r
+  * @param  Flag SPI flag to check\r
+  * @param  State flag state to check\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\r
+                                                       uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)\r
+  {\r
+    if (Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))\r
+      {\r
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
+        on both master and slave sides in order to resynchronize the master\r
+        and slave for their respective CRC calculation */\r
+\r
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+        {\r
+          /* Disable SPI peripheral */\r
+          __HAL_SPI_DISABLE(hspi);\r
+        }\r
+\r
+        /* Reset CRC Calculation */\r
+        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+        {\r
+          SPI_RESET_CRC(hspi);\r
+        }\r
+\r
+        hspi->State = HAL_SPI_STATE_READY;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hspi);\r
+\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handle SPI FIFO Communication Timeout.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *              the configuration information for SPI module.\r
+  * @param  Fifo Fifo to check\r
+  * @param  State Fifo state to check\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r
+                                                       uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  while ((hspi->Instance->SR & Fifo) != State)\r
+  {\r
+    if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))\r
+    {\r
+      /* Read 8bit CRC to flush Data Register */\r
+      READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));\r
+    }\r
+\r
+    if (Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))\r
+      {\r
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
+           on both master and slave sides in order to resynchronize the master\r
+           and slave for their respective CRC calculation */\r
+\r
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+        {\r
+          /* Disable SPI peripheral */\r
+          __HAL_SPI_DISABLE(hspi);\r
+        }\r
+\r
+        /* Reset CRC Calculation */\r
+        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+        {\r
+          SPI_RESET_CRC(hspi);\r
+        }\r
+\r
+        hspi->State = HAL_SPI_STATE_READY;\r
+\r
+        /* Process Unlocked */\r
+        __HAL_UNLOCK(hspi);\r
+\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handle the check of the RX transaction complete.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+  {\r
+    /* Disable SPI peripheral */\r
+    __HAL_SPI_DISABLE(hspi);\r
+  }\r
+\r
+  /* Control the BSY flag */\r
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+    return HAL_TIMEOUT;\r
+  }\r
+\r
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+  {\r
+    /* Empty the FRLVL fifo */\r
+    if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handle the check of the RXTX or TX transaction complete.\r
+  * @param  hspi SPI handle\r
+  * @param  Timeout Timeout duration\r
+  * @param  Tickstart tick start value\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+  /* Control if the TX fifo is empty */\r
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+    return HAL_TIMEOUT;\r
+  }\r
+\r
+  /* Control the BSY flag */\r
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+    return HAL_TIMEOUT;\r
+  }\r
+\r
+  /* Control if the RX fifo is empty */\r
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+    return HAL_TIMEOUT;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handle the end of the RXTX transaction.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Init tickstart for timeout managment*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Disable ERR interrupt */\r
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
+\r
+  /* Check the end of the transaction */\r
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+  }\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Check if CRC error occurred */\r
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+  {\r
+    hspi->State = HAL_SPI_STATE_READY;\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+    /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+    hspi->ErrorCallback(hspi);\r
+#else\r
+    HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+#endif /* USE_SPI_CRC */\r
+    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+    {\r
+      if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r
+      {\r
+        hspi->State = HAL_SPI_STATE_READY;\r
+        /* Call user Rx complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+        hspi->RxCpltCallback(hspi);\r
+#else\r
+        HAL_SPI_RxCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+      }\r
+      else\r
+      {\r
+        hspi->State = HAL_SPI_STATE_READY;\r
+        /* Call user TxRx complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+        hspi->TxRxCpltCallback(hspi);\r
+#else\r
+        HAL_SPI_TxRxCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+      }\r
+    }\r
+    else\r
+    {\r
+      hspi->State = HAL_SPI_STATE_READY;\r
+      /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+      hspi->ErrorCallback(hspi);\r
+#else\r
+      HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+    }\r
+#if (USE_SPI_CRC != 0U)\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+}\r
+\r
+/**\r
+  * @brief  Handle the end of the RX transaction.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+  /* Disable RXNE and ERR interrupt */\r
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+  /* Check the end of the transaction */\r
+  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+  }\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+\r
+#if (USE_SPI_CRC != 0U)\r
+  /* Check if CRC error occurred */\r
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+    /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+    hspi->ErrorCallback(hspi);\r
+#else\r
+    HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+#endif /* USE_SPI_CRC */\r
+    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+    {\r
+      /* Call user Rx complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+      hspi->RxCpltCallback(hspi);\r
+#else\r
+      HAL_SPI_RxCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+    }\r
+    else\r
+    {\r
+      /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+      hspi->ErrorCallback(hspi);\r
+#else\r
+      HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+    }\r
+#if (USE_SPI_CRC != 0U)\r
+  }\r
+#endif /* USE_SPI_CRC */\r
+}\r
+\r
+/**\r
+  * @brief  Handle the end of the TX transaction.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Init tickstart for timeout management*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Disable TXE and ERR interrupt */\r
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
+\r
+  /* Check the end of the transaction */\r
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
+  {\r
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
+  }\r
+\r
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+  {\r
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+  }\r
+\r
+  hspi->State = HAL_SPI_STATE_READY;\r
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+  {\r
+    /* Call user error callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+    hspi->ErrorCallback(hspi);\r
+#else\r
+    HAL_SPI_ErrorCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+  }\r
+  else\r
+  {\r
+    /* Call user Rx complete callback */\r
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
+    hspi->TxCpltCallback(hspi);\r
+#else\r
+    HAL_SPI_TxCpltCallback(hspi);\r
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Handle abort a Rx transaction.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+  __IO uint32_t count;\r
+\r
+  /* Disable SPI Peripheral */\r
+  __HAL_SPI_DISABLE(hspi);\r
+\r
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
+\r
+  /* Disable RXNEIE interrupt */\r
+  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));\r
+\r
+  /* Check RXNEIE is disabled */\r
+  do\r
+  {\r
+    if (count == 0U)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+      break;\r
+    }\r
+    count--;\r
+  }\r
+  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));\r
+\r
+  /* Control the BSY flag */\r
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  /* Empty the FRLVL fifo */\r
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  hspi->State = HAL_SPI_STATE_ABORT;\r
+}\r
+\r
+/**\r
+  * @brief  Handle abort a Tx or Rx/Tx transaction.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for SPI module.\r
+  * @retval None\r
+  */\r
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+  __IO uint32_t count;\r
+\r
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
+\r
+  /* Disable TXEIE interrupt */\r
+  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));\r
+\r
+  /* Check TXEIE is disabled */\r
+  do\r
+  {\r
+    if (count == 0U)\r
+    {\r
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+      break;\r
+    }\r
+    count--;\r
+  }\r
+  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));\r
+\r
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  /* Disable SPI Peripheral */\r
+  __HAL_SPI_DISABLE(hspi);\r
+\r
+  /* Empty the FRLVL fifo */\r
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+  {\r
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+  }\r
+\r
+  /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */\r
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
+  {\r
+    /* Disable RXNEIE interrupt */\r
+    CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));\r
+\r
+    /* Check RXNEIE is disabled */\r
+    do\r
+    {\r
+      if (count == 0U)\r
+      {\r
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
+        break;\r
+      }\r
+      count--;\r
+    }\r
+    while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));\r
+\r
+    /* Control the BSY flag */\r
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+    {\r
+      hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+    }\r
+\r
+    /* Empty the FRLVL fifo */\r
+    if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
+    {\r
+      hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
+    }\r
+  }\r
+  hspi->State = HAL_SPI_STATE_ABORT;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
new file mode 100644 (file)
index 0000000..6aae121
--- /dev/null
@@ -0,0 +1,115 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_spi_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   Extended SPI HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          SPI peripheral extended functionalities :\r
+  *           + IO operation functions\r
+  *\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SPIEx SPIEx\r
+  * @brief SPI Extended HAL module driver\r
+  * @{\r
+  */\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants\r
+  * @{\r
+  */\r
+#define SPI_FIFO_SIZE       4UL\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions\r
+  *  @brief   Data transfers functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                      ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..]\r
+    This subsection provides a set of extended functions to manage the SPI\r
+    data transfers.\r
+\r
+    (#) Rx data flush function:\r
+        (++) HAL_SPIEx_FlushRxFifo()\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Flush the RX fifo.\r
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified SPI module.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)\r
+{\r
+  __IO uint32_t tmpreg;\r
+  uint8_t  count = 0U;\r
+  while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)\r
+  {\r
+    count++;\r
+    tmpreg = hspi->Instance->DR;\r
+    UNUSED(tmpreg); /* To avoid GCC warning */\r
+    if (count == SPI_FIFO_SIZE)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
new file mode 100644 (file)
index 0000000..ef36e7c
--- /dev/null
@@ -0,0 +1,6904 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_tim.c\r
+  * @author  MCD Application Team\r
+  * @brief   TIM HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Timer (TIM) peripheral:\r
+  *           + TIM Time Base Initialization\r
+  *           + TIM Time Base Start\r
+  *           + TIM Time Base Start Interruption\r
+  *           + TIM Time Base Start DMA\r
+  *           + TIM Output Compare/PWM Initialization\r
+  *           + TIM Output Compare/PWM Channel Configuration\r
+  *           + TIM Output Compare/PWM  Start\r
+  *           + TIM Output Compare/PWM  Start Interruption\r
+  *           + TIM Output Compare/PWM Start DMA\r
+  *           + TIM Input Capture Initialization\r
+  *           + TIM Input Capture Channel Configuration\r
+  *           + TIM Input Capture Start\r
+  *           + TIM Input Capture Start Interruption\r
+  *           + TIM Input Capture Start DMA\r
+  *           + TIM One Pulse Initialization\r
+  *           + TIM One Pulse Channel Configuration\r
+  *           + TIM One Pulse Start\r
+  *           + TIM Encoder Interface Initialization\r
+  *           + TIM Encoder Interface Start\r
+  *           + TIM Encoder Interface Start Interruption\r
+  *           + TIM Encoder Interface Start DMA\r
+  *           + Commutation Event configuration with Interruption and DMA\r
+  *           + TIM OCRef clear configuration\r
+  *           + TIM External Clock configuration\r
+  @verbatim\r
+  ==============================================================================\r
+                      ##### TIMER Generic features #####\r
+  ==============================================================================\r
+  [..] The Timer features include:\r
+       (#) 16-bit up, down, up/down auto-reload counter.\r
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the\r
+           counter clock frequency either by any factor between 1 and 65536.\r
+       (#) Up to 4 independent channels for:\r
+           (++) Input Capture\r
+           (++) Output Compare\r
+           (++) PWM generation (Edge and Center-aligned Mode)\r
+           (++) One-pulse mode output\r
+       (#) Synchronization circuit to control the timer with external signals and to interconnect\r
+            several timers together.\r
+       (#) Supports incremental encoder for positioning purposes\r
+\r
+            ##### How to use this driver #####\r
+  ==============================================================================\r
+    [..]\r
+     (#) Initialize the TIM low level resources by implementing the following functions\r
+         depending on the selected feature:\r
+           (++) Time Base : HAL_TIM_Base_MspInit()\r
+           (++) Input Capture : HAL_TIM_IC_MspInit()\r
+           (++) Output Compare : HAL_TIM_OC_MspInit()\r
+           (++) PWM generation : HAL_TIM_PWM_MspInit()\r
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
+\r
+     (#) Initialize the TIM low level resources :\r
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
+        (##) TIM pins configuration\r
+            (+++) Enable the clock for the TIM GPIOs using the following function:\r
+             __HAL_RCC_GPIOx_CLK_ENABLE();\r
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
+\r
+     (#) The external Clock can be configured, if needed (the default clock is the\r
+         internal clock from the APBx), using the following function:\r
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
+         any start function.\r
+\r
+     (#) Configure the TIM in the desired functioning mode using one of the\r
+       Initialization function of this driver:\r
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an\r
+            Output Compare signal.\r
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a\r
+            PWM signal.\r
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an\r
+            external signal.\r
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer\r
+            in One Pulse Mode.\r
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
+\r
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:\r
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
+\r
+     (#) The DMA Burst is managed with the two following functions:\r
+         HAL_TIM_DMABurst_WriteStart()\r
+         HAL_TIM_DMABurst_ReadStart()\r
+\r
+    *** Callback registration ***\r
+  =============================================\r
+\r
+  [..]\r
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1\r
+  allows the user to configure dynamically the driver callbacks.\r
+\r
+  [..]\r
+  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.\r
+  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,\r
+  the Callback ID and a pointer to the user callback function.\r
+\r
+  [..]\r
+  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default\r
+  weak function.\r
+  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
+  and the Callback ID.\r
+\r
+  [..]\r
+  These functions allow to register/unregister following callbacks:\r
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.\r
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.\r
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.\r
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.\r
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.\r
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.\r
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.\r
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.\r
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.\r
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.\r
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.\r
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.\r
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.\r
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.\r
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.\r
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.\r
+    (+) TriggerCallback                   : TIM Trigger Callback.\r
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.\r
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.\r
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.\r
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.\r
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.\r
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.\r
+    (+) ErrorCallback                     : TIM Error Callback.\r
+    (+) CommutationCallback               : TIM Commutation Callback.\r
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.\r
+    (+) BreakCallback                     : TIM Break Callback.\r
+    (+) Break2Callback                    : TIM Break2 Callback.\r
+\r
+  [..]\r
+By default, after the Init and when the state is HAL_TIM_STATE_RESET\r
+all interrupt callbacks are set to the corresponding weak functions:\r
+  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().\r
+\r
+  [..]\r
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\r
+  functionalities in the Init / DeInit only when these callbacks are null\r
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit\r
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)\r
+\r
+  [..]\r
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.\r
+    Exception done MspInit / MspDeInit that can be registered / unregistered\r
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,\r
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.\r
+  In that case first register the MspInit/MspDeInit user callbacks\r
+      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.\r
+\r
+  [..]\r
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or\r
+      not defined, the callback registration feature is not available and all callbacks\r
+      are set to the corresponding weak functions.\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIM TIM\r
+  * @brief TIM HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup TIM_Private_Functions\r
+  * @{\r
+  */\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+                              uint32_t TIM_ICFilter);\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+                              uint32_t TIM_ICFilter);\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+                              uint32_t TIM_ICFilter);\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+/**\r
+  * @}\r
+  */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+  *  @brief    Time Base functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+              ##### Time Base functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Initialize and configure the TIM base.\r
+    (+) De-initialize the TIM base.\r
+    (+) Start the Time Base.\r
+    (+) Stop the Time Base.\r
+    (+) Start the Time Base and enable interrupt.\r
+    (+) Stop the Time Base and disable interrupt.\r
+    (+) Start the Time Base and enable DMA transfer.\r
+    (+) Stop the Time Base and disable DMA transfer.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initializes the TIM Time base Unit according to the specified\r
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.\r
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+  *         requires a timer reset to avoid unexpected direction\r
+  *         due to DIR bit readonly in center aligned mode.\r
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the TIM handle allocation */\r
+  if (htim == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+  if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+    /* Reset interrupt callbacks to legacy weak callbacks */\r
+    TIM_ResetCallback(htim);\r
+\r
+    if (htim->Base_MspInitCallback == NULL)\r
+    {\r
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;\r
+    }\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    htim->Base_MspInitCallback(htim);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    HAL_TIM_Base_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Set the Time Base configuration */\r
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+  /* Initialize the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the TIM Base peripheral\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the TIM Peripheral Clock */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  if (htim->Base_MspDeInitCallback == NULL)\r
+  {\r
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  htim->Base_MspDeInitCallback(htim);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+  HAL_TIM_Base_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  /* Change TIM state */\r
+  htim->State = HAL_TIM_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM Base MSP.\r
+  * @param  htim TIM Base handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_Base_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes TIM Base MSP.\r
+  * @param  htim TIM Base handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Starts the TIM Base generation.\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Change the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Base generation.\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Base generation in interrupt mode.\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  /* Enable the TIM Update interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Base generation in interrupt mode.\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+  /* Disable the TIM Update interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Base generation in DMA mode.\r
+  * @param  htim TIM Base handle\r
+  * @param  pData The source Buffer address.\r
+  * @param  Length The length of data to be transferred from memory to peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if ((pData == NULL) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+  /* Set the DMA Period elapsed callbacks */\r
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+  /* Set the DMA error callback */\r
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+  /* Enable the DMA channel */\r
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Enable the TIM Update DMA request */\r
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Base generation in DMA mode.\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+  /* Disable the TIM Update DMA request */\r
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+  *  @brief    TIM Output Compare functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                  ##### TIM Output Compare functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Initialize and configure the TIM Output Compare.\r
+    (+) De-initialize the TIM Output Compare.\r
+    (+) Start the TIM Output Compare.\r
+    (+) Stop the TIM Output Compare.\r
+    (+) Start the TIM Output Compare and enable interrupt.\r
+    (+) Stop the TIM Output Compare and disable interrupt.\r
+    (+) Start the TIM Output Compare and enable DMA transfer.\r
+    (+) Stop the TIM Output Compare and disable DMA transfer.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initializes the TIM Output Compare according to the specified\r
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+  *         requires a timer reset to avoid unexpected direction\r
+  *         due to DIR bit readonly in center aligned mode.\r
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()\r
+  * @param  htim TIM Output Compare handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the TIM handle allocation */\r
+  if (htim == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+  if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+    /* Reset interrupt callbacks to legacy weak callbacks */\r
+    TIM_ResetCallback(htim);\r
+\r
+    if (htim->OC_MspInitCallback == NULL)\r
+    {\r
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;\r
+    }\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    htim->OC_MspInitCallback(htim);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+    HAL_TIM_OC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Init the base time for the Output Compare */\r
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);\r
+\r
+  /* Initialize the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the TIM peripheral\r
+  * @param  htim TIM Output Compare handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the TIM Peripheral Clock */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  if (htim->OC_MspDeInitCallback == NULL)\r
+  {\r
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  htim->OC_MspDeInitCallback(htim);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+  HAL_TIM_OC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  /* Change TIM state */\r
+  htim->State = HAL_TIM_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM Output Compare MSP.\r
+  * @param  htim TIM Output Compare handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_OC_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes TIM Output Compare MSP.\r
+  * @param  htim TIM Output Compare handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Output Compare signal generation.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Enable the Output compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Output Compare signal generation.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Disable the Output compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Enable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Enable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Enable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Enable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the Output compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Disable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Output compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @param  pData The source Buffer address.\r
+  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if ((pData == NULL) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Enable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Enable the TIM Capture/Compare 2 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 3 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 4 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the Output compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Disable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Output compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+  *  @brief    TIM PWM functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                          ##### TIM PWM functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Initialize and configure the TIM PWM.\r
+    (+) De-initialize the TIM PWM.\r
+    (+) Start the TIM PWM.\r
+    (+) Stop the TIM PWM.\r
+    (+) Start the TIM PWM and enable interrupt.\r
+    (+) Stop the TIM PWM and disable interrupt.\r
+    (+) Start the TIM PWM and enable DMA transfer.\r
+    (+) Stop the TIM PWM and disable DMA transfer.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initializes the TIM PWM Time Base according to the specified\r
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+  *         requires a timer reset to avoid unexpected direction\r
+  *         due to DIR bit readonly in center aligned mode.\r
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()\r
+  * @param  htim TIM PWM handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the TIM handle allocation */\r
+  if (htim == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+  if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+    /* Reset interrupt callbacks to legacy weak callbacks */\r
+    TIM_ResetCallback(htim);\r
+\r
+    if (htim->PWM_MspInitCallback == NULL)\r
+    {\r
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;\r
+    }\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    htim->PWM_MspInitCallback(htim);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+    HAL_TIM_PWM_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Init the base time for the PWM */\r
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+  /* Initialize the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the TIM peripheral\r
+  * @param  htim TIM PWM handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the TIM Peripheral Clock */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  if (htim->PWM_MspDeInitCallback == NULL)\r
+  {\r
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  htim->PWM_MspDeInitCallback(htim);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+  HAL_TIM_PWM_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  /* Change TIM state */\r
+  htim->State = HAL_TIM_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM PWM MSP.\r
+  * @param  htim TIM PWM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_PWM_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes TIM PWM MSP.\r
+  * @param  htim TIM PWM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Starts the PWM signal generation.\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Enable the Capture compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the PWM signal generation.\r
+  * @param  htim TIM PWM handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Disable the Capture compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the PWM signal generation in interrupt mode.\r
+  * @param  htim TIM PWM handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Enable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Enable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Enable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Enable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the Capture compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the PWM signal generation in interrupt mode.\r
+  * @param  htim TIM PWM handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Disable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Capture compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM PWM signal generation in DMA mode.\r
+  * @param  htim TIM PWM handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @param  pData The source Buffer address.\r
+  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if ((pData == NULL) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Enable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 2 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Output Capture/Compare 3 request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 4 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the Capture compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM PWM signal generation in DMA mode.\r
+  * @param  htim TIM PWM handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Disable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Capture compare channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+  *  @brief    TIM Input Capture functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+              ##### TIM Input Capture functions #####\r
+  ==============================================================================\r
+ [..]\r
+   This section provides functions allowing to:\r
+   (+) Initialize and configure the TIM Input Capture.\r
+   (+) De-initialize the TIM Input Capture.\r
+   (+) Start the TIM Input Capture.\r
+   (+) Stop the TIM Input Capture.\r
+   (+) Start the TIM Input Capture and enable interrupt.\r
+   (+) Stop the TIM Input Capture and disable interrupt.\r
+   (+) Start the TIM Input Capture and enable DMA transfer.\r
+   (+) Stop the TIM Input Capture and disable DMA transfer.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initializes the TIM Input Capture Time base according to the specified\r
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+  *         requires a timer reset to avoid unexpected direction\r
+  *         due to DIR bit readonly in center aligned mode.\r
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()\r
+  * @param  htim TIM Input Capture handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the TIM handle allocation */\r
+  if (htim == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+  if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+    /* Reset interrupt callbacks to legacy weak callbacks */\r
+    TIM_ResetCallback(htim);\r
+\r
+    if (htim->IC_MspInitCallback == NULL)\r
+    {\r
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;\r
+    }\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    htim->IC_MspInitCallback(htim);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+    HAL_TIM_IC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Init the base time for the input capture */\r
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+  /* Initialize the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the TIM peripheral\r
+  * @param  htim TIM Input Capture handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the TIM Peripheral Clock */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  if (htim->IC_MspDeInitCallback == NULL)\r
+  {\r
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  htim->IC_MspDeInitCallback(htim);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+  HAL_TIM_IC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  /* Change TIM state */\r
+  htim->State = HAL_TIM_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM Input Capture MSP.\r
+  * @param  htim TIM Input Capture handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_IC_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes TIM Input Capture MSP.\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Input Capture measurement.\r
+  * @param  htim TIM Input Capture handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Enable the Input Capture channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Input Capture measurement.\r
+  * @param  htim TIM Input Capture handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Disable the Input Capture channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.\r
+  * @param  htim TIM Input Capture handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Enable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Enable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Enable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Enable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+  /* Enable the Input Capture channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.\r
+  * @param  htim TIM Input Capture handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Disable the TIM Capture/Compare 4 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Input Capture channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.\r
+  * @param  htim TIM Input Capture handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @param  pData The destination Buffer address.\r
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if ((pData == NULL) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 2  DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 3  DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 4  DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the Input Capture channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.\r
+  * @param  htim TIM Input Capture handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3  DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Disable the TIM Capture/Compare 4  DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Input Capture channel */\r
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+  *  @brief    TIM One Pulse functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                        ##### TIM One Pulse functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Initialize and configure the TIM One Pulse.\r
+    (+) De-initialize the TIM One Pulse.\r
+    (+) Start the TIM One Pulse.\r
+    (+) Stop the TIM One Pulse.\r
+    (+) Start the TIM One Pulse and enable interrupt.\r
+    (+) Stop the TIM One Pulse and disable interrupt.\r
+    (+) Start the TIM One Pulse and enable DMA transfer.\r
+    (+) Stop the TIM One Pulse and disable DMA transfer.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified\r
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+  *         requires a timer reset to avoid unexpected direction\r
+  *         due to DIR bit readonly in center aligned mode.\r
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OnePulseMode Select the One pulse mode.\r
+  *         This parameter can be one of the following values:\r
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
+{\r
+  /* Check the TIM handle allocation */\r
+  if (htim == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+  if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+    /* Reset interrupt callbacks to legacy weak callbacks */\r
+    TIM_ResetCallback(htim);\r
+\r
+    if (htim->OnePulse_MspInitCallback == NULL)\r
+    {\r
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;\r
+    }\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    htim->OnePulse_MspInitCallback(htim);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+    HAL_TIM_OnePulse_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Configure the Time base in the One Pulse Mode */\r
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+  /* Reset the OPM Bit */\r
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
+\r
+  /* Configure the OPM Mode */\r
+  htim->Instance->CR1 |= OnePulseMode;\r
+\r
+  /* Initialize the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the TIM One Pulse\r
+  * @param  htim TIM One Pulse handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the TIM Peripheral Clock */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  if (htim->OnePulse_MspDeInitCallback == NULL)\r
+  {\r
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  htim->OnePulse_MspDeInitCallback(htim);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+  HAL_TIM_OnePulse_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  /* Change TIM state */\r
+  htim->State = HAL_TIM_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM One Pulse MSP.\r
+  * @param  htim TIM One Pulse handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes TIM One Pulse MSP.\r
+  * @param  htim TIM One Pulse handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM One Pulse signal generation.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(OutputChannel);\r
+\r
+  /* Enable the Capture compare and the Input Capture channels\r
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+    No need to enable the counter, it's enabled automatically by hardware\r
+    (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM One Pulse signal generation.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channels to be disable\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(OutputChannel);\r
+\r
+  /* Disable the Capture compare and the Input Capture channels\r
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(OutputChannel);\r
+\r
+  /* Enable the Capture compare and the Input Capture channels\r
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+    No need to enable the counter, it's enabled automatically by hardware\r
+    (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+  /* Enable the TIM Capture/Compare 1 interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+  /* Enable the TIM Capture/Compare 2 interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Enable the main output */\r
+    __HAL_TIM_MOE_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(OutputChannel);\r
+\r
+  /* Disable the TIM Capture/Compare 1 interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+  /* Disable the TIM Capture/Compare 2 interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+\r
+  /* Disable the Capture compare and the Input Capture channels\r
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+  {\r
+    /* Disable the Main Output */\r
+    __HAL_TIM_MOE_DISABLE(htim);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+  *  @brief    TIM Encoder functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                          ##### TIM Encoder functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Initialize and configure the TIM Encoder.\r
+    (+) De-initialize the TIM Encoder.\r
+    (+) Start the TIM Encoder.\r
+    (+) Stop the TIM Encoder.\r
+    (+) Start the TIM Encoder and enable interrupt.\r
+    (+) Stop the TIM Encoder and disable interrupt.\r
+    (+) Start the TIM Encoder and enable DMA transfer.\r
+    (+) Stop the TIM Encoder and disable DMA transfer.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.\r
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+  *         requires a timer reset to avoid unexpected direction\r
+  *         due to DIR bit readonly in center aligned mode.\r
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()\r
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together\r
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource\r
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @param  sConfig TIM Encoder Interface configuration structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)\r
+{\r
+  uint32_t tmpsmcr;\r
+  uint32_t tmpccmr1;\r
+  uint32_t tmpccer;\r
+\r
+  /* Check the TIM handle allocation */\r
+  if (htim == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
+\r
+  if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+    /* Reset interrupt callbacks to legacy weak callbacks */\r
+    TIM_ResetCallback(htim);\r
+\r
+    if (htim->Encoder_MspInitCallback == NULL)\r
+    {\r
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;\r
+    }\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    htim->Encoder_MspInitCallback(htim);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+    HAL_TIM_Encoder_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Reset the SMS and ECE bits */\r
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);\r
+\r
+  /* Configure the Time base in the Encoder Mode */\r
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+  /* Get the TIMx SMCR register value */\r
+  tmpsmcr = htim->Instance->SMCR;\r
+\r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = htim->Instance->CCER;\r
+\r
+  /* Set the encoder Mode */\r
+  tmpsmcr |= sConfig->EncoderMode;\r
+\r
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));\r
+\r
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);\r
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);\r
+\r
+  /* Set the TI1 and the TI2 Polarities */\r
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);\r
+\r
+  /* Write to TIMx SMCR */\r
+  htim->Instance->SMCR = tmpsmcr;\r
+\r
+  /* Write to TIMx CCMR1 */\r
+  htim->Instance->CCMR1 = tmpccmr1;\r
+\r
+  /* Write to TIMx CCER */\r
+  htim->Instance->CCER = tmpccer;\r
+\r
+  /* Initialize the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  DeInitializes the TIM Encoder interface\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the TIM Peripheral Clock */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  if (htim->Encoder_MspDeInitCallback == NULL)\r
+  {\r
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  htim->Encoder_MspDeInitCallback(htim);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+  HAL_TIM_Encoder_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  /* Change TIM state */\r
+  htim->State = HAL_TIM_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM Encoder Interface MSP.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes TIM Encoder Interface MSP.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Encoder Interface.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+  /* Enable the encoder interface channels */\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+      break;\r
+    }\r
+\r
+    default :\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+      break;\r
+    }\r
+  }\r
+  /* Enable the Peripheral */\r
+  __HAL_TIM_ENABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Encoder Interface.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+  /* Disable the Input Capture channels 1 and 2\r
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+      break;\r
+    }\r
+\r
+    default :\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+      break;\r
+    }\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+  /* Enable the encoder interface channels */\r
+  /* Enable the capture compare Interrupts 1 and/or 2 */\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    default :\r
+    {\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+  }\r
+\r
+  /* Enable the Peripheral */\r
+  __HAL_TIM_ENABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @param  Channel TIM Channels to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+  /* Disable the Input Capture channels 1 and 2\r
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+  if (Channel == TIM_CHANNEL_1)\r
+  {\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+    /* Disable the capture compare Interrupts 1 */\r
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+  }\r
+  else if (Channel == TIM_CHANNEL_2)\r
+  {\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+    /* Disable the capture compare Interrupts 2 */\r
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+  }\r
+  else\r
+  {\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+    /* Disable the capture compare Interrupts 1 and 2 */\r
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Encoder Interface in DMA mode.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+  * @param  pData1 The destination Buffer address for IC1.\r
+  * @param  pData2 The destination Buffer address for IC2.\r
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\r
+                                            uint32_t *pData2, uint16_t Length)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Input Capture DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+      /* Enable the Peripheral */\r
+      __HAL_TIM_ENABLE(htim);\r
+\r
+      /* Enable the Capture compare channel */\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Input Capture  DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+\r
+      /* Enable the Peripheral */\r
+      __HAL_TIM_ENABLE(htim);\r
+\r
+      /* Enable the Capture compare channel */\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_ALL:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the Peripheral */\r
+      __HAL_TIM_ENABLE(htim);\r
+\r
+      /* Enable the Capture compare channel */\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+      /* Enable the TIM Input Capture  DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+      /* Enable the TIM Input Capture  DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Encoder Interface in DMA mode.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+  /* Disable the Input Capture channels 1 and 2\r
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+  if (Channel == TIM_CHANNEL_1)\r
+  {\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+    /* Disable the capture compare DMA Request 1 */\r
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+  }\r
+  else if (Channel == TIM_CHANNEL_2)\r
+  {\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+    /* Disable the capture compare DMA Request 2 */\r
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+  }\r
+  else\r
+  {\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+    /* Disable the capture compare DMA Request 1 and 2 */\r
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+  }\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+  *  @brief    TIM IRQ handler management\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                        ##### IRQ handler management #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides Timer IRQ handler function.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  This function handles TIM interrupts requests.\r
+  * @param  htim TIM  handle\r
+  * @retval None\r
+  */\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Capture compare 1 event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)\r
+    {\r
+      {\r
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+\r
+        /* Input capture event */\r
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)\r
+        {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+          htim->IC_CaptureCallback(htim);\r
+#else\r
+          HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+        }\r
+        /* Output compare event */\r
+        else\r
+        {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+          htim->OC_DelayElapsedCallback(htim);\r
+          htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+          HAL_TIM_OC_DelayElapsedCallback(htim);\r
+          HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+        }\r
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+      }\r
+    }\r
+  }\r
+  /* Capture compare 2 event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+      /* Input capture event */\r
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)\r
+      {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+        htim->IC_CaptureCallback(htim);\r
+#else\r
+        HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+      }\r
+      /* Output compare event */\r
+      else\r
+      {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+        htim->OC_DelayElapsedCallback(htim);\r
+        htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+        HAL_TIM_OC_DelayElapsedCallback(htim);\r
+        HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+      }\r
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+    }\r
+  }\r
+  /* Capture compare 3 event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+      /* Input capture event */\r
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)\r
+      {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+        htim->IC_CaptureCallback(htim);\r
+#else\r
+        HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+      }\r
+      /* Output compare event */\r
+      else\r
+      {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+        htim->OC_DelayElapsedCallback(htim);\r
+        htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+        HAL_TIM_OC_DelayElapsedCallback(htim);\r
+        HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+      }\r
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+    }\r
+  }\r
+  /* Capture compare 4 event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+      /* Input capture event */\r
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)\r
+      {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+        htim->IC_CaptureCallback(htim);\r
+#else\r
+        HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+      }\r
+      /* Output compare event */\r
+      else\r
+      {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+        htim->OC_DelayElapsedCallback(htim);\r
+        htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+        HAL_TIM_OC_DelayElapsedCallback(htim);\r
+        HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+      }\r
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+    }\r
+  }\r
+  /* TIM Update event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+      htim->PeriodElapsedCallback(htim);\r
+#else\r
+      HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  /* TIM Break input event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+      htim->BreakCallback(htim);\r
+#else\r
+      HAL_TIMEx_BreakCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  /* TIM Break2 input event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+      htim->Break2Callback(htim);\r
+#else\r
+      HAL_TIMEx_Break2Callback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  /* TIM Trigger detection event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+      htim->TriggerCallback(htim);\r
+#else\r
+      HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  /* TIM commutation event */\r
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r
+  {\r
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)\r
+    {\r
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+      htim->CommutationCallback(htim);\r
+#else\r
+      HAL_TIMEx_CommutCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+  *  @brief    TIM Peripheral Control functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                   ##### Peripheral Control functions #####\r
+  ==============================================================================\r
+ [..]\r
+   This section provides functions allowing to:\r
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.\r
+      (+) Configure External Clock source.\r
+      (+) Configure Complementary channels, break features and dead time.\r
+      (+) Configure Master and the Slave synchronization.\r
+      (+) Configure the DMA Burst Mode.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initializes the TIM Output Compare Channels according to the specified\r
+  *         parameters in the TIM_OC_InitTypeDef.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  sConfig TIM Output Compare configuration structure\r
+  * @param  Channel TIM Channels to configure\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,\r
+                                           TIM_OC_InitTypeDef *sConfig,\r
+                                           uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CHANNELS(Channel));\r
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the TIM Channel 1 in Output Compare */\r
+      TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the TIM Channel 2 in Output Compare */\r
+      TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the TIM Channel 3 in Output Compare */\r
+      TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the TIM Channel 4 in Output Compare */\r
+      TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_5:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the TIM Channel 5 in Output Compare */\r
+      TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_6:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the TIM Channel 6 in Output Compare */\r
+      TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM Input Capture Channels according to the specified\r
+  *         parameters in the TIM_IC_InitTypeDef.\r
+  * @param  htim TIM IC handle\r
+  * @param  sConfig TIM Input Capture configuration structure\r
+  * @param  Channel TIM Channel to configure\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  if (Channel == TIM_CHANNEL_1)\r
+  {\r
+    /* TI1 Configuration */\r
+    TIM_TI1_SetConfig(htim->Instance,\r
+                      sConfig->ICPolarity,\r
+                      sConfig->ICSelection,\r
+                      sConfig->ICFilter);\r
+\r
+    /* Reset the IC1PSC Bits */\r
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+    /* Set the IC1PSC value */\r
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
+  }\r
+  else if (Channel == TIM_CHANNEL_2)\r
+  {\r
+    /* TI2 Configuration */\r
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+    TIM_TI2_SetConfig(htim->Instance,\r
+                      sConfig->ICPolarity,\r
+                      sConfig->ICSelection,\r
+                      sConfig->ICFilter);\r
+\r
+    /* Reset the IC2PSC Bits */\r
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+    /* Set the IC2PSC value */\r
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);\r
+  }\r
+  else if (Channel == TIM_CHANNEL_3)\r
+  {\r
+    /* TI3 Configuration */\r
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+    TIM_TI3_SetConfig(htim->Instance,\r
+                      sConfig->ICPolarity,\r
+                      sConfig->ICSelection,\r
+                      sConfig->ICFilter);\r
+\r
+    /* Reset the IC3PSC Bits */\r
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
+\r
+    /* Set the IC3PSC value */\r
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
+  }\r
+  else\r
+  {\r
+    /* TI4 Configuration */\r
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+    TIM_TI4_SetConfig(htim->Instance,\r
+                      sConfig->ICPolarity,\r
+                      sConfig->ICSelection,\r
+                      sConfig->ICFilter);\r
+\r
+    /* Reset the IC4PSC Bits */\r
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
+\r
+    /* Set the IC4PSC value */\r
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);\r
+  }\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM PWM  channels according to the specified\r
+  *         parameters in the TIM_OC_InitTypeDef.\r
+  * @param  htim TIM PWM handle\r
+  * @param  sConfig TIM PWM configuration structure\r
+  * @param  Channel TIM Channels to be configured\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,\r
+                                            TIM_OC_InitTypeDef *sConfig,\r
+                                            uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CHANNELS(Channel));\r
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the Channel 1 in PWM mode */\r
+      TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+\r
+      /* Set the Preload enable bit for channel1 */\r
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+\r
+      /* Configure the Output Fast mode */\r
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the Channel 2 in PWM mode */\r
+      TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+\r
+      /* Set the Preload enable bit for channel2 */\r
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+\r
+      /* Configure the Output Fast mode */\r
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the Channel 3 in PWM mode */\r
+      TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+\r
+      /* Set the Preload enable bit for channel3 */\r
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+\r
+      /* Configure the Output Fast mode */\r
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the Channel 4 in PWM mode */\r
+      TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+\r
+      /* Set the Preload enable bit for channel4 */\r
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+\r
+      /* Configure the Output Fast mode */\r
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_5:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the Channel 5 in PWM mode */\r
+      TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+\r
+      /* Set the Preload enable bit for channel5*/\r
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;\r
+\r
+      /* Configure the Output Fast mode */\r
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;\r
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_6:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
+\r
+      /* Configure the Channel 6 in PWM mode */\r
+      TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+\r
+      /* Set the Preload enable bit for channel6 */\r
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;\r
+\r
+      /* Configure the Output Fast mode */\r
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;\r
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM One Pulse Channels according to the specified\r
+  *         parameters in the TIM_OnePulse_InitTypeDef.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  sConfig TIM One Pulse configuration structure\r
+  * @param  OutputChannel TIM output channel to configure\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @param  InputChannel TIM input Channel to configure\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,\r
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)\r
+{\r
+  TIM_OC_InitTypeDef temp1;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
+\r
+  if (OutputChannel != InputChannel)\r
+  {\r
+    /* Process Locked */\r
+    __HAL_LOCK(htim);\r
+\r
+    htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+    /* Extract the Output compare configuration from sConfig structure */\r
+    temp1.OCMode = sConfig->OCMode;\r
+    temp1.Pulse = sConfig->Pulse;\r
+    temp1.OCPolarity = sConfig->OCPolarity;\r
+    temp1.OCNPolarity = sConfig->OCNPolarity;\r
+    temp1.OCIdleState = sConfig->OCIdleState;\r
+    temp1.OCNIdleState = sConfig->OCNIdleState;\r
+\r
+    switch (OutputChannel)\r
+    {\r
+      case TIM_CHANNEL_1:\r
+      {\r
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+        TIM_OC1_SetConfig(htim->Instance, &temp1);\r
+        break;\r
+      }\r
+      case TIM_CHANNEL_2:\r
+      {\r
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+        TIM_OC2_SetConfig(htim->Instance, &temp1);\r
+        break;\r
+      }\r
+      default:\r
+        break;\r
+    }\r
+\r
+    switch (InputChannel)\r
+    {\r
+      case TIM_CHANNEL_1:\r
+      {\r
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+                          sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+        /* Reset the IC1PSC Bits */\r
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+        /* Select the Trigger source */\r
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+        htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
+\r
+        /* Select the Slave Mode */\r
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+        break;\r
+      }\r
+      case TIM_CHANNEL_2:\r
+      {\r
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+                          sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+        /* Reset the IC2PSC Bits */\r
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+        /* Select the Trigger source */\r
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+        htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
+\r
+        /* Select the Slave Mode */\r
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+        break;\r
+      }\r
+\r
+      default:\r
+        break;\r
+    }\r
+\r
+    htim->State = HAL_TIM_STATE_READY;\r
+\r
+    __HAL_UNLOCK(htim);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral\r
+  * @param  htim TIM handle\r
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write\r
+  *         This parameter can be one of the following values:\r
+  *            @arg TIM_DMABASE_CR1\r
+  *            @arg TIM_DMABASE_CR2\r
+  *            @arg TIM_DMABASE_SMCR\r
+  *            @arg TIM_DMABASE_DIER\r
+  *            @arg TIM_DMABASE_SR\r
+  *            @arg TIM_DMABASE_EGR\r
+  *            @arg TIM_DMABASE_CCMR1\r
+  *            @arg TIM_DMABASE_CCMR2\r
+  *            @arg TIM_DMABASE_CCER\r
+  *            @arg TIM_DMABASE_CNT\r
+  *            @arg TIM_DMABASE_PSC\r
+  *            @arg TIM_DMABASE_ARR\r
+  *            @arg TIM_DMABASE_RCR\r
+  *            @arg TIM_DMABASE_CCR1\r
+  *            @arg TIM_DMABASE_CCR2\r
+  *            @arg TIM_DMABASE_CCR3\r
+  *            @arg TIM_DMABASE_CCR4\r
+  *            @arg TIM_DMABASE_BDTR\r
+  *            @arg TIM_DMABASE_OR1\r
+  *            @arg TIM_DMABASE_CCMR3 \r
+  *            @arg TIM_DMABASE_CCR5 \r
+  *            @arg TIM_DMABASE_CCR6 \r
+  *            @arg TIM_DMABASE_OR2  \r
+  *            @arg TIM_DMABASE_OR3  \r
+  * @param  BurstRequestSrc TIM DMA Request sources\r
+  *         This parameter can be one of the following values:\r
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+  * @param  BurstBuffer The Buffer address.\r
+  * @param  BurstLength DMA Burst length. This parameter can be one value\r
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+                                              uint32_t *BurstBuffer, uint32_t  BurstLength)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+  switch (BurstRequestSrc)\r
+  {\r
+    case TIM_DMA_UPDATE:\r
+    {\r
+      /* Set the DMA Period elapsed callbacks */\r
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC1:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,\r
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC2:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,\r
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC3:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,\r
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC4:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,\r
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_COM:\r
+    {\r
+      /* Set the DMA commutation callbacks */\r
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;\r
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,\r
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_TRIGGER:\r
+    {\r
+      /* Set the DMA trigger callbacks */\r
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,\r
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    default:\r
+      break;\r
+  }\r
+  /* configure the DMA Burst Mode */\r
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+\r
+  /* Enable the TIM DMA Request */\r
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM DMA Burst mode\r
+  * @param  htim TIM handle\r
+  * @param  BurstRequestSrc TIM DMA Request sources to disable\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+  /* Abort the DMA transfer (at least disable the DMA channel) */\r
+  switch (BurstRequestSrc)\r
+  {\r
+    case TIM_DMA_UPDATE:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC1:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC2:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC3:\r
+    {\r
+      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC4:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+      break;\r
+    }\r
+    case TIM_DMA_COM:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+      break;\r
+    }\r
+    case TIM_DMA_TRIGGER:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+      break;\r
+    }\r
+    default:\r
+      break;\r
+  }\r
+\r
+  if (HAL_OK == status)\r
+  {\r
+    /* Disable the TIM Update DMA request */\r
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+  }\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\r
+  * @param  htim TIM handle\r
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read\r
+  *         This parameter can be one of the following values:\r
+  *            @arg TIM_DMABASE_CR1\r
+  *            @arg TIM_DMABASE_CR2\r
+  *            @arg TIM_DMABASE_SMCR\r
+  *            @arg TIM_DMABASE_DIER\r
+  *            @arg TIM_DMABASE_SR\r
+  *            @arg TIM_DMABASE_EGR\r
+  *            @arg TIM_DMABASE_CCMR1\r
+  *            @arg TIM_DMABASE_CCMR2\r
+  *            @arg TIM_DMABASE_CCER\r
+  *            @arg TIM_DMABASE_CNT\r
+  *            @arg TIM_DMABASE_PSC\r
+  *            @arg TIM_DMABASE_ARR\r
+  *            @arg TIM_DMABASE_RCR\r
+  *            @arg TIM_DMABASE_CCR1\r
+  *            @arg TIM_DMABASE_CCR2\r
+  *            @arg TIM_DMABASE_CCR3\r
+  *            @arg TIM_DMABASE_CCR4\r
+  *            @arg TIM_DMABASE_BDTR\r
+  *            @arg TIM_DMABASE_OR1\r
+  *            @arg TIM_DMABASE_CCMR3 \r
+  *            @arg TIM_DMABASE_CCR5 \r
+  *            @arg TIM_DMABASE_CCR6 \r
+  *            @arg TIM_DMABASE_OR2  \r
+  *            @arg TIM_DMABASE_OR3  \r
+  * @param  BurstRequestSrc TIM DMA Request sources\r
+  *         This parameter can be one of the following values:\r
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+  * @param  BurstBuffer The Buffer address.\r
+  * @param  BurstLength DMA Burst length. This parameter can be one value\r
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+  switch (BurstRequestSrc)\r
+  {\r
+    case TIM_DMA_UPDATE:\r
+    {\r
+      /* Set the DMA Period elapsed callbacks */\r
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC1:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC2:\r
+    {\r
+      /* Set the DMA capture/compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC3:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_CC4:\r
+    {\r
+      /* Set the DMA capture callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_COM:\r
+    {\r
+      /* Set the DMA commutation callbacks */\r
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;\r
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    case TIM_DMA_TRIGGER:\r
+    {\r
+      /* Set the DMA trigger callbacks */\r
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      break;\r
+    }\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* configure the DMA Burst Mode */\r
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+\r
+  /* Enable the TIM DMA Request */\r
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stop the DMA burst reading\r
+  * @param  htim TIM handle\r
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+  /* Abort the DMA transfer (at least disable the DMA channel) */\r
+  switch (BurstRequestSrc)\r
+  {\r
+    case TIM_DMA_UPDATE:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC1:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC2:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC3:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+      break;\r
+    }\r
+    case TIM_DMA_CC4:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+      break;\r
+    }\r
+    case TIM_DMA_COM:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+      break;\r
+    }\r
+    case TIM_DMA_TRIGGER:\r
+    {\r
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+      break;\r
+    }\r
+    default:\r
+      break;\r
+  }\r
+\r
+  if (HAL_OK == status)\r
+  {\r
+    /* Disable the TIM Update DMA request */\r
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+  }\r
+\r
+  /* Return function status */\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Generate a software event\r
+  * @param  htim TIM handle\r
+  * @param  EventSource specifies the event source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source\r
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source\r
+  * @note   Basic timers can only generate an update event.\r
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.\r
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant\r
+  *         only for timer instances supporting break input(s).\r
+  * @retval HAL status\r
+  */\r
+\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  /* Change the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Set the event sources */\r
+  htim->Instance->EGR = EventSource;\r
+\r
+  /* Change the TIM state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the OCRef clear feature\r
+  * @param  htim TIM handle\r
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that\r
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.\r
+  * @param  Channel specifies the TIM Channel\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+                                           uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  switch (sClearInputConfig->ClearInputSource)\r
+  {\r
+    case TIM_CLEARINPUTSOURCE_NONE:\r
+    {\r
+      /* Clear the OCREF clear selection bit and the the ETR Bits */\r
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));\r
+      break;\r
+    }\r
+    case TIM_CLEARINPUTSOURCE_OCREFCLR:\r
+    {\r
+      /* Clear the OCREF clear selection bit */\r
+      CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);\r
+    }\r
+    break;\r
+\r
+    case TIM_CLEARINPUTSOURCE_ETR:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+\r
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)\r
+      {\r
+        htim->State = HAL_TIM_STATE_READY;\r
+        __HAL_UNLOCK(htim);\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      TIM_ETR_SetConfig(htim->Instance,\r
+                        sClearInputConfig->ClearInputPrescaler,\r
+                        sClearInputConfig->ClearInputPolarity,\r
+                        sClearInputConfig->ClearInputFilter);\r
+\r
+      /* Set the OCREF clear selection bit */\r
+      SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+      {\r
+        /* Enable the OCREF clear feature for Channel 1 */\r
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+      }\r
+      else\r
+      {\r
+        /* Disable the OCREF clear feature for Channel 1 */\r
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+      }\r
+      break;\r
+    }\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+      {\r
+        /* Enable the OCREF clear feature for Channel 2 */\r
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+      }\r
+      else\r
+      {\r
+        /* Disable the OCREF clear feature for Channel 2 */\r
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+      }\r
+      break;\r
+    }\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+      {\r
+        /* Enable the OCREF clear feature for Channel 3 */\r
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+      }\r
+      else\r
+      {\r
+        /* Disable the OCREF clear feature for Channel 3 */\r
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+      }\r
+      break;\r
+    }\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+      {\r
+        /* Enable the OCREF clear feature for Channel 4 */\r
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+      }\r
+      else\r
+      {\r
+        /* Disable the OCREF clear feature for Channel 4 */\r
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+      }\r
+      break;\r
+    }\r
+    case TIM_CHANNEL_5:\r
+    {\r
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+      {\r
+        /* Enable the OCREF clear feature for Channel 5 */\r
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
+      }\r
+      else\r
+      {\r
+        /* Disable the OCREF clear feature for Channel 5 */\r
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
+      }\r
+      break;\r
+    }\r
+    case TIM_CHANNEL_6:\r
+    {\r
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+      {\r
+        /* Enable the OCREF clear feature for Channel 6 */\r
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
+      }\r
+      else\r
+      {\r
+        /* Disable the OCREF clear feature for Channel 6 */\r
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
+      }\r
+      break;\r
+    }\r
+    default:\r
+      break;\r
+  }\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief   Configures the clock source to be used\r
+  * @param  htim TIM handle\r
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that\r
+  *         contains the clock source information for the TIM peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
+\r
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
+  tmpsmcr = htim->Instance->SMCR;\r
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+  htim->Instance->SMCR = tmpsmcr;\r
+\r
+  switch (sClockSourceConfig->ClockSource)\r
+  {\r
+    case TIM_CLOCKSOURCE_INTERNAL:\r
+    {\r
+      assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+      break;\r
+    }\r
+\r
+    case TIM_CLOCKSOURCE_ETRMODE1:\r
+    {\r
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/\r
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+\r
+      /* Check ETR input conditioning related parameters */\r
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+      /* Configure the ETR Clock source */\r
+      TIM_ETR_SetConfig(htim->Instance,\r
+                        sClockSourceConfig->ClockPrescaler,\r
+                        sClockSourceConfig->ClockPolarity,\r
+                        sClockSourceConfig->ClockFilter);\r
+\r
+      /* Select the External clock mode1 and the ETRF trigger */\r
+      tmpsmcr = htim->Instance->SMCR;\r
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
+      /* Write to TIMx SMCR */\r
+      htim->Instance->SMCR = tmpsmcr;\r
+      break;\r
+    }\r
+\r
+    case TIM_CLOCKSOURCE_ETRMODE2:\r
+    {\r
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/\r
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));\r
+\r
+      /* Check ETR input conditioning related parameters */\r
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+      /* Configure the ETR Clock source */\r
+      TIM_ETR_SetConfig(htim->Instance,\r
+                        sClockSourceConfig->ClockPrescaler,\r
+                        sClockSourceConfig->ClockPolarity,\r
+                        sClockSourceConfig->ClockFilter);\r
+      /* Enable the External clock mode2 */\r
+      htim->Instance->SMCR |= TIM_SMCR_ECE;\r
+      break;\r
+    }\r
+\r
+    case TIM_CLOCKSOURCE_TI1:\r
+    {\r
+      /* Check whether or not the timer instance supports external clock mode 1 */\r
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+      /* Check TI1 input conditioning related parameters */\r
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+      TIM_TI1_ConfigInputStage(htim->Instance,\r
+                               sClockSourceConfig->ClockPolarity,\r
+                               sClockSourceConfig->ClockFilter);\r
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CLOCKSOURCE_TI2:\r
+    {\r
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/\r
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+      /* Check TI2 input conditioning related parameters */\r
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+      TIM_TI2_ConfigInputStage(htim->Instance,\r
+                               sClockSourceConfig->ClockPolarity,\r
+                               sClockSourceConfig->ClockFilter);\r
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CLOCKSOURCE_TI1ED:\r
+    {\r
+      /* Check whether or not the timer instance supports external clock mode 1 */\r
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+      /* Check TI1 input conditioning related parameters */\r
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+      TIM_TI1_ConfigInputStage(htim->Instance,\r
+                               sClockSourceConfig->ClockPolarity,\r
+                               sClockSourceConfig->ClockFilter);\r
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
+      break;\r
+    }\r
+\r
+    case TIM_CLOCKSOURCE_ITR0:\r
+    case TIM_CLOCKSOURCE_ITR1:\r
+    case TIM_CLOCKSOURCE_ITR2:\r
+    case TIM_CLOCKSOURCE_ITR3:\r
+    {\r
+      /* Check whether or not the timer instance supports internal trigger input */\r
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+\r
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input\r
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input\r
+  * @param  htim TIM handle.\r
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the\r
+  *         output of a XOR gate.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
+  *            pins are connected to the TI1 input (XOR combination)\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
+{\r
+  uint32_t tmpcr2;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
+\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 = htim->Instance->CR2;\r
+\r
+  /* Reset the TI1 selection */\r
+  tmpcr2 &= ~TIM_CR2_TI1S;\r
+\r
+  /* Set the TI1 selection */\r
+  tmpcr2 |= TI1_Selection;\r
+\r
+  /* Write to TIMxCR2 */\r
+  htim->Instance->CR2 = tmpcr2;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIM in Slave mode\r
+  * @param  htim TIM handle.\r
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+  *         contains the selected trigger (internal trigger input, filtered\r
+  *         timer input or external trigger input) and the Slave mode\r
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+  {\r
+    htim->State = HAL_TIM_STATE_READY;\r
+    __HAL_UNLOCK(htim);\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Disable Trigger Interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+  /* Disable Trigger DMA request */\r
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIM in Slave mode in interrupt mode\r
+  * @param  htim TIM handle.\r
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+  *         contains the selected trigger (internal trigger input, filtered\r
+  *         timer input or external trigger input) and the Slave mode\r
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,\r
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+  {\r
+    htim->State = HAL_TIM_STATE_READY;\r
+    __HAL_UNLOCK(htim);\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Enable Trigger Interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+  /* Disable Trigger DMA request */\r
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Read the captured value from Capture Compare unit\r
+  * @param  htim TIM handle.\r
+  * @param  Channel TIM Channels to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+  * @retval Captured value\r
+  */\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpreg = 0U;\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+      /* Return the capture 1 value */\r
+      tmpreg =  htim->Instance->CCR1;\r
+\r
+      break;\r
+    }\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+      /* Return the capture 2 value */\r
+      tmpreg =   htim->Instance->CCR2;\r
+\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+      /* Return the capture 3 value */\r
+      tmpreg =   htim->Instance->CCR3;\r
+\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_4:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+      /* Return the capture 4 value */\r
+      tmpreg =   htim->Instance->CCR4;\r
+\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  return tmpreg;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+  *  @brief    TIM Callbacks functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                        ##### TIM Callbacks functions #####\r
+  ==============================================================================\r
+ [..]\r
+   This section provides TIM callback functions:\r
+   (+) TIM Period elapsed callback\r
+   (+) TIM Output Compare callback\r
+   (+) TIM Input capture callback\r
+   (+) TIM Trigger callback\r
+   (+) TIM Error callback\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Period elapsed callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Period elapsed half complete callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Output Compare callback in non-blocking mode\r
+  * @param  htim TIM OC handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Input Capture callback in non-blocking mode\r
+  * @param  htim TIM IC handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Input Capture half complete callback in non-blocking mode\r
+  * @param  htim TIM IC handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  PWM Pulse finished callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Hall Trigger detection callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_TriggerCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Timer error callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIM_ErrorCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback\r
+  * @param htim tim handle\r
+  * @param CallbackID ID of the callback to be registered\r
+  *        This parameter can be one of the following values:\r
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
+  *          @param pCallback pointer to the callback function\r
+  *          @retval status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\r
+                                           pTIM_CallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+  /* Process locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  if (htim->State == HAL_TIM_STATE_READY)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+        htim->Base_MspInitCallback                 = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+        htim->Base_MspDeInitCallback               = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPINIT_CB_ID :\r
+        htim->IC_MspInitCallback                   = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+        htim->IC_MspDeInitCallback                 = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPINIT_CB_ID :\r
+        htim->OC_MspInitCallback                   = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+        htim->OC_MspDeInitCallback                 = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+        htim->PWM_MspInitCallback                  = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+        htim->PWM_MspDeInitCallback                = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+        htim->OnePulse_MspInitCallback             = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+        htim->OnePulse_MspDeInitCallback           = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+        htim->Encoder_MspInitCallback              = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+        htim->Encoder_MspDeInitCallback            = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+        htim->HallSensor_MspInitCallback           = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+        htim->HallSensor_MspDeInitCallback         = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+        htim->PeriodElapsedCallback                = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_TRIGGER_CB_ID :\r
+        htim->TriggerCallback                      = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+        htim->TriggerHalfCpltCallback              = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_IC_CAPTURE_CB_ID :\r
+        htim->IC_CaptureCallback                   = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+        htim->IC_CaptureHalfCpltCallback           = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+        htim->OC_DelayElapsedCallback              = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+        htim->PWM_PulseFinishedCallback            = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ERROR_CB_ID :\r
+        htim->ErrorCallback                        = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_COMMUTATION_CB_ID :\r
+        htim->CommutationCallback                  = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
+        htim->CommutationHalfCpltCallback          = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_BREAK_CB_ID :\r
+        htim->BreakCallback                        = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_BREAK2_CB_ID :\r
+        htim->Break2Callback                       = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+        htim->Base_MspInitCallback         = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+        htim->Base_MspDeInitCallback       = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPINIT_CB_ID :\r
+        htim->IC_MspInitCallback           = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+        htim->IC_MspDeInitCallback         = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPINIT_CB_ID :\r
+        htim->OC_MspInitCallback           = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+        htim->OC_MspDeInitCallback         = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+        htim->PWM_MspInitCallback          = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+        htim->PWM_MspDeInitCallback        = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+        htim->OnePulse_MspInitCallback     = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+        htim->OnePulse_MspDeInitCallback   = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+        htim->Encoder_MspInitCallback      = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+        htim->Encoder_MspDeInitCallback    = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+        htim->HallSensor_MspInitCallback   = pCallback;\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+        htim->HallSensor_MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister a TIM callback\r
+  *         TIM callback is redirected to the weak predefined callback\r
+  * @param htim tim handle\r
+  * @param CallbackID ID of the callback to be unregistered\r
+  *        This parameter can be one of the following values:\r
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
+  *          @retval status\r
+  */\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  /* Process locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  if (htim->State == HAL_TIM_STATE_READY)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPINIT_CB_ID :\r
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPINIT_CB_ID :\r
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */\r
+        break;\r
+\r
+      case HAL_TIM_TRIGGER_CB_ID :\r
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */\r
+        break;\r
+\r
+      case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */\r
+        break;\r
+\r
+      case HAL_TIM_IC_CAPTURE_CB_ID :\r
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */\r
+        break;\r
+\r
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */\r
+        break;\r
+\r
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ERROR_CB_ID :\r
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */\r
+        break;\r
+\r
+      case HAL_TIM_COMMUTATION_CB_ID :\r
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */\r
+        break;\r
+\r
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */\r
+        break;\r
+\r
+      case HAL_TIM_BREAK_CB_ID :\r
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */\r
+        break;\r
+\r
+      case HAL_TIM_BREAK2_CB_ID :\r
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */\r
+        break;\r
+\r
+      default :\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPINIT_CB_ID :\r
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPINIT_CB_ID :\r
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */\r
+        break;\r
+\r
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */\r
+        break;\r
+\r
+      default :\r
+        /* Return error status */\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Return error status */\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return status;\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+  *  @brief   TIM Peripheral State functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                        ##### Peripheral State functions #####\r
+  ==============================================================================\r
+    [..]\r
+    This subsection permits to get in run-time the status of the peripheral\r
+    and the data flow.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Return the TIM Base handle state.\r
+  * @param  htim TIM Base handle\r
+  * @retval HAL state\r
+  */\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+  return htim->State;\r
+}\r
+\r
+/**\r
+  * @brief  Return the TIM OC handle state.\r
+  * @param  htim TIM Output Compare handle\r
+  * @retval HAL state\r
+  */\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+  return htim->State;\r
+}\r
+\r
+/**\r
+  * @brief  Return the TIM PWM handle state.\r
+  * @param  htim TIM handle\r
+  * @retval HAL state\r
+  */\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+  return htim->State;\r
+}\r
+\r
+/**\r
+  * @brief  Return the TIM Input Capture handle state.\r
+  * @param  htim TIM IC handle\r
+  * @retval HAL state\r
+  */\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+  return htim->State;\r
+}\r
+\r
+/**\r
+  * @brief  Return the TIM One Pulse Mode handle state.\r
+  * @param  htim TIM OPM handle\r
+  * @retval HAL state\r
+  */\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+  return htim->State;\r
+}\r
+\r
+/**\r
+  * @brief  Return the TIM Encoder Mode handle state.\r
+  * @param  htim TIM Encoder Interface handle\r
+  * @retval HAL state\r
+  */\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+  return htim->State;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  TIM DMA error callback\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->ErrorCallback(htim);\r
+#else\r
+  HAL_TIM_ErrorCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Delay Pulse complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+  HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Delay Pulse half complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);\r
+#else\r
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Capture complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->IC_CaptureCallback(htim);\r
+#else\r
+  HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Capture half complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+  }\r
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+  {\r
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->IC_CaptureHalfCpltCallback(htim);\r
+#else\r
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Period Elapse complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->PeriodElapsedCallback(htim);\r
+#else\r
+  HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Period Elapse half complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->PeriodElapsedHalfCpltCallback(htim);\r
+#else\r
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Trigger callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->TriggerCallback(htim);\r
+#else\r
+  HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Trigger half complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->TriggerHalfCpltCallback(htim);\r
+#else\r
+  HAL_TIM_TriggerHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  Time Base configuration\r
+  * @param  TIMx TIM peripheral\r
+  * @param  Structure TIM Base configuration structure\r
+  * @retval None\r
+  */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
+{\r
+  uint32_t tmpcr1;\r
+  tmpcr1 = TIMx->CR1;\r
+\r
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))\r
+  {\r
+    /* Select the Counter Mode */\r
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
+    tmpcr1 |= Structure->CounterMode;\r
+  }\r
+\r
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))\r
+  {\r
+    /* Set the clock division */\r
+    tmpcr1 &= ~TIM_CR1_CKD;\r
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
+  }\r
+\r
+  /* Set the auto-reload preload */\r
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);\r
+\r
+  TIMx->CR1 = tmpcr1;\r
+\r
+  /* Set the Autoreload value */\r
+  TIMx->ARR = (uint32_t)Structure->Period ;\r
+\r
+  /* Set the Prescaler value */\r
+  TIMx->PSC = Structure->Prescaler;\r
+\r
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))\r
+  {\r
+    /* Set the Repetition Counter value */\r
+    TIMx->RCR = Structure->RepetitionCounter;\r
+  }\r
+\r
+  /* Generate an update event to reload the Prescaler\r
+     and the repetition counter (only for advanced timer) value immediately */\r
+  TIMx->EGR = TIM_EGR_UG;\r
+}\r
+\r
+/**\r
+  * @brief  Timer Output Compare 1 configuration\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  OC_Config The ouput configuration structure\r
+  * @retval None\r
+  */\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+  uint32_t tmpccmrx;\r
+  uint32_t tmpccer;\r
+  uint32_t tmpcr2;\r
+\r
+  /* Disable the Channel 1: Reset the CC1E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC1E;\r
+\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 =  TIMx->CR2;\r
+\r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmrx = TIMx->CCMR1;\r
+\r
+  /* Reset the Output Compare Mode Bits */\r
+  tmpccmrx &= ~TIM_CCMR1_OC1M;\r
+  tmpccmrx &= ~TIM_CCMR1_CC1S;\r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= OC_Config->OCMode;\r
+\r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= ~TIM_CCER_CC1P;\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= OC_Config->OCPolarity;\r
+\r
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))\r
+  {\r
+    /* Check parameters */\r
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+    /* Reset the Output N Polarity level */\r
+    tmpccer &= ~TIM_CCER_CC1NP;\r
+    /* Set the Output N Polarity */\r
+    tmpccer |= OC_Config->OCNPolarity;\r
+    /* Reset the Output N State */\r
+    tmpccer &= ~TIM_CCER_CC1NE;\r
+  }\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+  {\r
+    /* Check parameters */\r
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+    /* Reset the Output Compare and Output Compare N IDLE State */\r
+    tmpcr2 &= ~TIM_CR2_OIS1;\r
+    tmpcr2 &= ~TIM_CR2_OIS1N;\r
+    /* Set the Output Idle state */\r
+    tmpcr2 |= OC_Config->OCIdleState;\r
+    /* Set the Output N Idle state */\r
+    tmpcr2 |= OC_Config->OCNIdleState;\r
+  }\r
+\r
+  /* Write to TIMx CR2 */\r
+  TIMx->CR2 = tmpcr2;\r
+\r
+  /* Write to TIMx CCMR1 */\r
+  TIMx->CCMR1 = tmpccmrx;\r
+\r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR1 = OC_Config->Pulse;\r
+\r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Timer Output Compare 2 configuration\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  OC_Config The ouput configuration structure\r
+  * @retval None\r
+  */\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+  uint32_t tmpccmrx;\r
+  uint32_t tmpccer;\r
+  uint32_t tmpcr2;\r
+\r
+  /* Disable the Channel 2: Reset the CC2E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC2E;\r
+\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 =  TIMx->CR2;\r
+\r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmrx = TIMx->CCMR1;\r
+\r
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+  tmpccmrx &= ~TIM_CCMR1_OC2M;\r
+  tmpccmrx &= ~TIM_CCMR1_CC2S;\r
+\r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= ~TIM_CCER_CC2P;\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (OC_Config->OCPolarity << 4U);\r
+\r
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))\r
+  {\r
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+    /* Reset the Output N Polarity level */\r
+    tmpccer &= ~TIM_CCER_CC2NP;\r
+    /* Set the Output N Polarity */\r
+    tmpccer |= (OC_Config->OCNPolarity << 4U);\r
+    /* Reset the Output N State */\r
+    tmpccer &= ~TIM_CCER_CC2NE;\r
+\r
+  }\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+  {\r
+    /* Check parameters */\r
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+    /* Reset the Output Compare and Output Compare N IDLE State */\r
+    tmpcr2 &= ~TIM_CR2_OIS2;\r
+    tmpcr2 &= ~TIM_CR2_OIS2N;\r
+    /* Set the Output Idle state */\r
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);\r
+    /* Set the Output N Idle state */\r
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);\r
+  }\r
+\r
+  /* Write to TIMx CR2 */\r
+  TIMx->CR2 = tmpcr2;\r
+\r
+  /* Write to TIMx CCMR1 */\r
+  TIMx->CCMR1 = tmpccmrx;\r
+\r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR2 = OC_Config->Pulse;\r
+\r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Timer Output Compare 3 configuration\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  OC_Config The ouput configuration structure\r
+  * @retval None\r
+  */\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+  uint32_t tmpccmrx;\r
+  uint32_t tmpccer;\r
+  uint32_t tmpcr2;\r
+\r
+  /* Disable the Channel 3: Reset the CC2E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC3E;\r
+\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 =  TIMx->CR2;\r
+\r
+  /* Get the TIMx CCMR2 register value */\r
+  tmpccmrx = TIMx->CCMR2;\r
+\r
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+  tmpccmrx &= ~TIM_CCMR2_OC3M;\r
+  tmpccmrx &= ~TIM_CCMR2_CC3S;\r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= OC_Config->OCMode;\r
+\r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= ~TIM_CCER_CC3P;\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (OC_Config->OCPolarity << 8U);\r
+\r
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))\r
+  {\r
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+    /* Reset the Output N Polarity level */\r
+    tmpccer &= ~TIM_CCER_CC3NP;\r
+    /* Set the Output N Polarity */\r
+    tmpccer |= (OC_Config->OCNPolarity << 8U);\r
+    /* Reset the Output N State */\r
+    tmpccer &= ~TIM_CCER_CC3NE;\r
+  }\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+  {\r
+    /* Check parameters */\r
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+    /* Reset the Output Compare and Output Compare N IDLE State */\r
+    tmpcr2 &= ~TIM_CR2_OIS3;\r
+    tmpcr2 &= ~TIM_CR2_OIS3N;\r
+    /* Set the Output Idle state */\r
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);\r
+    /* Set the Output N Idle state */\r
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);\r
+  }\r
+\r
+  /* Write to TIMx CR2 */\r
+  TIMx->CR2 = tmpcr2;\r
+\r
+  /* Write to TIMx CCMR2 */\r
+  TIMx->CCMR2 = tmpccmrx;\r
+\r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR3 = OC_Config->Pulse;\r
+\r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Timer Output Compare 4 configuration\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  OC_Config The ouput configuration structure\r
+  * @retval None\r
+  */\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+  uint32_t tmpccmrx;\r
+  uint32_t tmpccer;\r
+  uint32_t tmpcr2;\r
+\r
+  /* Disable the Channel 4: Reset the CC4E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC4E;\r
+\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 =  TIMx->CR2;\r
+\r
+  /* Get the TIMx CCMR2 register value */\r
+  tmpccmrx = TIMx->CCMR2;\r
+\r
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+  tmpccmrx &= ~TIM_CCMR2_OC4M;\r
+  tmpccmrx &= ~TIM_CCMR2_CC4S;\r
+\r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= ~TIM_CCER_CC4P;\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (OC_Config->OCPolarity << 12U);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+  {\r
+    /* Check parameters */\r
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+    /* Reset the Output Compare IDLE State */\r
+    tmpcr2 &= ~TIM_CR2_OIS4;\r
+\r
+    /* Set the Output Idle state */\r
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);\r
+  }\r
+\r
+  /* Write to TIMx CR2 */\r
+  TIMx->CR2 = tmpcr2;\r
+\r
+  /* Write to TIMx CCMR2 */\r
+  TIMx->CCMR2 = tmpccmrx;\r
+\r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR4 = OC_Config->Pulse;\r
+\r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Timer Output Compare 5 configuration\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  OC_Config The ouput configuration structure\r
+  * @retval None\r
+  */\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,\r
+                              TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+  uint32_t tmpccmrx;\r
+  uint32_t tmpccer;\r
+  uint32_t tmpcr2;\r
+\r
+  /* Disable the output: Reset the CCxE Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC5E;\r
+\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 =  TIMx->CR2;\r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmrx = TIMx->CCMR3;\r
+\r
+  /* Reset the Output Compare Mode Bits */\r
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);\r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= OC_Config->OCMode;\r
+\r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= ~TIM_CCER_CC5P;\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (OC_Config->OCPolarity << 16U);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+  {\r
+    /* Reset the Output Compare IDLE State */\r
+    tmpcr2 &= ~TIM_CR2_OIS5;\r
+    /* Set the Output Idle state */\r
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);\r
+  }\r
+  /* Write to TIMx CR2 */\r
+  TIMx->CR2 = tmpcr2;\r
+\r
+  /* Write to TIMx CCMR3 */\r
+  TIMx->CCMR3 = tmpccmrx;\r
+\r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR5 = OC_Config->Pulse;\r
+\r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Timer Output Compare 6 configuration\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  OC_Config The ouput configuration structure\r
+  * @retval None\r
+  */\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,\r
+                              TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+  uint32_t tmpccmrx;\r
+  uint32_t tmpccer;\r
+  uint32_t tmpcr2;\r
+\r
+  /* Disable the output: Reset the CCxE Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC6E;\r
+\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 =  TIMx->CR2;\r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmrx = TIMx->CCMR3;\r
+\r
+  /* Reset the Output Compare Mode Bits */\r
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);\r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (OC_Config->OCPolarity << 20U);\r
+\r
+  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+  {\r
+    /* Reset the Output Compare IDLE State */\r
+    tmpcr2 &= ~TIM_CR2_OIS6;\r
+    /* Set the Output Idle state */\r
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);\r
+  }\r
+\r
+  /* Write to TIMx CR2 */\r
+  TIMx->CR2 = tmpcr2;\r
+\r
+  /* Write to TIMx CCMR3 */\r
+  TIMx->CCMR3 = tmpccmrx;\r
+\r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR6 = OC_Config->Pulse;\r
+\r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Slave Timer configuration function\r
+  * @param  htim TIM handle\r
+  * @param  sSlaveConfig Slave timer configuration\r
+  * @retval None\r
+  */\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+  uint32_t tmpsmcr;\r
+  uint32_t tmpccmr1;\r
+  uint32_t tmpccer;\r
+\r
+  /* Get the TIMx SMCR register value */\r
+  tmpsmcr = htim->Instance->SMCR;\r
+\r
+  /* Reset the Trigger Selection Bits */\r
+  tmpsmcr &= ~TIM_SMCR_TS;\r
+  /* Set the Input Trigger source */\r
+  tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+  /* Reset the slave mode Bits */\r
+  tmpsmcr &= ~TIM_SMCR_SMS;\r
+  /* Set the slave mode */\r
+  tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+  /* Write to TIMx SMCR */\r
+  htim->Instance->SMCR = tmpsmcr;\r
+\r
+  /* Configure the trigger prescaler, filter, and polarity */\r
+  switch (sSlaveConfig->InputTrigger)\r
+  {\r
+    case TIM_TS_ETRF:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+      /* Configure the ETR Trigger source */\r
+      TIM_ETR_SetConfig(htim->Instance,\r
+                        sSlaveConfig->TriggerPrescaler,\r
+                        sSlaveConfig->TriggerPolarity,\r
+                        sSlaveConfig->TriggerFilter);\r
+      break;\r
+    }\r
+\r
+    case TIM_TS_TI1F_ED:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+\r
+      /* Disable the Channel 1: Reset the CC1E Bit */\r
+      tmpccer = htim->Instance->CCER;\r
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+      tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+      /* Set the filter */\r
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);\r
+\r
+      /* Write to TIMx CCMR1 and CCER registers */\r
+      htim->Instance->CCMR1 = tmpccmr1;\r
+      htim->Instance->CCER = tmpccer;\r
+      break;\r
+    }\r
+\r
+    case TIM_TS_TI1FP1:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+      /* Configure TI1 Filter and Polarity */\r
+      TIM_TI1_ConfigInputStage(htim->Instance,\r
+                               sSlaveConfig->TriggerPolarity,\r
+                               sSlaveConfig->TriggerFilter);\r
+      break;\r
+    }\r
+\r
+    case TIM_TS_TI2FP2:\r
+    {\r
+      /* Check the parameters */\r
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+      /* Configure TI2 Filter and Polarity */\r
+      TIM_TI2_ConfigInputStage(htim->Instance,\r
+                               sSlaveConfig->TriggerPolarity,\r
+                               sSlaveConfig->TriggerFilter);\r
+      break;\r
+    }\r
+\r
+    case TIM_TS_ITR0:\r
+    case TIM_TS_ITR1:\r
+    case TIM_TS_ITR2:\r
+    case TIM_TS_ITR3:\r
+    {\r
+      /* Check the parameter */\r
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI1 as Input.\r
+  * @param  TIMx to select the TIM peripheral.\r
+  * @param  TIM_ICPolarity The Input Polarity.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICPOLARITY_RISING\r
+  *            @arg TIM_ICPOLARITY_FALLING\r
+  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
+  * @param  TIM_ICSelection specifies the input to be used.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.\r
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.\r
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
+  *          This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1\r
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be\r
+  *        protected against un-initialized filter and polarity values.\r
+  */\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+                       uint32_t TIM_ICFilter)\r
+{\r
+  uint32_t tmpccmr1;\r
+  uint32_t tmpccer;\r
+\r
+  /* Disable the Channel 1: Reset the CC1E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC1E;\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  tmpccer = TIMx->CCER;\r
+\r
+  /* Select the Input */\r
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
+  {\r
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
+    tmpccmr1 |= TIM_ICSelection;\r
+  }\r
+  else\r
+  {\r
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
+  }\r
+\r
+  /* Set the filter */\r
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);\r
+\r
+  /* Select the Polarity and set the CC1E Bit */\r
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+\r
+  /* Write to TIMx CCMR1 and CCER registers */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the Polarity and Filter for TI1.\r
+  * @param  TIMx to select the TIM peripheral.\r
+  * @param  TIM_ICPolarity The Input Polarity.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICPOLARITY_RISING\r
+  *            @arg TIM_ICPOLARITY_FALLING\r
+  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
+  *          This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  */\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+  uint32_t tmpccmr1;\r
+  uint32_t tmpccer;\r
+\r
+  /* Disable the Channel 1: Reset the CC1E Bit */\r
+  tmpccer = TIMx->CCER;\r
+  TIMx->CCER &= ~TIM_CCER_CC1E;\r
+  tmpccmr1 = TIMx->CCMR1;\r
+\r
+  /* Set the filter */\r
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+  tmpccmr1 |= (TIM_ICFilter << 4U);\r
+\r
+  /* Select the Polarity and set the CC1E Bit */\r
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+  tmpccer |= TIM_ICPolarity;\r
+\r
+  /* Write to TIMx CCMR1 and CCER registers */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI2 as Input.\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  TIM_ICPolarity The Input Polarity.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICPOLARITY_RISING\r
+  *            @arg TIM_ICPOLARITY_FALLING\r
+  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
+  * @param  TIM_ICSelection specifies the input to be used.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.\r
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.\r
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
+  *          This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2\r
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be\r
+  *        protected against un-initialized filter and polarity values.\r
+  */\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+                              uint32_t TIM_ICFilter)\r
+{\r
+  uint32_t tmpccmr1;\r
+  uint32_t tmpccer;\r
+\r
+  /* Disable the Channel 2: Reset the CC2E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC2E;\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  tmpccer = TIMx->CCER;\r
+\r
+  /* Select the Input */\r
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
+  tmpccmr1 |= (TIM_ICSelection << 8U);\r
+\r
+  /* Set the filter */\r
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);\r
+\r
+  /* Select the Polarity and set the CC2E Bit */\r
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+\r
+  /* Write to TIMx CCMR1 and CCER registers */\r
+  TIMx->CCMR1 = tmpccmr1 ;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the Polarity and Filter for TI2.\r
+  * @param  TIMx to select the TIM peripheral.\r
+  * @param  TIM_ICPolarity The Input Polarity.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICPOLARITY_RISING\r
+  *            @arg TIM_ICPOLARITY_FALLING\r
+  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
+  *          This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  */\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+  uint32_t tmpccmr1;\r
+  uint32_t tmpccer;\r
+\r
+  /* Disable the Channel 2: Reset the CC2E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC2E;\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  tmpccer = TIMx->CCER;\r
+\r
+  /* Set the filter */\r
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+  tmpccmr1 |= (TIM_ICFilter << 12U);\r
+\r
+  /* Select the Polarity and set the CC2E Bit */\r
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+  tmpccer |= (TIM_ICPolarity << 4U);\r
+\r
+  /* Write to TIMx CCMR1 and CCER registers */\r
+  TIMx->CCMR1 = tmpccmr1 ;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI3 as Input.\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  TIM_ICPolarity The Input Polarity.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICPOLARITY_RISING\r
+  *            @arg TIM_ICPOLARITY_FALLING\r
+  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
+  * @param  TIM_ICSelection specifies the input to be used.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.\r
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.\r
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
+  *          This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4\r
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+  *        protected against un-initialized filter and polarity values.\r
+  */\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+                              uint32_t TIM_ICFilter)\r
+{\r
+  uint32_t tmpccmr2;\r
+  uint32_t tmpccer;\r
+\r
+  /* Disable the Channel 3: Reset the CC3E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC3E;\r
+  tmpccmr2 = TIMx->CCMR2;\r
+  tmpccer = TIMx->CCER;\r
+\r
+  /* Select the Input */\r
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
+  tmpccmr2 |= TIM_ICSelection;\r
+\r
+  /* Set the filter */\r
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);\r
+\r
+  /* Select the Polarity and set the CC3E Bit */\r
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+\r
+  /* Write to TIMx CCMR2 and CCER registers */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI4 as Input.\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  TIM_ICPolarity The Input Polarity.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICPOLARITY_RISING\r
+  *            @arg TIM_ICPOLARITY_FALLING\r
+  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
+  * @param  TIM_ICSelection specifies the input to be used.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.\r
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.\r
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
+  *          This parameter must be a value between 0x00 and 0x0F.\r
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3\r
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+  *        protected against un-initialized filter and polarity values.\r
+  * @retval None\r
+  */\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+                              uint32_t TIM_ICFilter)\r
+{\r
+  uint32_t tmpccmr2;\r
+  uint32_t tmpccer;\r
+\r
+  /* Disable the Channel 4: Reset the CC4E Bit */\r
+  TIMx->CCER &= ~TIM_CCER_CC4E;\r
+  tmpccmr2 = TIMx->CCMR2;\r
+  tmpccer = TIMx->CCER;\r
+\r
+  /* Select the Input */\r
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
+  tmpccmr2 |= (TIM_ICSelection << 8U);\r
+\r
+  /* Set the filter */\r
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);\r
+\r
+  /* Select the Polarity and set the CC4E Bit */\r
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+\r
+  /* Write to TIMx CCMR2 and CCER registers */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+  TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the Input Trigger source\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  InputTriggerSource The Input Trigger source.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_TS_ITR0: Internal Trigger 0\r
+  *            @arg TIM_TS_ITR1: Internal Trigger 1\r
+  *            @arg TIM_TS_ITR2: Internal Trigger 2\r
+  *            @arg TIM_TS_ITR3: Internal Trigger 3\r
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+  *            @arg TIM_TS_ETRF: External Trigger input\r
+  * @retval None\r
+  */\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Get the TIMx SMCR register value */\r
+  tmpsmcr = TIMx->SMCR;\r
+  /* Reset the TS Bits */\r
+  tmpsmcr &= ~TIM_SMCR_TS;\r
+  /* Set the Input Trigger source and the slave mode*/\r
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);\r
+  /* Write to TIMx SMCR */\r
+  TIMx->SMCR = tmpsmcr;\r
+}\r
+/**\r
+  * @brief  Configures the TIMx External Trigger (ETR).\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.\r
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.\r
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.\r
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.\r
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.\r
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.\r
+  * @param  ExtTRGFilter External Trigger Filter.\r
+  *          This parameter must be a value between 0x00 and 0x0F\r
+  * @retval None\r
+  */\r
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  tmpsmcr = TIMx->SMCR;\r
+\r
+  /* Reset the ETR Bits */\r
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+\r
+  /* Set the Prescaler, the Filter value and the Polarity */\r
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));\r
+\r
+  /* Write to TIMx SMCR */\r
+  TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIM Capture Compare Channel x.\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  Channel specifies the TIM Channel\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3\r
+  *            @arg TIM_CHANNEL_4: TIM Channel 4\r
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.\r
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)\r
+{\r
+  uint32_t tmp;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));\r
+  assert_param(IS_TIM_CHANNELS(Channel));\r
+\r
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
+\r
+  /* Reset the CCxE Bit */\r
+  TIMx->CCER &= ~tmp;\r
+\r
+  /* Set or reset the CCxE Bit */\r
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.\r
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r
+  *                the configuration information for TIM module.\r
+  * @retval None\r
+  */\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Reset the TIM callback to the legacy weak callbacks */\r
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */\r
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */\r
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */\r
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */\r
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */\r
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */\r
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */\r
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */\r
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */\r
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */\r
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */\r
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */\r
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */\r
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
new file mode 100644 (file)
index 0000000..559abea
--- /dev/null
@@ -0,0 +1,2373 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_tim_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   TIM HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Timer Extended peripheral:\r
+  *           + Time Hall Sensor Interface Initialization\r
+  *           + Time Hall Sensor Interface Start\r
+  *           + Time Complementary signal break and dead time configuration\r
+  *           + Time Master and Slave synchronization configuration\r
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)\r
+  *           + Time OCRef clear configuration\r
+  *           + Timer remapping capabilities configuration\r
+  @verbatim\r
+  ==============================================================================\r
+                      ##### TIMER Extended features #####\r
+  ==============================================================================\r
+  [..]\r
+    The Timer Extended features include:\r
+    (#) Complementary outputs with programmable dead-time for :\r
+        (++) Output Compare\r
+        (++) PWM generation (Edge and Center-aligned Mode)\r
+        (++) One-pulse mode output\r
+    (#) Synchronization circuit to control the timer with external signals and to\r
+        interconnect several timers together.\r
+    (#) Break input to put the timer output signals in reset state or in a known state.\r
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for\r
+        positioning purposes\r
+\r
+            ##### How to use this driver #####\r
+  ==============================================================================\r
+    [..]\r
+     (#) Initialize the TIM low level resources by implementing the following functions\r
+         depending on the selected feature:\r
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()\r
+\r
+     (#) Initialize the TIM low level resources :\r
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
+        (##) TIM pins configuration\r
+            (+++) Enable the clock for the TIM GPIOs using the following function:\r
+              __HAL_RCC_GPIOx_CLK_ENABLE();\r
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
+\r
+     (#) The external Clock can be configured, if needed (the default clock is the\r
+         internal clock from the APBx), using the following function:\r
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
+         any start function.\r
+\r
+     (#) Configure the TIM in the desired functioning mode using one of the\r
+         initialization function of this driver:\r
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the\r
+               Timer Hall Sensor Interface and the commutation event with the corresponding\r
+               Interrupt and DMA request if needed (Note that One Timer is used to interface\r
+               with the Hall sensor Interface and another Timer should be used to use\r
+               the commutation event).\r
+\r
+     (#) Activate the TIM peripheral using one of the start functions:\r
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()\r
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIMEx TIMEx\r
+  * @brief TIM Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+  * @brief    Timer Hall Sensor functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                      ##### Timer Hall Sensor functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Initialize and configure TIM HAL Sensor.\r
+    (+) De-initialize TIM HAL Sensor.\r
+    (+) Start the Hall Sensor Interface.\r
+    (+) Stop the Hall Sensor Interface.\r
+    (+) Start the Hall Sensor Interface and enable interrupts.\r
+    (+) Stop the Hall Sensor Interface and disable interrupts.\r
+    (+) Start the Hall Sensor Interface and enable DMA transfers.\r
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @param  sConfig TIM Hall Sensor configuration structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)\r
+{\r
+  TIM_OC_InitTypeDef OC_Config;\r
+\r
+  /* Check the TIM handle allocation */\r
+  if (htim == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+\r
+  if (htim->State == HAL_TIM_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+    /* Reset interrupt callbacks to legacy week callbacks */\r
+    TIM_ResetCallback(htim);\r
+\r
+    if (htim->HallSensor_MspInitCallback == NULL)\r
+    {\r
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;\r
+    }\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+    htim->HallSensor_MspInitCallback(htim);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+    HAL_TIMEx_HallSensor_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  /* Set the TIM state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Configure the Time base in the Encoder Mode */\r
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */\r
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r
+\r
+  /* Reset the IC1PSC Bits */\r
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+  /* Set the IC1PSC value */\r
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r
+\r
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */\r
+  htim->Instance->CR2 |= TIM_CR2_TI1S;\r
+\r
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r
+\r
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */\r
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r
+\r
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
+  OC_Config.OCMode = TIM_OCMODE_PWM2;\r
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
+  OC_Config.Pulse = sConfig->Commutation_Delay;\r
+\r
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r
+\r
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r
+    register to 101 */\r
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;\r
+\r
+  /* Initialize the TIM state*/\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the TIM Hall Sensor interface\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Disable the TIM Peripheral Clock */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  if (htim->HallSensor_MspDeInitCallback == NULL)\r
+  {\r
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  htim->HallSensor_MspDeInitCallback(htim);\r
+#else\r
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+  HAL_TIMEx_HallSensor_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+  /* Change TIM state */\r
+  htim->State = HAL_TIM_STATE_RESET;\r
+\r
+  /* Release Lock */\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM Hall Sensor MSP.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes TIM Hall Sensor MSP.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Hall Sensor Interface.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+  /* Enable the Input Capture channel 1\r
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Hall sensor Interface.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+  /* Disable the Input Capture channels 1, 2 and 3\r
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+  /* Enable the capture compare Interrupts 1 event */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+  /* Enable the Input Capture channel 1\r
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+  /* Disable the Input Capture channel 1\r
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+  /* Disable the capture compare Interrupts event */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @param  pData The destination Buffer address.\r
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if (((uint32_t)pData == 0U) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+  /* Enable the Input Capture channel 1\r
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+  /* Set the DMA Input Capture 1 Callbacks */\r
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+  /* Set the DMA error callback */\r
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+  /* Enable the DMA channel for Capture 1*/\r
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+  /* Enable the capture compare 1 Interrupt */\r
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.\r
+  * @param  htim TIM Hall Sensor Interface handle\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+  /* Disable the Input Capture channel 1\r
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+\r
+  /* Disable the capture compare Interrupts 1 event */\r
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+  *  @brief   Timer Complementary Output Compare functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+              ##### Timer Complementary Output Compare functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Start the Complementary Output Compare/PWM.\r
+    (+) Stop the Complementary Output Compare/PWM.\r
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.\r
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Starts the TIM Output Compare signal generation on the complementary\r
+  *         output.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Enable the Capture compare channel N */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Output Compare signal generation on the complementary\r
+  *         output.\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Disable the Capture compare channel N */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode\r
+  *         on the complementary output.\r
+  * @param  htim TIM OC handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Enable the TIM Output Compare interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Enable the TIM Output Compare interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Enable the TIM Output Compare interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the TIM Break interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+\r
+  /* Enable the Capture compare channel N */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode\r
+  *         on the complementary output.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpccer;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Output Compare interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Output Compare interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Output Compare interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Capture compare channel N */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+  tmpccer = htim->Instance->CCER;\r
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
+  {\r
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+  }\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode\r
+  *         on the complementary output.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @param  pData The source Buffer address.\r
+  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if (((uint32_t)pData == 0U) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do  */\r
+  }\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Output Compare DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Output Compare DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Output Compare DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the Capture compare channel N */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode\r
+  *         on the complementary output.\r
+  * @param  htim TIM Output Compare handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Output Compare DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Output Compare DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Output Compare DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the Capture compare channel N */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+  * @brief    Timer Complementary PWM functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                 ##### Timer Complementary PWM functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Start the Complementary PWM.\r
+    (+) Stop the Complementary PWM.\r
+    (+) Start the Complementary PWM and enable interrupts.\r
+    (+) Stop the Complementary PWM and disable interrupts.\r
+    (+) Start the Complementary PWM and enable DMA transfers.\r
+    (+) Stop the Complementary PWM and disable DMA transfers.\r
+    (+) Start the Complementary Input Capture measurement.\r
+    (+) Stop the Complementary Input Capture.\r
+    (+) Start the Complementary Input Capture and enable interrupts.\r
+    (+) Stop the Complementary Input Capture and disable interrupts.\r
+    (+) Start the Complementary Input Capture and enable DMA transfers.\r
+    (+) Stop the Complementary Input Capture and disable DMA transfers.\r
+    (+) Start the Complementary One Pulse generation.\r
+    (+) Stop the Complementary One Pulse.\r
+    (+) Start the Complementary One Pulse and enable interrupts.\r
+    (+) Stop the Complementary One Pulse and disable interrupts.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Starts the PWM signal generation on the complementary output.\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Enable the complementary PWM output  */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the PWM signal generation on the complementary output.\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  /* Disable the complementary PWM output  */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the PWM signal generation in interrupt mode on the\r
+  *         complementary output.\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Enable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Enable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Enable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the TIM Break interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+\r
+  /* Enable the complementary PWM output  */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the PWM signal generation in interrupt mode on the\r
+  *         complementary output.\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  uint32_t tmpccer;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3 interrupt */\r
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the complementary PWM output  */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+  tmpccer = htim->Instance->CCER;\r
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
+  {\r
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+  }\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the\r
+  *         complementary output\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @param  pData The source Buffer address.\r
+  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  if ((htim->State == HAL_TIM_STATE_BUSY))\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+  else if ((htim->State == HAL_TIM_STATE_READY))\r
+  {\r
+    if (((uint32_t)pData == 0U) && (Length > 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+    else\r
+    {\r
+      htim->State = HAL_TIM_STATE_BUSY;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* nothing to do */\r
+  }\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 2 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Set the DMA compare callbacks */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+      {\r
+        return HAL_ERROR;\r
+      }\r
+      /* Enable the TIM Capture/Compare 3 DMA request */\r
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Enable the complementary PWM output  */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+  {\r
+    __HAL_TIM_ENABLE(htim);\r
+  }\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary\r
+  *         output\r
+  * @param  htim TIM handle\r
+  * @param  Channel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+  switch (Channel)\r
+  {\r
+    case TIM_CHANNEL_1:\r
+    {\r
+      /* Disable the TIM Capture/Compare 1 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_2:\r
+    {\r
+      /* Disable the TIM Capture/Compare 2 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+      break;\r
+    }\r
+\r
+    case TIM_CHANNEL_3:\r
+    {\r
+      /* Disable the TIM Capture/Compare 3 DMA request */\r
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+      break;\r
+    }\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  /* Disable the complementary PWM output */\r
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+  * @brief    Timer Complementary One Pulse functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                ##### Timer Complementary One Pulse functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+    (+) Start the Complementary One Pulse generation.\r
+    (+) Stop the Complementary One Pulse.\r
+    (+) Start the Complementary One Pulse and enable interrupts.\r
+    (+) Stop the Complementary One Pulse and disable interrupts.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Starts the TIM One Pulse signal generation on the complementary\r
+  *         output.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+  /* Enable the complementary One Pulse output */\r
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM One Pulse signal generation on the complementary\r
+  *         output.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+  /* Disable the complementary One Pulse output */\r
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the\r
+  *         complementary channel.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channel to be enabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+  /* Enable the TIM Capture/Compare 1 interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+  /* Enable the TIM Capture/Compare 2 interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+\r
+  /* Enable the complementary One Pulse output */\r
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
+\r
+  /* Enable the Main Output */\r
+  __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the\r
+  *         complementary channel.\r
+  * @param  htim TIM One Pulse handle\r
+  * @param  OutputChannel TIM Channel to be disabled\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+  /* Disable the TIM Capture/Compare 1 interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+  /* Disable the TIM Capture/Compare 2 interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+\r
+  /* Disable the complementary One Pulse output */\r
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+\r
+  /* Disable the Main Output */\r
+  __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_TIM_DISABLE(htim);\r
+\r
+  /* Return function status */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+  * @brief    Peripheral Control functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                    ##### Peripheral Control functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides functions allowing to:\r
+      (+) Configure the commutation event in case of use of the Hall sensor interface.\r
+      (+) Configure Output channels for OC and PWM mode.\r
+\r
+      (+) Configure Complementary channels, break features and dead time.\r
+      (+) Configure Master synchronization.\r
+      (+) Configure timer remapping capabilities.\r
+      (+) Enable or disable channel grouping.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Configure the TIM commutation event sequence.\r
+  * @note  This function is mandatory to use the commutation event in order to\r
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r
+  *        the typical use of this feature is with the use of another Timer(interface Timer)\r
+  *        configured in Hall sensor interface, this interface Timer will generate the\r
+  *        commutation at its TRGO output (connected to Timer used in this function) each time\r
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+  * @param  htim TIM handle\r
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+  *            @arg TIM_TS_NONE: No trigger is needed\r
+  * @param  CommutationSource the Commutation Event source\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
+                                              uint32_t  CommutationSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+  __HAL_LOCK(htim);\r
+\r
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+  {\r
+    /* Select the Input trigger */\r
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+    htim->Instance->SMCR |= InputTrigger;\r
+  }\r
+\r
+  /* Select the Capture Compare preload feature */\r
+  htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+  /* Select the Commutation event source */\r
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+  htim->Instance->CR2 |= CommutationSource;\r
+\r
+  /* Disable Commutation Interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
+\r
+  /* Disable Commutation DMA request */\r
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TIM commutation event sequence with interrupt.\r
+  * @note  This function is mandatory to use the commutation event in order to\r
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r
+  *        the typical use of this feature is with the use of another Timer(interface Timer)\r
+  *        configured in Hall sensor interface, this interface Timer will generate the\r
+  *        commutation at its TRGO output (connected to Timer used in this function) each time\r
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+  * @param  htim TIM handle\r
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+  *            @arg TIM_TS_NONE: No trigger is needed\r
+  * @param  CommutationSource the Commutation Event source\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
+                                                 uint32_t  CommutationSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+  __HAL_LOCK(htim);\r
+\r
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+  {\r
+    /* Select the Input trigger */\r
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+    htim->Instance->SMCR |= InputTrigger;\r
+  }\r
+\r
+  /* Select the Capture Compare preload feature */\r
+  htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+  /* Select the Commutation event source */\r
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+  htim->Instance->CR2 |= CommutationSource;\r
+\r
+  /* Disable Commutation DMA request */\r
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+  /* Enable the Commutation Interrupt */\r
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TIM commutation event sequence with DMA.\r
+  * @note  This function is mandatory to use the commutation event in order to\r
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r
+  *        the typical use of this feature is with the use of another Timer(interface Timer)\r
+  *        configured in Hall sensor interface, this interface Timer will generate the\r
+  *        commutation at its TRGO output (connected to Timer used in this function) each time\r
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set\r
+  * @param  htim TIM handle\r
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+  *            @arg TIM_TS_NONE: No trigger is needed\r
+  * @param  CommutationSource the Commutation Event source\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
+                                                  uint32_t  CommutationSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+  __HAL_LOCK(htim);\r
+\r
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+  {\r
+    /* Select the Input trigger */\r
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+    htim->Instance->SMCR |= InputTrigger;\r
+  }\r
+\r
+  /* Select the Capture Compare preload feature */\r
+  htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+  /* Select the Commutation event source */\r
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+  htim->Instance->CR2 |= CommutationSource;\r
+\r
+  /* Enable the Commutation DMA Request */\r
+  /* Set the DMA Commutation Callback */\r
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
+  /* Set the DMA error callback */\r
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;\r
+\r
+  /* Disable Commutation Interrupt */\r
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
+\r
+  /* Enable the Commutation DMA Request */\r
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIM in master mode.\r
+  * @param  htim TIM handle.\r
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that\r
+  *         contains the selected trigger output (TRGO) and the Master/Slave\r
+  *         mode.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)\r
+{\r
+  uint32_t tmpcr2;\r
+  uint32_t tmpsmcr;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
+\r
+  /* Check input state */\r
+  __HAL_LOCK(htim);\r
+\r
+  /* Change the handler state */\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Get the TIMx CR2 register value */\r
+  tmpcr2 = htim->Instance->CR2;\r
+\r
+  /* Get the TIMx SMCR register value */\r
+  tmpsmcr = htim->Instance->SMCR;\r
+\r
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */\r
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));\r
+\r
+    /* Clear the MMS2 bits */\r
+    tmpcr2 &= ~TIM_CR2_MMS2;\r
+    /* Select the TRGO2 source*/\r
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;\r
+  }\r
+\r
+  /* Reset the MMS Bits */\r
+  tmpcr2 &= ~TIM_CR2_MMS;\r
+  /* Select the TRGO source */\r
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;\r
+\r
+  /* Reset the MSM Bit */\r
+  tmpsmcr &= ~TIM_SMCR_MSM;\r
+  /* Set master mode */\r
+  tmpsmcr |= sMasterConfig->MasterSlaveMode;\r
+\r
+  /* Update TIMx CR2 */\r
+  htim->Instance->CR2 = tmpcr2;\r
+\r
+  /* Update TIMx SMCR */\r
+  htim->Instance->SMCR = tmpsmcr;\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r
+  *         and the AOE(automatic output enable).\r
+  * @param  htim TIM handle\r
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that\r
+  *         contains the BDTR Register configuration  information for the TIM peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)\r
+{\r
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */\r
+  uint32_t tmpbdtr = 0U;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));\r
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r
+\r
+  /* Check input state */\r
+  __HAL_LOCK(htim);\r
+\r
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+\r
+  /* Set the BDTR bits */\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);\r
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));\r
+\r
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));\r
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));\r
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));\r
+\r
+    /* Set the BREAK2 input related BDTR bits */\r
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));\r
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);\r
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);\r
+  }\r
+\r
+  /* Set TIMx_BDTR */\r
+  htim->Instance->BDTR = tmpbdtr;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the break input source.\r
+  * @param  htim TIM handle.\r
+  * @param  BreakInput Break input to configure\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input\r
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input\r
+  * @param  sBreakInputConfig Break input source configuration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,\r
+                                             uint32_t BreakInput,\r
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)\r
+\r
+{\r
+  uint32_t tmporx;\r
+  uint32_t bkin_enable_mask = 0U;\r
+  uint32_t bkin_polarity_mask = 0U;\r
+  uint32_t bkin_enable_bitpos = 0U;\r
+  uint32_t bkin_polarity_bitpos = 0U;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));\r
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));\r
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));\r
+#if defined(DFSDM1_Channel0)\r
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+  {\r
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));\r
+  }\r
+#else\r
+  assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));\r
+#endif /* DFSDM1_Channel0 */\r
+\r
+  /* Check input state */\r
+  __HAL_LOCK(htim);\r
+\r
+  switch (sBreakInputConfig->Source)\r
+  {\r
+    case TIM_BREAKINPUTSOURCE_BKIN:\r
+    {\r
+      bkin_enable_mask = TIM1_OR2_BKINE;\r
+      bkin_enable_bitpos = TIM1_OR2_BKINE_Pos;\r
+      bkin_polarity_mask = TIM1_OR2_BKINP;\r
+      bkin_polarity_bitpos = TIM1_OR2_BKINP_Pos;\r
+      break;\r
+    }\r
+    case TIM_BREAKINPUTSOURCE_COMP1:\r
+    {\r
+      bkin_enable_mask = TIM1_OR2_BKCMP1E;\r
+      bkin_enable_bitpos = TIM1_OR2_BKCMP1E_Pos;\r
+      bkin_polarity_mask = TIM1_OR2_BKCMP1P;\r
+      bkin_polarity_bitpos = TIM1_OR2_BKCMP1P_Pos;\r
+      break;\r
+    }\r
+    case TIM_BREAKINPUTSOURCE_COMP2:\r
+    {\r
+      bkin_enable_mask = TIM1_OR2_BKCMP2E;\r
+      bkin_enable_bitpos = TIM1_OR2_BKCMP2E_Pos;\r
+      bkin_polarity_mask = TIM1_OR2_BKCMP2P;\r
+      bkin_polarity_bitpos = TIM1_OR2_BKCMP2P_Pos;\r
+      break;\r
+    }\r
+#if defined(DFSDM1_Channel0)\r
+    case TIM_BREAKINPUTSOURCE_DFSDM1:\r
+    {\r
+      bkin_enable_mask = TIM1_OR2_BKDF1BK0E;\r
+      bkin_enable_bitpos = 8U;\r
+      break;\r
+    }\r
+#endif /* DFSDM1_Channel0 */\r
+\r
+    default:\r
+      break;\r
+  }\r
+\r
+  switch (BreakInput)\r
+  {\r
+    case TIM_BREAKINPUT_BRK:\r
+    {\r
+      /* Get the TIMx_OR2 register value */\r
+      tmporx = htim->Instance->OR2;\r
+\r
+      /* Enable the break input */\r
+      tmporx &= ~bkin_enable_mask;\r
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+\r
+      /* Set the break input polarity */\r
+#if defined(DFSDM1_Channel0)\r
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+#endif /* DFSDM1_Channel0 */\r
+      {\r
+        tmporx &= ~bkin_polarity_mask;\r
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
+      }\r
+\r
+      /* Set TIMx_OR2 */\r
+      htim->Instance->OR2 = tmporx;\r
+      break;\r
+    }\r
+    case TIM_BREAKINPUT_BRK2:\r
+    {\r
+      /* Get the TIMx_OR3 register value */\r
+      tmporx = htim->Instance->OR3;\r
+\r
+      /* Enable the break input */\r
+      tmporx &= ~bkin_enable_mask;\r
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+\r
+      /* Set the break input polarity */\r
+#if defined(DFSDM1_Channel0)\r
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+#endif /* DFSDM1_Channel0 */\r
+      {\r
+        tmporx &= ~bkin_polarity_mask;\r
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
+      }\r
+\r
+      /* Set TIMx_OR3 */\r
+      htim->Instance->OR3 = tmporx;\r
+      break;\r
+    }\r
+    default:\r
+      break;\r
+  }\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Remapping input capabilities.\r
+  * @param  htim TIM handle.\r
+  * @param  Remap specifies the TIM remapping source.\r
+    @if STM32L422xx\r
+  *         For TIM1, the parameter is a combination of 2 fields (field1 | field2):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output\r
+  *\r
+  @endif\r
+@if STM32L486xx\r
+  *         For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM1_ETR_ADC3_NONE:           TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)\r
+  *            @arg TIM_TIM1_ETR_ADC3_AWD1:           TIM1_ETR is connected to ADC3 AWD1\r
+  *            @arg TIM_TIM1_ETR_ADC3_AWD2:           TIM1_ETR is connected to ADC3 AWD2\r
+  *            @arg TIM_TIM1_ETR_ADC3_AWD3:           TIM1_ETR is connected to ADC3 AWD3\r
+  *\r
+  *                   field3 can have the following values:\r
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output\r
+  *\r
+  *                   field4 can have the following values:\r
+  *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output\r
+  *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output\r
+  *            @note  When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant\r
+  @endif\r
+  @if STM32L443xx\r
+  *         For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2\r
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output\r
+  *\r
+  *                   field3 can have the following values:\r
+  *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output\r
+  *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output\r
+  *\r
+  *            @note  When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant\r
+  *\r
+  @endif\r
+  @if STM32L486xx\r
+  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM2_ITR1_TIM8_TRGO:          TIM2_ITR1 is connected to TIM8_TRGO\r
+  *            @arg TIM_TIM2_ITR1_OTG_FS_SOF:         TIM2_ITR1 is connected to OTG_FS SOF\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO\r
+  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE\r
+  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output\r
+  *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output\r
+  *\r
+  *                   field3 can have the following values:\r
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO\r
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output\r
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output\r
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output\r
+  @endif\r
+  @if STM32L422xx\r
+  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1\r
+  *            @arg TIM_TIM2_ITR1_USB_SOF:            TIM2_ITR1 is connected to USB SOF\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO\r
+  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE\r
+  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output\r
+  *\r
+  *                   field3 can have the following values:\r
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO\r
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output\r
+  *\r
+  @endif\r
+  @if STM32L443xx\r
+  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1\r
+  *            @arg TIM_TIM2_ITR1_USB_SOF:            TIM2_ITR1 is connected to USB SOF\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO\r
+  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE\r
+  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output\r
+  *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output\r
+  *\r
+  *                   field3 can have the following values:\r
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO\r
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output\r
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output\r
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output\r
+  *\r
+  @endif\r
+  @if STM32L486xx\r
+  *         For TIM3, the parameter is a combination 2 fields(field1 | field2):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output\r
+  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output\r
+  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM3_ETR_GPIO:                TIM3_ETR is connected to GPIO\r
+  *            @arg TIM_TIM3_ETR_COMP1:               TIM3_ETR is connected to COMP1 output\r
+  *\r
+  @endif\r
+  @if STM32L486xx\r
+  *         For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM8_ETR_ADC2_NONE:          TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)\r
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1\r
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2\r
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM8_ETR_ADC3_NONE:          TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)\r
+  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1\r
+  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2\r
+  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3\r
+  *\r
+  *                   field3 can have the following values:\r
+  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output\r
+  *\r
+  *                   field4 can have the following values:\r
+  *            @arg TIM_TIM8_ETR_COMP1:               TIM8_ETR is connected to COMP1 output\r
+  *            @arg TIM_TIM8_ETR_COMP2:               TIM8_ETR is connected to COMP2 output\r
+  *            @note  When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant\r
+  *\r
+  @endif\r
+  @if STM32L422xx\r
+  *         For TIM15, the parameter is a combination of 2 fields (field1 | field2):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection\r
+  *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
+  *\r
+  @endif\r
+  @if STM32L443xx\r
+  *         For TIM15, the parameter is a combination of 2 fields (field1 | field2):\r
+  *\r
+  *                   field1 can have the following values:\r
+  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE\r
+  *\r
+  *                   field2 can have the following values:\r
+  *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection\r
+  *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
+  *            @arg TIM_TIM15_ENCODERMODE_TIM3:      TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
+  *            @arg TIM_TIM15_ENCODERMODE_TIM4:      TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
+  *\r
+  @endif\r
+  @if STM32L486xx\r
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI\r
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE\r
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt\r
+  *\r
+  @endif\r
+  @if STM32L422xx\r
+  *         For TIM16, the parameter can have the following values:\r
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI\r
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE\r
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt\r
+  *            @arg TIM_TIM16_TI1_MSI:               TIM16 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)\r
+  *            @arg TIM_TIM16_TI1_HSE_32:            TIM16 TI1 is connected to HSE div 32  (note that HSE div 32 must be selected as RTC clock source)\r
+  *            @arg TIM_TIM16_TI1_MCO:               TIM16 TI1 is connected to MCO\r
+  *\r
+  @endif\r
+  @if STM32L443xx\r
+  *         For TIM16, the parameter can have the following values:\r
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI\r
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE\r
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt\r
+  *            @arg TIM_TIM16_TI1_MSI:               TIM16 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)\r
+  *            @arg TIM_TIM16_TI1_HSE_32:            TIM16 TI1 is connected to HSE div 32  (note that HSE div 32 must be selected as RTC clock source)\r
+  *            @arg TIM_TIM16_TI1_MCO:               TIM16 TI1 is connected to MCO\r
+  *\r
+  @endif\r
+  @if STM32L486xx\r
+  *         For TIM17, the parameter can have the following values:\r
+  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO\r
+  *            @arg TIM_TIM17_TI1_MSI:               TIM17 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)\r
+  *            @arg TIM_TIM17_TI1_HSE_32:            TIM17 TI1 is connected to HSE div 32\r
+  *            @arg TIM_TIM17_TI1_MCO:               TIM17 TI1 is connected to MCO\r
+  @endif\r
+  *\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r
+{\r
+  uint32_t tmpor1 = 0U;\r
+  uint32_t tmpor2 = 0U;\r
+\r
+  __HAL_LOCK(htim);\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_REMAP(Remap));\r
+\r
+  /* Set ETR_SEL bit field (if required) */\r
+  if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))\r
+  {\r
+    tmpor2 = htim->Instance->OR2;\r
+    tmpor2 &= ~TIM1_OR2_ETRSEL_Msk;\r
+    tmpor2 |= (Remap & TIM1_OR2_ETRSEL_Msk);\r
+\r
+    /* Set TIMx_OR2 */\r
+    htim->Instance->OR2 = tmpor2;\r
+  }\r
+\r
+  /* Set other remapping capabilities */\r
+  tmpor1 = Remap;\r
+  tmpor1 &= ~TIM1_OR2_ETRSEL_Msk;\r
+\r
+  /* Set TIMx_OR1 */\r
+  htim->Instance->OR1 = tmpor1;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Group channel 5 and channel 1, 2 or 3\r
+  * @param  htim TIM handle.\r
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.\r
+  *         This parameter can be any combination of the following values:\r
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC\r
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF\r
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF\r
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)\r
+{\r
+  /* Check parameters */\r
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));\r
+  assert_param(IS_TIM_GROUPCH5(Channels));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(htim);\r
+\r
+  htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+  /* Clear GC5Cx bit fields */\r
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);\r
+\r
+  /* Set GC5Cx bit fields */\r
+  htim->Instance->CCR5 |= Channels;\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+  __HAL_UNLOCK(htim);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
+  * @brief    Extended Callbacks functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                    ##### Extended Callbacks functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This section provides Extended TIM callback functions:\r
+    (+) Timer Commutation callback\r
+    (+) Timer Break callback\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Hall commutation changed callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIMEx_CommutCallback could be implemented in the user file\r
+   */\r
+}\r
+/**\r
+  * @brief  Hall commutation changed half complete callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Hall Break detection callback in non-blocking mode\r
+  * @param  htim TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_TIMEx_BreakCallback could be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Hall Break2 detection callback in non blocking mode\r
+  * @param  htim: TIM handle\r
+  * @retval None\r
+  */\r
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(htim);\r
+\r
+  /* NOTE : This function Should not be modified, when the callback is needed,\r
+            the HAL_TIMEx_Break2Callback could be implemented in the user file\r
+   */\r
+}\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
+  * @brief    Extended Peripheral State functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+                ##### Extended Peripheral State functions #####\r
+  ==============================================================================\r
+  [..]\r
+    This subsection permits to get in run-time the status of the peripheral\r
+    and the data flow.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Return the TIM Hall Sensor interface handle state.\r
+  * @param  htim TIM Hall Sensor handle\r
+  * @retval HAL state\r
+  */\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+  return htim->State;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  TIM DMA Commutation callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->CommutationCallback(htim);\r
+#else\r
+  HAL_TIMEx_CommutCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  TIM DMA Commutation half complete callback.\r
+  * @param  hdma pointer to DMA handle.\r
+  * @retval None\r
+  */\r
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  /* Change the htim state */\r
+  htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+  htim->CommutationHalfCpltCallback(htim);\r
+#else\r
+  HAL_TIMEx_CommutHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.\r
+  * @param  TIMx to select the TIM peripheral\r
+  * @param  Channel specifies the TIM Channel\r
+  *          This parameter can be one of the following values:\r
+  *            @arg TIM_CHANNEL_1: TIM Channel 1\r
+  *            @arg TIM_CHANNEL_2: TIM Channel 2\r
+  *            @arg TIM_CHANNEL_3: TIM Channel 3\r
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.\r
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.\r
+  * @retval None\r
+  */\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)\r
+{\r
+  uint32_t tmp;\r
+\r
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
+\r
+  /* Reset the CCxNE Bit */\r
+  TIMx->CCER &=  ~tmp;\r
+\r
+  /* Set or reset the CCxNE Bit */\r
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
+}\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
new file mode 100644 (file)
index 0000000..696c3f0
--- /dev/null
@@ -0,0 +1,4143 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_uart.c\r
+  * @author  MCD Application Team\r
+  * @brief   UART HAL module driver.\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\r
+  *           + Initialization and de-initialization functions\r
+  *           + IO operation functions\r
+  *           + Peripheral Control functions\r
+  *\r
+  *\r
+  @verbatim\r
+ ===============================================================================\r
+                        ##### How to use this driver #####\r
+ ===============================================================================\r
+  [..]\r
+    The UART HAL driver can be used as follows:\r
+\r
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).\r
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r
+        (++) Enable the USARTx interface clock.\r
+        (++) UART pins configuration:\r
+            (+++) Enable the clock for the UART GPIOs.\r
+            (+++) Configure these UART pins as alternate function pull-up.\r
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r
+             and HAL_UART_Receive_IT() APIs):\r
+            (+++) Configure the USARTx interrupt priority.\r
+            (+++) Enable the NVIC USART IRQ handle.\r
+        (++) UART interrupts handling:\r
+              -@@-  The specific UART interrupts (Transmission complete interrupt,\r
+                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)\r
+                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()\r
+                inside the transmit and receive processes.\r
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r
+             and HAL_UART_Receive_DMA() APIs):\r
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.\r
+            (+++) Enable the DMAx interface clock.\r
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r
+            (+++) Configure the DMA Tx/Rx channel.\r
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.\r
+\r
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware\r
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.\r
+\r
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)\r
+        in the huart handle AdvancedInit structure.\r
+\r
+    (#) For the UART asynchronous mode, initialize the UART registers by calling\r
+        the HAL_UART_Init() API.\r
+\r
+    (#) For the UART Half duplex mode, initialize the UART registers by calling\r
+        the HAL_HalfDuplex_Init() API.\r
+\r
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers\r
+        by calling the HAL_LIN_Init() API.\r
+\r
+    (#) For the UART Multiprocessor mode, initialize the UART registers\r
+        by calling the HAL_MultiProcessor_Init() API.\r
+\r
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers\r
+        by calling the HAL_RS485Ex_Init() API.\r
+\r
+    [..]\r
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),\r
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by\r
+        calling the customized HAL_UART_MspInit() API.\r
+\r
+    ##### Callback registration #####\r
+    ==================================\r
+\r
+    [..]\r
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1\r
+    allows the user to configure dynamically the driver callbacks.\r
+\r
+    [..]\r
+    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.\r
+    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:\r
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.\r
+    (+) TxCpltCallback            : Tx Complete Callback.\r
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.\r
+    (+) RxCpltCallback            : Rx Complete Callback.\r
+    (+) ErrorCallback             : Error Callback.\r
+    (+) AbortCpltCallback         : Abort Complete Callback.\r
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.\r
+    (+) WakeupCallback            : Wakeup Callback.\r
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.\r
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.\r
+    (+) MspInitCallback           : UART MspInit.\r
+    (+) MspDeInitCallback         : UART MspDeInit.\r
+    This function takes as parameters the HAL peripheral handle, the Callback ID\r
+    and a pointer to the user callback function.\r
+\r
+    [..]\r
+    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default\r
+    weak (surcharged) function.\r
+    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
+    and the Callback ID.\r
+    This function allows to reset following callbacks:\r
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.\r
+    (+) TxCpltCallback            : Tx Complete Callback.\r
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.\r
+    (+) RxCpltCallback            : Rx Complete Callback.\r
+    (+) ErrorCallback             : Error Callback.\r
+    (+) AbortCpltCallback         : Abort Complete Callback.\r
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.\r
+    (+) WakeupCallback            : Wakeup Callback.\r
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.\r
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.\r
+    (+) MspInitCallback           : UART MspInit.\r
+    (+) MspDeInitCallback         : UART MspDeInit.\r
+\r
+    [..]\r
+    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET\r
+    all callbacks are set to the corresponding weak (surcharged) functions:\r
+    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().\r
+    Exception done for MspInit and MspDeInit functions that are respectively\r
+    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()\r
+    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).\r
+    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()\r
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).\r
+\r
+    [..]\r
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.\r
+    Exception done MspInit/MspDeInit that can be registered/unregistered\r
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)\r
+    MspInit/DeInit callbacks can be used during the Init/DeInit.\r
+    In that case first register the MspInit/MspDeInit user callbacks\r
+    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()\r
+    or @ref HAL_UART_Init() function.\r
+\r
+    [..]\r
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or\r
+    not defined, the callback registration feature is not available\r
+    and weak (surcharged) callbacks are used.\r
+\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup UART UART\r
+  * @brief HAL UART module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup UART_Private_Constants UART Private Constants\r
+  * @{\r
+  */\r
+#if defined(USART_CR1_FIFOEN)\r
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \\r
+                                      USART_CR1_FIFOEN ))                      /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */\r
+#else\r
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \\r
+                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */\r
+#else\r
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */\r
+#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */\r
+\r
+#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */\r
+#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions\r
+  * @{\r
+  */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);\r
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);\r
+#if defined(USART_CR1_FIFOEN)\r
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+#endif /* USART_CR1_FIFOEN */\r
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);\r
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);\r
+#if defined(USART_CR1_FIFOEN)\r
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+#endif /* USART_CR1_FIFOEN */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup UART_Exported_Functions UART Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  *  @brief    Initialization and Configuration functions\r
+  *\r
+@verbatim\r
+===============================================================================\r
+            ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
+    in asynchronous mode.\r
+      (+) For the asynchronous mode the parameters below can be configured:\r
+        (++) Baud Rate\r
+        (++) Word Length\r
+        (++) Stop Bit\r
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+             in the data register is transmitted but is changed by the parity bit.\r
+        (++) Hardware flow control\r
+        (++) Receiver/transmitter modes\r
+        (++) Over Sampling Method\r
+        (++) One-Bit Sampling Method\r
+      (+) For the asynchronous mode, the following advanced features can be configured as well:\r
+        (++) TX and/or RX pin level inversion\r
+        (++) data logical level inversion\r
+        (++) RX and TX pins swap\r
+        (++) RX overrun detection disabling\r
+        (++) DMA disabling on RX error\r
+        (++) MSB first on communication line\r
+        (++) auto Baud rate detection\r
+    [..]\r
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API\r
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode\r
+    and UART multiprocessor mode configuration procedures (details for the procedures\r
+    are available in reference manual).\r
+\r
+@endverbatim\r
+\r
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
+  8-bit or 9-bit), the possible UART formats are listed in the\r
+  following table.\r
+\r
+  Table 1. UART frame format.\r
+    +-----------------------------------------------------------------------+\r
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |\r
+    +-----------------------------------------------------------------------+\r
+\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Initialize the UART mode according to the specified\r
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r
+{\r
+  /* Check the UART handle allocation */\r
+  if (huart == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r
+  {\r
+    /* Check the parameters */\r
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r
+  }\r
+  else\r
+  {\r
+    /* Check the parameters */\r
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));\r
+  }\r
+\r
+  if (huart->gState == HAL_UART_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    UART_InitCallbacksToDefault(huart);\r
+\r
+    if (huart->MspInitCallback == NULL)\r
+    {\r
+      huart->MspInitCallback = HAL_UART_MspInit;\r
+    }\r
+\r
+    /* Init the low level hardware */\r
+    huart->MspInitCallback(huart);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK */\r
+    HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+  }\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Set the UART Communication parameters */\r
+  if (UART_SetConfig(huart) == HAL_ERROR)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+  {\r
+    UART_AdvFeatureConfig(huart);\r
+  }\r
+\r
+  /* In asynchronous mode, the following bits must be kept cleared:\r
+  - LINEN and CLKEN bits in the USART_CR2 register,\r
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/\r
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+  __HAL_UART_ENABLE(huart);\r
+\r
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+  * @brief Initialize the half-duplex mode according to the specified\r
+  *        parameters in the UART_InitTypeDef and creates the associated handle.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r
+{\r
+  /* Check the UART handle allocation */\r
+  if (huart == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check UART instance */\r
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));\r
+\r
+  if (huart->gState == HAL_UART_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    UART_InitCallbacksToDefault(huart);\r
+\r
+    if (huart->MspInitCallback == NULL)\r
+    {\r
+      huart->MspInitCallback = HAL_UART_MspInit;\r
+    }\r
+\r
+    /* Init the low level hardware */\r
+    huart->MspInitCallback(huart);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK */\r
+    HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+  }\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Set the UART Communication parameters */\r
+  if (UART_SetConfig(huart) == HAL_ERROR)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+  {\r
+    UART_AdvFeatureConfig(huart);\r
+  }\r
+\r
+  /* In half-duplex mode, the following bits must be kept cleared:\r
+  - LINEN and CLKEN bits in the USART_CR2 register,\r
+  - SCEN and IREN bits in the USART_CR3 register.*/\r
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\r
+\r
+  __HAL_UART_ENABLE(huart);\r
+\r
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+  * @brief Initialize the LIN mode according to the specified\r
+  *        parameters in the UART_InitTypeDef and creates the associated handle.\r
+  * @param huart             UART handle.\r
+  * @param BreakDetectLength Specifies the LIN break detection length.\r
+  *        This parameter can be one of the following values:\r
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection\r
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r
+{\r
+  /* Check the UART handle allocation */\r
+  if (huart == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the LIN UART instance */\r
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\r
+  /* Check the Break detection length parameter */\r
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r
+\r
+  /* LIN mode limited to 16-bit oversampling only */\r
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+  /* LIN mode limited to 8-bit data length */\r
+  if (huart->Init.WordLength != UART_WORDLENGTH_8B)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if (huart->gState == HAL_UART_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    UART_InitCallbacksToDefault(huart);\r
+\r
+    if (huart->MspInitCallback == NULL)\r
+    {\r
+      huart->MspInitCallback = HAL_UART_MspInit;\r
+    }\r
+\r
+    /* Init the low level hardware */\r
+    huart->MspInitCallback(huart);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK */\r
+    HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+  }\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Set the UART Communication parameters */\r
+  if (UART_SetConfig(huart) == HAL_ERROR)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+  {\r
+    UART_AdvFeatureConfig(huart);\r
+  }\r
+\r
+  /* In LIN mode, the following bits must be kept cleared:\r
+  - LINEN and CLKEN bits in the USART_CR2 register,\r
+  - SCEN and IREN bits in the USART_CR3 register.*/\r
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\r
+\r
+  /* Set the USART LIN Break detection length. */\r
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);\r
+\r
+  __HAL_UART_ENABLE(huart);\r
+\r
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+  * @brief Initialize the multiprocessor mode according to the specified\r
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.\r
+  * @param huart        UART handle.\r
+  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).\r
+  * @param WakeUpMethod Specifies the UART wakeup method.\r
+  *        This parameter can be one of the following values:\r
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection\r
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark\r
+  * @note  If the user resorts to idle line detection wake up, the Address parameter\r
+  *        is useless and ignored by the initialization function.\r
+  * @note  If the user resorts to address mark wake up, the address length detection\r
+  *        is configured by default to 4 bits only. For the UART to be able to\r
+  *        manage 6-, 7- or 8-bit long addresses detection, the API\r
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after\r
+  *        HAL_MultiProcessor_Init().\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r
+{\r
+  /* Check the UART handle allocation */\r
+  if (huart == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the wake up method parameter */\r
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r
+\r
+  if (huart->gState == HAL_UART_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    UART_InitCallbacksToDefault(huart);\r
+\r
+    if (huart->MspInitCallback == NULL)\r
+    {\r
+      huart->MspInitCallback = HAL_UART_MspInit;\r
+    }\r
+\r
+    /* Init the low level hardware */\r
+    huart->MspInitCallback(huart);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK */\r
+    HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+  }\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Set the UART Communication parameters */\r
+  if (UART_SetConfig(huart) == HAL_ERROR)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+  {\r
+    UART_AdvFeatureConfig(huart);\r
+  }\r
+\r
+  /* In multiprocessor mode, the following bits must be kept cleared:\r
+  - LINEN and CLKEN bits in the USART_CR2 register,\r
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */\r
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)\r
+  {\r
+    /* If address mark wake up method is chosen, set the USART address node */\r
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));\r
+  }\r
+\r
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */\r
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);\r
+\r
+  __HAL_UART_ENABLE(huart);\r
+\r
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+  * @brief DeInitialize the UART peripheral.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r
+{\r
+  /* Check the UART handle allocation */\r
+  if (huart == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the parameters */\r
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  huart->Instance->CR1 = 0x0U;\r
+  huart->Instance->CR2 = 0x0U;\r
+  huart->Instance->CR3 = 0x0U;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  if (huart->MspDeInitCallback == NULL)\r
+  {\r
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
+  }\r
+  /* DeInit the low level hardware */\r
+  huart->MspDeInitCallback(huart);\r
+#else\r
+  /* DeInit the low level hardware */\r
+  HAL_UART_MspDeInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+\r
+  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+  huart->gState = HAL_UART_STATE_RESET;\r
+  huart->RxState = HAL_UART_STATE_RESET;\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Initialize the UART MSP.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_MspInit can be implemented in the user file\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief DeInitialize the UART MSP.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_MspDeInit can be implemented in the user file\r
+   */\r
+}\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+/**\r
+  * @brief  Register a User UART Callback\r
+  *         To be used instead of the weak predefined callback\r
+  * @param  huart uart handle\r
+  * @param  CallbackID ID of the callback to be registered\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID\r
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+  * @param  pCallback pointer to the Callback function\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,\r
+                                            pUART_CallbackTypeDef pCallback)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  if (pCallback == NULL)\r
+  {\r
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  __HAL_LOCK(huart);\r
+\r
+  if (huart->gState == HAL_UART_STATE_READY)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
+        huart->TxHalfCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_TX_COMPLETE_CB_ID :\r
+        huart->TxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
+        huart->RxHalfCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_RX_COMPLETE_CB_ID :\r
+        huart->RxCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_ERROR_CB_ID :\r
+        huart->ErrorCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_ABORT_COMPLETE_CB_ID :\r
+        huart->AbortCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
+        huart->AbortTransmitCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
+        huart->AbortReceiveCpltCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_WAKEUP_CB_ID :\r
+        huart->WakeupCallback = pCallback;\r
+        break;\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+      case HAL_UART_RX_FIFO_FULL_CB_ID :\r
+        huart->RxFifoFullCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :\r
+        huart->TxFifoEmptyCallback = pCallback;\r
+        break;\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+      case HAL_UART_MSPINIT_CB_ID :\r
+        huart->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_MSPDEINIT_CB_ID :\r
+        huart->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (huart->gState == HAL_UART_STATE_RESET)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_UART_MSPINIT_CB_ID :\r
+        huart->MspInitCallback = pCallback;\r
+        break;\r
+\r
+      case HAL_UART_MSPDEINIT_CB_ID :\r
+        huart->MspDeInitCallback = pCallback;\r
+        break;\r
+\r
+      default :\r
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief  Unregister an UART Callback\r
+  *         UART callaback is redirected to the weak predefined callback\r
+  * @param  huart uart handle\r
+  * @param  CallbackID ID of the callback to be unregistered\r
+  *         This parameter can be one of the following values:\r
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID\r
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+\r
+  __HAL_LOCK(huart);\r
+\r
+  if (HAL_UART_STATE_READY == huart->gState)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */\r
+        break;\r
+\r
+      case HAL_UART_TX_COMPLETE_CB_ID :\r
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */\r
+        break;\r
+\r
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */\r
+        break;\r
+\r
+      case HAL_UART_RX_COMPLETE_CB_ID :\r
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */\r
+        break;\r
+\r
+      case HAL_UART_ERROR_CB_ID :\r
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */\r
+        break;\r
+\r
+      case HAL_UART_ABORT_COMPLETE_CB_ID :\r
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */\r
+        break;\r
+\r
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
+        break;\r
+\r
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */\r
+        break;\r
+\r
+      case HAL_UART_WAKEUP_CB_ID :\r
+        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback            */\r
+        break;\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+      case HAL_UART_RX_FIFO_FULL_CB_ID :\r
+        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */\r
+        break;\r
+\r
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :\r
+        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */\r
+        break;\r
+\r
+#endif /* USART_CR1_FIFOEN */\r
+      case HAL_UART_MSPINIT_CB_ID :\r
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */\r
+        break;\r
+\r
+      case HAL_UART_MSPDEINIT_CB_ID :\r
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */\r
+        break;\r
+\r
+      default :\r
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else if (HAL_UART_STATE_RESET == huart->gState)\r
+  {\r
+    switch (CallbackID)\r
+    {\r
+      case HAL_UART_MSPINIT_CB_ID :\r
+        huart->MspInitCallback = HAL_UART_MspInit;\r
+        break;\r
+\r
+      case HAL_UART_MSPDEINIT_CB_ID :\r
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
+        break;\r
+\r
+      default :\r
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+        status =  HAL_ERROR;\r
+        break;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+    status =  HAL_ERROR;\r
+  }\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return status;\r
+}\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions\r
+  * @brief UART Transmit/Receive functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### IO operation functions #####\r
+ ===============================================================================\r
+    This subsection provides a set of functions allowing to manage the UART asynchronous\r
+    and Half duplex data transfers.\r
+\r
+    (#) There are two mode of transfer:\r
+       (+) Blocking mode: The communication is performed in polling mode.\r
+           The HAL status of all data processing is returned by the same function\r
+           after finishing transfer.\r
+       (+) Non-Blocking mode: The communication is performed using Interrupts\r
+           or DMA, These API's return the HAL status.\r
+           The end of the data processing will be indicated through the\r
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\r
+           using DMA mode.\r
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\r
+           will be executed respectively at the end of the transmit or Receive process\r
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+    (#) Blocking mode API's are :\r
+        (+) HAL_UART_Transmit()\r
+        (+) HAL_UART_Receive()\r
+\r
+    (#) Non-Blocking mode API's with Interrupt are :\r
+        (+) HAL_UART_Transmit_IT()\r
+        (+) HAL_UART_Receive_IT()\r
+        (+) HAL_UART_IRQHandler()\r
+\r
+    (#) Non-Blocking mode API's with DMA are :\r
+        (+) HAL_UART_Transmit_DMA()\r
+        (+) HAL_UART_Receive_DMA()\r
+        (+) HAL_UART_DMAPause()\r
+        (+) HAL_UART_DMAResume()\r
+        (+) HAL_UART_DMAStop()\r
+\r
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r
+        (+) HAL_UART_TxHalfCpltCallback()\r
+        (+) HAL_UART_TxCpltCallback()\r
+        (+) HAL_UART_RxHalfCpltCallback()\r
+        (+) HAL_UART_RxCpltCallback()\r
+        (+) HAL_UART_ErrorCallback()\r
+\r
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :\r
+        (+) HAL_UART_Abort()\r
+        (+) HAL_UART_AbortTransmit()\r
+        (+) HAL_UART_AbortReceive()\r
+        (+) HAL_UART_Abort_IT()\r
+        (+) HAL_UART_AbortTransmit_IT()\r
+        (+) HAL_UART_AbortReceive_IT()\r
+\r
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:\r
+        (+) HAL_UART_AbortCpltCallback()\r
+        (+) HAL_UART_AbortTransmitCpltCallback()\r
+        (+) HAL_UART_AbortReceiveCpltCallback()\r
+\r
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.\r
+        Errors are handled as follows :\r
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is\r
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .\r
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,\r
+           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.\r
+           If user wants to abort it, Abort services should be called by user.\r
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.\r
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.\r
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.\r
+\r
+    -@- In the Half duplex communication, it is forbidden to run the transmit\r
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Send an amount of data in blocking mode.\r
+  * @note When FIFO mode is enabled, writing a data in the TDR register adds one\r
+  *       data to the TXFIFO. Write operations to the TDR register are performed\r
+  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and\r
+  *       TXE are mapped on the same bit-field.\r
+  * @param huart   UART handle.\r
+  * @param pData   Pointer to data buffer.\r
+  * @param Size    Amount of data to be sent.\r
+  * @param Timeout Timeout duration.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint8_t  *pdata8bits;\r
+  uint16_t *pdata16bits;\r
+  uint32_t tickstart;\r
+\r
+  /* Check that a Tx process is not already ongoing */\r
+  if (huart->gState == HAL_UART_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    __HAL_LOCK(huart);\r
+\r
+    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+    huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+    /* Init tickstart for timeout managment*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    huart->TxXferSize  = Size;\r
+    huart->TxXferCount = Size;\r
+\r
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */\r
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+    {\r
+      pdata8bits  = NULL;\r
+      pdata16bits = (uint16_t *) pData;\r
+    }\r
+    else\r
+    {\r
+      pdata8bits  = pData;\r
+      pdata16bits = NULL;\r
+    }\r
+\r
+    while (huart->TxXferCount > 0U)\r
+    {\r
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+      {\r
+        return HAL_TIMEOUT;\r
+      }\r
+      if (pdata8bits == NULL)\r
+      {\r
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);\r
+        pdata16bits++;\r
+      }\r
+      else\r
+      {\r
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);\r
+        pdata8bits++;\r
+      }\r
+      huart->TxXferCount--;\r
+    }\r
+\r
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+\r
+    /* At end of Tx process, restore huart->gState to Ready */\r
+    huart->gState = HAL_UART_STATE_READY;\r
+\r
+    __HAL_UNLOCK(huart);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Receive an amount of data in blocking mode.\r
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO\r
+  *       is not empty. Read operations from the RDR register are performed when\r
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and\r
+  *       RXNE are mapped on the same bit-field.\r
+  * @param huart   UART handle.\r
+  * @param pData   Pointer to data buffer.\r
+  * @param Size    Amount of data to be received.\r
+  * @param Timeout Timeout duration.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+  uint8_t  *pdata8bits;\r
+  uint16_t *pdata16bits;\r
+  uint16_t uhMask;\r
+  uint32_t tickstart;\r
+\r
+  /* Check that a Rx process is not already ongoing */\r
+  if (huart->RxState == HAL_UART_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      return  HAL_ERROR;\r
+    }\r
+\r
+    __HAL_LOCK(huart);\r
+\r
+    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+    huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+    /* Init tickstart for timeout managment*/\r
+    tickstart = HAL_GetTick();\r
+\r
+    huart->RxXferSize  = Size;\r
+    huart->RxXferCount = Size;\r
+\r
+    /* Computation of UART mask to apply to RDR register */\r
+    UART_MASK_COMPUTATION(huart);\r
+    uhMask = huart->Mask;\r
+\r
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */\r
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+    {\r
+      pdata8bits  = NULL;\r
+      pdata16bits = (uint16_t *) pData;\r
+    }\r
+    else\r
+    {\r
+      pdata8bits  = pData;\r
+      pdata16bits = NULL;\r
+    }\r
+\r
+    /* as long as data have to be received */\r
+    while (huart->RxXferCount > 0U)\r
+    {\r
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+      {\r
+        return HAL_TIMEOUT;\r
+      }\r
+      if (pdata8bits == NULL)\r
+      {\r
+        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);\r
+        pdata16bits++;\r
+      }\r
+      else\r
+      {\r
+        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r
+        pdata8bits++;\r
+      }\r
+      huart->RxXferCount--;\r
+    }\r
+\r
+    /* At end of Rx process, restore huart->RxState to Ready */\r
+    huart->RxState = HAL_UART_STATE_READY;\r
+\r
+    __HAL_UNLOCK(huart);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Send an amount of data in interrupt mode.\r
+  * @param huart UART handle.\r
+  * @param pData Pointer to data buffer.\r
+  * @param Size  Amount of data to be sent.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+  /* Check that a Tx process is not already ongoing */\r
+  if (huart->gState == HAL_UART_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    __HAL_LOCK(huart);\r
+\r
+    huart->pTxBuffPtr  = pData;\r
+    huart->TxXferSize  = Size;\r
+    huart->TxXferCount = Size;\r
+    huart->TxISR       = NULL;\r
+\r
+    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+    huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+    /* Configure Tx interrupt processing */\r
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+    {\r
+      /* Set the Tx ISR function pointer according to the data word length */\r
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+      {\r
+        huart->TxISR = UART_TxISR_16BIT_FIFOEN;\r
+      }\r
+      else\r
+      {\r
+        huart->TxISR = UART_TxISR_8BIT_FIFOEN;\r
+      }\r
+\r
+      __HAL_UNLOCK(huart);\r
+\r
+      /* Enable the TX FIFO threshold interrupt */\r
+      SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+    }\r
+    else\r
+    {\r
+      /* Set the Tx ISR function pointer according to the data word length */\r
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+      {\r
+        huart->TxISR = UART_TxISR_16BIT;\r
+      }\r
+      else\r
+      {\r
+        huart->TxISR = UART_TxISR_8BIT;\r
+      }\r
+\r
+      __HAL_UNLOCK(huart);\r
+\r
+      /* Enable the Transmit Data Register Empty interrupt */\r
+      SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
+    }\r
+#else\r
+    /* Set the Tx ISR function pointer according to the data word length */\r
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+    {\r
+      huart->TxISR = UART_TxISR_16BIT;\r
+    }\r
+    else\r
+    {\r
+      huart->TxISR = UART_TxISR_8BIT;\r
+    }\r
+\r
+    __HAL_UNLOCK(huart);\r
+\r
+    /* Enable the Transmit Data Register Empty interrupt */\r
+    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Receive an amount of data in interrupt mode.\r
+  * @param huart UART handle.\r
+  * @param pData Pointer to data buffer.\r
+  * @param Size  Amount of data to be received.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+  /* Check that a Rx process is not already ongoing */\r
+  if (huart->RxState == HAL_UART_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    __HAL_LOCK(huart);\r
+\r
+    huart->pRxBuffPtr  = pData;\r
+    huart->RxXferSize  = Size;\r
+    huart->RxXferCount = Size;\r
+    huart->RxISR       = NULL;\r
+\r
+    /* Computation of UART mask to apply to RDR register */\r
+    UART_MASK_COMPUTATION(huart);\r
+\r
+    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+    huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+    /* Configure Rx interrupt processing*/\r
+    if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))\r
+    {\r
+      /* Set the Rx ISR function pointer according to the data word length */\r
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+      {\r
+        huart->RxISR = UART_RxISR_16BIT_FIFOEN;\r
+      }\r
+      else\r
+      {\r
+        huart->RxISR = UART_RxISR_8BIT_FIFOEN;\r
+      }\r
+\r
+      __HAL_UNLOCK(huart);\r
+\r
+      /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */\r
+      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+      SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
+    }\r
+    else\r
+    {\r
+      /* Set the Rx ISR function pointer according to the data word length */\r
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+      {\r
+        huart->RxISR = UART_RxISR_16BIT;\r
+      }\r
+      else\r
+      {\r
+        huart->RxISR = UART_RxISR_8BIT;\r
+      }\r
+\r
+      __HAL_UNLOCK(huart);\r
+\r
+      /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */\r
+      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);\r
+    }\r
+#else\r
+    /* Set the Rx ISR function pointer according to the data word length */\r
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+    {\r
+      huart->RxISR = UART_RxISR_16BIT;\r
+    }\r
+    else\r
+    {\r
+      huart->RxISR = UART_RxISR_8BIT;\r
+    }\r
+\r
+    __HAL_UNLOCK(huart);\r
+\r
+    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */\r
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Send an amount of data in DMA mode.\r
+  * @param huart UART handle.\r
+  * @param pData Pointer to data buffer.\r
+  * @param Size  Amount of data to be sent.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+  /* Check that a Tx process is not already ongoing */\r
+  if (huart->gState == HAL_UART_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    __HAL_LOCK(huart);\r
+\r
+    huart->pTxBuffPtr  = pData;\r
+    huart->TxXferSize  = Size;\r
+    huart->TxXferCount = Size;\r
+\r
+    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+    huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+    if (huart->hdmatx != NULL)\r
+    {\r
+      /* Set the UART DMA transfer complete callback */\r
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r
+\r
+      /* Set the UART DMA Half transfer complete callback */\r
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      huart->hdmatx->XferErrorCallback = UART_DMAError;\r
+\r
+      /* Set the DMA abort callback */\r
+      huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the UART transmit DMA channel */\r
+      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)\r
+      {\r
+        /* Set error code to DMA */\r
+        huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+        __HAL_UNLOCK(huart);\r
+\r
+        /* Restore huart->gState to ready */\r
+        huart->gState = HAL_UART_STATE_READY;\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+    /* Clear the TC flag in the ICR register */\r
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);\r
+\r
+    __HAL_UNLOCK(huart);\r
+\r
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+    in the UART CR3 register */\r
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Receive an amount of data in DMA mode.\r
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain\r
+  *         the parity bit (MSB position).\r
+  * @param huart UART handle.\r
+  * @param pData Pointer to data buffer.\r
+  * @param Size  Amount of data to be received.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+  /* Check that a Rx process is not already ongoing */\r
+  if (huart->RxState == HAL_UART_STATE_READY)\r
+  {\r
+    if ((pData == NULL) || (Size == 0U))\r
+    {\r
+      return HAL_ERROR;\r
+    }\r
+\r
+    __HAL_LOCK(huart);\r
+\r
+    huart->pRxBuffPtr = pData;\r
+    huart->RxXferSize = Size;\r
+\r
+    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+    huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+    if (huart->hdmarx != NULL)\r
+    {\r
+      /* Set the UART DMA transfer complete callback */\r
+      huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r
+\r
+      /* Set the UART DMA Half transfer complete callback */\r
+      huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r
+\r
+      /* Set the DMA error callback */\r
+      huart->hdmarx->XferErrorCallback = UART_DMAError;\r
+\r
+      /* Set the DMA abort callback */\r
+      huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+      /* Enable the DMA channel */\r
+      if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)\r
+      {\r
+        /* Set error code to DMA */\r
+        huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+        __HAL_UNLOCK(huart);\r
+\r
+        /* Restore huart->gState to ready */\r
+        huart->gState = HAL_UART_STATE_READY;\r
+\r
+        return HAL_ERROR;\r
+      }\r
+    }\r
+    __HAL_UNLOCK(huart);\r
+\r
+    /* Enable the UART Parity Error Interrupt */\r
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+    in the UART CR3 register */\r
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+    return HAL_OK;\r
+  }\r
+  else\r
+  {\r
+    return HAL_BUSY;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Pause the DMA Transfer.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r
+{\r
+  const HAL_UART_StateTypeDef gstate = huart->gState;\r
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
+\r
+  __HAL_LOCK(huart);\r
+\r
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
+      (gstate == HAL_UART_STATE_BUSY_TX))\r
+  {\r
+    /* Disable the UART DMA Tx request */\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+  }\r
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
+      (rxstate == HAL_UART_STATE_BUSY_RX))\r
+  {\r
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+    /* Disable the UART DMA Rx request */\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+  }\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Resume the DMA Transfer.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r
+{\r
+  __HAL_LOCK(huart);\r
+\r
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+  {\r
+    /* Enable the UART DMA Tx request */\r
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+  }\r
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+  {\r
+    /* Clear the Overrun flag before resuming the Rx transfer */\r
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);\r
+\r
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+    /* Enable the UART DMA Rx request */\r
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+  }\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Stop the DMA Transfer.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r
+{\r
+  /* The Lock is not implemented on this API to allow the user application\r
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /\r
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:\r
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r
+     the stream and the corresponding call back is executed. */\r
+\r
+  const HAL_UART_StateTypeDef gstate = huart->gState;\r
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
+\r
+  /* Stop UART DMA Tx request if ongoing */\r
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
+      (gstate == HAL_UART_STATE_BUSY_TX))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+    /* Abort the UART DMA Tx channel */\r
+    if (huart->hdmatx != NULL)\r
+    {\r
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+      {\r
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+        {\r
+          /* Set error code to DMA */\r
+          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+\r
+    UART_EndTxTransfer(huart);\r
+  }\r
+\r
+  /* Stop UART DMA Rx request if ongoing */\r
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
+      (rxstate == HAL_UART_STATE_BUSY_RX))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+    /* Abort the UART DMA Rx channel */\r
+    if (huart->hdmarx != NULL)\r
+    {\r
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+      {\r
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+        {\r
+          /* Set error code to DMA */\r
+          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+\r
+    UART_EndRxTransfer(huart);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing transfers (blocking mode).\r
+  * @param  huart UART handle.\r
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable UART Interrupts (Tx and Rx)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)\r
+{\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);\r
+#else\r
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Disable the UART DMA Tx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
+    if (huart->hdmatx != NULL)\r
+    {\r
+      /* Set the UART DMA Abort callback to Null.\r
+         No call back execution at end of DMA abort procedure */\r
+      huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+      {\r
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+        {\r
+          /* Set error code to DMA */\r
+          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Disable the UART DMA Rx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
+    if (huart->hdmarx != NULL)\r
+    {\r
+      /* Set the UART DMA Abort callback to Null.\r
+         No call back execution at end of DMA abort procedure */\r
+      huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+      {\r
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+        {\r
+          /* Set error code to DMA */\r
+          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Reset Tx and Rx transfer counters */\r
+  huart->TxXferCount = 0U;\r
+  huart->RxXferCount = 0U;\r
+\r
+  /* Clear the Error flags in the ICR register */\r
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Flush the whole TX FIFO (if needed) */\r
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+  {\r
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+  }\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Discard the received data */\r
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+  /* Restore huart->gState and huart->RxState to Ready */\r
+  huart->gState  = HAL_UART_STATE_READY;\r
+  huart->RxState = HAL_UART_STATE_READY;\r
+\r
+  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing Transmit transfer (blocking mode).\r
+  * @param  huart UART handle.\r
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable UART Interrupts (Tx)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)\r
+{\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+#else\r
+  /* Disable TXEIE and TCIE interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Disable the UART DMA Tx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
+    if (huart->hdmatx != NULL)\r
+    {\r
+      /* Set the UART DMA Abort callback to Null.\r
+         No call back execution at end of DMA abort procedure */\r
+      huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+      {\r
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+        {\r
+          /* Set error code to DMA */\r
+          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Reset Tx transfer counter */\r
+  huart->TxXferCount = 0U;\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Flush the whole TX FIFO (if needed) */\r
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+  {\r
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+  }\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Restore huart->gState to Ready */\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing Receive transfer (blocking mode).\r
+  * @param  huart UART handle.\r
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable UART Interrupts (Rx)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)\r
+{\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);\r
+#else\r
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Disable the UART DMA Rx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
+    if (huart->hdmarx != NULL)\r
+    {\r
+      /* Set the UART DMA Abort callback to Null.\r
+         No call back execution at end of DMA abort procedure */\r
+      huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+      {\r
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+        {\r
+          /* Set error code to DMA */\r
+          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+          return HAL_TIMEOUT;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Reset Rx transfer counter */\r
+  huart->RxXferCount = 0U;\r
+\r
+  /* Clear the Error flags in the ICR register */\r
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+  /* Discard the received data */\r
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+  /* Restore huart->RxState to Ready */\r
+  huart->RxState = HAL_UART_STATE_READY;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing transfers (Interrupt mode).\r
+  * @param  huart UART handle.\r
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable UART Interrupts (Tx and Rx)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  *           - At abort completion, call user abort complete callback\r
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)\r
+{\r
+  uint32_t abortcplt = 1U;\r
+\r
+  /* Disable interrupts */\r
+#if defined(USART_CR1_FIFOEN)\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));\r
+#else\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised\r
+     before any call to DMA Abort functions */\r
+  /* DMA Tx Handle is valid */\r
+  if (huart->hdmatx != NULL)\r
+  {\r
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r
+       Otherwise, set it to NULL */\r
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+    {\r
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;\r
+    }\r
+    else\r
+    {\r
+      huart->hdmatx->XferAbortCallback = NULL;\r
+    }\r
+  }\r
+  /* DMA Rx Handle is valid */\r
+  if (huart->hdmarx != NULL)\r
+  {\r
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r
+       Otherwise, set it to NULL */\r
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+    {\r
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;\r
+    }\r
+    else\r
+    {\r
+      huart->hdmarx->XferAbortCallback = NULL;\r
+    }\r
+  }\r
+\r
+  /* Disable the UART DMA Tx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+  {\r
+    /* Disable DMA Tx at UART level */\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
+    if (huart->hdmatx != NULL)\r
+    {\r
+      /* UART Tx DMA Abort callback has already been initialised :\r
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+      /* Abort DMA TX */\r
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
+      {\r
+        huart->hdmatx->XferAbortCallback = NULL;\r
+      }\r
+      else\r
+      {\r
+        abortcplt = 0U;\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Disable the UART DMA Rx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
+    if (huart->hdmarx != NULL)\r
+    {\r
+      /* UART Rx DMA Abort callback has already been initialised :\r
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+      /* Abort DMA RX */\r
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+      {\r
+        huart->hdmarx->XferAbortCallback = NULL;\r
+        abortcplt = 1U;\r
+      }\r
+      else\r
+      {\r
+        abortcplt = 0U;\r
+      }\r
+    }\r
+  }\r
+\r
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */\r
+  if (abortcplt == 1U)\r
+  {\r
+    /* Reset Tx and Rx transfer counters */\r
+    huart->TxXferCount = 0U;\r
+    huart->RxXferCount = 0U;\r
+\r
+    /* Clear ISR function pointers */\r
+    huart->RxISR = NULL;\r
+    huart->TxISR = NULL;\r
+\r
+    /* Reset errorCode */\r
+    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+    /* Clear the Error flags in the ICR register */\r
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+    /* Flush the whole TX FIFO (if needed) */\r
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+    {\r
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+    }\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+    /* Discard the received data */\r
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+    /* Restore huart->gState and huart->RxState to Ready */\r
+    huart->gState  = HAL_UART_STATE_READY;\r
+    huart->RxState = HAL_UART_STATE_READY;\r
+\r
+    /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    /* Call registered Abort complete callback */\r
+    huart->AbortCpltCallback(huart);\r
+#else\r
+    /* Call legacy weak Abort complete callback */\r
+    HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).\r
+  * @param  huart UART handle.\r
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable UART Interrupts (Tx)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  *           - At abort completion, call user abort complete callback\r
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+  /* Disable interrupts */\r
+#if defined(USART_CR1_FIFOEN)\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+#else\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Disable the UART DMA Tx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
+    if (huart->hdmatx != NULL)\r
+    {\r
+      /* Set the UART DMA Abort callback :\r
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;\r
+\r
+      /* Abort DMA TX */\r
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
+      {\r
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */\r
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Reset Tx transfer counter */\r
+      huart->TxXferCount = 0U;\r
+\r
+      /* Clear TxISR function pointers */\r
+      huart->TxISR = NULL;\r
+\r
+      /* Restore huart->gState to Ready */\r
+      huart->gState = HAL_UART_STATE_READY;\r
+\r
+      /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+      /* Call registered Abort Transmit Complete Callback */\r
+      huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+      /* Call legacy weak Abort Transmit Complete Callback */\r
+      HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Reset Tx transfer counter */\r
+    huart->TxXferCount = 0U;\r
+\r
+    /* Clear TxISR function pointers */\r
+    huart->TxISR = NULL;\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+    /* Flush the whole TX FIFO (if needed) */\r
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+    {\r
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+    }\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+    /* Restore huart->gState to Ready */\r
+    huart->gState = HAL_UART_STATE_READY;\r
+\r
+    /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    /* Call registered Abort Transmit Complete Callback */\r
+    huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+    /* Call legacy weak Abort Transmit Complete Callback */\r
+    HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).\r
+  * @param  huart UART handle.\r
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
+  *         This procedure performs following operations :\r
+  *           - Disable UART Interrupts (Rx)\r
+  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+  *           - Set handle State to READY\r
+  *           - At abort completion, call user abort complete callback\r
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)\r
+{\r
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+#if defined(USART_CR1_FIFOEN)\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+#else\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Disable the UART DMA Rx request if enabled */\r
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+  {\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
+    if (huart->hdmarx != NULL)\r
+    {\r
+      /* Set the UART DMA Abort callback :\r
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;\r
+\r
+      /* Abort DMA RX */\r
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+      {\r
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /* Reset Rx transfer counter */\r
+      huart->RxXferCount = 0U;\r
+\r
+      /* Clear RxISR function pointer */\r
+      huart->pRxBuffPtr = NULL;\r
+\r
+      /* Clear the Error flags in the ICR register */\r
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+      /* Discard the received data */\r
+      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+      /* Restore huart->RxState to Ready */\r
+      huart->RxState = HAL_UART_STATE_READY;\r
+\r
+      /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+      /* Call registered Abort Receive Complete Callback */\r
+      huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+      /* Call legacy weak Abort Receive Complete Callback */\r
+      HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Reset Rx transfer counter */\r
+    huart->RxXferCount = 0U;\r
+\r
+    /* Clear RxISR function pointer */\r
+    huart->pRxBuffPtr = NULL;\r
+\r
+    /* Clear the Error flags in the ICR register */\r
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+    /* Restore huart->RxState to Ready */\r
+    huart->RxState = HAL_UART_STATE_READY;\r
+\r
+    /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    /* Call registered Abort Receive Complete Callback */\r
+    huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+    /* Call legacy weak Abort Receive Complete Callback */\r
+    HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Handle UART interrupt request.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r
+{\r
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);\r
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);\r
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);\r
+\r
+  uint32_t errorflags;\r
+  uint32_t errorcode;\r
+\r
+  /* If no error occurs */\r
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r
+  if (errorflags == 0U)\r
+  {\r
+    /* UART in mode Receiver ---------------------------------------------------*/\r
+#if defined(USART_CR1_FIFOEN)\r
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
+#else\r
+    if (((isrflags & USART_ISR_RXNE) != 0U)\r
+        && ((cr1its & USART_CR1_RXNEIE) != 0U))\r
+#endif /* USART_CR1_FIFOEN */\r
+    {\r
+      if (huart->RxISR != NULL)\r
+      {\r
+        huart->RxISR(huart);\r
+      }\r
+      return;\r
+    }\r
+  }\r
+\r
+  /* If some errors occur */\r
+#if defined(USART_CR1_FIFOEN)\r
+  if ((errorflags != 0U)\r
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)\r
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))\r
+#else\r
+  if ((errorflags != 0U)\r
+      && (((cr3its & USART_CR3_EIE) != 0U)\r
+          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))\r
+#endif /* USART_CR1_FIFOEN */\r
+  {\r
+    /* UART parity error interrupt occurred -------------------------------------*/\r
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))\r
+    {\r
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);\r
+\r
+      huart->ErrorCode |= HAL_UART_ERROR_PE;\r
+    }\r
+\r
+    /* UART frame error interrupt occurred --------------------------------------*/\r
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
+    {\r
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);\r
+\r
+      huart->ErrorCode |= HAL_UART_ERROR_FE;\r
+    }\r
+\r
+    /* UART noise error interrupt occurred --------------------------------------*/\r
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
+    {\r
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);\r
+\r
+      huart->ErrorCode |= HAL_UART_ERROR_NE;\r
+    }\r
+\r
+    /* UART Over-Run interrupt occurred -----------------------------------------*/\r
+#if defined(USART_CR1_FIFOEN)\r
+    if (((isrflags & USART_ISR_ORE) != 0U)\r
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||\r
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))\r
+#else\r
+    if (((isrflags & USART_ISR_ORE) != 0U)\r
+        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||\r
+            ((cr3its & USART_CR3_EIE) != 0U)))\r
+#endif /* USART_CR1_FIFOEN */\r
+    {\r
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);\r
+\r
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;\r
+    }\r
+\r
+    /* Call UART Error Call back function if need be --------------------------*/\r
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)\r
+    {\r
+      /* UART in mode Receiver ---------------------------------------------------*/\r
+#if defined(USART_CR1_FIFOEN)\r
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
+#else\r
+      if (((isrflags & USART_ISR_RXNE) != 0U)\r
+          && ((cr1its & USART_CR1_RXNEIE) != 0U))\r
+#endif /* USART_CR1_FIFOEN */\r
+      {\r
+        if (huart->RxISR != NULL)\r
+        {\r
+          huart->RxISR(huart);\r
+        }\r
+      }\r
+\r
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+         consider error as blocking */\r
+      errorcode = huart->ErrorCode;\r
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||\r
+          ((errorcode & HAL_UART_ERROR_ORE) != 0U))\r
+      {\r
+        /* Blocking error : transfer is aborted\r
+           Set the UART state ready to be able to start again the process,\r
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
+        UART_EndRxTransfer(huart);\r
+\r
+        /* Disable the UART DMA Rx request if enabled */\r
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+        {\r
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+          /* Abort the UART DMA Rx channel */\r
+          if (huart->hdmarx != NULL)\r
+          {\r
+            /* Set the UART DMA Abort callback :\r
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\r
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\r
+\r
+            /* Abort DMA RX */\r
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+            {\r
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
+            }\r
+          }\r
+          else\r
+          {\r
+            /* Call user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+            /*Call registered error callback*/\r
+            huart->ErrorCallback(huart);\r
+#else\r
+            /*Call legacy weak error callback*/\r
+            HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+          }\r
+        }\r
+        else\r
+        {\r
+          /* Call user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+          /*Call registered error callback*/\r
+          huart->ErrorCallback(huart);\r
+#else\r
+          /*Call legacy weak error callback*/\r
+          HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+        }\r
+      }\r
+      else\r
+      {\r
+        /* Non Blocking error : transfer could go on.\r
+           Error is notified to user through user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+        /*Call registered error callback*/\r
+        huart->ErrorCallback(huart);\r
+#else\r
+        /*Call legacy weak error callback*/\r
+        HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+        huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+      }\r
+    }\r
+    return;\r
+\r
+  } /* End if some error occurs */\r
+\r
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/\r
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))\r
+  {\r
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);\r
+\r
+    /* UART Rx state is not reset as a reception process might be ongoing.\r
+       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    /* Call registered Wakeup Callback */\r
+    huart->WakeupCallback(huart);\r
+#else\r
+    /* Call legacy weak Wakeup Callback */\r
+    HAL_UARTEx_WakeupCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+    return;\r
+  }\r
+\r
+  /* UART in mode Transmitter ------------------------------------------------*/\r
+#if defined(USART_CR1_FIFOEN)\r
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)\r
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)\r
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))\r
+#else\r
+  if (((isrflags & USART_ISR_TXE) != 0U)\r
+      && ((cr1its & USART_CR1_TXEIE) != 0U))\r
+#endif /* USART_CR1_FIFOEN */\r
+  {\r
+    if (huart->TxISR != NULL)\r
+    {\r
+      huart->TxISR(huart);\r
+    }\r
+    return;\r
+  }\r
+\r
+  /* UART in mode Transmitter (transmission end) -----------------------------*/\r
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))\r
+  {\r
+    UART_EndTransmit_IT(huart);\r
+    return;\r
+  }\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/\r
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))\r
+  {\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    /* Call registered Tx Fifo Empty Callback */\r
+    huart->TxFifoEmptyCallback(huart);\r
+#else\r
+    /* Call legacy weak Tx Fifo Empty Callback */\r
+    HAL_UARTEx_TxFifoEmptyCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+    return;\r
+  }\r
+\r
+  /* UART RX Fifo Full occurred ----------------------------------------------*/\r
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))\r
+  {\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    /* Call registered Rx Fifo Full Callback */\r
+    huart->RxFifoFullCallback(huart);\r
+#else\r
+    /* Call legacy weak Rx Fifo Full Callback */\r
+    HAL_UARTEx_RxFifoFullCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+    return;\r
+  }\r
+#endif /* USART_CR1_FIFOEN */\r
+}\r
+\r
+/**\r
+  * @brief Tx Transfer completed callback.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_TxCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Tx Half Transfer completed callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Rx Transfer completed callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_RxCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Rx Half Transfer completed callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE: This function should not be modified, when the callback is needed,\r
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  UART error callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_ErrorCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  UART Abort Complete callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  UART Abort Complete callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  UART Abort Receive Complete callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+  *  @brief   UART control functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to control the UART.\r
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode\r
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode\r
+     (+) UART_SetConfig() API configures the UART peripheral\r
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features\r
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization\r
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter\r
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver\r
+     (+) HAL_LIN_SendBreak() API transmits the break characters\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;\r
+  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).\r
+  * @param  huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */\r
+  SET_BIT(huart->Instance->CR1, USART_CR1_MME);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode\r
+  *         as it may not have been in mute mode at this very moment).\r
+  * @param  huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Disable USART mute mode by clearing the MME bit in the CR1 register */\r
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+  * @brief Enter UART mute mode (means UART actually enters mute mode).\r
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);\r
+}\r
+\r
+/**\r
+  * @brief  Enable the UART transmitter and disable the UART receiver.\r
+  * @param  huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r
+{\r
+  __HAL_LOCK(huart);\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Clear TE and RE bits */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+\r
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r
+  SET_BIT(huart->Instance->CR1, USART_CR1_TE);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Enable the UART receiver and disable the UART transmitter.\r
+  * @param  huart UART handle.\r
+  * @retval HAL status.\r
+  */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r
+{\r
+  __HAL_LOCK(huart);\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Clear TE and RE bits */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+\r
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r
+  SET_BIT(huart->Instance->CR1, USART_CR1_RE);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Transmit break characters.\r
+  * @param  huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\r
+\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Send break characters */\r
+  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
+  *  @brief   UART Peripheral State functions\r
+  *\r
+@verbatim\r
+  ==============================================================================\r
+            ##### Peripheral State and Error functions #####\r
+  ==============================================================================\r
+    [..]\r
+    This subsection provides functions allowing to :\r
+      (+) Return the UART handle state.\r
+      (+) Return the UART handle error code\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Return the UART handle state.\r
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified UART.\r
+  * @retval HAL state\r
+  */\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r
+{\r
+  uint32_t temp1;\r
+  uint32_t temp2;\r
+  temp1 = huart->gState;\r
+  temp2 = huart->RxState;\r
+\r
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+  * @brief  Return the UART handle error code.\r
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\r
+  *               the configuration information for the specified UART.\r
+  * @retval UART Error Code\r
+  */\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r
+{\r
+  return huart->ErrorCode;\r
+}\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UART_Private_Functions UART Private Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initialize the callbacks to their default values.\r
+  * @param  huart UART handle.\r
+  * @retval none\r
+  */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)\r
+{\r
+  /* Init the UART Callback settings */\r
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */\r
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */\r
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */\r
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */\r
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */\r
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */\r
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */\r
+  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */\r
+#if defined(USART_CR1_FIFOEN)\r
+  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */\r
+  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+}\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+  * @brief Configure the UART peripheral.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)\r
+{\r
+  uint32_t tmpreg;\r
+  uint16_t brrtemp;\r
+  UART_ClockSourceTypeDef clocksource;\r
+  uint32_t usartdiv                   = 0x00000000U;\r
+  HAL_StatusTypeDef ret               = HAL_OK;\r
+  uint32_t lpuart_ker_ck_pres         = 0x00000000U;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\r
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
+  if (UART_INSTANCE_LOWPOWER(huart))\r
+  {\r
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));\r
+  }\r
+  else\r
+  {\r
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));\r
+  }\r
+\r
+  assert_param(IS_UART_PARITY(huart->Init.Parity));\r
+  assert_param(IS_UART_MODE(huart->Init.Mode));\r
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\r
+#if defined(USART_PRESC_PRESCALER)\r
+  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));\r
+#endif /* USART_PRESC_PRESCALER */\r
+\r
+  /*-------------------------- USART CR1 Configuration -----------------------*/\r
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure\r
+  *  the UART Word Length, Parity, Mode and oversampling:\r
+  *  set the M bits according to huart->Init.WordLength value\r
+  *  set PCE and PS bits according to huart->Init.Parity value\r
+  *  set TE and RE bits according to huart->Init.Mode value\r
+  *  set OVER8 bit according to huart->Init.OverSampling value */\r
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;\r
+#if defined(USART_CR1_FIFOEN)\r
+  tmpreg |= (uint32_t)huart->FifoMode;\r
+#endif /* USART_CR1_FIFOEN */\r
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
+\r
+  /*-------------------------- USART CR2 Configuration -----------------------*/\r
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according\r
+  * to huart->Init.StopBits value */\r
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r
+\r
+  /*-------------------------- USART CR3 Configuration -----------------------*/\r
+  /* Configure\r
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according\r
+  *   to huart->Init.HwFlowCtl value\r
+  * - one-bit sampling method versus three samples' majority rule according\r
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */\r
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;\r
+\r
+  if (!(UART_INSTANCE_LOWPOWER(huart)))\r
+  {\r
+    tmpreg |= huart->Init.OneBitSampling;\r
+  }\r
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);\r
+\r
+#if defined(USART_PRESC_PRESCALER)\r
+  /*-------------------------- USART PRESC Configuration -----------------------*/\r
+  /* Configure\r
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */\r
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);\r
+#endif /* USART_PRESC_PRESCALER */\r
+\r
+  /*-------------------------- USART BRR Configuration -----------------------*/\r
+  UART_GETCLOCKSOURCE(huart, clocksource);\r
+\r
+  /* Check LPUART instance */\r
+  if (UART_INSTANCE_LOWPOWER(huart))\r
+  {\r
+    /* Retrieve frequency clock */\r
+    switch (clocksource)\r
+    {\r
+      case UART_CLOCKSOURCE_PCLK1:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+#else\r
+        lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq();\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_HSI:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+#else\r
+        lpuart_ker_ck_pres = (uint32_t)HSI_VALUE;\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_SYSCLK:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+#else\r
+        lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq();\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_LSE:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+#else\r
+        lpuart_ker_ck_pres = (uint32_t)LSE_VALUE;\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_UNDEFINED:\r
+      default:\r
+        ret = HAL_ERROR;\r
+        break;\r
+    }\r
+\r
+    /* if proper clock source reported */\r
+    if (lpuart_ker_ck_pres != 0U)\r
+    {\r
+      /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */\r
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||\r
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))\r
+      {\r
+        ret = HAL_ERROR;\r
+      }\r
+      else\r
+      {\r
+        switch (clocksource)\r
+        {\r
+          case UART_CLOCKSOURCE_PCLK1:\r
+#if defined(USART_PRESC_PRESCALER)\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+            break;\r
+          case UART_CLOCKSOURCE_HSI:\r
+#if defined(USART_PRESC_PRESCALER)\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+            break;\r
+          case UART_CLOCKSOURCE_SYSCLK:\r
+#if defined(USART_PRESC_PRESCALER)\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+            break;\r
+          case UART_CLOCKSOURCE_LSE:\r
+#if defined(USART_PRESC_PRESCALER)\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+            usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+            break;\r
+          case UART_CLOCKSOURCE_UNDEFINED:\r
+          default:\r
+            ret = HAL_ERROR;\r
+            break;\r
+        }\r
+\r
+        /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */\r
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))\r
+        {\r
+          huart->Instance->BRR = usartdiv;\r
+        }\r
+        else\r
+        {\r
+          ret = HAL_ERROR;\r
+        }\r
+      } /*   if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */\r
+    } /* if (lpuart_ker_ck_pres != 0) */\r
+  }\r
+  /* Check UART Over Sampling to set Baud Rate Register */\r
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
+  {\r
+    switch (clocksource)\r
+    {\r
+      case UART_CLOCKSOURCE_PCLK1:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_PCLK2:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_HSI:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_SYSCLK:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_LSE:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_UNDEFINED:\r
+      default:\r
+        ret = HAL_ERROR;\r
+        break;\r
+    }\r
+\r
+    /* USARTDIV must be greater than or equal to 0d16 */\r
+    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))\r
+    {\r
+      brrtemp = (uint16_t)(usartdiv & 0xFFF0U);\r
+      brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r
+      huart->Instance->BRR = brrtemp;\r
+    }\r
+    else\r
+    {\r
+      ret = HAL_ERROR;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    switch (clocksource)\r
+    {\r
+      case UART_CLOCKSOURCE_PCLK1:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_PCLK2:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_HSI:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_SYSCLK:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_LSE:\r
+#if defined(USART_PRESC_PRESCALER)\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+#else\r
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));\r
+#endif /* USART_PRESC_PRESCALER */\r
+        break;\r
+      case UART_CLOCKSOURCE_UNDEFINED:\r
+      default:\r
+        ret = HAL_ERROR;\r
+        break;\r
+    }\r
+\r
+    /* USARTDIV must be greater than or equal to 0d16 */\r
+    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))\r
+    {\r
+      huart->Instance->BRR = usartdiv;\r
+    }\r
+    else\r
+    {\r
+      ret = HAL_ERROR;\r
+    }\r
+  }\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Initialize the number of data to process during RX/TX ISR execution */\r
+  huart->NbTxDataToProcess = 1;\r
+  huart->NbRxDataToProcess = 1;\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Clear ISR function pointers */\r
+  huart->RxISR = NULL;\r
+  huart->TxISR = NULL;\r
+\r
+  return ret;\r
+}\r
+\r
+/**\r
+  * @brief Configure the UART peripheral advanced features.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)\r
+{\r
+  /* Check whether the set of advanced features to configure is properly set */\r
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));\r
+\r
+  /* if required, configure TX pin active level inversion */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))\r
+  {\r
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));\r
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);\r
+  }\r
+\r
+  /* if required, configure RX pin active level inversion */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))\r
+  {\r
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));\r
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);\r
+  }\r
+\r
+  /* if required, configure data inversion */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))\r
+  {\r
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));\r
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);\r
+  }\r
+\r
+  /* if required, configure RX/TX pins swap */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))\r
+  {\r
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));\r
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);\r
+  }\r
+\r
+  /* if required, configure RX overrun detection disabling */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r
+  {\r
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));\r
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);\r
+  }\r
+\r
+  /* if required, configure DMA disabling on reception error */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))\r
+  {\r
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));\r
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);\r
+  }\r
+\r
+  /* if required, configure auto Baud rate detection scheme */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))\r
+  {\r
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));\r
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));\r
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);\r
+    /* set auto Baudrate detection parameters if detection is enabled */\r
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)\r
+    {\r
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));\r
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);\r
+    }\r
+  }\r
+\r
+  /* if required, configure MSB first on communication line */\r
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))\r
+  {\r
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));\r
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Check the UART Idle State.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)\r
+{\r
+  uint32_t tickstart;\r
+\r
+  /* Initialize the UART ErrorCode */\r
+  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+  /* Init tickstart for timeout managment*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Check if the Transmitter is enabled */\r
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+  {\r
+    /* Wait until TEACK flag is set */\r
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+    {\r
+      /* Timeout occurred */\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+\r
+  /* Check if the Receiver is enabled */\r
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+  {\r
+    /* Wait until REACK flag is set */\r
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+    {\r
+      /* Timeout occurred */\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+\r
+  /* Initialize the UART State */\r
+  huart->gState = HAL_UART_STATE_READY;\r
+  huart->RxState = HAL_UART_STATE_READY;\r
+\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Handle UART Communication Timeout.\r
+  * @param huart     UART handle.\r
+  * @param Flag      Specifies the UART flag to check\r
+  * @param Status    Flag status (SET or RESET)\r
+  * @param Tickstart Tick start value\r
+  * @param Timeout   Timeout duration\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,\r
+                                              uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+  /* Wait until flag is set */\r
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\r
+  {\r
+    /* Check for the Timeout */\r
+    if (Timeout != HAL_MAX_DELAY)\r
+    {\r
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+      {\r
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+#if defined(USART_CR1_FIFOEN)\r
+        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));\r
+#else\r
+        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r
+#endif /* USART_CR1_FIFOEN */\r
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+        huart->gState = HAL_UART_STATE_READY;\r
+        huart->RxState = HAL_UART_STATE_READY;\r
+\r
+        __HAL_UNLOCK(huart);\r
+\r
+        return HAL_TIMEOUT;\r
+      }\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Disable TXEIE, TCIE, TXFT interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));\r
+#else\r
+  /* Disable TXEIE and TCIE interrupts */\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* At end of Tx process, restore huart->gState to Ready */\r
+  huart->gState = HAL_UART_STATE_READY;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+#if defined(USART_CR1_FIFOEN)\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+#else\r
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* At end of Rx process, restore huart->RxState to Ready */\r
+  huart->RxState = HAL_UART_STATE_READY;\r
+\r
+  /* Reset RxIsr function pointer */\r
+  huart->RxISR = NULL;\r
+}\r
+\r
+\r
+/**\r
+  * @brief DMA UART transmit process complete callback.\r
+  * @param hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+  /* DMA Normal mode */\r
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))\r
+  {\r
+    huart->TxXferCount = 0U;\r
+\r
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r
+       in the UART CR3 register */\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+    /* Enable the UART Transmit Complete Interrupt */\r
+    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+  }\r
+  /* DMA Circular mode */\r
+  else\r
+  {\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    /*Call registered Tx complete callback*/\r
+    huart->TxCpltCallback(huart);\r
+#else\r
+    /*Call legacy weak Tx complete callback*/\r
+    HAL_UART_TxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief DMA UART transmit process half complete callback.\r
+  * @param hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /*Call registered Tx Half complete callback*/\r
+  huart->TxHalfCpltCallback(huart);\r
+#else\r
+  /*Call legacy weak Tx Half complete callback*/\r
+  HAL_UART_TxHalfCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief DMA UART receive process complete callback.\r
+  * @param hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+  /* DMA Normal mode */\r
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))\r
+  {\r
+    huart->RxXferCount = 0U;\r
+\r
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit\r
+       in the UART CR3 register */\r
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+    /* At end of Rx process, restore huart->RxState to Ready */\r
+    huart->RxState = HAL_UART_STATE_READY;\r
+  }\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /*Call registered Rx complete callback*/\r
+  huart->RxCpltCallback(huart);\r
+#else\r
+  /*Call legacy weak Rx complete callback*/\r
+  HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief DMA UART receive process half complete callback.\r
+  * @param hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /*Call registered Rx Half complete callback*/\r
+  huart->RxHalfCpltCallback(huart);\r
+#else\r
+  /*Call legacy weak Rx Half complete callback*/\r
+  HAL_UART_RxHalfCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief DMA UART communication error callback.\r
+  * @param hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+  const HAL_UART_StateTypeDef gstate = huart->gState;\r
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
+\r
+  /* Stop UART DMA Tx request if ongoing */\r
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
+      (gstate == HAL_UART_STATE_BUSY_TX))\r
+  {\r
+    huart->TxXferCount = 0U;\r
+    UART_EndTxTransfer(huart);\r
+  }\r
+\r
+  /* Stop UART DMA Rx request if ongoing */\r
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
+      (rxstate == HAL_UART_STATE_BUSY_RX))\r
+  {\r
+    huart->RxXferCount = 0U;\r
+    UART_EndRxTransfer(huart);\r
+  }\r
+\r
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /*Call registered error callback*/\r
+  huart->ErrorCallback(huart);\r
+#else\r
+  /*Call legacy weak error callback*/\r
+  HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error\r
+  *         (To be called at end of DMA Abort procedure following error occurrence).\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+  huart->RxXferCount = 0U;\r
+  huart->TxXferCount = 0U;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /*Call registered error callback*/\r
+  huart->ErrorCallback(huart);\r
+#else\r
+  /*Call legacy weak error callback*/\r
+  HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA UART Tx communication abort callback, when initiated by user\r
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).\r
+  * @note   When this callback is executed, User Abort complete call back is called only if no\r
+  *         Abort still ongoing for Rx DMA Handle.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+  huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+  /* Check if an Abort process is still ongoing */\r
+  if (huart->hdmarx != NULL)\r
+  {\r
+    if (huart->hdmarx->XferAbortCallback != NULL)\r
+    {\r
+      return;\r
+    }\r
+  }\r
+\r
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+  huart->TxXferCount = 0U;\r
+  huart->RxXferCount = 0U;\r
+\r
+  /* Reset errorCode */\r
+  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+  /* Clear the Error flags in the ICR register */\r
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Flush the whole TX FIFO (if needed) */\r
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+  {\r
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+  }\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Restore huart->gState and huart->RxState to Ready */\r
+  huart->gState  = HAL_UART_STATE_READY;\r
+  huart->RxState = HAL_UART_STATE_READY;\r
+\r
+  /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /* Call registered Abort complete callback */\r
+  huart->AbortCpltCallback(huart);\r
+#else\r
+  /* Call legacy weak Abort complete callback */\r
+  HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  DMA UART Rx communication abort callback, when initiated by user\r
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).\r
+  * @note   When this callback is executed, User Abort complete call back is called only if no\r
+  *         Abort still ongoing for Tx DMA Handle.\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+  huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+  /* Check if an Abort process is still ongoing */\r
+  if (huart->hdmatx != NULL)\r
+  {\r
+    if (huart->hdmatx->XferAbortCallback != NULL)\r
+    {\r
+      return;\r
+    }\r
+  }\r
+\r
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+  huart->TxXferCount = 0U;\r
+  huart->RxXferCount = 0U;\r
+\r
+  /* Reset errorCode */\r
+  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+  /* Clear the Error flags in the ICR register */\r
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+  /* Discard the received data */\r
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+  /* Restore huart->gState and huart->RxState to Ready */\r
+  huart->gState  = HAL_UART_STATE_READY;\r
+  huart->RxState = HAL_UART_STATE_READY;\r
+\r
+  /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /* Call registered Abort complete callback */\r
+  huart->AbortCpltCallback(huart);\r
+#else\r
+  /* Call legacy weak Abort complete callback */\r
+  HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to\r
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)\r
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,\r
+  *         and leads to user Tx Abort Complete callback execution).\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+  huart->TxXferCount = 0U;\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+  /* Flush the whole TX FIFO (if needed) */\r
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+  {\r
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+  }\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+  /* Restore huart->gState to Ready */\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /* Call registered Abort Transmit Complete Callback */\r
+  huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+  /* Call legacy weak Abort Transmit Complete Callback */\r
+  HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to\r
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)\r
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,\r
+  *         and leads to user Rx Abort Complete callback execution).\r
+  * @param  hdma DMA handle.\r
+  * @retval None\r
+  */\r
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+  huart->RxXferCount = 0U;\r
+\r
+  /* Clear the Error flags in the ICR register */\r
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+  /* Discard the received data */\r
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+  /* Restore huart->RxState to Ready */\r
+  huart->RxState = HAL_UART_STATE_READY;\r
+\r
+  /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /* Call registered Abort Receive Complete Callback */\r
+  huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+  /* Call legacy weak Abort Receive Complete Callback */\r
+  HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief TX interrrupt handler for 7 or 8 bits data word length .\r
+  * @note   Function is called under interruption only, once\r
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)\r
+{\r
+  /* Check that a Tx process is ongoing */\r
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+  {\r
+    if (huart->TxXferCount == 0U)\r
+    {\r
+      /* Disable the UART Transmit Data Register Empty Interrupt */\r
+#if defined(USART_CR1_FIFOEN)\r
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
+#else\r
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+      /* Enable the UART Transmit Complete Interrupt */\r
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+    }\r
+    else\r
+    {\r
+      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);\r
+      huart->pTxBuffPtr++;\r
+      huart->TxXferCount--;\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief TX interrrupt handler for 9 bits data word length.\r
+  * @note   Function is called under interruption only, once\r
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)\r
+{\r
+  uint16_t *tmp;\r
+\r
+  /* Check that a Tx process is ongoing */\r
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+  {\r
+    if (huart->TxXferCount == 0U)\r
+    {\r
+      /* Disable the UART Transmit Data Register Empty Interrupt */\r
+#if defined(USART_CR1_FIFOEN)\r
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
+#else\r
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+      /* Enable the UART Transmit Complete Interrupt */\r
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+    }\r
+    else\r
+    {\r
+      tmp = (uint16_t *) huart->pTxBuffPtr;\r
+      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);\r
+      huart->pTxBuffPtr += 2U;\r
+      huart->TxXferCount--;\r
+    }\r
+  }\r
+}\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/**\r
+  * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.\r
+  * @note   Function is called under interruption only, once\r
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+  uint16_t  nb_tx_data;\r
+\r
+  /* Check that a Tx process is ongoing */\r
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+  {\r
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
+    {\r
+      if (huart->TxXferCount == 0U)\r
+      {\r
+        /* Disable the TX FIFO threshold interrupt */\r
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+\r
+        /* Enable the UART Transmit Complete Interrupt */\r
+        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+        break; /* force exit loop */\r
+      }\r
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)\r
+      {\r
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);\r
+        huart->pTxBuffPtr++;\r
+        huart->TxXferCount--;\r
+      }\r
+      else\r
+      {\r
+        /* Nothing to do */\r
+      }\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.\r
+  * @note   Function is called under interruption only, once\r
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+  uint16_t *tmp;\r
+  uint16_t  nb_tx_data;\r
+\r
+  /* Check that a Tx process is ongoing */\r
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+  {\r
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
+    {\r
+      if (huart->TxXferCount == 0U)\r
+      {\r
+        /* Disable the TX FIFO threshold interrupt */\r
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+\r
+        /* Enable the UART Transmit Complete Interrupt */\r
+        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+        break; /* force exit loop */\r
+      }\r
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)\r
+      {\r
+        tmp = (uint16_t *) huart->pTxBuffPtr;\r
+        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);\r
+        huart->pTxBuffPtr += 2U;\r
+        huart->TxXferCount--;\r
+      }\r
+      else\r
+      {\r
+        /* Nothing to do */\r
+      }\r
+    }\r
+  }\r
+}\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @brief  Wrap up transmission in non-blocking mode.\r
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains\r
+  *                the configuration information for the specified UART module.\r
+  * @retval None\r
+  */\r
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+  /* Disable the UART Transmit Complete Interrupt */\r
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+  /* Tx process is ended, restore huart->gState to Ready */\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  /* Cleat TxISR function pointer */\r
+  huart->TxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+  /*Call registered Tx complete callback*/\r
+  huart->TxCpltCallback(huart);\r
+#else\r
+  /*Call legacy weak Tx complete callback*/\r
+  HAL_UART_TxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+  * @brief RX interrrupt handler for 7 or 8 bits data word length .\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)\r
+{\r
+  uint16_t uhMask = huart->Mask;\r
+  uint16_t  uhdata;\r
+\r
+  /* Check that a Rx process is ongoing */\r
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+  {\r
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);\r
+    huart->pRxBuffPtr++;\r
+    huart->RxXferCount--;\r
+\r
+    if (huart->RxXferCount == 0U)\r
+    {\r
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */\r
+#if defined(USART_CR1_FIFOEN)\r
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+#else\r
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+      /* Rx process is completed, restore huart->RxState to Ready */\r
+      huart->RxState = HAL_UART_STATE_READY;\r
+\r
+      /* Clear RxISR function pointer */\r
+      huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+      /*Call registered Rx complete callback*/\r
+      huart->RxCpltCallback(huart);\r
+#else\r
+      /*Call legacy weak Rx complete callback*/\r
+      HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Clear RXNE interrupt flag */\r
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief RX interrrupt handler for 9 bits data word length .\r
+  * @note   Function is called under interruption only, once\r
+  *         interruptions have been enabled by HAL_UART_Receive_IT()\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)\r
+{\r
+  uint16_t *tmp;\r
+  uint16_t uhMask = huart->Mask;\r
+  uint16_t  uhdata;\r
+\r
+  /* Check that a Rx process is ongoing */\r
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+  {\r
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+    tmp = (uint16_t *) huart->pRxBuffPtr ;\r
+    *tmp = (uint16_t)(uhdata & uhMask);\r
+    huart->pRxBuffPtr += 2U;\r
+    huart->RxXferCount--;\r
+\r
+    if (huart->RxXferCount == 0U)\r
+    {\r
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/\r
+#if defined(USART_CR1_FIFOEN)\r
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+#else\r
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+      /* Rx process is completed, restore huart->RxState to Ready */\r
+      huart->RxState = HAL_UART_STATE_READY;\r
+\r
+      /* Clear RxISR function pointer */\r
+      huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+      /*Call registered Rx complete callback*/\r
+      huart->RxCpltCallback(huart);\r
+#else\r
+      /*Call legacy weak Rx complete callback*/\r
+      HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Clear RXNE interrupt flag */\r
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+  }\r
+}\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/**\r
+  * @brief RX interrrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.\r
+  * @note   Function is called under interruption only, once\r
+  *         interruptions have been enabled by HAL_UART_Receive_IT()\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+  uint16_t  uhMask = huart->Mask;\r
+  uint16_t  uhdata;\r
+  uint16_t   nb_rx_data;\r
+  uint16_t  rxdatacount;\r
+\r
+  /* Check that a Rx process is ongoing */\r
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+  {\r
+    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
+    {\r
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);\r
+      huart->pRxBuffPtr++;\r
+      huart->RxXferCount--;\r
+\r
+      if (huart->RxXferCount == 0U)\r
+      {\r
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/\r
+        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
+        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+        /* Rx process is completed, restore huart->RxState to Ready */\r
+        huart->RxState = HAL_UART_STATE_READY;\r
+\r
+        /* Clear RxISR function pointer */\r
+        huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+        /*Call registered Rx complete callback*/\r
+        huart->RxCpltCallback(huart);\r
+#else\r
+        /*Call legacy weak Rx complete callback*/\r
+        HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+      }\r
+    }\r
+\r
+    /* When remaining number of bytes to receive is less than the RX FIFO\r
+    threshold, next incoming frames are processed as if FIFO mode was\r
+    disabled (i.e. one interrupt per received frame).\r
+    */\r
+    rxdatacount = huart->RxXferCount;\r
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))\r
+    {\r
+      /* Disable the UART RXFT interrupt*/\r
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
+\r
+      /* Update the RxISR function pointer */\r
+      huart->RxISR = UART_RxISR_8BIT;\r
+\r
+      /* Enable the UART Data Register Not Empty interrupt */\r
+      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Clear RXNE interrupt flag */\r
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.\r
+  * @note   Function is called under interruption only, once\r
+  *         interruptions have been enabled by HAL_UART_Receive_IT()\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+  uint16_t *tmp;\r
+  uint16_t  uhMask = huart->Mask;\r
+  uint16_t  uhdata;\r
+  uint16_t   nb_rx_data;\r
+  uint16_t  rxdatacount;\r
+\r
+  /* Check that a Rx process is ongoing */\r
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+  {\r
+    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
+    {\r
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+      tmp = (uint16_t *) huart->pRxBuffPtr ;\r
+      *tmp = (uint16_t)(uhdata & uhMask);\r
+      huart->pRxBuffPtr += 2U;\r
+      huart->RxXferCount--;\r
+\r
+      if (huart->RxXferCount == 0U)\r
+      {\r
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/\r
+        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
+        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+        /* Rx process is completed, restore huart->RxState to Ready */\r
+        huart->RxState = HAL_UART_STATE_READY;\r
+\r
+        /* Clear RxISR function pointer */\r
+        huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+        /*Call registered Rx complete callback*/\r
+        huart->RxCpltCallback(huart);\r
+#else\r
+        /*Call legacy weak Rx complete callback*/\r
+        HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+      }\r
+    }\r
+\r
+    /* When remaining number of bytes to receive is less than the RX FIFO\r
+    threshold, next incoming frames are processed as if FIFO mode was\r
+    disabled (i.e. one interrupt per received frame).\r
+    */\r
+    rxdatacount = huart->RxXferCount;\r
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))\r
+    {\r
+      /* Disable the UART RXFT interrupt*/\r
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
+\r
+      /* Update the RxISR function pointer */\r
+      huart->RxISR = UART_RxISR_16BIT;\r
+\r
+      /* Enable the UART Data Register Not Empty interrupt */\r
+      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* Clear RXNE interrupt flag */\r
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+  }\r
+}\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
new file mode 100644 (file)
index 0000000..98f6d33
--- /dev/null
@@ -0,0 +1,787 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_hal_uart_ex.c\r
+  * @author  MCD Application Team\r
+  * @brief   Extended UART HAL module driver.\r
+  *          This file provides firmware functions to manage the following extended\r
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\r
+  *           + Initialization and de-initialization functions\r
+  *           + Peripheral Control functions\r
+  *\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+               ##### UART peripheral extended features  #####\r
+  ==============================================================================\r
+\r
+    (#) Declare a UART_HandleTypeDef handle structure.\r
+\r
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers\r
+        by calling the HAL_RS485Ex_Init() API.\r
+\r
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.\r
+\r
+        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior\r
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be\r
+            configured prior starting RX/TX transfers.\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup UARTEx UARTEx\r
+  * @brief UART Extended HAL module driver\r
+  * @{\r
+  */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#if defined(USART_CR1_FIFOEN)\r
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants\r
+  * @{\r
+  */\r
+/* UART RX FIFO depth */\r
+#define RX_FIFO_DEPTH 8U\r
+\r
+/* UART TX FIFO depth */\r
+#define TX_FIFO_DEPTH 8U\r
+/**\r
+  * @}\r
+  */\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions\r
+  * @{\r
+  */\r
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);\r
+#if defined(USART_CR1_FIFOEN)\r
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);\r
+#endif /* USART_CR1_FIFOEN */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions\r
+  * @brief    Extended Initialization and Configuration Functions\r
+  *\r
+@verbatim\r
+===============================================================================\r
+            ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+    [..]\r
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
+    in asynchronous mode.\r
+      (+) For the asynchronous mode the parameters below can be configured:\r
+        (++) Baud Rate\r
+        (++) Word Length\r
+        (++) Stop Bit\r
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+             in the data register is transmitted but is changed by the parity bit.\r
+        (++) Hardware flow control\r
+        (++) Receiver/transmitter modes\r
+        (++) Over Sampling Method\r
+        (++) One-Bit Sampling Method\r
+      (+) For the asynchronous mode, the following advanced features can be configured as well:\r
+        (++) TX and/or RX pin level inversion\r
+        (++) data logical level inversion\r
+        (++) RX and TX pins swap\r
+        (++) RX overrun detection disabling\r
+        (++) DMA disabling on RX error\r
+        (++) MSB first on communication line\r
+        (++) auto Baud rate detection\r
+    [..]\r
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration\r
+     procedures (details for the procedures are available in reference manual).\r
+\r
+@endverbatim\r
+\r
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
+  8-bit or 9-bit), the possible UART formats are listed in the\r
+  following table.\r
+\r
+    Table 1. UART frame format.\r
+    +-----------------------------------------------------------------------+\r
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |\r
+    |---------|---------|-----------|---------------------------------------|\r
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |\r
+    +-----------------------------------------------------------------------+\r
+\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Initialize the RS485 Driver enable feature according to the specified\r
+  *         parameters in the UART_InitTypeDef and creates the associated handle.\r
+  * @param huart            UART handle.\r
+  * @param Polarity         Select the driver enable polarity.\r
+  *          This parameter can be one of the following values:\r
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high\r
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low\r
+  * @param AssertionTime    Driver Enable assertion time:\r
+  *       5-bit value defining the time between the activation of the DE (Driver Enable)\r
+  *       signal and the beginning of the start bit. It is expressed in sample time\r
+  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)\r
+  * @param DeassertionTime  Driver Enable deassertion time:\r
+  *       5-bit value defining the time between the end of the last stop bit, in a\r
+  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.\r
+  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the\r
+  *       oversampling rate).\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,\r
+                                   uint32_t DeassertionTime)\r
+{\r
+  uint32_t temp;\r
+\r
+  /* Check the UART handle allocation */\r
+  if (huart == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+  /* Check the Driver Enable UART instance */\r
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));\r
+\r
+  /* Check the Driver Enable polarity */\r
+  assert_param(IS_UART_DE_POLARITY(Polarity));\r
+\r
+  /* Check the Driver Enable assertion time */\r
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));\r
+\r
+  /* Check the Driver Enable deassertion time */\r
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));\r
+\r
+  if (huart->gState == HAL_UART_STATE_RESET)\r
+  {\r
+    /* Allocate lock resource and initialize it */\r
+    huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+    UART_InitCallbacksToDefault(huart);\r
+\r
+    if (huart->MspInitCallback == NULL)\r
+    {\r
+      huart->MspInitCallback = HAL_UART_MspInit;\r
+    }\r
+\r
+    /* Init the low level hardware */\r
+    huart->MspInitCallback(huart);\r
+#else\r
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
+    HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+  }\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Set the UART Communication parameters */\r
+  if (UART_SetConfig(huart) == HAL_ERROR)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+  {\r
+    UART_AdvFeatureConfig(huart);\r
+  }\r
+\r
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */\r
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);\r
+\r
+  /* Set the Driver Enable polarity */\r
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);\r
+\r
+  /* Set the Driver Enable assertion and deassertion times */\r
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);\r
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);\r
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);\r
+\r
+  /* Enable the Peripheral */\r
+  __HAL_UART_ENABLE(huart);\r
+\r
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions\r
+  *  @brief Extended functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### IO operation functions #####\r
+ ===============================================================================\r
+    This subsection provides a set of Wakeup and FIFO mode related callback functions.\r
+\r
+    (#) Wakeup from Stop mode Callback:\r
+        (+) HAL_UARTEx_WakeupCallback()\r
+\r
+    (#) TX/RX Fifos Callbacks:\r
+        (+) HAL_UARTEx_RxFifoFullCallback()\r
+        (+) HAL_UARTEx_TxFifoEmptyCallback()\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief UART wakeup from Stop mode callback.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/**\r
+  * @brief  UART RX Fifo full callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  UART TX Fifo empty callback.\r
+  * @param  huart UART handle.\r
+  * @retval None\r
+  */\r
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(huart);\r
+\r
+  /* NOTE : This function should not be modified, when the callback is needed,\r
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.\r
+   */\r
+}\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions\r
+  * @brief    Extended Peripheral Control functions\r
+  *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+    [..] This section provides the following functions:\r
+     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode\r
+     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality\r
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address\r
+         detection length to more than 4 bits for multiprocessor address mark wake up.\r
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode\r
+         trigger: address match, Start Bit detection or RXNE bit status.\r
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode\r
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality\r
+     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode\r
+     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode\r
+     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold\r
+     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+\r
+\r
+#if defined(USART_CR3_UCESM)\r
+/**\r
+  * @brief  Keep UART Clock enabled when in Stop Mode.\r
+  * @note   When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled\r
+  *         this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.\r
+  * @note   When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source,\r
+  *         and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set.\r
+  * @param  huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart)\r
+{\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  /* Set UCESM bit */\r
+  SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Disable UART Clock when in Stop Mode.\r
+  * @param  huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart)\r
+{\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  /* Clear UCESM bit */\r
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+#endif /* USART_CR3_UCESM */\r
+\r
+/**\r
+  * @brief By default in multiprocessor mode, when the wake up method is set\r
+  *        to address mark, the UART handles only 4-bit long addresses detection;\r
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit\r
+  *        long).\r
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,\r
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.\r
+  * @param huart         UART handle.\r
+  * @param AddressLength This parameter can be one of the following values:\r
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address\r
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)\r
+{\r
+  /* Check the UART handle allocation */\r
+  if (huart == NULL)\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+\r
+  /* Check the address length parameter */\r
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Set the address length */\r
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);\r
+\r
+  /* Enable the Peripheral */\r
+  __HAL_UART_ENABLE(huart);\r
+\r
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */\r
+  return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+  * @brief Set Wakeup from Stop mode interrupt flag selection.\r
+  * @note It is the application responsibility to enable the interrupt used as\r
+  *       usart_wkup interrupt source before entering low-power mode.\r
+  * @param huart           UART handle.\r
+  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.\r
+  *          This parameter can be one of the following values:\r
+  *          @arg @ref UART_WAKEUP_ON_ADDRESS\r
+  *          @arg @ref UART_WAKEUP_ON_STARTBIT\r
+  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)\r
+{\r
+  HAL_StatusTypeDef status = HAL_OK;\r
+  uint32_t tickstart;\r
+\r
+  /* check the wake-up from stop mode UART instance */\r
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));\r
+  /* check the wake-up selection parameter */\r
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Disable the Peripheral */\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Set the wake-up selection scheme */\r
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);\r
+\r
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)\r
+  {\r
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);\r
+  }\r
+\r
+  /* Enable the Peripheral */\r
+  __HAL_UART_ENABLE(huart);\r
+\r
+  /* Init tickstart for timeout managment*/\r
+  tickstart = HAL_GetTick();\r
+\r
+  /* Wait until REACK flag is set */\r
+  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+  {\r
+    status = HAL_TIMEOUT;\r
+  }\r
+  else\r
+  {\r
+    /* Initialize the UART State */\r
+    huart->gState = HAL_UART_STATE_READY;\r
+  }\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return status;\r
+}\r
+\r
+/**\r
+  * @brief Enable UART Stop Mode.\r
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)\r
+{\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  /* Set UESM bit */\r
+  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Disable UART Stop Mode.\r
+  * @param huart UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)\r
+{\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  /* Clear UESM bit */\r
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/**\r
+  * @brief  Enable the FIFO mode.\r
+  * @param huart      UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)\r
+{\r
+  uint32_t tmpcr1;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Save actual UART configuration */\r
+  tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+  /* Disable UART */\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Enable FIFO mode */\r
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);\r
+  huart->FifoMode = UART_FIFOMODE_ENABLE;\r
+\r
+  /* Restore UART configuration */\r
+  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+  /* Determine the number of data to process during RX/TX ISR execution */\r
+  UARTEx_SetNbDataToProcess(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Disable the FIFO mode.\r
+  * @param huart      UART handle.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)\r
+{\r
+  uint32_t tmpcr1;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Save actual UART configuration */\r
+  tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+  /* Disable UART */\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Enable FIFO mode */\r
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);\r
+  huart->FifoMode = UART_FIFOMODE_DISABLE;\r
+\r
+  /* Restore UART configuration */\r
+  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Set the TXFIFO threshold.\r
+  * @param huart      UART handle.\r
+  * @param Threshold  TX FIFO threshold value\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8\r
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4\r
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2\r
+  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4\r
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8\r
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)\r
+{\r
+  uint32_t tmpcr1;\r
+\r
+  /* Check parameters */\r
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Save actual UART configuration */\r
+  tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+  /* Disable UART */\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Update TX threshold configuration */\r
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);\r
+\r
+  /* Determine the number of data to process during RX/TX ISR execution */\r
+  UARTEx_SetNbDataToProcess(huart);\r
+\r
+  /* Restore UART configuration */\r
+  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Set the RXFIFO threshold.\r
+  * @param huart      UART handle.\r
+  * @param Threshold  RX FIFO threshold value\r
+  *          This parameter can be one of the following values:\r
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8\r
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4\r
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2\r
+  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4\r
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8\r
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)\r
+{\r
+  uint32_t tmpcr1;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));\r
+\r
+  /* Process Locked */\r
+  __HAL_LOCK(huart);\r
+\r
+  huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+  /* Save actual UART configuration */\r
+  tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+  /* Disable UART */\r
+  __HAL_UART_DISABLE(huart);\r
+\r
+  /* Update RX threshold configuration */\r
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);\r
+\r
+  /* Determine the number of data to process during RX/TX ISR execution */\r
+  UARTEx_SetNbDataToProcess(huart);\r
+\r
+  /* Restore UART configuration */\r
+  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+  huart->gState = HAL_UART_STATE_READY;\r
+\r
+  /* Process Unlocked */\r
+  __HAL_UNLOCK(huart);\r
+\r
+  return HAL_OK;\r
+}\r
+#endif /* USART_CR1_FIFOEN */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup UARTEx_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.\r
+  * @param huart           UART handle.\r
+  * @param WakeUpSelection UART wake up from stop mode parameters.\r
+  * @retval None\r
+  */\r
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)\r
+{\r
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));\r
+\r
+  /* Set the USART address length */\r
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);\r
+\r
+  /* Set the USART address node */\r
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));\r
+}\r
+\r
+#if defined(USART_CR1_FIFOEN)\r
+/**\r
+  * @brief Calculate the number of data to process in RX/TX ISR.\r
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from\r
+  *       the UART configuration registers.\r
+  * @param huart UART handle.\r
+  * @retval None\r
+  */\r
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)\r
+{\r
+  uint8_t rx_fifo_depth;\r
+  uint8_t tx_fifo_depth;\r
+  uint8_t rx_fifo_threshold;\r
+  uint8_t tx_fifo_threshold;\r
+  uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};\r
+  uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};\r
+\r
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)\r
+  {\r
+    huart->NbTxDataToProcess = 1U;\r
+    huart->NbRxDataToProcess = 1U;\r
+  }\r
+  else\r
+  {\r
+    rx_fifo_depth = RX_FIFO_DEPTH;\r
+    tx_fifo_depth = TX_FIFO_DEPTH;\r
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);\r
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);\r
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];\r
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];\r
+  }\r
+}\r
+#endif /* USART_CR1_FIFOEN */\r
+/**\r
+  * @}\r
+  */\r
+\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
new file mode 100644 (file)
index 0000000..4533162
--- /dev/null
@@ -0,0 +1,2611 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l4xx_ll_usb.c\r
+  * @author  MCD Application Team\r
+  * @brief   USB Low Layer HAL module driver.\r
+  *\r
+  *          This file provides firmware functions to manage the following\r
+  *          functionalities of the USB Peripheral Controller:\r
+  *           + Initialization/de-initialization functions\r
+  *           + I/O operation functions\r
+  *           + Peripheral Control functions\r
+  *           + Peripheral State functions\r
+  *\r
+  @verbatim\r
+  ==============================================================================\r
+                    ##### How to use this driver #####\r
+  ==============================================================================\r
+    [..]\r
+      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r
+\r
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r
+\r
+      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r
+\r
+  @endverbatim\r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
+  * All rights reserved.</center></h2>\r
+  *\r
+  * This software component is licensed by ST under BSD 3-Clause license,\r
+  * the "License"; You may not use this file except in compliance with the\r
+  * License. You may obtain a copy of the License at:\r
+  *                        opensource.org/licenses/BSD-3-Clause\r
+  *\r
+  ******************************************************************************\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_LL_USB_DRIVER\r
+  * @{\r
+  */\r
+\r
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r
+#if defined (USB) || defined (USB_OTG_FS)\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+#if defined (USB_OTG_FS)\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions\r
+  * @{\r
+  */\r
+\r
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions\r
+ *  @brief    Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+                      ##### Initialization/de-initialization functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Initializes the USB Core\r
+  * @param  USBx USB Instance\r
+  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains\r
+  *         the configuration information for the specified USBx peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+  HAL_StatusTypeDef ret;\r
+\r
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+  {\r
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+\r
+    /* Init The ULPI Interface */\r
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r
+\r
+    /* Select vbus source */\r
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r
+    if (cfg.use_external_vbus == 1U)\r
+    {\r
+      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r
+    }\r
+    /* Reset after a PHY select  */\r
+    ret = USB_CoreReset(USBx);\r
+  }\r
+  else /* FS interface (embedded Phy) */\r
+  {\r
+    /* Select FS Embedded PHY */\r
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r
+\r
+    /* Reset after a PHY select and set Host mode */\r
+    ret = USB_CoreReset(USBx);\r
+\r
+    if (cfg.battery_charging_enable == 0U)\r
+    {\r
+      /* Activate the USB Transceiver */\r
+      USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\r
+    }\r
+    else\r
+    {\r
+      /* Deactivate the USB Transceiver */\r
+      USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+    }\r
+  }\r
+\r
+  return ret;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Set the USB turnaround time\r
+  * @param  USBx USB Instance\r
+  * @param  hclk: AHB clock frequency\r
+  * @retval USB turnaround time In PHY Clocks number\r
+  */\r
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,\r
+                                        uint32_t hclk, uint8_t speed)\r
+{\r
+  uint32_t UsbTrd;\r
+\r
+  /* The USBTRD is configured according to the tables below, depending on AHB frequency\r
+  used by application. In the low AHB frequency range it is used to stretch enough the USB response\r
+  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access\r
+  latency to the Data FIFO */\r
+  if (speed == USBD_FS_SPEED)\r
+  {\r
+    if ((hclk >= 14200000U) && (hclk < 15000000U))\r
+    {\r
+      /* hclk Clock Range between 14.2-15 MHz */\r
+      UsbTrd = 0xFU;\r
+    }\r
+    else if ((hclk >= 15000000U) && (hclk < 16000000U))\r
+    {\r
+      /* hclk Clock Range between 15-16 MHz */\r
+      UsbTrd = 0xEU;\r
+    }\r
+    else if ((hclk >= 16000000U) && (hclk < 17200000U))\r
+    {\r
+      /* hclk Clock Range between 16-17.2 MHz */\r
+      UsbTrd = 0xDU;\r
+    }\r
+    else if ((hclk >= 17200000U) && (hclk < 18500000U))\r
+    {\r
+      /* hclk Clock Range between 17.2-18.5 MHz */\r
+      UsbTrd = 0xCU;\r
+    }\r
+    else if ((hclk >= 18500000U) && (hclk < 20000000U))\r
+    {\r
+      /* hclk Clock Range between 18.5-20 MHz */\r
+      UsbTrd = 0xBU;\r
+    }\r
+    else if ((hclk >= 20000000U) && (hclk < 21800000U))\r
+    {\r
+      /* hclk Clock Range between 20-21.8 MHz */\r
+      UsbTrd = 0xAU;\r
+    }\r
+    else if ((hclk >= 21800000U) && (hclk < 24000000U))\r
+    {\r
+      /* hclk Clock Range between 21.8-24 MHz */\r
+      UsbTrd = 0x9U;\r
+    }\r
+    else if ((hclk >= 24000000U) && (hclk < 27700000U))\r
+    {\r
+      /* hclk Clock Range between 24-27.7 MHz */\r
+      UsbTrd = 0x8U;\r
+    }\r
+    else if ((hclk >= 27700000U) && (hclk < 32000000U))\r
+    {\r
+      /* hclk Clock Range between 27.7-32 MHz */\r
+      UsbTrd = 0x7U;\r
+    }\r
+    else /* if(hclk >= 32000000) */\r
+    {\r
+      /* hclk Clock Range between 32-200 MHz */\r
+      UsbTrd = 0x6U;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    UsbTrd = USBD_DEFAULT_TRDT_VALUE;\r
+  }\r
+\r
+  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\r
+  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_EnableGlobalInt\r
+  *         Enables the controller's Global Int in the AHB Config reg\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DisableGlobalInt\r
+  *         Disable the controller's Global Int in the AHB Config reg\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_SetCurrentMode : Set functional mode\r
+  * @param  USBx  Selected device\r
+  * @param  mode   current core mode\r
+  *          This parameter can be one of these values:\r
+  *            @arg USB_DEVICE_MODE: Peripheral mode\r
+  *            @arg USB_HOST_MODE: Host mode\r
+  *            @arg USB_DRD_MODE: Dual Role Device mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)\r
+{\r
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);\r
+\r
+  if (mode == USB_HOST_MODE)\r
+  {\r
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;\r
+  }\r
+  else if (mode == USB_DEVICE_MODE)\r
+  {\r
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;\r
+  }\r
+  else\r
+  {\r
+    return HAL_ERROR;\r
+  }\r
+  HAL_Delay(50U);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DevInit : Initializes the USB_OTG controller registers\r
+  *         for device mode\r
+  * @param  USBx  Selected device\r
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\r
+  *         the configuration information for the specified USBx peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+  HAL_StatusTypeDef ret = HAL_OK;\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t i;\r
+\r
+  for (i = 0U; i < 15U; i++)\r
+  {\r
+    USBx->DIEPTXF[i] = 0U;\r
+  }\r
+\r
+  /* VBUS Sensing setup */\r
+  if (cfg.vbus_sensing_enable == 0U)\r
+  {\r
+    /* Deactivate VBUS Sensing B */\r
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;\r
+\r
+    /* B-peripheral session valid override enable */\r
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r
+  }\r
+  else\r
+  {\r
+    /* Enable HW VBUS sensing */\r
+    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+  }\r
+\r
+  /* Restart the Phy Clock */\r
+  USBx_PCGCCTL = 0U;\r
+\r
+  /* Device mode configuration */\r
+  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r
+\r
+  /* Set Core speed to Full speed mode */\r
+  (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);\r
+\r
+  /* Flush the FIFOs */\r
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */\r
+  {\r
+    ret = HAL_ERROR;\r
+  }\r
+\r
+  if (USB_FlushRxFifo(USBx) != HAL_OK)\r
+  {\r
+    ret = HAL_ERROR;\r
+  }\r
+\r
+  /* Clear all pending Device Interrupts */\r
+  USBx_DEVICE->DIEPMSK = 0U;\r
+  USBx_DEVICE->DOEPMSK = 0U;\r
+  USBx_DEVICE->DAINTMSK = 0U;\r
+\r
+  for (i = 0U; i < cfg.dev_endpoints; i++)\r
+  {\r
+    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r
+    {\r
+      if (i == 0U)\r
+      {\r
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;\r
+      }\r
+      else\r
+      {\r
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      USBx_INEP(i)->DIEPCTL = 0U;\r
+    }\r
+\r
+    USBx_INEP(i)->DIEPTSIZ = 0U;\r
+    USBx_INEP(i)->DIEPINT  = 0xFB7FU;\r
+  }\r
+\r
+  for (i = 0U; i < cfg.dev_endpoints; i++)\r
+  {\r
+    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
+    {\r
+      if (i == 0U)\r
+      {\r
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;\r
+      }\r
+      else\r
+      {\r
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;\r
+      }\r
+    }\r
+    else\r
+    {\r
+      USBx_OUTEP(i)->DOEPCTL = 0U;\r
+    }\r
+\r
+    USBx_OUTEP(i)->DOEPTSIZ = 0U;\r
+    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;\r
+  }\r
+\r
+  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r
+\r
+  /* Disable all interrupts. */\r
+  USBx->GINTMSK = 0U;\r
+\r
+  /* Clear any pending interrupts */\r
+  USBx->GINTSTS = 0xBFFFFFFFU;\r
+\r
+  /* Enable the common interrupts */\r
+  USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r
+\r
+  /* Enable interrupts matching to the Device mode ONLY */\r
+  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\r
+                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\r
+                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |\r
+                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;\r
+\r
+  if (cfg.Sof_enable != 0U)\r
+  {\r
+    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r
+  }\r
+\r
+  if (cfg.vbus_sensing_enable == 1U)\r
+  {\r
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);\r
+  }\r
+\r
+  return ret;\r
+}\r
+\r
+/**\r
+  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO\r
+  * @param  USBx  Selected device\r
+  * @param  num  FIFO number\r
+  *         This parameter can be a value from 1 to 15\r
+            15 means Flush all Tx FIFOs\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)\r
+{\r
+  uint32_t count = 0U;\r
+\r
+  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));\r
+\r
+  do\r
+  {\r
+    if (++count > 200000U)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_FlushRxFifo : Flush Rx FIFO\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t count = 0;\r
+\r
+  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r
+\r
+  do\r
+  {\r
+    if (++count > 200000U)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register\r
+  *         depending the PHY type and the enumeration speed of the device.\r
+  * @param  USBx  Selected device\r
+  * @param  speed  device speed\r
+  *          This parameter can be one of these values:\r
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r
+  * @retval  Hal status\r
+  */\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  USBx_DEVICE->DCFG |= speed;\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_GetDevSpeed  Return the Dev Speed\r
+  * @param  USBx  Selected device\r
+  * @retval speed  device speed\r
+  *          This parameter can be one of these values:\r
+  *            @arg PCD_SPEED_FULL: Full speed mode\r
+  */\r
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint8_t speed;\r
+  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;\r
+\r
+  if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||\r
+      (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))\r
+  {\r
+    speed = USBD_FS_SPEED;\r
+  }\r
+  else\r
+  {\r
+    speed = 0xFU;\r
+  }\r
+\r
+  return speed;\r
+}\r
+\r
+/**\r
+  * @brief  Activate and configure an endpoint\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+\r
+  if (ep->is_in == 1U)\r
+  {\r
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\r
+\r
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)\r
+    {\r
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |\r
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+                                   USB_OTG_DIEPCTL_USBAEP;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\r
+\r
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r
+    {\r
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r
+                                    ((uint32_t)ep->type << 18) |\r
+                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+                                    USB_OTG_DOEPCTL_USBAEP;\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Activate and configure a dedicated endpoint\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+\r
+  /* Read DEPCTLn register */\r
+  if (ep->is_in == 1U)\r
+  {\r
+    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)\r
+    {\r
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |\r
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+                                   USB_OTG_DIEPCTL_USBAEP;\r
+    }\r
+\r
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\r
+  }\r
+  else\r
+  {\r
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r
+    {\r
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r
+                                    ((uint32_t)ep->type << 18) | (epnum << 22) |\r
+                                    USB_OTG_DOEPCTL_USBAEP;\r
+    }\r
+\r
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  De-activate and de-initialize an endpoint\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+\r
+  /* Read DEPCTLn register */\r
+  if (ep->is_in == 1U)\r
+  {\r
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
+    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |\r
+                                   USB_OTG_DIEPCTL_MPSIZ |\r
+                                   USB_OTG_DIEPCTL_TXFNUM |\r
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+                                   USB_OTG_DIEPCTL_EPTYP);\r
+  }\r
+  else\r
+  {\r
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
+    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |\r
+                                    USB_OTG_DOEPCTL_MPSIZ |\r
+                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |\r
+                                    USB_OTG_DOEPCTL_EPTYP);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  De-activate and de-initialize a dedicated endpoint\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+\r
+  /* Read DEPCTLn register */\r
+  if (ep->is_in == 1U)\r
+  {\r
+    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
+  }\r
+  else\r
+  {\r
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;\r
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+  uint16_t pktcnt;\r
+\r
+  /* IN endpoint */\r
+  if (ep->is_in == 1U)\r
+  {\r
+    /* Zero Length Packet? */\r
+    if (ep->xfer_len == 0U)\r
+    {\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+    }\r
+    else\r
+    {\r
+      /* Program the transfer size and packet count\r
+      * as follows: xfersize = N * maxpacket +\r
+      * short_packet pktcnt = N + (short_packet\r
+      * exist ? 1 : 0)\r
+      */\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));\r
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r
+\r
+      if (ep->type == EP_TYPE_ISOC)\r
+      {\r
+        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);\r
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));\r
+      }\r
+    }\r
+    /* EP enable, IN data in FIFO */\r
+    USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
+\r
+    if (ep->type != EP_TYPE_ISOC)\r
+    {\r
+      /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+      if (ep->xfer_len > 0U)\r
+      {\r
+        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r
+      {\r
+        USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r
+      }\r
+      else\r
+      {\r
+        USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r
+      }\r
+\r
+      (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len);\r
+    }\r
+  }\r
+  else /* OUT endpoint */\r
+  {\r
+    /* Program the transfer size and packet count as follows:\r
+    * pktcnt = N\r
+    * xfersize = N * maxpacket\r
+    */\r
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r
+\r
+    if (ep->xfer_len == 0U)\r
+    {\r
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
+    }\r
+    else\r
+    {\r
+      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);\r
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);\r
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);\r
+    }\r
+\r
+    if (ep->type == EP_TYPE_ISOC)\r
+    {\r
+      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r
+      {\r
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r
+      }\r
+      else\r
+      {\r
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r
+      }\r
+    }\r
+    /* EP enable */\r
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+\r
+  /* IN endpoint */\r
+  if (ep->is_in == 1U)\r
+  {\r
+    /* Zero Length Packet? */\r
+    if (ep->xfer_len == 0U)\r
+    {\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+    }\r
+    else\r
+    {\r
+      /* Program the transfer size and packet count\r
+      * as follows: xfersize = N * maxpacket +\r
+      * short_packet pktcnt = N + (short_packet\r
+      * exist ? 1 : 0)\r
+      */\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+\r
+      if (ep->xfer_len > ep->maxpacket)\r
+      {\r
+        ep->xfer_len = ep->maxpacket;\r
+      }\r
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r
+    }\r
+\r
+    /* EP enable, IN data in FIFO */\r
+    USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
+\r
+    /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+    if (ep->xfer_len > 0U)\r
+    {\r
+      USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\r
+    }\r
+  }\r
+  else /* OUT endpoint */\r
+  {\r
+    /* Program the transfer size and packet count as follows:\r
+    * pktcnt = N\r
+    * xfersize = N * maxpacket\r
+    */\r
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r
+\r
+    if (ep->xfer_len > 0U)\r
+    {\r
+      ep->xfer_len = ep->maxpacket;\r
+    }\r
+\r
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));\r
+\r
+    /* EP enable */\r
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated\r
+  *         with the EP/channel\r
+  * @param  USBx  Selected device\r
+  * @param  src   pointer to source buffer\r
+  * @param  ch_ep_num  endpoint or host channel number\r
+  * @param  len  Number of bytes to write\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t *pSrc = (uint32_t *)src;\r
+  uint32_t count32b, i;\r
+\r
+  count32b = ((uint32_t)len + 3U) / 4U;\r
+  for (i = 0U; i < count32b; i++)\r
+  {\r
+    USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);\r
+    pSrc++;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadPacket : read a packet from the RX FIFO\r
+  * @param  USBx  Selected device\r
+  * @param  dest  source pointer\r
+  * @param  len  Number of bytes to read\r
+  * @retval pointer to destination buffer\r
+  */\r
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t *pDest = (uint32_t *)dest;\r
+  uint32_t i;\r
+  uint32_t count32b = ((uint32_t)len + 3U) / 4U;\r
+\r
+  for (i = 0U; i < count32b; i++)\r
+  {\r
+    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));\r
+    pDest++;\r
+  }\r
+\r
+  return ((void *)pDest);\r
+}\r
+\r
+/**\r
+  * @brief  USB_EPSetStall : set a stall condition over an EP\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+\r
+  if (ep->is_in == 1U)\r
+  {\r
+    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))\r
+    {\r
+      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);\r
+    }\r
+    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r
+  }\r
+  else\r
+  {\r
+    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))\r
+    {\r
+      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);\r
+    }\r
+    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP\r
+  * @param  USBx  Selected device\r
+  * @param  ep pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t epnum = (uint32_t)ep->num;\r
+\r
+  if (ep->is_in == 1U)\r
+  {\r
+    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r
+    {\r
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+    }\r
+  }\r
+  else\r
+  {\r
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r
+    {\r
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+    }\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_StopDevice : Stop the usb device mode\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  HAL_StatusTypeDef ret;\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t i;\r
+\r
+  /* Clear Pending interrupt */\r
+  for (i = 0U; i < 15U; i++)\r
+  {\r
+    USBx_INEP(i)->DIEPINT = 0xFB7FU;\r
+    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r
+  }\r
+\r
+  /* Clear interrupt masks */\r
+  USBx_DEVICE->DIEPMSK  = 0U;\r
+  USBx_DEVICE->DOEPMSK  = 0U;\r
+  USBx_DEVICE->DAINTMSK = 0U;\r
+\r
+  /* Flush the FIFO */\r
+  ret = USB_FlushRxFifo(USBx);\r
+  if (ret != HAL_OK)\r
+  {\r
+    return ret;\r
+  }\r
+\r
+  ret = USB_FlushTxFifo(USBx,  0x10U);\r
+  if (ret != HAL_OK)\r
+  {\r
+    return ret;\r
+  }\r
+\r
+  return ret;\r
+}\r
+\r
+/**\r
+  * @brief  USB_SetDevAddress : Stop the usb device mode\r
+  * @param  USBx  Selected device\r
+  * @param  address  new device address to be assigned\r
+  *          This parameter can be a value from 0 to 255\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);\r
+  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;\r
+  HAL_Delay(3U);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\r
+  HAL_Delay(3U);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t tmpreg;\r
+\r
+  tmpreg = USBx->GINTSTS;\r
+  tmpreg &= USBx->GINTMSK;\r
+\r
+  return tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t tmpreg;\r
+\r
+  tmpreg  = USBx_DEVICE->DAINT;\r
+  tmpreg &= USBx_DEVICE->DAINTMSK;\r
+\r
+  return ((tmpreg & 0xffff0000U) >> 16);\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t tmpreg;\r
+\r
+  tmpreg  = USBx_DEVICE->DAINT;\r
+  tmpreg &= USBx_DEVICE->DAINTMSK;\r
+\r
+  return ((tmpreg & 0xFFFFU));\r
+}\r
+\r
+/**\r
+  * @brief  Returns Device OUT EP Interrupt register\r
+  * @param  USBx  Selected device\r
+  * @param  epnum  endpoint number\r
+  *          This parameter can be a value from 0 to 15\r
+  * @retval Device OUT EP Interrupt register\r
+  */\r
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t tmpreg;\r
+\r
+  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;\r
+  tmpreg &= USBx_DEVICE->DOEPMSK;\r
+\r
+  return tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Returns Device IN EP Interrupt register\r
+  * @param  USBx  Selected device\r
+  * @param  epnum  endpoint number\r
+  *          This parameter can be a value from 0 to 15\r
+  * @retval Device IN EP Interrupt register\r
+  */\r
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t tmpreg, msk, emp;\r
+\r
+  msk = USBx_DEVICE->DIEPMSK;\r
+  emp = USBx_DEVICE->DIEPEMPMSK;\r
+  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;\r
+  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;\r
+\r
+  return tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ClearInterrupts: clear a USB interrupt\r
+  * @param  USBx  Selected device\r
+  * @param  interrupt  interrupt flag\r
+  * @retval None\r
+  */\r
+void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r
+{\r
+  USBx->GINTSTS |= interrupt;\r
+}\r
+\r
+/**\r
+  * @brief  Returns USB core mode\r
+  * @param  USBx  Selected device\r
+  * @retval return core mode : Host or Device\r
+  *          This parameter can be one of these values:\r
+  *           0 : Host\r
+  *           1 : Device\r
+  */\r
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  return ((USBx->GINTSTS) & 0x1U);\r
+}\r
+\r
+/**\r
+  * @brief  Activate EP0 for Setup transactions\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  /* Set the MPS of the IN EP based on the enumeration speed */\r
+  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r
+\r
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+  {\r
+    USBx_INEP(0U)->DIEPCTL |= 3U;\r
+  }\r
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Prepare the EP0 to start the first control setup\r
+  * @param  USBx  Selected device\r
+  * @param  psetup  pointer to setup packet\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)\r
+{\r
+  UNUSED(psetup);\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\r
+\r
+  if (gSNPSiD > USB_OTG_CORE_ID_300A)\r
+  {\r
+    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
+    {\r
+      return HAL_OK;\r
+    }\r
+  }\r
+\r
+  USBx_OUTEP(0U)->DOEPTSIZ = 0U;\r
+  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
+  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);\r
+  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Reset the USB Core (needed after USB clock settings change)\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t count = 0U;\r
+\r
+  /* Wait for AHB master IDLE state. */\r
+  do\r
+  {\r
+    if (++count > 200000U)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);\r
+\r
+  /* Core Soft Reset */\r
+  count = 0U;\r
+  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r
+\r
+  do\r
+  {\r
+    if (++count > 200000U)\r
+    {\r
+      return HAL_TIMEOUT;\r
+    }\r
+  }\r
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers\r
+  *         for Host mode\r
+  * @param  USBx  Selected device\r
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\r
+  *         the configuration information for the specified USBx peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t i;\r
+\r
+  /* Restart the Phy Clock */\r
+  USBx_PCGCCTL = 0U;\r
+\r
+  /* Disable VBUS sensing */\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);\r
+\r
+  /* Disable Battery chargin detector */\r
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);\r
+\r
+  /* Set default Max speed support */\r
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);\r
+\r
+  /* Make sure the FIFOs are flushed. */\r
+  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */\r
+  (void)USB_FlushRxFifo(USBx);\r
+\r
+  /* Clear all pending HC Interrupts */\r
+  for (i = 0U; i < cfg.Host_channels; i++)\r
+  {\r
+    USBx_HC(i)->HCINT = 0xFFFFFFFFU;\r
+    USBx_HC(i)->HCINTMSK = 0U;\r
+  }\r
+\r
+  /* Enable VBUS driving */\r
+  (void)USB_DriveVbus(USBx, 1U);\r
+\r
+  HAL_Delay(200U);\r
+\r
+  /* Disable all interrupts. */\r
+  USBx->GINTMSK = 0U;\r
+\r
+  /* Clear any pending interrupts */\r
+  USBx->GINTSTS = 0xFFFFFFFFU;\r
+\r
+  /* set Rx FIFO size */\r
+  USBx->GRXFSIZ  = 0x80U;\r
+  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);\r
+  USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);\r
+  /* Enable the common interrupts */\r
+  USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r
+\r
+  /* Enable interrupts matching to the Host mode ONLY */\r
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \\r
+                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \\r
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the\r
+  *         HCFG register on the PHY type and set the right frame interval\r
+  * @param  USBx  Selected device\r
+  * @param  freq  clock frequency\r
+  *          This parameter can be one of these values:\r
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock\r
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r
+  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;\r
+\r
+  if (freq == HCFG_48_MHZ)\r
+  {\r
+    USBx_HOST->HFIR = 48000U;\r
+  }\r
+  else if (freq == HCFG_6_MHZ)\r
+  {\r
+    USBx_HOST->HFIR = 6000U;\r
+  }\r
+  else\r
+  {\r
+    /* ... */\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+* @brief  USB_OTG_ResetPort : Reset Host Port\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  * @note (1)The application must wait at least 10 ms\r
+  *   before clearing the reset bit.\r
+  */\r
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  __IO uint32_t hprt0 = 0U;\r
+\r
+  hprt0 = USBx_HPRT0;\r
+\r
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r
+\r
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);\r
+  HAL_Delay(100U);                                 /* See Note #1 */\r
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);\r
+  HAL_Delay(10U);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DriveVbus : activate or de-activate vbus\r
+  * @param  state  VBUS state\r
+  *          This parameter can be one of these values:\r
+  *           0 : VBUS Active\r
+  *           1 : VBUS Inactive\r
+  * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  __IO uint32_t hprt0 = 0U;\r
+\r
+  hprt0 = USBx_HPRT0;\r
+\r
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r
+\r
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))\r
+  {\r
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);\r
+  }\r
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))\r
+  {\r
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);\r
+  }\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Return Host Core speed\r
+  * @param  USBx  Selected device\r
+  * @retval speed : Host speed\r
+  *          This parameter can be one of these values:\r
+  *            @arg HCD_SPEED_FULL: Full speed mode\r
+  *            @arg HCD_SPEED_LOW: Low speed mode\r
+  */\r
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  __IO uint32_t hprt0 = 0U;\r
+\r
+  hprt0 = USBx_HPRT0;\r
+  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r
+}\r
+\r
+/**\r
+  * @brief  Return Host Current Frame number\r
+  * @param  USBx  Selected device\r
+  * @retval current frame number\r
+*/\r
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r
+}\r
+\r
+/**\r
+  * @brief  Initialize a host channel\r
+  * @param  USBx  Selected device\r
+  * @param  ch_num  Channel number\r
+  *         This parameter can be a value from 1 to 15\r
+  * @param  epnum  Endpoint number\r
+  *          This parameter can be a value from 1 to 15\r
+  * @param  dev_address  Current device address\r
+  *          This parameter can be a value from 0 to 255\r
+  * @param  speed  Current device speed\r
+  *          This parameter can be one of these values:\r
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r
+  * @param  ep_type  Endpoint Type\r
+  *          This parameter can be one of these values:\r
+  *            @arg EP_TYPE_CTRL: Control type\r
+  *            @arg EP_TYPE_ISOC: Isochronous type\r
+  *            @arg EP_TYPE_BULK: Bulk type\r
+  *            @arg EP_TYPE_INTR: Interrupt type\r
+  * @param  mps  Max Packet Size\r
+  *          This parameter can be a value from 0 to32K\r
+  * @retval HAL state\r
+  */\r
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,\r
+                              uint8_t ch_num,\r
+                              uint8_t epnum,\r
+                              uint8_t dev_address,\r
+                              uint8_t speed,\r
+                              uint8_t ep_type,\r
+                              uint16_t mps)\r
+{\r
+  HAL_StatusTypeDef ret = HAL_OK;\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t HCcharEpDir, HCcharLowSpeed;\r
+\r
+  /* Clear old interrupt conditions for this host channel. */\r
+  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;\r
+\r
+  /* Enable channel interrupts required for this transfer. */\r
+  switch (ep_type)\r
+  {\r
+    case EP_TYPE_CTRL:\r
+    case EP_TYPE_BULK:\r
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r
+                                            USB_OTG_HCINTMSK_STALLM |\r
+                                            USB_OTG_HCINTMSK_TXERRM |\r
+                                            USB_OTG_HCINTMSK_DTERRM |\r
+                                            USB_OTG_HCINTMSK_AHBERR |\r
+                                            USB_OTG_HCINTMSK_NAKM;\r
+\r
+      if ((epnum & 0x80U) == 0x80U)\r
+      {\r
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+      }\r
+      break;\r
+\r
+    case EP_TYPE_INTR:\r
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r
+                                            USB_OTG_HCINTMSK_STALLM |\r
+                                            USB_OTG_HCINTMSK_TXERRM |\r
+                                            USB_OTG_HCINTMSK_DTERRM |\r
+                                            USB_OTG_HCINTMSK_NAKM   |\r
+                                            USB_OTG_HCINTMSK_AHBERR |\r
+                                            USB_OTG_HCINTMSK_FRMORM;\r
+\r
+      if ((epnum & 0x80U) == 0x80U)\r
+      {\r
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+      }\r
+\r
+      break;\r
+\r
+    case EP_TYPE_ISOC:\r
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r
+                                            USB_OTG_HCINTMSK_ACKM   |\r
+                                            USB_OTG_HCINTMSK_AHBERR |\r
+                                            USB_OTG_HCINTMSK_FRMORM;\r
+\r
+      if ((epnum & 0x80U) == 0x80U)\r
+      {\r
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);\r
+      }\r
+      break;\r
+\r
+    default:\r
+      ret = HAL_ERROR;\r
+      break;\r
+  }\r
+\r
+  /* Enable the top level host channel interrupt. */\r
+  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);\r
+\r
+  /* Make sure host channel interrupts are enabled. */\r
+  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r
+\r
+  /* Program the HCCHAR register */\r
+  if ((epnum & 0x80U) == 0x80U)\r
+  {\r
+    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;\r
+  }\r
+  else\r
+  {\r
+    HCcharEpDir = 0U;\r
+  }\r
+\r
+  if (speed == HPRT0_PRTSPD_LOW_SPEED)\r
+  {\r
+    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;\r
+  }\r
+  else\r
+  {\r
+    HCcharLowSpeed = 0U;\r
+  }\r
+\r
+  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |\r
+                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |\r
+                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |\r
+                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;\r
+\r
+  if (ep_type == EP_TYPE_INTR)\r
+  {\r
+    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r
+  }\r
+\r
+  return ret;\r
+}\r
+\r
+/**\r
+  * @brief  Start a transfer over a host channel\r
+  * @param  USBx  Selected device\r
+  * @param  hc  pointer to host channel structure\r
+  * @retval HAL state\r
+  */\r
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t ch_num = (uint32_t)hc->ch_num;\r
+  static __IO uint32_t tmpreg = 0U;\r
+  uint8_t  is_oddframe;\r
+  uint16_t len_words;\r
+  uint16_t num_packets;\r
+  uint16_t max_hc_pkt_count = 256U;\r
+\r
+  /* Compute the expected number of packets associated to the transfer */\r
+  if (hc->xfer_len > 0U)\r
+  {\r
+    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);\r
+\r
+    if (num_packets > max_hc_pkt_count)\r
+    {\r
+      num_packets = max_hc_pkt_count;\r
+      hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    num_packets = 1U;\r
+  }\r
+  if (hc->ep_is_in != 0U)\r
+  {\r
+    hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r
+  }\r
+\r
+  /* Initialize the HCTSIZn register */\r
+  USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |\r
+                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r
+                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);\r
+\r
+  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;\r
+  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r
+  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;\r
+\r
+  /* Set host channel enable */\r
+  tmpreg = USBx_HC(ch_num)->HCCHAR;\r
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+\r
+  /* make sure to set the correct ep direction */\r
+  if (hc->ep_is_in != 0U)\r
+  {\r
+    tmpreg |= USB_OTG_HCCHAR_EPDIR;\r
+  }\r
+  else\r
+  {\r
+    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;\r
+  }\r
+  tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+  USBx_HC(ch_num)->HCCHAR = tmpreg;\r
+\r
+    if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))\r
+    {\r
+      switch (hc->ep_type)\r
+      {\r
+        /* Non periodic transfer */\r
+        case EP_TYPE_CTRL:\r
+        case EP_TYPE_BULK:\r
+\r
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r
+\r
+          /* check if there is enough space in FIFO space */\r
+          if (len_words > (USBx->HNPTXSTS & 0xFFFFU))\r
+          {\r
+            /* need to process data in nptxfempty interrupt */\r
+            USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r
+          }\r
+          break;\r
+\r
+        /* Periodic transfer */\r
+        case EP_TYPE_INTR:\r
+        case EP_TYPE_ISOC:\r
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r
+          /* check if there is enough space in FIFO space */\r
+          if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */\r
+          {\r
+            /* need to process data in ptxfempty interrupt */\r
+            USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;\r
+          }\r
+          break;\r
+\r
+        default:\r
+          break;\r
+      }\r
+\r
+      /* Write packet into the Tx FIFO. */\r
+      (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len);\r
+    }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Read all host channel interrupts status\r
+  * @param  USBx  Selected device\r
+  * @retval HAL state\r
+  */\r
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  return ((USBx_HOST->HAINT) & 0xFFFFU);\r
+}\r
+\r
+/**\r
+  * @brief  Halt a host channel\r
+  * @param  USBx  Selected device\r
+  * @param  hc_num  Host Channel number\r
+  *         This parameter can be a value from 1 to 15\r
+  * @retval HAL state\r
+  */\r
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t hcnum = (uint32_t)hc_num;\r
+  uint32_t count = 0U;\r
+  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;\r
+\r
+  /* Check for space in the request queue to issue the halt. */\r
+  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))\r
+  {\r
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+\r
+    if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)\r
+    {\r
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+      do\r
+      {\r
+        if (++count > 1000U)\r
+        {\r
+          break;\r
+        }\r
+      }\r
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+    }\r
+    else\r
+    {\r
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+\r
+    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)\r
+    {\r
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+      do\r
+      {\r
+        if (++count > 1000U)\r
+        {\r
+          break;\r
+        }\r
+      }\r
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+    }\r
+    else\r
+    {\r
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+    }\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Initiate Do Ping protocol\r
+  * @param  USBx  Selected device\r
+  * @param  hc_num  Host Channel number\r
+  *         This parameter can be a value from 1 to 15\r
+  * @retval HAL state\r
+  */\r
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t chnum = (uint32_t)ch_num;\r
+  uint32_t num_packets = 1U;\r
+  uint32_t tmpreg;\r
+\r
+  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r
+                           USB_OTG_HCTSIZ_DOPING;\r
+\r
+  /* Set host channel enable */\r
+  tmpreg = USBx_HC(chnum)->HCCHAR;\r
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+  tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+  USBx_HC(chnum)->HCCHAR = tmpreg;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Stop Host Core\r
+  * @param  USBx  Selected device\r
+  * @retval HAL state\r
+  */\r
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+  uint32_t count = 0U;\r
+  uint32_t value;\r
+  uint32_t i;\r
+\r
+\r
+  (void)USB_DisableGlobalInt(USBx);\r
+\r
+  /* Flush FIFO */\r
+  (void)USB_FlushTxFifo(USBx, 0x10U);\r
+  (void)USB_FlushRxFifo(USBx);\r
+\r
+  /* Flush out any leftover queued requests. */\r
+  for (i = 0U; i <= 15U; i++)\r
+  {\r
+    value = USBx_HC(i)->HCCHAR;\r
+    value |=  USB_OTG_HCCHAR_CHDIS;\r
+    value &= ~USB_OTG_HCCHAR_CHENA;\r
+    value &= ~USB_OTG_HCCHAR_EPDIR;\r
+    USBx_HC(i)->HCCHAR = value;\r
+  }\r
+\r
+  /* Halt all channels to put them into a known state. */\r
+  for (i = 0U; i <= 15U; i++)\r
+  {\r
+    value = USBx_HC(i)->HCCHAR;\r
+    value |= USB_OTG_HCCHAR_CHDIS;\r
+    value |= USB_OTG_HCCHAR_CHENA;\r
+    value &= ~USB_OTG_HCCHAR_EPDIR;\r
+    USBx_HC(i)->HCCHAR = value;\r
+\r
+    do\r
+    {\r
+      if (++count > 1000U)\r
+      {\r
+        break;\r
+      }\r
+    }\r
+    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+  }\r
+\r
+  /* Clear any pending Host interrupts */\r
+  USBx_HOST->HAINT = 0xFFFFFFFFU;\r
+  USBx->GINTSTS = 0xFFFFFFFFU;\r
+  (void)USB_EnableGlobalInt(USBx);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling\r
+  * @param  USBx Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
+  {\r
+    /* active Remote wakeup signalling */\r
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling\r
+  * @param  USBx Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+  uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+  /* active Remote wakeup signalling */\r
+  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\r
+\r
+  return HAL_OK;\r
+}\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+/**\r
+  * @brief  Initializes the USB Core\r
+  * @param  USBx: USB Instance\r
+  * @param  cfg : pointer to a USB_CfgTypeDef structure that contains\r
+  *         the configuration information for the specified USBx peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(cfg);\r
+\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_EnableGlobalInt\r
+  *         Enables the controller's Global Int in the AHB Config reg\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)\r
+{\r
+  uint16_t winterruptmask;\r
+\r
+  /* Set winterruptmask variable */\r
+  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |\r
+                   USB_CNTR_SUSPM | USB_CNTR_ERRM |\r
+                   USB_CNTR_SOFM | USB_CNTR_ESOFM |\r
+                   USB_CNTR_RESETM | USB_CNTR_L1REQM;\r
+\r
+  /* Set interrupt mask */\r
+  USBx->CNTR |= winterruptmask;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DisableGlobalInt\r
+  *         Disable the controller's Global Int in the AHB Config reg\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)\r
+{\r
+  uint16_t winterruptmask;\r
+\r
+  /* Set winterruptmask variable */\r
+  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |\r
+                   USB_CNTR_SUSPM | USB_CNTR_ERRM |\r
+                   USB_CNTR_SOFM | USB_CNTR_ESOFM |\r
+                   USB_CNTR_RESETM | USB_CNTR_L1REQM;\r
+\r
+  /* Clear interrupt mask */\r
+  USBx->CNTR &= ~winterruptmask;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_SetCurrentMode : Set functional mode\r
+  * @param  USBx : Selected device\r
+  * @param  mode :  current core mode\r
+  *          This parameter can be one of the these values:\r
+  *            @arg USB_DEVICE_MODE: Peripheral mode mode\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(mode);\r
+\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DevInit : Initializes the USB controller registers\r
+  *         for device mode\r
+  * @param  USBx : Selected device\r
+  * @param  cfg  : pointer to a USB_CfgTypeDef structure that contains\r
+  *         the configuration information for the specified USBx peripheral.\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(cfg);\r
+\r
+  /* Init Device */\r
+  /*CNTR_FRES = 1*/\r
+  USBx->CNTR = USB_CNTR_FRES;\r
+\r
+  /*CNTR_FRES = 0*/\r
+  USBx->CNTR = 0;\r
+\r
+  /*Clear pending interrupts*/\r
+  USBx->ISTR = 0;\r
+\r
+  /*Set Btable Address*/\r
+  USBx->BTABLE = BTABLE_ADDRESS;\r
+\r
+  /* Enable USB Device Interrupt mask */\r
+  (void)USB_EnableGlobalInt(USBx);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_SetDevSpeed :Initializes the device speed\r
+  *         depending on the PHY type and the enumeration speed of the device.\r
+  * @param  USBx  Selected device\r
+  * @param  speed  device speed\r
+  * @retval  Hal status\r
+  */\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(speed);\r
+\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_FlushTxFifo : Flush a Tx FIFO\r
+  * @param  USBx : Selected device\r
+  * @param  num : FIFO number\r
+  *         This parameter can be a value from 1 to 15\r
+            15 means Flush all Tx FIFOs\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(num);\r
+\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_FlushRxFifo : Flush Rx FIFO\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  Activate and configure an endpoint\r
+  * @param  USBx : Selected device\r
+  * @param  ep: pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+  HAL_StatusTypeDef ret = HAL_OK;\r
+  uint16_t wEpRegVal;\r
+\r
+  wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;\r
+\r
+  /* initialize Endpoint */\r
+  switch (ep->type)\r
+  {\r
+    case EP_TYPE_CTRL:\r
+      wEpRegVal |= USB_EP_CONTROL;\r
+      break;\r
+\r
+    case EP_TYPE_BULK:\r
+      wEpRegVal |= USB_EP_BULK;\r
+      break;\r
+\r
+    case EP_TYPE_INTR:\r
+      wEpRegVal |= USB_EP_INTERRUPT;\r
+      break;\r
+\r
+    case EP_TYPE_ISOC:\r
+      wEpRegVal |= USB_EP_ISOCHRONOUS;\r
+      break;\r
+\r
+    default:\r
+      ret = HAL_ERROR;\r
+      break;\r
+  }\r
+\r
+  PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);\r
+\r
+  PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);\r
+\r
+  if (ep->doublebuffer == 0U)\r
+  {\r
+    if (ep->is_in != 0U)\r
+    {\r
+      /*Set the endpoint Transmit buffer address */\r
+      PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);\r
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+      if (ep->type != EP_TYPE_ISOC)\r
+      {\r
+        /* Configure NAK status for the Endpoint */\r
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
+      }\r
+      else\r
+      {\r
+        /* Configure TX Endpoint to disabled state */\r
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      /*Set the endpoint Receive buffer address */\r
+      PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);\r
+      /*Set the endpoint Receive buffer counter*/\r
+      PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);\r
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+      /* Configure VALID status for the Endpoint*/\r
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+    }\r
+  }\r
+  /*Double Buffer*/\r
+  else\r
+  {\r
+    /* Set the endpoint as double buffered */\r
+    PCD_SET_EP_DBUF(USBx, ep->num);\r
+    /* Set buffer address for double buffered mode */\r
+    PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);\r
+\r
+    if (ep->is_in == 0U)\r
+    {\r
+      /* Clear the data toggle bits for the endpoint IN/OUT */\r
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+      /* Reset value of the data toggle bits for the endpoint out */\r
+      PCD_TX_DTOG(USBx, ep->num);\r
+\r
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+    }\r
+    else\r
+    {\r
+      /* Clear the data toggle bits for the endpoint IN/OUT */\r
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+      PCD_RX_DTOG(USBx, ep->num);\r
+\r
+      if (ep->type != EP_TYPE_ISOC)\r
+      {\r
+        /* Configure NAK status for the Endpoint */\r
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
+      }\r
+      else\r
+      {\r
+        /* Configure TX Endpoint to disabled state */\r
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+      }\r
+\r
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+    }\r
+  }\r
+\r
+  return ret;\r
+}\r
+\r
+/**\r
+  * @brief  De-activate and de-initialize an endpoint\r
+  * @param  USBx : Selected device\r
+  * @param  ep: pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+  if (ep->doublebuffer == 0U)\r
+  {\r
+    if (ep->is_in != 0U)\r
+    {\r
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+      /* Configure DISABLE status for the Endpoint*/\r
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+    }\r
+    else\r
+    {\r
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+      /* Configure DISABLE status for the Endpoint*/\r
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+    }\r
+  }\r
+  /*Double Buffer*/\r
+  else\r
+  {\r
+    if (ep->is_in == 0U)\r
+    {\r
+      /* Clear the data toggle bits for the endpoint IN/OUT*/\r
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+      /* Reset value of the data toggle bits for the endpoint out*/\r
+      PCD_TX_DTOG(USBx, ep->num);\r
+\r
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+    }\r
+    else\r
+    {\r
+      /* Clear the data toggle bits for the endpoint IN/OUT*/\r
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+      PCD_RX_DTOG(USBx, ep->num);\r
+      /* Configure DISABLE status for the Endpoint*/\r
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+    }\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP\r
+  * @param  USBx : Selected device\r
+  * @param  ep: pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+  uint16_t pmabuffer;\r
+  uint32_t len;\r
+\r
+  /* IN endpoint */\r
+  if (ep->is_in == 1U)\r
+  {\r
+    /*Multi packet transfer*/\r
+    if (ep->xfer_len > ep->maxpacket)\r
+    {\r
+      len = ep->maxpacket;\r
+      ep->xfer_len -= len;\r
+    }\r
+    else\r
+    {\r
+      len = ep->xfer_len;\r
+      ep->xfer_len = 0U;\r
+    }\r
+\r
+    /* configure and validate Tx endpoint */\r
+    if (ep->doublebuffer == 0U)\r
+    {\r
+      USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);\r
+      PCD_SET_EP_TX_CNT(USBx, ep->num, len);\r
+    }\r
+    else\r
+    {\r
+      /* Write the data to the USB endpoint */\r
+      if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)\r
+      {\r
+        /* Set the Double buffer counter for pmabuffer1 */\r
+        PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);\r
+        pmabuffer = ep->pmaaddr1;\r
+      }\r
+      else\r
+      {\r
+        /* Set the Double buffer counter for pmabuffer0 */\r
+        PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);\r
+        pmabuffer = ep->pmaaddr0;\r
+      }\r
+      USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);\r
+      PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);\r
+    }\r
+\r
+    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);\r
+  }\r
+  else /* OUT endpoint */\r
+  {\r
+    /* Multi packet transfer*/\r
+    if (ep->xfer_len > ep->maxpacket)\r
+    {\r
+      len = ep->maxpacket;\r
+      ep->xfer_len -= len;\r
+    }\r
+    else\r
+    {\r
+      len = ep->xfer_len;\r
+      ep->xfer_len = 0U;\r
+    }\r
+\r
+    /* configure and validate Rx endpoint */\r
+    if (ep->doublebuffer == 0U)\r
+    {\r
+      /*Set RX buffer count*/\r
+      PCD_SET_EP_RX_CNT(USBx, ep->num, len);\r
+    }\r
+    else\r
+    {\r
+      /*Set the Double buffer counter*/\r
+      PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);\r
+    }\r
+\r
+    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated\r
+  *         with the EP/channel\r
+  * @param  USBx : Selected device\r
+  * @param  src :  pointer to source buffer\r
+  * @param  ch_ep_num : endpoint or host channel number\r
+  * @param  len : Number of bytes to write\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(src);\r
+  UNUSED(ch_ep_num);\r
+  UNUSED(len);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated\r
+  *         with the EP/channel\r
+  * @param  USBx : Selected device\r
+  * @param  dest : destination pointer\r
+  * @param  len : Number of bytes to read\r
+  * @retval pointer to destination buffer\r
+  */\r
+void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(dest);\r
+  UNUSED(len);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return ((void *)NULL);\r
+}\r
+\r
+/**\r
+  * @brief  USB_EPSetStall : set a stall condition over an EP\r
+  * @param  USBx : Selected device\r
+  * @param  ep: pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+  if (ep->is_in != 0U)\r
+  {\r
+    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);\r
+  }\r
+  else\r
+  {\r
+    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP\r
+  * @param  USBx : Selected device\r
+  * @param  ep: pointer to endpoint structure\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+  if (ep->doublebuffer == 0U)\r
+  {\r
+    if (ep->is_in != 0U)\r
+    {\r
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+      if (ep->type != EP_TYPE_ISOC)\r
+      {\r
+        /* Configure NAK status for the Endpoint */\r
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
+      }\r
+    }\r
+    else\r
+    {\r
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+\r
+      /* Configure VALID status for the Endpoint*/\r
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+    }\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_StopDevice : Stop the usb device mode\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)\r
+{\r
+  /* disable all interrupts and force USB reset */\r
+  USBx->CNTR = USB_CNTR_FRES;\r
+\r
+  /* clear interrupt status register */\r
+  USBx->ISTR = 0;\r
+\r
+  /* switch-off device */\r
+  USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_SetDevAddress : Stop the usb device mode\r
+  * @param  USBx : Selected device\r
+  * @param  address : new device address to be assigned\r
+  *          This parameter can be a value from 0 to 255\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef  USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)\r
+{\r
+  if (address == 0U)\r
+  {\r
+    /* set device address and enable function */\r
+    USBx->DADDR = USB_DADDR_EF;\r
+  }\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef  USB_DevConnect(USB_TypeDef *USBx)\r
+{\r
+  /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */\r
+  USBx->BCDR |= USB_BCDR_DPPU;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef  USB_DevDisconnect(USB_TypeDef *USBx)\r
+{\r
+  /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */\r
+  USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+uint32_t  USB_ReadInterrupts(USB_TypeDef *USBx)\r
+{\r
+  uint32_t tmpreg;\r
+\r
+  tmpreg = USBx->ISTR;\r
+  return tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return (0);\r
+}\r
+\r
+/**\r
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
+  * @param  USBx : Selected device\r
+  * @retval HAL status\r
+  */\r
+uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return (0);\r
+}\r
+\r
+/**\r
+  * @brief  Returns Device OUT EP Interrupt register\r
+  * @param  USBx : Selected device\r
+  * @param  epnum : endpoint number\r
+  *          This parameter can be a value from 0 to 15\r
+  * @retval Device OUT EP Interrupt register\r
+  */\r
+uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(epnum);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return (0);\r
+}\r
+\r
+/**\r
+  * @brief  Returns Device IN EP Interrupt register\r
+  * @param  USBx : Selected device\r
+  * @param  epnum : endpoint number\r
+  *          This parameter can be a value from 0 to 15\r
+  * @retval Device IN EP Interrupt register\r
+  */\r
+uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(epnum);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return (0);\r
+}\r
+\r
+/**\r
+  * @brief  USB_ClearInterrupts: clear a USB interrupt\r
+  * @param  USBx  Selected device\r
+  * @param  interrupt  interrupt flag\r
+  * @retval None\r
+  */\r
+void  USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(interrupt);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+}\r
+\r
+/**\r
+  * @brief  Prepare the EP0 to start the first control setup\r
+  * @param  USBx  Selected device\r
+  * @param  psetup  pointer to setup packet\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)\r
+{\r
+  /* Prevent unused argument(s) compilation warning */\r
+  UNUSED(USBx);\r
+  UNUSED(psetup);\r
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+              only by USB OTG FS peripheral.\r
+            - This function is added to ensure compatibility across platforms.\r
+   */\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)\r
+{\r
+  USBx->CNTR |= USB_CNTR_RESUME;\r
+\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief  USB_DeActivateRemoteWakeup : de-active remote wakeup signalling\r
+  * @param  USBx  Selected device\r
+  * @retval HAL status\r
+  */\r
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)\r
+{\r
+  USBx->CNTR &= ~(USB_CNTR_RESUME);\r
+  return HAL_OK;\r
+}\r
+\r
+/**\r
+  * @brief Copy a buffer from user memory area to packet memory area (PMA)\r
+  * @param   USBx USB peripheral instance register address.\r
+  * @param   pbUsrBuf pointer to user memory area.\r
+  * @param   wPMABufAddr address into PMA.\r
+  * @param   wNBytes: no. of bytes to be copied.\r
+  * @retval None\r
+  */\r
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)\r
+{\r
+  uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;\r
+  uint32_t BaseAddr = (uint32_t)USBx;\r
+  uint32_t i, temp1, temp2;\r
+  uint16_t *pdwVal;\r
+  uint8_t *pBuf = pbUsrBuf;\r
+\r
+  pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));\r
+\r
+  for (i = n; i != 0U; i--)\r
+  {\r
+    temp1 = (uint16_t) * pBuf;\r
+    pBuf++;\r
+    temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8));\r
+    *pdwVal = (uint16_t)temp2;\r
+    pdwVal++;\r
+\r
+#if PMA_ACCESS > 1U\r
+    pdwVal++;\r
+#endif\r
+\r
+    pBuf++;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief Copy a buffer from user memory area to packet memory area (PMA)\r
+  * @param   USBx: USB peripheral instance register address.\r
+  * @param   pbUsrBuf pointer to user memory area.\r
+  * @param   wPMABufAddr address into PMA.\r
+  * @param   wNBytes: no. of bytes to be copied.\r
+  * @retval None\r
+  */\r
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)\r
+{\r
+  uint32_t n = (uint32_t)wNBytes >> 1;\r
+  uint32_t BaseAddr = (uint32_t)USBx;\r
+  uint32_t i, temp;\r
+  uint16_t *pdwVal;\r
+  uint8_t *pBuf = pbUsrBuf;\r
+\r
+  pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));\r
+\r
+  for (i = n; i != 0U; i--)\r
+  {\r
+    temp = *pdwVal;\r
+    pdwVal++;\r
+    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);\r
+    pBuf++;\r
+    *pBuf = (uint8_t)((temp >> 8) & 0xFFU);\r
+    pBuf++;\r
+\r
+#if PMA_ACCESS > 1U\r
+    pdwVal++;\r
+#endif\r
+  }\r
+\r
+  if ((wNBytes % 2U) != 0U)\r
+  {\r
+    temp = *pdwVal;\r
+    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);\r
+  }\r
+}\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+#endif /* defined (USB) || defined (USB_OTG_FS) */\r
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Config/FreeRTOSConfig.h
deleted file mode 100644 (file)
index c8f6553..0000000
+++ /dev/null
@@ -1,164 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
- *\r
- * See http://www.freertos.org/a00110.html\r
- *----------------------------------------------------------*/\r
-\r
-/* The MPU version of port.c includes and excludes functions depending on the\r
-settings within this file.  Therefore, to ensure all the functions in port.c\r
-build, this configuration file has all options turned on. */\r
-\r
-#define configUSE_PREEMPTION                                   1\r
-#define configTICK_RATE_HZ                                             ( 1000 )\r
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION        1\r
-#define configUSE_QUEUE_SETS                                   1\r
-#define configUSE_IDLE_HOOK                                            0\r
-#define configUSE_TICK_HOOK                                            0\r
-#define configCPU_CLOCK_HZ                                             48000000\r
-#define configMAX_PRIORITIES                                   ( 5 )\r
-#define configMINIMAL_STACK_SIZE                               ( ( unsigned short ) 256 )\r
-#define configTOTAL_HEAP_SIZE                                  ( ( size_t ) ( 16 * 1024 ) )\r
-#define configMAX_TASK_NAME_LEN                                        ( 10 )\r
-#define configUSE_TRACE_FACILITY                               1\r
-#define configUSE_16_BIT_TICKS                                 0\r
-#define configIDLE_SHOULD_YIELD                                        1\r
-#define configUSE_MUTEXES                                              1\r
-#define configQUEUE_REGISTRY_SIZE                              5\r
-#define configCHECK_FOR_STACK_OVERFLOW                 2\r
-#define configUSE_RECURSIVE_MUTEXES                            1\r
-#define configUSE_MALLOC_FAILED_HOOK                   1\r
-#define configUSE_APPLICATION_TASK_TAG                 1\r
-#define configUSE_COUNTING_SEMAPHORES                  1\r
-#define configUSE_TICKLESS_IDLE                                        0\r
-#define configNUM_THREAD_LOCAL_STORAGE_POINTERS        2\r
-\r
-/* This demo shows the MPU being used without any dynamic memory allocation. */\r
-#define configSUPPORT_STATIC_ALLOCATION                        1\r
-#define configSUPPORT_DYNAMIC_ALLOCATION               1\r
-\r
-/* Run time stats gathering definitions. */\r
-#define configGENERATE_RUN_TIME_STATS                  1\r
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
-#define portGET_RUN_TIME_COUNTER_VALUE()               0\r
-\r
-/* This demo makes use of one or more example stats formatting functions.  These\r
-format the raw data provided by the uxTaskGetSystemState() function in to human\r
-readable ASCII form.  See the notes in the implementation of vTaskList() within\r
-FreeRTOS/Source/tasks.c for limitations. */\r
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0\r
-\r
-/* Co-routine definitions. */\r
-#define configUSE_CO_ROUTINES                                  0\r
-#define configMAX_CO_ROUTINE_PRIORITIES                ( 2 )\r
-\r
-/* Software timer definitions. */\r
-#define configUSE_TIMERS                                               1\r
-#define configTIMER_TASK_PRIORITY                              ( 2 )\r
-#define configTIMER_QUEUE_LENGTH                               5\r
-#define configTIMER_TASK_STACK_DEPTH                   ( configMINIMAL_STACK_SIZE )\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-#define INCLUDE_vTaskPrioritySet                               1\r
-#define INCLUDE_uxTaskPriorityGet                              1\r
-#define INCLUDE_vTaskDelete                                            1\r
-#define INCLUDE_vTaskCleanUpResources                  1\r
-#define INCLUDE_vTaskSuspend                                   1\r
-#define INCLUDE_vTaskDelayUntil                                        1\r
-#define INCLUDE_vTaskDelay                                             1\r
-#define INCLUDE_eTaskGetState                                  1\r
-#define INCLUDE_xTimerPendFunctionCall                 0\r
-#define INCLUDE_xSemaphoreGetMutexHolder               1\r
-#define INCLUDE_xTaskGetHandle                                 1\r
-#define INCLUDE_xTaskGetCurrentTaskHandle              1\r
-#define INCLUDE_xTaskGetIdleTaskHandle                 1\r
-#define INCLUDE_xTaskAbortDelay                                        1\r
-#define INCLUDE_xTaskGetSchedulerState                 1\r
-#define INCLUDE_xTaskGetIdleTaskHandle                 1\r
-#define INCLUDE_uxTaskGetStackHighWaterMark    1\r
-\r
-/* Cortex-M specific definitions. */\r
-#ifdef __NVIC_PRIO_BITS\r
-       /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
-       #define configPRIO_BITS                                         __NVIC_PRIO_BITS\r
-#else\r
-       #define configPRIO_BITS                                         4       /* 15 priority levels */\r
-#endif\r
-\r
-/* The lowest interrupt priority that can be used in a call to a "set priority"\r
-function. */\r
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY                        0xf\r
-\r
-/* The highest interrupt priority that can be used by any interrupt service\r
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\r
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY   5\r
-\r
-/* Interrupt priorities used by the kernel port layer itself.  These are generic\r
-to all Cortex-M ports, and do not rely on any particular library functions. */\r
-#define configKERNEL_INTERRUPT_PRIORITY                                        ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY                   ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
-\r
-\r
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
-standard names. */\r
-#define xPortPendSVHandler                     PendSV_Handler\r
-#define vPortSVCHandler                        SVC_Handler\r
-#define xPortSysTickHandler            SysTick_Handler\r
-\r
-/* Normal assert() semantics without relying on the provision of an assert.h\r
-header file. */\r
-#define configASSERT( x )                      if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); }\r
-\r
-/* Ensure that system calls can only be made from kernel code. */\r
-#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY            1\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* FREERTOS_CONFIG_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.c
deleted file mode 100644 (file)
index 81d6f5f..0000000
+++ /dev/null
@@ -1,117 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* App includes. */\r
-#include "app_main.h"\r
-\r
-/* Demo includes. */\r
-#include "mpu_demo.h"\r
-\r
-void app_main( void )\r
-{\r
-       /* Start the MPU demo. */\r
-       vStartMPUDemo();\r
-\r
-       /* Start the scheduler. */\r
-       vTaskStartScheduler();\r
-\r
-       /* Should not get here. */\r
-       for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
-       /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this\r
-       function will automatically get called if a task overflows its stack. */\r
-       ( void ) pxTask;\r
-       ( void ) pcTaskName;\r
-       for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
-       /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will\r
-       be called automatically if a call to pvPortMalloc() fails.  pvPortMalloc()\r
-       is called automatically when a task, queue or semaphore is created. */\r
-       for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
-implementation of vApplicationGetIdleTaskMemory() to provide the memory that is\r
-used by the Idle task. */\r
-void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
-{\r
-/* If the buffers to be provided to the Idle task are declared inside this\r
-function then they must be declared static - otherwise they will be allocated on\r
-the stack and so not exists after this function exits. */\r
-static StaticTask_t xIdleTaskTCB;\r
-static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
-\r
-       /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
-       state will be stored. */\r
-       *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
-\r
-       /* Pass out the array that will be used as the Idle task's stack. */\r
-       *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
-\r
-       /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
-       Note that, as the array is necessarily of type StackType_t,\r
-       configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
-       *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
-application must provide an implementation of vApplicationGetTimerTaskMemory()\r
-to provide the memory that is used by the Timer service task. */\r
-void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\r
-{\r
-/* If the buffers to be provided to the Timer task are declared inside this\r
-function then they must be declared static - otherwise they will be allocated on\r
-the stack and so not exists after this function exits. */\r
-static StaticTask_t xTimerTaskTCB;\r
-static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
-\r
-       /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
-       task's state will be stored. */\r
-       *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
-\r
-       /* Pass out the array that will be used as the Timer task's stack. */\r
-       *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
-\r
-       /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
-       Note that, as the array is necessarily of type StackType_t,\r
-       configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
-       *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
-}\r
-/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.h
deleted file mode 100644 (file)
index 64210fc..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-#ifndef __APP_MAIN_H__\r
-#define __APP_MAIN_H__\r
-\r
-/**\r
- * @brief Main app entry point.\r
- */\r
-void app_main( void );\r
-\r
-#endif /* __APP_MAIN_H__ */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.c
deleted file mode 100644 (file)
index 039439a..0000000
+++ /dev/null
@@ -1,301 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/* FreeRTOS includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/** ARMv7 MPU Details:\r
- *\r
- * - ARMv7 MPU requires that the size of a MPU region is a power of 2.\r
- * - Smallest supported region size is 32 bytes.\r
- * - Start address of a region must be aligned to an integer multiple of the\r
- *   region size. For example, if the region size is 4 KB(0x1000), the starting\r
- *   address must be N x 0x1000, where N is an integer.\r
- */\r
-\r
-/**\r
- * @brief Size of the shared memory region.\r
- */\r
-#define SHARED_MEMORY_SIZE 32\r
-\r
-/**\r
- * @brief Memory region shared between two tasks.\r
- */\r
-static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) );\r
-\r
-/**\r
- * @brief Memory region used to track Memory Fault intentionally caused by the\r
- * RO Access task.\r
- *\r
- * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal\r
- * memory. Illegal memory access causes Memory Fault and the fault handler\r
- * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We\r
- * recover gracefully from an expected fault by jumping to the next instruction.\r
- *\r
- * @note We are declaring a region of 32 bytes even though we need only one.\r
- * The reason is that the smallest supported MPU region size is 32 bytes.\r
- */\r
-static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 };\r
-/*-----------------------------------------------------------*/\r
-\r
-/**\r
- * @brief Implements the task which has Read Only access to the memory region\r
- * ucSharedMemory.\r
- *\r
- * @param pvParameters[in] Parameters as passed during task creation.\r
- */\r
-static void prvROAccessTask( void * pvParameters );\r
-\r
-/**\r
- * @brief Implements the task which has Read Write access to the memory region\r
- * ucSharedMemory.\r
- *\r
- * @param pvParameters[in] Parameters as passed during task creation.\r
- */\r
-static void prvRWAccessTask( void * pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvROAccessTask( void * pvParameters )\r
-{\r
-uint8_t ucVal;\r
-\r
-       /* Unused parameters. */\r
-       ( void ) pvParameters;\r
-\r
-       for( ; ; )\r
-       {\r
-               /* This task has RO access to ucSharedMemory and therefore it can read\r
-                * it but cannot modify it. */\r
-               ucVal = ucSharedMemory[ 0 ];\r
-\r
-               /* Silent compiler warnings about unused variables. */\r
-               ( void ) ucVal;\r
-\r
-               /* Since this task has Read Only access to the ucSharedMemory region,\r
-                * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]\r
-                * to 1 to tell the Memory Fault Handler that this is an expected fault.\r
-                * The handler will recover from this fault gracefully by jumping to the\r
-                * next instruction. */\r
-               ucROTaskFaultTracker[ 0 ] = 1;\r
-\r
-               /* Illegal access to generate Memory Fault. */\r
-               ucSharedMemory[ 0 ] = 0;\r
-\r
-               /* Ensure that the above line did generate MemFault and the fault\r
-                * handler did clear the  ucROTaskFaultTracker[ 0 ]. */\r
-               configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
-\r
-               #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
-               {\r
-                       /* Generate an SVC to raise the privilege. Since privilege\r
-                        * escalation is only allowed from kernel code, this request must\r
-                        * get rejected and the task must remain unprivileged. As a result,\r
-                        * trying to write to ucSharedMemory will still result in Memory\r
-                        * Fault. */\r
-                       portRAISE_PRIVILEGE();\r
-\r
-                       /* Set ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault\r
-                        * Handler that this is an expected fault. The handler will then be\r
-                        * able to recover from this fault gracefully by jumping to the\r
-                        * next instruction.*/\r
-                       ucROTaskFaultTracker[ 0 ] = 1;\r
-\r
-                       /* The following must still result in Memory Fault since the task\r
-                        * is still running unprivileged. */\r
-                       ucSharedMemory[ 0 ] = 0;\r
-\r
-                       /* Ensure that the above line did generate MemFault and the fault\r
-                        * handler did clear the  ucROTaskFaultTracker[ 0 ]. */\r
-                       configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
-               }\r
-               #else\r
-               {\r
-                       /* Generate an SVC to raise the privilege. Since\r
-                        * configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not enabled, the\r
-                        * task will be able to escalate privilege. */\r
-                       portRAISE_PRIVILEGE();\r
-\r
-                       /* At this point, the task is running privileged. The following\r
-                        * access must not result in Memory Fault. If something goes\r
-                        * wrong and we do get a fault, the execution will stop in fault\r
-                        * handler as ucROTaskFaultTracker[ 0 ] is not set (i.e.\r
-                        * un-expected fault). */\r
-                       ucSharedMemory[ 0 ] = 0;\r
-\r
-                       /* Lower down the privilege. */\r
-                       portSWITCH_TO_USER_MODE();\r
-\r
-                       /* Now the task is running unprivileged and therefore an attempt to\r
-                        * write to ucSharedMemory will result in a Memory Fault. Set\r
-                        * ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault Handler\r
-                        * that this is an expected fault. The handler will then be able to\r
-                        * recover from this fault gracefully by jumping to the next\r
-                        * instruction.*/\r
-                       ucROTaskFaultTracker[ 0 ] = 1;\r
-\r
-                       /* The following must result in Memory Fault since the task is now\r
-                        * running unprivileged. */\r
-                       ucSharedMemory[ 0 ] = 0;\r
-\r
-                       /* Ensure that the above line did generate MemFault and the fault\r
-                        * handler did clear the  ucROTaskFaultTracker[ 0 ]. */\r
-                       configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
-               }\r
-               #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
-\r
-               /* Wait for a second. */\r
-               vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
-       }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvRWAccessTask( void * pvParameters )\r
-{\r
-       /* Unused parameters. */\r
-       ( void ) pvParameters;\r
-\r
-       for( ; ; )\r
-       {\r
-               /* This task has RW access to ucSharedMemory and therefore can write to\r
-                * it. */\r
-               ucSharedMemory[ 0 ] = 0;\r
-\r
-               /* Wait for a second. */\r
-               vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
-       }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vStartMPUDemo( void )\r
-{\r
-/**\r
- * Since stack of a task is protected using MPU, it must satisfy MPU\r
- * requirements as mentioned at the top of this file.\r
- */\r
-static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
-static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
-TaskParameters_t xROAccessTaskParameters =\r
-{\r
-       .pvTaskCode             = prvROAccessTask,\r
-       .pcName                 = "ROAccess",\r
-       .usStackDepth   = configMINIMAL_STACK_SIZE,\r
-       .pvParameters   = NULL,\r
-       .uxPriority             = tskIDLE_PRIORITY,\r
-       .puxStackBuffer = xROAccessTaskStack,\r
-       .xRegions               =       {\r
-                                                       { ucSharedMemory,                                       SHARED_MEMORY_SIZE,     portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER    },\r
-                                                       { ( void * ) ucROTaskFaultTracker,      SHARED_MEMORY_SIZE,     portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER                                                                },\r
-                                                       { 0,                                                            0,                                      0                                                                                                                                                                               },\r
-                                               }\r
-};\r
-TaskParameters_t xRWAccessTaskParameters =\r
-{\r
-       .pvTaskCode             = prvRWAccessTask,\r
-       .pcName                 = "RWAccess",\r
-       .usStackDepth   = configMINIMAL_STACK_SIZE,\r
-       .pvParameters   = NULL,\r
-       .uxPriority             = tskIDLE_PRIORITY,\r
-       .puxStackBuffer = xRWAccessTaskStack,\r
-       .xRegions               =       {\r
-                                                       { ucSharedMemory,       SHARED_MEMORY_SIZE,     portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER},\r
-                                                       { 0,                            0,                                      0                                                                                                               },\r
-                                                       { 0,                            0,                                      0                                                                                                               },\r
-                                               }\r
-};\r
-\r
-       /* Create an unprivileged task with RO access to ucSharedMemory. */\r
-       xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );\r
-\r
-       /* Create an unprivileged task with RW access to ucSharedMemory. */\r
-       xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )\r
-{\r
-uint32_t ulPC;\r
-uint16_t usOffendingInstruction;\r
-\r
-       /* Is this an expected fault? */\r
-       if( ucROTaskFaultTracker[ 0 ] == 1 )\r
-       {\r
-               /* Read program counter. */\r
-               ulPC = pulFaultStackAddress[ 6 ];\r
-\r
-               /* Read the offending instruction. */\r
-               usOffendingInstruction = *( uint16_t * )ulPC;\r
-\r
-               /* From ARM docs:\r
-                * If the value of bits[15:11] of the halfword being decoded is one of\r
-                * the following, the halfword is the first halfword of a 32-bit\r
-                * instruction:\r
-                * - 0b11101.\r
-                * - 0b11110.\r
-                * - 0b11111.\r
-                * Otherwise, the halfword is a 16-bit instruction.\r
-                */\r
-\r
-               /* Extract bits[15:11] of the offending instruction. */\r
-               usOffendingInstruction = usOffendingInstruction & 0xF800;\r
-               usOffendingInstruction = ( usOffendingInstruction >> 11 );\r
-\r
-               /* Determine if the offending instruction is a 32-bit instruction or\r
-                * a 16-bit instruction. */\r
-               if( usOffendingInstruction == 0x001F ||\r
-                       usOffendingInstruction == 0x001E ||\r
-                       usOffendingInstruction == 0x001D )\r
-               {\r
-                       /* Since the offending instruction is a 32-bit instruction,\r
-                        * increment the program counter by 4 to move to the next\r
-                        * instruction. */\r
-                       ulPC += 4;\r
-               }\r
-               else\r
-               {\r
-                       /* Since the offending instruction is a 16-bit instruction,\r
-                        * increment the program counter by 2 to move to the next\r
-                        * instruction. */\r
-                       ulPC += 2;\r
-               }\r
-\r
-               /* Save the new program counter on the stack. */\r
-               pulFaultStackAddress[ 6 ] = ulPC;\r
-\r
-               /* Mark the fault as handled. */\r
-               ucROTaskFaultTracker[ 0 ] = 0;\r
-       }\r
-       else\r
-       {\r
-               /* This is an unexpected fault - loop forever. */\r
-               for( ; ; )\r
-               {\r
-               }\r
-       }\r
-}\r
-/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.h
deleted file mode 100644 (file)
index e624027..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-#ifndef __MPU_DEMO_H__\r
-#define __MPU_DEMO_H__\r
-\r
-/**\r
- * @brief Creates all the tasks for MPU demo.\r
- *\r
- * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access\r
- * to a shared memory region while the other has Read Write access. The task\r
- * with Read Only access then tries to write to the shared memory which results\r
- * in a Memory fault. The fault handler examines that it is the fault generated\r
- * by the task with Read Only access and if so, it recovers from the fault\r
- * greacefully by moving the Program Counter to the next instruction to the one\r
- * which generated the fault. If any other memory access violation occurs, the\r
- * fault handler will get stuck in an inifinite loop.\r
- */\r
-void vStartMPUDemo( void );\r
-\r
-#endif /* __MPU_DEMO_H__ */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewd
deleted file mode 100644 (file)
index f9ec12d..0000000
+++ /dev/null
@@ -1,1419 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>\r
-<project>\r
-       <fileVersion>3</fileVersion>\r
-       <configuration>\r
-               <name>MPUDemo</name>\r
-               <toolchain>\r
-                       <name>ARM</name>\r
-               </toolchain>\r
-               <debug>1</debug>\r
-               <settings>\r
-                       <name>C-SPY</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>29</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>CInput</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CEndian</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CProcessor</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCVariant</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>MacOverride</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>MacFile</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>MemOverride</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>MemFile</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>RunToEnable</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RunToName</name>\r
-                                       <state>main</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CExtraOptionsCheck</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CExtraOptions</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CFpuProcessor</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDDFArgumentProducer</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDownloadSuppressDownload</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDownloadVerifyAll</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCProductVersion</name>\r
-                                       <state>7.10.3.6927</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDynDriverList</name>\r
-                                       <state>STLINK_ID</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCLastSavedByProductVersion</name>\r
-                                       <state>8.20.1.14181</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>UseFlashLoader</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CLowLevel</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCBE8Slave</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>MacFile2</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CDevice</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>FlashLoadersV3</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesSuppressCheck1</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesPath1</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesSuppressCheck2</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesPath2</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesSuppressCheck3</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesPath3</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OverrideDefFlashBoard</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesOffset1</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesOffset2</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesOffset3</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesUse1</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesUse2</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCImagesUse3</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDeviceConfigMacroFile</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDebuggerExtraOption</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCAllMTBOptions</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCMulticoreNrOfCores</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCMulticoreMaster</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCMulticorePort</name>\r
-                                       <state>53461</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCMulticoreWorkspace</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCMulticoreSlaveProject</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCMulticoreSlaveConfiguration</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDownloadExtraImage</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCAttachSlave</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>MassEraseBeforeFlashing</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>ARMSIM_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>1</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>OCSimDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCSimEnablePSP</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCSimPspOverrideConfig</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCSimPspConfigFile</name>\r
-                                       <state />\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>CADI_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>0</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>CCadiMemory</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>Fast Model</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCADILogFileCheck</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCADILogFileEditB</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>CMSISDAP_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>4</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>CatchSFERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCIarProbeScriptFile</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPResetList</name>\r
-                                       <version>1</version>\r
-                                       <state>10</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPHWResetDuration</name>\r
-                                       <state>300</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPHWResetDelay</name>\r
-                                       <state>200</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPDoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPLogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPInterfaceRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPInterfaceCmdLine</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPMultiTargetEnable</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPMultiTarget</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPJtagSpeedList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPBreakpointRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPRestoreBreakpointsCheck</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPUpdateBreakpointsEdit</name>\r
-                                       <state>_call_main</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchReset</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchUndef</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchSWI</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchData</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchPrefetch</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchIRQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchFIQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchCORERESET</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchMMERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchNOCPERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchCHKERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchSTATERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchBUSERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchINTERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchHARDERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchDummy</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPMultiCPUEnable</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPMultiCPUNumber</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCProbeCfgOverride</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCProbeConfig</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPProbeConfigRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CMSISDAPSelectedCPUBehaviour</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>ICpuName</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCJetEmuParams</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCMSISDAPUsbSerialNo</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCMSISDAPUsbSerialNoSelect</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>GDBSERVER_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>0</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>TCPIP</name>\r
-                                       <state>aaa.bbb.ccc.ddd</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>DoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>LogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJTagBreakpointRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJTagDoUpdateBreakpoints</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJTagUpdateBreakpoints</name>\r
-                                       <state>_call_main</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>IJET_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>8</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>CatchSFERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCIarProbeScriptFile</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetResetList</name>\r
-                                       <version>1</version>\r
-                                       <state>10</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetHWResetDuration</name>\r
-                                       <state>300</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetHWResetDelay</name>\r
-                                       <state>200</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetPowerFromProbe</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetPowerRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetDoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetLogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetInterfaceRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetInterfaceCmdLine</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetMultiTargetEnable</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetMultiTarget</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetScanChainNonARMDevices</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetIRLength</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetJtagSpeedList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetProtocolRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetSwoPin</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetCpuClockEdit</name>\r
-                                       <state>72.0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetSwoPrescalerList</name>\r
-                                       <version>1</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetBreakpointRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetRestoreBreakpointsCheck</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetUpdateBreakpointsEdit</name>\r
-                                       <state>_call_main</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchReset</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchUndef</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchSWI</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchData</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchPrefetch</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchIRQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>RDICatchFIQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchCORERESET</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchMMERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchNOCPERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchCHKERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchSTATERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchBUSERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchINTERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchHARDERR</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CatchDummy</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCProbeCfgOverride</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCProbeConfig</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetProbeConfigRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetMultiCPUEnable</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetMultiCPUNumber</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetSelectedCPUBehaviour</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>ICpuName</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCJetEmuParams</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetPreferETB</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetTraceSettingsList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>IjetTraceSizeList</name>\r
-                                       <version>0</version>\r
-                                       <state>4</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>FlashBoardPathSlave</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCIjetUsbSerialNo</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCIjetUsbSerialNoSelect</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>JLINK_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>16</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>CCCatchSFERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>JLinkSpeed</name>\r
-                                       <state>1000</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkDoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkLogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkHWResetDelay</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>JLinkInitialSpeed</name>\r
-                                       <state>1000</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCDoJlinkMultiTarget</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCScanChainNonARMDevices</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkMultiTarget</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkIRLength</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkCommRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkTCPIP</name>\r
-                                       <state>aaa.bbb.ccc.ddd</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkSpeedRadioV2</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCUSBDevice</name>\r
-                                       <version>1</version>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCRDICatchReset</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCRDICatchUndef</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCRDICatchSWI</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCRDICatchData</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCRDICatchPrefetch</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCRDICatchIRQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCRDICatchFIQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkBreakpointRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkDoUpdateBreakpoints</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkUpdateBreakpoints</name>\r
-                                       <state>_call_main</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkInterfaceRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkResetList</name>\r
-                                       <version>6</version>\r
-                                       <state>7</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkInterfaceCmdLine</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchCORERESET</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchMMERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchNOCPERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchCHRERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchSTATERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchBUSERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchINTERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchHARDERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCatchDummy</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCJLinkScriptFile</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkUsbSerialNo</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCTcpIpAlt</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJLinkTcpIpSerialNo</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCpuClockEdit</name>\r
-                                       <state>72.0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSwoClockAuto</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSwoClockEdit</name>\r
-                                       <state>2000</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCJLinkTraceSource</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCJLinkTraceSourceDummy</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCJLinkDeviceName</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>LMIFTDI_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>2</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>LmiftdiSpeed</name>\r
-                                       <state>500</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCLmiftdiDoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCLmiftdiLogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCLmiFtdiInterfaceRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCLmiFtdiInterfaceCmdLine</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>PEMICRO_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>3</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCJPEMicroShowSettings</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>DoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>LogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>STLINK_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>4</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkInterfaceRadio</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkInterfaceCmdLine</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkResetList</name>\r
-                                       <version>3</version>\r
-                                       <state>4</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCCpuClockEdit</name>\r
-                                       <state>80.0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSwoClockAuto</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSwoClockEdit</name>\r
-                                       <state>2000</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>DoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>LogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkDoUpdateBreakpoints</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkUpdateBreakpoints</name>\r
-                                       <state>_call_main</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchCORERESET</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchMMERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchNOCPERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchCHRERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchSTATERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchBUSERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchINTERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchSFERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchHARDERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkCatchDummy</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkUsbSerialNo</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkUsbSerialNoSelect</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkJtagSpeedList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkDAPNumber</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCSTLinkDebugAccessPortRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>THIRDPARTY_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>0</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>CThirdPartyDriverDll</name>\r
-                                       <state>###Uninitialized###</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CThirdPartyLogFileCheck</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CThirdPartyLogFileEditB</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>TIFET_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>1</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetResetList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetInterfaceRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetInterfaceCmdLine</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetTargetVccTypeDefault</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetTargetVoltage</name>\r
-                                       <state>###Uninitialized###</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetVCCDefault</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetTargetSettlingtime</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetRadioJtagSpeedType</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetConnection</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetUsbComPort</name>\r
-                                       <state>Automatic</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetAllowAccessToBSL</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetDoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetLogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCMSPFetRadioEraseFlash</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <settings>\r
-                       <name>XDS100_ID</name>\r
-                       <archiveVersion>2</archiveVersion>\r
-                       <data>\r
-                               <version>6</version>\r
-                               <wantNonLocal>1</wantNonLocal>\r
-                               <debug>1</debug>\r
-                               <option>\r
-                                       <name>OCDriverInfo</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>TIPackageOverride</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>TIPackage</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>BoardFile</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>DoLogfile</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>LogFile</name>\r
-                                       <state>$PROJ_DIR$\cspycomm.log</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100BreakpointRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100DoUpdateBreakpoints</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100UpdateBreakpoints</name>\r
-                                       <state>_call_main</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchReset</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchUndef</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchSWI</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchData</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchPrefetch</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchIRQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchFIQ</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchCORERESET</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchMMERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchNOCPERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchCHRERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchSTATERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchBUSERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchINTERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchSFERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchHARDERR</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CatchDummy</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100CpuClockEdit</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100SwoClockAuto</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100SwoClockEdit</name>\r
-                                       <state>1000</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100HWResetDelay</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100ResetList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100UsbSerialNo</name>\r
-                                       <state />\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100UsbSerialNoSelect</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100JtagSpeedList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100InterfaceRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100InterfaceCmdLine</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100ProbeList</name>\r
-                                       <version>0</version>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100SWOPortRadio</name>\r
-                                       <state>0</state>\r
-                               </option>\r
-                               <option>\r
-                                       <name>CCXds100SWOPort</name>\r
-                                       <state>1</state>\r
-                               </option>\r
-                       </data>\r
-               </settings>\r
-               <debuggerPlugins>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
-                               <loadFlag>1</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-                       <plugin>\r
-                               <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
-                               <loadFlag>0</loadFlag>\r
-                       </plugin>\r
-               </debuggerPlugins>\r
-       </configuration>\r
-</project>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewp
deleted file mode 100644 (file)
index 7344028..0000000
+++ /dev/null
@@ -1,1212 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>\r
-<project>\r
-    <fileVersion>3</fileVersion>\r
-    <configuration>\r
-        <name>MPUDemo</name>\r
-        <toolchain>\r
-            <name>ARM</name>\r
-        </toolchain>\r
-        <debug>1</debug>\r
-        <settings>\r
-            <name>General</name>\r
-            <archiveVersion>3</archiveVersion>\r
-            <data>\r
-                <version>31</version>\r
-                <wantNonLocal>1</wantNonLocal>\r
-                <debug>1</debug>\r
-                <option>\r
-                    <name>ExePath</name>\r
-                    <state>Debug/Objects</state>\r
-                </option>\r
-                <option>\r
-                    <name>ObjPath</name>\r
-                    <state>Debug/Objects</state>\r
-                </option>\r
-                <option>\r
-                    <name>ListPath</name>\r
-                    <state>Debug/Listings</state>\r
-                </option>\r
-                <option>\r
-                    <name>GEndianMode</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>Input description</name>\r
-                    <state>Full formatting, with multibyte support.</state>\r
-                </option>\r
-                <option>\r
-                    <name>Output description</name>\r
-                    <state>Full formatting, with multibyte support.</state>\r
-                </option>\r
-                <option>\r
-                    <name>GOutputBinary</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGCoreOrChip</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>GRuntimeLibSelect</name>\r
-                    <version>0</version>\r
-                    <state>2</state>\r
-                </option>\r
-                <option>\r
-                    <name>GRuntimeLibSelectSlave</name>\r
-                    <version>0</version>\r
-                    <state>2</state>\r
-                </option>\r
-                <option>\r
-                    <name>RTDescription</name>\r
-                    <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGProductVersion</name>\r
-                    <state>4.41A</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGLastSavedByProductVersion</name>\r
-                    <state>8.30.2.18207</state>\r
-                </option>\r
-                <option>\r
-                    <name>GeneralEnableMisra</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>GeneralMisraVerbose</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGChipSelectEditMenu</name>\r
-                    <state>STM32L475VG ST STM32L475VG</state>\r
-                </option>\r
-                <option>\r
-                    <name>GenLowLevelInterface</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>GEndianModeBE</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGBufferedTerminalOutput</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>GenStdoutInterface</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>GeneralMisraRules98</name>\r
-                    <version>0</version>\r
-                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
-                </option>\r
-                <option>\r
-                    <name>GeneralMisraVer</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>GeneralMisraRules04</name>\r
-                    <version>0</version>\r
-                    <state>011111111111111110111111111111011111111111111011110100111111111111111111111111111111111111111111101111111111111011111111111111111111111111111</state>\r
-                </option>\r
-                <option>\r
-                    <name>RTConfigPath2</name>\r
-                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>\r
-                </option>\r
-                <option>\r
-                    <name>GBECoreSlave</name>\r
-                    <version>26</version>\r
-                    <state>39</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGUseCmsis</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGUseCmsisDspLib</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>GRuntimeLibThreads</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CoreVariant</name>\r
-                    <version>26</version>\r
-                    <state>39</state>\r
-                </option>\r
-                <option>\r
-                    <name>GFPUDeviceSlave</name>\r
-                    <state>STM32L475VG ST STM32L475VG</state>\r
-                </option>\r
-                <option>\r
-                    <name>FPU2</name>\r
-                    <version>0</version>\r
-                    <state>4</state>\r
-                </option>\r
-                <option>\r
-                    <name>NrRegs</name>\r
-                    <version>0</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>NEON</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>GFPUCoreSlave2</name>\r
-                    <version>26</version>\r
-                    <state>39</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGCMSISPackSelectDevice</name>\r
-                </option>\r
-                <option>\r
-                    <name>OgLibHeap</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGLibAdditionalLocale</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGPrintfVariant</name>\r
-                    <version>0</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGPrintfMultibyteSupport</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGScanfVariant</name>\r
-                    <version>0</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OGScanfMultibyteSupport</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>GenLocaleTags</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>GenLocaleDisplayOnly</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>DSPExtension</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>TrustZone</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>TrustZoneModes</name>\r
-                    <version>0</version>\r
-                    <state>0</state>\r
-                </option>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>ICCARM</name>\r
-            <archiveVersion>2</archiveVersion>\r
-            <data>\r
-                <version>34</version>\r
-                <wantNonLocal>1</wantNonLocal>\r
-                <debug>1</debug>\r
-                <option>\r
-                    <name>CCOptimizationNoSizeConstraints</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCDefines</name>\r
-                    <state>USE_HAL_DRIVER</state>\r
-                    <state>STM32L475xx</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCPreprocFile</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCPreprocComments</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCPreprocLine</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCListCFile</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCListCMnemonics</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCListCMessages</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCListAssFile</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCListAssSource</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCEnableRemarks</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCDiagSuppress</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>CCDiagRemark</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>CCDiagWarning</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>CCDiagError</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>CCObjPrefix</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCAllowList</name>\r
-                    <version>1</version>\r
-                    <state>00000000</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCDebugInfo</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IEndianMode</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IProcessor</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IExtraOptionsCheck</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IExtraOptions</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>CCLangConformance</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCSignedPlainChar</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCRequirePrototypes</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCDiagWarnAreErr</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCCompilerRuntimeInfo</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IFpuProcessor</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OutputFile</name>\r
-                    <state>$FILE_BNAME$.o</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCLibConfigHeader</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>PreInclude</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>CompilerMisraOverride</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCIncludePath2</name>\r
-                    <state>$PROJ_DIR$/../../ST_Code/Core/Inc</state>\r
-                    <state>$PROJ_DIR$/../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc</state>\r
-                    <state>$PROJ_DIR$/../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy</state>\r
-                    <state>$PROJ_DIR$/../../ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include</state>\r
-                    <state>$PROJ_DIR$/../../ST_Code/Drivers/CMSIS/Include</state>\r
-                    <state>$PROJ_DIR$/../../Config</state>\r
-                    <state>$PROJ_DIR$/../../Demo</state>\r
-                    <state>$PROJ_DIR$/../../../../Source/include</state>\r
-                    <state>$PROJ_DIR$/../../../../Source/portable/IAR/ARM_CM4F_MPU</state>\r
-                    <state>$PROJ_DIR$/../../../../Source/portable/IAR/ARM_CM4F_MPU</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCStdIncCheck</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCCodeSection</name>\r
-                    <state>.text</state>\r
-                </option>\r
-                <option>\r
-                    <name>IProcessorMode2</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCOptLevel</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCOptStrategy</name>\r
-                    <version>0</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCOptLevelSlave</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CompilerMisraRules98</name>\r
-                    <version>0</version>\r
-                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
-                </option>\r
-                <option>\r
-                    <name>CompilerMisraRules04</name>\r
-                    <version>0</version>\r
-                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCPosIndRopi</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCPosIndRwpi</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCPosIndNoDynInit</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccLang</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccCDialect</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccAllowVLA</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccStaticDestr</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccCppInlineSemantics</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccCmsis</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccFloatSemantics</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCNoLiteralPool</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCOptStrategySlave</name>\r
-                    <version>0</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCGuardCalls</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCEncSource</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCEncOutput</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCEncOutputBom</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CCEncInput</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccExceptions2</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IccRTTI2</name>\r
-                    <state>0</state>\r
-                </option>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>AARM</name>\r
-            <archiveVersion>2</archiveVersion>\r
-            <data>\r
-                <version>10</version>\r
-                <wantNonLocal>1</wantNonLocal>\r
-                <debug>1</debug>\r
-                <option>\r
-                    <name>AObjPrefix</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>AEndian</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>ACaseSensitivity</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>MacroChars</name>\r
-                    <version>0</version>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AWarnEnable</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AWarnWhat</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AWarnOne</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>AWarnRange1</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>AWarnRange2</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>ADebug</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>AltRegisterNames</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>ADefines</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>AList</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AListHeader</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>AListing</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>Includes</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>MacDefs</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>MacExps</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>MacExec</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>OnlyAssed</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>MultiLine</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>PageLengthCheck</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>PageLength</name>\r
-                    <state>80</state>\r
-                </option>\r
-                <option>\r
-                    <name>TabSpacing</name>\r
-                    <state>8</state>\r
-                </option>\r
-                <option>\r
-                    <name>AXRef</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AXRefDefines</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AXRefInternal</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AXRefDual</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AProcessor</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>AFpuProcessor</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>AOutputFile</name>\r
-                    <state>$FILE_BNAME$.o</state>\r
-                </option>\r
-                <option>\r
-                    <name>ALimitErrorsCheck</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>ALimitErrorsEdit</name>\r
-                    <state>100</state>\r
-                </option>\r
-                <option>\r
-                    <name>AIgnoreStdInclude</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AUserIncludes</name>\r
-                    <state>$PROJ_DIR$\..\..\Config</state>\r
-                </option>\r
-                <option>\r
-                    <name>AExtraOptionsCheckV2</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>AExtraOptionsV2</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>AsmNoLiteralPool</name>\r
-                    <state>0</state>\r
-                </option>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>OBJCOPY</name>\r
-            <archiveVersion>0</archiveVersion>\r
-            <data>\r
-                <version>1</version>\r
-                <wantNonLocal>1</wantNonLocal>\r
-                <debug>1</debug>\r
-                <option>\r
-                    <name>OOCOutputFormat</name>\r
-                    <version>3</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OCOutputOverride</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OOCOutputFile</name>\r
-                    <state>MPUDemo.hex</state>\r
-                </option>\r
-                <option>\r
-                    <name>OOCCommandLineProducer</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>OOCObjCopyEnable</name>\r
-                    <state>1</state>\r
-                </option>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>CUSTOM</name>\r
-            <archiveVersion>3</archiveVersion>\r
-            <data>\r
-                <extensions></extensions>\r
-                <cmdline></cmdline>\r
-                <hasPrio>0</hasPrio>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>BICOMP</name>\r
-            <archiveVersion>0</archiveVersion>\r
-            <data />\r
-        </settings>\r
-        <settings>\r
-            <name>BUILDACTION</name>\r
-            <archiveVersion>1</archiveVersion>\r
-            <data>\r
-                <prebuild></prebuild>\r
-                <postbuild></postbuild>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>ILINK</name>\r
-            <archiveVersion>0</archiveVersion>\r
-            <data>\r
-                <version>21</version>\r
-                <wantNonLocal>1</wantNonLocal>\r
-                <debug>1</debug>\r
-                <option>\r
-                    <name>IlinkLibIOConfig</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>XLinkMisraHandler</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkInputFileSlave</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOutputFile</name>\r
-                    <state>MPUDemo.out</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkDebugInfoEnable</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkKeepSymbols</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkRawBinaryFile</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkRawBinarySymbol</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkRawBinarySegment</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkRawBinaryAlign</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkDefines</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkConfigDefines</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkMapFile</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogFile</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogInitialization</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogModule</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogSection</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogVeneer</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkIcfOverride</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkIcfFile</name>\r
-                    <state>$PROJ_DIR$/stm32l475xx_flash.icf</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkIcfFileSlave</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkEnableRemarks</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkSuppressDiags</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkTreatAsRem</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkTreatAsWarn</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkTreatAsErr</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkWarningsAreErrors</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkUseExtraOptions</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkExtraOptions</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLowLevelInterfaceSlave</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkAutoLibEnable</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkAdditionalLibs</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOverrideProgramEntryLabel</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkProgramEntryLabelSelect</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkProgramEntryLabel</name>\r
-                    <state>__iar_program_start</state>\r
-                </option>\r
-                <option>\r
-                    <name>DoFill</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>FillerByte</name>\r
-                    <state>0xFF</state>\r
-                </option>\r
-                <option>\r
-                    <name>FillerStart</name>\r
-                    <state>0x0</state>\r
-                </option>\r
-                <option>\r
-                    <name>FillerEnd</name>\r
-                    <state>0x0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcSize</name>\r
-                    <version>0</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcAlign</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcPoly</name>\r
-                    <state>0x11021</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcCompl</name>\r
-                    <version>0</version>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcBitOrder</name>\r
-                    <version>0</version>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcInitialValue</name>\r
-                    <state>0x0</state>\r
-                </option>\r
-                <option>\r
-                    <name>DoCrc</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkBE8Slave</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkBufferedTerminalOutput</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkStdoutInterfaceSlave</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcFullSize</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkIElfToolPostProcess</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogAutoLibSelect</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogRedirSymbols</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogUnusedFragments</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkCrcReverseByteOrder</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkCrcUseAsInput</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOptInline</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOptExceptionsAllow</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOptExceptionsForce</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkCmsis</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOptMergeDuplSections</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOptUseVfe</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkOptForceVfe</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkStackAnalysisEnable</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkStackControlFile</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkStackCallGraphFile</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcAlgorithm</name>\r
-                    <version>1</version>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>CrcUnitSize</name>\r
-                    <version>0</version>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkThreadsSlave</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLogCallGraph</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkIcfFile_AltDefault</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkEncInput</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkEncOutput</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkEncOutputBom</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkHeapSelect</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkLocaleSelect</name>\r
-                    <state>1</state>\r
-                </option>\r
-                <option>\r
-                    <name>IlinkTrustzoneImportLibraryOut</name>\r
-                    <state>MPUDemo_import_lib.o</state>\r
-                </option>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>IARCHIVE</name>\r
-            <archiveVersion>0</archiveVersion>\r
-            <data>\r
-                <version>0</version>\r
-                <wantNonLocal>1</wantNonLocal>\r
-                <debug>1</debug>\r
-                <option>\r
-                    <name>IarchiveInputs</name>\r
-                    <state></state>\r
-                </option>\r
-                <option>\r
-                    <name>IarchiveOverride</name>\r
-                    <state>0</state>\r
-                </option>\r
-                <option>\r
-                    <name>IarchiveOutput</name>\r
-                    <state>###Unitialized###</state>\r
-                </option>\r
-            </data>\r
-        </settings>\r
-        <settings>\r
-            <name>BILINK</name>\r
-            <archiveVersion>0</archiveVersion>\r
-            <data />\r
-        </settings>\r
-    </configuration>\r
-    <group>\r
-        <name>Config</name>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\Config\FreeRTOSConfig.h</name>\r
-        </file>\r
-    </group>\r
-    <group>\r
-        <name>Demo</name>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\Demo\app_main.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\Demo\app_main.h</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\Demo\mpu_demo.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\Demo\mpu_demo.h</name>\r
-        </file>\r
-    </group>\r
-    <group>\r
-        <name>FreeRTOS</name>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\croutine.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\event_groups.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_4.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\list.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\portable\Common\mpu_wrappers.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\port.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\portasm.s</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\portmacro.h</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\queue.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\stream_buffer.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\tasks.c</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\..\..\..\..\Source\timers.c</name>\r
-        </file>\r
-    </group>\r
-    <group>\r
-        <name>ST_Code</name>\r
-        <group>\r
-            <name>Core</name>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\main.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_hal_msp.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_hal_timebase_tim.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_it.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Core\Src\system_stm32l4xx.c</name>\r
-            </file>\r
-        </group>\r
-        <group>\r
-            <name>STM32L4xx_HAL_Driver</name>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c</name>\r
-            </file>\r
-            <file>\r
-                <name>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c</name>\r
-            </file>\r
-        </group>\r
-    </group>\r
-    <group>\r
-        <name>Startup</name>\r
-        <file>\r
-            <name>$PROJ_DIR$\memfault_handler.s</name>\r
-        </file>\r
-        <file>\r
-            <name>$PROJ_DIR$\startup_stm32l475xx.s</name>\r
-        </file>\r
-    </group>\r
-</project>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.eww b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.eww
deleted file mode 100644 (file)
index 5fcd4a0..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>\r
-<workspace>\r
-  <project>\r
-    <path>$WS_DIR$\MPUDemo.ewp</path>\r
-  </project>\r
-  <batchBuild />\r
-</workspace>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/memfault_handler.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/memfault_handler.s
deleted file mode 100644 (file)
index 4e7b3af..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-       EXTERN vHandleMemoryFault\r
-       PUBLIC MemManage_Handler\r
-\r
-       SECTION .text:CODE:NOROOT(2)\r
-       THUMB\r
-/*-----------------------------------------------------------*/\r
-\r
-MemManage_Handler:\r
-       tst lr, #4\r
-       ite eq\r
-       mrseq r0, msp\r
-       mrsne r0, psp\r
-       b vHandleMemoryFault\r
-/*-----------------------------------------------------------*/\r
-\r
-       END\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/startup_stm32l475xx.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/startup_stm32l475xx.s
deleted file mode 100644 (file)
index ca1cd67..0000000
+++ /dev/null
@@ -1,630 +0,0 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************\r
-;* File Name          : startup_stm32l475xx.s\r
-;* Author             : MCD Application Team\r
-;* Description        : STM32L475xx Ultra Low Power Devices vector\r
-;*                      This module performs:\r
-;*                      - Set the initial SP\r
-;*                      - Set the initial PC == _iar_program_start,\r
-;*                      - Set the vector table entries with the exceptions ISR\r
-;*                        address.\r
-;*                      - Branches to main in the C library (which eventually\r
-;*                        calls main()).\r
-;*                      After Reset the Cortex-M4 processor is in Thread mode,\r
-;*                      priority is Privileged, and the Stack is set to Main.\r
-;********************************************************************************\r
-;*\r
-;* Redistribution and use in source and binary forms, with or without modification,\r
-;* are permitted provided that the following conditions are met:\r
-;*   1. Redistributions of source code must retain the above copyright notice,\r
-;*      this list of conditions and the following disclaimer.\r
-;*   2. Redistributions in binary form must reproduce the above copyright notice,\r
-;*      this list of conditions and the following disclaimer in the documentation\r
-;*      and/or other materials provided with the distribution.\r
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-;*      may be used to endorse or promote products derived from this software\r
-;*      without specific prior written permission.\r
-;*\r
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-;*\r
-;*******************************************************************************\r
-;\r
-;\r
-; The modules in this file are included in the libraries, and may be replaced\r
-; by any user-defined modules that define the PUBLIC symbol _program_start or\r
-; a user defined start symbol.\r
-; To override the cstartup defined in the library, simply add your modified\r
-; version to the workbench project.\r
-;\r
-; The vector table is normally located at address 0.\r
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
-; The name "__vector_table" has special meaning for C-SPY:\r
-; it is where the SP start value is found, and the NVIC vector\r
-; table register (VTOR) is initialized to this address if != 0.\r
-;\r
-; Cortex-M version\r
-;\r
-\r
-        MODULE  ?cstartup\r
-\r
-        ;; Forward declaration of sections.\r
-        SECTION CSTACK:DATA:NOROOT(3)\r
-\r
-        SECTION .intvec:CODE:NOROOT(2)\r
-\r
-        EXTERN  __iar_program_start\r
-        EXTERN  SystemInit\r
-        PUBLIC  __vector_table\r
-\r
-        DATA\r
-__vector_table\r
-        DCD     sfe(CSTACK)\r
-        DCD     Reset_Handler             ; Reset Handler\r
-\r
-        DCD     NMI_Handler               ; NMI Handler\r
-        DCD     HardFault_Handler         ; Hard Fault Handler\r
-        DCD     MemManage_Handler         ; MPU Fault Handler\r
-        DCD     BusFault_Handler          ; Bus Fault Handler\r
-        DCD     UsageFault_Handler        ; Usage Fault Handler\r
-        DCD     0                         ; Reserved\r
-        DCD     0                         ; Reserved\r
-        DCD     0                         ; Reserved\r
-        DCD     0                         ; Reserved\r
-        DCD     SVC_Handler               ; SVCall Handler\r
-        DCD     DebugMon_Handler          ; Debug Monitor Handler\r
-        DCD     0                         ; Reserved\r
-        DCD     PendSV_Handler            ; PendSV Handler\r
-        DCD     SysTick_Handler           ; SysTick Handler\r
-\r
-         ; External Interrupts\r
-        DCD     WWDG_IRQHandler                   ; Window WatchDog\r
-        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection\r
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line\r
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line\r
-        DCD     FLASH_IRQHandler                  ; FLASH\r
-        DCD     RCC_IRQHandler                    ; RCC\r
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0\r
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1\r
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2\r
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3\r
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4\r
-        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1\r
-        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2\r
-        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3\r
-        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4\r
-        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5\r
-        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6\r
-        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7\r
-        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2\r
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX\r
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0\r
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1\r
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE\r
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s\r
-        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15\r
-        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16\r
-        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17\r
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare\r
-        DCD     TIM2_IRQHandler                   ; TIM2\r
-        DCD     TIM3_IRQHandler                   ; TIM3\r
-        DCD     TIM4_IRQHandler                   ; TIM4\r
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event\r
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error\r
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event\r
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error\r
-        DCD     SPI1_IRQHandler                   ; SPI1\r
-        DCD     SPI2_IRQHandler                   ; SPI2\r
-        DCD     USART1_IRQHandler                 ; USART1\r
-        DCD     USART2_IRQHandler                 ; USART2\r
-        DCD     USART3_IRQHandler                 ; USART3\r
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]\r
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line\r
-        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt\r
-        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt\r
-        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt\r
-        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt\r
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt\r
-        DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt\r
-        DCD     FMC_IRQHandler                    ; FMC\r
-        DCD     SDMMC1_IRQHandler                 ; SDMMC1\r
-        DCD     TIM5_IRQHandler                   ; TIM5\r
-        DCD     SPI3_IRQHandler                   ; SPI3\r
-        DCD     UART4_IRQHandler                  ; UART4\r
-        DCD     UART5_IRQHandler                  ; UART5\r
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors\r
-        DCD     TIM7_IRQHandler                   ; TIM7\r
-        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1\r
-        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2\r
-        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3\r
-        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4\r
-        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5\r
-        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt\r
-        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt\r
-        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt\r
-        DCD     COMP_IRQHandler                   ; COMP Interrupt\r
-        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt\r
-        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt\r
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS\r
-        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6\r
-        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7\r
-        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt\r
-        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt\r
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event\r
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error\r
-        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt\r
-        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt\r
-        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt\r
-        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt\r
-        DCD     0                                 ; Reserved        \r
-        DCD     0                                 ; Reserved        \r
-        DCD     RNG_IRQHandler                    ; RNG global interrupt\r
-        DCD     FPU_IRQHandler                    ; FPU\r
-\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-;;\r
-;; Default interrupt handlers.\r
-;;\r
-        THUMB\r
-        PUBWEAK Reset_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(2)\r
-Reset_Handler\r
-        LDR     R0, =SystemInit\r
-        BLX     R0\r
-        LDR     R0, =__iar_program_start\r
-        BX      R0\r
-\r
-        PUBWEAK NMI_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-NMI_Handler\r
-        B NMI_Handler\r
-\r
-        PUBWEAK HardFault_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-HardFault_Handler\r
-        B HardFault_Handler\r
-\r
-        PUBWEAK MemManage_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-MemManage_Handler\r
-        B MemManage_Handler\r
-\r
-        PUBWEAK BusFault_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-BusFault_Handler\r
-        B BusFault_Handler\r
-\r
-        PUBWEAK UsageFault_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-UsageFault_Handler\r
-        B UsageFault_Handler\r
-\r
-        PUBWEAK SVC_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SVC_Handler\r
-        B SVC_Handler\r
-\r
-        PUBWEAK DebugMon_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DebugMon_Handler\r
-        B DebugMon_Handler\r
-\r
-        PUBWEAK PendSV_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-PendSV_Handler\r
-        B PendSV_Handler\r
-\r
-        PUBWEAK SysTick_Handler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SysTick_Handler\r
-        B SysTick_Handler\r
-\r
-        PUBWEAK WWDG_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-WWDG_IRQHandler\r
-        B WWDG_IRQHandler\r
-\r
-        PUBWEAK PVD_PVM_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-PVD_PVM_IRQHandler\r
-        B PVD_PVM_IRQHandler\r
-\r
-        PUBWEAK TAMP_STAMP_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TAMP_STAMP_IRQHandler\r
-        B TAMP_STAMP_IRQHandler\r
-\r
-        PUBWEAK RTC_WKUP_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-RTC_WKUP_IRQHandler\r
-        B RTC_WKUP_IRQHandler\r
-\r
-        PUBWEAK FLASH_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-FLASH_IRQHandler\r
-        B FLASH_IRQHandler\r
-\r
-        PUBWEAK RCC_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-RCC_IRQHandler\r
-        B RCC_IRQHandler\r
-\r
-        PUBWEAK EXTI0_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-EXTI0_IRQHandler\r
-        B EXTI0_IRQHandler\r
-\r
-        PUBWEAK EXTI1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-EXTI1_IRQHandler\r
-        B EXTI1_IRQHandler\r
-\r
-        PUBWEAK EXTI2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-EXTI2_IRQHandler\r
-        B EXTI2_IRQHandler\r
-\r
-        PUBWEAK EXTI3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-EXTI3_IRQHandler\r
-        B EXTI3_IRQHandler\r
-\r
-        PUBWEAK EXTI4_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-EXTI4_IRQHandler\r
-        B EXTI4_IRQHandler\r
-\r
-        PUBWEAK DMA1_Channel1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA1_Channel1_IRQHandler\r
-        B DMA1_Channel1_IRQHandler\r
-\r
-        PUBWEAK DMA1_Channel2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA1_Channel2_IRQHandler\r
-        B DMA1_Channel2_IRQHandler\r
-\r
-        PUBWEAK DMA1_Channel3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA1_Channel3_IRQHandler\r
-        B DMA1_Channel3_IRQHandler\r
-\r
-        PUBWEAK DMA1_Channel4_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA1_Channel4_IRQHandler\r
-        B DMA1_Channel4_IRQHandler\r
-\r
-        PUBWEAK DMA1_Channel5_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA1_Channel5_IRQHandler\r
-        B DMA1_Channel5_IRQHandler\r
-\r
-        PUBWEAK DMA1_Channel6_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA1_Channel6_IRQHandler\r
-        B DMA1_Channel6_IRQHandler\r
-\r
-        PUBWEAK DMA1_Channel7_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA1_Channel7_IRQHandler\r
-        B DMA1_Channel7_IRQHandler\r
-\r
-        PUBWEAK ADC1_2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-ADC1_2_IRQHandler\r
-        B ADC1_2_IRQHandler\r
-\r
-        PUBWEAK CAN1_TX_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-CAN1_TX_IRQHandler\r
-        B CAN1_TX_IRQHandler\r
-\r
-        PUBWEAK CAN1_RX0_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-CAN1_RX0_IRQHandler\r
-        B CAN1_RX0_IRQHandler\r
-\r
-        PUBWEAK CAN1_RX1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-CAN1_RX1_IRQHandler\r
-        B CAN1_RX1_IRQHandler\r
-\r
-        PUBWEAK CAN1_SCE_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-CAN1_SCE_IRQHandler\r
-        B CAN1_SCE_IRQHandler\r
-\r
-        PUBWEAK EXTI9_5_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-EXTI9_5_IRQHandler\r
-        B EXTI9_5_IRQHandler\r
-\r
-        PUBWEAK TIM1_BRK_TIM15_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM1_BRK_TIM15_IRQHandler\r
-        B TIM1_BRK_TIM15_IRQHandler\r
-\r
-        PUBWEAK TIM1_UP_TIM16_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM1_UP_TIM16_IRQHandler\r
-        B TIM1_UP_TIM16_IRQHandler\r
-\r
-        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM1_TRG_COM_TIM17_IRQHandler\r
-        B TIM1_TRG_COM_TIM17_IRQHandler\r
-\r
-        PUBWEAK TIM1_CC_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM1_CC_IRQHandler\r
-        B TIM1_CC_IRQHandler\r
-\r
-        PUBWEAK TIM2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM2_IRQHandler\r
-        B TIM2_IRQHandler\r
-\r
-        PUBWEAK TIM3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM3_IRQHandler\r
-        B TIM3_IRQHandler\r
-\r
-        PUBWEAK TIM4_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM4_IRQHandler\r
-        B TIM4_IRQHandler\r
-\r
-        PUBWEAK I2C1_EV_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-I2C1_EV_IRQHandler\r
-        B I2C1_EV_IRQHandler\r
-\r
-        PUBWEAK I2C1_ER_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-I2C1_ER_IRQHandler\r
-        B I2C1_ER_IRQHandler\r
-\r
-        PUBWEAK I2C2_EV_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-I2C2_EV_IRQHandler\r
-        B I2C2_EV_IRQHandler\r
-\r
-        PUBWEAK I2C2_ER_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-I2C2_ER_IRQHandler\r
-        B I2C2_ER_IRQHandler\r
-\r
-        PUBWEAK SPI1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SPI1_IRQHandler\r
-        B SPI1_IRQHandler\r
-\r
-        PUBWEAK SPI2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SPI2_IRQHandler\r
-        B SPI2_IRQHandler\r
-\r
-        PUBWEAK USART1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-USART1_IRQHandler\r
-        B USART1_IRQHandler\r
-\r
-        PUBWEAK USART2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-USART2_IRQHandler\r
-        B USART2_IRQHandler\r
-\r
-        PUBWEAK USART3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-USART3_IRQHandler\r
-        B USART3_IRQHandler\r
-\r
-        PUBWEAK EXTI15_10_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-EXTI15_10_IRQHandler\r
-        B EXTI15_10_IRQHandler\r
-\r
-        PUBWEAK RTC_Alarm_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-RTC_Alarm_IRQHandler\r
-        B RTC_Alarm_IRQHandler\r
-\r
-        PUBWEAK DFSDM1_FLT3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DFSDM1_FLT3_IRQHandler\r
-        B DFSDM1_FLT3_IRQHandler\r
-\r
-        PUBWEAK TIM8_BRK_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM8_BRK_IRQHandler\r
-        B TIM8_BRK_IRQHandler\r
-\r
-        PUBWEAK TIM8_UP_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM8_UP_IRQHandler\r
-        B TIM8_UP_IRQHandler\r
-\r
-        PUBWEAK TIM8_TRG_COM_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM8_TRG_COM_IRQHandler\r
-        B TIM8_TRG_COM_IRQHandler\r
-\r
-        PUBWEAK TIM8_CC_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM8_CC_IRQHandler\r
-        B TIM8_CC_IRQHandler\r
-\r
-        PUBWEAK ADC3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-ADC3_IRQHandler\r
-        B ADC3_IRQHandler\r
-\r
-        PUBWEAK FMC_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-FMC_IRQHandler\r
-        B FMC_IRQHandler\r
-\r
-        PUBWEAK SDMMC1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SDMMC1_IRQHandler\r
-        B SDMMC1_IRQHandler\r
-\r
-        PUBWEAK TIM5_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM5_IRQHandler\r
-        B TIM5_IRQHandler\r
-\r
-        PUBWEAK SPI3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SPI3_IRQHandler\r
-        B SPI3_IRQHandler\r
-\r
-        PUBWEAK UART4_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-UART4_IRQHandler\r
-        B UART4_IRQHandler\r
-\r
-        PUBWEAK UART5_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-UART5_IRQHandler\r
-        B UART5_IRQHandler\r
-\r
-        PUBWEAK TIM6_DAC_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM6_DAC_IRQHandler\r
-        B TIM6_DAC_IRQHandler\r
-\r
-        PUBWEAK TIM7_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-TIM7_IRQHandler\r
-        B TIM7_IRQHandler\r
-\r
-        PUBWEAK DMA2_Channel1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA2_Channel1_IRQHandler\r
-        B DMA2_Channel1_IRQHandler\r
-\r
-        PUBWEAK DMA2_Channel2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA2_Channel2_IRQHandler\r
-        B DMA2_Channel2_IRQHandler\r
-\r
-        PUBWEAK DMA2_Channel3_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA2_Channel3_IRQHandler\r
-        B DMA2_Channel3_IRQHandler\r
-\r
-        PUBWEAK DMA2_Channel4_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA2_Channel4_IRQHandler\r
-        B DMA2_Channel4_IRQHandler\r
-\r
-        PUBWEAK DMA2_Channel5_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA2_Channel5_IRQHandler\r
-        B DMA2_Channel5_IRQHandler\r
-\r
-        PUBWEAK DFSDM1_FLT0_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DFSDM1_FLT0_IRQHandler\r
-        B DFSDM1_FLT0_IRQHandler\r
-\r
-        PUBWEAK DFSDM1_FLT1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DFSDM1_FLT1_IRQHandler\r
-        B DFSDM1_FLT1_IRQHandler\r
-\r
-        PUBWEAK DFSDM1_FLT2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DFSDM1_FLT2_IRQHandler\r
-        B DFSDM1_FLT2_IRQHandler\r
-\r
-        PUBWEAK COMP_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-COMP_IRQHandler\r
-        B COMP_IRQHandler\r
-\r
-        PUBWEAK LPTIM1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-LPTIM1_IRQHandler\r
-        B LPTIM1_IRQHandler\r
-\r
-        PUBWEAK LPTIM2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-LPTIM2_IRQHandler\r
-        B LPTIM2_IRQHandler\r
-\r
-        PUBWEAK OTG_FS_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-OTG_FS_IRQHandler\r
-        B OTG_FS_IRQHandler\r
-\r
-        PUBWEAK DMA2_Channel6_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA2_Channel6_IRQHandler\r
-        B DMA2_Channel6_IRQHandler\r
-\r
-        PUBWEAK DMA2_Channel7_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-DMA2_Channel7_IRQHandler\r
-        B DMA2_Channel7_IRQHandler\r
-\r
-        PUBWEAK LPUART1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-LPUART1_IRQHandler\r
-        B LPUART1_IRQHandler\r
-\r
-        PUBWEAK QUADSPI_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-QUADSPI_IRQHandler\r
-        B QUADSPI_IRQHandler\r
-\r
-        PUBWEAK I2C3_EV_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-I2C3_EV_IRQHandler\r
-        B I2C3_EV_IRQHandler\r
-\r
-        PUBWEAK I2C3_ER_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-I2C3_ER_IRQHandler\r
-        B I2C3_ER_IRQHandler\r
-\r
-        PUBWEAK SAI1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SAI1_IRQHandler\r
-        B SAI1_IRQHandler\r
-\r
-       PUBWEAK SAI2_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SAI2_IRQHandler\r
-        B SAI2_IRQHandler\r
-\r
-        PUBWEAK SWPMI1_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-SWPMI1_IRQHandler\r
-        B SWPMI1_IRQHandler\r
-\r
-       PUBWEAK TSC_IRQHandler\r
-       SECTION .text:CODE:NOROOT:REORDER(1)\r
-TSC_IRQHandler\r
-       B TSC_IRQHandler\r
-\r
-        PUBWEAK RNG_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-RNG_IRQHandler\r
-        B RNG_IRQHandler\r
-\r
-        PUBWEAK FPU_IRQHandler\r
-        SECTION .text:CODE:NOROOT:REORDER(1)\r
-FPU_IRQHandler\r
-        B FPU_IRQHandler\r
-\r
-        END\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/stm32l475xx_flash.icf b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/stm32l475xx_flash.icf
deleted file mode 100644 (file)
index 90a1e1e..0000000
+++ /dev/null
@@ -1,96 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/\r
-/*-Editor annotation file-*/\r
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
-/*-Specials-*/\r
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
-/*-Memory Regions-*/\r
-define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;\r
-define symbol __ICFEDIT_region_ROM_end__      = 0x080FFFFF;\r
-define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;\r
-define symbol __ICFEDIT_region_RAM_end__      = 0x20017FFF;\r
-\r
-/*-Sizes-*/\r
-define symbol __ICFEDIT_size_cstack__ = 0x400;\r
-define symbol __ICFEDIT_size_heap__ = 0x200;\r
-/**** End of ICF editor section. ###ICF###*/\r
-\r
-/* Flash Organization\r
- *  1. Privileged Code:\r
- *      Start   : 0x08000000\r
- *      End     : 0x08007FFF\r
- *      Size    : 32 Kbytes\r
- *  2. System calls:\r
- *      Start   : 0x08008000\r
- *      End     : 0x08008FFF\r
- *      Size    : 4 Kbytes\r
- *  3. Unprivileged Code:\r
- *      Start   : 0x08009000\r
- *      End     : 0x080FFFFF\r
- *      Size    : 988 Kbytes\r
- */\r
-define symbol __reigon_ROM_privileged_start__   = __ICFEDIT_region_ROM_start__;\r
-define symbol __reigon_ROM_privileged_end__     = 0x08007FFF;\r
-define symbol __reigon_ROM_system_calls_start__ = 0x08008000;\r
-define symbol __reigon_ROM_system_calls_end__   = 0x08008FFF;\r
-define symbol __reigon_ROM_unprivileged_start__ = 0x08009000;\r
-define symbol __reigon_ROM_unprivileged_end__   = __ICFEDIT_region_ROM_end__;\r
-\r
-/* RAM Organization\r
- *  1. Privileged Data:\r
- *      Start   : 0x20000000\r
- *      End     : 0x200003FF\r
- *      Size    : 1 Kbytes\r
- *  2. Unprivileged Data:\r
- *      Start   : 0x20000400\r
- *      End     : 0x20017FFF\r
- *      Size    : 95 Kbytes\r
- */\r
-define symbol __region_RAM_privileged_start__   = __ICFEDIT_region_RAM_start__;\r
-define symbol __region_RAM_privileged_end__     = 0x200003FF;\r
-define symbol __region_RAM_unprivileged_start__ = 0x20000400;\r
-define symbol __region_RAM_unprivileged_end__   = __ICFEDIT_region_RAM_end__;\r
-define symbol __region_SRAM2_start__            = 0x10000000;\r
-define symbol __region_SRAM2_end__              = 0x10007FFF;\r
-\r
-/* Memory regions. */\r
-define memory mem with size = 4G;\r
-define region ROM_region_privileged     = mem:[from __reigon_ROM_privileged_start__ to __reigon_ROM_privileged_end__];\r
-define region ROM_region_system_calls   = mem:[from __reigon_ROM_system_calls_start__ to __reigon_ROM_system_calls_end__];\r
-define region ROM_region_unprivileged   = mem:[from __reigon_ROM_unprivileged_start__ to __reigon_ROM_unprivileged_end__];\r
-define region RAM_region_privileged     = mem:[from __region_RAM_privileged_start__   to __region_RAM_privileged_end__];\r
-define region RAM_region_unprivileged   = mem:[from __region_RAM_unprivileged_start__   to __region_RAM_unprivileged_end__];\r
-define region SRAM2_region              = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];\r
-\r
-/* Stack and Heap. */\r
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
-\r
-/* Initialization. */\r
-initialize by copy { readwrite };\r
-do not initialize  { section .noinit };\r
-\r
-/* Exported symbols. */\r
-define exported symbol __FLASH_segment_start__          = __ICFEDIT_region_ROM_start__;\r
-define exported symbol __FLASH_segment_end__            = __ICFEDIT_region_ROM_end__;\r
-define exported symbol __SRAM_segment_start__           = __ICFEDIT_region_RAM_start__;\r
-define exported symbol __SRAM_segment_end__             = __ICFEDIT_region_RAM_end__;\r
-\r
-define exported symbol __privileged_functions_start__   = __reigon_ROM_privileged_start__;\r
-define exported symbol __privileged_functions_end__     = __reigon_ROM_privileged_end__;\r
-define exported symbol __privileged_data_start__        = __region_RAM_privileged_start__;\r
-define exported symbol __privileged_data_end__          = __region_RAM_privileged_end__;\r
-\r
-define exported symbol __syscalls_flash_start__         = __reigon_ROM_system_calls_start__;\r
-define exported symbol __syscalls_flash_end__           = __reigon_ROM_system_calls_end__;\r
-\r
-/* Placements. */\r
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
-\r
-place in ROM_region_privileged      { readonly section privileged_functions };\r
-place in ROM_region_system_calls    { readonly section freertos_system_calls };\r
-place in ROM_region_unprivileged    { readonly };\r
-\r
-place in RAM_region_privileged      { readwrite section privileged_data };\r
-place in RAM_region_unprivileged    { readwrite,\r
-                                      block CSTACK, block HEAP }; \r
-place in SRAM2_region               { };\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/EventRecorderStub.scvd b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/EventRecorderStub.scvd
deleted file mode 100644 (file)
index 0fb3ee5..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>\r
-\r
-<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">\r
-\r
-<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->\r
-  <events>\r
-  </events>\r
-\r
-</component_viewer>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.sct b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.sct
deleted file mode 100644 (file)
index 891bc1b..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-; Flash Layout\r
-;\r
-;  ---------------------\r
-; |   Privileged Code   |\r
-;  ---------------------\r
-; |  Unprivileged Code  |\r
-;  ---------------------\r
-;\r
-; RAM Layout\r
-;\r
-;  ---------------------\r
-; |   Privileged Data   |\r
-;  ---------------------\r
-; |  Unprivileged Data  |\r
-;  ---------------------\r
-\r
-LR_APP 0x08000000 0x100000 ; load region size_region\r
-{\r
-    ER_IROM_PRIVILEGED 0x08000000\r
-    {\r
-        *.o (RESET, +First)\r
-        *(InRoot$$Sections)\r
-        *(privileged_functions)\r
-    }\r
-\r
-    ER_IROM_FREERTOS_SYSTEM_CALLS 0x08008000 FIXED\r
-    {\r
-        *(freertos_system_calls)\r
-    }\r
-\r
-    ER_IROM_UNPRIVILEGED +0\r
-    {\r
-        .ANY (+RO)\r
-    }\r
-\r
-    RW_IRAM_PRIVILEGED 0x20000000\r
-    {\r
-        *(privileged_data)\r
-    }\r
-\r
-    RW_IRAM_UNPRIVILEGED 0x20000400\r
-    {\r
-        .ANY (+RW +ZI)\r
-    }\r
-}\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvoptx
deleted file mode 100644 (file)
index 6cdaf39..0000000
+++ /dev/null
@@ -1,856 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj; *.o</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-    <nMigrate>0</nMigrate>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>MPUDemo</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>80000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-        <RunAbUc>0</RunAbUc>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath></ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>18</CpuCode>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>1</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>1</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <bEvRecOn>1</bEvRecOn>
-        <bSchkAxf>0</bSchkAxf>
-        <bTchkAxf>0</bTchkAxf>
-        <nTsel>5</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>ARMRTXEVENTFLAGS</Key>
-          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>DLGTARM</Key>
-          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=2981,231,3458,546,0)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>ARMDBGFLAGS</Key>
-          <Name></Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>DLGUARM</Key>
-          <Name>(105=-1,-1,-1,-1,0)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32L475VGTx$CMSIS\Flash\STM32L4xx_1024.FLM))</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>ST-LINKIII-KEIL_SWO</Key>
-          <Name>-U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L475VGTx$CMSIS\Flash\STM32L4xx_1024.FLM)</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint/>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>1</periodic>
-        <aLwin>1</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>1</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
-        <AscS2>0</AscS2>
-        <AscS3>0</AscS3>
-        <aSer3>0</aSer3>
-        <eProf>0</eProf>
-        <aLa>0</aLa>
-        <aPa1>0</aPa1>
-        <AscS4>0</AscS4>
-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-      <bLintAuto>0</bLintAuto>
-      <bAutoGenD>0</bAutoGenD>
-      <LntExFlags>0</LntExFlags>
-      <pMisraName></pMisraName>
-      <pszMrule></pszMrule>
-      <pSingCmds></pSingCmds>
-      <pMultCmds></pMultCmds>
-      <pMisraNamep></pMisraNamep>
-      <pszMrulep></pszMrulep>
-      <pSingCmdsp></pSingCmdsp>
-      <pMultCmdsp></pMultCmdsp>
-      <DebugDescription>
-        <Enable>1</Enable>
-        <EnableFlashSeq>0</EnableFlashSeq>
-        <EnableLog>0</EnableLog>
-        <Protocol>2</Protocol>
-        <DbgClock>10000000</DbgClock>
-      </DebugDescription>
-    </TargetOption>
-  </Target>
-
-  <Group>
-    <GroupName>Startup</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>1</GroupNumber>
-      <FileNumber>1</FileNumber>
-      <FileType>2</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>startup_stm32l475xx.s</PathWithFileName>
-      <FilenameWithoutPath>startup_stm32l475xx.s</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>1</GroupNumber>
-      <FileNumber>2</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>.\memfault_handler.c</PathWithFileName>
-      <FilenameWithoutPath>memfault_handler.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
-  <Group>
-    <GroupName>FreeRTOS</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>3</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/croutine.c</PathWithFileName>
-      <FilenameWithoutPath>croutine.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>4</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/event_groups.c</PathWithFileName>
-      <FilenameWithoutPath>event_groups.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>5</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/list.c</PathWithFileName>
-      <FilenameWithoutPath>list.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>6</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/queue.c</PathWithFileName>
-      <FilenameWithoutPath>queue.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>7</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/stream_buffer.c</PathWithFileName>
-      <FilenameWithoutPath>stream_buffer.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>8</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/tasks.c</PathWithFileName>
-      <FilenameWithoutPath>tasks.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>9</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/timers.c</PathWithFileName>
-      <FilenameWithoutPath>timers.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>10</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/portable/Common/mpu_wrappers.c</PathWithFileName>
-      <FilenameWithoutPath>mpu_wrappers.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>11</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/portable/GCC/ARM_CM4_MPU/port.c</PathWithFileName>
-      <FilenameWithoutPath>port.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>12</FileNumber>
-      <FileType>5</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/portable/GCC/ARM_CM4_MPU/portmacro.h</PathWithFileName>
-      <FilenameWithoutPath>portmacro.h</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>2</GroupNumber>
-      <FileNumber>13</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../../../Source/portable/MemMang/heap_4.c</PathWithFileName>
-      <FilenameWithoutPath>heap_4.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
-  <Group>
-    <GroupName>Config</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>3</GroupNumber>
-      <FileNumber>14</FileNumber>
-      <FileType>5</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../Config/FreeRTOSConfig.h</PathWithFileName>
-      <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
-  <Group>
-    <GroupName>Demo</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>4</GroupNumber>
-      <FileNumber>15</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../Demo/app_main.c</PathWithFileName>
-      <FilenameWithoutPath>app_main.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>4</GroupNumber>
-      <FileNumber>16</FileNumber>
-      <FileType>5</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../Demo/app_main.h</PathWithFileName>
-      <FilenameWithoutPath>app_main.h</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>4</GroupNumber>
-      <FileNumber>17</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../Demo/mpu_demo.c</PathWithFileName>
-      <FilenameWithoutPath>mpu_demo.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>4</GroupNumber>
-      <FileNumber>18</FileNumber>
-      <FileType>5</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../Demo/mpu_demo.h</PathWithFileName>
-      <FilenameWithoutPath>mpu_demo.h</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
-  <Group>
-    <GroupName>Core</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>19</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Core/Src/main.c</PathWithFileName>
-      <FilenameWithoutPath>main.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>20</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Core/Src/stm32l4xx_it.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_it.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>21</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Core/Src/stm32l4xx_hal_msp.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_msp.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>22</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_timebase_tim.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
-  <Group>
-    <GroupName>Drivers/STM32L4xx_HAL_Driver</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>23</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_dfsdm.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>24</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_i2c.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>25</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_i2c_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>26</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_qspi.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>27</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_spi.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>28</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_spi_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>29</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_tim.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>30</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_tim_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>31</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_uart.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>32</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_uart_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>33</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_pcd.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>34</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_pcd_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>35</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_ll_usb.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>36</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>37</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_rcc.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>38</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_rcc_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>39</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_flash.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>40</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_flash_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>41</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_flash_ramfunc.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>42</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_gpio.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>43</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_dma.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>44</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_dma_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>45</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_pwr.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>46</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_pwr_ex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>47</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_cortex.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>48</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c</PathWithFileName>
-      <FilenameWithoutPath>stm32l4xx_hal_exti.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
-  <Group>
-    <GroupName>Drivers/CMSIS</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-    <File>
-      <GroupNumber>7</GroupNumber>
-      <FileNumber>49</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>../../ST_Code/Core/Src/system_stm32l4xx.c</PathWithFileName>
-      <FilenameWithoutPath>system_stm32l4xx.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
-  <Group>
-    <GroupName>::CMSIS</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>1</RteFlg>
-  </Group>
-
-</ProjectOpt>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvprojx
deleted file mode 100644 (file)
index b69de9d..0000000
+++ /dev/null
@@ -1,733 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
-
-  <SchemaVersion>2.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>MPUDemo</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
-      <uAC6>1</uAC6>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>STM32L475VGTx</Device>
-          <Vendor>STMicroelectronics</Vendor>
-          <PackID>Keil.STM32L4xx_DFP.2.2.0</PackID>
-          <PackURL>http://www.keil.com/pack</PackURL>
-          <Cpu>IRAM(0x20000000-0x20017FFF) IRAM2(0x10000000-0x10007FFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll></FlashDriverDll>
-          <DeviceId></DeviceId>
-          <RegisterFile></RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:STM32L475VGTx$CMSIS\SVD\STM32L4x5.svd</SFDFile>
-          <bCustSvd>0</bCustSvd>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath></RegisterFilePath>
-          <DBRegisterFilePath></DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>Debug\</OutputDirectory>
-          <OutputName>MPUDemo</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>1</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath></ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopB1X>0</nStopB1X>
-            <nStopB2X>0</nStopB2X>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopA1X>0</nStopA1X>
-            <nStopA2X>0</nStopA2X>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-          <ComprImg>0</ComprImg>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>-REMAP -MPU</SimDllArguments>
-          <SimDlgDll>DCM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments>-MPU</TargetDllArguments>
-          <TargetDlgDll>TCM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4107</DriverSelection>
-          </Flash1>
-          <bUseTDR>1</bUseTDR>
-          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
-          <Flash3></Flash3>
-          <Flash4></Flash4>
-          <pFcarmOut></pFcarmOut>
-          <pFcarmGrp></pFcarmGrp>
-          <pFcArmRoot></pFcArmRoot>
-          <FcArmLst>0</FcArmLst>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M4"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>2</RvdsVP>
-            <RvdsMve>0</RvdsMve>
-            <hadIRAM2>1</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <nSecure>0</nSecure>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x18000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x100000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x100000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x18000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x10000000</StartAddress>
-                <Size>0x8000</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>1</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>3</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <uC99>1</uC99>
-            <uGnu>0</uGnu>
-            <useXO>0</useXO>
-            <v6Lang>3</v6Lang>
-            <v6LangP>3</v6LangP>
-            <vShortEn>1</vShortEn>
-            <vShortWch>1</vShortWch>
-            <v6Lto>0</v6Lto>
-            <v6WtE>0</v6WtE>
-            <v6Rtti>0</v6Rtti>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define>USE_HAL_DRIVER,STM32L475xx</Define>
-              <Undefine></Undefine>
-              <IncludePath>../../ST_Code/Core/Inc;../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc;../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy;../../ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include;../../ST_Code/Drivers/CMSIS/Include;../../Config;../../Demo;../../../../Source/include;../../../../Source/portable/GCC/ARM_CM4_MPU</IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <useXO>0</useXO>
-            <uClangAs>0</uClangAs>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>0</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <pXoBase></pXoBase>
-            <ScatterFile>MPUDemo.sct</ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>Startup</GroupName>
-          <Files>
-            <File>
-              <FileName>startup_stm32l475xx.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>startup_stm32l475xx.s</FilePath>
-            </File>
-            <File>
-              <FileName>memfault_handler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\memfault_handler.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>FreeRTOS</GroupName>
-          <Files>
-            <File>
-              <FileName>croutine.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/croutine.c</FilePath>
-            </File>
-            <File>
-              <FileName>event_groups.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/event_groups.c</FilePath>
-            </File>
-            <File>
-              <FileName>list.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/list.c</FilePath>
-            </File>
-            <File>
-              <FileName>queue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/queue.c</FilePath>
-            </File>
-            <File>
-              <FileName>stream_buffer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/stream_buffer.c</FilePath>
-            </File>
-            <File>
-              <FileName>tasks.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/tasks.c</FilePath>
-            </File>
-            <File>
-              <FileName>timers.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/timers.c</FilePath>
-            </File>
-            <File>
-              <FileName>mpu_wrappers.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/portable/Common/mpu_wrappers.c</FilePath>
-            </File>
-            <File>
-              <FileName>port.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/portable/GCC/ARM_CM4_MPU/port.c</FilePath>
-            </File>
-            <File>
-              <FileName>portmacro.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>../../../../Source/portable/GCC/ARM_CM4_MPU/portmacro.h</FilePath>
-            </File>
-            <File>
-              <FileName>heap_4.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../Source/portable/MemMang/heap_4.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Config</GroupName>
-          <Files>
-            <File>
-              <FileName>FreeRTOSConfig.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>../../Config/FreeRTOSConfig.h</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Demo</GroupName>
-          <Files>
-            <File>
-              <FileName>app_main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../Demo/app_main.c</FilePath>
-            </File>
-            <File>
-              <FileName>app_main.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>../../Demo/app_main.h</FilePath>
-            </File>
-            <File>
-              <FileName>mpu_demo.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../Demo/mpu_demo.c</FilePath>
-            </File>
-            <File>
-              <FileName>mpu_demo.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>../../Demo/mpu_demo.h</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Core</GroupName>
-          <Files>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Core/Src/main.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Core/Src/stm32l4xx_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_msp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Core/Src/stm32l4xx_hal_msp.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_timebase_tim.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Drivers/STM32L4xx_HAL_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32l4xx_hal_dfsdm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_i2c_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_qspi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_spi_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_tim.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_tim_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_uart_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_pcd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_pcd_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_ll_usb.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c</FilePath>
-              <FileOption>
-                <CommonProperty>
-                  <UseCPPCompiler>2</UseCPPCompiler>
-                  <RVCTCodeConst>0</RVCTCodeConst>
-                  <RVCTZI>0</RVCTZI>
-                  <RVCTOtherData>0</RVCTOtherData>
-                  <ModuleSelection>0</ModuleSelection>
-                  <IncludeInBuild>2</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
-                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
-                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
-                  <PublicsOnly>2</PublicsOnly>
-                  <StopOnExitCode>11</StopOnExitCode>
-                  <CustomArgument></CustomArgument>
-                  <IncludeLibraryModules></IncludeLibraryModules>
-                  <ComprImg>1</ComprImg>
-                </CommonProperty>
-                <FileArmAds>
-                  <Cads>
-                    <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
-                    <Ropi>2</Ropi>
-                    <Rwpi>2</Rwpi>
-                    <wLevel>1</wLevel>
-                    <uThumb>2</uThumb>
-                    <uSurpInc>2</uSurpInc>
-                    <uC99>2</uC99>
-                    <uGnu>2</uGnu>
-                    <useXO>2</useXO>
-                    <v6Lang>0</v6Lang>
-                    <v6LangP>0</v6LangP>
-                    <vShortEn>2</vShortEn>
-                    <vShortWch>2</vShortWch>
-                    <v6Lto>2</v6Lto>
-                    <v6WtE>2</v6WtE>
-                    <v6Rtti>2</v6Rtti>
-                    <VariousControls>
-                      <MiscControls></MiscControls>
-                      <Define></Define>
-                      <Undefine></Undefine>
-                      <IncludePath></IncludePath>
-                    </VariousControls>
-                  </Cads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_rcc_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_flash_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_flash_ramfunc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_dma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_dma_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_pwr.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_pwr_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_cortex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32l4xx_hal_exti.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Drivers/CMSIS</GroupName>
-          <Files>
-            <File>
-              <FileName>system_stm32l4xx.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../ST_Code/Core/Src/system_stm32l4xx.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>::CMSIS</GroupName>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-  <RTE>
-    <apis/>
-    <components>
-      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
-        <targetInfos>
-          <targetInfo name="MPUDemo"/>
-        </targetInfos>
-      </component>
-    </components>
-    <files/>
-  </RTE>
-
-</Project>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/memfault_handler.c
deleted file mode 100644 (file)
index 59efcd7..0000000
+++ /dev/null
@@ -1,69 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-#include <stdint.h>\r
-\r
-extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base;\r
-extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit;\r
-\r
-/* Memory map needed for MPU setup. Must must match the one defined in\r
- * the scatter-loading file (MPUDemo.sct). */\r
-const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x08000000;\r
-const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x08100000;\r
-const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000;\r
-const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20018000;\r
-\r
-const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x08000000;\r
-const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x08008000;\r
-const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000;\r
-const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20000400;\r
-\r
-const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base );\r
-const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit );\r
-/*-----------------------------------------------------------*/\r
-\r
-/**\r
- * @brief Mem fault handler.\r
- */\r
-void MemManage_Handler( void ) __attribute__ (( naked ));\r
-/*-----------------------------------------------------------*/\r
-\r
-void MemManage_Handler( void )\r
-{\r
-       __asm volatile\r
-       (\r
-               " tst lr, #4                                                                            \n"\r
-               " ite eq                                                                                        \n"\r
-               " mrseq r0, msp                                                                         \n"\r
-               " mrsne r0, psp                                                                         \n"\r
-               " ldr r1, handler_address_const                                         \n"\r
-               " bx r1                                                                                         \n"\r
-               "                                                                                                       \n"\r
-               " handler_address_const: .word vHandleMemoryFault       \n"\r
-       );\r
-}\r
-/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/startup_stm32l475xx.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/startup_stm32l475xx.s
deleted file mode 100644 (file)
index 18a4ee1..0000000
+++ /dev/null
@@ -1,435 +0,0 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************\r
-;* File Name          : startup_stm32l475xx.s\r
-;* Author             : MCD Application Team\r
-;* Description        : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain.\r
-;*                      This module performs:\r
-;*                      - Set the initial SP\r
-;*                      - Set the initial PC == Reset_Handler\r
-;*                      - Set the vector table entries with the exceptions ISR address\r
-;*                      - Branches to __main in the C library (which eventually\r
-;*                        calls main()).\r
-;*                      After Reset the Cortex-M4 processor is in Thread mode,\r
-;*                      priority is Privileged, and the Stack is set to Main.\r
-;* <<< Use Configuration Wizard in Context Menu >>>\r
-;*******************************************************************************\r
-;*\r
-;* Redistribution and use in source and binary forms, with or without modification,\r
-;* are permitted provided that the following conditions are met:\r
-;*   1. Redistributions of source code must retain the above copyright notice,\r
-;*      this list of conditions and the following disclaimer.\r
-;*   2. Redistributions in binary form must reproduce the above copyright notice,\r
-;*      this list of conditions and the following disclaimer in the documentation\r
-;*      and/or other materials provided with the distribution.\r
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-;*      may be used to endorse or promote products derived from this software\r
-;*      without specific prior written permission.\r
-;*\r
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-;*\r
-;*******************************************************************************\r
-;\r
-; Amount of memory (in bytes) allocated for Stack\r
-; Tailor this value to your application needs\r
-; <h> Stack Configuration\r
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Stack_Size             EQU     0x400\r
-\r
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
-Stack_Mem       SPACE   Stack_Size\r
-__initial_sp\r
-\r
-\r
-; <h> Heap Configuration\r
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Heap_Size      EQU     0x200\r
-\r
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
-__heap_base\r
-Heap_Mem        SPACE   Heap_Size\r
-__heap_limit\r
-\r
-                PRESERVE8\r
-                THUMB\r
-\r
-\r
-; Vector Table Mapped to Address 0 at Reset\r
-                AREA    RESET, DATA, READONLY\r
-                EXPORT  __Vectors\r
-                EXPORT  __Vectors_End\r
-                EXPORT  __Vectors_Size\r
-\r
-__Vectors       DCD     __initial_sp               ; Top of Stack\r
-                DCD     Reset_Handler              ; Reset Handler\r
-                DCD     NMI_Handler                ; NMI Handler\r
-                DCD     HardFault_Handler          ; Hard Fault Handler\r
-                DCD     MemManage_Handler          ; MPU Fault Handler\r
-                DCD     BusFault_Handler           ; Bus Fault Handler\r
-                DCD     UsageFault_Handler         ; Usage Fault Handler\r
-                DCD     0                          ; Reserved\r
-                DCD     0                          ; Reserved\r
-                DCD     0                          ; Reserved\r
-                DCD     0                          ; Reserved\r
-                DCD     SVC_Handler                ; SVCall Handler\r
-                DCD     DebugMon_Handler           ; Debug Monitor Handler\r
-                DCD     0                          ; Reserved\r
-                DCD     PendSV_Handler             ; PendSV Handler\r
-                DCD     SysTick_Handler            ; SysTick Handler\r
-\r
-                ; External Interrupts\r
-                DCD     WWDG_IRQHandler                   ; Window WatchDog\r
-                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection\r
-                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line\r
-                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line\r
-                DCD     FLASH_IRQHandler                  ; FLASH\r
-                DCD     RCC_IRQHandler                    ; RCC\r
-                DCD     EXTI0_IRQHandler                  ; EXTI Line0\r
-                DCD     EXTI1_IRQHandler                  ; EXTI Line1\r
-                DCD     EXTI2_IRQHandler                  ; EXTI Line2\r
-                DCD     EXTI3_IRQHandler                  ; EXTI Line3\r
-                DCD     EXTI4_IRQHandler                  ; EXTI Line4\r
-                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1\r
-                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2\r
-                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3\r
-                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4\r
-                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5\r
-                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6\r
-                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7\r
-                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2\r
-                DCD     CAN1_TX_IRQHandler                ; CAN1 TX\r
-                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0\r
-                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1\r
-                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE\r
-                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s\r
-                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15\r
-                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16\r
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17\r
-                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare\r
-                DCD     TIM2_IRQHandler                   ; TIM2\r
-                DCD     TIM3_IRQHandler                   ; TIM3\r
-                DCD     TIM4_IRQHandler                   ; TIM4\r
-                DCD     I2C1_EV_IRQHandler                ; I2C1 Event\r
-                DCD     I2C1_ER_IRQHandler                ; I2C1 Error\r
-                DCD     I2C2_EV_IRQHandler                ; I2C2 Event\r
-                DCD     I2C2_ER_IRQHandler                ; I2C2 Error\r
-                DCD     SPI1_IRQHandler                   ; SPI1\r
-                DCD     SPI2_IRQHandler                   ; SPI2\r
-                DCD     USART1_IRQHandler                 ; USART1\r
-                DCD     USART2_IRQHandler                 ; USART2\r
-                DCD     USART3_IRQHandler                 ; USART3\r
-                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]\r
-                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line\r
-                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt\r
-                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt\r
-                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt\r
-                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt\r
-                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt\r
-                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt\r
-                DCD     FMC_IRQHandler                    ; FMC\r
-                DCD     SDMMC1_IRQHandler                 ; SDMMC1\r
-                DCD     TIM5_IRQHandler                   ; TIM5\r
-                DCD     SPI3_IRQHandler                   ; SPI3\r
-                DCD     UART4_IRQHandler                  ; UART4\r
-                DCD     UART5_IRQHandler                  ; UART5\r
-                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors\r
-                DCD     TIM7_IRQHandler                   ; TIM7\r
-                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1\r
-                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2\r
-                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3\r
-                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4\r
-                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5\r
-                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt\r
-                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt\r
-                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt\r
-                DCD     COMP_IRQHandler                   ; COMP Interrupt\r
-                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt\r
-                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt\r
-                DCD     OTG_FS_IRQHandler                 ; USB OTG FS\r
-                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6\r
-                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7\r
-                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt\r
-                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt\r
-                DCD     I2C3_EV_IRQHandler                ; I2C3 event\r
-                DCD     I2C3_ER_IRQHandler                ; I2C3 error\r
-                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt\r
-                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt\r
-                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt\r
-                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt\r
-                DCD     0                                 ; Reserved                \r
-                DCD     0                                 ; Reserved                \r
-                DCD     RNG_IRQHandler                    ; RNG global interrupt\r
-                DCD     FPU_IRQHandler                    ; FPU\r
-\r
-__Vectors_End\r
-\r
-__Vectors_Size  EQU  __Vectors_End - __Vectors\r
-\r
-                AREA    |.text|, CODE, READONLY\r
-\r
-; Reset handler\r
-Reset_Handler    PROC\r
-                 EXPORT  Reset_Handler             [WEAK]\r
-        IMPORT  SystemInit\r
-        IMPORT  __main\r
-\r
-                 LDR     R0, =SystemInit\r
-                 BLX     R0\r
-                 LDR     R0, =__main\r
-                 BX      R0\r
-                 ENDP\r
-\r
-; Dummy Exception Handlers (infinite loops which can be modified)\r
-\r
-NMI_Handler     PROC\r
-                EXPORT  NMI_Handler                [WEAK]\r
-                B       .\r
-                ENDP\r
-HardFault_Handler\\r
-                PROC\r
-                EXPORT  HardFault_Handler          [WEAK]\r
-                B       .\r
-                ENDP\r
-MemManage_Handler\\r
-                PROC\r
-                EXPORT  MemManage_Handler          [WEAK]\r
-                B       .\r
-                ENDP\r
-BusFault_Handler\\r
-                PROC\r
-                EXPORT  BusFault_Handler           [WEAK]\r
-                B       .\r
-                ENDP\r
-UsageFault_Handler\\r
-                PROC\r
-                EXPORT  UsageFault_Handler         [WEAK]\r
-                B       .\r
-                ENDP\r
-SVC_Handler     PROC\r
-                EXPORT  SVC_Handler                [WEAK]\r
-                B       .\r
-                ENDP\r
-DebugMon_Handler\\r
-                PROC\r
-                EXPORT  DebugMon_Handler           [WEAK]\r
-                B       .\r
-                ENDP\r
-PendSV_Handler  PROC\r
-                EXPORT  PendSV_Handler             [WEAK]\r
-                B       .\r
-                ENDP\r
-SysTick_Handler PROC\r
-                EXPORT  SysTick_Handler            [WEAK]\r
-                B       .\r
-                ENDP\r
-\r
-Default_Handler PROC\r
-\r
-        EXPORT     WWDG_IRQHandler                   [WEAK]\r
-        EXPORT     PVD_PVM_IRQHandler                [WEAK]\r
-        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]\r
-        EXPORT     RTC_WKUP_IRQHandler               [WEAK]\r
-        EXPORT     FLASH_IRQHandler                  [WEAK]\r
-        EXPORT     RCC_IRQHandler                    [WEAK]\r
-        EXPORT     EXTI0_IRQHandler                  [WEAK]\r
-        EXPORT     EXTI1_IRQHandler                  [WEAK]\r
-        EXPORT     EXTI2_IRQHandler                  [WEAK]\r
-        EXPORT     EXTI3_IRQHandler                  [WEAK]\r
-        EXPORT     EXTI4_IRQHandler                  [WEAK]\r
-        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]\r
-        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]\r
-        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]\r
-        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]\r
-        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]\r
-        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]\r
-        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]\r
-        EXPORT     ADC1_2_IRQHandler                 [WEAK]\r
-        EXPORT     CAN1_TX_IRQHandler                [WEAK]\r
-        EXPORT     CAN1_RX0_IRQHandler               [WEAK]\r
-        EXPORT     CAN1_RX1_IRQHandler               [WEAK]\r
-        EXPORT     CAN1_SCE_IRQHandler               [WEAK]\r
-        EXPORT     EXTI9_5_IRQHandler                [WEAK]\r
-        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]\r
-        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]\r
-        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]\r
-        EXPORT     TIM1_CC_IRQHandler                [WEAK]\r
-        EXPORT     TIM2_IRQHandler                   [WEAK]\r
-        EXPORT     TIM3_IRQHandler                   [WEAK]\r
-        EXPORT     TIM4_IRQHandler                   [WEAK]\r
-        EXPORT     I2C1_EV_IRQHandler                [WEAK]\r
-        EXPORT     I2C1_ER_IRQHandler                [WEAK]\r
-        EXPORT     I2C2_EV_IRQHandler                [WEAK]\r
-        EXPORT     I2C2_ER_IRQHandler                [WEAK]\r
-        EXPORT     SPI1_IRQHandler                   [WEAK]\r
-        EXPORT     SPI2_IRQHandler                   [WEAK]\r
-        EXPORT     USART1_IRQHandler                 [WEAK]\r
-        EXPORT     USART2_IRQHandler                 [WEAK]\r
-        EXPORT     USART3_IRQHandler                 [WEAK]\r
-        EXPORT     EXTI15_10_IRQHandler              [WEAK]\r
-        EXPORT     RTC_Alarm_IRQHandler              [WEAK]\r
-        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]\r
-        EXPORT     TIM8_BRK_IRQHandler               [WEAK]\r
-        EXPORT     TIM8_UP_IRQHandler                [WEAK]\r
-        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]\r
-        EXPORT     TIM8_CC_IRQHandler                [WEAK]\r
-        EXPORT     ADC3_IRQHandler                   [WEAK]\r
-        EXPORT     FMC_IRQHandler                    [WEAK]\r
-        EXPORT     SDMMC1_IRQHandler                 [WEAK]\r
-        EXPORT     TIM5_IRQHandler                   [WEAK]\r
-        EXPORT     SPI3_IRQHandler                   [WEAK]\r
-        EXPORT     UART4_IRQHandler                  [WEAK]\r
-        EXPORT     UART5_IRQHandler                  [WEAK]\r
-        EXPORT     TIM6_DAC_IRQHandler               [WEAK]\r
-        EXPORT     TIM7_IRQHandler                   [WEAK]\r
-        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]\r
-        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]\r
-        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]\r
-        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]\r
-        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]\r
-        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]\r
-        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]\r
-        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]\r
-        EXPORT     COMP_IRQHandler                   [WEAK]\r
-        EXPORT     LPTIM1_IRQHandler                 [WEAK]\r
-        EXPORT     LPTIM2_IRQHandler                 [WEAK]\r
-        EXPORT     OTG_FS_IRQHandler                 [WEAK]\r
-        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]\r
-        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]\r
-        EXPORT     LPUART1_IRQHandler                [WEAK]\r
-        EXPORT     QUADSPI_IRQHandler                [WEAK]\r
-        EXPORT     I2C3_EV_IRQHandler                [WEAK]\r
-        EXPORT     I2C3_ER_IRQHandler                [WEAK]\r
-        EXPORT     SAI1_IRQHandler                   [WEAK]\r
-        EXPORT     SAI2_IRQHandler                   [WEAK]\r
-        EXPORT     SWPMI1_IRQHandler                 [WEAK]\r
-        EXPORT     TSC_IRQHandler                    [WEAK]\r
-        EXPORT     RNG_IRQHandler                    [WEAK]\r
-        EXPORT     FPU_IRQHandler                    [WEAK]\r
-\r
-WWDG_IRQHandler\r
-PVD_PVM_IRQHandler\r
-TAMP_STAMP_IRQHandler\r
-RTC_WKUP_IRQHandler\r
-FLASH_IRQHandler\r
-RCC_IRQHandler\r
-EXTI0_IRQHandler\r
-EXTI1_IRQHandler\r
-EXTI2_IRQHandler\r
-EXTI3_IRQHandler\r
-EXTI4_IRQHandler\r
-DMA1_Channel1_IRQHandler\r
-DMA1_Channel2_IRQHandler\r
-DMA1_Channel3_IRQHandler\r
-DMA1_Channel4_IRQHandler\r
-DMA1_Channel5_IRQHandler\r
-DMA1_Channel6_IRQHandler\r
-DMA1_Channel7_IRQHandler\r
-ADC1_2_IRQHandler\r
-CAN1_TX_IRQHandler\r
-CAN1_RX0_IRQHandler\r
-CAN1_RX1_IRQHandler\r
-CAN1_SCE_IRQHandler\r
-EXTI9_5_IRQHandler\r
-TIM1_BRK_TIM15_IRQHandler\r
-TIM1_UP_TIM16_IRQHandler\r
-TIM1_TRG_COM_TIM17_IRQHandler\r
-TIM1_CC_IRQHandler\r
-TIM2_IRQHandler\r
-TIM3_IRQHandler\r
-TIM4_IRQHandler\r
-I2C1_EV_IRQHandler\r
-I2C1_ER_IRQHandler\r
-I2C2_EV_IRQHandler\r
-I2C2_ER_IRQHandler\r
-SPI1_IRQHandler\r
-SPI2_IRQHandler\r
-USART1_IRQHandler\r
-USART2_IRQHandler\r
-USART3_IRQHandler\r
-EXTI15_10_IRQHandler\r
-RTC_Alarm_IRQHandler\r
-DFSDM1_FLT3_IRQHandler\r
-TIM8_BRK_IRQHandler\r
-TIM8_UP_IRQHandler\r
-TIM8_TRG_COM_IRQHandler\r
-TIM8_CC_IRQHandler\r
-ADC3_IRQHandler\r
-FMC_IRQHandler\r
-SDMMC1_IRQHandler\r
-TIM5_IRQHandler\r
-SPI3_IRQHandler\r
-UART4_IRQHandler\r
-UART5_IRQHandler\r
-TIM6_DAC_IRQHandler\r
-TIM7_IRQHandler\r
-DMA2_Channel1_IRQHandler\r
-DMA2_Channel2_IRQHandler\r
-DMA2_Channel3_IRQHandler\r
-DMA2_Channel4_IRQHandler\r
-DMA2_Channel5_IRQHandler\r
-DFSDM1_FLT0_IRQHandler\r
-DFSDM1_FLT1_IRQHandler\r
-DFSDM1_FLT2_IRQHandler\r
-COMP_IRQHandler\r
-LPTIM1_IRQHandler\r
-LPTIM2_IRQHandler\r
-OTG_FS_IRQHandler\r
-DMA2_Channel6_IRQHandler\r
-DMA2_Channel7_IRQHandler\r
-LPUART1_IRQHandler\r
-QUADSPI_IRQHandler\r
-I2C3_EV_IRQHandler\r
-I2C3_ER_IRQHandler\r
-SAI1_IRQHandler\r
-SAI2_IRQHandler\r
-SWPMI1_IRQHandler\r
-TSC_IRQHandler\r
-RNG_IRQHandler\r
-FPU_IRQHandler\r
-\r
-                B       .\r
-\r
-                ENDP\r
-\r
-                ALIGN\r
-\r
-;*******************************************************************************\r
-; User Stack and Heap initialization\r
-;*******************************************************************************\r
-                 IF      :DEF:__MICROLIB\r
-\r
-                 EXPORT  __initial_sp\r
-                 EXPORT  __heap_base\r
-                 EXPORT  __heap_limit\r
-\r
-                 ELSE\r
-\r
-                 IMPORT  __use_two_region_memory\r
-                 EXPORT  __user_initial_stackheap\r
-\r
-__user_initial_stackheap\r
-\r
-                 LDR     R0, =  Heap_Mem\r
-                 LDR     R1, =(Stack_Mem + Stack_Size)\r
-                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
-                 LDR     R3, = Stack_Mem\r
-                 BX      LR\r
-\r
-                 ALIGN\r
-\r
-                 ENDIF\r
-\r
-                 END\r
-\r
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/.cproject b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/.cproject
deleted file mode 100644 (file)
index 7b75704..0000000
+++ /dev/null
@@ -1,218 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
-       <storageModule moduleId="org.eclipse.cdt.core.settings">\r
-               <cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567">\r
-                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567" moduleId="org.eclipse.cdt.core.settings" name="Debug">\r
-                               <externalSettings/>\r
-                               <extensions>\r
-                                       <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                               </extensions>\r
-                       </storageModule>\r
-                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
-                               <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">\r
-                                       <folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567." name="/" resourcePath="">\r
-                                               <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.151851129" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">\r
-                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1653744095" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1681944964" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.8945483" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32L475VGTx" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1577664432" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1898127558" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.2108997886" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.2001329861" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1091286848" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="B-L475E-IOT01A1" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1037532678" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || B-L475E-IOT01A1 || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/CMSIS/Device/ST/STM32L4xx/Include | ../Drivers/STM32L4xx_HAL_Driver/Inc | ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy ||  ||  || USE_HAL_DRIVER | STM32L475xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>\r
-                                                       <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.426124029" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>\r
-                                                       <builder buildPath="${workspace_loc:/MPUDemo}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.2128934708" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.593503556" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1563011769" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>\r
-                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1415168970" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1478257368" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1219427263" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1995035483" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>\r
-                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.894694479" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">\r
-                                                                       <listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>\r
-                                                                       <listOptionValue builtIn="false" value="DEBUG"/>\r
-                                                                       <listOptionValue builtIn="false" value="STM32L475xx"/>\r
-                                                               </option>\r
-                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1719315783" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">\r
-                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/CMSIS/Include"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Core/Inc"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../Config"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../Demo"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../../../Source/include"/>\r
-                                                                       <listOptionValue builtIn="false" value="../../../../../Source/portable/GCC/ARM_CM4_MPU"/>\r
-                                                               </option>\r
-                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1633770288" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.427031050" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.308658656" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1955283688" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.909277324" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1282618698" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
-                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.422722354" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">\r
-                                                                       <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
-                                                                       <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
-                                                               </inputType>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.422475117" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.1092153668" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1299869734" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.2094239253" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1582287773" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.670067362" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1387142483" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1905141019" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.475038865" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1528425390" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>\r
-                                               </toolChain>\r
-                                       </folderInfo>\r
-                                       <folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567.19817946" name="/" resourcePath="Startup">\r
-                                               <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1794512592" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug" unusedChildren="">\r
-                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1653744095.169975929" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1653744095"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1681944964.946377599" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1681944964"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.8945483.262684702" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.8945483"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1577664432.427235401" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1577664432"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1898127558.560835881" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1898127558"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.2108997886.140706480" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.2108997886"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.2001329861.1331183223" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.2001329861"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1091286848.1020682886" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1091286848"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1037532678.1618834064" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1037532678"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.692231107" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.593503556"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.245264136" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1478257368"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.763839302" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.427031050"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.2022161589" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.909277324"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.778888425" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.422475117"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.728912733" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1299869734"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1521916125" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.2094239253"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.171635900" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1582287773"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.510896173" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.670067362"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1631939929" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1387142483"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1716690007" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1905141019"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.302624683" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.475038865"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1335461923" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1528425390"/>\r
-                                               </toolChain>\r
-                                       </folderInfo>\r
-                                       <sourceEntries>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Config"/>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Demo"/>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FreeRTOS"/>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>\r
-                                       </sourceEntries>\r
-                               </configuration>\r
-                       </storageModule>\r
-                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
-               </cconfiguration>\r
-               <cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181">\r
-                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181" moduleId="org.eclipse.cdt.core.settings" name="Release">\r
-                               <externalSettings/>\r
-                               <extensions>\r
-                                       <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
-                               </extensions>\r
-                       </storageModule>\r
-                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
-                               <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">\r
-                                       <folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181." name="/" resourcePath="">\r
-                                               <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1940388223" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">\r
-                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1164105596" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.969849987" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1143746181" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32L475VGTx" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1546095951" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.990303221" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.1809067860" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1254746839" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.204372413" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="B-L475E-IOT01A1" valueType="string"/>\r
-                                                       <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1344132037" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || B-L475E-IOT01A1 || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/CMSIS/Device/ST/STM32L4xx/Include | ../Drivers/STM32L4xx_HAL_Driver/Inc | ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy ||  ||  || USE_HAL_DRIVER | STM32L475xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>\r
-                                                       <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.605687567" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>\r
-                                                       <builder buildPath="${workspace_loc:/MPUDemo}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.924159257" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1457338997" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.625237364" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>\r
-                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.2042536896" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.236149066" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.883085407" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.895688238" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.o3" valueType="enumerated"/>\r
-                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1094376630" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">\r
-                                                                       <listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>\r
-                                                                       <listOptionValue builtIn="false" value="STM32L475xx"/>\r
-                                                               </option>\r
-                                                               <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1390012251" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">\r
-                                                                       <listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>\r
-                                                                       <listOptionValue builtIn="false" value="../Core/Inc"/>\r
-                                                                       <listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L4xx/Include"/>\r
-                                                                       <listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc"/>\r
-                                                                       <listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy"/>\r
-                                                               </option>\r
-                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.879588113" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1264350081" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.441749113" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.214554399" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.o3" valueType="enumerated"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.799737946" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1204679986" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
-                                                               <inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.346247509" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">\r
-                                                                       <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
-                                                                       <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
-                                                               </inputType>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.504797300" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">\r
-                                                               <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.351476792" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L475VGTX_FLASH.ld}" valueType="string"/>\r
-                                                       </tool>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1580405798" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1682675601" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1606608792" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1519571618" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.516527531" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1259742608" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1453134435" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>\r
-                                                       <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1610429959" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>\r
-                                               </toolChain>\r
-                                       </folderInfo>\r
-                                       <sourceEntries>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>\r
-                                               <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>\r
-                                       </sourceEntries>\r
-                               </configuration>\r
-                       </storageModule>\r
-                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
-               </cconfiguration>\r
-       </storageModule>\r
-       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
-               <project id="MPUDemo.null.551361165" name="MPUDemo"/>\r
-       </storageModule>\r
-       <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>\r
-       <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>\r
-       <storageModule moduleId="scannerConfiguration">\r
-               <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
-               <scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.946769567.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1478257368;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1633770288">\r
-                       <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>\r
-               </scannerConfigBuildInfo>\r
-               <scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.132882181.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.236149066;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.879588113">\r
-                       <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>\r
-               </scannerConfigBuildInfo>\r
-       </storageModule>\r
-       <storageModule moduleId="refreshScope" versionNumber="2">\r
-               <configuration configurationName="Debug">\r
-                       <resource resourceType="PROJECT" workspacePath="/MPUDemo"/>\r
-               </configuration>\r
-               <configuration configurationName="Release">\r
-                       <resource resourceType="PROJECT" workspacePath="/MPUDemo"/>\r
-               </configuration>\r
-       </storageModule>\r
-</cproject>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/.project b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/.project
deleted file mode 100644 (file)
index 6f28b16..0000000
+++ /dev/null
@@ -1,107 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>\r
-<projectDescription>\r
-       <name>MPUDemo</name>\r
-       <comment></comment>\r
-       <projects>\r
-       </projects>\r
-       <buildSpec>\r
-               <buildCommand>\r
-                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
-                       <triggers>clean,full,incremental,</triggers>\r
-                       <arguments>\r
-                       </arguments>\r
-               </buildCommand>\r
-               <buildCommand>\r
-                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
-                       <triggers>full,incremental,</triggers>\r
-                       <arguments>\r
-                       </arguments>\r
-               </buildCommand>\r
-       </buildSpec>\r
-       <natures>\r
-               <nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>\r
-               <nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>\r
-               <nature>org.eclipse.cdt.core.cnature</nature>\r
-               <nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature</nature>\r
-               <nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>\r
-               <nature>com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature</nature>\r
-               <nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>\r
-               <nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>\r
-               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
-               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
-       </natures>\r
-       <linkedResources>\r
-               <link>\r
-                       <name>Config</name>\r
-                       <type>2</type>\r
-                       <locationURI>PARENT-2-PROJECT_LOC/Config</locationURI>\r
-               </link>\r
-               <link>\r
-                       <name>Core</name>\r
-                       <type>2</type>\r
-                       <locationURI>PARENT-2-PROJECT_LOC/ST_Code/Core</locationURI>\r
-               </link>\r
-               <link>\r
-                       <name>Demo</name>\r
-                       <type>2</type>\r
-                       <locationURI>PARENT-2-PROJECT_LOC/Demo</locationURI>\r
-               </link>\r
-               <link>\r
-                       <name>Drivers</name>\r
-                       <type>2</type>\r
-                       <locationURI>PARENT-2-PROJECT_LOC/ST_Code/Drivers</locationURI>\r
-               </link>\r
-               <link>\r
-                       <name>FreeRTOS</name>\r
-                       <type>2</type>\r
-                       <locationURI>PARENT-4-PROJECT_LOC/Source</locationURI>\r
-               </link>\r
-       </linkedResources>\r
-       <filteredResources>\r
-               <filter>\r
-                       <id>1576807148309</id>\r
-                       <name>FreeRTOS/portable</name>\r
-                       <type>9</type>\r
-                       <matcher>\r
-                               <id>org.eclipse.ui.ide.multiFilter</id>\r
-                               <arguments>1.0-name-matches-false-false-GCC</arguments>\r
-                       </matcher>\r
-               </filter>\r
-               <filter>\r
-                       <id>1576807148309</id>\r
-                       <name>FreeRTOS/portable</name>\r
-                       <type>9</type>\r
-                       <matcher>\r
-                               <id>org.eclipse.ui.ide.multiFilter</id>\r
-                               <arguments>1.0-name-matches-false-false-MemMang</arguments>\r
-                       </matcher>\r
-               </filter>\r
-               <filter>\r
-                       <id>1576807148325</id>\r
-                       <name>FreeRTOS/portable</name>\r
-                       <type>9</type>\r
-                       <matcher>\r
-                               <id>org.eclipse.ui.ide.multiFilter</id>\r
-                               <arguments>1.0-name-matches-false-false-Common</arguments>\r
-                       </matcher>\r
-               </filter>\r
-               <filter>\r
-                       <id>1576807182461</id>\r
-                       <name>FreeRTOS/portable/GCC</name>\r
-                       <type>9</type>\r
-                       <matcher>\r
-                               <id>org.eclipse.ui.ide.multiFilter</id>\r
-                               <arguments>1.0-name-matches-false-false-ARM_CM4_MPU</arguments>\r
-                       </matcher>\r
-               </filter>\r
-               <filter>\r
-                       <id>1576807232013</id>\r
-                       <name>FreeRTOS/portable/MemMang</name>\r
-                       <type>5</type>\r
-                       <matcher>\r
-                               <id>org.eclipse.ui.ide.multiFilter</id>\r
-                               <arguments>1.0-name-matches-false-false-heap_4.c</arguments>\r
-                       </matcher>\r
-               </filter>\r
-       </filteredResources>\r
-</projectDescription>\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/STM32L475VGTX_FLASH.ld b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/STM32L475VGTX_FLASH.ld
deleted file mode 100644 (file)
index 6d41308..0000000
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
-******************************************************************************
-**
-**  File        : LinkerScript.ld
-**
-**  Author             : Auto-generated by STM32CubeIDE
-**
-**  Abstract    : Linker script for B-L475E-IOT01A1 Board embedding STM32L475VGTx Device from STM32L4 series
-**                      1024Kbytes FLASH
-**                      96Kbytes RAM
-**                      32Kbytes RAM2
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Distribution: The file is distributed as is without any warranty
-**                of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + LENGTH(RAM);   /* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200 ;       /* required amount of heap  */
-_Min_Stack_Size = 0x400 ;      /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  RAM  (xrw)   : ORIGIN = 0x20000000,  LENGTH = 96K
-  RAM2 (xrw)   : ORIGIN = 0x10000000,  LENGTH = 32K
-  FLASH        (rx)    : ORIGIN = 0x8000000,   LENGTH = 1024K
-}
-
-/* Initial 32K Flash is used to store kernel functions and
- * initial 512 bytes of RAM is used to store kernel data. */
-__privileged_functions_region_size__  = 32K;
-__privileged_data_region_size__       = 512;
-
-__FLASH_segment_start__               = ORIGIN( FLASH );
-__FLASH_segment_end__                 = __FLASH_segment_start__ + LENGTH( FLASH );
-
-__SRAM_segment_start__                = ORIGIN( RAM );
-__SRAM_segment_end__                  = __SRAM_segment_start__ + LENGTH( RAM );
-
-__privileged_functions_start__        = __FLASH_segment_start__;
-__privileged_functions_end__          = __FLASH_segment_start__ + __privileged_functions_region_size__;
-
-__privileged_data_start__             = __SRAM_segment_start__;
-__privileged_data_end__               = __SRAM_segment_start__ + __privileged_data_region_size__;
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code and FreeRTOS kernel code are placed into privileged
-   * flash. */
-  .privileged_functions :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code. */
-    . = ALIGN(4);
-    *(privileged_functions)
-    . = ALIGN(4);
-    FILL(0xDEAD);
-    /* Ensure that non-privileged code is placed after the region reserved for
-     * privileged kernel code. */
-    /* Note that dot (.) actually refers to the byte offset from the start of
-     * the current section (.privileged_functions in this case). As a result,
-     * setting dot (.) to a value sets the size of the section. */
-    . = __privileged_functions_region_size__;
-  } >FLASH
-
-  /* The program code and other data into "FLASH" Rom type memory */
-  .text :
-  {
-    /* Place the FreeRTOS System Calls first in the unprivileged region. */
-    . = ALIGN(4);
-    __syscalls_flash_start__ = .;
-    *(freertos_system_calls)
-    __syscalls_flash_end__ = .;
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data into "FLASH" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : {
-    . = ALIGN(4);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM : {
-    . = ALIGN(4);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(4);
-  } >FLASH
-
-  .preinit_array     :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-
-  .init_array :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-
-  .fini_array :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.privileged_data);
-
-  /* FreeRTOS kernel data. */
-  .privileged_data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* Create a global symbol at data start. */
-    *(privileged_data)
-    . = ALIGN(4);
-    FILL(0xDEAD);
-    /* Ensure that non-privileged data is placed after the region reserved for
-     * privileged kernel data. */
-    /* Note that dot (.) actually refers to the byte offset from the start of
-     * the current section (.privileged_data in this case). As a result, setting
-     * dot (.) to a value sets the size of the section. */
-    . = __privileged_data_region_size__;
-  } >RAM AT> FLASH
-
-  /* Initialized data sections into "RAM" Ram type memory */
-  .data :
-  {
-    . = ALIGN(4);
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section into "RAM" Ram type memory */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/memfault_handler.c
deleted file mode 100644 (file)
index f0e1b92..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/**\r
- * @brief Mem fault handler.\r
- */\r
-void MemManage_Handler( void ) __attribute__ (( naked ));\r
-/*-----------------------------------------------------------*/\r
-\r
-void MemManage_Handler( void )\r
-{\r
-       __asm volatile\r
-       (\r
-               " tst lr, #4                                                                            \n"\r
-               " ite eq                                                                                        \n"\r
-               " mrseq r0, msp                                                                         \n"\r
-               " mrsne r0, psp                                                                         \n"\r
-               " ldr r1, handler_address_const                                         \n"\r
-               " bx r1                                                                                         \n"\r
-               "                                                                                                       \n"\r
-               " handler_address_const: .word vHandleMemoryFault       \n"\r
-       );\r
-}\r
-/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/startup_stm32l475vgtx.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/startup_stm32l475vgtx.s
deleted file mode 100644 (file)
index 9e2b0ff..0000000
+++ /dev/null
@@ -1,505 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file      startup_stm32l475xx.s\r
-  * @author    MCD Application Team\r
-  * @brief     STM32L475xx devices vector table for GCC toolchain.\r
-  *            This module performs:\r
-  *                - Set the initial SP\r
-  *                - Set the initial PC == Reset_Handler,\r
-  *                - Set the vector table entries with the exceptions ISR address,\r
-  *                - Configure the clock system  \r
-  *                - Branches to main in the C library (which eventually\r
-  *                  calls main()).\r
-  *            After Reset the Cortex-M4 processor is in Thread mode,\r
-  *            priority is Privileged, and the Stack is set to Main.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-  .syntax unified\r
-       .cpu cortex-m4\r
-       .fpu softvfp\r
-       .thumb\r
-\r
-.global        g_pfnVectors\r
-.global        Default_Handler\r
-\r
-/* start address for the initialization values of the .data section.\r
-defined in linker script */\r
-.word  _sidata\r
-/* start address for the .data section. defined in linker script */\r
-.word  _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word  _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word  _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word  _ebss\r
-\r
-.equ  BootRAM,        0xF1E0F85F\r
-/**\r
- * @brief  This is the code that gets called when the processor first\r
- *          starts execution following a reset event. Only the absolutely\r
- *          necessary set is performed, after which the application\r
- *          supplied main() routine is called.\r
- * @param  None\r
- * @retval : None\r
-*/\r
-\r
-    .section   .text.Reset_Handler\r
-       .weak   Reset_Handler\r
-       .type   Reset_Handler, %function\r
-Reset_Handler:\r
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */\r
-\r
-/* Copy the data segment initializers from flash to SRAM */\r
-  movs r1, #0\r
-  b    LoopCopyDataInit\r
-\r
-CopyDataInit:\r
-       ldr     r3, =_sidata\r
-       ldr     r3, [r3, r1]\r
-       str     r3, [r0, r1]\r
-       adds    r1, r1, #4\r
-\r
-LoopCopyDataInit:\r
-       ldr     r0, =_sdata\r
-       ldr     r3, =_edata\r
-       adds    r2, r0, r1\r
-       cmp     r2, r3\r
-       bcc     CopyDataInit\r
-       ldr     r2, =_sbss\r
-       b       LoopFillZerobss\r
-/* Zero fill the bss segment. */\r
-FillZerobss:\r
-       movs    r3, #0\r
-       str     r3, [r2], #4\r
-\r
-LoopFillZerobss:\r
-       ldr     r3, = _ebss\r
-       cmp     r2, r3\r
-       bcc     FillZerobss\r
-\r
-/* Call the clock system intitialization function.*/\r
-    bl  SystemInit\r
-/* Call static constructors */\r
-    bl __libc_init_array\r
-/* Call the application's entry point.*/\r
-       bl      main\r
-\r
-LoopForever:\r
-    b LoopForever\r
-    \r
-.size  Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief  This is the code that gets called when the processor receives an\r
- *         unexpected interrupt.  This simply enters an infinite loop, preserving\r
- *         the system state for examination by a debugger.\r
- *\r
- * @param  None\r
- * @retval : None\r
-*/\r
-    .section   .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
-       b       Infinite_Loop\r
-       .size   Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex-M4.  Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/\r
-       .section        .isr_vector,"a",%progbits\r
-       .type   g_pfnVectors, %object\r
-       .size   g_pfnVectors, .-g_pfnVectors\r
-\r
-\r
-g_pfnVectors:\r
-       .word   _estack\r
-       .word   Reset_Handler\r
-       .word   NMI_Handler\r
-       .word   HardFault_Handler\r
-       .word   MemManage_Handler\r
-       .word   BusFault_Handler\r
-       .word   UsageFault_Handler\r
-       .word   0\r
-       .word   0\r
-       .word   0\r
-       .word   0\r
-       .word   SVC_Handler\r
-       .word   DebugMon_Handler\r
-       .word   0\r
-       .word   PendSV_Handler\r
-       .word   SysTick_Handler\r
-       .word   WWDG_IRQHandler\r
-       .word   PVD_PVM_IRQHandler\r
-       .word   TAMP_STAMP_IRQHandler\r
-       .word   RTC_WKUP_IRQHandler\r
-       .word   FLASH_IRQHandler\r
-       .word   RCC_IRQHandler\r
-       .word   EXTI0_IRQHandler\r
-       .word   EXTI1_IRQHandler\r
-       .word   EXTI2_IRQHandler\r
-       .word   EXTI3_IRQHandler\r
-       .word   EXTI4_IRQHandler\r
-       .word   DMA1_Channel1_IRQHandler\r
-       .word   DMA1_Channel2_IRQHandler\r
-       .word   DMA1_Channel3_IRQHandler\r
-       .word   DMA1_Channel4_IRQHandler\r
-       .word   DMA1_Channel5_IRQHandler\r
-       .word   DMA1_Channel6_IRQHandler\r
-       .word   DMA1_Channel7_IRQHandler\r
-       .word   ADC1_2_IRQHandler\r
-       .word   CAN1_TX_IRQHandler\r
-       .word   CAN1_RX0_IRQHandler\r
-       .word   CAN1_RX1_IRQHandler\r
-       .word   CAN1_SCE_IRQHandler\r
-       .word   EXTI9_5_IRQHandler\r
-       .word   TIM1_BRK_TIM15_IRQHandler\r
-       .word   TIM1_UP_TIM16_IRQHandler\r
-       .word   TIM1_TRG_COM_TIM17_IRQHandler\r
-       .word   TIM1_CC_IRQHandler\r
-       .word   TIM2_IRQHandler\r
-       .word   TIM3_IRQHandler\r
-       .word   TIM4_IRQHandler\r
-       .word   I2C1_EV_IRQHandler\r
-       .word   I2C1_ER_IRQHandler\r
-       .word   I2C2_EV_IRQHandler\r
-       .word   I2C2_ER_IRQHandler\r
-       .word   SPI1_IRQHandler\r
-       .word   SPI2_IRQHandler\r
-       .word   USART1_IRQHandler\r
-       .word   USART2_IRQHandler\r
-       .word   USART3_IRQHandler\r
-       .word   EXTI15_10_IRQHandler\r
-       .word   RTC_Alarm_IRQHandler\r
-       .word   DFSDM1_FLT3_IRQHandler\r
-       .word   TIM8_BRK_IRQHandler\r
-       .word   TIM8_UP_IRQHandler\r
-       .word   TIM8_TRG_COM_IRQHandler\r
-       .word   TIM8_CC_IRQHandler\r
-       .word   ADC3_IRQHandler\r
-       .word   FMC_IRQHandler\r
-       .word   SDMMC1_IRQHandler\r
-       .word   TIM5_IRQHandler\r
-       .word   SPI3_IRQHandler\r
-       .word   UART4_IRQHandler\r
-       .word   UART5_IRQHandler\r
-       .word   TIM6_DAC_IRQHandler\r
-       .word   TIM7_IRQHandler\r
-       .word   DMA2_Channel1_IRQHandler\r
-       .word   DMA2_Channel2_IRQHandler\r
-       .word   DMA2_Channel3_IRQHandler\r
-       .word   DMA2_Channel4_IRQHandler\r
-       .word   DMA2_Channel5_IRQHandler\r
-       .word   DFSDM1_FLT0_IRQHandler\r
-       .word   DFSDM1_FLT1_IRQHandler\r
-       .word   DFSDM1_FLT2_IRQHandler\r
-       .word   COMP_IRQHandler\r
-       .word   LPTIM1_IRQHandler\r
-       .word   LPTIM2_IRQHandler\r
-       .word   OTG_FS_IRQHandler\r
-       .word   DMA2_Channel6_IRQHandler\r
-       .word   DMA2_Channel7_IRQHandler\r
-       .word   LPUART1_IRQHandler\r
-       .word   QUADSPI_IRQHandler\r
-       .word   I2C3_EV_IRQHandler\r
-       .word   I2C3_ER_IRQHandler\r
-       .word   SAI1_IRQHandler\r
-       .word   SAI2_IRQHandler\r
-       .word   SWPMI1_IRQHandler\r
-       .word   TSC_IRQHandler\r
-       .word 0\r
-       .word 0\r
-       .word   RNG_IRQHandler\r
-       .word   FPU_IRQHandler\r
-\r
-\r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler.\r
-* As they are weak aliases, any function with the same name will override\r
-* this definition.\r
-*\r
-*******************************************************************************/\r
-\r
-  .weak        NMI_Handler\r
-       .thumb_set NMI_Handler,Default_Handler\r
-\r
-  .weak        HardFault_Handler\r
-       .thumb_set HardFault_Handler,Default_Handler\r
-\r
-  .weak        MemManage_Handler\r
-       .thumb_set MemManage_Handler,Default_Handler\r
-\r
-  .weak        BusFault_Handler\r
-       .thumb_set BusFault_Handler,Default_Handler\r
-\r
-       .weak   UsageFault_Handler\r
-       .thumb_set UsageFault_Handler,Default_Handler\r
-\r
-       .weak   SVC_Handler\r
-       .thumb_set SVC_Handler,Default_Handler\r
-\r
-       .weak   DebugMon_Handler\r
-       .thumb_set DebugMon_Handler,Default_Handler\r
-\r
-       .weak   PendSV_Handler\r
-       .thumb_set PendSV_Handler,Default_Handler\r
-\r
-       .weak   SysTick_Handler\r
-       .thumb_set SysTick_Handler,Default_Handler\r
-\r
-       .weak   WWDG_IRQHandler\r
-       .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
-       .weak   PVD_PVM_IRQHandler\r
-       .thumb_set PVD_PVM_IRQHandler,Default_Handler\r
-\r
-       .weak   TAMP_STAMP_IRQHandler\r
-       .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r
-\r
-       .weak   RTC_WKUP_IRQHandler\r
-       .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
-\r
-       .weak   FLASH_IRQHandler\r
-       .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
-       .weak   RCC_IRQHandler\r
-       .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
-       .weak   EXTI0_IRQHandler\r
-       .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
-       .weak   EXTI1_IRQHandler\r
-       .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
-       .weak   EXTI2_IRQHandler\r
-       .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
-       .weak   EXTI3_IRQHandler\r
-       .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
-       .weak   EXTI4_IRQHandler\r
-       .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA1_Channel1_IRQHandler\r
-       .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA1_Channel2_IRQHandler\r
-       .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA1_Channel3_IRQHandler\r
-       .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA1_Channel4_IRQHandler\r
-       .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA1_Channel5_IRQHandler\r
-       .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA1_Channel6_IRQHandler\r
-       .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA1_Channel7_IRQHandler\r
-       .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
-       .weak   ADC1_2_IRQHandler\r
-       .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
-       .weak   CAN1_TX_IRQHandler\r
-       .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
-\r
-       .weak   CAN1_RX0_IRQHandler\r
-       .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
-\r
-       .weak   CAN1_RX1_IRQHandler\r
-       .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
-       .weak   CAN1_SCE_IRQHandler\r
-       .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
-       .weak   EXTI9_5_IRQHandler\r
-       .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM1_BRK_TIM15_IRQHandler\r
-       .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM1_UP_TIM16_IRQHandler\r
-       .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM1_TRG_COM_TIM17_IRQHandler\r
-       .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM1_CC_IRQHandler\r
-       .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM2_IRQHandler\r
-       .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM3_IRQHandler\r
-       .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM4_IRQHandler\r
-       .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
-       .weak   I2C1_EV_IRQHandler\r
-       .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
-       .weak   I2C1_ER_IRQHandler\r
-       .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
-       .weak   I2C2_EV_IRQHandler\r
-       .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
-       .weak   I2C2_ER_IRQHandler\r
-       .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
-       .weak   SPI1_IRQHandler\r
-       .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
-       .weak   SPI2_IRQHandler\r
-       .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
-       .weak   USART1_IRQHandler\r
-       .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
-       .weak   USART2_IRQHandler\r
-       .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
-       .weak   USART3_IRQHandler\r
-       .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
-       .weak   EXTI15_10_IRQHandler\r
-       .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
-       .weak   RTC_Alarm_IRQHandler\r
-       .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
-\r
-       .weak   DFSDM1_FLT3_IRQHandler\r
-       .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM8_BRK_IRQHandler\r
-       .thumb_set TIM8_BRK_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM8_UP_IRQHandler\r
-       .thumb_set TIM8_UP_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM8_TRG_COM_IRQHandler\r
-       .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM8_CC_IRQHandler\r
-       .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
-\r
-       .weak   ADC3_IRQHandler\r
-       .thumb_set ADC3_IRQHandler,Default_Handler\r
-\r
-       .weak   FMC_IRQHandler\r
-       .thumb_set FMC_IRQHandler,Default_Handler\r
-\r
-       .weak   SDMMC1_IRQHandler\r
-       .thumb_set SDMMC1_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM5_IRQHandler\r
-       .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
-       .weak   SPI3_IRQHandler\r
-       .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
-       .weak   UART4_IRQHandler\r
-       .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
-       .weak   UART5_IRQHandler\r
-       .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM6_DAC_IRQHandler\r
-       .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r
-\r
-       .weak   TIM7_IRQHandler\r
-       .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA2_Channel1_IRQHandler\r
-       .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA2_Channel2_IRQHandler\r
-       .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA2_Channel3_IRQHandler\r
-       .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA2_Channel4_IRQHandler\r
-       .thumb_set DMA2_Channel4_IRQHandler,Default_Handler\r
-\r
-       .weak   DMA2_Channel5_IRQHandler\r
-       .thumb_set DMA2_Channel5_IRQHandler,Default_Handler\r
-\r
-       .weak   DFSDM1_FLT0_IRQHandler\r
-       .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler       \r
-       \r
-       .weak   DFSDM1_FLT1_IRQHandler\r
-       .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler       \r
-       \r
-       .weak   DFSDM1_FLT2_IRQHandler\r
-       .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler       \r
-       \r
-       .weak   COMP_IRQHandler\r
-       .thumb_set COMP_IRQHandler,Default_Handler\r
-       \r
-       .weak   LPTIM1_IRQHandler\r
-       .thumb_set LPTIM1_IRQHandler,Default_Handler\r
-       \r
-       .weak   LPTIM2_IRQHandler\r
-       .thumb_set LPTIM2_IRQHandler,Default_Handler    \r
-       \r
-       .weak   OTG_FS_IRQHandler\r
-       .thumb_set OTG_FS_IRQHandler,Default_Handler    \r
-       \r
-       .weak   DMA2_Channel6_IRQHandler\r
-       .thumb_set DMA2_Channel6_IRQHandler,Default_Handler     \r
-       \r
-       .weak   DMA2_Channel7_IRQHandler\r
-       .thumb_set DMA2_Channel7_IRQHandler,Default_Handler     \r
-       \r
-       .weak   LPUART1_IRQHandler\r
-       .thumb_set LPUART1_IRQHandler,Default_Handler   \r
-       \r
-       .weak   QUADSPI_IRQHandler\r
-       .thumb_set QUADSPI_IRQHandler,Default_Handler   \r
-       \r
-       .weak   I2C3_EV_IRQHandler\r
-       .thumb_set I2C3_EV_IRQHandler,Default_Handler   \r
-       \r
-       .weak   I2C3_ER_IRQHandler\r
-       .thumb_set I2C3_ER_IRQHandler,Default_Handler   \r
-       \r
-       .weak   SAI1_IRQHandler\r
-       .thumb_set SAI1_IRQHandler,Default_Handler\r
-       \r
-       .weak   SAI2_IRQHandler\r
-       .thumb_set SAI2_IRQHandler,Default_Handler\r
-       \r
-       .weak   SWPMI1_IRQHandler\r
-       .thumb_set SWPMI1_IRQHandler,Default_Handler\r
-       \r
-       .weak   TSC_IRQHandler\r
-       .thumb_set TSC_IRQHandler,Default_Handler\r
-       \r
-       .weak   RNG_IRQHandler\r
-       .thumb_set RNG_IRQHandler,Default_Handler\r
-       \r
-       .weak   FPU_IRQHandler\r
-       .thumb_set FPU_IRQHandler,Default_Handler\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/syscalls.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/syscalls.c
deleted file mode 100644 (file)
index 9f32dad..0000000
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
-*****************************************************************************
-**
-**  File        : syscalls.c
-**
-**  Author         : Auto-generated by STM32CubeIDE
-**
-**  Abstract    : STM32CubeIDE Minimal System calls file
-**
-**                       For more information about which c-functions
-**                need which of these lowlevel functions
-**                please consult the Newlib libc-manual
-**
-**  Environment : STM32CubeIDE MCU
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-*****************************************************************************
-**
-** <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**
-*****************************************************************************
-*/
-
-/* Includes */
-#include <sys/stat.h>
-#include <stdlib.h>
-#include <errno.h>
-#include <stdio.h>
-#include <signal.h>
-#include <time.h>
-#include <sys/time.h>
-#include <sys/times.h>
-
-
-/* Variables */
-//#undef errno
-extern int errno;
-extern int __io_putchar(int ch) __attribute__((weak));
-extern int __io_getchar(void) __attribute__((weak));
-
-register char * stack_ptr asm("sp");
-
-char *__env[1] = { 0 };
-char **environ = __env;
-
-
-/* Functions */
-void initialise_monitor_handles()
-{
-}
-
-int _getpid(void)
-{
-       return 1;
-}
-
-int _kill(int pid, int sig)
-{
-       errno = EINVAL;
-       return -1;
-}
-
-void _exit (int status)
-{
-       _kill(status, -1);
-       while (1) {}            /* Make sure we hang here */
-}
-
-__attribute__((weak)) int _read(int file, char *ptr, int len)
-{
-       int DataIdx;
-
-       for (DataIdx = 0; DataIdx < len; DataIdx++)
-       {
-               *ptr++ = __io_getchar();
-       }
-
-return len;
-}
-
-__attribute__((weak)) int _write(int file, char *ptr, int len)
-{
-       int DataIdx;
-
-       for (DataIdx = 0; DataIdx < len; DataIdx++)
-       {
-               __io_putchar(*ptr++);
-       }
-       return len;
-}
-
-int _close(int file)
-{
-       return -1;
-}
-
-
-int _fstat(int file, struct stat *st)
-{
-       st->st_mode = S_IFCHR;
-       return 0;
-}
-
-int _isatty(int file)
-{
-       return 1;
-}
-
-int _lseek(int file, int ptr, int dir)
-{
-       return 0;
-}
-
-int _open(char *path, int flags, ...)
-{
-       /* Pretend like we always fail */
-       return -1;
-}
-
-int _wait(int *status)
-{
-       errno = ECHILD;
-       return -1;
-}
-
-int _unlink(char *name)
-{
-       errno = ENOENT;
-       return -1;
-}
-
-int _times(struct tms *buf)
-{
-       return -1;
-}
-
-int _stat(char *file, struct stat *st)
-{
-       st->st_mode = S_IFCHR;
-       return 0;
-}
-
-int _link(char *old, char *new)
-{
-       errno = EMLINK;
-       return -1;
-}
-
-int _fork(void)
-{
-       errno = EAGAIN;
-       return -1;
-}
-
-int _execve(char *name, char **argv, char **env)
-{
-       errno = ENOMEM;
-       return -1;
-}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/sysmem.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/sysmem.c
deleted file mode 100644 (file)
index e5e1bc2..0000000
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
-*****************************************************************************
-**
-**  File        : sysmem.c
-**
-**  Author         : Auto-generated by STM32CubeIDE
-**
-**  Abstract    : STM32CubeIDE Minimal System Memory calls file
-**
-**                       For more information about which c-functions
-**                need which of these lowlevel functions
-**                please consult the Newlib libc-manual
-**
-**  Environment : STM32CubeIDE MCU
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-*****************************************************************************
-**
-** <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**
-*****************************************************************************
-*/
-
-/* Includes */
-#include <errno.h>
-#include <stdio.h>
-
-/* Variables */
-extern int errno;
-register char * stack_ptr asm("sp");
-
-/* Functions */
-
-/**
- _sbrk
- Increase program data space. Malloc and related functions depend on this
-**/
-caddr_t _sbrk(int incr)
-{
-       extern char end asm("end");
-       static char *heap_end;
-       char *prev_heap_end;
-
-       if (heap_end == 0)
-               heap_end = &end;
-
-       prev_heap_end = heap_end;
-       if (heap_end + incr > stack_ptr)
-       {
-               errno = ENOMEM;
-               return (caddr_t) -1;
-       }
-
-       heap_end += incr;
-
-       return (caddr_t) prev_heap_end;
-}
-
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/main.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/main.h
deleted file mode 100644 (file)
index 28f22d8..0000000
+++ /dev/null
@@ -1,236 +0,0 @@
-/* USER CODE BEGIN Header */\r
-/**\r
-  ******************************************************************************\r
-  * @file           : main.h\r
-  * @brief          : Header for main.c file.\r
-  *                   This file contains the common defines of the application.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-/* USER CODE END Header */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __MAIN_H\r
-#define __MAIN_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* USER CODE BEGIN ET */\r
-\r
-/* USER CODE END ET */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/* USER CODE BEGIN EC */\r
-\r
-/* USER CODE END EC */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* USER CODE BEGIN EM */\r
-\r
-/* USER CODE END EM */\r
-\r
-/* Exported functions prototypes ---------------------------------------------*/\r
-void Error_Handler(void);\r
-\r
-/* USER CODE BEGIN EFP */\r
-\r
-/* USER CODE END EFP */\r
-\r
-/* Private defines -----------------------------------------------------------*/\r
-#define M24SR64_Y_RF_DISABLE_Pin GPIO_PIN_2\r
-#define M24SR64_Y_RF_DISABLE_GPIO_Port GPIOE\r
-#define USB_OTG_FS_OVRCR_EXTI3_Pin GPIO_PIN_3\r
-#define USB_OTG_FS_OVRCR_EXTI3_GPIO_Port GPIOE\r
-#define M24SR64_Y_GPO_Pin GPIO_PIN_4\r
-#define M24SR64_Y_GPO_GPIO_Port GPIOE\r
-#define SPSGRF_915_GPIO3_EXTI5_Pin GPIO_PIN_5\r
-#define SPSGRF_915_GPIO3_EXTI5_GPIO_Port GPIOE\r
-#define SPSGRF_915_GPIO3_EXTI5_EXTI_IRQn EXTI9_5_IRQn\r
-#define SPBTLE_RF_IRQ_EXTI6_Pin GPIO_PIN_6\r
-#define SPBTLE_RF_IRQ_EXTI6_GPIO_Port GPIOE\r
-#define SPBTLE_RF_IRQ_EXTI6_EXTI_IRQn EXTI9_5_IRQn\r
-#define BUTTON_EXTI13_Pin GPIO_PIN_13\r
-#define BUTTON_EXTI13_GPIO_Port GPIOC\r
-#define BUTTON_EXTI13_EXTI_IRQn EXTI15_10_IRQn\r
-#define ARD_A5_Pin GPIO_PIN_0\r
-#define ARD_A5_GPIO_Port GPIOC\r
-#define ARD_A4_Pin GPIO_PIN_1\r
-#define ARD_A4_GPIO_Port GPIOC\r
-#define ARD_A3_Pin GPIO_PIN_2\r
-#define ARD_A3_GPIO_Port GPIOC\r
-#define ARD_A2_Pin GPIO_PIN_3\r
-#define ARD_A2_GPIO_Port GPIOC\r
-#define ARD_D1_Pin GPIO_PIN_0\r
-#define ARD_D1_GPIO_Port GPIOA\r
-#define ARD_D0_Pin GPIO_PIN_1\r
-#define ARD_D0_GPIO_Port GPIOA\r
-#define ARD_D10_Pin GPIO_PIN_2\r
-#define ARD_D10_GPIO_Port GPIOA\r
-#define ARD_D4_Pin GPIO_PIN_3\r
-#define ARD_D4_GPIO_Port GPIOA\r
-#define ARD_D7_Pin GPIO_PIN_4\r
-#define ARD_D7_GPIO_Port GPIOA\r
-#define ARD_D13_Pin GPIO_PIN_5\r
-#define ARD_D13_GPIO_Port GPIOA\r
-#define ARD_D12_Pin GPIO_PIN_6\r
-#define ARD_D12_GPIO_Port GPIOA\r
-#define ARD_D11_Pin GPIO_PIN_7\r
-#define ARD_D11_GPIO_Port GPIOA\r
-#define ARD_A1_Pin GPIO_PIN_4\r
-#define ARD_A1_GPIO_Port GPIOC\r
-#define ARD_A0_Pin GPIO_PIN_5\r
-#define ARD_A0_GPIO_Port GPIOC\r
-#define ARD_D3_Pin GPIO_PIN_0\r
-#define ARD_D3_GPIO_Port GPIOB\r
-#define ARD_D6_Pin GPIO_PIN_1\r
-#define ARD_D6_GPIO_Port GPIOB\r
-#define ARD_D8_Pin GPIO_PIN_2\r
-#define ARD_D8_GPIO_Port GPIOB\r
-#define DFSDM1_DATIN2_Pin GPIO_PIN_7\r
-#define DFSDM1_DATIN2_GPIO_Port GPIOE\r
-#define ISM43362_RST_Pin GPIO_PIN_8\r
-#define ISM43362_RST_GPIO_Port GPIOE\r
-#define DFSDM1_CKOUT_Pin GPIO_PIN_9\r
-#define DFSDM1_CKOUT_GPIO_Port GPIOE\r
-#define QUADSPI_CLK_Pin GPIO_PIN_10\r
-#define QUADSPI_CLK_GPIO_Port GPIOE\r
-#define QUADSPI_NCS_Pin GPIO_PIN_11\r
-#define QUADSPI_NCS_GPIO_Port GPIOE\r
-#define OQUADSPI_BK1_IO0_Pin GPIO_PIN_12\r
-#define OQUADSPI_BK1_IO0_GPIO_Port GPIOE\r
-#define QUADSPI_BK1_IO1_Pin GPIO_PIN_13\r
-#define QUADSPI_BK1_IO1_GPIO_Port GPIOE\r
-#define QUAD_SPI_BK1_IO2_Pin GPIO_PIN_14\r
-#define QUAD_SPI_BK1_IO2_GPIO_Port GPIOE\r
-#define QUAD_SPI_BK1_IO3_Pin GPIO_PIN_15\r
-#define QUAD_SPI_BK1_IO3_GPIO_Port GPIOE\r
-#define INTERNAL_I2C2_SCL_Pin GPIO_PIN_10\r
-#define INTERNAL_I2C2_SCL_GPIO_Port GPIOB\r
-#define INTERNAL_I2C2_SDA_Pin GPIO_PIN_11\r
-#define INTERNAL_I2C2_SDA_GPIO_Port GPIOB\r
-#define ISM43362_BOOT0_Pin GPIO_PIN_12\r
-#define ISM43362_BOOT0_GPIO_Port GPIOB\r
-#define ISM43362_WAKEUP_Pin GPIO_PIN_13\r
-#define ISM43362_WAKEUP_GPIO_Port GPIOB\r
-#define LED2_Pin GPIO_PIN_14\r
-#define LED2_GPIO_Port GPIOB\r
-#define SPSGRF_915_SDN_Pin GPIO_PIN_15\r
-#define SPSGRF_915_SDN_GPIO_Port GPIOB\r
-#define INTERNAL_UART3_TX_Pin GPIO_PIN_8\r
-#define INTERNAL_UART3_TX_GPIO_Port GPIOD\r
-#define INTERNAL_UART3_RX_Pin GPIO_PIN_9\r
-#define INTERNAL_UART3_RX_GPIO_Port GPIOD\r
-#define LPS22HB_INT_DRDY_EXTI0_Pin GPIO_PIN_10\r
-#define LPS22HB_INT_DRDY_EXTI0_GPIO_Port GPIOD\r
-#define LPS22HB_INT_DRDY_EXTI0_EXTI_IRQn EXTI15_10_IRQn\r
-#define LSM6DSL_INT1_EXTI11_Pin GPIO_PIN_11\r
-#define LSM6DSL_INT1_EXTI11_GPIO_Port GPIOD\r
-#define LSM6DSL_INT1_EXTI11_EXTI_IRQn EXTI15_10_IRQn\r
-#define USB_OTG_FS_PWR_EN_Pin GPIO_PIN_12\r
-#define USB_OTG_FS_PWR_EN_GPIO_Port GPIOD\r
-#define SPBTLE_RF_SPI3_CSN_Pin GPIO_PIN_13\r
-#define SPBTLE_RF_SPI3_CSN_GPIO_Port GPIOD\r
-#define ARD_D2_Pin GPIO_PIN_14\r
-#define ARD_D2_GPIO_Port GPIOD\r
-#define ARD_D2_EXTI_IRQn EXTI15_10_IRQn\r
-#define HTS221_DRDY_EXTI15_Pin GPIO_PIN_15\r
-#define HTS221_DRDY_EXTI15_GPIO_Port GPIOD\r
-#define HTS221_DRDY_EXTI15_EXTI_IRQn EXTI15_10_IRQn\r
-#define VL53L0X_XSHUT_Pin GPIO_PIN_6\r
-#define VL53L0X_XSHUT_GPIO_Port GPIOC\r
-#define VL53L0X_GPIO1_EXTI7_Pin GPIO_PIN_7\r
-#define VL53L0X_GPIO1_EXTI7_GPIO_Port GPIOC\r
-#define VL53L0X_GPIO1_EXTI7_EXTI_IRQn EXTI9_5_IRQn\r
-#define LSM3MDL_DRDY_EXTI8_Pin GPIO_PIN_8\r
-#define LSM3MDL_DRDY_EXTI8_GPIO_Port GPIOC\r
-#define LSM3MDL_DRDY_EXTI8_EXTI_IRQn EXTI9_5_IRQn\r
-#define LED3_WIFI__LED4_BLE_Pin GPIO_PIN_9\r
-#define LED3_WIFI__LED4_BLE_GPIO_Port GPIOC\r
-#define SPBTLE_RF_RST_Pin GPIO_PIN_8\r
-#define SPBTLE_RF_RST_GPIO_Port GPIOA\r
-#define USB_OTG_FS_VBUS_Pin GPIO_PIN_9\r
-#define USB_OTG_FS_VBUS_GPIO_Port GPIOA\r
-#define USB_OTG_FS_ID_Pin GPIO_PIN_10\r
-#define USB_OTG_FS_ID_GPIO_Port GPIOA\r
-#define USB_OTG_FS_DM_Pin GPIO_PIN_11\r
-#define USB_OTG_FS_DM_GPIO_Port GPIOA\r
-#define USB_OTG_FS_DP_Pin GPIO_PIN_12\r
-#define USB_OTG_FS_DP_GPIO_Port GPIOA\r
-#define SYS_JTMS_SWDIO_Pin GPIO_PIN_13\r
-#define SYS_JTMS_SWDIO_GPIO_Port GPIOA\r
-#define SYS_JTCK_SWCLK_Pin GPIO_PIN_14\r
-#define SYS_JTCK_SWCLK_GPIO_Port GPIOA\r
-#define ARD_D9_Pin GPIO_PIN_15\r
-#define ARD_D9_GPIO_Port GPIOA\r
-#define INTERNAL_SPI3_SCK_Pin GPIO_PIN_10\r
-#define INTERNAL_SPI3_SCK_GPIO_Port GPIOC\r
-#define INTERNAL_SPI3_MISO_Pin GPIO_PIN_11\r
-#define INTERNAL_SPI3_MISO_GPIO_Port GPIOC\r
-#define INTERNAL_SPI3_MOSI_Pin GPIO_PIN_12\r
-#define INTERNAL_SPI3_MOSI_GPIO_Port GPIOC\r
-#define PMOD_RESET_Pin GPIO_PIN_0\r
-#define PMOD_RESET_GPIO_Port GPIOD\r
-#define PMOD_SPI2_SCK_Pin GPIO_PIN_1\r
-#define PMOD_SPI2_SCK_GPIO_Port GPIOD\r
-#define PMOD_IRQ_EXTI12_Pin GPIO_PIN_2\r
-#define PMOD_IRQ_EXTI12_GPIO_Port GPIOD\r
-#define PMOD_UART2_CTS_Pin GPIO_PIN_3\r
-#define PMOD_UART2_CTS_GPIO_Port GPIOD\r
-#define PMOD_UART2_RTS_Pin GPIO_PIN_4\r
-#define PMOD_UART2_RTS_GPIO_Port GPIOD\r
-#define PMOD_UART2_TX_Pin GPIO_PIN_5\r
-#define PMOD_UART2_TX_GPIO_Port GPIOD\r
-#define PMOD_UART2_RX_Pin GPIO_PIN_6\r
-#define PMOD_UART2_RX_GPIO_Port GPIOD\r
-#define STSAFE_A100_RESET_Pin GPIO_PIN_7\r
-#define STSAFE_A100_RESET_GPIO_Port GPIOD\r
-#define SYS_JTD0_SWO_Pin GPIO_PIN_3\r
-#define SYS_JTD0_SWO_GPIO_Port GPIOB\r
-#define ARD_D5_Pin GPIO_PIN_4\r
-#define ARD_D5_GPIO_Port GPIOB\r
-#define SPSGRF_915_SPI3_CSN_Pin GPIO_PIN_5\r
-#define SPSGRF_915_SPI3_CSN_GPIO_Port GPIOB\r
-#define ST_LINK_UART1_TX_Pin GPIO_PIN_6\r
-#define ST_LINK_UART1_TX_GPIO_Port GPIOB\r
-#define ST_LINK_UART1_RX_Pin GPIO_PIN_7\r
-#define ST_LINK_UART1_RX_GPIO_Port GPIOB\r
-#define ARD_D15_Pin GPIO_PIN_8\r
-#define ARD_D15_GPIO_Port GPIOB\r
-#define ARD_D14_Pin GPIO_PIN_9\r
-#define ARD_D14_GPIO_Port GPIOB\r
-#define ISM43362_SPI3_CSN_Pin GPIO_PIN_0\r
-#define ISM43362_SPI3_CSN_GPIO_Port GPIOE\r
-#define ISM43362_DRDY_EXTI1_Pin GPIO_PIN_1\r
-#define ISM43362_DRDY_EXTI1_GPIO_Port GPIOE\r
-/* USER CODE BEGIN Private defines */\r
-\r
-/* USER CODE END Private defines */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MAIN_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/stm32l4xx_hal_conf.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/stm32l4xx_hal_conf.h
deleted file mode 100644 (file)
index 25b2a0d..0000000
+++ /dev/null
@@ -1,440 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_conf.h\r
-  * @brief   HAL configuration file.             \r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>\r
-  *\r
-  * Redistribution and use in source and binary forms, with or without modification,\r
-  * are permitted provided that the following conditions are met:\r
-  *   1. Redistributions of source code must retain the above copyright notice,\r
-  *      this list of conditions and the following disclaimer.\r
-  *   2. Redistributions in binary form must reproduce the above copyright notice,\r
-  *      this list of conditions and the following disclaimer in the documentation\r
-  *      and/or other materials provided with the distribution.\r
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-  *      may be used to endorse or promote products derived from this software\r
-  *      without specific prior written permission.\r
-  *\r
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-  *\r
-  ******************************************************************************\r
-  */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_CONF_H\r
-#define __STM32L4xx_HAL_CONF_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/* ########################## Module Selection ############################## */\r
-/**\r
-  * @brief This is the list of modules to be used in the HAL driver \r
-  */\r
-\r
-#define HAL_MODULE_ENABLED  \r
-/*#define HAL_ADC_MODULE_ENABLED   */\r
-/*#define HAL_CRYP_MODULE_ENABLED   */\r
-/*#define HAL_CAN_MODULE_ENABLED   */\r
-/*#define HAL_COMP_MODULE_ENABLED   */\r
-/*#define HAL_CRC_MODULE_ENABLED   */\r
-/*#define HAL_CRYP_MODULE_ENABLED   */\r
-/*#define HAL_DAC_MODULE_ENABLED   */\r
-/*#define HAL_DCMI_MODULE_ENABLED   */\r
-/*#define HAL_DMA2D_MODULE_ENABLED   */\r
-#define HAL_DFSDM_MODULE_ENABLED\r
-/*#define HAL_DSI_MODULE_ENABLED   */\r
-/*#define HAL_FIREWALL_MODULE_ENABLED   */\r
-/*#define HAL_GFXMMU_MODULE_ENABLED   */\r
-/*#define HAL_HCD_MODULE_ENABLED   */\r
-/*#define HAL_HASH_MODULE_ENABLED   */\r
-/*#define HAL_I2S_MODULE_ENABLED   */\r
-/*#define HAL_IRDA_MODULE_ENABLED   */\r
-/*#define HAL_IWDG_MODULE_ENABLED   */\r
-/*#define HAL_LTDC_MODULE_ENABLED   */\r
-/*#define HAL_LCD_MODULE_ENABLED   */\r
-/*#define HAL_LPTIM_MODULE_ENABLED   */\r
-/*#define HAL_MMC_MODULE_ENABLED   */\r
-/*#define HAL_NAND_MODULE_ENABLED   */\r
-/*#define HAL_NOR_MODULE_ENABLED   */\r
-/*#define HAL_OPAMP_MODULE_ENABLED   */\r
-/*#define HAL_OSPI_MODULE_ENABLED   */\r
-/*#define HAL_OSPI_MODULE_ENABLED   */\r
-#define HAL_PCD_MODULE_ENABLED\r
-/*#define HAL_QSPI_MODULE_ENABLED   */\r
-#define HAL_QSPI_MODULE_ENABLED\r
-/*#define HAL_RNG_MODULE_ENABLED   */\r
-/*#define HAL_RTC_MODULE_ENABLED   */\r
-/*#define HAL_SAI_MODULE_ENABLED   */\r
-/*#define HAL_SD_MODULE_ENABLED   */\r
-/*#define HAL_SMBUS_MODULE_ENABLED   */\r
-/*#define HAL_SMARTCARD_MODULE_ENABLED   */\r
-#define HAL_SPI_MODULE_ENABLED\r
-/*#define HAL_SRAM_MODULE_ENABLED   */\r
-/*#define HAL_SWPMI_MODULE_ENABLED   */\r
-#define HAL_TIM_MODULE_ENABLED\r
-/*#define HAL_TSC_MODULE_ENABLED   */\r
-#define HAL_UART_MODULE_ENABLED\r
-/*#define HAL_USART_MODULE_ENABLED   */\r
-/*#define HAL_WWDG_MODULE_ENABLED   */\r
-/*#define HAL_EXTI_MODULE_ENABLED   */\r
-#define HAL_GPIO_MODULE_ENABLED\r
-#define HAL_EXTI_MODULE_ENABLED \r
-#define HAL_I2C_MODULE_ENABLED\r
-#define HAL_DMA_MODULE_ENABLED\r
-#define HAL_RCC_MODULE_ENABLED\r
-#define HAL_FLASH_MODULE_ENABLED\r
-#define HAL_PWR_MODULE_ENABLED\r
-#define HAL_CORTEX_MODULE_ENABLED\r
-\r
-/* ########################## Oscillator Values adaptation ####################*/\r
-/**\r
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
-  *        This value is used by the RCC HAL module to compute the system frequency\r
-  *        (when HSE is used as system clock source, directly or through the PLL).  \r
-  */\r
-#if !defined  (HSE_VALUE) \r
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */\r
-#endif /* HSE_VALUE */\r
-\r
-#if !defined  (HSE_STARTUP_TIMEOUT)\r
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */\r
-#endif /* HSE_STARTUP_TIMEOUT */\r
-\r
-/**\r
-  * @brief Internal Multiple Speed oscillator (MSI) default value.\r
-  *        This value is the default MSI range value after Reset.\r
-  */\r
-#if !defined  (MSI_VALUE)\r
-  #define MSI_VALUE    ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/\r
-#endif /* MSI_VALUE */\r
-/**\r
-  * @brief Internal High Speed oscillator (HSI) value.\r
-  *        This value is used by the RCC HAL module to compute the system frequency\r
-  *        (when HSI is used as system clock source, directly or through the PLL). \r
-  */\r
-#if !defined  (HSI_VALUE)\r
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/\r
-#endif /* HSI_VALUE */\r
-\r
-/**\r
-  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.\r
-  *        This internal oscillator is mainly dedicated to provide a high precision clock to\r
-  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.\r
-  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency\r
-  *        which is subject to manufacturing process variations.\r
-  */\r
-#if !defined  (HSI48_VALUE) \r
- #define HSI48_VALUE   ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.\r
-                                              The real value my vary depending on manufacturing process variations.*/\r
-#endif /* HSI48_VALUE */\r
-\r
-/**\r
-  * @brief Internal Low Speed oscillator (LSI) value.\r
-  */\r
-#if !defined  (LSI_VALUE) \r
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/\r
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz\r
-                                             The real value may vary depending on the variations\r
-                                             in voltage and temperature.*/\r
-\r
-/**\r
-  * @brief External Low Speed oscillator (LSE) value.\r
-  *        This value is used by the UART, RTC HAL module to compute the system frequency\r
-  */\r
-#if !defined  (LSE_VALUE)\r
-  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/\r
-#endif /* LSE_VALUE */\r
-\r
-#if !defined  (LSE_STARTUP_TIMEOUT)\r
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */\r
-#endif /* HSE_STARTUP_TIMEOUT */\r
-\r
-/**\r
-  * @brief External clock source for SAI1 peripheral\r
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source \r
-  *        frequency.\r
-  */\r
-#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)\r
-  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/\r
-#endif /* EXTERNAL_SAI1_CLOCK_VALUE */\r
-\r
-/**\r
-  * @brief External clock source for SAI2 peripheral\r
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source \r
-  *        frequency.\r
-  */\r
-#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)\r
-  #define EXTERNAL_SAI2_CLOCK_VALUE    ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/\r
-#endif /* EXTERNAL_SAI2_CLOCK_VALUE */\r
-\r
-/* Tip: To avoid modifying this file each time you need to use different HSE,\r
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */\r
-\r
-/* ########################### System Configuration ######################### */\r
-/**\r
-  * @brief This is the HAL system configuration section\r
-  */     \r
-  \r
-#define  VDD_VALUE                                       ((uint32_t)3300U) /*!< Value of VDD in mv */           \r
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */            \r
-#define  USE_RTOS                     0U     \r
-#define  PREFETCH_ENABLE              0U\r
-#define  INSTRUCTION_CACHE_ENABLE     1U\r
-#define  DATA_CACHE_ENABLE            1U\r
-\r
-/* ########################## Assert Selection ############################## */\r
-/**\r
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
-  *        HAL drivers code\r
-  */\r
-/* #define USE_FULL_ASSERT    1U */\r
-\r
-/* ################## SPI peripheral configuration ########################## */\r
-\r
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\r
- * Activated: CRC code is present inside driver\r
- * Deactivated: CRC code cleaned from driver\r
- */\r
-\r
-#define USE_SPI_CRC                   0U\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/**\r
-  * @brief Include module's header file\r
-  */\r
-\r
-#ifdef HAL_RCC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_rcc.h"\r
-  #include "stm32l4xx_hal_rcc_ex.h"\r
-#endif /* HAL_RCC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_EXTI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_exti.h"\r
-#endif /* HAL_EXTI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_GPIO_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_gpio.h"\r
-#endif /* HAL_GPIO_MODULE_ENABLED */\r
-\r
-#ifdef HAL_DMA_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_dma.h"\r
-  #include "stm32l4xx_hal_dma_ex.h"\r
-#endif /* HAL_DMA_MODULE_ENABLED */\r
-\r
-#ifdef HAL_DFSDM_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_dfsdm.h"\r
-#endif /* HAL_DFSDM_MODULE_ENABLED */\r
-\r
-#ifdef HAL_CORTEX_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_cortex.h"\r
-#endif /* HAL_CORTEX_MODULE_ENABLED */\r
-\r
-#ifdef HAL_ADC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_adc.h"\r
-#endif /* HAL_ADC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_CAN_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_can.h"\r
-#endif /* HAL_CAN_MODULE_ENABLED */\r
-\r
-#ifdef HAL_COMP_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_comp.h"\r
-#endif /* HAL_COMP_MODULE_ENABLED */\r
-\r
-#ifdef HAL_CRC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_crc.h"\r
-#endif /* HAL_CRC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_CRYP_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_cryp.h"\r
-#endif /* HAL_CRYP_MODULE_ENABLED */\r
-\r
-#ifdef HAL_DAC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_dac.h"\r
-#endif /* HAL_DAC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_DCMI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_dcmi.h"\r
-#endif /* HAL_DCMI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_DMA2D_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_dma2d.h"\r
-#endif /* HAL_DMA2D_MODULE_ENABLED */\r
-\r
-#ifdef HAL_DSI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_dsi.h"\r
-#endif /* HAL_DSI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_FIREWALL_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_firewall.h"\r
-#endif /* HAL_FIREWALL_MODULE_ENABLED */\r
-\r
-#ifdef HAL_FLASH_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_flash.h"\r
-#endif /* HAL_FLASH_MODULE_ENABLED */\r
-\r
-#ifdef HAL_HASH_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_hash.h"\r
-#endif /* HAL_HASH_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SRAM_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_sram.h"\r
-#endif /* HAL_SRAM_MODULE_ENABLED */\r
-\r
-#ifdef HAL_MMC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_mmc.h"\r
-#endif /* HAL_MMC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_NOR_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_nor.h"\r
-#endif /* HAL_NOR_MODULE_ENABLED */\r
-\r
-#ifdef HAL_NAND_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_nand.h"\r
-#endif /* HAL_NAND_MODULE_ENABLED */\r
-\r
-#ifdef HAL_I2C_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_i2c.h"\r
-#endif /* HAL_I2C_MODULE_ENABLED */\r
-\r
-#ifdef HAL_IWDG_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_iwdg.h"\r
-#endif /* HAL_IWDG_MODULE_ENABLED */\r
-\r
-#ifdef HAL_LCD_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_lcd.h"\r
-#endif /* HAL_LCD_MODULE_ENABLED */\r
-\r
-#ifdef HAL_LPTIM_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_lptim.h"\r
-#endif /* HAL_LPTIM_MODULE_ENABLED */\r
-\r
-#ifdef HAL_LTDC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_ltdc.h"\r
-#endif /* HAL_LTDC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_OPAMP_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_opamp.h"\r
-#endif /* HAL_OPAMP_MODULE_ENABLED */\r
-\r
-#ifdef HAL_OSPI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_ospi.h"\r
-#endif /* HAL_OSPI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_PWR_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_pwr.h"\r
-#endif /* HAL_PWR_MODULE_ENABLED */\r
-\r
-#ifdef HAL_QSPI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_qspi.h"\r
-#endif /* HAL_QSPI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_RNG_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_rng.h"\r
-#endif /* HAL_RNG_MODULE_ENABLED */\r
-\r
-#ifdef HAL_RTC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_rtc.h"\r
-#endif /* HAL_RTC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SAI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_sai.h"\r
-#endif /* HAL_SAI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SD_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_sd.h"\r
-#endif /* HAL_SD_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SMBUS_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_smbus.h"\r
-#endif /* HAL_SMBUS_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SPI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_spi.h"\r
-#endif /* HAL_SPI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SWPMI_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_swpmi.h"\r
-#endif /* HAL_SWPMI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_TIM_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_tim.h"\r
-#endif /* HAL_TIM_MODULE_ENABLED */\r
-\r
-#ifdef HAL_TSC_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_tsc.h"\r
-#endif /* HAL_TSC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_UART_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_uart.h"\r
-#endif /* HAL_UART_MODULE_ENABLED */\r
-\r
-#ifdef HAL_USART_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_usart.h"\r
-#endif /* HAL_USART_MODULE_ENABLED */\r
-\r
-#ifdef HAL_IRDA_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_irda.h"\r
-#endif /* HAL_IRDA_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_smartcard.h"\r
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
-\r
-#ifdef HAL_WWDG_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_wwdg.h"\r
-#endif /* HAL_WWDG_MODULE_ENABLED */\r
-\r
-#ifdef HAL_PCD_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_pcd.h"\r
-#endif /* HAL_PCD_MODULE_ENABLED */\r
-\r
-#ifdef HAL_HCD_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_hcd.h"\r
-#endif /* HAL_HCD_MODULE_ENABLED */\r
-\r
-#ifdef HAL_GFXMMU_MODULE_ENABLED\r
-  #include "stm32l4xx_hal_gfxmmu.h"\r
-#endif /* HAL_GFXMMU_MODULE_ENABLED */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-#ifdef  USE_FULL_ASSERT\r
-/**\r
-  * @brief  The assert_param macro is used for function's parameters check.\r
-  * @param  expr: If expr is false, it calls assert_failed function\r
-  *         which reports the name of the source file and the source\r
-  *         line number of the call that failed.\r
-  *         If expr is true, it returns no value.\r
-  * @retval None\r
-  */\r
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))\r
-/* Exported functions ------------------------------------------------------- */\r
-  void assert_failed(char *file, uint32_t line);\r
-#else\r
-  #define assert_param(expr) ((void)0U)\r
-#endif /* USE_FULL_ASSERT */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_CONF_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/stm32l4xx_it.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Inc/stm32l4xx_it.h
deleted file mode 100644 (file)
index 832f37a..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-/* USER CODE BEGIN Header */\r
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_it.h\r
-  * @brief   This file contains the headers of the interrupt handlers.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
- ******************************************************************************\r
-  */\r
-/* USER CODE END Header */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_IT_H\r
-#define __STM32L4xx_IT_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* USER CODE BEGIN ET */\r
-\r
-/* USER CODE END ET */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/* USER CODE BEGIN EC */\r
-\r
-/* USER CODE END EC */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* USER CODE BEGIN EM */\r
-\r
-/* USER CODE END EM */\r
-\r
-/* Exported functions prototypes ---------------------------------------------*/\r
-void NMI_Handler(void);\r
-void HardFault_Handler(void);\r
-void BusFault_Handler(void);\r
-void UsageFault_Handler(void);\r
-void DebugMon_Handler(void);\r
-void EXTI9_5_IRQHandler(void);\r
-void EXTI15_10_IRQHandler(void);\r
-void TIM6_DAC_IRQHandler(void);\r
-/* USER CODE BEGIN EFP */\r
-\r
-/* USER CODE END EFP */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_IT_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/main.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/main.c
deleted file mode 100644 (file)
index cfeb512..0000000
+++ /dev/null
@@ -1,710 +0,0 @@
-/* USER CODE BEGIN Header */\r
-/**\r
-  ******************************************************************************\r
-  * @file           : main.c\r
-  * @brief          : Main program body\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-/* USER CODE END Header */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-#include "app_main.h"\r
-/* USER CODE END Includes */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* USER CODE BEGIN PTD */\r
-\r
-/* USER CODE END PTD */\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-/* USER CODE BEGIN PD */\r
-/* USER CODE END PD */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* USER CODE BEGIN PM */\r
-\r
-/* USER CODE END PM */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-DFSDM_Channel_HandleTypeDef hdfsdm1_channel1;\r
-\r
-I2C_HandleTypeDef hi2c2;\r
-\r
-QSPI_HandleTypeDef hqspi;\r
-\r
-SPI_HandleTypeDef hspi3;\r
-\r
-UART_HandleTypeDef huart1;\r
-UART_HandleTypeDef huart3;\r
-\r
-PCD_HandleTypeDef hpcd_USB_OTG_FS;\r
-\r
-/* USER CODE BEGIN PV */\r
-\r
-/* USER CODE END PV */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-void SystemClock_Config(void);\r
-static void MX_GPIO_Init(void);\r
-static void MX_DFSDM1_Init(void);\r
-static void MX_I2C2_Init(void);\r
-static void MX_QUADSPI_Init(void);\r
-static void MX_SPI3_Init(void);\r
-static void MX_USART1_UART_Init(void);\r
-static void MX_USART3_UART_Init(void);\r
-static void MX_USB_OTG_FS_PCD_Init(void);\r
-/* USER CODE BEGIN PFP */\r
-\r
-/* USER CODE END PFP */\r
-\r
-/* Private user code ---------------------------------------------------------*/\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-\r
-/**\r
-  * @brief  The application entry point.\r
-  * @retval int\r
-  */\r
-int main(void)\r
-{\r
-  /* USER CODE BEGIN 1 */\r
-\r
-  /* USER CODE END 1 */\r
-  \r
-\r
-  /* MCU Configuration--------------------------------------------------------*/\r
-\r
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\r
-  HAL_Init();\r
-\r
-  /* USER CODE BEGIN Init */\r
-\r
-  /* USER CODE END Init */\r
-\r
-  /* Configure the system clock */\r
-  SystemClock_Config();\r
-\r
-  /* USER CODE BEGIN SysInit */\r
-\r
-  /* USER CODE END SysInit */\r
-\r
-  /* Initialize all configured peripherals */\r
-  MX_GPIO_Init();\r
-  MX_DFSDM1_Init();\r
-  MX_I2C2_Init();\r
-  MX_QUADSPI_Init();\r
-  MX_SPI3_Init();\r
-  MX_USART1_UART_Init();\r
-  MX_USART3_UART_Init();\r
-  MX_USB_OTG_FS_PCD_Init();\r
-  /* USER CODE BEGIN 2 */\r
-  /* Call our entry point. */\r
-  app_main();\r
-  /* USER CODE END 2 */\r
-\r
-  /* Infinite loop */\r
-  /* USER CODE BEGIN WHILE */\r
-  while (1)\r
-  {\r
-    /* USER CODE END WHILE */\r
-\r
-    /* USER CODE BEGIN 3 */\r
-  }\r
-  /* USER CODE END 3 */\r
-}\r
-\r
-/**\r
-  * @brief System Clock Configuration\r
-  * @retval None\r
-  */\r
-void SystemClock_Config(void)\r
-{\r
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};\r
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};\r
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};\r
-\r
-  /** Configure LSE Drive Capability \r
-  */\r
-  HAL_PWR_EnableBkUpAccess();\r
-  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);\r
-  /** Initializes the CPU, AHB and APB busses clocks \r
-  */\r
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;\r
-  RCC_OscInitStruct.LSEState = RCC_LSE_ON;\r
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;\r
-  RCC_OscInitStruct.MSICalibrationValue = 0;\r
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;\r
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;\r
-  RCC_OscInitStruct.PLL.PLLM = 1;\r
-  RCC_OscInitStruct.PLL.PLLN = 40;\r
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;\r
-  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;\r
-  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;\r
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /** Initializes the CPU, AHB and APB busses clocks \r
-  */\r
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\r
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;\r
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;\r
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;\r
-\r
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART3\r
-                              |RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_DFSDM1\r
-                              |RCC_PERIPHCLK_USB;\r
-  PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;\r
-  PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;\r
-  PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;\r
-  PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;\r
-  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;\r
-  PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;\r
-  PeriphClkInit.PLLSAI1.PLLSAI1M = 1;\r
-  PeriphClkInit.PLLSAI1.PLLSAI1N = 24;\r
-  PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;\r
-  PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;\r
-  PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;\r
-  PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;\r
-  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /** Configure the main internal regulator output voltage \r
-  */\r
-  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /** Enable MSI Auto calibration \r
-  */\r
-  HAL_RCCEx_EnableMSIPLLMode();\r
-}\r
-\r
-/**\r
-  * @brief DFSDM1 Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_DFSDM1_Init(void)\r
-{\r
-\r
-  /* USER CODE BEGIN DFSDM1_Init 0 */\r
-\r
-  /* USER CODE END DFSDM1_Init 0 */\r
-\r
-  /* USER CODE BEGIN DFSDM1_Init 1 */\r
-\r
-  /* USER CODE END DFSDM1_Init 1 */\r
-  hdfsdm1_channel1.Instance = DFSDM1_Channel1;\r
-  hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;\r
-  hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;\r
-  hdfsdm1_channel1.Init.OutputClock.Divider = 2;\r
-  hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;\r
-  hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;\r
-  hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;\r
-  hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;\r
-  hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;\r
-  hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;\r
-  hdfsdm1_channel1.Init.Awd.Oversampling = 1;\r
-  hdfsdm1_channel1.Init.Offset = 0;\r
-  hdfsdm1_channel1.Init.RightBitShift = 0x00;\r
-  if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /* USER CODE BEGIN DFSDM1_Init 2 */\r
-\r
-  /* USER CODE END DFSDM1_Init 2 */\r
-\r
-}\r
-\r
-/**\r
-  * @brief I2C2 Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_I2C2_Init(void)\r
-{\r
-\r
-  /* USER CODE BEGIN I2C2_Init 0 */\r
-\r
-  /* USER CODE END I2C2_Init 0 */\r
-\r
-  /* USER CODE BEGIN I2C2_Init 1 */\r
-\r
-  /* USER CODE END I2C2_Init 1 */\r
-  hi2c2.Instance = I2C2;\r
-  hi2c2.Init.Timing = 0x10909CEC;\r
-  hi2c2.Init.OwnAddress1 = 0;\r
-  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;\r
-  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;\r
-  hi2c2.Init.OwnAddress2 = 0;\r
-  hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;\r
-  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;\r
-  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;\r
-  if (HAL_I2C_Init(&hi2c2) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /** Configure Analogue filter \r
-  */\r
-  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /** Configure Digital filter \r
-  */\r
-  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /* USER CODE BEGIN I2C2_Init 2 */\r
-\r
-  /* USER CODE END I2C2_Init 2 */\r
-\r
-}\r
-\r
-/**\r
-  * @brief QUADSPI Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_QUADSPI_Init(void)\r
-{\r
-\r
-  /* USER CODE BEGIN QUADSPI_Init 0 */\r
-\r
-  /* USER CODE END QUADSPI_Init 0 */\r
-\r
-  /* USER CODE BEGIN QUADSPI_Init 1 */\r
-\r
-  /* USER CODE END QUADSPI_Init 1 */\r
-  /* QUADSPI parameter configuration*/\r
-  hqspi.Instance = QUADSPI;\r
-  hqspi.Init.ClockPrescaler = 255;\r
-  hqspi.Init.FifoThreshold = 1;\r
-  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE;\r
-  hqspi.Init.FlashSize = 1;\r
-  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;\r
-  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;\r
-  if (HAL_QSPI_Init(&hqspi) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /* USER CODE BEGIN QUADSPI_Init 2 */\r
-\r
-  /* USER CODE END QUADSPI_Init 2 */\r
-\r
-}\r
-\r
-/**\r
-  * @brief SPI3 Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_SPI3_Init(void)\r
-{\r
-\r
-  /* USER CODE BEGIN SPI3_Init 0 */\r
-\r
-  /* USER CODE END SPI3_Init 0 */\r
-\r
-  /* USER CODE BEGIN SPI3_Init 1 */\r
-\r
-  /* USER CODE END SPI3_Init 1 */\r
-  /* SPI3 parameter configuration*/\r
-  hspi3.Instance = SPI3;\r
-  hspi3.Init.Mode = SPI_MODE_MASTER;\r
-  hspi3.Init.Direction = SPI_DIRECTION_2LINES;\r
-  hspi3.Init.DataSize = SPI_DATASIZE_4BIT;\r
-  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;\r
-  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;\r
-  hspi3.Init.NSS = SPI_NSS_SOFT;\r
-  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\r
-  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;\r
-  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;\r
-  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
-  hspi3.Init.CRCPolynomial = 7;\r
-  hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;\r
-  hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;\r
-  if (HAL_SPI_Init(&hspi3) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /* USER CODE BEGIN SPI3_Init 2 */\r
-\r
-  /* USER CODE END SPI3_Init 2 */\r
-\r
-}\r
-\r
-/**\r
-  * @brief USART1 Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_USART1_UART_Init(void)\r
-{\r
-\r
-  /* USER CODE BEGIN USART1_Init 0 */\r
-\r
-  /* USER CODE END USART1_Init 0 */\r
-\r
-  /* USER CODE BEGIN USART1_Init 1 */\r
-\r
-  /* USER CODE END USART1_Init 1 */\r
-  huart1.Instance = USART1;\r
-  huart1.Init.BaudRate = 115200;\r
-  huart1.Init.WordLength = UART_WORDLENGTH_8B;\r
-  huart1.Init.StopBits = UART_STOPBITS_1;\r
-  huart1.Init.Parity = UART_PARITY_NONE;\r
-  huart1.Init.Mode = UART_MODE_TX_RX;\r
-  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;\r
-  huart1.Init.OverSampling = UART_OVERSAMPLING_16;\r
-  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;\r
-  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;\r
-  if (HAL_UART_Init(&huart1) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /* USER CODE BEGIN USART1_Init 2 */\r
-\r
-  /* USER CODE END USART1_Init 2 */\r
-\r
-}\r
-\r
-/**\r
-  * @brief USART3 Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_USART3_UART_Init(void)\r
-{\r
-\r
-  /* USER CODE BEGIN USART3_Init 0 */\r
-\r
-  /* USER CODE END USART3_Init 0 */\r
-\r
-  /* USER CODE BEGIN USART3_Init 1 */\r
-\r
-  /* USER CODE END USART3_Init 1 */\r
-  huart3.Instance = USART3;\r
-  huart3.Init.BaudRate = 115200;\r
-  huart3.Init.WordLength = UART_WORDLENGTH_8B;\r
-  huart3.Init.StopBits = UART_STOPBITS_1;\r
-  huart3.Init.Parity = UART_PARITY_NONE;\r
-  huart3.Init.Mode = UART_MODE_TX_RX;\r
-  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;\r
-  huart3.Init.OverSampling = UART_OVERSAMPLING_16;\r
-  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;\r
-  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;\r
-  if (HAL_UART_Init(&huart3) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /* USER CODE BEGIN USART3_Init 2 */\r
-\r
-  /* USER CODE END USART3_Init 2 */\r
-\r
-}\r
-\r
-/**\r
-  * @brief USB_OTG_FS Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_USB_OTG_FS_PCD_Init(void)\r
-{\r
-\r
-  /* USER CODE BEGIN USB_OTG_FS_Init 0 */\r
-\r
-  /* USER CODE END USB_OTG_FS_Init 0 */\r
-\r
-  /* USER CODE BEGIN USB_OTG_FS_Init 1 */\r
-\r
-  /* USER CODE END USB_OTG_FS_Init 1 */\r
-  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;\r
-  hpcd_USB_OTG_FS.Init.dev_endpoints = 6;\r
-  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;\r
-  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;\r
-  hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;\r
-  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;\r
-  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;\r
-  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;\r
-  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;\r
-  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;\r
-  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)\r
-  {\r
-    Error_Handler();\r
-  }\r
-  /* USER CODE BEGIN USB_OTG_FS_Init 2 */\r
-\r
-  /* USER CODE END USB_OTG_FS_Init 2 */\r
-\r
-}\r
-\r
-/**\r
-  * @brief GPIO Initialization Function\r
-  * @param None\r
-  * @retval None\r
-  */\r
-static void MX_GPIO_Init(void)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-\r
-  /* GPIO Ports Clock Enable */\r
-  __HAL_RCC_GPIOE_CLK_ENABLE();\r
-  __HAL_RCC_GPIOC_CLK_ENABLE();\r
-  __HAL_RCC_GPIOA_CLK_ENABLE();\r
-  __HAL_RCC_GPIOB_CLK_ENABLE();\r
-  __HAL_RCC_GPIOD_CLK_ENABLE();\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET);\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin \r
-                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET);\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);\r
-\r
-  /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);\r
-\r
-  /*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */\r
-  GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
-  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */\r
-  GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pin : BUTTON_EXTI13_Pin */\r
-  GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin \r
-                           ARD_A1_Pin ARD_A0_Pin */\r
-  GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin \r
-                          |ARD_A1_Pin|ARD_A0_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-  GPIO_InitStruct.Alternate = GPIO_AF8_UART4;\r
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : ARD_D10_Pin SPBTLE_RF_RST_Pin ARD_D9_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pin : ARD_D4_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D4_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
-  GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;\r
-  HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pin : ARD_D7_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D7_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : ARD_D13_Pin ARD_D12_Pin ARD_D11_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin|ARD_D11_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-  GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\r
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pin : ARD_D3_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D3_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pin : ARD_D6_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D6_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin \r
-                           SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin \r
-                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin \r
-                           PMOD_IRQ_EXTI12_Pin */\r
-  GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin \r
-                          |PMOD_IRQ_EXTI12_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */\r
-  GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */\r
-  GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */\r
-  GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pin : PMOD_SPI2_SCK_Pin */\r
-  GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-  GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;\r
-  HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */\r
-  GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-  GPIO_InitStruct.Alternate = GPIO_AF7_USART2;\r
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
-\r
-  /*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */\r
-  GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\r
-  GPIO_InitStruct.Pull = GPIO_PULLUP;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-  GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;\r
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
-\r
-  /* EXTI interrupt init*/\r
-  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);\r
-  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);\r
-\r
-  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);\r
-  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);\r
-\r
-}\r
-\r
-/* USER CODE BEGIN 4 */\r
-\r
-/* USER CODE END 4 */\r
-\r
-/**\r
-  * @brief  Period elapsed callback in non blocking mode\r
-  * @note   This function is called  when TIM6 interrupt took place, inside\r
-  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment\r
-  * a global variable "uwTick" used as application time base.\r
-  * @param  htim : TIM handle\r
-  * @retval None\r
-  */\r
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* USER CODE BEGIN Callback 0 */\r
-\r
-  /* USER CODE END Callback 0 */\r
-  if (htim->Instance == TIM6) {\r
-    HAL_IncTick();\r
-  }\r
-  /* USER CODE BEGIN Callback 1 */\r
-\r
-  /* USER CODE END Callback 1 */\r
-}\r
-\r
-/**\r
-  * @brief  This function is executed in case of error occurrence.\r
-  * @retval None\r
-  */\r
-void Error_Handler(void)\r
-{\r
-  /* USER CODE BEGIN Error_Handler_Debug */\r
-  /* User can add his own implementation to report the HAL error return state */\r
-\r
-  /* USER CODE END Error_Handler_Debug */\r
-}\r
-\r
-#ifdef  USE_FULL_ASSERT\r
-/**\r
-  * @brief  Reports the name of the source file and the source line number\r
-  *         where the assert_param error has occurred.\r
-  * @param  file: pointer to the source file name\r
-  * @param  line: assert_param error line source number\r
-  * @retval None\r
-  */\r
-void assert_failed(char *file, uint32_t line)\r
-{ \r
-  /* USER CODE BEGIN 6 */\r
-  /* User can add his own implementation to report the file name and line number,\r
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
-  /* USER CODE END 6 */\r
-}\r
-#endif /* USE_FULL_ASSERT */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_hal_msp.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_hal_msp.c
deleted file mode 100644 (file)
index a8cea7a..0000000
+++ /dev/null
@@ -1,562 +0,0 @@
-/* USER CODE BEGIN Header */\r
-/**\r
-  ******************************************************************************\r
-  * File Name          : stm32l4xx_hal_msp.c\r
-  * Description        : This file provides code for the MSP Initialization \r
-  *                      and de-Initialization codes.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-/* USER CODE END Header */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* USER CODE BEGIN TD */\r
-\r
-/* USER CODE END TD */\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-/* USER CODE BEGIN Define */\r
\r
-/* USER CODE END Define */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* USER CODE BEGIN Macro */\r
-\r
-/* USER CODE END Macro */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/* USER CODE BEGIN PV */\r
-\r
-/* USER CODE END PV */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* USER CODE BEGIN PFP */\r
-\r
-/* USER CODE END PFP */\r
-\r
-/* External functions --------------------------------------------------------*/\r
-/* USER CODE BEGIN ExternalFunctions */\r
-\r
-/* USER CODE END ExternalFunctions */\r
-\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-/**\r
-  * Initializes the Global MSP.\r
-  */\r
-void HAL_MspInit(void)\r
-{\r
-  /* USER CODE BEGIN MspInit 0 */\r
-\r
-  /* USER CODE END MspInit 0 */\r
-\r
-  __HAL_RCC_SYSCFG_CLK_ENABLE();\r
-  __HAL_RCC_PWR_CLK_ENABLE();\r
-\r
-  /* System interrupt init*/\r
-\r
-  /* USER CODE BEGIN MspInit 1 */\r
-\r
-  /* USER CODE END MspInit 1 */\r
-}\r
-\r
-static uint32_t DFSDM1_Init = 0;\r
-/**\r
-* @brief DFSDM_Channel MSP Initialization\r
-* This function configures the hardware resources used in this example\r
-* @param hdfsdm_channel: DFSDM_Channel handle pointer\r
-* @retval None\r
-*/\r
-void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-  if(DFSDM1_Init == 0)\r
-  {\r
-  /* USER CODE BEGIN DFSDM1_MspInit 0 */\r
-\r
-  /* USER CODE END DFSDM1_MspInit 0 */\r
-    /* Peripheral clock enable */\r
-    __HAL_RCC_DFSDM1_CLK_ENABLE();\r
-  \r
-    __HAL_RCC_GPIOE_CLK_ENABLE();\r
-    /**DFSDM1 GPIO Configuration    \r
-    PE7     ------> DFSDM1_DATIN2\r
-    PE9     ------> DFSDM1_CKOUT \r
-    */\r
-    GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
-    GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;\r
-    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
-\r
-  /* USER CODE BEGIN DFSDM1_MspInit 1 */\r
-\r
-  /* USER CODE END DFSDM1_MspInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief DFSDM_Channel MSP De-Initialization\r
-* This function freeze the hardware resources used in this example\r
-* @param hdfsdm_channel: DFSDM_Channel handle pointer\r
-* @retval None\r
-*/\r
-void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)\r
-{\r
-  DFSDM1_Init-- ;\r
-  if(DFSDM1_Init == 0)\r
-    {\r
-  /* USER CODE BEGIN DFSDM1_MspDeInit 0 */\r
-\r
-  /* USER CODE END DFSDM1_MspDeInit 0 */\r
-    /* Peripheral clock disable */\r
-    __HAL_RCC_DFSDM1_CLK_DISABLE();\r
-  \r
-    /**DFSDM1 GPIO Configuration    \r
-    PE7     ------> DFSDM1_DATIN2\r
-    PE9     ------> DFSDM1_CKOUT \r
-    */\r
-    HAL_GPIO_DeInit(GPIOE, DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin);\r
-\r
-  /* USER CODE BEGIN DFSDM1_MspDeInit 1 */\r
-\r
-  /* USER CODE END DFSDM1_MspDeInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief I2C MSP Initialization\r
-* This function configures the hardware resources used in this example\r
-* @param hi2c: I2C handle pointer\r
-* @retval None\r
-*/\r
-void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-  if(hi2c->Instance==I2C2)\r
-  {\r
-  /* USER CODE BEGIN I2C2_MspInit 0 */\r
-\r
-  /* USER CODE END I2C2_MspInit 0 */\r
-  \r
-    __HAL_RCC_GPIOB_CLK_ENABLE();\r
-    /**I2C2 GPIO Configuration    \r
-    PB10     ------> I2C2_SCL\r
-    PB11     ------> I2C2_SDA \r
-    */\r
-    GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\r
-    GPIO_InitStruct.Pull = GPIO_PULLUP;\r
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;\r
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
-\r
-    /* Peripheral clock enable */\r
-    __HAL_RCC_I2C2_CLK_ENABLE();\r
-  /* USER CODE BEGIN I2C2_MspInit 1 */\r
-\r
-  /* USER CODE END I2C2_MspInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief I2C MSP De-Initialization\r
-* This function freeze the hardware resources used in this example\r
-* @param hi2c: I2C handle pointer\r
-* @retval None\r
-*/\r
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)\r
-{\r
-  if(hi2c->Instance==I2C2)\r
-  {\r
-  /* USER CODE BEGIN I2C2_MspDeInit 0 */\r
-\r
-  /* USER CODE END I2C2_MspDeInit 0 */\r
-    /* Peripheral clock disable */\r
-    __HAL_RCC_I2C2_CLK_DISABLE();\r
-  \r
-    /**I2C2 GPIO Configuration    \r
-    PB10     ------> I2C2_SCL\r
-    PB11     ------> I2C2_SDA \r
-    */\r
-    HAL_GPIO_DeInit(GPIOB, INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin);\r
-\r
-  /* USER CODE BEGIN I2C2_MspDeInit 1 */\r
-\r
-  /* USER CODE END I2C2_MspDeInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief QSPI MSP Initialization\r
-* This function configures the hardware resources used in this example\r
-* @param hqspi: QSPI handle pointer\r
-* @retval None\r
-*/\r
-void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-  if(hqspi->Instance==QUADSPI)\r
-  {\r
-  /* USER CODE BEGIN QUADSPI_MspInit 0 */\r
-\r
-  /* USER CODE END QUADSPI_MspInit 0 */\r
-    /* Peripheral clock enable */\r
-    __HAL_RCC_QSPI_CLK_ENABLE();\r
-  \r
-    __HAL_RCC_GPIOE_CLK_ENABLE();\r
-    /**QUADSPI GPIO Configuration    \r
-    PE10     ------> QUADSPI_CLK\r
-    PE11     ------> QUADSPI_NCS\r
-    PE12     ------> QUADSPI_BK1_IO0\r
-    PE13     ------> QUADSPI_BK1_IO1\r
-    PE14     ------> QUADSPI_BK1_IO2\r
-    PE15     ------> QUADSPI_BK1_IO3 \r
-    */\r
-    GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin \r
-                          |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;\r
-    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r
-\r
-  /* USER CODE BEGIN QUADSPI_MspInit 1 */\r
-\r
-  /* USER CODE END QUADSPI_MspInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief QSPI MSP De-Initialization\r
-* This function freeze the hardware resources used in this example\r
-* @param hqspi: QSPI handle pointer\r
-* @retval None\r
-*/\r
-void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)\r
-{\r
-  if(hqspi->Instance==QUADSPI)\r
-  {\r
-  /* USER CODE BEGIN QUADSPI_MspDeInit 0 */\r
-\r
-  /* USER CODE END QUADSPI_MspDeInit 0 */\r
-    /* Peripheral clock disable */\r
-    __HAL_RCC_QSPI_CLK_DISABLE();\r
-  \r
-    /**QUADSPI GPIO Configuration    \r
-    PE10     ------> QUADSPI_CLK\r
-    PE11     ------> QUADSPI_NCS\r
-    PE12     ------> QUADSPI_BK1_IO0\r
-    PE13     ------> QUADSPI_BK1_IO1\r
-    PE14     ------> QUADSPI_BK1_IO2\r
-    PE15     ------> QUADSPI_BK1_IO3 \r
-    */\r
-    HAL_GPIO_DeInit(GPIOE, QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin \r
-                          |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin);\r
-\r
-  /* USER CODE BEGIN QUADSPI_MspDeInit 1 */\r
-\r
-  /* USER CODE END QUADSPI_MspDeInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief SPI MSP Initialization\r
-* This function configures the hardware resources used in this example\r
-* @param hspi: SPI handle pointer\r
-* @retval None\r
-*/\r
-void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-  if(hspi->Instance==SPI3)\r
-  {\r
-  /* USER CODE BEGIN SPI3_MspInit 0 */\r
-\r
-  /* USER CODE END SPI3_MspInit 0 */\r
-    /* Peripheral clock enable */\r
-    __HAL_RCC_SPI3_CLK_ENABLE();\r
-  \r
-    __HAL_RCC_GPIOC_CLK_ENABLE();\r
-    /**SPI3 GPIO Configuration    \r
-    PC10     ------> SPI3_SCK\r
-    PC11     ------> SPI3_MISO\r
-    PC12     ------> SPI3_MOSI \r
-    */\r
-    GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;\r
-    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r
-\r
-  /* USER CODE BEGIN SPI3_MspInit 1 */\r
-\r
-  /* USER CODE END SPI3_MspInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief SPI MSP De-Initialization\r
-* This function freeze the hardware resources used in this example\r
-* @param hspi: SPI handle pointer\r
-* @retval None\r
-*/\r
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)\r
-{\r
-  if(hspi->Instance==SPI3)\r
-  {\r
-  /* USER CODE BEGIN SPI3_MspDeInit 0 */\r
-\r
-  /* USER CODE END SPI3_MspDeInit 0 */\r
-    /* Peripheral clock disable */\r
-    __HAL_RCC_SPI3_CLK_DISABLE();\r
-  \r
-    /**SPI3 GPIO Configuration    \r
-    PC10     ------> SPI3_SCK\r
-    PC11     ------> SPI3_MISO\r
-    PC12     ------> SPI3_MOSI \r
-    */\r
-    HAL_GPIO_DeInit(GPIOC, INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin);\r
-\r
-  /* USER CODE BEGIN SPI3_MspDeInit 1 */\r
-\r
-  /* USER CODE END SPI3_MspDeInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief UART MSP Initialization\r
-* This function configures the hardware resources used in this example\r
-* @param huart: UART handle pointer\r
-* @retval None\r
-*/\r
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-  if(huart->Instance==USART1)\r
-  {\r
-  /* USER CODE BEGIN USART1_MspInit 0 */\r
-\r
-  /* USER CODE END USART1_MspInit 0 */\r
-    /* Peripheral clock enable */\r
-    __HAL_RCC_USART1_CLK_ENABLE();\r
-  \r
-    __HAL_RCC_GPIOB_CLK_ENABLE();\r
-    /**USART1 GPIO Configuration    \r
-    PB6     ------> USART1_TX\r
-    PB7     ------> USART1_RX \r
-    */\r
-    GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;\r
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
-\r
-  /* USER CODE BEGIN USART1_MspInit 1 */\r
-\r
-  /* USER CODE END USART1_MspInit 1 */\r
-  }\r
-  else if(huart->Instance==USART3)\r
-  {\r
-  /* USER CODE BEGIN USART3_MspInit 0 */\r
-\r
-  /* USER CODE END USART3_MspInit 0 */\r
-    /* Peripheral clock enable */\r
-    __HAL_RCC_USART3_CLK_ENABLE();\r
-  \r
-    __HAL_RCC_GPIOD_CLK_ENABLE();\r
-    /**USART3 GPIO Configuration    \r
-    PD8     ------> USART3_TX\r
-    PD9     ------> USART3_RX \r
-    */\r
-    GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;\r
-    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r
-\r
-  /* USER CODE BEGIN USART3_MspInit 1 */\r
-\r
-  /* USER CODE END USART3_MspInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief UART MSP De-Initialization\r
-* This function freeze the hardware resources used in this example\r
-* @param huart: UART handle pointer\r
-* @retval None\r
-*/\r
-void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)\r
-{\r
-  if(huart->Instance==USART1)\r
-  {\r
-  /* USER CODE BEGIN USART1_MspDeInit 0 */\r
-\r
-  /* USER CODE END USART1_MspDeInit 0 */\r
-    /* Peripheral clock disable */\r
-    __HAL_RCC_USART1_CLK_DISABLE();\r
-  \r
-    /**USART1 GPIO Configuration    \r
-    PB6     ------> USART1_TX\r
-    PB7     ------> USART1_RX \r
-    */\r
-    HAL_GPIO_DeInit(GPIOB, ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin);\r
-\r
-  /* USER CODE BEGIN USART1_MspDeInit 1 */\r
-\r
-  /* USER CODE END USART1_MspDeInit 1 */\r
-  }\r
-  else if(huart->Instance==USART3)\r
-  {\r
-  /* USER CODE BEGIN USART3_MspDeInit 0 */\r
-\r
-  /* USER CODE END USART3_MspDeInit 0 */\r
-    /* Peripheral clock disable */\r
-    __HAL_RCC_USART3_CLK_DISABLE();\r
-  \r
-    /**USART3 GPIO Configuration    \r
-    PD8     ------> USART3_TX\r
-    PD9     ------> USART3_RX \r
-    */\r
-    HAL_GPIO_DeInit(GPIOD, INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin);\r
-\r
-  /* USER CODE BEGIN USART3_MspDeInit 1 */\r
-\r
-  /* USER CODE END USART3_MspDeInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief PCD MSP Initialization\r
-* This function configures the hardware resources used in this example\r
-* @param hpcd: PCD handle pointer\r
-* @retval None\r
-*/\r
-void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-  if(hpcd->Instance==USB_OTG_FS)\r
-  {\r
-  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */\r
-\r
-  /* USER CODE END USB_OTG_FS_MspInit 0 */\r
-  \r
-    __HAL_RCC_GPIOA_CLK_ENABLE();\r
-    /**USB_OTG_FS GPIO Configuration    \r
-    PA9     ------> USB_OTG_FS_VBUS\r
-    PA10     ------> USB_OTG_FS_ID\r
-    PA11     ------> USB_OTG_FS_DM\r
-    PA12     ------> USB_OTG_FS_DP \r
-    */\r
-    GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r
-    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-    HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);\r
-\r
-    GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;\r
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-    GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
-    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;\r
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
-\r
-    /* Peripheral clock enable */\r
-    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r
-\r
-    /* Enable VDDUSB */\r
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
-    {\r
-      __HAL_RCC_PWR_CLK_ENABLE();\r
-      HAL_PWREx_EnableVddUSB();\r
-      __HAL_RCC_PWR_CLK_DISABLE();\r
-    }\r
-    else\r
-    {\r
-      HAL_PWREx_EnableVddUSB();\r
-    }\r
-  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */\r
-\r
-  /* USER CODE END USB_OTG_FS_MspInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/**\r
-* @brief PCD MSP De-Initialization\r
-* This function freeze the hardware resources used in this example\r
-* @param hpcd: PCD handle pointer\r
-* @retval None\r
-*/\r
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)\r
-{\r
-  if(hpcd->Instance==USB_OTG_FS)\r
-  {\r
-  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */\r
-\r
-  /* USER CODE END USB_OTG_FS_MspDeInit 0 */\r
-    /* Peripheral clock disable */\r
-    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();\r
-  \r
-    /**USB_OTG_FS GPIO Configuration    \r
-    PA9     ------> USB_OTG_FS_VBUS\r
-    PA10     ------> USB_OTG_FS_ID\r
-    PA11     ------> USB_OTG_FS_DM\r
-    PA12     ------> USB_OTG_FS_DP \r
-    */\r
-    HAL_GPIO_DeInit(GPIOA, USB_OTG_FS_VBUS_Pin|USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin);\r
-\r
-    /* Disable VDDUSB */\r
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
-    {\r
-      __HAL_RCC_PWR_CLK_ENABLE();\r
-      HAL_PWREx_DisableVddUSB();\r
-      __HAL_RCC_PWR_CLK_DISABLE();\r
-    }\r
-    else\r
-    {\r
-      HAL_PWREx_DisableVddUSB();\r
-    }\r
-  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */\r
-\r
-  /* USER CODE END USB_OTG_FS_MspDeInit 1 */\r
-  }\r
-\r
-}\r
-\r
-/* USER CODE BEGIN 1 */\r
-\r
-/* USER CODE END 1 */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_hal_timebase_tim.c
deleted file mode 100644 (file)
index 47f531b..0000000
+++ /dev/null
@@ -1,114 +0,0 @@
-/* USER CODE BEGIN Header */\r
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_timebase_TIM.c \r
-  * @brief   HAL time base based on the hardware TIM.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-/* USER CODE END Header */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-#include "stm32l4xx_hal_tim.h"\r
\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-TIM_HandleTypeDef        htim6; \r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/**\r
-  * @brief  This function configures the TIM6 as a time base source. \r
-  *         The time source is configured  to have 1ms time base with a dedicated \r
-  *         Tick interrupt priority. \r
-  * @note   This function is called  automatically at the beginning of program after\r
-  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). \r
-  * @param  TickPriority: Tick interrupt priority.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
-{\r
-  RCC_ClkInitTypeDef    clkconfig;\r
-  uint32_t              uwTimclock = 0;\r
-  uint32_t              uwPrescalerValue = 0;\r
-  uint32_t              pFLatency;\r
-  \r
-  /*Configure the TIM6 IRQ priority */\r
-  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0); \r
-  \r
-  /* Enable the TIM6 global Interrupt */\r
-  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); \r
-  \r
-  /* Enable TIM6 clock */\r
-  __HAL_RCC_TIM6_CLK_ENABLE();\r
-  \r
-  /* Get clock configuration */\r
-  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);\r
-  \r
-  /* Compute TIM6 clock */\r
-  uwTimclock = HAL_RCC_GetPCLK1Freq();\r
-   \r
-  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */\r
-  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);\r
-  \r
-  /* Initialize TIM6 */\r
-  htim6.Instance = TIM6;\r
-  \r
-  /* Initialize TIMx peripheral as follow:\r
-  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.\r
-  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.\r
-  + ClockDivision = 0\r
-  + Counter direction = Up\r
-  */\r
-  htim6.Init.Period = (1000000 / 1000) - 1;\r
-  htim6.Init.Prescaler = uwPrescalerValue;\r
-  htim6.Init.ClockDivision = 0;\r
-  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;\r
-  if(HAL_TIM_Base_Init(&htim6) == HAL_OK)\r
-  {\r
-    /* Start the TIM time Base generation in interrupt mode */\r
-    return HAL_TIM_Base_Start_IT(&htim6);\r
-  }\r
-  \r
-  /* Return function status */\r
-  return HAL_ERROR;\r
-}\r
-\r
-/**\r
-  * @brief  Suspend Tick increment.\r
-  * @note   Disable the tick increment by disabling TIM6 update interrupt.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void HAL_SuspendTick(void)\r
-{\r
-  /* Disable TIM6 update Interrupt */\r
-  __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);                                                  \r
-}\r
-\r
-/**\r
-  * @brief  Resume Tick increment.\r
-  * @note   Enable the tick increment by Enabling TIM6 update interrupt.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void HAL_ResumeTick(void)\r
-{\r
-  /* Enable TIM6 Update interrupt */\r
-  __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);\r
-}\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_it.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/stm32l4xx_it.c
deleted file mode 100644 (file)
index f707420..0000000
+++ /dev/null
@@ -1,200 +0,0 @@
-/* USER CODE BEGIN Header */\r
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_it.c\r
-  * @brief   Interrupt Service Routines.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-/* USER CODE END Header */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-#include "stm32l4xx_it.h"\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-/* USER CODE END Includes */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* USER CODE BEGIN TD */\r
-\r
-/* USER CODE END TD */\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-/* USER CODE BEGIN PD */\r
\r
-/* USER CODE END PD */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* USER CODE BEGIN PM */\r
-\r
-/* USER CODE END PM */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/* USER CODE BEGIN PV */\r
-\r
-/* USER CODE END PV */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* USER CODE BEGIN PFP */\r
-\r
-/* USER CODE END PFP */\r
-\r
-/* Private user code ---------------------------------------------------------*/\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-\r
-/* External variables --------------------------------------------------------*/\r
-extern TIM_HandleTypeDef htim6;\r
-\r
-/* USER CODE BEGIN EV */\r
-\r
-/* USER CODE END EV */\r
-\r
-/******************************************************************************/\r
-/*           Cortex-M4 Processor Interruption and Exception Handlers          */ \r
-/******************************************************************************/\r
-/**\r
-  * @brief This function handles Non maskable interrupt.\r
-  */\r
-void NMI_Handler(void)\r
-{\r
-  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */\r
-\r
-  /* USER CODE END NonMaskableInt_IRQn 0 */\r
-  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */\r
-\r
-  /* USER CODE END NonMaskableInt_IRQn 1 */\r
-}\r
-\r
-/**\r
-  * @brief This function handles Hard fault interrupt.\r
-  */\r
-void HardFault_Handler(void)\r
-{\r
-  /* USER CODE BEGIN HardFault_IRQn 0 */\r
-\r
-  /* USER CODE END HardFault_IRQn 0 */\r
-  while (1)\r
-  {\r
-    /* USER CODE BEGIN W1_HardFault_IRQn 0 */\r
-    /* USER CODE END W1_HardFault_IRQn 0 */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief This function handles Prefetch fault, memory access fault.\r
-  */\r
-void BusFault_Handler(void)\r
-{\r
-  /* USER CODE BEGIN BusFault_IRQn 0 */\r
-\r
-  /* USER CODE END BusFault_IRQn 0 */\r
-  while (1)\r
-  {\r
-    /* USER CODE BEGIN W1_BusFault_IRQn 0 */\r
-    /* USER CODE END W1_BusFault_IRQn 0 */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief This function handles Undefined instruction or illegal state.\r
-  */\r
-void UsageFault_Handler(void)\r
-{\r
-  /* USER CODE BEGIN UsageFault_IRQn 0 */\r
-\r
-  /* USER CODE END UsageFault_IRQn 0 */\r
-  while (1)\r
-  {\r
-    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */\r
-    /* USER CODE END W1_UsageFault_IRQn 0 */\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  * @brief This function handles Debug monitor.\r
-  */\r
-void DebugMon_Handler(void)\r
-{\r
-  /* USER CODE BEGIN DebugMonitor_IRQn 0 */\r
-\r
-  /* USER CODE END DebugMonitor_IRQn 0 */\r
-  /* USER CODE BEGIN DebugMonitor_IRQn 1 */\r
-\r
-  /* USER CODE END DebugMonitor_IRQn 1 */\r
-}\r
-\r
-\r
-/******************************************************************************/\r
-/* STM32L4xx Peripheral Interrupt Handlers                                    */\r
-/* Add here the Interrupt Handlers for the used peripherals.                  */\r
-/* For the available peripheral interrupt handler names,                      */\r
-/* please refer to the startup file (startup_stm32l4xx.s).                    */\r
-/******************************************************************************/\r
-\r
-/**\r
-  * @brief This function handles EXTI line[9:5] interrupts.\r
-  */\r
-void EXTI9_5_IRQHandler(void)\r
-{\r
-  /* USER CODE BEGIN EXTI9_5_IRQn 0 */\r
-\r
-  /* USER CODE END EXTI9_5_IRQn 0 */\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);\r
-  /* USER CODE BEGIN EXTI9_5_IRQn 1 */\r
-\r
-  /* USER CODE END EXTI9_5_IRQn 1 */\r
-}\r
-\r
-/**\r
-  * @brief This function handles EXTI line[15:10] interrupts.\r
-  */\r
-void EXTI15_10_IRQHandler(void)\r
-{\r
-  /* USER CODE BEGIN EXTI15_10_IRQn 0 */\r
-\r
-  /* USER CODE END EXTI15_10_IRQn 0 */\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);\r
-  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);\r
-  /* USER CODE BEGIN EXTI15_10_IRQn 1 */\r
-\r
-  /* USER CODE END EXTI15_10_IRQn 1 */\r
-}\r
-\r
-/**\r
-  * @brief This function handles TIM6 global interrupt, DAC channel1 and channel2 underrun error interrupts.\r
-  */\r
-void TIM6_DAC_IRQHandler(void)\r
-{\r
-  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */\r
-\r
-  /* USER CODE END TIM6_DAC_IRQn 0 */\r
-  HAL_TIM_IRQHandler(&htim6);\r
-  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */\r
-\r
-  /* USER CODE END TIM6_DAC_IRQn 1 */\r
-}\r
-\r
-/* USER CODE BEGIN 1 */\r
-\r
-/* USER CODE END 1 */\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/system_stm32l4xx.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Core/Src/system_stm32l4xx.c
deleted file mode 100644 (file)
index 1db59ec..0000000
+++ /dev/null
@@ -1,337 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    system_stm32l4xx.c\r
-  * @author  MCD Application Team\r
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File\r
-  *\r
-  *   This file provides two functions and one global variable to be called from\r
-  *   user application:\r
-  *      - SystemInit(): This function is called at startup just after reset and\r
-  *                      before branch to main program. This call is made inside\r
-  *                      the "startup_stm32l4xx.s" file.\r
-  *\r
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
-  *                                  by the user application to setup the SysTick\r
-  *                                  timer or configure other parameters.\r
-  *\r
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
-  *                                 be called whenever the core clock is changed\r
-  *                                 during program execution.\r
-  *\r
-  *   After each device reset the MSI (4 MHz) is used as system clock source.\r
-  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to\r
-  *   configure the system clock before to branch to main program.\r
-  *\r
-  *   This file configures the system clock as follows:\r
-  *=============================================================================\r
-  *-----------------------------------------------------------------------------\r
-  *        System Clock source                    | MSI\r
-  *-----------------------------------------------------------------------------\r
-  *        SYSCLK(Hz)                             | 4000000\r
-  *-----------------------------------------------------------------------------\r
-  *        HCLK(Hz)                               | 4000000\r
-  *-----------------------------------------------------------------------------\r
-  *        AHB Prescaler                          | 1\r
-  *-----------------------------------------------------------------------------\r
-  *        APB1 Prescaler                         | 1\r
-  *-----------------------------------------------------------------------------\r
-  *        APB2 Prescaler                         | 1\r
-  *-----------------------------------------------------------------------------\r
-  *        PLL_M                                  | 1\r
-  *-----------------------------------------------------------------------------\r
-  *        PLL_N                                  | 8\r
-  *-----------------------------------------------------------------------------\r
-  *        PLL_P                                  | 7\r
-  *-----------------------------------------------------------------------------\r
-  *        PLL_Q                                  | 2\r
-  *-----------------------------------------------------------------------------\r
-  *        PLL_R                                  | 2\r
-  *-----------------------------------------------------------------------------\r
-  *        PLLSAI1_P                              | NA\r
-  *-----------------------------------------------------------------------------\r
-  *        PLLSAI1_Q                              | NA\r
-  *-----------------------------------------------------------------------------\r
-  *        PLLSAI1_R                              | NA\r
-  *-----------------------------------------------------------------------------\r
-  *        PLLSAI2_P                              | NA\r
-  *-----------------------------------------------------------------------------\r
-  *        PLLSAI2_Q                              | NA\r
-  *-----------------------------------------------------------------------------\r
-  *        PLLSAI2_R                              | NA\r
-  *-----------------------------------------------------------------------------\r
-  *        Require 48MHz for USB OTG FS,          | Disabled\r
-  *        SDIO and RNG clock                     |\r
-  *-----------------------------------------------------------------------------\r
-  *=============================================================================\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/** @addtogroup CMSIS\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup stm32l4xx_system\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Private_Includes\r
-  * @{\r
-  */\r
-\r
-#include "stm32l4xx.h"\r
-\r
-#if !defined  (HSE_VALUE)\r
-  #define HSE_VALUE    8000000U  /*!< Value of the External oscillator in Hz */\r
-#endif /* HSE_VALUE */\r
-\r
-#if !defined  (MSI_VALUE)\r
-  #define MSI_VALUE    4000000U  /*!< Value of the Internal oscillator in Hz*/\r
-#endif /* MSI_VALUE */\r
-\r
-#if !defined  (HSI_VALUE)\r
-  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/\r
-#endif /* HSI_VALUE */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Private_TypesDefinitions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Private_Defines\r
-  * @{\r
-  */\r
-\r
-/************************* Miscellaneous Configuration ************************/\r
-/*!< Uncomment the following line if you need to relocate your vector Table in\r
-     Internal SRAM. */\r
-/* #define VECT_TAB_SRAM */\r
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.\r
-                                   This value must be a multiple of 0x200. */\r
-/******************************************************************************/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Private_Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Private_Variables\r
-  * @{\r
-  */\r
-  /* The SystemCoreClock variable is updated in three ways:\r
-      1) by calling CMSIS function SystemCoreClockUpdate()\r
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
-         Note: If you use this function to configure the system clock; then there\r
-               is no need to call the 2 first functions listed above, since SystemCoreClock\r
-               variable is updated automatically.\r
-  */\r
-  uint32_t SystemCoreClock = 4000000U;\r
-\r
-  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};\r
-  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};\r
-  const uint32_t MSIRangeTable[12] = {100000U,   200000U,   400000U,   800000U,  1000000U,  2000000U, \\r
-                                      4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Private_Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Setup the microcontroller system.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-\r
-void SystemInit(void)\r
-{\r
-  /* FPU settings ------------------------------------------------------------*/\r
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\r
-  #endif\r
-\r
-  /* Reset the RCC clock configuration to the default reset state ------------*/\r
-  /* Set MSION bit */\r
-  RCC->CR |= RCC_CR_MSION;\r
-\r
-  /* Reset CFGR register */\r
-  RCC->CFGR = 0x00000000U;\r
-\r
-  /* Reset HSEON, CSSON , HSION, and PLLON bits */\r
-  RCC->CR &= 0xEAF6FFFFU;\r
-\r
-  /* Reset PLLCFGR register */\r
-  RCC->PLLCFGR = 0x00001000U;\r
-\r
-  /* Reset HSEBYP bit */\r
-  RCC->CR &= 0xFFFBFFFFU;\r
-\r
-  /* Disable all interrupts */\r
-  RCC->CIER = 0x00000000U;\r
-\r
-  /* Configure the Vector Table location add offset address ------------------*/\r
-#ifdef VECT_TAB_SRAM\r
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
-#else\r
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.\r
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can\r
-  *         be used by the user application to setup the SysTick timer or configure\r
-  *         other parameters.\r
-  *\r
-  * @note   Each time the core clock (HCLK) changes, this function must be called\r
-  *         to update SystemCoreClock variable value. Otherwise, any configuration\r
-  *         based on this variable will be incorrect.\r
-  *\r
-  * @note   - The system frequency computed by this function is not the real\r
-  *           frequency in the chip. It is calculated based on the predefined\r
-  *           constant and the selected clock source:\r
-  *\r
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)\r
-  *\r
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)\r
-  *\r
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)\r
-  *\r
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)\r
-  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.\r
-  *\r
-  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
-  *             4 MHz) but the real value may vary depending on the variations\r
-  *             in voltage and temperature.\r
-  *\r
-  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
-  *              16 MHz) but the real value may vary depending on the variations\r
-  *              in voltage and temperature.\r
-  *\r
-  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real\r
-  *              frequency of the crystal used. Otherwise, this function may\r
-  *              have wrong result.\r
-  *\r
-  *         - The result of this function could be not correct when using fractional\r
-  *           value for HSE crystal.\r
-  *\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void SystemCoreClockUpdate(void)\r
-{\r
-  uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;\r
-\r
-  /* Get MSI Range frequency--------------------------------------------------*/\r
-  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)\r
-  { /* MSISRANGE from RCC_CSR applies */\r
-    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;\r
-  }\r
-  else\r
-  { /* MSIRANGE from RCC_CR applies */\r
-    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;\r
-  }\r
-  /*MSI frequency range in HZ*/\r
-  msirange = MSIRangeTable[msirange];\r
-\r
-  /* Get SYSCLK source -------------------------------------------------------*/\r
-  switch (RCC->CFGR & RCC_CFGR_SWS)\r
-  {\r
-    case 0x00:  /* MSI used as system clock source */\r
-      SystemCoreClock = msirange;\r
-      break;\r
-\r
-    case 0x04:  /* HSI used as system clock source */\r
-      SystemCoreClock = HSI_VALUE;\r
-      break;\r
-\r
-    case 0x08:  /* HSE used as system clock source */\r
-      SystemCoreClock = HSE_VALUE;\r
-      break;\r
-\r
-    case 0x0C:  /* PLL used as system clock  source */\r
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN\r
-         SYSCLK = PLL_VCO / PLLR\r
-         */\r
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r
-      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;\r
-\r
-      switch (pllsource)\r
-      {\r
-        case 0x02:  /* HSI used as PLL clock source */\r
-          pllvco = (HSI_VALUE / pllm);\r
-          break;\r
-\r
-        case 0x03:  /* HSE used as PLL clock source */\r
-          pllvco = (HSE_VALUE / pllm);\r
-          break;\r
-\r
-        default:    /* MSI used as PLL clock source */\r
-          pllvco = (msirange / pllm);\r
-          break;\r
-      }\r
-      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);\r
-      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;\r
-      SystemCoreClock = pllvco/pllr;\r
-      break;\r
-\r
-    default:\r
-      SystemCoreClock = msirange;\r
-      break;\r
-  }\r
-  /* Compute HCLK clock frequency --------------------------------------------*/\r
-  /* Get HCLK prescaler */\r
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];\r
-  /* HCLK clock frequency */\r
-  SystemCoreClock >>= tmp;\r
-}\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h
deleted file mode 100644 (file)
index cc1a05a..0000000
+++ /dev/null
@@ -1,18327 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l475xx.h\r
-  * @author  MCD Application Team\r
-  * @brief   CMSIS STM32L475xx Device Peripheral Access Layer Header File.\r
-  *\r
-  *          This file contains:\r
-  *           - Data structures and the address mapping for all peripherals\r
-  *           - Peripheral's registers declarations and bits definition\r
-  *           - Macros to access peripheral\92s registers hardware\r
-  *\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/** @addtogroup CMSIS_Device\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup stm32l475xx\r
-  * @{\r
-  */\r
-\r
-#ifndef __STM32L475xx_H\r
-#define __STM32L475xx_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif /* __cplusplus */\r
-\r
-/** @addtogroup Configuration_section_for_CMSIS\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
-   */\r
-#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */\r
-#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */\r
-#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */\r
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\r
-#define __FPU_PRESENT             1       /*!< FPU present                                   */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup Peripheral_interrupt_number_definition\r
-  * @{\r
-  */\r
-\r
-/**\r
- * @brief STM32L4XX Interrupt Number Definition, according to the selected device\r
- *        in @ref Library_configuration_section\r
- */\r
-typedef enum\r
-{\r
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\r
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */\r
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */\r
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\r
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\r
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\r
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\r
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\r
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\r
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\r
-/******  STM32 specific Interrupt Numbers **********************************************************************/\r
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\r
-  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */\r
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\r
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\r
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\r
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\r
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\r
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\r
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\r
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\r
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\r
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */\r
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */\r
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */\r
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */\r
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */\r
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */\r
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */\r
-  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */\r
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\r
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\r
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\r
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\r
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\r
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */\r
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */\r
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */\r
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\r
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\r
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\r
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\r
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\r
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\r
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\r
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\r
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\r
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\r
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\r
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\r
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\r
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\r
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\r
-  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */\r
-  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */\r
-  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */\r
-  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */\r
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\r
-  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */\r
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\r
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\r
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\r
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\r
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\r
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\r
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\r
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\r
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */\r
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */\r
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */\r
-  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */\r
-  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */\r
-  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */\r
-  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */\r
-  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */\r
-  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */\r
-  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */\r
-  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */\r
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\r
-  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */\r
-  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */\r
-  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */\r
-  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */\r
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\r
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\r
-  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */\r
-  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */\r
-  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */\r
-  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */\r
-  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */\r
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */\r
-} IRQn_Type;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */\r
-#include "system_stm32l4xx.h"\r
-#include <stdint.h>\r
-\r
-/** @addtogroup Peripheral_registers_structures\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Analog to Digital Converter\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */\r
-  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */\r
-  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */\r
-  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */\r
-  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */\r
-  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */\r
-  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */\r
-       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */\r
-  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */\r
-  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */\r
-  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */\r
-       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */\r
-  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */\r
-  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */\r
-  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */\r
-  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */\r
-  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */\r
-       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */\r
-       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */\r
-  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */\r
-       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */\r
-  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */\r
-  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */\r
-  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */\r
-  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */\r
-       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */\r
-  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */\r
-  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */\r
-  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */\r
-  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */\r
-       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */\r
-  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */\r
-  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */\r
-       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */\r
-       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */\r
-  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */\r
-  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */\r
-\r
-} ADC_TypeDef;\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */\r
-  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */\r
-  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */\r
-  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */\r
-} ADC_Common_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Controller Area Network TxMailBox\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\r
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
-} CAN_TxMailBox_TypeDef;\r
-\r
-/**\r
-  * @brief Controller Area Network FIFOMailBox\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\r
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
-} CAN_FIFOMailBox_TypeDef;\r
-\r
-/**\r
-  * @brief Controller Area Network FilterRegister\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
-} CAN_FilterRegister_TypeDef;\r
-\r
-/**\r
-  * @brief Controller Area Network\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\r
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\r
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\r
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\r
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\r
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\r
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\r
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\r
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\r
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\r
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\r
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\r
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\r
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\r
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\r
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\r
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\r
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\r
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\r
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\r
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\r
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\r
-} CAN_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Comparator\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */\r
-} COMP_TypeDef;\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\r
-} COMP_Common_TypeDef;\r
-\r
-/**\r
-  * @brief CRC calculation unit\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */\r
-  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\r
-  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */\r
-  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */\r
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */\r
-  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */\r
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\r
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\r
-} CRC_TypeDef;\r
-\r
-/**\r
-  * @brief Digital to Analog Converter\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */\r
-  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */\r
-  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
-  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\r
-  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\r
-  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
-  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\r
-  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\r
-  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\r
-  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\r
-  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\r
-  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */\r
-  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */\r
-  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */\r
-  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */\r
-  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */\r
-  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */\r
-  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */\r
-  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */\r
-  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */\r
-} DAC_TypeDef;\r
-\r
-/**\r
-  * @brief DFSDM module registers\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */\r
-  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */\r
-  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\r
-  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\r
-  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\r
-  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */\r
-  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */\r
-  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */\r
-  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\r
-  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\r
-  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\r
-  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\r
-  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\r
-  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\r
-  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */\r
-} DFSDM_Filter_TypeDef;\r
-\r
-/**\r
-  * @brief DFSDM channel configuration registers\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\r
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\r
-  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and\r
-                                  short circuit detector register,                  Address offset: 0x08 */\r
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\r
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */\r
-} DFSDM_Channel_TypeDef;\r
-\r
-/**\r
-  * @brief Debug MCU\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */\r
-  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */\r
-  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */\r
-  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */\r
-  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */\r
-} DBGMCU_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief DMA Controller\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */\r
-  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */\r
-  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */\r
-  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */\r
-} DMA_Channel_TypeDef;\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */\r
-  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */\r
-} DMA_TypeDef;\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSELR;       /*!< DMA channel selection register              */\r
-} DMA_Request_TypeDef;\r
-\r
-/* Legacy define */\r
-#define DMA_request_TypeDef  DMA_Request_TypeDef\r
-\r
-\r
-/**\r
-  * @brief External Interrupt/Event Controller\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */\r
-  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */\r
-  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */\r
-  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */\r
-  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */\r
-  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */\r
-  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */\r
-  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */\r
-  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */\r
-  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */\r
-  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */\r
-  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */\r
-  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */\r
-  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */\r
-} EXTI_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Firewall\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */\r
-  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */\r
-  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */\r
-  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */\r
-  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */\r
-  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */\r
-  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */\r
-  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */\r
-  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */\r
-} FIREWALL_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief FLASH Registers\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */\r
-  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */\r
-  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */\r
-  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */\r
-  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */\r
-  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */\r
-  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */\r
-  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */\r
-  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */\r
-  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */\r
-  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */\r
-  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */\r
-  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */\r
-       uint32_t RESERVED2[4];     /*!< Reserved2,                           Address offset: 0x34-0x40 */\r
-  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */\r
-  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */\r
-  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */\r
-  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */\r
-} FLASH_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Flexible Memory Controller\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r
-} FMC_Bank1_TypeDef;\r
-\r
-/**\r
-  * @brief Flexible Memory Controller Bank1E\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
-} FMC_Bank1E_TypeDef;\r
-\r
-/**\r
-  * @brief Flexible Memory Controller Bank3\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */\r
-  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */\r
-  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */\r
-  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */\r
-  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */\r
-} FMC_Bank3_TypeDef;\r
-\r
-/**\r
-  * @brief General Purpose I/O\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */\r
-  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */\r
-  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */\r
-  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\r
-  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */\r
-  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */\r
-  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */\r
-  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */\r
-  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\r
-  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */\r
-  __IO uint32_t ASCR;        /*!< GPIO analog switch control register,   Address offset: 0x2C     */\r
-\r
-} GPIO_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Inter-integrated Circuit Interface\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */\r
-  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */\r
-  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */\r
-  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */\r
-  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */\r
-  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */\r
-  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
-  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */\r
-  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */\r
-  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */\r
-  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */\r
-} I2C_TypeDef;\r
-\r
-/**\r
-  * @brief Independent WATCHDOG\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */\r
-  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */\r
-  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */\r
-  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */\r
-  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */\r
-} IWDG_TypeDef;\r
-\r
-/**\r
-  * @brief LPTIMER\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\r
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\r
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\r
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */\r
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */\r
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */\r
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\r
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */\r
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */\r
-} LPTIM_TypeDef;\r
-\r
-/**\r
-  * @brief Operational Amplifier (OPAMP)\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */\r
-  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */\r
-  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */\r
-} OPAMP_TypeDef;\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */\r
-} OPAMP_Common_TypeDef;\r
-\r
-/**\r
-  * @brief Power Control\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */\r
-  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */\r
-  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */\r
-  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */\r
-  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */\r
-  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */\r
-  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */\r
-  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */\r
-  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */\r
-  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */\r
-  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */\r
-  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */\r
-  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */\r
-  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */\r
-  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */\r
-  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */\r
-  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */\r
-  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */\r
-  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */\r
-  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */\r
-  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */\r
-  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */\r
-  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */\r
-  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */\r
-} PWR_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief QUAD Serial Peripheral Interface\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */\r
-  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\r
-  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */\r
-  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\r
-  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\r
-  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\r
-  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */\r
-  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\r
-  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */\r
-  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\r
-  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\r
-  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\r
-  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\r
-} QUADSPI_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Reset and Clock Control\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */\r
-  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */\r
-  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */\r
-  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */\r
-  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */\r
-  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */\r
-  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */\r
-  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */\r
-  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */\r
-  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */\r
-  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */\r
-  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */\r
-  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */\r
-  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */\r
-  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */\r
-  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */\r
-  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */\r
-  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */\r
-  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */\r
-  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */\r
-  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */\r
-  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */\r
-  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */\r
-  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */\r
-  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */\r
-  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */\r
-  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */\r
-  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */\r
-  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */\r
-  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */\r
-  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */\r
-  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */\r
-  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */\r
-  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */\r
-  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */\r
-  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */\r
-  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */\r
-  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */\r
-} RCC_TypeDef;\r
-\r
-/**\r
-  * @brief Real-Time Clock\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */\r
-  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */\r
-  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */\r
-  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */\r
-  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */\r
-  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\r
-       uint32_t reserved;    /*!< Reserved  */\r
-  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */\r
-  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */\r
-  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */\r
-  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */\r
-  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */\r
-  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */\r
-  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */\r
-  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\r
-  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */\r
-  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */\r
-  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\r
-  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\r
-  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */\r
-  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */\r
-  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */\r
-  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */\r
-  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */\r
-  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */\r
-  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */\r
-  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */\r
-  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */\r
-  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */\r
-  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */\r
-  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */\r
-  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */\r
-  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */\r
-  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */\r
-  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */\r
-  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */\r
-  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */\r
-  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */\r
-  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */\r
-  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */\r
-  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */\r
-  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */\r
-  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */\r
-  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */\r
-  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */\r
-  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */\r
-  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */\r
-  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */\r
-  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */\r
-  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */\r
-  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */\r
-  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */\r
-} RTC_TypeDef;\r
-\r
-/**\r
-  * @brief Serial Audio Interface\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */\r
-} SAI_TypeDef;\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */\r
-  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */\r
-  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
-  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */\r
-  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\r
-  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */\r
-  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */\r
-  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */\r
-} SAI_Block_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Secure digital input/output Interface\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */\r
-  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */\r
-  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */\r
-  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */\r
-  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */\r
-  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */\r
-  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */\r
-  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */\r
-  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */\r
-  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */\r
-  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */\r
-  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */\r
-  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */\r
-  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */\r
-  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */\r
-  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */\r
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */\r
-  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */\r
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */\r
-  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */\r
-} SDMMC_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Serial Peripheral Interface\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */\r
-  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */\r
-  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */\r
-  __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */\r
-  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */\r
-  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */\r
-  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */\r
-} SPI_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Single Wire Protocol Master Interface SPWMI\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */\r
-  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */\r
-    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */\r
-  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */\r
-  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */\r
-  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */\r
-  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */\r
-  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */\r
-  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */\r
-  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */\r
-} SWPMI_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief System configuration controller\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\r
-  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */\r
-  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
-  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */\r
-  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */\r
-  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */\r
-  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */\r
-} SYSCFG_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief TIM\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */\r
-  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */\r
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */\r
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */\r
-  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */\r
-  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */\r
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */\r
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */\r
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */\r
-  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */\r
-  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */\r
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */\r
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */\r
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */\r
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */\r
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */\r
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */\r
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */\r
-  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */\r
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */\r
-  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */\r
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\r
-  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */\r
-  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */\r
-  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */\r
-  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */\r
-} TIM_TypeDef;\r
-\r
-\r
-/**\r
-  * @brief Touch Sensing Controller (TSC)\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */\r
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */\r
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */\r
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */\r
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */\r
-  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */\r
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */\r
-  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */\r
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */\r
-  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */\r
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */\r
-  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */\r
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */\r
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */\r
-} TSC_TypeDef;\r
-\r
-/**\r
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */\r
-  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */\r
-  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */\r
-  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */\r
-  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\r
-  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */\r
-  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */\r
-  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */\r
-  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */\r
-  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */\r
-  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\r
-  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */\r
-  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */\r
-  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */\r
-  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */\r
-} USART_TypeDef;\r
-\r
-/**\r
-  * @brief VREFBUF\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */\r
-  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */\r
-} VREFBUF_TypeDef;\r
-\r
-/**\r
-  * @brief Window WATCHDOG\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */\r
-  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */\r
-  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */\r
-} WWDG_TypeDef;\r
-\r
-/**\r
-  * @brief RNG\r
-  */\r
-\r
-typedef struct\r
-{\r
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\r
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\r
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\r
-} RNG_TypeDef;\r
-\r
-/**\r
-  * @brief USB_OTG_Core_register\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/\r
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/\r
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/\r
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/\r
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/\r
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/\r
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/\r
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/\r
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/\r
-  __IO uint32_t GRXFSIZ;              /*!<  Receive FIFO Size Register                   024h*/\r
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/\r
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/\r
-  uint32_t Reserved30[2];             /*!<  Reserved                                     030h*/\r
-  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register                  038h*/\r
-  __IO uint32_t CID;                  /*!<  User ID Register                             03Ch*/\r
-  __IO uint32_t GSNPSID;              /*!<  USB_OTG core ID                              040h*/\r
-  __IO uint32_t GHWCFG1;              /*!<  User HW config1                              044h*/\r
-  __IO uint32_t GHWCFG2;              /*!<  User HW config2                              048h*/\r
-  __IO uint32_t GHWCFG3;              /*!<  User HW config3                              04Ch*/\r
-  uint32_t  Reserved6;                /*!<  Reserved                                     050h*/\r
-  __IO uint32_t GLPMCFG;              /*!<  LPM Register                                 054h*/\r
-  __IO uint32_t GPWRDN;               /*!<  Power Down Register                          058h*/\r
-  __IO uint32_t GDFIFOCFG;            /*!<  DFIFO Software Config Register               05Ch*/\r
-   __IO uint32_t GADPCTL;             /*!<  ADP Timer, Control and Status Register       060h*/\r
-    uint32_t  Reserved43[39];         /*!<  Reserved                                064h-0FFh*/\r
-  __IO uint32_t HPTXFSIZ;             /*!<  Host Periodic Tx FIFO Size Reg               100h*/\r
-  __IO uint32_t DIEPTXF[0x0F];        /*!<  dev Periodic Transmit FIFO */\r
-} USB_OTG_GlobalTypeDef;\r
-\r
-/**\r
-  * @brief USB_OTG_device_Registers\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/\r
-  __IO uint32_t DCTL;        /* dev Control Register         804h*/\r
-  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/\r
-  uint32_t Reserved0C;       /* Reserved                     80Ch*/\r
-  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/\r
-  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/\r
-  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/\r
-  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/\r
-  uint32_t Reserved20;       /* Reserved                     820h*/\r
-  uint32_t Reserved24;       /* Reserved                     824h*/\r
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/\r
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/\r
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/\r
-  __IO uint32_t DIEPEMPMSK;  /* dev empty msk                834h*/\r
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/\r
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/\r
-  uint32_t Reserved40;       /* Reserved                     840h*/\r
-  __IO uint32_t DINEP1MSK;   /* dedicated EP mask            844h*/\r
-  uint32_t  Reserved44[15];  /* Reserved                 848-880h*/\r
-  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk             884h*/\r
-} USB_OTG_DeviceTypeDef;\r
-\r
-/**\r
-  * @brief USB_OTG_IN_Endpoint-Specific_Register\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/\r
-  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/\r
-  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/\r
-  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/\r
-  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/\r
-  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/\r
-  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/\r
-  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/\r
-} USB_OTG_INEndpointTypeDef;\r
-\r
-/**\r
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/\r
-  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/\r
-  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/\r
-  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/\r
-  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/\r
-  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/\r
-  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/\r
-} USB_OTG_OUTEndpointTypeDef;\r
-\r
-/**\r
-  * @brief USB_OTG_Host_Mode_Register_Structures\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/\r
-  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/\r
-  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/\r
-  uint32_t Reserved40C;      /* Reserved                       40Ch*/\r
-  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/\r
-  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/\r
-  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/\r
-} USB_OTG_HostTypeDef;\r
-\r
-/**\r
-  * @brief USB_OTG_Host_Channel_Specific_Registers\r
-  */\r
-typedef struct\r
-{\r
-  __IO uint32_t HCCHAR;\r
-  __IO uint32_t HCSPLT;\r
-  __IO uint32_t HCINT;\r
-  __IO uint32_t HCINTMSK;\r
-  __IO uint32_t HCTSIZ;\r
-  __IO uint32_t HCDMA;\r
-  uint32_t Reserved[2];\r
-} USB_OTG_HostChannelTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup Peripheral_memory_map\r
-  * @{\r
-  */\r
-#define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 1 MB) base address */\r
-#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */\r
-#define SRAM2_BASE            (0x10000000UL) /*!< SRAM2(32 KB) base address */\r
-#define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */\r
-#define FMC_BASE              (0x60000000UL) /*!< FMC base address */\r
-#define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */\r
-\r
-#define FMC_R_BASE            (0xA0000000UL) /*!< FMC  control registers base address */\r
-#define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */\r
-#define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */\r
-#define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */\r
-\r
-/* Legacy defines */\r
-#define SRAM_BASE             SRAM1_BASE\r
-#define SRAM_BB_BASE          SRAM1_BB_BASE\r
-\r
-#define SRAM1_SIZE_MAX        (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */\r
-#define SRAM2_SIZE            (0x00008000UL) /*!< SRAM2 size (32 KBytes) */\r
-\r
-/*!< Peripheral memory map */\r
-#define APB1PERIPH_BASE        PERIPH_BASE\r
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\r
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\r
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)\r
-\r
-#define FMC_BANK1             FMC_BASE\r
-#define FMC_BANK1_1           FMC_BANK1\r
-#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000UL)\r
-#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000UL)\r
-#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000UL)\r
-#define FMC_BANK3             (FMC_BASE  + 0x20000000UL)\r
-\r
-/*!< APB1 peripherals */\r
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\r
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\r
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\r
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\r
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\r
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\r
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\r
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\r
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\r
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\r
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\r
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\r
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\r
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)\r
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)\r
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\r
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\r
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\r
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\r
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\r
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)\r
-#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)\r
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)\r
-#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)\r
-#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810UL)\r
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)\r
-#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)\r
-#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800UL)\r
-#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)\r
-\r
-\r
-/*!< APB2 peripherals */\r
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)\r
-#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)\r
-#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)\r
-#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)\r
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)\r
-#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)\r
-#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800UL)\r
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)\r
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\r
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)\r
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)\r
-#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)\r
-#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)\r
-#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)\r
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)\r
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)\r
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)\r
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800UL)\r
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x0004UL)\r
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x0024UL)\r
-#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000UL)\r
-#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x0000UL)\r
-#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x0020UL)\r
-#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x0040UL)\r
-#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x0060UL)\r
-#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x0080UL)\r
-#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0x00A0UL)\r
-#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0x00C0UL)\r
-#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0x00E0UL)\r
-#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x0100UL)\r
-#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x0180UL)\r
-#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x0200UL)\r
-#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x0280UL)\r
-\r
-/*!< AHB1 peripherals */\r
-#define DMA1_BASE             (AHB1PERIPH_BASE)\r
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)\r
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)\r
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)\r
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\r
-#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)\r
-\r
-\r
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)\r
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)\r
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)\r
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)\r
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)\r
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)\r
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)\r
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)\r
-\r
-\r
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)\r
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)\r
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)\r
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)\r
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)\r
-#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)\r
-#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)\r
-#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)\r
-\r
-\r
-/*!< AHB2 peripherals */\r
-#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)\r
-#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)\r
-#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)\r
-#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)\r
-#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)\r
-#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)\r
-#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)\r
-#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)\r
-\r
-#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000UL)\r
-\r
-#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)\r
-#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100UL)\r
-#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200UL)\r
-#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300UL)\r
-\r
-\r
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)\r
-\r
-\r
-/*!< FMC Banks registers base  address */\r
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)\r
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)\r
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)\r
-\r
-/* Debug MCU registers base address */\r
-#define DBGMCU_BASE           (0xE0042000UL)\r
-\r
-/*!< USB registers base address */\r
-#define USB_OTG_FS_PERIPH_BASE               (0x50000000UL)\r
-\r
-#define USB_OTG_GLOBAL_BASE                  (0x00000000UL)\r
-#define USB_OTG_DEVICE_BASE                  (0x00000800UL)\r
-#define USB_OTG_IN_ENDPOINT_BASE             (0x00000900UL)\r
-#define USB_OTG_OUT_ENDPOINT_BASE            (0x00000B00UL)\r
-#define USB_OTG_EP_REG_SIZE                  (0x00000020UL)\r
-#define USB_OTG_HOST_BASE                    (0x00000400UL)\r
-#define USB_OTG_HOST_PORT_BASE               (0x00000440UL)\r
-#define USB_OTG_HOST_CHANNEL_BASE            (0x00000500UL)\r
-#define USB_OTG_HOST_CHANNEL_SIZE            (0x00000020UL)\r
-#define USB_OTG_PCGCCTL_BASE                 (0x00000E00UL)\r
-#define USB_OTG_FIFO_BASE                    (0x00001000UL)\r
-#define USB_OTG_FIFO_SIZE                    (0x00001000UL)\r
-\r
-\r
-#define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */\r
-#define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */\r
-#define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup Peripheral_declaration\r
-  * @{\r
-  */\r
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\r
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\r
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\r
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\r
-#define USART2              ((USART_TypeDef *) USART2_BASE)\r
-#define USART3              ((USART_TypeDef *) USART3_BASE)\r
-#define UART4               ((USART_TypeDef *) UART4_BASE)\r
-#define UART5               ((USART_TypeDef *) UART5_BASE)\r
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\r
-#define CAN                 ((CAN_TypeDef *) CAN1_BASE)\r
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\r
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r
-#define DAC                 ((DAC_TypeDef *) DAC1_BASE)\r
-#define DAC1                ((DAC_TypeDef *) DAC1_BASE)\r
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)\r
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)\r
-#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)\r
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)\r
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\r
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)\r
-#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)\r
-#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)\r
-\r
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
-#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)\r
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)\r
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)\r
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)\r
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)\r
-#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)\r
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\r
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\r
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\r
-#define USART1              ((USART_TypeDef *) USART1_BASE)\r
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)\r
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\r
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\r
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\r
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)\r
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
-#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\r
-#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\r
-#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\r
-#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\r
-#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\r
-#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\r
-#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\r
-#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\r
-#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\r
-#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\r
-#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\r
-#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\r
-/* Aliases to keep compatibility after DFSDM renaming */\r
-#define DFSDM_Channel0      DFSDM1_Channel0\r
-#define DFSDM_Channel1      DFSDM1_Channel1\r
-#define DFSDM_Channel2      DFSDM1_Channel2\r
-#define DFSDM_Channel3      DFSDM1_Channel3\r
-#define DFSDM_Channel4      DFSDM1_Channel4\r
-#define DFSDM_Channel5      DFSDM1_Channel5\r
-#define DFSDM_Channel6      DFSDM1_Channel6\r
-#define DFSDM_Channel7      DFSDM1_Channel7\r
-#define DFSDM_Filter0       DFSDM1_Filter0\r
-#define DFSDM_Filter1       DFSDM1_Filter1\r
-#define DFSDM_Filter2       DFSDM1_Filter2\r
-#define DFSDM_Filter3       DFSDM1_Filter3\r
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\r
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)\r
-\r
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\r
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\r
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\r
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\r
-#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\r
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)\r
-\r
-\r
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)\r
-\r
-\r
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\r
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\r
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\r
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\r
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\r
-#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)\r
-#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)\r
-#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)\r
-\r
-\r
-#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
-#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
-#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
-\r
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
-\r
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
-\r
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup Exported_constants\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup Peripheral_Registers_Bits_Definition\r
-  * @{\r
-  */\r
-\r
-/******************************************************************************/\r
-/*                         Peripheral Registers_Bits_Definition               */\r
-/******************************************************************************/\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                        Analog to Digital Converter                         */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-\r
-/*\r
- * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)\r
- */\r
-#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\r
-\r
-/********************  Bit definition for ADC_ISR register  *******************/\r
-#define ADC_ISR_ADRDY_Pos              (0U)\r
-#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */\r
-#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */\r
-#define ADC_ISR_EOSMP_Pos              (1U)\r
-#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */\r
-#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */\r
-#define ADC_ISR_EOC_Pos                (2U)\r
-#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */\r
-#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */\r
-#define ADC_ISR_EOS_Pos                (3U)\r
-#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */\r
-#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */\r
-#define ADC_ISR_OVR_Pos                (4U)\r
-#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */\r
-#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */\r
-#define ADC_ISR_JEOC_Pos               (5U)\r
-#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */\r
-#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */\r
-#define ADC_ISR_JEOS_Pos               (6U)\r
-#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */\r
-#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */\r
-#define ADC_ISR_AWD1_Pos               (7U)\r
-#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */\r
-#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */\r
-#define ADC_ISR_AWD2_Pos               (8U)\r
-#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */\r
-#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */\r
-#define ADC_ISR_AWD3_Pos               (9U)\r
-#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */\r
-#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */\r
-#define ADC_ISR_JQOVF_Pos              (10U)\r
-#define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */\r
-#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */\r
-\r
-/********************  Bit definition for ADC_IER register  *******************/\r
-#define ADC_IER_ADRDYIE_Pos            (0U)\r
-#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */\r
-#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */\r
-#define ADC_IER_EOSMPIE_Pos            (1U)\r
-#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */\r
-#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */\r
-#define ADC_IER_EOCIE_Pos              (2U)\r
-#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */\r
-#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */\r
-#define ADC_IER_EOSIE_Pos              (3U)\r
-#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */\r
-#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */\r
-#define ADC_IER_OVRIE_Pos              (4U)\r
-#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */\r
-#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */\r
-#define ADC_IER_JEOCIE_Pos             (5U)\r
-#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */\r
-#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */\r
-#define ADC_IER_JEOSIE_Pos             (6U)\r
-#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */\r
-#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */\r
-#define ADC_IER_AWD1IE_Pos             (7U)\r
-#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */\r
-#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */\r
-#define ADC_IER_AWD2IE_Pos             (8U)\r
-#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */\r
-#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */\r
-#define ADC_IER_AWD3IE_Pos             (9U)\r
-#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */\r
-#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */\r
-#define ADC_IER_JQOVFIE_Pos            (10U)\r
-#define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */\r
-#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */\r
-\r
-/* Legacy defines */\r
-#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)\r
-#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)\r
-#define ADC_IER_EOC             (ADC_IER_EOCIE)\r
-#define ADC_IER_EOS             (ADC_IER_EOSIE)\r
-#define ADC_IER_OVR             (ADC_IER_OVRIE)\r
-#define ADC_IER_JEOC            (ADC_IER_JEOCIE)\r
-#define ADC_IER_JEOS            (ADC_IER_JEOSIE)\r
-#define ADC_IER_AWD1            (ADC_IER_AWD1IE)\r
-#define ADC_IER_AWD2            (ADC_IER_AWD2IE)\r
-#define ADC_IER_AWD3            (ADC_IER_AWD3IE)\r
-#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)\r
-\r
-/********************  Bit definition for ADC_CR register  ********************/\r
-#define ADC_CR_ADEN_Pos                (0U)\r
-#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */\r
-#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */\r
-#define ADC_CR_ADDIS_Pos               (1U)\r
-#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */\r
-#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */\r
-#define ADC_CR_ADSTART_Pos             (2U)\r
-#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */\r
-#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */\r
-#define ADC_CR_JADSTART_Pos            (3U)\r
-#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */\r
-#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */\r
-#define ADC_CR_ADSTP_Pos               (4U)\r
-#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */\r
-#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */\r
-#define ADC_CR_JADSTP_Pos              (5U)\r
-#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */\r
-#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */\r
-#define ADC_CR_ADVREGEN_Pos            (28U)\r
-#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */\r
-#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */\r
-#define ADC_CR_DEEPPWD_Pos             (29U)\r
-#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */\r
-#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */\r
-#define ADC_CR_ADCALDIF_Pos            (30U)\r
-#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */\r
-#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */\r
-#define ADC_CR_ADCAL_Pos               (31U)\r
-#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */\r
-#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */\r
-\r
-/********************  Bit definition for ADC_CFGR register  ******************/\r
-#define ADC_CFGR_DMAEN_Pos             (0U)\r
-#define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */\r
-#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */\r
-#define ADC_CFGR_DMACFG_Pos            (1U)\r
-#define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */\r
-#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */\r
-\r
-#define ADC_CFGR_RES_Pos               (3U)\r
-#define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */\r
-#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */\r
-#define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */\r
-#define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */\r
-\r
-#define ADC_CFGR_ALIGN_Pos             (5U)\r
-#define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00000020 */\r
-#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */\r
-\r
-#define ADC_CFGR_EXTSEL_Pos            (6U)\r
-#define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x000003C0 */\r
-#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */\r
-#define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */\r
-#define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */\r
-#define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */\r
-#define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000200 */\r
-\r
-#define ADC_CFGR_EXTEN_Pos             (10U)\r
-#define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */\r
-#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */\r
-#define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */\r
-#define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */\r
-\r
-#define ADC_CFGR_OVRMOD_Pos            (12U)\r
-#define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */\r
-#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */\r
-#define ADC_CFGR_CONT_Pos              (13U)\r
-#define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */\r
-#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */\r
-#define ADC_CFGR_AUTDLY_Pos            (14U)\r
-#define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */\r
-#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */\r
-\r
-#define ADC_CFGR_DISCEN_Pos            (16U)\r
-#define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */\r
-#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */\r
-\r
-#define ADC_CFGR_DISCNUM_Pos           (17U)\r
-#define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */\r
-#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */\r
-#define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */\r
-#define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */\r
-#define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */\r
-\r
-#define ADC_CFGR_JDISCEN_Pos           (20U)\r
-#define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */\r
-#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */\r
-#define ADC_CFGR_JQM_Pos               (21U)\r
-#define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */\r
-#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */\r
-#define ADC_CFGR_AWD1SGL_Pos           (22U)\r
-#define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */\r
-#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\r
-#define ADC_CFGR_AWD1EN_Pos            (23U)\r
-#define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */\r
-#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */\r
-#define ADC_CFGR_JAWD1EN_Pos           (24U)\r
-#define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */\r
-#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */\r
-#define ADC_CFGR_JAUTO_Pos             (25U)\r
-#define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */\r
-#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */\r
-\r
-#define ADC_CFGR_AWD1CH_Pos            (26U)\r
-#define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */\r
-#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */\r
-#define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */\r
-#define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */\r
-#define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */\r
-#define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */\r
-#define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */\r
-\r
-#define ADC_CFGR_JQDIS_Pos             (31U)\r
-#define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */\r
-#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */\r
-\r
-/********************  Bit definition for ADC_CFGR2 register  *****************/\r
-#define ADC_CFGR2_ROVSE_Pos            (0U)\r
-#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */\r
-#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */\r
-#define ADC_CFGR2_JOVSE_Pos            (1U)\r
-#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */\r
-#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */\r
-\r
-#define ADC_CFGR2_OVSR_Pos             (2U)\r
-#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */\r
-#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */\r
-#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */\r
-#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */\r
-#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */\r
-\r
-#define ADC_CFGR2_OVSS_Pos             (5U)\r
-#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */\r
-#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */\r
-#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */\r
-#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */\r
-#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */\r
-#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */\r
-\r
-#define ADC_CFGR2_TROVS_Pos            (9U)\r
-#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */\r
-#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */\r
-#define ADC_CFGR2_ROVSM_Pos            (10U)\r
-#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */\r
-#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */\r
-\r
-/********************  Bit definition for ADC_SMPR1 register  *****************/\r
-#define ADC_SMPR1_SMP0_Pos             (0U)\r
-#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */\r
-#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */\r
-#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */\r
-#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */\r
-#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */\r
-\r
-#define ADC_SMPR1_SMP1_Pos             (3U)\r
-#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */\r
-#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */\r
-#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */\r
-#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */\r
-#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */\r
-\r
-#define ADC_SMPR1_SMP2_Pos             (6U)\r
-#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */\r
-#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */\r
-#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */\r
-#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */\r
-#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */\r
-\r
-#define ADC_SMPR1_SMP3_Pos             (9U)\r
-#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */\r
-#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */\r
-#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */\r
-#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */\r
-#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */\r
-\r
-#define ADC_SMPR1_SMP4_Pos             (12U)\r
-#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */\r
-#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */\r
-#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */\r
-#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */\r
-#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */\r
-\r
-#define ADC_SMPR1_SMP5_Pos             (15U)\r
-#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */\r
-#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */\r
-#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */\r
-#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */\r
-#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */\r
-\r
-#define ADC_SMPR1_SMP6_Pos             (18U)\r
-#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */\r
-#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */\r
-#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */\r
-#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */\r
-#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */\r
-\r
-#define ADC_SMPR1_SMP7_Pos             (21U)\r
-#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */\r
-#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */\r
-#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */\r
-#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */\r
-#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */\r
-\r
-#define ADC_SMPR1_SMP8_Pos             (24U)\r
-#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */\r
-#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */\r
-#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */\r
-#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */\r
-#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */\r
-\r
-#define ADC_SMPR1_SMP9_Pos             (27U)\r
-#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */\r
-#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */\r
-#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */\r
-#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */\r
-#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */\r
-\r
-/********************  Bit definition for ADC_SMPR2 register  *****************/\r
-#define ADC_SMPR2_SMP10_Pos            (0U)\r
-#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */\r
-#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */\r
-#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */\r
-#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */\r
-#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */\r
-\r
-#define ADC_SMPR2_SMP11_Pos            (3U)\r
-#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */\r
-#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */\r
-#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */\r
-#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */\r
-#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */\r
-\r
-#define ADC_SMPR2_SMP12_Pos            (6U)\r
-#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */\r
-#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */\r
-#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */\r
-#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */\r
-#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */\r
-\r
-#define ADC_SMPR2_SMP13_Pos            (9U)\r
-#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */\r
-#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */\r
-#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */\r
-#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */\r
-#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */\r
-\r
-#define ADC_SMPR2_SMP14_Pos            (12U)\r
-#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */\r
-#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */\r
-#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */\r
-#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */\r
-#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */\r
-\r
-#define ADC_SMPR2_SMP15_Pos            (15U)\r
-#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */\r
-#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */\r
-#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */\r
-#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */\r
-#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */\r
-\r
-#define ADC_SMPR2_SMP16_Pos            (18U)\r
-#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */\r
-#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */\r
-#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */\r
-#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */\r
-#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */\r
-\r
-#define ADC_SMPR2_SMP17_Pos            (21U)\r
-#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */\r
-#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */\r
-#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */\r
-#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */\r
-#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */\r
-\r
-#define ADC_SMPR2_SMP18_Pos            (24U)\r
-#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */\r
-#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */\r
-#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */\r
-#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */\r
-#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */\r
-\r
-/********************  Bit definition for ADC_TR1 register  *******************/\r
-#define ADC_TR1_LT1_Pos                (0U)\r
-#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */\r
-#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */\r
-#define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */\r
-#define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */\r
-#define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */\r
-#define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */\r
-#define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */\r
-#define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */\r
-#define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */\r
-#define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */\r
-#define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */\r
-#define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */\r
-#define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */\r
-#define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */\r
-\r
-#define ADC_TR1_HT1_Pos                (16U)\r
-#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */\r
-#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */\r
-#define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */\r
-#define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */\r
-#define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */\r
-#define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */\r
-#define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */\r
-#define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */\r
-#define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */\r
-#define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */\r
-#define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */\r
-#define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */\r
-#define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */\r
-#define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */\r
-\r
-/********************  Bit definition for ADC_TR2 register  *******************/\r
-#define ADC_TR2_LT2_Pos                (0U)\r
-#define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */\r
-#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */\r
-#define ADC_TR2_LT2_0                  (0x01UL << ADC_TR2_LT2_Pos)             /*!< 0x00000001 */\r
-#define ADC_TR2_LT2_1                  (0x02UL << ADC_TR2_LT2_Pos)             /*!< 0x00000002 */\r
-#define ADC_TR2_LT2_2                  (0x04UL << ADC_TR2_LT2_Pos)             /*!< 0x00000004 */\r
-#define ADC_TR2_LT2_3                  (0x08UL << ADC_TR2_LT2_Pos)             /*!< 0x00000008 */\r
-#define ADC_TR2_LT2_4                  (0x10UL << ADC_TR2_LT2_Pos)             /*!< 0x00000010 */\r
-#define ADC_TR2_LT2_5                  (0x20UL << ADC_TR2_LT2_Pos)             /*!< 0x00000020 */\r
-#define ADC_TR2_LT2_6                  (0x40UL << ADC_TR2_LT2_Pos)             /*!< 0x00000040 */\r
-#define ADC_TR2_LT2_7                  (0x80UL << ADC_TR2_LT2_Pos)             /*!< 0x00000080 */\r
-\r
-#define ADC_TR2_HT2_Pos                (16U)\r
-#define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */\r
-#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */\r
-#define ADC_TR2_HT2_0                  (0x01UL << ADC_TR2_HT2_Pos)             /*!< 0x00010000 */\r
-#define ADC_TR2_HT2_1                  (0x02UL << ADC_TR2_HT2_Pos)             /*!< 0x00020000 */\r
-#define ADC_TR2_HT2_2                  (0x04UL << ADC_TR2_HT2_Pos)             /*!< 0x00040000 */\r
-#define ADC_TR2_HT2_3                  (0x08UL << ADC_TR2_HT2_Pos)             /*!< 0x00080000 */\r
-#define ADC_TR2_HT2_4                  (0x10UL << ADC_TR2_HT2_Pos)             /*!< 0x00100000 */\r
-#define ADC_TR2_HT2_5                  (0x20UL << ADC_TR2_HT2_Pos)             /*!< 0x00200000 */\r
-#define ADC_TR2_HT2_6                  (0x40UL << ADC_TR2_HT2_Pos)             /*!< 0x00400000 */\r
-#define ADC_TR2_HT2_7                  (0x80UL << ADC_TR2_HT2_Pos)             /*!< 0x00800000 */\r
-\r
-/********************  Bit definition for ADC_TR3 register  *******************/\r
-#define ADC_TR3_LT3_Pos                (0U)\r
-#define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */\r
-#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */\r
-#define ADC_TR3_LT3_0                  (0x01UL << ADC_TR3_LT3_Pos)             /*!< 0x00000001 */\r
-#define ADC_TR3_LT3_1                  (0x02UL << ADC_TR3_LT3_Pos)             /*!< 0x00000002 */\r
-#define ADC_TR3_LT3_2                  (0x04UL << ADC_TR3_LT3_Pos)             /*!< 0x00000004 */\r
-#define ADC_TR3_LT3_3                  (0x08UL << ADC_TR3_LT3_Pos)             /*!< 0x00000008 */\r
-#define ADC_TR3_LT3_4                  (0x10UL << ADC_TR3_LT3_Pos)             /*!< 0x00000010 */\r
-#define ADC_TR3_LT3_5                  (0x20UL << ADC_TR3_LT3_Pos)             /*!< 0x00000020 */\r
-#define ADC_TR3_LT3_6                  (0x40UL << ADC_TR3_LT3_Pos)             /*!< 0x00000040 */\r
-#define ADC_TR3_LT3_7                  (0x80UL << ADC_TR3_LT3_Pos)             /*!< 0x00000080 */\r
-\r
-#define ADC_TR3_HT3_Pos                (16U)\r
-#define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */\r
-#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */\r
-#define ADC_TR3_HT3_0                  (0x01UL << ADC_TR3_HT3_Pos)             /*!< 0x00010000 */\r
-#define ADC_TR3_HT3_1                  (0x02UL << ADC_TR3_HT3_Pos)             /*!< 0x00020000 */\r
-#define ADC_TR3_HT3_2                  (0x04UL << ADC_TR3_HT3_Pos)             /*!< 0x00040000 */\r
-#define ADC_TR3_HT3_3                  (0x08UL << ADC_TR3_HT3_Pos)             /*!< 0x00080000 */\r
-#define ADC_TR3_HT3_4                  (0x10UL << ADC_TR3_HT3_Pos)             /*!< 0x00100000 */\r
-#define ADC_TR3_HT3_5                  (0x20UL << ADC_TR3_HT3_Pos)             /*!< 0x00200000 */\r
-#define ADC_TR3_HT3_6                  (0x40UL << ADC_TR3_HT3_Pos)             /*!< 0x00400000 */\r
-#define ADC_TR3_HT3_7                  (0x80UL << ADC_TR3_HT3_Pos)             /*!< 0x00800000 */\r
-\r
-/********************  Bit definition for ADC_SQR1 register  ******************/\r
-#define ADC_SQR1_L_Pos                 (0U)\r
-#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */\r
-#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */\r
-#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */\r
-#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */\r
-#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */\r
-#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */\r
-\r
-#define ADC_SQR1_SQ1_Pos               (6U)\r
-#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */\r
-#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */\r
-#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */\r
-#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */\r
-#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */\r
-#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */\r
-#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */\r
-\r
-#define ADC_SQR1_SQ2_Pos               (12U)\r
-#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */\r
-#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */\r
-#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */\r
-#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */\r
-#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */\r
-#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */\r
-#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */\r
-\r
-#define ADC_SQR1_SQ3_Pos               (18U)\r
-#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */\r
-#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */\r
-#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */\r
-#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */\r
-#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */\r
-#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */\r
-#define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */\r
-\r
-#define ADC_SQR1_SQ4_Pos               (24U)\r
-#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */\r
-#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */\r
-#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */\r
-#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */\r
-#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */\r
-#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */\r
-#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */\r
-\r
-/********************  Bit definition for ADC_SQR2 register  ******************/\r
-#define ADC_SQR2_SQ5_Pos               (0U)\r
-#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */\r
-#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */\r
-#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */\r
-#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */\r
-#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */\r
-#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */\r
-#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */\r
-\r
-#define ADC_SQR2_SQ6_Pos               (6U)\r
-#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */\r
-#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */\r
-#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */\r
-#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */\r
-#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */\r
-#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */\r
-#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */\r
-\r
-#define ADC_SQR2_SQ7_Pos               (12U)\r
-#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */\r
-#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */\r
-#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */\r
-#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */\r
-#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */\r
-#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */\r
-#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */\r
-\r
-#define ADC_SQR2_SQ8_Pos               (18U)\r
-#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */\r
-#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */\r
-#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */\r
-#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */\r
-#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */\r
-#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */\r
-#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */\r
-\r
-#define ADC_SQR2_SQ9_Pos               (24U)\r
-#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */\r
-#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */\r
-#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */\r
-#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */\r
-#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */\r
-#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */\r
-#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */\r
-\r
-/********************  Bit definition for ADC_SQR3 register  ******************/\r
-#define ADC_SQR3_SQ10_Pos              (0U)\r
-#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */\r
-#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */\r
-#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */\r
-#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */\r
-#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */\r
-#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */\r
-#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */\r
-\r
-#define ADC_SQR3_SQ11_Pos              (6U)\r
-#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */\r
-#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */\r
-#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */\r
-#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */\r
-#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */\r
-#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */\r
-#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */\r
-\r
-#define ADC_SQR3_SQ12_Pos              (12U)\r
-#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */\r
-#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */\r
-#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */\r
-#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */\r
-#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */\r
-#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */\r
-#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */\r
-\r
-#define ADC_SQR3_SQ13_Pos              (18U)\r
-#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */\r
-#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */\r
-#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */\r
-#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */\r
-#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */\r
-#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */\r
-#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */\r
-\r
-#define ADC_SQR3_SQ14_Pos              (24U)\r
-#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */\r
-#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */\r
-#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */\r
-#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */\r
-#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */\r
-#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */\r
-#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */\r
-\r
-/********************  Bit definition for ADC_SQR4 register  ******************/\r
-#define ADC_SQR4_SQ15_Pos              (0U)\r
-#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */\r
-#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */\r
-#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */\r
-#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */\r
-#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */\r
-#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */\r
-#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */\r
-\r
-#define ADC_SQR4_SQ16_Pos              (6U)\r
-#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */\r
-#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */\r
-#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */\r
-#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */\r
-#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */\r
-#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */\r
-#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */\r
-\r
-/********************  Bit definition for ADC_DR register  ********************/\r
-#define ADC_DR_RDATA_Pos               (0U)\r
-#define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */\r
-#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */\r
-#define ADC_DR_RDATA_0                 (0x0001UL << ADC_DR_RDATA_Pos)          /*!< 0x00000001 */\r
-#define ADC_DR_RDATA_1                 (0x0002UL << ADC_DR_RDATA_Pos)          /*!< 0x00000002 */\r
-#define ADC_DR_RDATA_2                 (0x0004UL << ADC_DR_RDATA_Pos)          /*!< 0x00000004 */\r
-#define ADC_DR_RDATA_3                 (0x0008UL << ADC_DR_RDATA_Pos)          /*!< 0x00000008 */\r
-#define ADC_DR_RDATA_4                 (0x0010UL << ADC_DR_RDATA_Pos)          /*!< 0x00000010 */\r
-#define ADC_DR_RDATA_5                 (0x0020UL << ADC_DR_RDATA_Pos)          /*!< 0x00000020 */\r
-#define ADC_DR_RDATA_6                 (0x0040UL << ADC_DR_RDATA_Pos)          /*!< 0x00000040 */\r
-#define ADC_DR_RDATA_7                 (0x0080UL << ADC_DR_RDATA_Pos)          /*!< 0x00000080 */\r
-#define ADC_DR_RDATA_8                 (0x0100UL << ADC_DR_RDATA_Pos)          /*!< 0x00000100 */\r
-#define ADC_DR_RDATA_9                 (0x0200UL << ADC_DR_RDATA_Pos)          /*!< 0x00000200 */\r
-#define ADC_DR_RDATA_10                (0x0400UL << ADC_DR_RDATA_Pos)          /*!< 0x00000400 */\r
-#define ADC_DR_RDATA_11                (0x0800UL << ADC_DR_RDATA_Pos)          /*!< 0x00000800 */\r
-#define ADC_DR_RDATA_12                (0x1000UL << ADC_DR_RDATA_Pos)          /*!< 0x00001000 */\r
-#define ADC_DR_RDATA_13                (0x2000UL << ADC_DR_RDATA_Pos)          /*!< 0x00002000 */\r
-#define ADC_DR_RDATA_14                (0x4000UL << ADC_DR_RDATA_Pos)          /*!< 0x00004000 */\r
-#define ADC_DR_RDATA_15                (0x8000UL << ADC_DR_RDATA_Pos)          /*!< 0x00008000 */\r
-\r
-/********************  Bit definition for ADC_JSQR register  ******************/\r
-#define ADC_JSQR_JL_Pos                (0U)\r
-#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */\r
-#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */\r
-#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */\r
-#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */\r
-\r
-#define ADC_JSQR_JEXTSEL_Pos           (2U)\r
-#define ADC_JSQR_JEXTSEL_Msk           (0xFUL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x0000003C */\r
-#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */\r
-#define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */\r
-#define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */\r
-#define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */\r
-#define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */\r
-\r
-#define ADC_JSQR_JEXTEN_Pos            (6U)\r
-#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x000000C0 */\r
-#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */\r
-#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000040 */\r
-#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */\r
-\r
-#define ADC_JSQR_JSQ1_Pos              (8U)\r
-#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001F00 */\r
-#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */\r
-#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000100 */\r
-#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */\r
-#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */\r
-#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */\r
-#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */\r
-\r
-#define ADC_JSQR_JSQ2_Pos              (14U)\r
-#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */\r
-#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */\r
-#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */\r
-#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */\r
-#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */\r
-#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */\r
-#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */\r
-\r
-#define ADC_JSQR_JSQ3_Pos              (20U)\r
-#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01F00000 */\r
-#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */\r
-#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00100000 */\r
-#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */\r
-#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */\r
-#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */\r
-#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */\r
-\r
-#define ADC_JSQR_JSQ4_Pos              (26U)\r
-#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0x7C000000 */\r
-#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */\r
-#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x04000000 */\r
-#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */\r
-#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */\r
-#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */\r
-#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */\r
-\r
-/********************  Bit definition for ADC_OFR1 register  ******************/\r
-#define ADC_OFR1_OFFSET1_Pos           (0U)\r
-#define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */\r
-#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */\r
-#define ADC_OFR1_OFFSET1_0             (0x001UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000001 */\r
-#define ADC_OFR1_OFFSET1_1             (0x002UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000002 */\r
-#define ADC_OFR1_OFFSET1_2             (0x004UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000004 */\r
-#define ADC_OFR1_OFFSET1_3             (0x008UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000008 */\r
-#define ADC_OFR1_OFFSET1_4             (0x010UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000010 */\r
-#define ADC_OFR1_OFFSET1_5             (0x020UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000020 */\r
-#define ADC_OFR1_OFFSET1_6             (0x040UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000040 */\r
-#define ADC_OFR1_OFFSET1_7             (0x080UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000080 */\r
-#define ADC_OFR1_OFFSET1_8             (0x100UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000100 */\r
-#define ADC_OFR1_OFFSET1_9             (0x200UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000200 */\r
-#define ADC_OFR1_OFFSET1_10            (0x400UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000400 */\r
-#define ADC_OFR1_OFFSET1_11            (0x800UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000800 */\r
-\r
-#define ADC_OFR1_OFFSET1_CH_Pos        (26U)\r
-#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */\r
-#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */\r
-#define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */\r
-#define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */\r
-#define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */\r
-#define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */\r
-#define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */\r
-\r
-#define ADC_OFR1_OFFSET1_EN_Pos        (31U)\r
-#define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */\r
-#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */\r
-\r
-/********************  Bit definition for ADC_OFR2 register  ******************/\r
-#define ADC_OFR2_OFFSET2_Pos           (0U)\r
-#define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */\r
-#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */\r
-#define ADC_OFR2_OFFSET2_0             (0x001UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000001 */\r
-#define ADC_OFR2_OFFSET2_1             (0x002UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000002 */\r
-#define ADC_OFR2_OFFSET2_2             (0x004UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000004 */\r
-#define ADC_OFR2_OFFSET2_3             (0x008UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000008 */\r
-#define ADC_OFR2_OFFSET2_4             (0x010UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000010 */\r
-#define ADC_OFR2_OFFSET2_5             (0x020UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000020 */\r
-#define ADC_OFR2_OFFSET2_6             (0x040UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000040 */\r
-#define ADC_OFR2_OFFSET2_7             (0x080UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000080 */\r
-#define ADC_OFR2_OFFSET2_8             (0x100UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000100 */\r
-#define ADC_OFR2_OFFSET2_9             (0x200UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000200 */\r
-#define ADC_OFR2_OFFSET2_10            (0x400UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000400 */\r
-#define ADC_OFR2_OFFSET2_11            (0x800UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000800 */\r
-\r
-#define ADC_OFR2_OFFSET2_CH_Pos        (26U)\r
-#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */\r
-#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */\r
-#define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */\r
-#define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */\r
-#define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */\r
-#define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */\r
-#define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */\r
-\r
-#define ADC_OFR2_OFFSET2_EN_Pos        (31U)\r
-#define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */\r
-#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */\r
-\r
-/********************  Bit definition for ADC_OFR3 register  ******************/\r
-#define ADC_OFR3_OFFSET3_Pos           (0U)\r
-#define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */\r
-#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */\r
-#define ADC_OFR3_OFFSET3_0             (0x001UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000001 */\r
-#define ADC_OFR3_OFFSET3_1             (0x002UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000002 */\r
-#define ADC_OFR3_OFFSET3_2             (0x004UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000004 */\r
-#define ADC_OFR3_OFFSET3_3             (0x008UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000008 */\r
-#define ADC_OFR3_OFFSET3_4             (0x010UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000010 */\r
-#define ADC_OFR3_OFFSET3_5             (0x020UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000020 */\r
-#define ADC_OFR3_OFFSET3_6             (0x040UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000040 */\r
-#define ADC_OFR3_OFFSET3_7             (0x080UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000080 */\r
-#define ADC_OFR3_OFFSET3_8             (0x100UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000100 */\r
-#define ADC_OFR3_OFFSET3_9             (0x200UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000200 */\r
-#define ADC_OFR3_OFFSET3_10            (0x400UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000400 */\r
-#define ADC_OFR3_OFFSET3_11            (0x800UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000800 */\r
-\r
-#define ADC_OFR3_OFFSET3_CH_Pos        (26U)\r
-#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */\r
-#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */\r
-#define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */\r
-#define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */\r
-#define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */\r
-#define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */\r
-#define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */\r
-\r
-#define ADC_OFR3_OFFSET3_EN_Pos        (31U)\r
-#define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */\r
-#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */\r
-\r
-/********************  Bit definition for ADC_OFR4 register  ******************/\r
-#define ADC_OFR4_OFFSET4_Pos           (0U)\r
-#define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */\r
-#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */\r
-#define ADC_OFR4_OFFSET4_0             (0x001UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000001 */\r
-#define ADC_OFR4_OFFSET4_1             (0x002UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000002 */\r
-#define ADC_OFR4_OFFSET4_2             (0x004UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000004 */\r
-#define ADC_OFR4_OFFSET4_3             (0x008UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000008 */\r
-#define ADC_OFR4_OFFSET4_4             (0x010UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000010 */\r
-#define ADC_OFR4_OFFSET4_5             (0x020UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000020 */\r
-#define ADC_OFR4_OFFSET4_6             (0x040UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000040 */\r
-#define ADC_OFR4_OFFSET4_7             (0x080UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000080 */\r
-#define ADC_OFR4_OFFSET4_8             (0x100UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000100 */\r
-#define ADC_OFR4_OFFSET4_9             (0x200UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000200 */\r
-#define ADC_OFR4_OFFSET4_10            (0x400UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000400 */\r
-#define ADC_OFR4_OFFSET4_11            (0x800UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000800 */\r
-\r
-#define ADC_OFR4_OFFSET4_CH_Pos        (26U)\r
-#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */\r
-#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */\r
-#define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */\r
-#define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */\r
-#define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */\r
-#define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */\r
-#define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */\r
-\r
-#define ADC_OFR4_OFFSET4_EN_Pos        (31U)\r
-#define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */\r
-#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */\r
-\r
-/********************  Bit definition for ADC_JDR1 register  ******************/\r
-#define ADC_JDR1_JDATA_Pos             (0U)\r
-#define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */\r
-#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */\r
-#define ADC_JDR1_JDATA_0               (0x0001UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000001 */\r
-#define ADC_JDR1_JDATA_1               (0x0002UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000002 */\r
-#define ADC_JDR1_JDATA_2               (0x0004UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000004 */\r
-#define ADC_JDR1_JDATA_3               (0x0008UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000008 */\r
-#define ADC_JDR1_JDATA_4               (0x0010UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000010 */\r
-#define ADC_JDR1_JDATA_5               (0x0020UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000020 */\r
-#define ADC_JDR1_JDATA_6               (0x0040UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000040 */\r
-#define ADC_JDR1_JDATA_7               (0x0080UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000080 */\r
-#define ADC_JDR1_JDATA_8               (0x0100UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000100 */\r
-#define ADC_JDR1_JDATA_9               (0x0200UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000200 */\r
-#define ADC_JDR1_JDATA_10              (0x0400UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000400 */\r
-#define ADC_JDR1_JDATA_11              (0x0800UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000800 */\r
-#define ADC_JDR1_JDATA_12              (0x1000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00001000 */\r
-#define ADC_JDR1_JDATA_13              (0x2000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00002000 */\r
-#define ADC_JDR1_JDATA_14              (0x4000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00004000 */\r
-#define ADC_JDR1_JDATA_15              (0x8000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00008000 */\r
-\r
-/********************  Bit definition for ADC_JDR2 register  ******************/\r
-#define ADC_JDR2_JDATA_Pos             (0U)\r
-#define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */\r
-#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */\r
-#define ADC_JDR2_JDATA_0               (0x0001UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000001 */\r
-#define ADC_JDR2_JDATA_1               (0x0002UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000002 */\r
-#define ADC_JDR2_JDATA_2               (0x0004UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000004 */\r
-#define ADC_JDR2_JDATA_3               (0x0008UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000008 */\r
-#define ADC_JDR2_JDATA_4               (0x0010UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000010 */\r
-#define ADC_JDR2_JDATA_5               (0x0020UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000020 */\r
-#define ADC_JDR2_JDATA_6               (0x0040UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000040 */\r
-#define ADC_JDR2_JDATA_7               (0x0080UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000080 */\r
-#define ADC_JDR2_JDATA_8               (0x0100UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000100 */\r
-#define ADC_JDR2_JDATA_9               (0x0200UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000200 */\r
-#define ADC_JDR2_JDATA_10              (0x0400UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000400 */\r
-#define ADC_JDR2_JDATA_11              (0x0800UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000800 */\r
-#define ADC_JDR2_JDATA_12              (0x1000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00001000 */\r
-#define ADC_JDR2_JDATA_13              (0x2000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00002000 */\r
-#define ADC_JDR2_JDATA_14              (0x4000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00004000 */\r
-#define ADC_JDR2_JDATA_15              (0x8000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00008000 */\r
-\r
-/********************  Bit definition for ADC_JDR3 register  ******************/\r
-#define ADC_JDR3_JDATA_Pos             (0U)\r
-#define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */\r
-#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */\r
-#define ADC_JDR3_JDATA_0               (0x0001UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000001 */\r
-#define ADC_JDR3_JDATA_1               (0x0002UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000002 */\r
-#define ADC_JDR3_JDATA_2               (0x0004UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000004 */\r
-#define ADC_JDR3_JDATA_3               (0x0008UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000008 */\r
-#define ADC_JDR3_JDATA_4               (0x0010UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000010 */\r
-#define ADC_JDR3_JDATA_5               (0x0020UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000020 */\r
-#define ADC_JDR3_JDATA_6               (0x0040UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000040 */\r
-#define ADC_JDR3_JDATA_7               (0x0080UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000080 */\r
-#define ADC_JDR3_JDATA_8               (0x0100UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000100 */\r
-#define ADC_JDR3_JDATA_9               (0x0200UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000200 */\r
-#define ADC_JDR3_JDATA_10              (0x0400UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000400 */\r
-#define ADC_JDR3_JDATA_11              (0x0800UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000800 */\r
-#define ADC_JDR3_JDATA_12              (0x1000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00001000 */\r
-#define ADC_JDR3_JDATA_13              (0x2000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00002000 */\r
-#define ADC_JDR3_JDATA_14              (0x4000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00004000 */\r
-#define ADC_JDR3_JDATA_15              (0x8000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00008000 */\r
-\r
-/********************  Bit definition for ADC_JDR4 register  ******************/\r
-#define ADC_JDR4_JDATA_Pos             (0U)\r
-#define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */\r
-#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */\r
-#define ADC_JDR4_JDATA_0               (0x0001UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000001 */\r
-#define ADC_JDR4_JDATA_1               (0x0002UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000002 */\r
-#define ADC_JDR4_JDATA_2               (0x0004UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000004 */\r
-#define ADC_JDR4_JDATA_3               (0x0008UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000008 */\r
-#define ADC_JDR4_JDATA_4               (0x0010UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000010 */\r
-#define ADC_JDR4_JDATA_5               (0x0020UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000020 */\r
-#define ADC_JDR4_JDATA_6               (0x0040UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000040 */\r
-#define ADC_JDR4_JDATA_7               (0x0080UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000080 */\r
-#define ADC_JDR4_JDATA_8               (0x0100UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000100 */\r
-#define ADC_JDR4_JDATA_9               (0x0200UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000200 */\r
-#define ADC_JDR4_JDATA_10              (0x0400UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000400 */\r
-#define ADC_JDR4_JDATA_11              (0x0800UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000800 */\r
-#define ADC_JDR4_JDATA_12              (0x1000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00001000 */\r
-#define ADC_JDR4_JDATA_13              (0x2000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00002000 */\r
-#define ADC_JDR4_JDATA_14              (0x4000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00004000 */\r
-#define ADC_JDR4_JDATA_15              (0x8000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00008000 */\r
-\r
-/********************  Bit definition for ADC_AWD2CR register  ****************/\r
-#define ADC_AWD2CR_AWD2CH_Pos          (0U)\r
-#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */\r
-#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */\r
-#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */\r
-#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */\r
-#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */\r
-#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */\r
-#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */\r
-#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */\r
-#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */\r
-#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */\r
-#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */\r
-#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */\r
-#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */\r
-#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */\r
-#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */\r
-#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */\r
-#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */\r
-#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */\r
-#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */\r
-#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */\r
-#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */\r
-\r
-/********************  Bit definition for ADC_AWD3CR register  ****************/\r
-#define ADC_AWD3CR_AWD3CH_Pos          (0U)\r
-#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */\r
-#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */\r
-#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */\r
-#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */\r
-#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */\r
-#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */\r
-#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */\r
-#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */\r
-#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */\r
-#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */\r
-#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */\r
-#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */\r
-#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */\r
-#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */\r
-#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */\r
-#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */\r
-#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */\r
-#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */\r
-#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */\r
-#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */\r
-#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */\r
-\r
-/********************  Bit definition for ADC_DIFSEL register  ****************/\r
-#define ADC_DIFSEL_DIFSEL_Pos          (0U)\r
-#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */\r
-#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */\r
-#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */\r
-#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */\r
-#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */\r
-#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */\r
-#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */\r
-#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */\r
-#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */\r
-#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */\r
-#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */\r
-#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */\r
-#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */\r
-#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */\r
-#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */\r
-#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */\r
-#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */\r
-#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */\r
-#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */\r
-#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */\r
-#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */\r
-\r
-/********************  Bit definition for ADC_CALFACT register  ***************/\r
-#define ADC_CALFACT_CALFACT_S_Pos      (0U)\r
-#define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */\r
-#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */\r
-#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */\r
-#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */\r
-#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */\r
-#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */\r
-#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */\r
-#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */\r
-#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */\r
-\r
-#define ADC_CALFACT_CALFACT_D_Pos      (16U)\r
-#define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */\r
-#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */\r
-#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */\r
-#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */\r
-#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */\r
-#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */\r
-#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */\r
-#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */\r
-#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */\r
-\r
-/*************************  ADC Common registers  *****************************/\r
-/********************  Bit definition for ADC_CSR register  *******************/\r
-#define ADC_CSR_ADRDY_MST_Pos          (0U)\r
-#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */\r
-#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */\r
-#define ADC_CSR_EOSMP_MST_Pos          (1U)\r
-#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */\r
-#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */\r
-#define ADC_CSR_EOC_MST_Pos            (2U)\r
-#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */\r
-#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */\r
-#define ADC_CSR_EOS_MST_Pos            (3U)\r
-#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */\r
-#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */\r
-#define ADC_CSR_OVR_MST_Pos            (4U)\r
-#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */\r
-#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */\r
-#define ADC_CSR_JEOC_MST_Pos           (5U)\r
-#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */\r
-#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */\r
-#define ADC_CSR_JEOS_MST_Pos           (6U)\r
-#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */\r
-#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */\r
-#define ADC_CSR_AWD1_MST_Pos           (7U)\r
-#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */\r
-#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */\r
-#define ADC_CSR_AWD2_MST_Pos           (8U)\r
-#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */\r
-#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */\r
-#define ADC_CSR_AWD3_MST_Pos           (9U)\r
-#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */\r
-#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */\r
-#define ADC_CSR_JQOVF_MST_Pos          (10U)\r
-#define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */\r
-#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */\r
-\r
-#define ADC_CSR_ADRDY_SLV_Pos          (16U)\r
-#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */\r
-#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */\r
-#define ADC_CSR_EOSMP_SLV_Pos          (17U)\r
-#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */\r
-#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */\r
-#define ADC_CSR_EOC_SLV_Pos            (18U)\r
-#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */\r
-#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */\r
-#define ADC_CSR_EOS_SLV_Pos            (19U)\r
-#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */\r
-#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */\r
-#define ADC_CSR_OVR_SLV_Pos            (20U)\r
-#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */\r
-#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */\r
-#define ADC_CSR_JEOC_SLV_Pos           (21U)\r
-#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */\r
-#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */\r
-#define ADC_CSR_JEOS_SLV_Pos           (22U)\r
-#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */\r
-#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */\r
-#define ADC_CSR_AWD1_SLV_Pos           (23U)\r
-#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */\r
-#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */\r
-#define ADC_CSR_AWD2_SLV_Pos           (24U)\r
-#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */\r
-#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */\r
-#define ADC_CSR_AWD3_SLV_Pos           (25U)\r
-#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */\r
-#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */\r
-#define ADC_CSR_JQOVF_SLV_Pos          (26U)\r
-#define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */\r
-#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */\r
-\r
-/********************  Bit definition for ADC_CCR register  *******************/\r
-#define ADC_CCR_DUAL_Pos               (0U)\r
-#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */\r
-#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */\r
-#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */\r
-#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */\r
-#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */\r
-#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */\r
-#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */\r
-\r
-#define ADC_CCR_DELAY_Pos              (8U)\r
-#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */\r
-#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */\r
-#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */\r
-#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */\r
-#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */\r
-#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */\r
-\r
-#define ADC_CCR_DMACFG_Pos             (13U)\r
-#define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */\r
-#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */\r
-\r
-#define ADC_CCR_MDMA_Pos               (14U)\r
-#define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */\r
-#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */\r
-#define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */\r
-#define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */\r
-\r
-#define ADC_CCR_CKMODE_Pos             (16U)\r
-#define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */\r
-#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */\r
-#define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */\r
-#define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */\r
-\r
-#define ADC_CCR_PRESC_Pos              (18U)\r
-#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */\r
-#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */\r
-#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */\r
-#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */\r
-#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */\r
-#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */\r
-\r
-#define ADC_CCR_VREFEN_Pos             (22U)\r
-#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */\r
-#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */\r
-#define ADC_CCR_TSEN_Pos               (23U)\r
-#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */\r
-#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */\r
-#define ADC_CCR_VBATEN_Pos             (24U)\r
-#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */\r
-#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */\r
-\r
-/********************  Bit definition for ADC_CDR register  *******************/\r
-#define ADC_CDR_RDATA_MST_Pos          (0U)\r
-#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */\r
-#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */\r
-#define ADC_CDR_RDATA_MST_0            (0x0001UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000001 */\r
-#define ADC_CDR_RDATA_MST_1            (0x0002UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000002 */\r
-#define ADC_CDR_RDATA_MST_2            (0x0004UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000004 */\r
-#define ADC_CDR_RDATA_MST_3            (0x0008UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000008 */\r
-#define ADC_CDR_RDATA_MST_4            (0x0010UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000010 */\r
-#define ADC_CDR_RDATA_MST_5            (0x0020UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000020 */\r
-#define ADC_CDR_RDATA_MST_6            (0x0040UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000040 */\r
-#define ADC_CDR_RDATA_MST_7            (0x0080UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000080 */\r
-#define ADC_CDR_RDATA_MST_8            (0x0100UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000100 */\r
-#define ADC_CDR_RDATA_MST_9            (0x0200UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000200 */\r
-#define ADC_CDR_RDATA_MST_10           (0x0400UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000400 */\r
-#define ADC_CDR_RDATA_MST_11           (0x0800UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000800 */\r
-#define ADC_CDR_RDATA_MST_12           (0x1000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00001000 */\r
-#define ADC_CDR_RDATA_MST_13           (0x2000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00002000 */\r
-#define ADC_CDR_RDATA_MST_14           (0x4000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00004000 */\r
-#define ADC_CDR_RDATA_MST_15           (0x8000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00008000 */\r
-\r
-#define ADC_CDR_RDATA_SLV_Pos          (16U)\r
-#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */\r
-#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */\r
-#define ADC_CDR_RDATA_SLV_0            (0x0001UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00010000 */\r
-#define ADC_CDR_RDATA_SLV_1            (0x0002UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00020000 */\r
-#define ADC_CDR_RDATA_SLV_2            (0x0004UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00040000 */\r
-#define ADC_CDR_RDATA_SLV_3            (0x0008UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00080000 */\r
-#define ADC_CDR_RDATA_SLV_4            (0x0010UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00100000 */\r
-#define ADC_CDR_RDATA_SLV_5            (0x0020UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00200000 */\r
-#define ADC_CDR_RDATA_SLV_6            (0x0040UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00400000 */\r
-#define ADC_CDR_RDATA_SLV_7            (0x0080UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00800000 */\r
-#define ADC_CDR_RDATA_SLV_8            (0x0100UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x01000000 */\r
-#define ADC_CDR_RDATA_SLV_9            (0x0200UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x02000000 */\r
-#define ADC_CDR_RDATA_SLV_10           (0x0400UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x04000000 */\r
-#define ADC_CDR_RDATA_SLV_11           (0x0800UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x08000000 */\r
-#define ADC_CDR_RDATA_SLV_12           (0x1000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x10000000 */\r
-#define ADC_CDR_RDATA_SLV_13           (0x2000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x20000000 */\r
-#define ADC_CDR_RDATA_SLV_14           (0x4000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x40000000 */\r
-#define ADC_CDR_RDATA_SLV_15           (0x8000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x80000000 */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                         Controller Area Network                            */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*!<CAN control and status registers */\r
-/*******************  Bit definition for CAN_MCR register  ********************/\r
-#define CAN_MCR_INRQ_Pos       (0U)\r
-#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                     /*!< 0x00000001 */\r
-#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\r
-#define CAN_MCR_SLEEP_Pos      (1U)\r
-#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                    /*!< 0x00000002 */\r
-#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\r
-#define CAN_MCR_TXFP_Pos       (2U)\r
-#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                     /*!< 0x00000004 */\r
-#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\r
-#define CAN_MCR_RFLM_Pos       (3U)\r
-#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                     /*!< 0x00000008 */\r
-#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\r
-#define CAN_MCR_NART_Pos       (4U)\r
-#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                     /*!< 0x00000010 */\r
-#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\r
-#define CAN_MCR_AWUM_Pos       (5U)\r
-#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                     /*!< 0x00000020 */\r
-#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\r
-#define CAN_MCR_ABOM_Pos       (6U)\r
-#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                     /*!< 0x00000040 */\r
-#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\r
-#define CAN_MCR_TTCM_Pos       (7U)\r
-#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                     /*!< 0x00000080 */\r
-#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\r
-#define CAN_MCR_RESET_Pos      (15U)\r
-#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                    /*!< 0x00008000 */\r
-#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\r
-\r
-/*******************  Bit definition for CAN_MSR register  ********************/\r
-#define CAN_MSR_INAK_Pos       (0U)\r
-#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                     /*!< 0x00000001 */\r
-#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\r
-#define CAN_MSR_SLAK_Pos       (1U)\r
-#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                     /*!< 0x00000002 */\r
-#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\r
-#define CAN_MSR_ERRI_Pos       (2U)\r
-#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                     /*!< 0x00000004 */\r
-#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\r
-#define CAN_MSR_WKUI_Pos       (3U)\r
-#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                     /*!< 0x00000008 */\r
-#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\r
-#define CAN_MSR_SLAKI_Pos      (4U)\r
-#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                    /*!< 0x00000010 */\r
-#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\r
-#define CAN_MSR_TXM_Pos        (8U)\r
-#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                      /*!< 0x00000100 */\r
-#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\r
-#define CAN_MSR_RXM_Pos        (9U)\r
-#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                      /*!< 0x00000200 */\r
-#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\r
-#define CAN_MSR_SAMP_Pos       (10U)\r
-#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                     /*!< 0x00000400 */\r
-#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\r
-#define CAN_MSR_RX_Pos         (11U)\r
-#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                       /*!< 0x00000800 */\r
-#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\r
-\r
-/*******************  Bit definition for CAN_TSR register  ********************/\r
-#define CAN_TSR_RQCP0_Pos      (0U)\r
-#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\r
-#define CAN_TSR_TXOK0_Pos      (1U)\r
-#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                    /*!< 0x00000002 */\r
-#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\r
-#define CAN_TSR_ALST0_Pos      (2U)\r
-#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                    /*!< 0x00000004 */\r
-#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\r
-#define CAN_TSR_TERR0_Pos      (3U)\r
-#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                    /*!< 0x00000008 */\r
-#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\r
-#define CAN_TSR_ABRQ0_Pos      (7U)\r
-#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                    /*!< 0x00000080 */\r
-#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\r
-#define CAN_TSR_RQCP1_Pos      (8U)\r
-#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                    /*!< 0x00000100 */\r
-#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\r
-#define CAN_TSR_TXOK1_Pos      (9U)\r
-#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                    /*!< 0x00000200 */\r
-#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\r
-#define CAN_TSR_ALST1_Pos      (10U)\r
-#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                    /*!< 0x00000400 */\r
-#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\r
-#define CAN_TSR_TERR1_Pos      (11U)\r
-#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                    /*!< 0x00000800 */\r
-#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\r
-#define CAN_TSR_ABRQ1_Pos      (15U)\r
-#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                    /*!< 0x00008000 */\r
-#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\r
-#define CAN_TSR_RQCP2_Pos      (16U)\r
-#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                    /*!< 0x00010000 */\r
-#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\r
-#define CAN_TSR_TXOK2_Pos      (17U)\r
-#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                    /*!< 0x00020000 */\r
-#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\r
-#define CAN_TSR_ALST2_Pos      (18U)\r
-#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                    /*!< 0x00040000 */\r
-#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\r
-#define CAN_TSR_TERR2_Pos      (19U)\r
-#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                    /*!< 0x00080000 */\r
-#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\r
-#define CAN_TSR_ABRQ2_Pos      (23U)\r
-#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                    /*!< 0x00800000 */\r
-#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\r
-#define CAN_TSR_CODE_Pos       (24U)\r
-#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                     /*!< 0x03000000 */\r
-#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\r
-\r
-#define CAN_TSR_TME_Pos        (26U)\r
-#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                      /*!< 0x1C000000 */\r
-#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\r
-#define CAN_TSR_TME0_Pos       (26U)\r
-#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                     /*!< 0x04000000 */\r
-#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\r
-#define CAN_TSR_TME1_Pos       (27U)\r
-#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                     /*!< 0x08000000 */\r
-#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\r
-#define CAN_TSR_TME2_Pos       (28U)\r
-#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                     /*!< 0x10000000 */\r
-#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\r
-\r
-#define CAN_TSR_LOW_Pos        (29U)\r
-#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                      /*!< 0xE0000000 */\r
-#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\r
-#define CAN_TSR_LOW0_Pos       (29U)\r
-#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                     /*!< 0x20000000 */\r
-#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\r
-#define CAN_TSR_LOW1_Pos       (30U)\r
-#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                     /*!< 0x40000000 */\r
-#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\r
-#define CAN_TSR_LOW2_Pos       (31U)\r
-#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                     /*!< 0x80000000 */\r
-#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\r
-\r
-/*******************  Bit definition for CAN_RF0R register  *******************/\r
-#define CAN_RF0R_FMP0_Pos      (0U)\r
-#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                    /*!< 0x00000003 */\r
-#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\r
-#define CAN_RF0R_FULL0_Pos     (3U)\r
-#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                   /*!< 0x00000008 */\r
-#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\r
-#define CAN_RF0R_FOVR0_Pos     (4U)\r
-#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                   /*!< 0x00000010 */\r
-#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\r
-#define CAN_RF0R_RFOM0_Pos     (5U)\r
-#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                   /*!< 0x00000020 */\r
-#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\r
-\r
-/*******************  Bit definition for CAN_RF1R register  *******************/\r
-#define CAN_RF1R_FMP1_Pos      (0U)\r
-#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                    /*!< 0x00000003 */\r
-#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\r
-#define CAN_RF1R_FULL1_Pos     (3U)\r
-#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                   /*!< 0x00000008 */\r
-#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\r
-#define CAN_RF1R_FOVR1_Pos     (4U)\r
-#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                   /*!< 0x00000010 */\r
-#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\r
-#define CAN_RF1R_RFOM1_Pos     (5U)\r
-#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                   /*!< 0x00000020 */\r
-#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\r
-\r
-/********************  Bit definition for CAN_IER register  *******************/\r
-#define CAN_IER_TMEIE_Pos      (0U)\r
-#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                    /*!< 0x00000001 */\r
-#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\r
-#define CAN_IER_FMPIE0_Pos     (1U)\r
-#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                   /*!< 0x00000002 */\r
-#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE0_Pos      (2U)\r
-#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                    /*!< 0x00000004 */\r
-#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE0_Pos     (3U)\r
-#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                   /*!< 0x00000008 */\r
-#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_FMPIE1_Pos     (4U)\r
-#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                   /*!< 0x00000010 */\r
-#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE1_Pos      (5U)\r
-#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                    /*!< 0x00000020 */\r
-#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE1_Pos     (6U)\r
-#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                   /*!< 0x00000040 */\r
-#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_EWGIE_Pos      (8U)\r
-#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                    /*!< 0x00000100 */\r
-#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\r
-#define CAN_IER_EPVIE_Pos      (9U)\r
-#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                    /*!< 0x00000200 */\r
-#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\r
-#define CAN_IER_BOFIE_Pos      (10U)\r
-#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                    /*!< 0x00000400 */\r
-#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\r
-#define CAN_IER_LECIE_Pos      (11U)\r
-#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                    /*!< 0x00000800 */\r
-#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\r
-#define CAN_IER_ERRIE_Pos      (15U)\r
-#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                    /*!< 0x00008000 */\r
-#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\r
-#define CAN_IER_WKUIE_Pos      (16U)\r
-#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                    /*!< 0x00010000 */\r
-#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\r
-#define CAN_IER_SLKIE_Pos      (17U)\r
-#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                    /*!< 0x00020000 */\r
-#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\r
-\r
-/********************  Bit definition for CAN_ESR register  *******************/\r
-#define CAN_ESR_EWGF_Pos       (0U)\r
-#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                     /*!< 0x00000001 */\r
-#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\r
-#define CAN_ESR_EPVF_Pos       (1U)\r
-#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                     /*!< 0x00000002 */\r
-#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\r
-#define CAN_ESR_BOFF_Pos       (2U)\r
-#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                     /*!< 0x00000004 */\r
-#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\r
-\r
-#define CAN_ESR_LEC_Pos        (4U)\r
-#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000070 */\r
-#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\r
-#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000010 */\r
-#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000020 */\r
-#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000040 */\r
-\r
-#define CAN_ESR_TEC_Pos        (16U)\r
-#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                     /*!< 0x00FF0000 */\r
-#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
-#define CAN_ESR_REC_Pos        (24U)\r
-#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                     /*!< 0xFF000000 */\r
-#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\r
-\r
-/*******************  Bit definition for CAN_BTR register  ********************/\r
-#define CAN_BTR_BRP_Pos        (0U)\r
-#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                    /*!< 0x000003FF */\r
-#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\r
-#define CAN_BTR_TS1_Pos        (16U)\r
-#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                      /*!< 0x000F0000 */\r
-#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\r
-#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                      /*!< 0x00010000 */\r
-#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                      /*!< 0x00020000 */\r
-#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                      /*!< 0x00040000 */\r
-#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                      /*!< 0x00080000 */\r
-#define CAN_BTR_TS2_Pos        (20U)\r
-#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                      /*!< 0x00700000 */\r
-#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\r
-#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                      /*!< 0x00100000 */\r
-#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                      /*!< 0x00200000 */\r
-#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                      /*!< 0x00400000 */\r
-#define CAN_BTR_SJW_Pos        (24U)\r
-#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                      /*!< 0x03000000 */\r
-#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\r
-#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                      /*!< 0x01000000 */\r
-#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                      /*!< 0x02000000 */\r
-#define CAN_BTR_LBKM_Pos       (30U)\r
-#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                     /*!< 0x40000000 */\r
-#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\r
-#define CAN_BTR_SILM_Pos       (31U)\r
-#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                     /*!< 0x80000000 */\r
-#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\r
-\r
-/*!<Mailbox registers */\r
-/******************  Bit definition for CAN_TI0R register  ********************/\r
-#define CAN_TI0R_TXRQ_Pos      (0U)\r
-#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                    /*!< 0x00000001 */\r
-#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\r
-#define CAN_TI0R_RTR_Pos       (1U)\r
-#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                     /*!< 0x00000002 */\r
-#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\r
-#define CAN_TI0R_IDE_Pos       (2U)\r
-#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                     /*!< 0x00000004 */\r
-#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\r
-#define CAN_TI0R_EXID_Pos      (3U)\r
-#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                /*!< 0x001FFFF8 */\r
-#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\r
-#define CAN_TI0R_STID_Pos      (21U)\r
-#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                  /*!< 0xFFE00000 */\r
-#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************  Bit definition for CAN_TDT0R register  *******************/\r
-#define CAN_TDT0R_DLC_Pos      (0U)\r
-#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                    /*!< 0x0000000F */\r
-#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\r
-#define CAN_TDT0R_TGT_Pos      (8U)\r
-#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                    /*!< 0x00000100 */\r
-#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\r
-#define CAN_TDT0R_TIME_Pos     (16U)\r
-#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                /*!< 0xFFFF0000 */\r
-#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\r
-\r
-/******************  Bit definition for CAN_TDL0R register  *******************/\r
-#define CAN_TDL0R_DATA0_Pos    (0U)\r
-#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                 /*!< 0x000000FF */\r
-#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\r
-#define CAN_TDL0R_DATA1_Pos    (8U)\r
-#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\r
-#define CAN_TDL0R_DATA2_Pos    (16U)\r
-#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\r
-#define CAN_TDL0R_DATA3_Pos    (24U)\r
-#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\r
-\r
-/******************  Bit definition for CAN_TDH0R register  *******************/\r
-#define CAN_TDH0R_DATA4_Pos    (0U)\r
-#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                 /*!< 0x000000FF */\r
-#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\r
-#define CAN_TDH0R_DATA5_Pos    (8U)\r
-#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\r
-#define CAN_TDH0R_DATA6_Pos    (16U)\r
-#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\r
-#define CAN_TDH0R_DATA7_Pos    (24U)\r
-#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\r
-\r
-/*******************  Bit definition for CAN_TI1R register  *******************/\r
-#define CAN_TI1R_TXRQ_Pos      (0U)\r
-#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                    /*!< 0x00000001 */\r
-#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\r
-#define CAN_TI1R_RTR_Pos       (1U)\r
-#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                     /*!< 0x00000002 */\r
-#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\r
-#define CAN_TI1R_IDE_Pos       (2U)\r
-#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                     /*!< 0x00000004 */\r
-#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\r
-#define CAN_TI1R_EXID_Pos      (3U)\r
-#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                /*!< 0x001FFFF8 */\r
-#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\r
-#define CAN_TI1R_STID_Pos      (21U)\r
-#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                  /*!< 0xFFE00000 */\r
-#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
-\r
-/*******************  Bit definition for CAN_TDT1R register  ******************/\r
-#define CAN_TDT1R_DLC_Pos      (0U)\r
-#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                    /*!< 0x0000000F */\r
-#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\r
-#define CAN_TDT1R_TGT_Pos      (8U)\r
-#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                    /*!< 0x00000100 */\r
-#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\r
-#define CAN_TDT1R_TIME_Pos     (16U)\r
-#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                /*!< 0xFFFF0000 */\r
-#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\r
-\r
-/*******************  Bit definition for CAN_TDL1R register  ******************/\r
-#define CAN_TDL1R_DATA0_Pos    (0U)\r
-#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                 /*!< 0x000000FF */\r
-#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\r
-#define CAN_TDL1R_DATA1_Pos    (8U)\r
-#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\r
-#define CAN_TDL1R_DATA2_Pos    (16U)\r
-#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\r
-#define CAN_TDL1R_DATA3_Pos    (24U)\r
-#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\r
-\r
-/*******************  Bit definition for CAN_TDH1R register  ******************/\r
-#define CAN_TDH1R_DATA4_Pos    (0U)\r
-#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                 /*!< 0x000000FF */\r
-#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\r
-#define CAN_TDH1R_DATA5_Pos    (8U)\r
-#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\r
-#define CAN_TDH1R_DATA6_Pos    (16U)\r
-#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\r
-#define CAN_TDH1R_DATA7_Pos    (24U)\r
-#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\r
-\r
-/*******************  Bit definition for CAN_TI2R register  *******************/\r
-#define CAN_TI2R_TXRQ_Pos      (0U)\r
-#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                    /*!< 0x00000001 */\r
-#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\r
-#define CAN_TI2R_RTR_Pos       (1U)\r
-#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                     /*!< 0x00000002 */\r
-#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\r
-#define CAN_TI2R_IDE_Pos       (2U)\r
-#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                     /*!< 0x00000004 */\r
-#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\r
-#define CAN_TI2R_EXID_Pos      (3U)\r
-#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                /*!< 0x001FFFF8 */\r
-#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\r
-#define CAN_TI2R_STID_Pos      (21U)\r
-#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                  /*!< 0xFFE00000 */\r
-#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
-\r
-/*******************  Bit definition for CAN_TDT2R register  ******************/\r
-#define CAN_TDT2R_DLC_Pos      (0U)\r
-#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                    /*!< 0x0000000F */\r
-#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\r
-#define CAN_TDT2R_TGT_Pos      (8U)\r
-#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                    /*!< 0x00000100 */\r
-#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\r
-#define CAN_TDT2R_TIME_Pos     (16U)\r
-#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                /*!< 0xFFFF0000 */\r
-#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\r
-\r
-/*******************  Bit definition for CAN_TDL2R register  ******************/\r
-#define CAN_TDL2R_DATA0_Pos    (0U)\r
-#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                 /*!< 0x000000FF */\r
-#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\r
-#define CAN_TDL2R_DATA1_Pos    (8U)\r
-#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\r
-#define CAN_TDL2R_DATA2_Pos    (16U)\r
-#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\r
-#define CAN_TDL2R_DATA3_Pos    (24U)\r
-#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\r
-\r
-/*******************  Bit definition for CAN_TDH2R register  ******************/\r
-#define CAN_TDH2R_DATA4_Pos    (0U)\r
-#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                 /*!< 0x000000FF */\r
-#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\r
-#define CAN_TDH2R_DATA5_Pos    (8U)\r
-#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\r
-#define CAN_TDH2R_DATA6_Pos    (16U)\r
-#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\r
-#define CAN_TDH2R_DATA7_Pos    (24U)\r
-#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\r
-\r
-/*******************  Bit definition for CAN_RI0R register  *******************/\r
-#define CAN_RI0R_RTR_Pos       (1U)\r
-#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                     /*!< 0x00000002 */\r
-#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\r
-#define CAN_RI0R_IDE_Pos       (2U)\r
-#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                     /*!< 0x00000004 */\r
-#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\r
-#define CAN_RI0R_EXID_Pos      (3U)\r
-#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                /*!< 0x001FFFF8 */\r
-#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\r
-#define CAN_RI0R_STID_Pos      (21U)\r
-#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                  /*!< 0xFFE00000 */\r
-#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
-\r
-/*******************  Bit definition for CAN_RDT0R register  ******************/\r
-#define CAN_RDT0R_DLC_Pos      (0U)\r
-#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                    /*!< 0x0000000F */\r
-#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\r
-#define CAN_RDT0R_FMI_Pos      (8U)\r
-#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                   /*!< 0x0000FF00 */\r
-#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\r
-#define CAN_RDT0R_TIME_Pos     (16U)\r
-#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                /*!< 0xFFFF0000 */\r
-#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\r
-\r
-/*******************  Bit definition for CAN_RDL0R register  ******************/\r
-#define CAN_RDL0R_DATA0_Pos    (0U)\r
-#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                 /*!< 0x000000FF */\r
-#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\r
-#define CAN_RDL0R_DATA1_Pos    (8U)\r
-#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\r
-#define CAN_RDL0R_DATA2_Pos    (16U)\r
-#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\r
-#define CAN_RDL0R_DATA3_Pos    (24U)\r
-#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\r
-\r
-/*******************  Bit definition for CAN_RDH0R register  ******************/\r
-#define CAN_RDH0R_DATA4_Pos    (0U)\r
-#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                 /*!< 0x000000FF */\r
-#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\r
-#define CAN_RDH0R_DATA5_Pos    (8U)\r
-#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\r
-#define CAN_RDH0R_DATA6_Pos    (16U)\r
-#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\r
-#define CAN_RDH0R_DATA7_Pos    (24U)\r
-#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\r
-\r
-/*******************  Bit definition for CAN_RI1R register  *******************/\r
-#define CAN_RI1R_RTR_Pos       (1U)\r
-#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                     /*!< 0x00000002 */\r
-#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\r
-#define CAN_RI1R_IDE_Pos       (2U)\r
-#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                     /*!< 0x00000004 */\r
-#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\r
-#define CAN_RI1R_EXID_Pos      (3U)\r
-#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                /*!< 0x001FFFF8 */\r
-#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\r
-#define CAN_RI1R_STID_Pos      (21U)\r
-#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                  /*!< 0xFFE00000 */\r
-#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r
-\r
-/*******************  Bit definition for CAN_RDT1R register  ******************/\r
-#define CAN_RDT1R_DLC_Pos      (0U)\r
-#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                    /*!< 0x0000000F */\r
-#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\r
-#define CAN_RDT1R_FMI_Pos      (8U)\r
-#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                   /*!< 0x0000FF00 */\r
-#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\r
-#define CAN_RDT1R_TIME_Pos     (16U)\r
-#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                /*!< 0xFFFF0000 */\r
-#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\r
-\r
-/*******************  Bit definition for CAN_RDL1R register  ******************/\r
-#define CAN_RDL1R_DATA0_Pos    (0U)\r
-#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                 /*!< 0x000000FF */\r
-#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\r
-#define CAN_RDL1R_DATA1_Pos    (8U)\r
-#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\r
-#define CAN_RDL1R_DATA2_Pos    (16U)\r
-#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\r
-#define CAN_RDL1R_DATA3_Pos    (24U)\r
-#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\r
-\r
-/*******************  Bit definition for CAN_RDH1R register  ******************/\r
-#define CAN_RDH1R_DATA4_Pos    (0U)\r
-#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                 /*!< 0x000000FF */\r
-#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\r
-#define CAN_RDH1R_DATA5_Pos    (8U)\r
-#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                 /*!< 0x0000FF00 */\r
-#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\r
-#define CAN_RDH1R_DATA6_Pos    (16U)\r
-#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                 /*!< 0x00FF0000 */\r
-#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\r
-#define CAN_RDH1R_DATA7_Pos    (24U)\r
-#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                 /*!< 0xFF000000 */\r
-#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\r
-\r
-/*!<CAN filter registers */\r
-/*******************  Bit definition for CAN_FMR register  ********************/\r
-#define CAN_FMR_FINIT_Pos      (0U)\r
-#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                    /*!< 0x00000001 */\r
-#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\r
-\r
-/*******************  Bit definition for CAN_FM1R register  *******************/\r
-#define CAN_FM1R_FBM_Pos       (0U)\r
-#define CAN_FM1R_FBM_Msk       (0x3FFFUL << CAN_FM1R_FBM_Pos)                  /*!< 0x00003FFF */\r
-#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\r
-#define CAN_FM1R_FBM0_Pos      (0U)\r
-#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\r
-#define CAN_FM1R_FBM1_Pos      (1U)\r
-#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\r
-#define CAN_FM1R_FBM2_Pos      (2U)\r
-#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\r
-#define CAN_FM1R_FBM3_Pos      (3U)\r
-#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\r
-#define CAN_FM1R_FBM4_Pos      (4U)\r
-#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\r
-#define CAN_FM1R_FBM5_Pos      (5U)\r
-#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\r
-#define CAN_FM1R_FBM6_Pos      (6U)\r
-#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\r
-#define CAN_FM1R_FBM7_Pos      (7U)\r
-#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\r
-#define CAN_FM1R_FBM8_Pos      (8U)\r
-#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\r
-#define CAN_FM1R_FBM9_Pos      (9U)\r
-#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\r
-#define CAN_FM1R_FBM10_Pos     (10U)\r
-#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\r
-#define CAN_FM1R_FBM11_Pos     (11U)\r
-#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\r
-#define CAN_FM1R_FBM12_Pos     (12U)\r
-#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\r
-#define CAN_FM1R_FBM13_Pos     (13U)\r
-#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\r
-\r
-/*******************  Bit definition for CAN_FS1R register  *******************/\r
-#define CAN_FS1R_FSC_Pos       (0U)\r
-#define CAN_FS1R_FSC_Msk       (0x3FFFUL << CAN_FS1R_FSC_Pos)                  /*!< 0x00003FFF */\r
-#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\r
-#define CAN_FS1R_FSC0_Pos      (0U)\r
-#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\r
-#define CAN_FS1R_FSC1_Pos      (1U)\r
-#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\r
-#define CAN_FS1R_FSC2_Pos      (2U)\r
-#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\r
-#define CAN_FS1R_FSC3_Pos      (3U)\r
-#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\r
-#define CAN_FS1R_FSC4_Pos      (4U)\r
-#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\r
-#define CAN_FS1R_FSC5_Pos      (5U)\r
-#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\r
-#define CAN_FS1R_FSC6_Pos      (6U)\r
-#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\r
-#define CAN_FS1R_FSC7_Pos      (7U)\r
-#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\r
-#define CAN_FS1R_FSC8_Pos      (8U)\r
-#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\r
-#define CAN_FS1R_FSC9_Pos      (9U)\r
-#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\r
-#define CAN_FS1R_FSC10_Pos     (10U)\r
-#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\r
-#define CAN_FS1R_FSC11_Pos     (11U)\r
-#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\r
-#define CAN_FS1R_FSC12_Pos     (12U)\r
-#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\r
-#define CAN_FS1R_FSC13_Pos     (13U)\r
-#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\r
-\r
-/******************  Bit definition for CAN_FFA1R register  *******************/\r
-#define CAN_FFA1R_FFA_Pos      (0U)\r
-#define CAN_FFA1R_FFA_Msk      (0x3FFFUL << CAN_FFA1R_FFA_Pos)                 /*!< 0x00003FFF */\r
-#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\r
-#define CAN_FFA1R_FFA0_Pos     (0U)\r
-#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                   /*!< 0x00000001 */\r
-#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */\r
-#define CAN_FFA1R_FFA1_Pos     (1U)\r
-#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                   /*!< 0x00000002 */\r
-#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */\r
-#define CAN_FFA1R_FFA2_Pos     (2U)\r
-#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                   /*!< 0x00000004 */\r
-#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */\r
-#define CAN_FFA1R_FFA3_Pos     (3U)\r
-#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                   /*!< 0x00000008 */\r
-#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */\r
-#define CAN_FFA1R_FFA4_Pos     (4U)\r
-#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                   /*!< 0x00000010 */\r
-#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */\r
-#define CAN_FFA1R_FFA5_Pos     (5U)\r
-#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                   /*!< 0x00000020 */\r
-#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */\r
-#define CAN_FFA1R_FFA6_Pos     (6U)\r
-#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                   /*!< 0x00000040 */\r
-#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */\r
-#define CAN_FFA1R_FFA7_Pos     (7U)\r
-#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                   /*!< 0x00000080 */\r
-#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */\r
-#define CAN_FFA1R_FFA8_Pos     (8U)\r
-#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                   /*!< 0x00000100 */\r
-#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */\r
-#define CAN_FFA1R_FFA9_Pos     (9U)\r
-#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                   /*!< 0x00000200 */\r
-#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */\r
-#define CAN_FFA1R_FFA10_Pos    (10U)\r
-#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                  /*!< 0x00000400 */\r
-#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */\r
-#define CAN_FFA1R_FFA11_Pos    (11U)\r
-#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                  /*!< 0x00000800 */\r
-#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */\r
-#define CAN_FFA1R_FFA12_Pos    (12U)\r
-#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                  /*!< 0x00001000 */\r
-#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */\r
-#define CAN_FFA1R_FFA13_Pos    (13U)\r
-#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                  /*!< 0x00002000 */\r
-#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */\r
-\r
-/*******************  Bit definition for CAN_FA1R register  *******************/\r
-#define CAN_FA1R_FACT_Pos      (0U)\r
-#define CAN_FA1R_FACT_Msk      (0x3FFFUL << CAN_FA1R_FACT_Pos)                 /*!< 0x00003FFF */\r
-#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\r
-#define CAN_FA1R_FACT0_Pos     (0U)\r
-#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                   /*!< 0x00000001 */\r
-#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */\r
-#define CAN_FA1R_FACT1_Pos     (1U)\r
-#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                   /*!< 0x00000002 */\r
-#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */\r
-#define CAN_FA1R_FACT2_Pos     (2U)\r
-#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                   /*!< 0x00000004 */\r
-#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */\r
-#define CAN_FA1R_FACT3_Pos     (3U)\r
-#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                   /*!< 0x00000008 */\r
-#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */\r
-#define CAN_FA1R_FACT4_Pos     (4U)\r
-#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                   /*!< 0x00000010 */\r
-#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */\r
-#define CAN_FA1R_FACT5_Pos     (5U)\r
-#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                   /*!< 0x00000020 */\r
-#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */\r
-#define CAN_FA1R_FACT6_Pos     (6U)\r
-#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                   /*!< 0x00000040 */\r
-#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */\r
-#define CAN_FA1R_FACT7_Pos     (7U)\r
-#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                   /*!< 0x00000080 */\r
-#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */\r
-#define CAN_FA1R_FACT8_Pos     (8U)\r
-#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                   /*!< 0x00000100 */\r
-#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */\r
-#define CAN_FA1R_FACT9_Pos     (9U)\r
-#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                   /*!< 0x00000200 */\r
-#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */\r
-#define CAN_FA1R_FACT10_Pos    (10U)\r
-#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                  /*!< 0x00000400 */\r
-#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */\r
-#define CAN_FA1R_FACT11_Pos    (11U)\r
-#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                  /*!< 0x00000800 */\r
-#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */\r
-#define CAN_FA1R_FACT12_Pos    (12U)\r
-#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                  /*!< 0x00001000 */\r
-#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */\r
-#define CAN_FA1R_FACT13_Pos    (13U)\r
-#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                  /*!< 0x00002000 */\r
-#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */\r
-\r
-/*******************  Bit definition for CAN_F0R1 register  *******************/\r
-#define CAN_F0R1_FB0_Pos       (0U)\r
-#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F0R1_FB1_Pos       (1U)\r
-#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F0R1_FB2_Pos       (2U)\r
-#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F0R1_FB3_Pos       (3U)\r
-#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F0R1_FB4_Pos       (4U)\r
-#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F0R1_FB5_Pos       (5U)\r
-#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F0R1_FB6_Pos       (6U)\r
-#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F0R1_FB7_Pos       (7U)\r
-#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F0R1_FB8_Pos       (8U)\r
-#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F0R1_FB9_Pos       (9U)\r
-#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F0R1_FB10_Pos      (10U)\r
-#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F0R1_FB11_Pos      (11U)\r
-#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F0R1_FB12_Pos      (12U)\r
-#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F0R1_FB13_Pos      (13U)\r
-#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F0R1_FB14_Pos      (14U)\r
-#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F0R1_FB15_Pos      (15U)\r
-#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F0R1_FB16_Pos      (16U)\r
-#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F0R1_FB17_Pos      (17U)\r
-#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F0R1_FB18_Pos      (18U)\r
-#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F0R1_FB19_Pos      (19U)\r
-#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F0R1_FB20_Pos      (20U)\r
-#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F0R1_FB21_Pos      (21U)\r
-#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F0R1_FB22_Pos      (22U)\r
-#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F0R1_FB23_Pos      (23U)\r
-#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F0R1_FB24_Pos      (24U)\r
-#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F0R1_FB25_Pos      (25U)\r
-#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F0R1_FB26_Pos      (26U)\r
-#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F0R1_FB27_Pos      (27U)\r
-#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F0R1_FB28_Pos      (28U)\r
-#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F0R1_FB29_Pos      (29U)\r
-#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F0R1_FB30_Pos      (30U)\r
-#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F0R1_FB31_Pos      (31U)\r
-#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F1R1 register  *******************/\r
-#define CAN_F1R1_FB0_Pos       (0U)\r
-#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F1R1_FB1_Pos       (1U)\r
-#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F1R1_FB2_Pos       (2U)\r
-#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F1R1_FB3_Pos       (3U)\r
-#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F1R1_FB4_Pos       (4U)\r
-#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F1R1_FB5_Pos       (5U)\r
-#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F1R1_FB6_Pos       (6U)\r
-#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F1R1_FB7_Pos       (7U)\r
-#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F1R1_FB8_Pos       (8U)\r
-#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F1R1_FB9_Pos       (9U)\r
-#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F1R1_FB10_Pos      (10U)\r
-#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F1R1_FB11_Pos      (11U)\r
-#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F1R1_FB12_Pos      (12U)\r
-#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F1R1_FB13_Pos      (13U)\r
-#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F1R1_FB14_Pos      (14U)\r
-#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F1R1_FB15_Pos      (15U)\r
-#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F1R1_FB16_Pos      (16U)\r
-#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F1R1_FB17_Pos      (17U)\r
-#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F1R1_FB18_Pos      (18U)\r
-#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F1R1_FB19_Pos      (19U)\r
-#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F1R1_FB20_Pos      (20U)\r
-#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F1R1_FB21_Pos      (21U)\r
-#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F1R1_FB22_Pos      (22U)\r
-#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F1R1_FB23_Pos      (23U)\r
-#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F1R1_FB24_Pos      (24U)\r
-#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F1R1_FB25_Pos      (25U)\r
-#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F1R1_FB26_Pos      (26U)\r
-#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F1R1_FB27_Pos      (27U)\r
-#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F1R1_FB28_Pos      (28U)\r
-#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F1R1_FB29_Pos      (29U)\r
-#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F1R1_FB30_Pos      (30U)\r
-#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F1R1_FB31_Pos      (31U)\r
-#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F2R1 register  *******************/\r
-#define CAN_F2R1_FB0_Pos       (0U)\r
-#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F2R1_FB1_Pos       (1U)\r
-#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F2R1_FB2_Pos       (2U)\r
-#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F2R1_FB3_Pos       (3U)\r
-#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F2R1_FB4_Pos       (4U)\r
-#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F2R1_FB5_Pos       (5U)\r
-#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F2R1_FB6_Pos       (6U)\r
-#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F2R1_FB7_Pos       (7U)\r
-#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F2R1_FB8_Pos       (8U)\r
-#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F2R1_FB9_Pos       (9U)\r
-#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F2R1_FB10_Pos      (10U)\r
-#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F2R1_FB11_Pos      (11U)\r
-#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F2R1_FB12_Pos      (12U)\r
-#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F2R1_FB13_Pos      (13U)\r
-#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F2R1_FB14_Pos      (14U)\r
-#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F2R1_FB15_Pos      (15U)\r
-#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F2R1_FB16_Pos      (16U)\r
-#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F2R1_FB17_Pos      (17U)\r
-#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F2R1_FB18_Pos      (18U)\r
-#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F2R1_FB19_Pos      (19U)\r
-#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F2R1_FB20_Pos      (20U)\r
-#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F2R1_FB21_Pos      (21U)\r
-#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F2R1_FB22_Pos      (22U)\r
-#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F2R1_FB23_Pos      (23U)\r
-#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F2R1_FB24_Pos      (24U)\r
-#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F2R1_FB25_Pos      (25U)\r
-#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F2R1_FB26_Pos      (26U)\r
-#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F2R1_FB27_Pos      (27U)\r
-#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F2R1_FB28_Pos      (28U)\r
-#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F2R1_FB29_Pos      (29U)\r
-#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F2R1_FB30_Pos      (30U)\r
-#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F2R1_FB31_Pos      (31U)\r
-#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F3R1 register  *******************/\r
-#define CAN_F3R1_FB0_Pos       (0U)\r
-#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F3R1_FB1_Pos       (1U)\r
-#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F3R1_FB2_Pos       (2U)\r
-#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F3R1_FB3_Pos       (3U)\r
-#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F3R1_FB4_Pos       (4U)\r
-#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F3R1_FB5_Pos       (5U)\r
-#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F3R1_FB6_Pos       (6U)\r
-#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F3R1_FB7_Pos       (7U)\r
-#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F3R1_FB8_Pos       (8U)\r
-#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F3R1_FB9_Pos       (9U)\r
-#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F3R1_FB10_Pos      (10U)\r
-#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F3R1_FB11_Pos      (11U)\r
-#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F3R1_FB12_Pos      (12U)\r
-#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F3R1_FB13_Pos      (13U)\r
-#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F3R1_FB14_Pos      (14U)\r
-#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F3R1_FB15_Pos      (15U)\r
-#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F3R1_FB16_Pos      (16U)\r
-#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F3R1_FB17_Pos      (17U)\r
-#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F3R1_FB18_Pos      (18U)\r
-#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F3R1_FB19_Pos      (19U)\r
-#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F3R1_FB20_Pos      (20U)\r
-#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F3R1_FB21_Pos      (21U)\r
-#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F3R1_FB22_Pos      (22U)\r
-#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F3R1_FB23_Pos      (23U)\r
-#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F3R1_FB24_Pos      (24U)\r
-#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F3R1_FB25_Pos      (25U)\r
-#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F3R1_FB26_Pos      (26U)\r
-#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F3R1_FB27_Pos      (27U)\r
-#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F3R1_FB28_Pos      (28U)\r
-#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F3R1_FB29_Pos      (29U)\r
-#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F3R1_FB30_Pos      (30U)\r
-#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F3R1_FB31_Pos      (31U)\r
-#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F4R1 register  *******************/\r
-#define CAN_F4R1_FB0_Pos       (0U)\r
-#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F4R1_FB1_Pos       (1U)\r
-#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F4R1_FB2_Pos       (2U)\r
-#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F4R1_FB3_Pos       (3U)\r
-#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F4R1_FB4_Pos       (4U)\r
-#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F4R1_FB5_Pos       (5U)\r
-#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F4R1_FB6_Pos       (6U)\r
-#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F4R1_FB7_Pos       (7U)\r
-#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F4R1_FB8_Pos       (8U)\r
-#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F4R1_FB9_Pos       (9U)\r
-#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F4R1_FB10_Pos      (10U)\r
-#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F4R1_FB11_Pos      (11U)\r
-#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F4R1_FB12_Pos      (12U)\r
-#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F4R1_FB13_Pos      (13U)\r
-#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F4R1_FB14_Pos      (14U)\r
-#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F4R1_FB15_Pos      (15U)\r
-#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F4R1_FB16_Pos      (16U)\r
-#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F4R1_FB17_Pos      (17U)\r
-#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F4R1_FB18_Pos      (18U)\r
-#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F4R1_FB19_Pos      (19U)\r
-#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F4R1_FB20_Pos      (20U)\r
-#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F4R1_FB21_Pos      (21U)\r
-#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F4R1_FB22_Pos      (22U)\r
-#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F4R1_FB23_Pos      (23U)\r
-#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F4R1_FB24_Pos      (24U)\r
-#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F4R1_FB25_Pos      (25U)\r
-#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F4R1_FB26_Pos      (26U)\r
-#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F4R1_FB27_Pos      (27U)\r
-#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F4R1_FB28_Pos      (28U)\r
-#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F4R1_FB29_Pos      (29U)\r
-#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F4R1_FB30_Pos      (30U)\r
-#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F4R1_FB31_Pos      (31U)\r
-#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F5R1 register  *******************/\r
-#define CAN_F5R1_FB0_Pos       (0U)\r
-#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F5R1_FB1_Pos       (1U)\r
-#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F5R1_FB2_Pos       (2U)\r
-#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F5R1_FB3_Pos       (3U)\r
-#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F5R1_FB4_Pos       (4U)\r
-#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F5R1_FB5_Pos       (5U)\r
-#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F5R1_FB6_Pos       (6U)\r
-#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F5R1_FB7_Pos       (7U)\r
-#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F5R1_FB8_Pos       (8U)\r
-#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F5R1_FB9_Pos       (9U)\r
-#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F5R1_FB10_Pos      (10U)\r
-#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F5R1_FB11_Pos      (11U)\r
-#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F5R1_FB12_Pos      (12U)\r
-#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F5R1_FB13_Pos      (13U)\r
-#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F5R1_FB14_Pos      (14U)\r
-#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F5R1_FB15_Pos      (15U)\r
-#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F5R1_FB16_Pos      (16U)\r
-#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F5R1_FB17_Pos      (17U)\r
-#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F5R1_FB18_Pos      (18U)\r
-#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F5R1_FB19_Pos      (19U)\r
-#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F5R1_FB20_Pos      (20U)\r
-#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F5R1_FB21_Pos      (21U)\r
-#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F5R1_FB22_Pos      (22U)\r
-#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F5R1_FB23_Pos      (23U)\r
-#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F5R1_FB24_Pos      (24U)\r
-#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F5R1_FB25_Pos      (25U)\r
-#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F5R1_FB26_Pos      (26U)\r
-#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F5R1_FB27_Pos      (27U)\r
-#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F5R1_FB28_Pos      (28U)\r
-#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F5R1_FB29_Pos      (29U)\r
-#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F5R1_FB30_Pos      (30U)\r
-#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F5R1_FB31_Pos      (31U)\r
-#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F6R1 register  *******************/\r
-#define CAN_F6R1_FB0_Pos       (0U)\r
-#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F6R1_FB1_Pos       (1U)\r
-#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F6R1_FB2_Pos       (2U)\r
-#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F6R1_FB3_Pos       (3U)\r
-#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F6R1_FB4_Pos       (4U)\r
-#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F6R1_FB5_Pos       (5U)\r
-#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F6R1_FB6_Pos       (6U)\r
-#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F6R1_FB7_Pos       (7U)\r
-#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F6R1_FB8_Pos       (8U)\r
-#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F6R1_FB9_Pos       (9U)\r
-#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F6R1_FB10_Pos      (10U)\r
-#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F6R1_FB11_Pos      (11U)\r
-#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F6R1_FB12_Pos      (12U)\r
-#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F6R1_FB13_Pos      (13U)\r
-#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F6R1_FB14_Pos      (14U)\r
-#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F6R1_FB15_Pos      (15U)\r
-#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F6R1_FB16_Pos      (16U)\r
-#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F6R1_FB17_Pos      (17U)\r
-#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F6R1_FB18_Pos      (18U)\r
-#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F6R1_FB19_Pos      (19U)\r
-#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F6R1_FB20_Pos      (20U)\r
-#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F6R1_FB21_Pos      (21U)\r
-#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F6R1_FB22_Pos      (22U)\r
-#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F6R1_FB23_Pos      (23U)\r
-#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F6R1_FB24_Pos      (24U)\r
-#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F6R1_FB25_Pos      (25U)\r
-#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F6R1_FB26_Pos      (26U)\r
-#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F6R1_FB27_Pos      (27U)\r
-#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F6R1_FB28_Pos      (28U)\r
-#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F6R1_FB29_Pos      (29U)\r
-#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F6R1_FB30_Pos      (30U)\r
-#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F6R1_FB31_Pos      (31U)\r
-#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F7R1 register  *******************/\r
-#define CAN_F7R1_FB0_Pos       (0U)\r
-#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F7R1_FB1_Pos       (1U)\r
-#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F7R1_FB2_Pos       (2U)\r
-#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F7R1_FB3_Pos       (3U)\r
-#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F7R1_FB4_Pos       (4U)\r
-#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F7R1_FB5_Pos       (5U)\r
-#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F7R1_FB6_Pos       (6U)\r
-#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F7R1_FB7_Pos       (7U)\r
-#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F7R1_FB8_Pos       (8U)\r
-#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F7R1_FB9_Pos       (9U)\r
-#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F7R1_FB10_Pos      (10U)\r
-#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F7R1_FB11_Pos      (11U)\r
-#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F7R1_FB12_Pos      (12U)\r
-#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F7R1_FB13_Pos      (13U)\r
-#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F7R1_FB14_Pos      (14U)\r
-#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F7R1_FB15_Pos      (15U)\r
-#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F7R1_FB16_Pos      (16U)\r
-#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F7R1_FB17_Pos      (17U)\r
-#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F7R1_FB18_Pos      (18U)\r
-#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F7R1_FB19_Pos      (19U)\r
-#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F7R1_FB20_Pos      (20U)\r
-#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F7R1_FB21_Pos      (21U)\r
-#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F7R1_FB22_Pos      (22U)\r
-#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F7R1_FB23_Pos      (23U)\r
-#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F7R1_FB24_Pos      (24U)\r
-#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F7R1_FB25_Pos      (25U)\r
-#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F7R1_FB26_Pos      (26U)\r
-#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F7R1_FB27_Pos      (27U)\r
-#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F7R1_FB28_Pos      (28U)\r
-#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F7R1_FB29_Pos      (29U)\r
-#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F7R1_FB30_Pos      (30U)\r
-#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F7R1_FB31_Pos      (31U)\r
-#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F8R1 register  *******************/\r
-#define CAN_F8R1_FB0_Pos       (0U)\r
-#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F8R1_FB1_Pos       (1U)\r
-#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F8R1_FB2_Pos       (2U)\r
-#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F8R1_FB3_Pos       (3U)\r
-#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F8R1_FB4_Pos       (4U)\r
-#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F8R1_FB5_Pos       (5U)\r
-#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F8R1_FB6_Pos       (6U)\r
-#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F8R1_FB7_Pos       (7U)\r
-#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F8R1_FB8_Pos       (8U)\r
-#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F8R1_FB9_Pos       (9U)\r
-#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F8R1_FB10_Pos      (10U)\r
-#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F8R1_FB11_Pos      (11U)\r
-#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F8R1_FB12_Pos      (12U)\r
-#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F8R1_FB13_Pos      (13U)\r
-#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F8R1_FB14_Pos      (14U)\r
-#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F8R1_FB15_Pos      (15U)\r
-#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F8R1_FB16_Pos      (16U)\r
-#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F8R1_FB17_Pos      (17U)\r
-#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F8R1_FB18_Pos      (18U)\r
-#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F8R1_FB19_Pos      (19U)\r
-#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F8R1_FB20_Pos      (20U)\r
-#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F8R1_FB21_Pos      (21U)\r
-#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F8R1_FB22_Pos      (22U)\r
-#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F8R1_FB23_Pos      (23U)\r
-#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F8R1_FB24_Pos      (24U)\r
-#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F8R1_FB25_Pos      (25U)\r
-#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F8R1_FB26_Pos      (26U)\r
-#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F8R1_FB27_Pos      (27U)\r
-#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F8R1_FB28_Pos      (28U)\r
-#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F8R1_FB29_Pos      (29U)\r
-#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F8R1_FB30_Pos      (30U)\r
-#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F8R1_FB31_Pos      (31U)\r
-#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F9R1 register  *******************/\r
-#define CAN_F9R1_FB0_Pos       (0U)\r
-#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F9R1_FB1_Pos       (1U)\r
-#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F9R1_FB2_Pos       (2U)\r
-#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F9R1_FB3_Pos       (3U)\r
-#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F9R1_FB4_Pos       (4U)\r
-#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F9R1_FB5_Pos       (5U)\r
-#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F9R1_FB6_Pos       (6U)\r
-#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F9R1_FB7_Pos       (7U)\r
-#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F9R1_FB8_Pos       (8U)\r
-#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F9R1_FB9_Pos       (9U)\r
-#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F9R1_FB10_Pos      (10U)\r
-#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F9R1_FB11_Pos      (11U)\r
-#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F9R1_FB12_Pos      (12U)\r
-#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F9R1_FB13_Pos      (13U)\r
-#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F9R1_FB14_Pos      (14U)\r
-#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F9R1_FB15_Pos      (15U)\r
-#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F9R1_FB16_Pos      (16U)\r
-#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F9R1_FB17_Pos      (17U)\r
-#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F9R1_FB18_Pos      (18U)\r
-#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F9R1_FB19_Pos      (19U)\r
-#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F9R1_FB20_Pos      (20U)\r
-#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F9R1_FB21_Pos      (21U)\r
-#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F9R1_FB22_Pos      (22U)\r
-#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F9R1_FB23_Pos      (23U)\r
-#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F9R1_FB24_Pos      (24U)\r
-#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F9R1_FB25_Pos      (25U)\r
-#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F9R1_FB26_Pos      (26U)\r
-#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F9R1_FB27_Pos      (27U)\r
-#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F9R1_FB28_Pos      (28U)\r
-#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F9R1_FB29_Pos      (29U)\r
-#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F9R1_FB30_Pos      (30U)\r
-#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F9R1_FB31_Pos      (31U)\r
-#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F10R1 register  ******************/\r
-#define CAN_F10R1_FB0_Pos      (0U)\r
-#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F10R1_FB1_Pos      (1U)\r
-#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F10R1_FB2_Pos      (2U)\r
-#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F10R1_FB3_Pos      (3U)\r
-#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F10R1_FB4_Pos      (4U)\r
-#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F10R1_FB5_Pos      (5U)\r
-#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F10R1_FB6_Pos      (6U)\r
-#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F10R1_FB7_Pos      (7U)\r
-#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F10R1_FB8_Pos      (8U)\r
-#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F10R1_FB9_Pos      (9U)\r
-#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F10R1_FB10_Pos     (10U)\r
-#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F10R1_FB11_Pos     (11U)\r
-#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F10R1_FB12_Pos     (12U)\r
-#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F10R1_FB13_Pos     (13U)\r
-#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F10R1_FB14_Pos     (14U)\r
-#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F10R1_FB15_Pos     (15U)\r
-#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F10R1_FB16_Pos     (16U)\r
-#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F10R1_FB17_Pos     (17U)\r
-#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F10R1_FB18_Pos     (18U)\r
-#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F10R1_FB19_Pos     (19U)\r
-#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F10R1_FB20_Pos     (20U)\r
-#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F10R1_FB21_Pos     (21U)\r
-#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F10R1_FB22_Pos     (22U)\r
-#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F10R1_FB23_Pos     (23U)\r
-#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F10R1_FB24_Pos     (24U)\r
-#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F10R1_FB25_Pos     (25U)\r
-#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F10R1_FB26_Pos     (26U)\r
-#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F10R1_FB27_Pos     (27U)\r
-#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F10R1_FB28_Pos     (28U)\r
-#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F10R1_FB29_Pos     (29U)\r
-#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F10R1_FB30_Pos     (30U)\r
-#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F10R1_FB31_Pos     (31U)\r
-#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F11R1 register  ******************/\r
-#define CAN_F11R1_FB0_Pos      (0U)\r
-#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F11R1_FB1_Pos      (1U)\r
-#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F11R1_FB2_Pos      (2U)\r
-#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F11R1_FB3_Pos      (3U)\r
-#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F11R1_FB4_Pos      (4U)\r
-#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F11R1_FB5_Pos      (5U)\r
-#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F11R1_FB6_Pos      (6U)\r
-#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F11R1_FB7_Pos      (7U)\r
-#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F11R1_FB8_Pos      (8U)\r
-#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F11R1_FB9_Pos      (9U)\r
-#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F11R1_FB10_Pos     (10U)\r
-#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F11R1_FB11_Pos     (11U)\r
-#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F11R1_FB12_Pos     (12U)\r
-#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F11R1_FB13_Pos     (13U)\r
-#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F11R1_FB14_Pos     (14U)\r
-#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F11R1_FB15_Pos     (15U)\r
-#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F11R1_FB16_Pos     (16U)\r
-#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F11R1_FB17_Pos     (17U)\r
-#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F11R1_FB18_Pos     (18U)\r
-#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F11R1_FB19_Pos     (19U)\r
-#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F11R1_FB20_Pos     (20U)\r
-#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F11R1_FB21_Pos     (21U)\r
-#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F11R1_FB22_Pos     (22U)\r
-#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F11R1_FB23_Pos     (23U)\r
-#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F11R1_FB24_Pos     (24U)\r
-#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F11R1_FB25_Pos     (25U)\r
-#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F11R1_FB26_Pos     (26U)\r
-#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F11R1_FB27_Pos     (27U)\r
-#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F11R1_FB28_Pos     (28U)\r
-#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F11R1_FB29_Pos     (29U)\r
-#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F11R1_FB30_Pos     (30U)\r
-#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F11R1_FB31_Pos     (31U)\r
-#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F12R1 register  ******************/\r
-#define CAN_F12R1_FB0_Pos      (0U)\r
-#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F12R1_FB1_Pos      (1U)\r
-#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F12R1_FB2_Pos      (2U)\r
-#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F12R1_FB3_Pos      (3U)\r
-#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F12R1_FB4_Pos      (4U)\r
-#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F12R1_FB5_Pos      (5U)\r
-#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F12R1_FB6_Pos      (6U)\r
-#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F12R1_FB7_Pos      (7U)\r
-#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F12R1_FB8_Pos      (8U)\r
-#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F12R1_FB9_Pos      (9U)\r
-#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F12R1_FB10_Pos     (10U)\r
-#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F12R1_FB11_Pos     (11U)\r
-#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F12R1_FB12_Pos     (12U)\r
-#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F12R1_FB13_Pos     (13U)\r
-#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F12R1_FB14_Pos     (14U)\r
-#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F12R1_FB15_Pos     (15U)\r
-#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F12R1_FB16_Pos     (16U)\r
-#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F12R1_FB17_Pos     (17U)\r
-#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F12R1_FB18_Pos     (18U)\r
-#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F12R1_FB19_Pos     (19U)\r
-#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F12R1_FB20_Pos     (20U)\r
-#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F12R1_FB21_Pos     (21U)\r
-#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F12R1_FB22_Pos     (22U)\r
-#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F12R1_FB23_Pos     (23U)\r
-#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F12R1_FB24_Pos     (24U)\r
-#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F12R1_FB25_Pos     (25U)\r
-#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F12R1_FB26_Pos     (26U)\r
-#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F12R1_FB27_Pos     (27U)\r
-#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F12R1_FB28_Pos     (28U)\r
-#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F12R1_FB29_Pos     (29U)\r
-#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F12R1_FB30_Pos     (30U)\r
-#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F12R1_FB31_Pos     (31U)\r
-#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F13R1 register  ******************/\r
-#define CAN_F13R1_FB0_Pos      (0U)\r
-#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F13R1_FB1_Pos      (1U)\r
-#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F13R1_FB2_Pos      (2U)\r
-#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F13R1_FB3_Pos      (3U)\r
-#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F13R1_FB4_Pos      (4U)\r
-#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F13R1_FB5_Pos      (5U)\r
-#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F13R1_FB6_Pos      (6U)\r
-#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F13R1_FB7_Pos      (7U)\r
-#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F13R1_FB8_Pos      (8U)\r
-#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F13R1_FB9_Pos      (9U)\r
-#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F13R1_FB10_Pos     (10U)\r
-#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F13R1_FB11_Pos     (11U)\r
-#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F13R1_FB12_Pos     (12U)\r
-#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F13R1_FB13_Pos     (13U)\r
-#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F13R1_FB14_Pos     (14U)\r
-#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F13R1_FB15_Pos     (15U)\r
-#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F13R1_FB16_Pos     (16U)\r
-#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F13R1_FB17_Pos     (17U)\r
-#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F13R1_FB18_Pos     (18U)\r
-#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F13R1_FB19_Pos     (19U)\r
-#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F13R1_FB20_Pos     (20U)\r
-#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F13R1_FB21_Pos     (21U)\r
-#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F13R1_FB22_Pos     (22U)\r
-#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F13R1_FB23_Pos     (23U)\r
-#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F13R1_FB24_Pos     (24U)\r
-#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F13R1_FB25_Pos     (25U)\r
-#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F13R1_FB26_Pos     (26U)\r
-#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F13R1_FB27_Pos     (27U)\r
-#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F13R1_FB28_Pos     (28U)\r
-#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F13R1_FB29_Pos     (29U)\r
-#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F13R1_FB30_Pos     (30U)\r
-#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F13R1_FB31_Pos     (31U)\r
-#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F0R2 register  *******************/\r
-#define CAN_F0R2_FB0_Pos       (0U)\r
-#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F0R2_FB1_Pos       (1U)\r
-#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F0R2_FB2_Pos       (2U)\r
-#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F0R2_FB3_Pos       (3U)\r
-#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F0R2_FB4_Pos       (4U)\r
-#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F0R2_FB5_Pos       (5U)\r
-#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F0R2_FB6_Pos       (6U)\r
-#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F0R2_FB7_Pos       (7U)\r
-#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F0R2_FB8_Pos       (8U)\r
-#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F0R2_FB9_Pos       (9U)\r
-#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F0R2_FB10_Pos      (10U)\r
-#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F0R2_FB11_Pos      (11U)\r
-#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F0R2_FB12_Pos      (12U)\r
-#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F0R2_FB13_Pos      (13U)\r
-#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F0R2_FB14_Pos      (14U)\r
-#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F0R2_FB15_Pos      (15U)\r
-#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F0R2_FB16_Pos      (16U)\r
-#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F0R2_FB17_Pos      (17U)\r
-#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F0R2_FB18_Pos      (18U)\r
-#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F0R2_FB19_Pos      (19U)\r
-#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F0R2_FB20_Pos      (20U)\r
-#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F0R2_FB21_Pos      (21U)\r
-#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F0R2_FB22_Pos      (22U)\r
-#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F0R2_FB23_Pos      (23U)\r
-#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F0R2_FB24_Pos      (24U)\r
-#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F0R2_FB25_Pos      (25U)\r
-#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F0R2_FB26_Pos      (26U)\r
-#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F0R2_FB27_Pos      (27U)\r
-#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F0R2_FB28_Pos      (28U)\r
-#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F0R2_FB29_Pos      (29U)\r
-#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F0R2_FB30_Pos      (30U)\r
-#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F0R2_FB31_Pos      (31U)\r
-#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F1R2 register  *******************/\r
-#define CAN_F1R2_FB0_Pos       (0U)\r
-#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F1R2_FB1_Pos       (1U)\r
-#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F1R2_FB2_Pos       (2U)\r
-#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F1R2_FB3_Pos       (3U)\r
-#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F1R2_FB4_Pos       (4U)\r
-#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F1R2_FB5_Pos       (5U)\r
-#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F1R2_FB6_Pos       (6U)\r
-#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F1R2_FB7_Pos       (7U)\r
-#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F1R2_FB8_Pos       (8U)\r
-#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F1R2_FB9_Pos       (9U)\r
-#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F1R2_FB10_Pos      (10U)\r
-#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F1R2_FB11_Pos      (11U)\r
-#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F1R2_FB12_Pos      (12U)\r
-#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F1R2_FB13_Pos      (13U)\r
-#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F1R2_FB14_Pos      (14U)\r
-#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F1R2_FB15_Pos      (15U)\r
-#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F1R2_FB16_Pos      (16U)\r
-#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F1R2_FB17_Pos      (17U)\r
-#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F1R2_FB18_Pos      (18U)\r
-#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F1R2_FB19_Pos      (19U)\r
-#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F1R2_FB20_Pos      (20U)\r
-#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F1R2_FB21_Pos      (21U)\r
-#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F1R2_FB22_Pos      (22U)\r
-#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F1R2_FB23_Pos      (23U)\r
-#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F1R2_FB24_Pos      (24U)\r
-#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F1R2_FB25_Pos      (25U)\r
-#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F1R2_FB26_Pos      (26U)\r
-#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F1R2_FB27_Pos      (27U)\r
-#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F1R2_FB28_Pos      (28U)\r
-#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F1R2_FB29_Pos      (29U)\r
-#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F1R2_FB30_Pos      (30U)\r
-#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F1R2_FB31_Pos      (31U)\r
-#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F2R2 register  *******************/\r
-#define CAN_F2R2_FB0_Pos       (0U)\r
-#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F2R2_FB1_Pos       (1U)\r
-#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F2R2_FB2_Pos       (2U)\r
-#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F2R2_FB3_Pos       (3U)\r
-#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F2R2_FB4_Pos       (4U)\r
-#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F2R2_FB5_Pos       (5U)\r
-#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F2R2_FB6_Pos       (6U)\r
-#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F2R2_FB7_Pos       (7U)\r
-#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F2R2_FB8_Pos       (8U)\r
-#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F2R2_FB9_Pos       (9U)\r
-#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F2R2_FB10_Pos      (10U)\r
-#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F2R2_FB11_Pos      (11U)\r
-#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F2R2_FB12_Pos      (12U)\r
-#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F2R2_FB13_Pos      (13U)\r
-#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F2R2_FB14_Pos      (14U)\r
-#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F2R2_FB15_Pos      (15U)\r
-#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F2R2_FB16_Pos      (16U)\r
-#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F2R2_FB17_Pos      (17U)\r
-#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F2R2_FB18_Pos      (18U)\r
-#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F2R2_FB19_Pos      (19U)\r
-#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F2R2_FB20_Pos      (20U)\r
-#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F2R2_FB21_Pos      (21U)\r
-#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F2R2_FB22_Pos      (22U)\r
-#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F2R2_FB23_Pos      (23U)\r
-#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F2R2_FB24_Pos      (24U)\r
-#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F2R2_FB25_Pos      (25U)\r
-#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F2R2_FB26_Pos      (26U)\r
-#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F2R2_FB27_Pos      (27U)\r
-#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F2R2_FB28_Pos      (28U)\r
-#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F2R2_FB29_Pos      (29U)\r
-#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F2R2_FB30_Pos      (30U)\r
-#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F2R2_FB31_Pos      (31U)\r
-#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F3R2 register  *******************/\r
-#define CAN_F3R2_FB0_Pos       (0U)\r
-#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F3R2_FB1_Pos       (1U)\r
-#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F3R2_FB2_Pos       (2U)\r
-#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F3R2_FB3_Pos       (3U)\r
-#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F3R2_FB4_Pos       (4U)\r
-#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F3R2_FB5_Pos       (5U)\r
-#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F3R2_FB6_Pos       (6U)\r
-#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F3R2_FB7_Pos       (7U)\r
-#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F3R2_FB8_Pos       (8U)\r
-#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F3R2_FB9_Pos       (9U)\r
-#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F3R2_FB10_Pos      (10U)\r
-#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F3R2_FB11_Pos      (11U)\r
-#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F3R2_FB12_Pos      (12U)\r
-#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F3R2_FB13_Pos      (13U)\r
-#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F3R2_FB14_Pos      (14U)\r
-#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F3R2_FB15_Pos      (15U)\r
-#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F3R2_FB16_Pos      (16U)\r
-#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F3R2_FB17_Pos      (17U)\r
-#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F3R2_FB18_Pos      (18U)\r
-#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F3R2_FB19_Pos      (19U)\r
-#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F3R2_FB20_Pos      (20U)\r
-#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F3R2_FB21_Pos      (21U)\r
-#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F3R2_FB22_Pos      (22U)\r
-#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F3R2_FB23_Pos      (23U)\r
-#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F3R2_FB24_Pos      (24U)\r
-#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F3R2_FB25_Pos      (25U)\r
-#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F3R2_FB26_Pos      (26U)\r
-#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F3R2_FB27_Pos      (27U)\r
-#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F3R2_FB28_Pos      (28U)\r
-#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F3R2_FB29_Pos      (29U)\r
-#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F3R2_FB30_Pos      (30U)\r
-#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F3R2_FB31_Pos      (31U)\r
-#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F4R2 register  *******************/\r
-#define CAN_F4R2_FB0_Pos       (0U)\r
-#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F4R2_FB1_Pos       (1U)\r
-#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F4R2_FB2_Pos       (2U)\r
-#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F4R2_FB3_Pos       (3U)\r
-#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F4R2_FB4_Pos       (4U)\r
-#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F4R2_FB5_Pos       (5U)\r
-#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F4R2_FB6_Pos       (6U)\r
-#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F4R2_FB7_Pos       (7U)\r
-#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F4R2_FB8_Pos       (8U)\r
-#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F4R2_FB9_Pos       (9U)\r
-#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F4R2_FB10_Pos      (10U)\r
-#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F4R2_FB11_Pos      (11U)\r
-#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F4R2_FB12_Pos      (12U)\r
-#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F4R2_FB13_Pos      (13U)\r
-#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F4R2_FB14_Pos      (14U)\r
-#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F4R2_FB15_Pos      (15U)\r
-#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F4R2_FB16_Pos      (16U)\r
-#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F4R2_FB17_Pos      (17U)\r
-#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F4R2_FB18_Pos      (18U)\r
-#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F4R2_FB19_Pos      (19U)\r
-#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F4R2_FB20_Pos      (20U)\r
-#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F4R2_FB21_Pos      (21U)\r
-#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F4R2_FB22_Pos      (22U)\r
-#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F4R2_FB23_Pos      (23U)\r
-#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F4R2_FB24_Pos      (24U)\r
-#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F4R2_FB25_Pos      (25U)\r
-#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F4R2_FB26_Pos      (26U)\r
-#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F4R2_FB27_Pos      (27U)\r
-#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F4R2_FB28_Pos      (28U)\r
-#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F4R2_FB29_Pos      (29U)\r
-#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F4R2_FB30_Pos      (30U)\r
-#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F4R2_FB31_Pos      (31U)\r
-#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F5R2 register  *******************/\r
-#define CAN_F5R2_FB0_Pos       (0U)\r
-#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F5R2_FB1_Pos       (1U)\r
-#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F5R2_FB2_Pos       (2U)\r
-#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F5R2_FB3_Pos       (3U)\r
-#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F5R2_FB4_Pos       (4U)\r
-#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F5R2_FB5_Pos       (5U)\r
-#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F5R2_FB6_Pos       (6U)\r
-#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F5R2_FB7_Pos       (7U)\r
-#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F5R2_FB8_Pos       (8U)\r
-#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F5R2_FB9_Pos       (9U)\r
-#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F5R2_FB10_Pos      (10U)\r
-#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F5R2_FB11_Pos      (11U)\r
-#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F5R2_FB12_Pos      (12U)\r
-#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F5R2_FB13_Pos      (13U)\r
-#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F5R2_FB14_Pos      (14U)\r
-#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F5R2_FB15_Pos      (15U)\r
-#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F5R2_FB16_Pos      (16U)\r
-#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F5R2_FB17_Pos      (17U)\r
-#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F5R2_FB18_Pos      (18U)\r
-#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F5R2_FB19_Pos      (19U)\r
-#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F5R2_FB20_Pos      (20U)\r
-#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F5R2_FB21_Pos      (21U)\r
-#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F5R2_FB22_Pos      (22U)\r
-#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F5R2_FB23_Pos      (23U)\r
-#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F5R2_FB24_Pos      (24U)\r
-#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F5R2_FB25_Pos      (25U)\r
-#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F5R2_FB26_Pos      (26U)\r
-#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F5R2_FB27_Pos      (27U)\r
-#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F5R2_FB28_Pos      (28U)\r
-#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F5R2_FB29_Pos      (29U)\r
-#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F5R2_FB30_Pos      (30U)\r
-#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F5R2_FB31_Pos      (31U)\r
-#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F6R2 register  *******************/\r
-#define CAN_F6R2_FB0_Pos       (0U)\r
-#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F6R2_FB1_Pos       (1U)\r
-#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F6R2_FB2_Pos       (2U)\r
-#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F6R2_FB3_Pos       (3U)\r
-#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F6R2_FB4_Pos       (4U)\r
-#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F6R2_FB5_Pos       (5U)\r
-#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F6R2_FB6_Pos       (6U)\r
-#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F6R2_FB7_Pos       (7U)\r
-#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F6R2_FB8_Pos       (8U)\r
-#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F6R2_FB9_Pos       (9U)\r
-#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F6R2_FB10_Pos      (10U)\r
-#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F6R2_FB11_Pos      (11U)\r
-#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F6R2_FB12_Pos      (12U)\r
-#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F6R2_FB13_Pos      (13U)\r
-#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F6R2_FB14_Pos      (14U)\r
-#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F6R2_FB15_Pos      (15U)\r
-#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F6R2_FB16_Pos      (16U)\r
-#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F6R2_FB17_Pos      (17U)\r
-#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F6R2_FB18_Pos      (18U)\r
-#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F6R2_FB19_Pos      (19U)\r
-#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F6R2_FB20_Pos      (20U)\r
-#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F6R2_FB21_Pos      (21U)\r
-#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F6R2_FB22_Pos      (22U)\r
-#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F6R2_FB23_Pos      (23U)\r
-#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F6R2_FB24_Pos      (24U)\r
-#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F6R2_FB25_Pos      (25U)\r
-#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F6R2_FB26_Pos      (26U)\r
-#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F6R2_FB27_Pos      (27U)\r
-#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F6R2_FB28_Pos      (28U)\r
-#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F6R2_FB29_Pos      (29U)\r
-#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F6R2_FB30_Pos      (30U)\r
-#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F6R2_FB31_Pos      (31U)\r
-#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F7R2 register  *******************/\r
-#define CAN_F7R2_FB0_Pos       (0U)\r
-#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F7R2_FB1_Pos       (1U)\r
-#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F7R2_FB2_Pos       (2U)\r
-#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F7R2_FB3_Pos       (3U)\r
-#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F7R2_FB4_Pos       (4U)\r
-#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F7R2_FB5_Pos       (5U)\r
-#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F7R2_FB6_Pos       (6U)\r
-#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F7R2_FB7_Pos       (7U)\r
-#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F7R2_FB8_Pos       (8U)\r
-#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F7R2_FB9_Pos       (9U)\r
-#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F7R2_FB10_Pos      (10U)\r
-#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F7R2_FB11_Pos      (11U)\r
-#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F7R2_FB12_Pos      (12U)\r
-#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F7R2_FB13_Pos      (13U)\r
-#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F7R2_FB14_Pos      (14U)\r
-#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F7R2_FB15_Pos      (15U)\r
-#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F7R2_FB16_Pos      (16U)\r
-#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F7R2_FB17_Pos      (17U)\r
-#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F7R2_FB18_Pos      (18U)\r
-#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F7R2_FB19_Pos      (19U)\r
-#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F7R2_FB20_Pos      (20U)\r
-#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F7R2_FB21_Pos      (21U)\r
-#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F7R2_FB22_Pos      (22U)\r
-#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F7R2_FB23_Pos      (23U)\r
-#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F7R2_FB24_Pos      (24U)\r
-#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F7R2_FB25_Pos      (25U)\r
-#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F7R2_FB26_Pos      (26U)\r
-#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F7R2_FB27_Pos      (27U)\r
-#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F7R2_FB28_Pos      (28U)\r
-#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F7R2_FB29_Pos      (29U)\r
-#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F7R2_FB30_Pos      (30U)\r
-#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F7R2_FB31_Pos      (31U)\r
-#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F8R2 register  *******************/\r
-#define CAN_F8R2_FB0_Pos       (0U)\r
-#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F8R2_FB1_Pos       (1U)\r
-#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F8R2_FB2_Pos       (2U)\r
-#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F8R2_FB3_Pos       (3U)\r
-#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F8R2_FB4_Pos       (4U)\r
-#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F8R2_FB5_Pos       (5U)\r
-#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F8R2_FB6_Pos       (6U)\r
-#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F8R2_FB7_Pos       (7U)\r
-#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F8R2_FB8_Pos       (8U)\r
-#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F8R2_FB9_Pos       (9U)\r
-#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F8R2_FB10_Pos      (10U)\r
-#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F8R2_FB11_Pos      (11U)\r
-#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F8R2_FB12_Pos      (12U)\r
-#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F8R2_FB13_Pos      (13U)\r
-#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F8R2_FB14_Pos      (14U)\r
-#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F8R2_FB15_Pos      (15U)\r
-#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F8R2_FB16_Pos      (16U)\r
-#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F8R2_FB17_Pos      (17U)\r
-#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F8R2_FB18_Pos      (18U)\r
-#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F8R2_FB19_Pos      (19U)\r
-#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F8R2_FB20_Pos      (20U)\r
-#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F8R2_FB21_Pos      (21U)\r
-#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F8R2_FB22_Pos      (22U)\r
-#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F8R2_FB23_Pos      (23U)\r
-#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F8R2_FB24_Pos      (24U)\r
-#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F8R2_FB25_Pos      (25U)\r
-#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F8R2_FB26_Pos      (26U)\r
-#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F8R2_FB27_Pos      (27U)\r
-#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F8R2_FB28_Pos      (28U)\r
-#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F8R2_FB29_Pos      (29U)\r
-#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F8R2_FB30_Pos      (30U)\r
-#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F8R2_FB31_Pos      (31U)\r
-#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F9R2 register  *******************/\r
-#define CAN_F9R2_FB0_Pos       (0U)\r
-#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                     /*!< 0x00000001 */\r
-#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\r
-#define CAN_F9R2_FB1_Pos       (1U)\r
-#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                     /*!< 0x00000002 */\r
-#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\r
-#define CAN_F9R2_FB2_Pos       (2U)\r
-#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                     /*!< 0x00000004 */\r
-#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\r
-#define CAN_F9R2_FB3_Pos       (3U)\r
-#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                     /*!< 0x00000008 */\r
-#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\r
-#define CAN_F9R2_FB4_Pos       (4U)\r
-#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                     /*!< 0x00000010 */\r
-#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\r
-#define CAN_F9R2_FB5_Pos       (5U)\r
-#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                     /*!< 0x00000020 */\r
-#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\r
-#define CAN_F9R2_FB6_Pos       (6U)\r
-#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                     /*!< 0x00000040 */\r
-#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\r
-#define CAN_F9R2_FB7_Pos       (7U)\r
-#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                     /*!< 0x00000080 */\r
-#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\r
-#define CAN_F9R2_FB8_Pos       (8U)\r
-#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                     /*!< 0x00000100 */\r
-#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\r
-#define CAN_F9R2_FB9_Pos       (9U)\r
-#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                     /*!< 0x00000200 */\r
-#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\r
-#define CAN_F9R2_FB10_Pos      (10U)\r
-#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                    /*!< 0x00000400 */\r
-#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\r
-#define CAN_F9R2_FB11_Pos      (11U)\r
-#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                    /*!< 0x00000800 */\r
-#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\r
-#define CAN_F9R2_FB12_Pos      (12U)\r
-#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                    /*!< 0x00001000 */\r
-#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\r
-#define CAN_F9R2_FB13_Pos      (13U)\r
-#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                    /*!< 0x00002000 */\r
-#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\r
-#define CAN_F9R2_FB14_Pos      (14U)\r
-#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                    /*!< 0x00004000 */\r
-#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\r
-#define CAN_F9R2_FB15_Pos      (15U)\r
-#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                    /*!< 0x00008000 */\r
-#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\r
-#define CAN_F9R2_FB16_Pos      (16U)\r
-#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                    /*!< 0x00010000 */\r
-#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\r
-#define CAN_F9R2_FB17_Pos      (17U)\r
-#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                    /*!< 0x00020000 */\r
-#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\r
-#define CAN_F9R2_FB18_Pos      (18U)\r
-#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                    /*!< 0x00040000 */\r
-#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\r
-#define CAN_F9R2_FB19_Pos      (19U)\r
-#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                    /*!< 0x00080000 */\r
-#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\r
-#define CAN_F9R2_FB20_Pos      (20U)\r
-#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                    /*!< 0x00100000 */\r
-#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\r
-#define CAN_F9R2_FB21_Pos      (21U)\r
-#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                    /*!< 0x00200000 */\r
-#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\r
-#define CAN_F9R2_FB22_Pos      (22U)\r
-#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                    /*!< 0x00400000 */\r
-#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\r
-#define CAN_F9R2_FB23_Pos      (23U)\r
-#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                    /*!< 0x00800000 */\r
-#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\r
-#define CAN_F9R2_FB24_Pos      (24U)\r
-#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                    /*!< 0x01000000 */\r
-#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\r
-#define CAN_F9R2_FB25_Pos      (25U)\r
-#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                    /*!< 0x02000000 */\r
-#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\r
-#define CAN_F9R2_FB26_Pos      (26U)\r
-#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                    /*!< 0x04000000 */\r
-#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\r
-#define CAN_F9R2_FB27_Pos      (27U)\r
-#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                    /*!< 0x08000000 */\r
-#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\r
-#define CAN_F9R2_FB28_Pos      (28U)\r
-#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                    /*!< 0x10000000 */\r
-#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\r
-#define CAN_F9R2_FB29_Pos      (29U)\r
-#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                    /*!< 0x20000000 */\r
-#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\r
-#define CAN_F9R2_FB30_Pos      (30U)\r
-#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                    /*!< 0x40000000 */\r
-#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\r
-#define CAN_F9R2_FB31_Pos      (31U)\r
-#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                    /*!< 0x80000000 */\r
-#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F10R2 register  ******************/\r
-#define CAN_F10R2_FB0_Pos      (0U)\r
-#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F10R2_FB1_Pos      (1U)\r
-#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F10R2_FB2_Pos      (2U)\r
-#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F10R2_FB3_Pos      (3U)\r
-#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F10R2_FB4_Pos      (4U)\r
-#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F10R2_FB5_Pos      (5U)\r
-#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F10R2_FB6_Pos      (6U)\r
-#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F10R2_FB7_Pos      (7U)\r
-#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F10R2_FB8_Pos      (8U)\r
-#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F10R2_FB9_Pos      (9U)\r
-#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F10R2_FB10_Pos     (10U)\r
-#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F10R2_FB11_Pos     (11U)\r
-#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F10R2_FB12_Pos     (12U)\r
-#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F10R2_FB13_Pos     (13U)\r
-#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F10R2_FB14_Pos     (14U)\r
-#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F10R2_FB15_Pos     (15U)\r
-#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F10R2_FB16_Pos     (16U)\r
-#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F10R2_FB17_Pos     (17U)\r
-#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F10R2_FB18_Pos     (18U)\r
-#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F10R2_FB19_Pos     (19U)\r
-#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F10R2_FB20_Pos     (20U)\r
-#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F10R2_FB21_Pos     (21U)\r
-#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F10R2_FB22_Pos     (22U)\r
-#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F10R2_FB23_Pos     (23U)\r
-#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F10R2_FB24_Pos     (24U)\r
-#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F10R2_FB25_Pos     (25U)\r
-#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F10R2_FB26_Pos     (26U)\r
-#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F10R2_FB27_Pos     (27U)\r
-#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F10R2_FB28_Pos     (28U)\r
-#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F10R2_FB29_Pos     (29U)\r
-#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F10R2_FB30_Pos     (30U)\r
-#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F10R2_FB31_Pos     (31U)\r
-#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F11R2 register  ******************/\r
-#define CAN_F11R2_FB0_Pos      (0U)\r
-#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F11R2_FB1_Pos      (1U)\r
-#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F11R2_FB2_Pos      (2U)\r
-#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F11R2_FB3_Pos      (3U)\r
-#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F11R2_FB4_Pos      (4U)\r
-#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F11R2_FB5_Pos      (5U)\r
-#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F11R2_FB6_Pos      (6U)\r
-#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F11R2_FB7_Pos      (7U)\r
-#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F11R2_FB8_Pos      (8U)\r
-#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F11R2_FB9_Pos      (9U)\r
-#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F11R2_FB10_Pos     (10U)\r
-#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F11R2_FB11_Pos     (11U)\r
-#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F11R2_FB12_Pos     (12U)\r
-#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F11R2_FB13_Pos     (13U)\r
-#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F11R2_FB14_Pos     (14U)\r
-#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F11R2_FB15_Pos     (15U)\r
-#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F11R2_FB16_Pos     (16U)\r
-#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F11R2_FB17_Pos     (17U)\r
-#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F11R2_FB18_Pos     (18U)\r
-#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F11R2_FB19_Pos     (19U)\r
-#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F11R2_FB20_Pos     (20U)\r
-#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F11R2_FB21_Pos     (21U)\r
-#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F11R2_FB22_Pos     (22U)\r
-#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F11R2_FB23_Pos     (23U)\r
-#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F11R2_FB24_Pos     (24U)\r
-#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F11R2_FB25_Pos     (25U)\r
-#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F11R2_FB26_Pos     (26U)\r
-#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F11R2_FB27_Pos     (27U)\r
-#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F11R2_FB28_Pos     (28U)\r
-#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F11R2_FB29_Pos     (29U)\r
-#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F11R2_FB30_Pos     (30U)\r
-#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F11R2_FB31_Pos     (31U)\r
-#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F12R2 register  ******************/\r
-#define CAN_F12R2_FB0_Pos      (0U)\r
-#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F12R2_FB1_Pos      (1U)\r
-#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F12R2_FB2_Pos      (2U)\r
-#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F12R2_FB3_Pos      (3U)\r
-#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F12R2_FB4_Pos      (4U)\r
-#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F12R2_FB5_Pos      (5U)\r
-#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F12R2_FB6_Pos      (6U)\r
-#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F12R2_FB7_Pos      (7U)\r
-#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F12R2_FB8_Pos      (8U)\r
-#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F12R2_FB9_Pos      (9U)\r
-#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F12R2_FB10_Pos     (10U)\r
-#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F12R2_FB11_Pos     (11U)\r
-#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F12R2_FB12_Pos     (12U)\r
-#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F12R2_FB13_Pos     (13U)\r
-#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F12R2_FB14_Pos     (14U)\r
-#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F12R2_FB15_Pos     (15U)\r
-#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F12R2_FB16_Pos     (16U)\r
-#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F12R2_FB17_Pos     (17U)\r
-#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F12R2_FB18_Pos     (18U)\r
-#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F12R2_FB19_Pos     (19U)\r
-#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F12R2_FB20_Pos     (20U)\r
-#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F12R2_FB21_Pos     (21U)\r
-#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F12R2_FB22_Pos     (22U)\r
-#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F12R2_FB23_Pos     (23U)\r
-#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F12R2_FB24_Pos     (24U)\r
-#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F12R2_FB25_Pos     (25U)\r
-#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F12R2_FB26_Pos     (26U)\r
-#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F12R2_FB27_Pos     (27U)\r
-#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F12R2_FB28_Pos     (28U)\r
-#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F12R2_FB29_Pos     (29U)\r
-#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F12R2_FB30_Pos     (30U)\r
-#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F12R2_FB31_Pos     (31U)\r
-#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/*******************  Bit definition for CAN_F13R2 register  ******************/\r
-#define CAN_F13R2_FB0_Pos      (0U)\r
-#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                    /*!< 0x00000001 */\r
-#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\r
-#define CAN_F13R2_FB1_Pos      (1U)\r
-#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                    /*!< 0x00000002 */\r
-#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\r
-#define CAN_F13R2_FB2_Pos      (2U)\r
-#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                    /*!< 0x00000004 */\r
-#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\r
-#define CAN_F13R2_FB3_Pos      (3U)\r
-#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                    /*!< 0x00000008 */\r
-#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\r
-#define CAN_F13R2_FB4_Pos      (4U)\r
-#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                    /*!< 0x00000010 */\r
-#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\r
-#define CAN_F13R2_FB5_Pos      (5U)\r
-#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                    /*!< 0x00000020 */\r
-#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\r
-#define CAN_F13R2_FB6_Pos      (6U)\r
-#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                    /*!< 0x00000040 */\r
-#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\r
-#define CAN_F13R2_FB7_Pos      (7U)\r
-#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                    /*!< 0x00000080 */\r
-#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\r
-#define CAN_F13R2_FB8_Pos      (8U)\r
-#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                    /*!< 0x00000100 */\r
-#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\r
-#define CAN_F13R2_FB9_Pos      (9U)\r
-#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                    /*!< 0x00000200 */\r
-#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\r
-#define CAN_F13R2_FB10_Pos     (10U)\r
-#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                   /*!< 0x00000400 */\r
-#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\r
-#define CAN_F13R2_FB11_Pos     (11U)\r
-#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                   /*!< 0x00000800 */\r
-#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\r
-#define CAN_F13R2_FB12_Pos     (12U)\r
-#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                   /*!< 0x00001000 */\r
-#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\r
-#define CAN_F13R2_FB13_Pos     (13U)\r
-#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                   /*!< 0x00002000 */\r
-#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\r
-#define CAN_F13R2_FB14_Pos     (14U)\r
-#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                   /*!< 0x00004000 */\r
-#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\r
-#define CAN_F13R2_FB15_Pos     (15U)\r
-#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                   /*!< 0x00008000 */\r
-#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\r
-#define CAN_F13R2_FB16_Pos     (16U)\r
-#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                   /*!< 0x00010000 */\r
-#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\r
-#define CAN_F13R2_FB17_Pos     (17U)\r
-#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                   /*!< 0x00020000 */\r
-#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\r
-#define CAN_F13R2_FB18_Pos     (18U)\r
-#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                   /*!< 0x00040000 */\r
-#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\r
-#define CAN_F13R2_FB19_Pos     (19U)\r
-#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                   /*!< 0x00080000 */\r
-#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\r
-#define CAN_F13R2_FB20_Pos     (20U)\r
-#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                   /*!< 0x00100000 */\r
-#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\r
-#define CAN_F13R2_FB21_Pos     (21U)\r
-#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                   /*!< 0x00200000 */\r
-#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\r
-#define CAN_F13R2_FB22_Pos     (22U)\r
-#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                   /*!< 0x00400000 */\r
-#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\r
-#define CAN_F13R2_FB23_Pos     (23U)\r
-#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                   /*!< 0x00800000 */\r
-#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\r
-#define CAN_F13R2_FB24_Pos     (24U)\r
-#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                   /*!< 0x01000000 */\r
-#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\r
-#define CAN_F13R2_FB25_Pos     (25U)\r
-#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                   /*!< 0x02000000 */\r
-#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\r
-#define CAN_F13R2_FB26_Pos     (26U)\r
-#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                   /*!< 0x04000000 */\r
-#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\r
-#define CAN_F13R2_FB27_Pos     (27U)\r
-#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                   /*!< 0x08000000 */\r
-#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\r
-#define CAN_F13R2_FB28_Pos     (28U)\r
-#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                   /*!< 0x10000000 */\r
-#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\r
-#define CAN_F13R2_FB29_Pos     (29U)\r
-#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                   /*!< 0x20000000 */\r
-#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\r
-#define CAN_F13R2_FB30_Pos     (30U)\r
-#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                   /*!< 0x40000000 */\r
-#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\r
-#define CAN_F13R2_FB31_Pos     (31U)\r
-#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                   /*!< 0x80000000 */\r
-#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                          CRC calculation unit                              */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for CRC_DR register  *********************/\r
-#define CRC_DR_DR_Pos            (0U)\r
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */\r
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */\r
-\r
-/*******************  Bit definition for CRC_IDR register  ********************/\r
-#define CRC_IDR_IDR_Pos          (0U)\r
-#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */\r
-#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */\r
-\r
-/********************  Bit definition for CRC_CR register  ********************/\r
-#define CRC_CR_RESET_Pos         (0U)\r
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */\r
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */\r
-#define CRC_CR_POLYSIZE_Pos      (3U)\r
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */\r
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */\r
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */\r
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */\r
-#define CRC_CR_REV_IN_Pos        (5U)\r
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */\r
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */\r
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */\r
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */\r
-#define CRC_CR_REV_OUT_Pos       (7U)\r
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */\r
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */\r
-\r
-/*******************  Bit definition for CRC_INIT register  *******************/\r
-#define CRC_INIT_INIT_Pos        (0U)\r
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */\r
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */\r
-\r
-/*******************  Bit definition for CRC_POL register  ********************/\r
-#define CRC_POL_POL_Pos          (0U)\r
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */\r
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                      Digital to Analog Converter                           */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*\r
- * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)\r
- */\r
-#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */\r
-\r
-/********************  Bit definition for DAC_CR register  ********************/\r
-#define DAC_CR_EN1_Pos              (0U)\r
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */\r
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\r
-#define DAC_CR_TEN1_Pos             (2U)\r
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000004 */\r
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\r
-\r
-#define DAC_CR_TSEL1_Pos            (3U)\r
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000038 */\r
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */\r
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */\r
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */\r
-\r
-#define DAC_CR_WAVE1_Pos            (6U)\r
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */\r
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */\r
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */\r
-\r
-#define DAC_CR_MAMP1_Pos            (8U)\r
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */\r
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */\r
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */\r
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */\r
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */\r
-\r
-#define DAC_CR_DMAEN1_Pos           (12U)\r
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */\r
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\r
-#define DAC_CR_DMAUDRIE1_Pos        (13U)\r
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */\r
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/\r
-#define DAC_CR_CEN1_Pos             (14U)\r
-#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */\r
-#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/\r
-\r
-#define DAC_CR_EN2_Pos              (16U)\r
-#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */\r
-#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\r
-#define DAC_CR_TEN2_Pos             (18U)\r
-#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00040000 */\r
-#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\r
-\r
-#define DAC_CR_TSEL2_Pos            (19U)\r
-#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                /*!< 0x00380000 */\r
-#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
-#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */\r
-#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */\r
-#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */\r
-\r
-#define DAC_CR_WAVE2_Pos            (22U)\r
-#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */\r
-#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */\r
-#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */\r
-\r
-#define DAC_CR_MAMP2_Pos            (24U)\r
-#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */\r
-#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */\r
-#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */\r
-#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */\r
-#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */\r
-\r
-#define DAC_CR_DMAEN2_Pos           (28U)\r
-#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */\r
-#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\r
-#define DAC_CR_DMAUDRIE2_Pos        (29U)\r
-#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */\r
-#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/\r
-#define DAC_CR_CEN2_Pos             (30U)\r
-#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */\r
-#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/\r
-\r
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\r
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */\r
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\r
-#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\r
-#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */\r
-#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\r
-\r
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\r
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */\r
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r
-\r
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\r
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r
-\r
-/******************  Bit definition for DAC_DHR8R1 register  ******************/\r
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\r
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */\r
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r
-\r
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r
-#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\r
-#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */\r
-#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r
-#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\r
-#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */\r
-#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/******************  Bit definition for DAC_DHR8R2 register  ******************/\r
-#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\r
-#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */\r
-#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/*****************  Bit definition for DAC_DHR12RD register  ******************/\r
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\r
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */\r
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r
-#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\r
-#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */\r
-#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/*****************  Bit definition for DAC_DHR12LD register  ******************/\r
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\r
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r
-#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\r
-#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */\r
-#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/******************  Bit definition for DAC_DHR8RD register  ******************/\r
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\r
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */\r
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r
-#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\r
-#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */\r
-#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/*******************  Bit definition for DAC_DOR1 register  *******************/\r
-#define DAC_DOR1_DACC1DOR_Pos       (0U)\r
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */\r
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\r
-\r
-/*******************  Bit definition for DAC_DOR2 register  *******************/\r
-#define DAC_DOR2_DACC2DOR_Pos       (0U)\r
-#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */\r
-#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\r
-\r
-/********************  Bit definition for DAC_SR register  ********************/\r
-#define DAC_SR_DMAUDR1_Pos          (13U)\r
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */\r
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\r
-#define DAC_SR_CAL_FLAG1_Pos        (14U)\r
-#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */\r
-#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */\r
-#define DAC_SR_BWST1_Pos            (15U)\r
-#define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */\r
-#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */\r
-\r
-#define DAC_SR_DMAUDR2_Pos          (29U)\r
-#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */\r
-#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\r
-#define DAC_SR_CAL_FLAG2_Pos        (30U)\r
-#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */\r
-#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */\r
-#define DAC_SR_BWST2_Pos            (31U)\r
-#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */\r
-#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */\r
-\r
-/*******************  Bit definition for DAC_CCR register  ********************/\r
-#define DAC_CCR_OTRIM1_Pos          (0U)\r
-#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */\r
-#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */\r
-#define DAC_CCR_OTRIM2_Pos          (16U)\r
-#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */\r
-#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */\r
-\r
-/*******************  Bit definition for DAC_MCR register  *******************/\r
-#define DAC_MCR_MODE1_Pos           (0U)\r
-#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */\r
-#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */\r
-#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */\r
-#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */\r
-#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */\r
-\r
-#define DAC_MCR_MODE2_Pos           (16U)\r
-#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */\r
-#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */\r
-#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */\r
-#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */\r
-#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */\r
-\r
-/******************  Bit definition for DAC_SHSR1 register  ******************/\r
-#define DAC_SHSR1_TSAMPLE1_Pos      (0U)\r
-#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */\r
-#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */\r
-\r
-/******************  Bit definition for DAC_SHSR2 register  ******************/\r
-#define DAC_SHSR2_TSAMPLE2_Pos      (0U)\r
-#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */\r
-#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */\r
-\r
-/******************  Bit definition for DAC_SHHR register  ******************/\r
-#define DAC_SHHR_THOLD1_Pos         (0U)\r
-#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */\r
-#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */\r
-#define DAC_SHHR_THOLD2_Pos         (16U)\r
-#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */\r
-#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */\r
-\r
-/******************  Bit definition for DAC_SHRR register  ******************/\r
-#define DAC_SHRR_TREFRESH1_Pos      (0U)\r
-#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */\r
-#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */\r
-#define DAC_SHRR_TREFRESH2_Pos      (16U)\r
-#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */\r
-#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                 Digital Filter for Sigma Delta Modulators                  */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-\r
-/****************   DFSDM channel configuration registers  ********************/\r
-\r
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\r
-#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\r
-#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */\r
-#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\r
-#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\r
-#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */\r
-#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\r
-#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\r
-#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */\r
-#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\r
-#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\r
-#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */\r
-#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\r
-#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x00008000 */\r
-#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x00004000 */\r
-#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\r
-#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */\r
-#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\r
-#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00002000 */\r
-#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00001000 */\r
-#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\r
-#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */\r
-#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\r
-#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\r
-#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */\r
-#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\r
-#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\r
-#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */\r
-#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\r
-#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\r
-#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */\r
-#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\r
-#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\r
-#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */\r
-#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\r
-#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x00000008 */\r
-#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x00000004 */\r
-#define DFSDM_CHCFGR1_SITP_Pos          (0U)\r
-#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */\r
-#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\r
-#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000002 */\r
-#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000001 */\r
-\r
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\r
-#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\r
-#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\r
-#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\r
-#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\r
-#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */\r
-#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\r
-\r
-/****************  Bit definition for DFSDM_CHAWSCDR register *****************/\r
-#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\r
-#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */\r
-#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\r
-#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00800000 */\r
-#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00400000 */\r
-#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\r
-#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */\r
-#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\r
-#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\r
-#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */\r
-#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\r
-#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\r
-#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */\r
-#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\r
-\r
-/****************  Bit definition for DFSDM_CHWDATR register *******************/\r
-#define DFSDM_CHWDATR_WDATA_Pos         (0U)\r
-#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */\r
-#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\r
-\r
-/****************  Bit definition for DFSDM_CHDATINR register *****************/\r
-#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\r
-#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\r
-#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\r
-#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\r
-#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\r
-#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\r
-\r
-/************************   DFSDM module registers  ****************************/\r
-\r
-/*****************  Bit definition for DFSDM_FLTCR1 register *******************/\r
-#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\r
-#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */\r
-#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\r
-#define DFSDM_FLTCR1_FAST_Pos           (29U)\r
-#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */\r
-#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\r
-#define DFSDM_FLTCR1_RCH_Pos            (24U)\r
-#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */\r
-#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\r
-#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\r
-#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */\r
-#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\r
-#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\r
-#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */\r
-#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\r
-#define DFSDM_FLTCR1_RCONT_Pos          (18U)\r
-#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */\r
-#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\r
-#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\r
-#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */\r
-#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\r
-#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\r
-#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */\r
-#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\r
-#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00004000 */\r
-#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00002000 */\r
-#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\r
-#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000700 */\r
-#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */\r
-#define DFSDM_FLTCR1_JEXTSEL_2          (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */\r
-#define DFSDM_FLTCR1_JEXTSEL_1          (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */\r
-#define DFSDM_FLTCR1_JEXTSEL_0          (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */\r
-#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\r
-#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */\r
-#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\r
-#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\r
-#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */\r
-#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\r
-#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\r
-#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */\r
-#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\r
-#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\r
-#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */\r
-#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\r
-#define DFSDM_FLTCR1_DFEN_Pos           (0U)\r
-#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */\r
-#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\r
-\r
-/*****************  Bit definition for DFSDM_FLTCR2 register *******************/\r
-#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\r
-#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */\r
-#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\r
-#define DFSDM_FLTCR2_EXCH_Pos           (8U)\r
-#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */\r
-#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\r
-#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\r
-#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */\r
-#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\r
-#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\r
-#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */\r
-#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\r
-#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\r
-#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */\r
-#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\r
-#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\r
-#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */\r
-#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\r
-#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\r
-#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */\r
-#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\r
-#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\r
-#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */\r
-#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\r
-#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\r
-#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */\r
-#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\r
-\r
-/*****************  Bit definition for DFSDM_FLTISR register *******************/\r
-#define DFSDM_FLTISR_SCDF_Pos           (24U)\r
-#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */\r
-#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\r
-#define DFSDM_FLTISR_CKABF_Pos          (16U)\r
-#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */\r
-#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\r
-#define DFSDM_FLTISR_RCIP_Pos           (14U)\r
-#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */\r
-#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\r
-#define DFSDM_FLTISR_JCIP_Pos           (13U)\r
-#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */\r
-#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\r
-#define DFSDM_FLTISR_AWDF_Pos           (4U)\r
-#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */\r
-#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\r
-#define DFSDM_FLTISR_ROVRF_Pos          (3U)\r
-#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */\r
-#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\r
-#define DFSDM_FLTISR_JOVRF_Pos          (2U)\r
-#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */\r
-#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\r
-#define DFSDM_FLTISR_REOCF_Pos          (1U)\r
-#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */\r
-#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\r
-#define DFSDM_FLTISR_JEOCF_Pos          (0U)\r
-#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */\r
-#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\r
-\r
-/*****************  Bit definition for DFSDM_FLTICR register *******************/\r
-#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)\r
-#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */\r
-#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCDF[7:0] Clear the short circuit detector flag */\r
-#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\r
-#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */\r
-#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\r
-#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\r
-#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */\r
-#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\r
-#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\r
-#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */\r
-#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\r
-\r
-/****************  Bit definition for DFSDM_FLTJCHGR register ******************/\r
-#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\r
-#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */\r
-#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\r
-\r
-/*****************  Bit definition for DFSDM_FLTFCR register *******************/\r
-#define DFSDM_FLTFCR_FORD_Pos           (29U)\r
-#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */\r
-#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\r
-#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x80000000 */\r
-#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x40000000 */\r
-#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x20000000 */\r
-#define DFSDM_FLTFCR_FOSR_Pos           (16U)\r
-#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */\r
-#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\r
-#define DFSDM_FLTFCR_IOSR_Pos           (0U)\r
-#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */\r
-#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\r
-\r
-/***************  Bit definition for DFSDM_FLTJDATAR register *****************/\r
-#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\r
-#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\r
-#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\r
-#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\r
-#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */\r
-#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\r
-\r
-/***************  Bit definition for DFSDM_FLTRDATAR register *****************/\r
-#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\r
-#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\r
-#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\r
-#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\r
-#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */\r
-#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\r
-#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\r
-#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */\r
-#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\r
-\r
-/***************  Bit definition for DFSDM_FLTAWHTR register ******************/\r
-#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\r
-#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\r
-#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\r
-#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\r
-#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */\r
-#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\r
-\r
-/***************  Bit definition for DFSDM_FLTAWLTR register ******************/\r
-#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\r
-#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\r
-#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */\r
-#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\r
-#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */\r
-#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\r
-\r
-/***************  Bit definition for DFSDM_FLTAWSR register *******************/\r
-#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\r
-#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */\r
-#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\r
-#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\r
-#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */\r
-#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\r
-\r
-/***************  Bit definition for DFSDM_FLTAWCFR register ******************/\r
-#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\r
-#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\r
-#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\r
-#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\r
-#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\r
-#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\r
-\r
-/***************  Bit definition for DFSDM_FLTEXMAX register ******************/\r
-#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\r
-#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\r
-#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\r
-#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\r
-#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */\r
-#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\r
-\r
-/***************  Bit definition for DFSDM_FLTEXMIN register ******************/\r
-#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\r
-#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\r
-#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\r
-#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\r
-#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */\r
-#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\r
-\r
-/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/\r
-#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\r
-#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\r
-#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                           DMA Controller (DMA)                             */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-\r
-/*******************  Bit definition for DMA_ISR register  ********************/\r
-#define DMA_ISR_GIF1_Pos       (0U)\r
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */\r
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */\r
-#define DMA_ISR_TCIF1_Pos      (1U)\r
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */\r
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */\r
-#define DMA_ISR_HTIF1_Pos      (2U)\r
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */\r
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */\r
-#define DMA_ISR_TEIF1_Pos      (3U)\r
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */\r
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */\r
-#define DMA_ISR_GIF2_Pos       (4U)\r
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */\r
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */\r
-#define DMA_ISR_TCIF2_Pos      (5U)\r
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */\r
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */\r
-#define DMA_ISR_HTIF2_Pos      (6U)\r
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */\r
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */\r
-#define DMA_ISR_TEIF2_Pos      (7U)\r
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */\r
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */\r
-#define DMA_ISR_GIF3_Pos       (8U)\r
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */\r
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */\r
-#define DMA_ISR_TCIF3_Pos      (9U)\r
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */\r
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */\r
-#define DMA_ISR_HTIF3_Pos      (10U)\r
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */\r
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */\r
-#define DMA_ISR_TEIF3_Pos      (11U)\r
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */\r
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */\r
-#define DMA_ISR_GIF4_Pos       (12U)\r
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */\r
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */\r
-#define DMA_ISR_TCIF4_Pos      (13U)\r
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */\r
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */\r
-#define DMA_ISR_HTIF4_Pos      (14U)\r
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */\r
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */\r
-#define DMA_ISR_TEIF4_Pos      (15U)\r
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */\r
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */\r
-#define DMA_ISR_GIF5_Pos       (16U)\r
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */\r
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */\r
-#define DMA_ISR_TCIF5_Pos      (17U)\r
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */\r
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */\r
-#define DMA_ISR_HTIF5_Pos      (18U)\r
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */\r
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */\r
-#define DMA_ISR_TEIF5_Pos      (19U)\r
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */\r
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */\r
-#define DMA_ISR_GIF6_Pos       (20U)\r
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */\r
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */\r
-#define DMA_ISR_TCIF6_Pos      (21U)\r
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */\r
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */\r
-#define DMA_ISR_HTIF6_Pos      (22U)\r
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */\r
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */\r
-#define DMA_ISR_TEIF6_Pos      (23U)\r
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */\r
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */\r
-#define DMA_ISR_GIF7_Pos       (24U)\r
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */\r
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */\r
-#define DMA_ISR_TCIF7_Pos      (25U)\r
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */\r
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */\r
-#define DMA_ISR_HTIF7_Pos      (26U)\r
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */\r
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */\r
-#define DMA_ISR_TEIF7_Pos      (27U)\r
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */\r
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */\r
-\r
-/*******************  Bit definition for DMA_IFCR register  *******************/\r
-#define DMA_IFCR_CGIF1_Pos     (0U)\r
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */\r
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */\r
-#define DMA_IFCR_CTCIF1_Pos    (1U)\r
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */\r
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF1_Pos    (2U)\r
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */\r
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF1_Pos    (3U)\r
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */\r
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */\r
-#define DMA_IFCR_CGIF2_Pos     (4U)\r
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */\r
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF2_Pos    (5U)\r
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */\r
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF2_Pos    (6U)\r
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */\r
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF2_Pos    (7U)\r
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */\r
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */\r
-#define DMA_IFCR_CGIF3_Pos     (8U)\r
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */\r
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF3_Pos    (9U)\r
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */\r
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF3_Pos    (10U)\r
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */\r
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF3_Pos    (11U)\r
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */\r
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */\r
-#define DMA_IFCR_CGIF4_Pos     (12U)\r
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */\r
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF4_Pos    (13U)\r
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */\r
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF4_Pos    (14U)\r
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */\r
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF4_Pos    (15U)\r
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */\r
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */\r
-#define DMA_IFCR_CGIF5_Pos     (16U)\r
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */\r
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF5_Pos    (17U)\r
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */\r
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF5_Pos    (18U)\r
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */\r
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF5_Pos    (19U)\r
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */\r
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */\r
-#define DMA_IFCR_CGIF6_Pos     (20U)\r
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */\r
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF6_Pos    (21U)\r
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */\r
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF6_Pos    (22U)\r
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */\r
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF6_Pos    (23U)\r
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */\r
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */\r
-#define DMA_IFCR_CGIF7_Pos     (24U)\r
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */\r
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF7_Pos    (25U)\r
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */\r
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF7_Pos    (26U)\r
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */\r
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF7_Pos    (27U)\r
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */\r
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */\r
-\r
-/*******************  Bit definition for DMA_CCR register  ********************/\r
-#define DMA_CCR_EN_Pos         (0U)\r
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */\r
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */\r
-#define DMA_CCR_TCIE_Pos       (1U)\r
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */\r
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */\r
-#define DMA_CCR_HTIE_Pos       (2U)\r
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */\r
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */\r
-#define DMA_CCR_TEIE_Pos       (3U)\r
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */\r
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */\r
-#define DMA_CCR_DIR_Pos        (4U)\r
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */\r
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */\r
-#define DMA_CCR_CIRC_Pos       (5U)\r
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */\r
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */\r
-#define DMA_CCR_PINC_Pos       (6U)\r
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */\r
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */\r
-#define DMA_CCR_MINC_Pos       (7U)\r
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */\r
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */\r
-\r
-#define DMA_CCR_PSIZE_Pos      (8U)\r
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */\r
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */\r
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */\r
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */\r
-\r
-#define DMA_CCR_MSIZE_Pos      (10U)\r
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */\r
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */\r
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */\r
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */\r
-\r
-#define DMA_CCR_PL_Pos         (12U)\r
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */\r
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/\r
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */\r
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */\r
-\r
-#define DMA_CCR_MEM2MEM_Pos    (14U)\r
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */\r
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */\r
-\r
-/******************  Bit definition for DMA_CNDTR register  *******************/\r
-#define DMA_CNDTR_NDT_Pos      (0U)\r
-#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */\r
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */\r
-\r
-/******************  Bit definition for DMA_CPAR register  ********************/\r
-#define DMA_CPAR_PA_Pos        (0U)\r
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */\r
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */\r
-\r
-/******************  Bit definition for DMA_CMAR register  ********************/\r
-#define DMA_CMAR_MA_Pos        (0U)\r
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */\r
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */\r
-\r
-\r
-/*******************  Bit definition for DMA_CSELR register  *******************/\r
-#define DMA_CSELR_C1S_Pos      (0U)\r
-#define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                    /*!< 0x0000000F */\r
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */\r
-#define DMA_CSELR_C2S_Pos      (4U)\r
-#define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                    /*!< 0x000000F0 */\r
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */\r
-#define DMA_CSELR_C3S_Pos      (8U)\r
-#define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                    /*!< 0x00000F00 */\r
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */\r
-#define DMA_CSELR_C4S_Pos      (12U)\r
-#define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                    /*!< 0x0000F000 */\r
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */\r
-#define DMA_CSELR_C5S_Pos      (16U)\r
-#define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                    /*!< 0x000F0000 */\r
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */\r
-#define DMA_CSELR_C6S_Pos      (20U)\r
-#define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                    /*!< 0x00F00000 */\r
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */\r
-#define DMA_CSELR_C7S_Pos      (24U)\r
-#define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                    /*!< 0x0F000000 */\r
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                    External Interrupt/Event Controller                     */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for EXTI_IMR1 register  ******************/\r
-#define EXTI_IMR1_IM0_Pos        (0U)\r
-#define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */\r
-#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */\r
-#define EXTI_IMR1_IM1_Pos        (1U)\r
-#define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */\r
-#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */\r
-#define EXTI_IMR1_IM2_Pos        (2U)\r
-#define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */\r
-#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */\r
-#define EXTI_IMR1_IM3_Pos        (3U)\r
-#define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */\r
-#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */\r
-#define EXTI_IMR1_IM4_Pos        (4U)\r
-#define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */\r
-#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */\r
-#define EXTI_IMR1_IM5_Pos        (5U)\r
-#define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */\r
-#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */\r
-#define EXTI_IMR1_IM6_Pos        (6U)\r
-#define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */\r
-#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */\r
-#define EXTI_IMR1_IM7_Pos        (7U)\r
-#define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */\r
-#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */\r
-#define EXTI_IMR1_IM8_Pos        (8U)\r
-#define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */\r
-#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */\r
-#define EXTI_IMR1_IM9_Pos        (9U)\r
-#define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */\r
-#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */\r
-#define EXTI_IMR1_IM10_Pos       (10U)\r
-#define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */\r
-#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */\r
-#define EXTI_IMR1_IM11_Pos       (11U)\r
-#define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */\r
-#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */\r
-#define EXTI_IMR1_IM12_Pos       (12U)\r
-#define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */\r
-#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */\r
-#define EXTI_IMR1_IM13_Pos       (13U)\r
-#define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */\r
-#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */\r
-#define EXTI_IMR1_IM14_Pos       (14U)\r
-#define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */\r
-#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */\r
-#define EXTI_IMR1_IM15_Pos       (15U)\r
-#define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */\r
-#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */\r
-#define EXTI_IMR1_IM16_Pos       (16U)\r
-#define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */\r
-#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */\r
-#define EXTI_IMR1_IM17_Pos       (17U)\r
-#define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */\r
-#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */\r
-#define EXTI_IMR1_IM18_Pos       (18U)\r
-#define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */\r
-#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */\r
-#define EXTI_IMR1_IM19_Pos       (19U)\r
-#define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */\r
-#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */\r
-#define EXTI_IMR1_IM20_Pos       (20U)\r
-#define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */\r
-#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */\r
-#define EXTI_IMR1_IM21_Pos       (21U)\r
-#define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */\r
-#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */\r
-#define EXTI_IMR1_IM22_Pos       (22U)\r
-#define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */\r
-#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */\r
-#define EXTI_IMR1_IM23_Pos       (23U)\r
-#define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */\r
-#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */\r
-#define EXTI_IMR1_IM24_Pos       (24U)\r
-#define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */\r
-#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */\r
-#define EXTI_IMR1_IM25_Pos       (25U)\r
-#define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */\r
-#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */\r
-#define EXTI_IMR1_IM26_Pos       (26U)\r
-#define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */\r
-#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */\r
-#define EXTI_IMR1_IM27_Pos       (27U)\r
-#define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */\r
-#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */\r
-#define EXTI_IMR1_IM28_Pos       (28U)\r
-#define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */\r
-#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */\r
-#define EXTI_IMR1_IM29_Pos       (29U)\r
-#define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */\r
-#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */\r
-#define EXTI_IMR1_IM30_Pos       (30U)\r
-#define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */\r
-#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */\r
-#define EXTI_IMR1_IM31_Pos       (31U)\r
-#define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */\r
-#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */\r
-#define EXTI_IMR1_IM_Pos         (0U)\r
-#define EXTI_IMR1_IM_Msk         (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0xFFFFFFFF */\r
-#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */\r
-\r
-/*******************  Bit definition for EXTI_EMR1 register  ******************/\r
-#define EXTI_EMR1_EM0_Pos        (0U)\r
-#define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */\r
-#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */\r
-#define EXTI_EMR1_EM1_Pos        (1U)\r
-#define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */\r
-#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */\r
-#define EXTI_EMR1_EM2_Pos        (2U)\r
-#define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */\r
-#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */\r
-#define EXTI_EMR1_EM3_Pos        (3U)\r
-#define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */\r
-#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */\r
-#define EXTI_EMR1_EM4_Pos        (4U)\r
-#define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */\r
-#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */\r
-#define EXTI_EMR1_EM5_Pos        (5U)\r
-#define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */\r
-#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */\r
-#define EXTI_EMR1_EM6_Pos        (6U)\r
-#define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */\r
-#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */\r
-#define EXTI_EMR1_EM7_Pos        (7U)\r
-#define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */\r
-#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */\r
-#define EXTI_EMR1_EM8_Pos        (8U)\r
-#define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */\r
-#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */\r
-#define EXTI_EMR1_EM9_Pos        (9U)\r
-#define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */\r
-#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */\r
-#define EXTI_EMR1_EM10_Pos       (10U)\r
-#define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */\r
-#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */\r
-#define EXTI_EMR1_EM11_Pos       (11U)\r
-#define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */\r
-#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */\r
-#define EXTI_EMR1_EM12_Pos       (12U)\r
-#define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */\r
-#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */\r
-#define EXTI_EMR1_EM13_Pos       (13U)\r
-#define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */\r
-#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */\r
-#define EXTI_EMR1_EM14_Pos       (14U)\r
-#define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */\r
-#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */\r
-#define EXTI_EMR1_EM15_Pos       (15U)\r
-#define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */\r
-#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */\r
-#define EXTI_EMR1_EM16_Pos       (16U)\r
-#define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */\r
-#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */\r
-#define EXTI_EMR1_EM17_Pos       (17U)\r
-#define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */\r
-#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */\r
-#define EXTI_EMR1_EM18_Pos       (18U)\r
-#define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */\r
-#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */\r
-#define EXTI_EMR1_EM19_Pos       (19U)\r
-#define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */\r
-#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */\r
-#define EXTI_EMR1_EM20_Pos       (20U)\r
-#define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */\r
-#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */\r
-#define EXTI_EMR1_EM21_Pos       (21U)\r
-#define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */\r
-#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */\r
-#define EXTI_EMR1_EM22_Pos       (22U)\r
-#define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */\r
-#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */\r
-#define EXTI_EMR1_EM23_Pos       (23U)\r
-#define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */\r
-#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */\r
-#define EXTI_EMR1_EM24_Pos       (24U)\r
-#define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */\r
-#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */\r
-#define EXTI_EMR1_EM25_Pos       (25U)\r
-#define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */\r
-#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */\r
-#define EXTI_EMR1_EM26_Pos       (26U)\r
-#define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */\r
-#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */\r
-#define EXTI_EMR1_EM27_Pos       (27U)\r
-#define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */\r
-#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */\r
-#define EXTI_EMR1_EM28_Pos       (28U)\r
-#define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */\r
-#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */\r
-#define EXTI_EMR1_EM29_Pos       (29U)\r
-#define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */\r
-#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */\r
-#define EXTI_EMR1_EM30_Pos       (30U)\r
-#define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */\r
-#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */\r
-#define EXTI_EMR1_EM31_Pos       (31U)\r
-#define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */\r
-#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */\r
-\r
-/******************  Bit definition for EXTI_RTSR1 register  ******************/\r
-#define EXTI_RTSR1_RT0_Pos       (0U)\r
-#define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */\r
-#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\r
-#define EXTI_RTSR1_RT1_Pos       (1U)\r
-#define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */\r
-#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\r
-#define EXTI_RTSR1_RT2_Pos       (2U)\r
-#define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */\r
-#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\r
-#define EXTI_RTSR1_RT3_Pos       (3U)\r
-#define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */\r
-#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\r
-#define EXTI_RTSR1_RT4_Pos       (4U)\r
-#define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */\r
-#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\r
-#define EXTI_RTSR1_RT5_Pos       (5U)\r
-#define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */\r
-#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\r
-#define EXTI_RTSR1_RT6_Pos       (6U)\r
-#define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */\r
-#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\r
-#define EXTI_RTSR1_RT7_Pos       (7U)\r
-#define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */\r
-#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\r
-#define EXTI_RTSR1_RT8_Pos       (8U)\r
-#define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */\r
-#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\r
-#define EXTI_RTSR1_RT9_Pos       (9U)\r
-#define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */\r
-#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\r
-#define EXTI_RTSR1_RT10_Pos      (10U)\r
-#define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */\r
-#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\r
-#define EXTI_RTSR1_RT11_Pos      (11U)\r
-#define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */\r
-#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\r
-#define EXTI_RTSR1_RT12_Pos      (12U)\r
-#define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */\r
-#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\r
-#define EXTI_RTSR1_RT13_Pos      (13U)\r
-#define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */\r
-#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\r
-#define EXTI_RTSR1_RT14_Pos      (14U)\r
-#define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */\r
-#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\r
-#define EXTI_RTSR1_RT15_Pos      (15U)\r
-#define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */\r
-#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\r
-#define EXTI_RTSR1_RT16_Pos      (16U)\r
-#define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */\r
-#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\r
-#define EXTI_RTSR1_RT18_Pos      (18U)\r
-#define EXTI_RTSR1_RT18_Msk      (0x1UL << EXTI_RTSR1_RT18_Pos)                /*!< 0x00040000 */\r
-#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\r
-#define EXTI_RTSR1_RT19_Pos      (19U)\r
-#define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */\r
-#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\r
-#define EXTI_RTSR1_RT20_Pos      (20U)\r
-#define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */\r
-#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\r
-#define EXTI_RTSR1_RT21_Pos      (21U)\r
-#define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */\r
-#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\r
-#define EXTI_RTSR1_RT22_Pos      (22U)\r
-#define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */\r
-#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\r
-\r
-/******************  Bit definition for EXTI_FTSR1 register  ******************/\r
-#define EXTI_FTSR1_FT0_Pos       (0U)\r
-#define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */\r
-#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\r
-#define EXTI_FTSR1_FT1_Pos       (1U)\r
-#define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */\r
-#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\r
-#define EXTI_FTSR1_FT2_Pos       (2U)\r
-#define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */\r
-#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\r
-#define EXTI_FTSR1_FT3_Pos       (3U)\r
-#define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */\r
-#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\r
-#define EXTI_FTSR1_FT4_Pos       (4U)\r
-#define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */\r
-#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\r
-#define EXTI_FTSR1_FT5_Pos       (5U)\r
-#define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */\r
-#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\r
-#define EXTI_FTSR1_FT6_Pos       (6U)\r
-#define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */\r
-#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\r
-#define EXTI_FTSR1_FT7_Pos       (7U)\r
-#define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */\r
-#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\r
-#define EXTI_FTSR1_FT8_Pos       (8U)\r
-#define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */\r
-#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\r
-#define EXTI_FTSR1_FT9_Pos       (9U)\r
-#define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */\r
-#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\r
-#define EXTI_FTSR1_FT10_Pos      (10U)\r
-#define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */\r
-#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\r
-#define EXTI_FTSR1_FT11_Pos      (11U)\r
-#define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */\r
-#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\r
-#define EXTI_FTSR1_FT12_Pos      (12U)\r
-#define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */\r
-#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\r
-#define EXTI_FTSR1_FT13_Pos      (13U)\r
-#define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */\r
-#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\r
-#define EXTI_FTSR1_FT14_Pos      (14U)\r
-#define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */\r
-#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\r
-#define EXTI_FTSR1_FT15_Pos      (15U)\r
-#define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */\r
-#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\r
-#define EXTI_FTSR1_FT16_Pos      (16U)\r
-#define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */\r
-#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\r
-#define EXTI_FTSR1_FT18_Pos      (18U)\r
-#define EXTI_FTSR1_FT18_Msk      (0x1UL << EXTI_FTSR1_FT18_Pos)                /*!< 0x00040000 */\r
-#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\r
-#define EXTI_FTSR1_FT19_Pos      (19U)\r
-#define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */\r
-#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\r
-#define EXTI_FTSR1_FT20_Pos      (20U)\r
-#define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */\r
-#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\r
-#define EXTI_FTSR1_FT21_Pos      (21U)\r
-#define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */\r
-#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\r
-#define EXTI_FTSR1_FT22_Pos      (22U)\r
-#define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */\r
-#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\r
-\r
-/******************  Bit definition for EXTI_SWIER1 register  *****************/\r
-#define EXTI_SWIER1_SWI0_Pos     (0U)\r
-#define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */\r
-#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */\r
-#define EXTI_SWIER1_SWI1_Pos     (1U)\r
-#define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */\r
-#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */\r
-#define EXTI_SWIER1_SWI2_Pos     (2U)\r
-#define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */\r
-#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */\r
-#define EXTI_SWIER1_SWI3_Pos     (3U)\r
-#define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */\r
-#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */\r
-#define EXTI_SWIER1_SWI4_Pos     (4U)\r
-#define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */\r
-#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */\r
-#define EXTI_SWIER1_SWI5_Pos     (5U)\r
-#define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */\r
-#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */\r
-#define EXTI_SWIER1_SWI6_Pos     (6U)\r
-#define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */\r
-#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */\r
-#define EXTI_SWIER1_SWI7_Pos     (7U)\r
-#define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */\r
-#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */\r
-#define EXTI_SWIER1_SWI8_Pos     (8U)\r
-#define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */\r
-#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */\r
-#define EXTI_SWIER1_SWI9_Pos     (9U)\r
-#define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */\r
-#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */\r
-#define EXTI_SWIER1_SWI10_Pos    (10U)\r
-#define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */\r
-#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */\r
-#define EXTI_SWIER1_SWI11_Pos    (11U)\r
-#define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */\r
-#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */\r
-#define EXTI_SWIER1_SWI12_Pos    (12U)\r
-#define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */\r
-#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */\r
-#define EXTI_SWIER1_SWI13_Pos    (13U)\r
-#define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */\r
-#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */\r
-#define EXTI_SWIER1_SWI14_Pos    (14U)\r
-#define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */\r
-#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */\r
-#define EXTI_SWIER1_SWI15_Pos    (15U)\r
-#define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */\r
-#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */\r
-#define EXTI_SWIER1_SWI16_Pos    (16U)\r
-#define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */\r
-#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */\r
-#define EXTI_SWIER1_SWI18_Pos    (18U)\r
-#define EXTI_SWIER1_SWI18_Msk    (0x1UL << EXTI_SWIER1_SWI18_Pos)              /*!< 0x00040000 */\r
-#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */\r
-#define EXTI_SWIER1_SWI19_Pos    (19U)\r
-#define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */\r
-#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */\r
-#define EXTI_SWIER1_SWI20_Pos    (20U)\r
-#define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */\r
-#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */\r
-#define EXTI_SWIER1_SWI21_Pos    (21U)\r
-#define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */\r
-#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */\r
-#define EXTI_SWIER1_SWI22_Pos    (22U)\r
-#define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */\r
-#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */\r
-\r
-/*******************  Bit definition for EXTI_PR1 register  *******************/\r
-#define EXTI_PR1_PIF0_Pos        (0U)\r
-#define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */\r
-#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */\r
-#define EXTI_PR1_PIF1_Pos        (1U)\r
-#define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */\r
-#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */\r
-#define EXTI_PR1_PIF2_Pos        (2U)\r
-#define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */\r
-#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */\r
-#define EXTI_PR1_PIF3_Pos        (3U)\r
-#define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */\r
-#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */\r
-#define EXTI_PR1_PIF4_Pos        (4U)\r
-#define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */\r
-#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */\r
-#define EXTI_PR1_PIF5_Pos        (5U)\r
-#define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */\r
-#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */\r
-#define EXTI_PR1_PIF6_Pos        (6U)\r
-#define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */\r
-#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */\r
-#define EXTI_PR1_PIF7_Pos        (7U)\r
-#define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */\r
-#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */\r
-#define EXTI_PR1_PIF8_Pos        (8U)\r
-#define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */\r
-#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */\r
-#define EXTI_PR1_PIF9_Pos        (9U)\r
-#define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */\r
-#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */\r
-#define EXTI_PR1_PIF10_Pos       (10U)\r
-#define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */\r
-#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */\r
-#define EXTI_PR1_PIF11_Pos       (11U)\r
-#define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */\r
-#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */\r
-#define EXTI_PR1_PIF12_Pos       (12U)\r
-#define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */\r
-#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */\r
-#define EXTI_PR1_PIF13_Pos       (13U)\r
-#define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */\r
-#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */\r
-#define EXTI_PR1_PIF14_Pos       (14U)\r
-#define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */\r
-#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */\r
-#define EXTI_PR1_PIF15_Pos       (15U)\r
-#define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */\r
-#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */\r
-#define EXTI_PR1_PIF16_Pos       (16U)\r
-#define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */\r
-#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */\r
-#define EXTI_PR1_PIF18_Pos       (18U)\r
-#define EXTI_PR1_PIF18_Msk       (0x1UL << EXTI_PR1_PIF18_Pos)                 /*!< 0x00040000 */\r
-#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */\r
-#define EXTI_PR1_PIF19_Pos       (19U)\r
-#define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */\r
-#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */\r
-#define EXTI_PR1_PIF20_Pos       (20U)\r
-#define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */\r
-#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */\r
-#define EXTI_PR1_PIF21_Pos       (21U)\r
-#define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */\r
-#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */\r
-#define EXTI_PR1_PIF22_Pos       (22U)\r
-#define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */\r
-#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */\r
-\r
-/*******************  Bit definition for EXTI_IMR2 register  ******************/\r
-#define EXTI_IMR2_IM32_Pos       (0U)\r
-#define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */\r
-#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */\r
-#define EXTI_IMR2_IM33_Pos       (1U)\r
-#define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */\r
-#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */\r
-#define EXTI_IMR2_IM34_Pos       (2U)\r
-#define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */\r
-#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */\r
-#define EXTI_IMR2_IM35_Pos       (3U)\r
-#define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */\r
-#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */\r
-#define EXTI_IMR2_IM36_Pos       (4U)\r
-#define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */\r
-#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */\r
-#define EXTI_IMR2_IM37_Pos       (5U)\r
-#define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */\r
-#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */\r
-#define EXTI_IMR2_IM38_Pos       (6U)\r
-#define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */\r
-#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */\r
-#define EXTI_IMR2_IM_Pos         (0U)\r
-#define EXTI_IMR2_IM_Msk         (0x7FUL << EXTI_IMR2_IM_Pos)                  /*!< 0x0000007F */\r
-#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */\r
-\r
-/*******************  Bit definition for EXTI_EMR2 register  ******************/\r
-#define EXTI_EMR2_EM32_Pos       (0U)\r
-#define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */\r
-#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */\r
-#define EXTI_EMR2_EM33_Pos       (1U)\r
-#define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */\r
-#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */\r
-#define EXTI_EMR2_EM34_Pos       (2U)\r
-#define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */\r
-#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */\r
-#define EXTI_EMR2_EM35_Pos       (3U)\r
-#define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */\r
-#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */\r
-#define EXTI_EMR2_EM36_Pos       (4U)\r
-#define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */\r
-#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */\r
-#define EXTI_EMR2_EM37_Pos       (5U)\r
-#define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */\r
-#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */\r
-#define EXTI_EMR2_EM38_Pos       (6U)\r
-#define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */\r
-#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */\r
-#define EXTI_EMR2_EM_Pos         (0U)\r
-#define EXTI_EMR2_EM_Msk         (0x7FUL << EXTI_EMR2_EM_Pos)                  /*!< 0x0000007F */\r
-#define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */\r
-\r
-/******************  Bit definition for EXTI_RTSR2 register  ******************/\r
-#define EXTI_RTSR2_RT35_Pos      (3U)\r
-#define EXTI_RTSR2_RT35_Msk      (0x1UL << EXTI_RTSR2_RT35_Pos)                /*!< 0x00000008 */\r
-#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */\r
-#define EXTI_RTSR2_RT36_Pos      (4U)\r
-#define EXTI_RTSR2_RT36_Msk      (0x1UL << EXTI_RTSR2_RT36_Pos)                /*!< 0x00000010 */\r
-#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */\r
-#define EXTI_RTSR2_RT37_Pos      (5U)\r
-#define EXTI_RTSR2_RT37_Msk      (0x1UL << EXTI_RTSR2_RT37_Pos)                /*!< 0x00000020 */\r
-#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */\r
-#define EXTI_RTSR2_RT38_Pos      (6U)\r
-#define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */\r
-#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */\r
-\r
-/******************  Bit definition for EXTI_FTSR2 register  ******************/\r
-#define EXTI_FTSR2_FT35_Pos      (3U)\r
-#define EXTI_FTSR2_FT35_Msk      (0x1UL << EXTI_FTSR2_FT35_Pos)                /*!< 0x00000008 */\r
-#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */\r
-#define EXTI_FTSR2_FT36_Pos      (4U)\r
-#define EXTI_FTSR2_FT36_Msk      (0x1UL << EXTI_FTSR2_FT36_Pos)                /*!< 0x00000010 */\r
-#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */\r
-#define EXTI_FTSR2_FT37_Pos      (5U)\r
-#define EXTI_FTSR2_FT37_Msk      (0x1UL << EXTI_FTSR2_FT37_Pos)                /*!< 0x00000020 */\r
-#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */\r
-#define EXTI_FTSR2_FT38_Pos      (6U)\r
-#define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */\r
-#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */\r
-\r
-/******************  Bit definition for EXTI_SWIER2 register  *****************/\r
-#define EXTI_SWIER2_SWI35_Pos    (3U)\r
-#define EXTI_SWIER2_SWI35_Msk    (0x1UL << EXTI_SWIER2_SWI35_Pos)              /*!< 0x00000008 */\r
-#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */\r
-#define EXTI_SWIER2_SWI36_Pos    (4U)\r
-#define EXTI_SWIER2_SWI36_Msk    (0x1UL << EXTI_SWIER2_SWI36_Pos)              /*!< 0x00000010 */\r
-#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */\r
-#define EXTI_SWIER2_SWI37_Pos    (5U)\r
-#define EXTI_SWIER2_SWI37_Msk    (0x1UL << EXTI_SWIER2_SWI37_Pos)              /*!< 0x00000020 */\r
-#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */\r
-#define EXTI_SWIER2_SWI38_Pos    (6U)\r
-#define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */\r
-#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */\r
-\r
-/*******************  Bit definition for EXTI_PR2 register  *******************/\r
-#define EXTI_PR2_PIF35_Pos       (3U)\r
-#define EXTI_PR2_PIF35_Msk       (0x1UL << EXTI_PR2_PIF35_Pos)                 /*!< 0x00000008 */\r
-#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */\r
-#define EXTI_PR2_PIF36_Pos       (4U)\r
-#define EXTI_PR2_PIF36_Msk       (0x1UL << EXTI_PR2_PIF36_Pos)                 /*!< 0x00000010 */\r
-#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */\r
-#define EXTI_PR2_PIF37_Pos       (5U)\r
-#define EXTI_PR2_PIF37_Msk       (0x1UL << EXTI_PR2_PIF37_Pos)                 /*!< 0x00000020 */\r
-#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */\r
-#define EXTI_PR2_PIF38_Pos       (6U)\r
-#define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */\r
-#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */\r
-\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                    FLASH                                   */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bits definition for FLASH_ACR register  *****************/\r
-#define FLASH_ACR_LATENCY_Pos             (0U)\r
-#define FLASH_ACR_LATENCY_Msk             (0x7UL << FLASH_ACR_LATENCY_Pos)     /*!< 0x00000007 */\r
-#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk\r
-#define FLASH_ACR_LATENCY_0WS             (0x00000000UL)\r
-#define FLASH_ACR_LATENCY_1WS             (0x00000001UL)\r
-#define FLASH_ACR_LATENCY_2WS             (0x00000002UL)\r
-#define FLASH_ACR_LATENCY_3WS             (0x00000003UL)\r
-#define FLASH_ACR_LATENCY_4WS             (0x00000004UL)\r
-#define FLASH_ACR_PRFTEN_Pos              (8U)\r
-#define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */\r
-#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk\r
-#define FLASH_ACR_ICEN_Pos                (9U)\r
-#define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */\r
-#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk\r
-#define FLASH_ACR_DCEN_Pos                (10U)\r
-#define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */\r
-#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk\r
-#define FLASH_ACR_ICRST_Pos               (11U)\r
-#define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */\r
-#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk\r
-#define FLASH_ACR_DCRST_Pos               (12U)\r
-#define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */\r
-#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk\r
-#define FLASH_ACR_RUN_PD_Pos              (13U)\r
-#define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */\r
-#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */\r
-#define FLASH_ACR_SLEEP_PD_Pos            (14U)\r
-#define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */\r
-#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */\r
-\r
-/*******************  Bits definition for FLASH_SR register  ******************/\r
-#define FLASH_SR_EOP_Pos                  (0U)\r
-#define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */\r
-#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk\r
-#define FLASH_SR_OPERR_Pos                (1U)\r
-#define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */\r
-#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk\r
-#define FLASH_SR_PROGERR_Pos              (3U)\r
-#define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */\r
-#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk\r
-#define FLASH_SR_WRPERR_Pos               (4U)\r
-#define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */\r
-#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk\r
-#define FLASH_SR_PGAERR_Pos               (5U)\r
-#define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */\r
-#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk\r
-#define FLASH_SR_SIZERR_Pos               (6U)\r
-#define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */\r
-#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk\r
-#define FLASH_SR_PGSERR_Pos               (7U)\r
-#define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */\r
-#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk\r
-#define FLASH_SR_MISERR_Pos               (8U)\r
-#define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */\r
-#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk\r
-#define FLASH_SR_FASTERR_Pos              (9U)\r
-#define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */\r
-#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk\r
-#define FLASH_SR_RDERR_Pos                (14U)\r
-#define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */\r
-#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk\r
-#define FLASH_SR_OPTVERR_Pos              (15U)\r
-#define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */\r
-#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk\r
-#define FLASH_SR_BSY_Pos                  (16U)\r
-#define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */\r
-#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk\r
-\r
-/*******************  Bits definition for FLASH_CR register  ******************/\r
-#define FLASH_CR_PG_Pos                   (0U)\r
-#define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */\r
-#define FLASH_CR_PG                       FLASH_CR_PG_Msk\r
-#define FLASH_CR_PER_Pos                  (1U)\r
-#define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */\r
-#define FLASH_CR_PER                      FLASH_CR_PER_Msk\r
-#define FLASH_CR_MER1_Pos                 (2U)\r
-#define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */\r
-#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk\r
-#define FLASH_CR_PNB_Pos                  (3U)\r
-#define FLASH_CR_PNB_Msk                  (0xFFUL << FLASH_CR_PNB_Pos)         /*!< 0x000007F8 */\r
-#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk\r
-#define FLASH_CR_BKER_Pos                 (11U)\r
-#define FLASH_CR_BKER_Msk                 (0x1UL << FLASH_CR_BKER_Pos)         /*!< 0x00000800 */\r
-#define FLASH_CR_BKER                     FLASH_CR_BKER_Msk\r
-#define FLASH_CR_MER2_Pos                 (15U)\r
-#define FLASH_CR_MER2_Msk                 (0x1UL << FLASH_CR_MER2_Pos)         /*!< 0x00008000 */\r
-#define FLASH_CR_MER2                     FLASH_CR_MER2_Msk\r
-#define FLASH_CR_STRT_Pos                 (16U)\r
-#define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */\r
-#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk\r
-#define FLASH_CR_OPTSTRT_Pos              (17U)\r
-#define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */\r
-#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk\r
-#define FLASH_CR_FSTPG_Pos                (18U)\r
-#define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */\r
-#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk\r
-#define FLASH_CR_EOPIE_Pos                (24U)\r
-#define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */\r
-#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk\r
-#define FLASH_CR_ERRIE_Pos                (25U)\r
-#define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */\r
-#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk\r
-#define FLASH_CR_RDERRIE_Pos              (26U)\r
-#define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */\r
-#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk\r
-#define FLASH_CR_OBL_LAUNCH_Pos           (27U)\r
-#define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */\r
-#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk\r
-#define FLASH_CR_OPTLOCK_Pos              (30U)\r
-#define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */\r
-#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk\r
-#define FLASH_CR_LOCK_Pos                 (31U)\r
-#define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */\r
-#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk\r
-\r
-/*******************  Bits definition for FLASH_ECCR register  ***************/\r
-#define FLASH_ECCR_ADDR_ECC_Pos           (0U)\r
-#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */\r
-#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk\r
-#define FLASH_ECCR_BK_ECC_Pos             (19U)\r
-#define FLASH_ECCR_BK_ECC_Msk             (0x1UL << FLASH_ECCR_BK_ECC_Pos)     /*!< 0x00080000 */\r
-#define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk\r
-#define FLASH_ECCR_SYSF_ECC_Pos           (20U)\r
-#define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00100000 */\r
-#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk\r
-#define FLASH_ECCR_ECCIE_Pos              (24U)\r
-#define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */\r
-#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk\r
-#define FLASH_ECCR_ECCC_Pos               (30U)\r
-#define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */\r
-#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk\r
-#define FLASH_ECCR_ECCD_Pos               (31U)\r
-#define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */\r
-#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk\r
-\r
-/*******************  Bits definition for FLASH_OPTR register  ***************/\r
-#define FLASH_OPTR_RDP_Pos                (0U)\r
-#define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */\r
-#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk\r
-#define FLASH_OPTR_BOR_LEV_Pos            (8U)\r
-#define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */\r
-#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk\r
-#define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */\r
-#define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */\r
-#define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */\r
-#define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */\r
-#define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */\r
-#define FLASH_OPTR_nRST_STOP_Pos          (12U)\r
-#define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */\r
-#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk\r
-#define FLASH_OPTR_nRST_STDBY_Pos         (13U)\r
-#define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */\r
-#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk\r
-#define FLASH_OPTR_nRST_SHDW_Pos          (14U)\r
-#define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */\r
-#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk\r
-#define FLASH_OPTR_IWDG_SW_Pos            (16U)\r
-#define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */\r
-#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk\r
-#define FLASH_OPTR_IWDG_STOP_Pos          (17U)\r
-#define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */\r
-#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk\r
-#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)\r
-#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */\r
-#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk\r
-#define FLASH_OPTR_WWDG_SW_Pos            (19U)\r
-#define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */\r
-#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk\r
-#define FLASH_OPTR_BFB2_Pos               (20U)\r
-#define FLASH_OPTR_BFB2_Msk               (0x1UL << FLASH_OPTR_BFB2_Pos)       /*!< 0x00100000 */\r
-#define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk\r
-#define FLASH_OPTR_DUALBANK_Pos           (21U)\r
-#define FLASH_OPTR_DUALBANK_Msk           (0x1UL << FLASH_OPTR_DUALBANK_Pos)   /*!< 0x00200000 */\r
-#define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk\r
-#define FLASH_OPTR_nBOOT1_Pos             (23U)\r
-#define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */\r
-#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk\r
-#define FLASH_OPTR_SRAM2_PE_Pos           (24U)\r
-#define FLASH_OPTR_SRAM2_PE_Msk           (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)   /*!< 0x01000000 */\r
-#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk\r
-#define FLASH_OPTR_SRAM2_RST_Pos          (25U)\r
-#define FLASH_OPTR_SRAM2_RST_Msk          (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)  /*!< 0x02000000 */\r
-#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk\r
-\r
-/******************  Bits definition for FLASH_PCROP1SR register  **********/\r
-#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)\r
-#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */\r
-#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk\r
-\r
-/******************  Bits definition for FLASH_PCROP1ER register  ***********/\r
-#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)\r
-#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */\r
-#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk\r
-#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)\r
-#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */\r
-#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk\r
-\r
-/******************  Bits definition for FLASH_WRP1AR register  ***************/\r
-#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)\r
-#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */\r
-#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk\r
-#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)\r
-#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos)  /*!< 0x00FF0000 */\r
-#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk\r
-\r
-/******************  Bits definition for FLASH_WRPB1R register  ***************/\r
-#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)\r
-#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */\r
-#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk\r
-#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)\r
-#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos)  /*!< 0x00FF0000 */\r
-#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk\r
-\r
-/******************  Bits definition for FLASH_PCROP2SR register  **********/\r
-#define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)\r
-#define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */\r
-#define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk\r
-\r
-/******************  Bits definition for FLASH_PCROP2ER register  ***********/\r
-#define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)\r
-#define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFUL << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */\r
-#define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk\r
-\r
-/******************  Bits definition for FLASH_WRP2AR register  ***************/\r
-#define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)\r
-#define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFUL << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */\r
-#define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk\r
-#define FLASH_WRP2AR_WRP2A_END_Pos        (16U)\r
-#define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFUL << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */\r
-#define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk\r
-\r
-/******************  Bits definition for FLASH_WRP2BR register  ***************/\r
-#define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)\r
-#define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFUL << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */\r
-#define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk\r
-#define FLASH_WRP2BR_WRP2B_END_Pos        (16U)\r
-#define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFUL << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */\r
-#define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk\r
-\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                          Flexible Memory Controller                        */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/******************  Bit definition for FMC_BCR1 register  *******************/\r
-#define FMC_BCR1_CCLKEN_Pos        (20U)\r
-#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\r
-#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */\r
-\r
-/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/\r
-#define FMC_BCRx_MBKEN_Pos         (0U)\r
-#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */\r
-#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r
-#define FMC_BCRx_MUXEN_Pos         (1U)\r
-#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */\r
-#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r
-\r
-#define FMC_BCRx_MTYP_Pos          (2U)\r
-#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */\r
-#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r
-#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */\r
-#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */\r
-\r
-#define FMC_BCRx_MWID_Pos          (4U)\r
-#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */\r
-#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */\r
-#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */\r
-\r
-#define FMC_BCRx_FACCEN_Pos        (6U)\r
-#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */\r
-#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */\r
-#define FMC_BCRx_BURSTEN_Pos       (8U)\r
-#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */\r
-#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */\r
-#define FMC_BCRx_WAITPOL_Pos       (9U)\r
-#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */\r
-#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r
-#define FMC_BCRx_WAITCFG_Pos       (11U)\r
-#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */\r
-#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */\r
-#define FMC_BCRx_WREN_Pos          (12U)\r
-#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */\r
-#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */\r
-#define FMC_BCRx_WAITEN_Pos        (13U)\r
-#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */\r
-#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */\r
-#define FMC_BCRx_EXTMOD_Pos        (14U)\r
-#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */\r
-#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */\r
-#define FMC_BCRx_ASYNCWAIT_Pos     (15U)\r
-#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */\r
-#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r
-\r
-#define FMC_BCRx_CPSIZE_Pos        (16U)\r
-#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */\r
-#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */\r
-#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */\r
-#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */\r
-#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */\r
-\r
-#define FMC_BCRx_CBURSTRW_Pos      (19U)\r
-#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */\r
-#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */\r
-\r
-/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/\r
-#define FMC_BTRx_ADDSET_Pos        (0U)\r
-#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */\r
-#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */\r
-#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */\r
-#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */\r
-#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */\r
-\r
-#define FMC_BTRx_ADDHLD_Pos        (4U)\r
-#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */\r
-#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\r
-#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */\r
-#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */\r
-#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */\r
-#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */\r
-\r
-#define FMC_BTRx_DATAST_Pos        (8U)\r
-#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */\r
-#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */\r
-#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */\r
-#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */\r
-#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */\r
-#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */\r
-#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */\r
-#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */\r
-#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */\r
-\r
-#define FMC_BTRx_BUSTURN_Pos       (16U)\r
-#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */\r
-#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */\r
-#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */\r
-#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */\r
-#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */\r
-\r
-#define FMC_BTRx_CLKDIV_Pos        (20U)\r
-#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */\r
-#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */\r
-#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */\r
-#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */\r
-#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */\r
-\r
-#define FMC_BTRx_DATLAT_Pos        (24U)\r
-#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */\r
-#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */\r
-#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */\r
-#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */\r
-#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */\r
-#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */\r
-\r
-#define FMC_BTRx_ACCMOD_Pos        (28U)\r
-#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */\r
-#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */\r
-#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */\r
-\r
-/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/\r
-#define FMC_BWTRx_ADDSET_Pos       (0U)\r
-#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */\r
-#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */\r
-#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */\r
-#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */\r
-#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */\r
-\r
-#define FMC_BWTRx_ADDHLD_Pos       (4U)\r
-#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */\r
-#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */\r
-#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */\r
-#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */\r
-#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */\r
-\r
-#define FMC_BWTRx_DATAST_Pos       (8U)\r
-#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */\r
-#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */\r
-#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */\r
-#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */\r
-#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */\r
-#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */\r
-#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */\r
-#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */\r
-#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */\r
-\r
-#define FMC_BWTRx_BUSTURN_Pos      (16U)\r
-#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */\r
-#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */\r
-#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */\r
-#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */\r
-#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */\r
-\r
-#define FMC_BWTRx_ACCMOD_Pos       (28U)\r
-#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */\r
-#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */\r
-#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */\r
-\r
-/******************  Bit definition for FMC_PCR register  ********************/\r
-#define FMC_PCR_PWAITEN_Pos        (1U)\r
-#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */\r
-#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */\r
-#define FMC_PCR_PBKEN_Pos          (2U)\r
-#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */\r
-#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */\r
-#define FMC_PCR_PTYP_Pos           (3U)\r
-#define FMC_PCR_PTYP_Msk           (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */\r
-#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */\r
-\r
-#define FMC_PCR_PWID_Pos           (4U)\r
-#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */\r
-#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */\r
-#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */\r
-\r
-#define FMC_PCR_ECCEN_Pos          (6U)\r
-#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */\r
-#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */\r
-\r
-#define FMC_PCR_TCLR_Pos           (9U)\r
-#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */\r
-#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */\r
-#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */\r
-#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */\r
-#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */\r
-#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */\r
-\r
-#define FMC_PCR_TAR_Pos            (13U)\r
-#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */\r
-#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */\r
-#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */\r
-#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */\r
-#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */\r
-#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */\r
-\r
-#define FMC_PCR_ECCPS_Pos          (17U)\r
-#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */\r
-#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */\r
-#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */\r
-#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */\r
-#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */\r
-\r
-/*******************  Bit definition for FMC_SR register  ********************/\r
-#define FMC_SR_IRS_Pos             (0U)\r
-#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */\r
-#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */\r
-#define FMC_SR_ILS_Pos             (1U)\r
-#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */\r
-#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */\r
-#define FMC_SR_IFS_Pos             (2U)\r
-#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */\r
-#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */\r
-#define FMC_SR_IREN_Pos            (3U)\r
-#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */\r
-#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */\r
-#define FMC_SR_ILEN_Pos            (4U)\r
-#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */\r
-#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */\r
-#define FMC_SR_IFEN_Pos            (5U)\r
-#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */\r
-#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FMC_SR_FEMPT_Pos           (6U)\r
-#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */\r
-#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */\r
-\r
-/******************  Bit definition for FMC_PMEM register  ******************/\r
-#define FMC_PMEM_MEMSET_Pos        (0U)\r
-#define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */\r
-#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */\r
-#define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */\r
-#define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */\r
-#define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */\r
-#define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */\r
-#define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */\r
-#define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */\r
-#define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */\r
-#define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */\r
-\r
-#define FMC_PMEM_MEMWAIT_Pos       (8U)\r
-#define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */\r
-#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */\r
-#define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */\r
-#define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */\r
-#define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */\r
-#define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */\r
-#define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */\r
-#define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */\r
-#define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */\r
-#define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */\r
-\r
-#define FMC_PMEM_MEMHOLD_Pos       (16U)\r
-#define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */\r
-#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */\r
-#define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */\r
-#define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */\r
-#define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */\r
-#define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */\r
-#define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */\r
-#define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */\r
-#define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */\r
-#define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */\r
-\r
-#define FMC_PMEM_MEMHIZ_Pos        (24U)\r
-#define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */\r
-#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */\r
-#define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */\r
-#define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */\r
-#define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */\r
-#define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */\r
-#define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */\r
-#define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */\r
-#define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */\r
-#define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */\r
-\r
-/******************  Bit definition for FMC_PATT register  *******************/\r
-#define FMC_PATT_ATTSET_Pos        (0U)\r
-#define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */\r
-#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */\r
-#define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */\r
-#define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */\r
-#define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */\r
-#define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */\r
-#define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */\r
-#define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */\r
-#define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */\r
-#define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */\r
-\r
-#define FMC_PATT_ATTWAIT_Pos       (8U)\r
-#define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */\r
-#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */\r
-#define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */\r
-#define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */\r
-#define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */\r
-#define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */\r
-#define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */\r
-#define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */\r
-#define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */\r
-#define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */\r
-\r
-#define FMC_PATT_ATTHOLD_Pos       (16U)\r
-#define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */\r
-#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */\r
-#define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */\r
-#define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */\r
-#define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */\r
-#define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */\r
-#define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */\r
-#define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */\r
-#define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */\r
-#define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */\r
-\r
-#define FMC_PATT_ATTHIZ_Pos        (24U)\r
-#define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */\r
-#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */\r
-#define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */\r
-#define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */\r
-#define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */\r
-#define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */\r
-#define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */\r
-#define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */\r
-#define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */\r
-#define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */\r
-\r
-/******************  Bit definition for FMC_ECCR register  *******************/\r
-#define FMC_ECCR_ECC_Pos           (0U)\r
-#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)          /*!< 0xFFFFFFFF */\r
-#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                       General Purpose IOs (GPIO)                           */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/******************  Bits definition for GPIO_MODER register  *****************/\r
-#define GPIO_MODER_MODE0_Pos           (0U)\r
-#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */\r
-#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk\r
-#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */\r
-#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */\r
-#define GPIO_MODER_MODE1_Pos           (2U)\r
-#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */\r
-#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk\r
-#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */\r
-#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */\r
-#define GPIO_MODER_MODE2_Pos           (4U)\r
-#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */\r
-#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk\r
-#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */\r
-#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */\r
-#define GPIO_MODER_MODE3_Pos           (6U)\r
-#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */\r
-#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk\r
-#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */\r
-#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */\r
-#define GPIO_MODER_MODE4_Pos           (8U)\r
-#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */\r
-#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk\r
-#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */\r
-#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */\r
-#define GPIO_MODER_MODE5_Pos           (10U)\r
-#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */\r
-#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk\r
-#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */\r
-#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */\r
-#define GPIO_MODER_MODE6_Pos           (12U)\r
-#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */\r
-#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk\r
-#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */\r
-#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */\r
-#define GPIO_MODER_MODE7_Pos           (14U)\r
-#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */\r
-#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk\r
-#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */\r
-#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */\r
-#define GPIO_MODER_MODE8_Pos           (16U)\r
-#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */\r
-#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk\r
-#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */\r
-#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */\r
-#define GPIO_MODER_MODE9_Pos           (18U)\r
-#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */\r
-#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk\r
-#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */\r
-#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */\r
-#define GPIO_MODER_MODE10_Pos          (20U)\r
-#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */\r
-#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk\r
-#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */\r
-#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */\r
-#define GPIO_MODER_MODE11_Pos          (22U)\r
-#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */\r
-#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk\r
-#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */\r
-#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */\r
-#define GPIO_MODER_MODE12_Pos          (24U)\r
-#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */\r
-#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk\r
-#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */\r
-#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */\r
-#define GPIO_MODER_MODE13_Pos          (26U)\r
-#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */\r
-#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk\r
-#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */\r
-#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */\r
-#define GPIO_MODER_MODE14_Pos          (28U)\r
-#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */\r
-#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk\r
-#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */\r
-#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */\r
-#define GPIO_MODER_MODE15_Pos          (30U)\r
-#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */\r
-#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk\r
-#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */\r
-#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */\r
-\r
-/* Legacy defines */\r
-#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0\r
-#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0\r
-#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1\r
-#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1\r
-#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0\r
-#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1\r
-#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2\r
-#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0\r
-#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1\r
-#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3\r
-#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0\r
-#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1\r
-#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4\r
-#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0\r
-#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1\r
-#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5\r
-#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0\r
-#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1\r
-#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6\r
-#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0\r
-#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1\r
-#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7\r
-#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0\r
-#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1\r
-#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8\r
-#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0\r
-#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1\r
-#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9\r
-#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0\r
-#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1\r
-#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10\r
-#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0\r
-#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1\r
-#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11\r
-#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0\r
-#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1\r
-#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12\r
-#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0\r
-#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1\r
-#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13\r
-#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0\r
-#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1\r
-#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14\r
-#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0\r
-#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1\r
-#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15\r
-#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0\r
-#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1\r
-\r
-/******************  Bits definition for GPIO_OTYPER register  ****************/\r
-#define GPIO_OTYPER_OT0_Pos            (0U)\r
-#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */\r
-#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk\r
-#define GPIO_OTYPER_OT1_Pos            (1U)\r
-#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */\r
-#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk\r
-#define GPIO_OTYPER_OT2_Pos            (2U)\r
-#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */\r
-#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk\r
-#define GPIO_OTYPER_OT3_Pos            (3U)\r
-#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */\r
-#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk\r
-#define GPIO_OTYPER_OT4_Pos            (4U)\r
-#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */\r
-#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk\r
-#define GPIO_OTYPER_OT5_Pos            (5U)\r
-#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */\r
-#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk\r
-#define GPIO_OTYPER_OT6_Pos            (6U)\r
-#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */\r
-#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk\r
-#define GPIO_OTYPER_OT7_Pos            (7U)\r
-#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */\r
-#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk\r
-#define GPIO_OTYPER_OT8_Pos            (8U)\r
-#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */\r
-#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk\r
-#define GPIO_OTYPER_OT9_Pos            (9U)\r
-#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */\r
-#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk\r
-#define GPIO_OTYPER_OT10_Pos           (10U)\r
-#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */\r
-#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk\r
-#define GPIO_OTYPER_OT11_Pos           (11U)\r
-#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */\r
-#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk\r
-#define GPIO_OTYPER_OT12_Pos           (12U)\r
-#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */\r
-#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk\r
-#define GPIO_OTYPER_OT13_Pos           (13U)\r
-#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */\r
-#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk\r
-#define GPIO_OTYPER_OT14_Pos           (14U)\r
-#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */\r
-#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk\r
-#define GPIO_OTYPER_OT15_Pos           (15U)\r
-#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */\r
-#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk\r
-\r
-/* Legacy defines */\r
-#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0\r
-#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1\r
-#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2\r
-#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3\r
-#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4\r
-#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5\r
-#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6\r
-#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7\r
-#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8\r
-#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9\r
-#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10\r
-#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11\r
-#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12\r
-#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13\r
-#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14\r
-#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15\r
-\r
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/\r
-#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)\r
-#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */\r
-#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk\r
-#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */\r
-#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */\r
-#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)\r
-#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */\r
-#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk\r
-#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */\r
-#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */\r
-#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)\r
-#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */\r
-#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk\r
-#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */\r
-#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */\r
-#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)\r
-#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */\r
-#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk\r
-#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */\r
-#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */\r
-#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)\r
-#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */\r
-#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk\r
-#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */\r
-#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */\r
-#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)\r
-#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */\r
-#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk\r
-#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */\r
-#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */\r
-#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)\r
-#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */\r
-#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk\r
-#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */\r
-#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */\r
-#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)\r
-#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */\r
-#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk\r
-#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */\r
-#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */\r
-#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)\r
-#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */\r
-#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk\r
-#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */\r
-#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */\r
-#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)\r
-#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */\r
-#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk\r
-#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */\r
-#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */\r
-#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)\r
-#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */\r
-#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk\r
-#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */\r
-#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */\r
-#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)\r
-#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */\r
-#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk\r
-#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */\r
-#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */\r
-#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)\r
-#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */\r
-#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk\r
-#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */\r
-#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */\r
-#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)\r
-#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */\r
-#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk\r
-#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */\r
-#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */\r
-#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)\r
-#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */\r
-#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk\r
-#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */\r
-#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */\r
-#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)\r
-#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */\r
-#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk\r
-#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */\r
-#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */\r
-\r
-/* Legacy defines */\r
-#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0\r
-#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0\r
-#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1\r
-#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1\r
-#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0\r
-#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1\r
-#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2\r
-#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0\r
-#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1\r
-#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3\r
-#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0\r
-#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1\r
-#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4\r
-#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0\r
-#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1\r
-#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5\r
-#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0\r
-#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1\r
-#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6\r
-#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0\r
-#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1\r
-#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7\r
-#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0\r
-#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1\r
-#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8\r
-#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0\r
-#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1\r
-#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9\r
-#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0\r
-#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1\r
-#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10\r
-#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0\r
-#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1\r
-#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11\r
-#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0\r
-#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1\r
-#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12\r
-#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0\r
-#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1\r
-#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13\r
-#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0\r
-#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1\r
-#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14\r
-#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0\r
-#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1\r
-#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15\r
-#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0\r
-#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1\r
-\r
-/******************  Bits definition for GPIO_PUPDR register  *****************/\r
-#define GPIO_PUPDR_PUPD0_Pos           (0U)\r
-#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */\r
-#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk\r
-#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */\r
-#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */\r
-#define GPIO_PUPDR_PUPD1_Pos           (2U)\r
-#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */\r
-#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk\r
-#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */\r
-#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */\r
-#define GPIO_PUPDR_PUPD2_Pos           (4U)\r
-#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */\r
-#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk\r
-#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */\r
-#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */\r
-#define GPIO_PUPDR_PUPD3_Pos           (6U)\r
-#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */\r
-#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk\r
-#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */\r
-#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */\r
-#define GPIO_PUPDR_PUPD4_Pos           (8U)\r
-#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */\r
-#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk\r
-#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */\r
-#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */\r
-#define GPIO_PUPDR_PUPD5_Pos           (10U)\r
-#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */\r
-#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk\r
-#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */\r
-#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */\r
-#define GPIO_PUPDR_PUPD6_Pos           (12U)\r
-#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */\r
-#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk\r
-#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */\r
-#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */\r
-#define GPIO_PUPDR_PUPD7_Pos           (14U)\r
-#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */\r
-#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk\r
-#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */\r
-#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */\r
-#define GPIO_PUPDR_PUPD8_Pos           (16U)\r
-#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */\r
-#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk\r
-#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */\r
-#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */\r
-#define GPIO_PUPDR_PUPD9_Pos           (18U)\r
-#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */\r
-#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk\r
-#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */\r
-#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */\r
-#define GPIO_PUPDR_PUPD10_Pos          (20U)\r
-#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */\r
-#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk\r
-#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */\r
-#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */\r
-#define GPIO_PUPDR_PUPD11_Pos          (22U)\r
-#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */\r
-#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk\r
-#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */\r
-#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */\r
-#define GPIO_PUPDR_PUPD12_Pos          (24U)\r
-#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */\r
-#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk\r
-#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */\r
-#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */\r
-#define GPIO_PUPDR_PUPD13_Pos          (26U)\r
-#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */\r
-#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk\r
-#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */\r
-#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */\r
-#define GPIO_PUPDR_PUPD14_Pos          (28U)\r
-#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */\r
-#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk\r
-#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */\r
-#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */\r
-#define GPIO_PUPDR_PUPD15_Pos          (30U)\r
-#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */\r
-#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk\r
-#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */\r
-#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */\r
-\r
-/* Legacy defines */\r
-#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0\r
-#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0\r
-#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1\r
-#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1\r
-#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0\r
-#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1\r
-#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2\r
-#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0\r
-#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1\r
-#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3\r
-#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0\r
-#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1\r
-#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4\r
-#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0\r
-#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1\r
-#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5\r
-#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0\r
-#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1\r
-#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6\r
-#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0\r
-#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1\r
-#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7\r
-#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0\r
-#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1\r
-#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8\r
-#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0\r
-#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1\r
-#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9\r
-#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0\r
-#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1\r
-#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10\r
-#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0\r
-#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1\r
-#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11\r
-#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0\r
-#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1\r
-#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12\r
-#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0\r
-#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1\r
-#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13\r
-#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0\r
-#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1\r
-#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14\r
-#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0\r
-#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1\r
-#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15\r
-#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0\r
-#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1\r
-\r
-/******************  Bits definition for GPIO_IDR register  *******************/\r
-#define GPIO_IDR_ID0_Pos               (0U)\r
-#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */\r
-#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk\r
-#define GPIO_IDR_ID1_Pos               (1U)\r
-#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */\r
-#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk\r
-#define GPIO_IDR_ID2_Pos               (2U)\r
-#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */\r
-#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk\r
-#define GPIO_IDR_ID3_Pos               (3U)\r
-#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */\r
-#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk\r
-#define GPIO_IDR_ID4_Pos               (4U)\r
-#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */\r
-#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk\r
-#define GPIO_IDR_ID5_Pos               (5U)\r
-#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */\r
-#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk\r
-#define GPIO_IDR_ID6_Pos               (6U)\r
-#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */\r
-#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk\r
-#define GPIO_IDR_ID7_Pos               (7U)\r
-#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */\r
-#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk\r
-#define GPIO_IDR_ID8_Pos               (8U)\r
-#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */\r
-#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk\r
-#define GPIO_IDR_ID9_Pos               (9U)\r
-#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */\r
-#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk\r
-#define GPIO_IDR_ID10_Pos              (10U)\r
-#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */\r
-#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk\r
-#define GPIO_IDR_ID11_Pos              (11U)\r
-#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */\r
-#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk\r
-#define GPIO_IDR_ID12_Pos              (12U)\r
-#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */\r
-#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk\r
-#define GPIO_IDR_ID13_Pos              (13U)\r
-#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */\r
-#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk\r
-#define GPIO_IDR_ID14_Pos              (14U)\r
-#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */\r
-#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk\r
-#define GPIO_IDR_ID15_Pos              (15U)\r
-#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */\r
-#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk\r
-\r
-/* Legacy defines */\r
-#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0\r
-#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1\r
-#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2\r
-#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3\r
-#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4\r
-#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5\r
-#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6\r
-#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7\r
-#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8\r
-#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9\r
-#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10\r
-#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11\r
-#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12\r
-#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13\r
-#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14\r
-#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15\r
-\r
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\r
-#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0\r
-#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1\r
-#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2\r
-#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3\r
-#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4\r
-#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5\r
-#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6\r
-#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7\r
-#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8\r
-#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9\r
-#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10\r
-#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11\r
-#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12\r
-#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13\r
-#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14\r
-#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15\r
-\r
-/******************  Bits definition for GPIO_ODR register  *******************/\r
-#define GPIO_ODR_OD0_Pos               (0U)\r
-#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */\r
-#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk\r
-#define GPIO_ODR_OD1_Pos               (1U)\r
-#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */\r
-#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk\r
-#define GPIO_ODR_OD2_Pos               (2U)\r
-#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */\r
-#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk\r
-#define GPIO_ODR_OD3_Pos               (3U)\r
-#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */\r
-#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk\r
-#define GPIO_ODR_OD4_Pos               (4U)\r
-#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */\r
-#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk\r
-#define GPIO_ODR_OD5_Pos               (5U)\r
-#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */\r
-#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk\r
-#define GPIO_ODR_OD6_Pos               (6U)\r
-#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */\r
-#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk\r
-#define GPIO_ODR_OD7_Pos               (7U)\r
-#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */\r
-#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk\r
-#define GPIO_ODR_OD8_Pos               (8U)\r
-#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */\r
-#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk\r
-#define GPIO_ODR_OD9_Pos               (9U)\r
-#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */\r
-#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk\r
-#define GPIO_ODR_OD10_Pos              (10U)\r
-#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */\r
-#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk\r
-#define GPIO_ODR_OD11_Pos              (11U)\r
-#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */\r
-#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk\r
-#define GPIO_ODR_OD12_Pos              (12U)\r
-#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */\r
-#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk\r
-#define GPIO_ODR_OD13_Pos              (13U)\r
-#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */\r
-#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk\r
-#define GPIO_ODR_OD14_Pos              (14U)\r
-#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */\r
-#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk\r
-#define GPIO_ODR_OD15_Pos              (15U)\r
-#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */\r
-#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk\r
-\r
-/* Legacy defines */\r
-#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0\r
-#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1\r
-#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2\r
-#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3\r
-#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4\r
-#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5\r
-#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6\r
-#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7\r
-#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8\r
-#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9\r
-#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10\r
-#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11\r
-#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12\r
-#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13\r
-#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14\r
-#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15\r
-\r
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\r
-#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0\r
-#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1\r
-#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2\r
-#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3\r
-#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4\r
-#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5\r
-#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6\r
-#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7\r
-#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8\r
-#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9\r
-#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10\r
-#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11\r
-#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12\r
-#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13\r
-#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14\r
-#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15\r
-\r
-/******************  Bits definition for GPIO_BSRR register  ******************/\r
-#define GPIO_BSRR_BS0_Pos              (0U)\r
-#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */\r
-#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk\r
-#define GPIO_BSRR_BS1_Pos              (1U)\r
-#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */\r
-#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk\r
-#define GPIO_BSRR_BS2_Pos              (2U)\r
-#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */\r
-#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk\r
-#define GPIO_BSRR_BS3_Pos              (3U)\r
-#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */\r
-#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk\r
-#define GPIO_BSRR_BS4_Pos              (4U)\r
-#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */\r
-#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk\r
-#define GPIO_BSRR_BS5_Pos              (5U)\r
-#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */\r
-#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk\r
-#define GPIO_BSRR_BS6_Pos              (6U)\r
-#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */\r
-#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk\r
-#define GPIO_BSRR_BS7_Pos              (7U)\r
-#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */\r
-#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk\r
-#define GPIO_BSRR_BS8_Pos              (8U)\r
-#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */\r
-#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk\r
-#define GPIO_BSRR_BS9_Pos              (9U)\r
-#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */\r
-#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk\r
-#define GPIO_BSRR_BS10_Pos             (10U)\r
-#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */\r
-#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk\r
-#define GPIO_BSRR_BS11_Pos             (11U)\r
-#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */\r
-#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk\r
-#define GPIO_BSRR_BS12_Pos             (12U)\r
-#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */\r
-#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk\r
-#define GPIO_BSRR_BS13_Pos             (13U)\r
-#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */\r
-#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk\r
-#define GPIO_BSRR_BS14_Pos             (14U)\r
-#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */\r
-#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk\r
-#define GPIO_BSRR_BS15_Pos             (15U)\r
-#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */\r
-#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk\r
-#define GPIO_BSRR_BR0_Pos              (16U)\r
-#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */\r
-#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk\r
-#define GPIO_BSRR_BR1_Pos              (17U)\r
-#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */\r
-#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk\r
-#define GPIO_BSRR_BR2_Pos              (18U)\r
-#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */\r
-#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk\r
-#define GPIO_BSRR_BR3_Pos              (19U)\r
-#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */\r
-#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk\r
-#define GPIO_BSRR_BR4_Pos              (20U)\r
-#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */\r
-#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk\r
-#define GPIO_BSRR_BR5_Pos              (21U)\r
-#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */\r
-#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk\r
-#define GPIO_BSRR_BR6_Pos              (22U)\r
-#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */\r
-#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk\r
-#define GPIO_BSRR_BR7_Pos              (23U)\r
-#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */\r
-#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk\r
-#define GPIO_BSRR_BR8_Pos              (24U)\r
-#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */\r
-#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk\r
-#define GPIO_BSRR_BR9_Pos              (25U)\r
-#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */\r
-#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk\r
-#define GPIO_BSRR_BR10_Pos             (26U)\r
-#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */\r
-#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk\r
-#define GPIO_BSRR_BR11_Pos             (27U)\r
-#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */\r
-#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk\r
-#define GPIO_BSRR_BR12_Pos             (28U)\r
-#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */\r
-#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk\r
-#define GPIO_BSRR_BR13_Pos             (29U)\r
-#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */\r
-#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk\r
-#define GPIO_BSRR_BR14_Pos             (30U)\r
-#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */\r
-#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk\r
-#define GPIO_BSRR_BR15_Pos             (31U)\r
-#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */\r
-#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk\r
-\r
-/* Legacy defines */\r
-#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0\r
-#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1\r
-#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2\r
-#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3\r
-#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4\r
-#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5\r
-#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6\r
-#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7\r
-#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8\r
-#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9\r
-#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10\r
-#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11\r
-#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12\r
-#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13\r
-#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14\r
-#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15\r
-#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0\r
-#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1\r
-#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2\r
-#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3\r
-#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4\r
-#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5\r
-#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6\r
-#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7\r
-#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8\r
-#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9\r
-#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10\r
-#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11\r
-#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12\r
-#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13\r
-#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14\r
-#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15\r
-\r
-/****************** Bit definition for GPIO_LCKR register *********************/\r
-#define GPIO_LCKR_LCK0_Pos             (0U)\r
-#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */\r
-#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk\r
-#define GPIO_LCKR_LCK1_Pos             (1U)\r
-#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */\r
-#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk\r
-#define GPIO_LCKR_LCK2_Pos             (2U)\r
-#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */\r
-#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk\r
-#define GPIO_LCKR_LCK3_Pos             (3U)\r
-#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */\r
-#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk\r
-#define GPIO_LCKR_LCK4_Pos             (4U)\r
-#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */\r
-#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk\r
-#define GPIO_LCKR_LCK5_Pos             (5U)\r
-#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */\r
-#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk\r
-#define GPIO_LCKR_LCK6_Pos             (6U)\r
-#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */\r
-#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk\r
-#define GPIO_LCKR_LCK7_Pos             (7U)\r
-#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */\r
-#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk\r
-#define GPIO_LCKR_LCK8_Pos             (8U)\r
-#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */\r
-#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk\r
-#define GPIO_LCKR_LCK9_Pos             (9U)\r
-#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */\r
-#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk\r
-#define GPIO_LCKR_LCK10_Pos            (10U)\r
-#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */\r
-#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk\r
-#define GPIO_LCKR_LCK11_Pos            (11U)\r
-#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */\r
-#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk\r
-#define GPIO_LCKR_LCK12_Pos            (12U)\r
-#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */\r
-#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk\r
-#define GPIO_LCKR_LCK13_Pos            (13U)\r
-#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */\r
-#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk\r
-#define GPIO_LCKR_LCK14_Pos            (14U)\r
-#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */\r
-#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk\r
-#define GPIO_LCKR_LCK15_Pos            (15U)\r
-#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */\r
-#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk\r
-#define GPIO_LCKR_LCKK_Pos             (16U)\r
-#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */\r
-#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk\r
-\r
-/****************** Bit definition for GPIO_AFRL register *********************/\r
-#define GPIO_AFRL_AFSEL0_Pos           (0U)\r
-#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */\r
-#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk\r
-#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */\r
-#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */\r
-#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */\r
-#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */\r
-#define GPIO_AFRL_AFSEL1_Pos           (4U)\r
-#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */\r
-#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk\r
-#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */\r
-#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */\r
-#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */\r
-#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */\r
-#define GPIO_AFRL_AFSEL2_Pos           (8U)\r
-#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */\r
-#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk\r
-#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */\r
-#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */\r
-#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */\r
-#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */\r
-#define GPIO_AFRL_AFSEL3_Pos           (12U)\r
-#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */\r
-#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk\r
-#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */\r
-#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */\r
-#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */\r
-#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */\r
-#define GPIO_AFRL_AFSEL4_Pos           (16U)\r
-#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */\r
-#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk\r
-#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */\r
-#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */\r
-#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */\r
-#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */\r
-#define GPIO_AFRL_AFSEL5_Pos           (20U)\r
-#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */\r
-#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk\r
-#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */\r
-#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */\r
-#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */\r
-#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */\r
-#define GPIO_AFRL_AFSEL6_Pos           (24U)\r
-#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */\r
-#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk\r
-#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */\r
-#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */\r
-#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */\r
-#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */\r
-#define GPIO_AFRL_AFSEL7_Pos           (28U)\r
-#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */\r
-#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk\r
-#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */\r
-#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */\r
-#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */\r
-#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */\r
-\r
-/* Legacy defines */\r
-#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\r
-#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\r
-#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\r
-#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\r
-#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\r
-#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\r
-#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\r
-#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\r
-\r
-/****************** Bit definition for GPIO_AFRH register *********************/\r
-#define GPIO_AFRH_AFSEL8_Pos           (0U)\r
-#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */\r
-#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk\r
-#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */\r
-#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */\r
-#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */\r
-#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */\r
-#define GPIO_AFRH_AFSEL9_Pos           (4U)\r
-#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */\r
-#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk\r
-#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */\r
-#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */\r
-#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */\r
-#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */\r
-#define GPIO_AFRH_AFSEL10_Pos          (8U)\r
-#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */\r
-#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk\r
-#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */\r
-#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */\r
-#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */\r
-#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */\r
-#define GPIO_AFRH_AFSEL11_Pos          (12U)\r
-#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */\r
-#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk\r
-#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */\r
-#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */\r
-#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */\r
-#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */\r
-#define GPIO_AFRH_AFSEL12_Pos          (16U)\r
-#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */\r
-#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk\r
-#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */\r
-#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */\r
-#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */\r
-#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */\r
-#define GPIO_AFRH_AFSEL13_Pos          (20U)\r
-#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */\r
-#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk\r
-#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */\r
-#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */\r
-#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */\r
-#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */\r
-#define GPIO_AFRH_AFSEL14_Pos          (24U)\r
-#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */\r
-#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk\r
-#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */\r
-#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */\r
-#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */\r
-#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */\r
-#define GPIO_AFRH_AFSEL15_Pos          (28U)\r
-#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */\r
-#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk\r
-#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */\r
-#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */\r
-#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */\r
-#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */\r
-\r
-/* Legacy defines */\r
-#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\r
-#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\r
-#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\r
-#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\r
-#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\r
-#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\r
-#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\r
-#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\r
-\r
-/******************  Bits definition for GPIO_BRR register  ******************/\r
-#define GPIO_BRR_BR0_Pos               (0U)\r
-#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */\r
-#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk\r
-#define GPIO_BRR_BR1_Pos               (1U)\r
-#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */\r
-#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk\r
-#define GPIO_BRR_BR2_Pos               (2U)\r
-#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */\r
-#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk\r
-#define GPIO_BRR_BR3_Pos               (3U)\r
-#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */\r
-#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk\r
-#define GPIO_BRR_BR4_Pos               (4U)\r
-#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */\r
-#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk\r
-#define GPIO_BRR_BR5_Pos               (5U)\r
-#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */\r
-#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk\r
-#define GPIO_BRR_BR6_Pos               (6U)\r
-#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */\r
-#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk\r
-#define GPIO_BRR_BR7_Pos               (7U)\r
-#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */\r
-#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk\r
-#define GPIO_BRR_BR8_Pos               (8U)\r
-#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */\r
-#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk\r
-#define GPIO_BRR_BR9_Pos               (9U)\r
-#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */\r
-#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk\r
-#define GPIO_BRR_BR10_Pos              (10U)\r
-#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */\r
-#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk\r
-#define GPIO_BRR_BR11_Pos              (11U)\r
-#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */\r
-#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk\r
-#define GPIO_BRR_BR12_Pos              (12U)\r
-#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */\r
-#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk\r
-#define GPIO_BRR_BR13_Pos              (13U)\r
-#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */\r
-#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk\r
-#define GPIO_BRR_BR14_Pos              (14U)\r
-#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */\r
-#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk\r
-#define GPIO_BRR_BR15_Pos              (15U)\r
-#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */\r
-#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk\r
-\r
-/* Legacy defines */\r
-#define GPIO_BRR_BR_0                       GPIO_BRR_BR0\r
-#define GPIO_BRR_BR_1                       GPIO_BRR_BR1\r
-#define GPIO_BRR_BR_2                       GPIO_BRR_BR2\r
-#define GPIO_BRR_BR_3                       GPIO_BRR_BR3\r
-#define GPIO_BRR_BR_4                       GPIO_BRR_BR4\r
-#define GPIO_BRR_BR_5                       GPIO_BRR_BR5\r
-#define GPIO_BRR_BR_6                       GPIO_BRR_BR6\r
-#define GPIO_BRR_BR_7                       GPIO_BRR_BR7\r
-#define GPIO_BRR_BR_8                       GPIO_BRR_BR8\r
-#define GPIO_BRR_BR_9                       GPIO_BRR_BR9\r
-#define GPIO_BRR_BR_10                      GPIO_BRR_BR10\r
-#define GPIO_BRR_BR_11                      GPIO_BRR_BR11\r
-#define GPIO_BRR_BR_12                      GPIO_BRR_BR12\r
-#define GPIO_BRR_BR_13                      GPIO_BRR_BR13\r
-#define GPIO_BRR_BR_14                      GPIO_BRR_BR14\r
-#define GPIO_BRR_BR_15                      GPIO_BRR_BR15\r
-\r
-\r
-/******************  Bits definition for GPIO_ASCR register  *******************/\r
-#define GPIO_ASCR_ASC0_Pos             (0U)\r
-#define GPIO_ASCR_ASC0_Msk             (0x1UL << GPIO_ASCR_ASC0_Pos)           /*!< 0x00000001 */\r
-#define GPIO_ASCR_ASC0                 GPIO_ASCR_ASC0_Msk\r
-#define GPIO_ASCR_ASC1_Pos             (1U)\r
-#define GPIO_ASCR_ASC1_Msk             (0x1UL << GPIO_ASCR_ASC1_Pos)           /*!< 0x00000002 */\r
-#define GPIO_ASCR_ASC1                 GPIO_ASCR_ASC1_Msk\r
-#define GPIO_ASCR_ASC2_Pos             (2U)\r
-#define GPIO_ASCR_ASC2_Msk             (0x1UL << GPIO_ASCR_ASC2_Pos)           /*!< 0x00000004 */\r
-#define GPIO_ASCR_ASC2                 GPIO_ASCR_ASC2_Msk\r
-#define GPIO_ASCR_ASC3_Pos             (3U)\r
-#define GPIO_ASCR_ASC3_Msk             (0x1UL << GPIO_ASCR_ASC3_Pos)           /*!< 0x00000008 */\r
-#define GPIO_ASCR_ASC3                 GPIO_ASCR_ASC3_Msk\r
-#define GPIO_ASCR_ASC4_Pos             (4U)\r
-#define GPIO_ASCR_ASC4_Msk             (0x1UL << GPIO_ASCR_ASC4_Pos)           /*!< 0x00000010 */\r
-#define GPIO_ASCR_ASC4                 GPIO_ASCR_ASC4_Msk\r
-#define GPIO_ASCR_ASC5_Pos             (5U)\r
-#define GPIO_ASCR_ASC5_Msk             (0x1UL << GPIO_ASCR_ASC5_Pos)           /*!< 0x00000020 */\r
-#define GPIO_ASCR_ASC5                 GPIO_ASCR_ASC5_Msk\r
-#define GPIO_ASCR_ASC6_Pos             (6U)\r
-#define GPIO_ASCR_ASC6_Msk             (0x1UL << GPIO_ASCR_ASC6_Pos)           /*!< 0x00000040 */\r
-#define GPIO_ASCR_ASC6                 GPIO_ASCR_ASC6_Msk\r
-#define GPIO_ASCR_ASC7_Pos             (7U)\r
-#define GPIO_ASCR_ASC7_Msk             (0x1UL << GPIO_ASCR_ASC7_Pos)           /*!< 0x00000080 */\r
-#define GPIO_ASCR_ASC7                 GPIO_ASCR_ASC7_Msk\r
-#define GPIO_ASCR_ASC8_Pos             (8U)\r
-#define GPIO_ASCR_ASC8_Msk             (0x1UL << GPIO_ASCR_ASC8_Pos)           /*!< 0x00000100 */\r
-#define GPIO_ASCR_ASC8                 GPIO_ASCR_ASC8_Msk\r
-#define GPIO_ASCR_ASC9_Pos             (9U)\r
-#define GPIO_ASCR_ASC9_Msk             (0x1UL << GPIO_ASCR_ASC9_Pos)           /*!< 0x00000200 */\r
-#define GPIO_ASCR_ASC9                 GPIO_ASCR_ASC9_Msk\r
-#define GPIO_ASCR_ASC10_Pos            (10U)\r
-#define GPIO_ASCR_ASC10_Msk            (0x1UL << GPIO_ASCR_ASC10_Pos)          /*!< 0x00000400 */\r
-#define GPIO_ASCR_ASC10                GPIO_ASCR_ASC10_Msk\r
-#define GPIO_ASCR_ASC11_Pos            (11U)\r
-#define GPIO_ASCR_ASC11_Msk            (0x1UL << GPIO_ASCR_ASC11_Pos)          /*!< 0x00000800 */\r
-#define GPIO_ASCR_ASC11                GPIO_ASCR_ASC11_Msk\r
-#define GPIO_ASCR_ASC12_Pos            (12U)\r
-#define GPIO_ASCR_ASC12_Msk            (0x1UL << GPIO_ASCR_ASC12_Pos)          /*!< 0x00001000 */\r
-#define GPIO_ASCR_ASC12                GPIO_ASCR_ASC12_Msk\r
-#define GPIO_ASCR_ASC13_Pos            (13U)\r
-#define GPIO_ASCR_ASC13_Msk            (0x1UL << GPIO_ASCR_ASC13_Pos)          /*!< 0x00002000 */\r
-#define GPIO_ASCR_ASC13                GPIO_ASCR_ASC13_Msk\r
-#define GPIO_ASCR_ASC14_Pos            (14U)\r
-#define GPIO_ASCR_ASC14_Msk            (0x1UL << GPIO_ASCR_ASC14_Pos)          /*!< 0x00004000 */\r
-#define GPIO_ASCR_ASC14                GPIO_ASCR_ASC14_Msk\r
-#define GPIO_ASCR_ASC15_Pos            (15U)\r
-#define GPIO_ASCR_ASC15_Msk            (0x1UL << GPIO_ASCR_ASC15_Pos)          /*!< 0x00008000 */\r
-#define GPIO_ASCR_ASC15                GPIO_ASCR_ASC15_Msk\r
-\r
-/* Legacy defines */\r
-#define GPIO_ASCR_EN_0                      GPIO_ASCR_ASC0\r
-#define GPIO_ASCR_EN_1                      GPIO_ASCR_ASC1\r
-#define GPIO_ASCR_EN_2                      GPIO_ASCR_ASC2\r
-#define GPIO_ASCR_EN_3                      GPIO_ASCR_ASC3\r
-#define GPIO_ASCR_EN_4                      GPIO_ASCR_ASC4\r
-#define GPIO_ASCR_EN_5                      GPIO_ASCR_ASC5\r
-#define GPIO_ASCR_EN_6                      GPIO_ASCR_ASC6\r
-#define GPIO_ASCR_EN_7                      GPIO_ASCR_ASC7\r
-#define GPIO_ASCR_EN_8                      GPIO_ASCR_ASC8\r
-#define GPIO_ASCR_EN_9                      GPIO_ASCR_ASC9\r
-#define GPIO_ASCR_EN_10                     GPIO_ASCR_ASC10\r
-#define GPIO_ASCR_EN_11                     GPIO_ASCR_ASC11\r
-#define GPIO_ASCR_EN_12                     GPIO_ASCR_ASC12\r
-#define GPIO_ASCR_EN_13                     GPIO_ASCR_ASC13\r
-#define GPIO_ASCR_EN_14                     GPIO_ASCR_ASC14\r
-#define GPIO_ASCR_EN_15                     GPIO_ASCR_ASC15\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                      Inter-integrated Circuit Interface (I2C)              */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for I2C_CR1 register  *******************/\r
-#define I2C_CR1_PE_Pos               (0U)\r
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */\r
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */\r
-#define I2C_CR1_TXIE_Pos             (1U)\r
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */\r
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */\r
-#define I2C_CR1_RXIE_Pos             (2U)\r
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */\r
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */\r
-#define I2C_CR1_ADDRIE_Pos           (3U)\r
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */\r
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */\r
-#define I2C_CR1_NACKIE_Pos           (4U)\r
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */\r
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */\r
-#define I2C_CR1_STOPIE_Pos           (5U)\r
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */\r
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */\r
-#define I2C_CR1_TCIE_Pos             (6U)\r
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */\r
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */\r
-#define I2C_CR1_ERRIE_Pos            (7U)\r
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */\r
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */\r
-#define I2C_CR1_DNF_Pos              (8U)\r
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */\r
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */\r
-#define I2C_CR1_ANFOFF_Pos           (12U)\r
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */\r
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */\r
-#define I2C_CR1_SWRST_Pos            (13U)\r
-#define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */\r
-#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */\r
-#define I2C_CR1_TXDMAEN_Pos          (14U)\r
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */\r
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */\r
-#define I2C_CR1_RXDMAEN_Pos          (15U)\r
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */\r
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */\r
-#define I2C_CR1_SBC_Pos              (16U)\r
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */\r
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */\r
-#define I2C_CR1_NOSTRETCH_Pos        (17U)\r
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */\r
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */\r
-#define I2C_CR1_WUPEN_Pos            (18U)\r
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */\r
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */\r
-#define I2C_CR1_GCEN_Pos             (19U)\r
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */\r
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */\r
-#define I2C_CR1_SMBHEN_Pos           (20U)\r
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */\r
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */\r
-#define I2C_CR1_SMBDEN_Pos           (21U)\r
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */\r
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\r
-#define I2C_CR1_ALERTEN_Pos          (22U)\r
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */\r
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */\r
-#define I2C_CR1_PECEN_Pos            (23U)\r
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */\r
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */\r
-\r
-/******************  Bit definition for I2C_CR2 register  ********************/\r
-#define I2C_CR2_SADD_Pos             (0U)\r
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */\r
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */\r
-#define I2C_CR2_RD_WRN_Pos           (10U)\r
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */\r
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */\r
-#define I2C_CR2_ADD10_Pos            (11U)\r
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */\r
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */\r
-#define I2C_CR2_HEAD10R_Pos          (12U)\r
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */\r
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\r
-#define I2C_CR2_START_Pos            (13U)\r
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */\r
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */\r
-#define I2C_CR2_STOP_Pos             (14U)\r
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */\r
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */\r
-#define I2C_CR2_NACK_Pos             (15U)\r
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */\r
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */\r
-#define I2C_CR2_NBYTES_Pos           (16U)\r
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */\r
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */\r
-#define I2C_CR2_RELOAD_Pos           (24U)\r
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */\r
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */\r
-#define I2C_CR2_AUTOEND_Pos          (25U)\r
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */\r
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */\r
-#define I2C_CR2_PECBYTE_Pos          (26U)\r
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */\r
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */\r
-\r
-/*******************  Bit definition for I2C_OAR1 register  ******************/\r
-#define I2C_OAR1_OA1_Pos             (0U)\r
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */\r
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */\r
-#define I2C_OAR1_OA1MODE_Pos         (10U)\r
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */\r
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\r
-#define I2C_OAR1_OA1EN_Pos           (15U)\r
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */\r
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */\r
-\r
-/*******************  Bit definition for I2C_OAR2 register  ******************/\r
-#define I2C_OAR2_OA2_Pos             (1U)\r
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */\r
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */\r
-#define I2C_OAR2_OA2MSK_Pos          (8U)\r
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */\r
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */\r
-#define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */\r
-#define I2C_OAR2_OA2MASK01_Pos       (8U)\r
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */\r
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */\r
-#define I2C_OAR2_OA2MASK02_Pos       (9U)\r
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */\r
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r
-#define I2C_OAR2_OA2MASK03_Pos       (8U)\r
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */\r
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r
-#define I2C_OAR2_OA2MASK04_Pos       (10U)\r
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */\r
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r
-#define I2C_OAR2_OA2MASK05_Pos       (8U)\r
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */\r
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r
-#define I2C_OAR2_OA2MASK06_Pos       (9U)\r
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */\r
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */\r
-#define I2C_OAR2_OA2MASK07_Pos       (8U)\r
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */\r
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */\r
-#define I2C_OAR2_OA2EN_Pos           (15U)\r
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */\r
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */\r
-\r
-/*******************  Bit definition for I2C_TIMINGR register *******************/\r
-#define I2C_TIMINGR_SCLL_Pos         (0U)\r
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */\r
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */\r
-#define I2C_TIMINGR_SCLH_Pos         (8U)\r
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */\r
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\r
-#define I2C_TIMINGR_SDADEL_Pos       (16U)\r
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */\r
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */\r
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)\r
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */\r
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */\r
-#define I2C_TIMINGR_PRESC_Pos        (28U)\r
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */\r
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */\r
-\r
-/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\r
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */\r
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */\r
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)\r
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */\r
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */\r
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\r
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */\r
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */\r
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\r
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */\r
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */\r
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)\r
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */\r
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\r
-\r
-/******************  Bit definition for I2C_ISR register  *********************/\r
-#define I2C_ISR_TXE_Pos              (0U)\r
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */\r
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */\r
-#define I2C_ISR_TXIS_Pos             (1U)\r
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */\r
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */\r
-#define I2C_ISR_RXNE_Pos             (2U)\r
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */\r
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\r
-#define I2C_ISR_ADDR_Pos             (3U)\r
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */\r
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */\r
-#define I2C_ISR_NACKF_Pos            (4U)\r
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */\r
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */\r
-#define I2C_ISR_STOPF_Pos            (5U)\r
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */\r
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */\r
-#define I2C_ISR_TC_Pos               (6U)\r
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */\r
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\r
-#define I2C_ISR_TCR_Pos              (7U)\r
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */\r
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */\r
-#define I2C_ISR_BERR_Pos             (8U)\r
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */\r
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */\r
-#define I2C_ISR_ARLO_Pos             (9U)\r
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */\r
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */\r
-#define I2C_ISR_OVR_Pos              (10U)\r
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */\r
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */\r
-#define I2C_ISR_PECERR_Pos           (11U)\r
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */\r
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */\r
-#define I2C_ISR_TIMEOUT_Pos          (12U)\r
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */\r
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */\r
-#define I2C_ISR_ALERT_Pos            (13U)\r
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */\r
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */\r
-#define I2C_ISR_BUSY_Pos             (15U)\r
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */\r
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */\r
-#define I2C_ISR_DIR_Pos              (16U)\r
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */\r
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\r
-#define I2C_ISR_ADDCODE_Pos          (17U)\r
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */\r
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\r
-\r
-/******************  Bit definition for I2C_ICR register  *********************/\r
-#define I2C_ICR_ADDRCF_Pos           (3U)\r
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */\r
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */\r
-#define I2C_ICR_NACKCF_Pos           (4U)\r
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */\r
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */\r
-#define I2C_ICR_STOPCF_Pos           (5U)\r
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */\r
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */\r
-#define I2C_ICR_BERRCF_Pos           (8U)\r
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */\r
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */\r
-#define I2C_ICR_ARLOCF_Pos           (9U)\r
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */\r
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */\r
-#define I2C_ICR_OVRCF_Pos            (10U)\r
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */\r
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */\r
-#define I2C_ICR_PECCF_Pos            (11U)\r
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */\r
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */\r
-#define I2C_ICR_TIMOUTCF_Pos         (12U)\r
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */\r
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */\r
-#define I2C_ICR_ALERTCF_Pos          (13U)\r
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */\r
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */\r
-\r
-/******************  Bit definition for I2C_PECR register  *********************/\r
-#define I2C_PECR_PEC_Pos             (0U)\r
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */\r
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */\r
-\r
-/******************  Bit definition for I2C_RXDR register  *********************/\r
-#define I2C_RXDR_RXDATA_Pos          (0U)\r
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */\r
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */\r
-\r
-/******************  Bit definition for I2C_TXDR register  *********************/\r
-#define I2C_TXDR_TXDATA_Pos          (0U)\r
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */\r
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                           Independent WATCHDOG                             */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for IWDG_KR register  ********************/\r
-#define IWDG_KR_KEY_Pos      (0U)\r
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */\r
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\r
-\r
-/*******************  Bit definition for IWDG_PR register  ********************/\r
-#define IWDG_PR_PR_Pos       (0U)\r
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */\r
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\r
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */\r
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */\r
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */\r
-\r
-/*******************  Bit definition for IWDG_RLR register  *******************/\r
-#define IWDG_RLR_RL_Pos      (0U)\r
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */\r
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\r
-\r
-/*******************  Bit definition for IWDG_SR register  ********************/\r
-#define IWDG_SR_PVU_Pos      (0U)\r
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */\r
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\r
-#define IWDG_SR_RVU_Pos      (1U)\r
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */\r
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\r
-#define IWDG_SR_WVU_Pos      (2U)\r
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */\r
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\r
-\r
-/*******************  Bit definition for IWDG_KR register  ********************/\r
-#define IWDG_WINR_WIN_Pos    (0U)\r
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */\r
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                     Firewall                               */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-\r
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */\r
-#define FW_CSSA_ADD_Pos      (8U)\r
-#define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                     /*!< 0x00FFFF00 */\r
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */\r
-#define FW_CSL_LENG_Pos      (8U)\r
-#define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                     /*!< 0x003FFF00 */\r
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */\r
-#define FW_NVDSSA_ADD_Pos    (8U)\r
-#define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                   /*!< 0x00FFFF00 */\r
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */\r
-#define FW_NVDSL_LENG_Pos    (8U)\r
-#define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                   /*!< 0x003FFF00 */\r
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */\r
-#define FW_VDSSA_ADD_Pos     (6U)\r
-#define FW_VDSSA_ADD_Msk     (0x7FFUL << FW_VDSSA_ADD_Pos)                     /*!< 0x0001FFC0 */\r
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */\r
-#define FW_VDSL_LENG_Pos     (6U)\r
-#define FW_VDSL_LENG_Msk     (0x7FFUL << FW_VDSL_LENG_Pos)                     /*!< 0x0001FFC0 */\r
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */\r
-\r
-/**************************Bit definition for CR register *********************/\r
-#define FW_CR_FPA_Pos        (0U)\r
-#define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                          /*!< 0x00000001 */\r
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/\r
-#define FW_CR_VDS_Pos        (1U)\r
-#define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                          /*!< 0x00000002 */\r
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/\r
-#define FW_CR_VDE_Pos        (2U)\r
-#define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                          /*!< 0x00000004 */\r
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                             Power Control                                  */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-\r
-/********************  Bit definition for PWR_CR1 register  ********************/\r
-\r
-#define PWR_CR1_LPR_Pos              (14U)\r
-#define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */\r
-#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */\r
-#define PWR_CR1_VOS_Pos              (9U)\r
-#define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */\r
-#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
-#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */\r
-#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */\r
-#define PWR_CR1_DBP_Pos              (8U)\r
-#define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */\r
-#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */\r
-#define PWR_CR1_LPMS_Pos             (0U)\r
-#define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */\r
-#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */\r
-#define PWR_CR1_LPMS_STOP0           (0x00000000UL)                            /*!< Stop 0 mode */\r
-#define PWR_CR1_LPMS_STOP1_Pos       (0U)\r
-#define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */\r
-#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */\r
-#define PWR_CR1_LPMS_STOP2_Pos       (1U)\r
-#define PWR_CR1_LPMS_STOP2_Msk       (0x1UL << PWR_CR1_LPMS_STOP2_Pos)         /*!< 0x00000002 */\r
-#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */\r
-#define PWR_CR1_LPMS_STANDBY_Pos     (0U)\r
-#define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */\r
-#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */\r
-#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)\r
-#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */\r
-#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */\r
-\r
-\r
-/********************  Bit definition for PWR_CR2 register  ********************/\r
-#define PWR_CR2_USV_Pos              (10U)\r
-#define PWR_CR2_USV_Msk              (0x1UL << PWR_CR2_USV_Pos)                /*!< 0x00000400 */\r
-#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */\r
-#define PWR_CR2_IOSV_Pos             (9U)\r
-#define PWR_CR2_IOSV_Msk             (0x1UL << PWR_CR2_IOSV_Pos)               /*!< 0x00000200 */\r
-#define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */\r
-/*!< PVME  Peripheral Voltage Monitor Enable */\r
-#define PWR_CR2_PVME_Pos             (4U)\r
-#define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */\r
-#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */\r
-#define PWR_CR2_PVME4_Pos            (7U)\r
-#define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */\r
-#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */\r
-#define PWR_CR2_PVME3_Pos            (6U)\r
-#define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */\r
-#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */\r
-#define PWR_CR2_PVME2_Pos            (5U)\r
-#define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */\r
-#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */\r
-#define PWR_CR2_PVME1_Pos            (4U)\r
-#define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */\r
-#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */\r
-/*!< PVD level configuration */\r
-#define PWR_CR2_PLS_Pos              (1U)\r
-#define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */\r
-#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */\r
-#define PWR_CR2_PLS_LEV0             (0x00000000UL)                            /*!< PVD level 0 */\r
-#define PWR_CR2_PLS_LEV1_Pos         (1U)\r
-#define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */\r
-#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */\r
-#define PWR_CR2_PLS_LEV2_Pos         (2U)\r
-#define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */\r
-#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */\r
-#define PWR_CR2_PLS_LEV3_Pos         (1U)\r
-#define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */\r
-#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */\r
-#define PWR_CR2_PLS_LEV4_Pos         (3U)\r
-#define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */\r
-#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */\r
-#define PWR_CR2_PLS_LEV5_Pos         (1U)\r
-#define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */\r
-#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */\r
-#define PWR_CR2_PLS_LEV6_Pos         (2U)\r
-#define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */\r
-#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */\r
-#define PWR_CR2_PLS_LEV7_Pos         (1U)\r
-#define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */\r
-#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */\r
-#define PWR_CR2_PVDE_Pos             (0U)\r
-#define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */\r
-#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */\r
-\r
-/********************  Bit definition for PWR_CR3 register  ********************/\r
-#define PWR_CR3_EIWUL_Pos            (15U)\r
-#define PWR_CR3_EIWUL_Msk            (0x1UL << PWR_CR3_EIWUL_Pos)              /*!< 0x00008000 */\r
-#define PWR_CR3_EIWUL                PWR_CR3_EIWUL_Msk                         /*!< Enable Internal Wake-up line */\r
-#define PWR_CR3_APC_Pos              (10U)\r
-#define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */\r
-#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */\r
-#define PWR_CR3_RRS_Pos              (8U)\r
-#define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */\r
-#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */\r
-#define PWR_CR3_EWUP5_Pos            (4U)\r
-#define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */\r
-#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */\r
-#define PWR_CR3_EWUP4_Pos            (3U)\r
-#define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */\r
-#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */\r
-#define PWR_CR3_EWUP3_Pos            (2U)\r
-#define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */\r
-#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */\r
-#define PWR_CR3_EWUP2_Pos            (1U)\r
-#define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */\r
-#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */\r
-#define PWR_CR3_EWUP1_Pos            (0U)\r
-#define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */\r
-#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */\r
-#define PWR_CR3_EWUP_Pos             (0U)\r
-#define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */\r
-#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */\r
-\r
-/* Legacy defines */\r
-#define PWR_CR3_EIWF_Pos             PWR_CR3_EIWUL_Pos\r
-#define PWR_CR3_EIWF_Msk             PWR_CR3_EIWUL_Msk\r
-#define PWR_CR3_EIWF                 PWR_CR3_EIWUL\r
-\r
-\r
-/********************  Bit definition for PWR_CR4 register  ********************/\r
-#define PWR_CR4_VBRS_Pos             (9U)\r
-#define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */\r
-#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */\r
-#define PWR_CR4_VBE_Pos              (8U)\r
-#define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */\r
-#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */\r
-#define PWR_CR4_WP5_Pos              (4U)\r
-#define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */\r
-#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */\r
-#define PWR_CR4_WP4_Pos              (3U)\r
-#define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */\r
-#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */\r
-#define PWR_CR4_WP3_Pos              (2U)\r
-#define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */\r
-#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */\r
-#define PWR_CR4_WP2_Pos              (1U)\r
-#define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */\r
-#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */\r
-#define PWR_CR4_WP1_Pos              (0U)\r
-#define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */\r
-#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */\r
-\r
-/********************  Bit definition for PWR_SR1 register  ********************/\r
-#define PWR_SR1_WUFI_Pos             (15U)\r
-#define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */\r
-#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */\r
-#define PWR_SR1_SBF_Pos              (8U)\r
-#define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */\r
-#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */\r
-#define PWR_SR1_WUF_Pos              (0U)\r
-#define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */\r
-#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */\r
-#define PWR_SR1_WUF5_Pos             (4U)\r
-#define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */\r
-#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */\r
-#define PWR_SR1_WUF4_Pos             (3U)\r
-#define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */\r
-#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */\r
-#define PWR_SR1_WUF3_Pos             (2U)\r
-#define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */\r
-#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */\r
-#define PWR_SR1_WUF2_Pos             (1U)\r
-#define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */\r
-#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */\r
-#define PWR_SR1_WUF1_Pos             (0U)\r
-#define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */\r
-#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */\r
-\r
-/********************  Bit definition for PWR_SR2 register  ********************/\r
-#define PWR_SR2_PVMO4_Pos            (15U)\r
-#define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */\r
-#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */\r
-#define PWR_SR2_PVMO3_Pos            (14U)\r
-#define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */\r
-#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */\r
-#define PWR_SR2_PVMO2_Pos            (13U)\r
-#define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */\r
-#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */\r
-#define PWR_SR2_PVMO1_Pos            (12U)\r
-#define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */\r
-#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */\r
-#define PWR_SR2_PVDO_Pos             (11U)\r
-#define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */\r
-#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */\r
-#define PWR_SR2_VOSF_Pos             (10U)\r
-#define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */\r
-#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */\r
-#define PWR_SR2_REGLPF_Pos           (9U)\r
-#define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */\r
-#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */\r
-#define PWR_SR2_REGLPS_Pos           (8U)\r
-#define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */\r
-#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */\r
-\r
-/********************  Bit definition for PWR_SCR register  ********************/\r
-#define PWR_SCR_CSBF_Pos             (8U)\r
-#define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */\r
-#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */\r
-#define PWR_SCR_CWUF_Pos             (0U)\r
-#define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */\r
-#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */\r
-#define PWR_SCR_CWUF5_Pos            (4U)\r
-#define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */\r
-#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */\r
-#define PWR_SCR_CWUF4_Pos            (3U)\r
-#define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */\r
-#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */\r
-#define PWR_SCR_CWUF3_Pos            (2U)\r
-#define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */\r
-#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */\r
-#define PWR_SCR_CWUF2_Pos            (1U)\r
-#define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */\r
-#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */\r
-#define PWR_SCR_CWUF1_Pos            (0U)\r
-#define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */\r
-#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */\r
-\r
-/********************  Bit definition for PWR_PUCRA register  ********************/\r
-#define PWR_PUCRA_PA15_Pos           (15U)\r
-#define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */\r
-#define PWR_PUCRA_PA13_Pos           (13U)\r
-#define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */\r
-#define PWR_PUCRA_PA12_Pos           (12U)\r
-#define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */\r
-#define PWR_PUCRA_PA11_Pos           (11U)\r
-#define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */\r
-#define PWR_PUCRA_PA10_Pos           (10U)\r
-#define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */\r
-#define PWR_PUCRA_PA9_Pos            (9U)\r
-#define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */\r
-#define PWR_PUCRA_PA8_Pos            (8U)\r
-#define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */\r
-#define PWR_PUCRA_PA7_Pos            (7U)\r
-#define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */\r
-#define PWR_PUCRA_PA6_Pos            (6U)\r
-#define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */\r
-#define PWR_PUCRA_PA5_Pos            (5U)\r
-#define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */\r
-#define PWR_PUCRA_PA4_Pos            (4U)\r
-#define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */\r
-#define PWR_PUCRA_PA3_Pos            (3U)\r
-#define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */\r
-#define PWR_PUCRA_PA2_Pos            (2U)\r
-#define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */\r
-#define PWR_PUCRA_PA1_Pos            (1U)\r
-#define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */\r
-#define PWR_PUCRA_PA0_Pos            (0U)\r
-#define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRA register  ********************/\r
-#define PWR_PDCRA_PA14_Pos           (14U)\r
-#define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */\r
-#define PWR_PDCRA_PA12_Pos           (12U)\r
-#define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */\r
-#define PWR_PDCRA_PA11_Pos           (11U)\r
-#define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */\r
-#define PWR_PDCRA_PA10_Pos           (10U)\r
-#define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */\r
-#define PWR_PDCRA_PA9_Pos            (9U)\r
-#define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */\r
-#define PWR_PDCRA_PA8_Pos            (8U)\r
-#define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */\r
-#define PWR_PDCRA_PA7_Pos            (7U)\r
-#define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */\r
-#define PWR_PDCRA_PA6_Pos            (6U)\r
-#define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */\r
-#define PWR_PDCRA_PA5_Pos            (5U)\r
-#define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */\r
-#define PWR_PDCRA_PA4_Pos            (4U)\r
-#define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */\r
-#define PWR_PDCRA_PA3_Pos            (3U)\r
-#define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */\r
-#define PWR_PDCRA_PA2_Pos            (2U)\r
-#define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */\r
-#define PWR_PDCRA_PA1_Pos            (1U)\r
-#define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */\r
-#define PWR_PDCRA_PA0_Pos            (0U)\r
-#define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */\r
-\r
-/********************  Bit definition for PWR_PUCRB register  ********************/\r
-#define PWR_PUCRB_PB15_Pos           (15U)\r
-#define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */\r
-#define PWR_PUCRB_PB14_Pos           (14U)\r
-#define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */\r
-#define PWR_PUCRB_PB13_Pos           (13U)\r
-#define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */\r
-#define PWR_PUCRB_PB12_Pos           (12U)\r
-#define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */\r
-#define PWR_PUCRB_PB11_Pos           (11U)\r
-#define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */\r
-#define PWR_PUCRB_PB10_Pos           (10U)\r
-#define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */\r
-#define PWR_PUCRB_PB9_Pos            (9U)\r
-#define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */\r
-#define PWR_PUCRB_PB8_Pos            (8U)\r
-#define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */\r
-#define PWR_PUCRB_PB7_Pos            (7U)\r
-#define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */\r
-#define PWR_PUCRB_PB6_Pos            (6U)\r
-#define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */\r
-#define PWR_PUCRB_PB5_Pos            (5U)\r
-#define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */\r
-#define PWR_PUCRB_PB4_Pos            (4U)\r
-#define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */\r
-#define PWR_PUCRB_PB3_Pos            (3U)\r
-#define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */\r
-#define PWR_PUCRB_PB2_Pos            (2U)\r
-#define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */\r
-#define PWR_PUCRB_PB1_Pos            (1U)\r
-#define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */\r
-#define PWR_PUCRB_PB0_Pos            (0U)\r
-#define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRB register  ********************/\r
-#define PWR_PDCRB_PB15_Pos           (15U)\r
-#define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */\r
-#define PWR_PDCRB_PB14_Pos           (14U)\r
-#define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */\r
-#define PWR_PDCRB_PB13_Pos           (13U)\r
-#define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */\r
-#define PWR_PDCRB_PB12_Pos           (12U)\r
-#define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */\r
-#define PWR_PDCRB_PB11_Pos           (11U)\r
-#define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */\r
-#define PWR_PDCRB_PB10_Pos           (10U)\r
-#define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */\r
-#define PWR_PDCRB_PB9_Pos            (9U)\r
-#define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */\r
-#define PWR_PDCRB_PB8_Pos            (8U)\r
-#define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */\r
-#define PWR_PDCRB_PB7_Pos            (7U)\r
-#define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */\r
-#define PWR_PDCRB_PB6_Pos            (6U)\r
-#define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */\r
-#define PWR_PDCRB_PB5_Pos            (5U)\r
-#define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */\r
-#define PWR_PDCRB_PB3_Pos            (3U)\r
-#define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */\r
-#define PWR_PDCRB_PB2_Pos            (2U)\r
-#define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */\r
-#define PWR_PDCRB_PB1_Pos            (1U)\r
-#define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */\r
-#define PWR_PDCRB_PB0_Pos            (0U)\r
-#define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */\r
-\r
-/********************  Bit definition for PWR_PUCRC register  ********************/\r
-#define PWR_PUCRC_PC15_Pos           (15U)\r
-#define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */\r
-#define PWR_PUCRC_PC14_Pos           (14U)\r
-#define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */\r
-#define PWR_PUCRC_PC13_Pos           (13U)\r
-#define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */\r
-#define PWR_PUCRC_PC12_Pos           (12U)\r
-#define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */\r
-#define PWR_PUCRC_PC11_Pos           (11U)\r
-#define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */\r
-#define PWR_PUCRC_PC10_Pos           (10U)\r
-#define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */\r
-#define PWR_PUCRC_PC9_Pos            (9U)\r
-#define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */\r
-#define PWR_PUCRC_PC8_Pos            (8U)\r
-#define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */\r
-#define PWR_PUCRC_PC7_Pos            (7U)\r
-#define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */\r
-#define PWR_PUCRC_PC6_Pos            (6U)\r
-#define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */\r
-#define PWR_PUCRC_PC5_Pos            (5U)\r
-#define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */\r
-#define PWR_PUCRC_PC4_Pos            (4U)\r
-#define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */\r
-#define PWR_PUCRC_PC3_Pos            (3U)\r
-#define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */\r
-#define PWR_PUCRC_PC2_Pos            (2U)\r
-#define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */\r
-#define PWR_PUCRC_PC1_Pos            (1U)\r
-#define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */\r
-#define PWR_PUCRC_PC0_Pos            (0U)\r
-#define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRC register  ********************/\r
-#define PWR_PDCRC_PC15_Pos           (15U)\r
-#define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */\r
-#define PWR_PDCRC_PC14_Pos           (14U)\r
-#define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */\r
-#define PWR_PDCRC_PC13_Pos           (13U)\r
-#define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */\r
-#define PWR_PDCRC_PC12_Pos           (12U)\r
-#define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */\r
-#define PWR_PDCRC_PC11_Pos           (11U)\r
-#define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */\r
-#define PWR_PDCRC_PC10_Pos           (10U)\r
-#define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */\r
-#define PWR_PDCRC_PC9_Pos            (9U)\r
-#define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */\r
-#define PWR_PDCRC_PC8_Pos            (8U)\r
-#define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */\r
-#define PWR_PDCRC_PC7_Pos            (7U)\r
-#define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */\r
-#define PWR_PDCRC_PC6_Pos            (6U)\r
-#define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */\r
-#define PWR_PDCRC_PC5_Pos            (5U)\r
-#define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */\r
-#define PWR_PDCRC_PC4_Pos            (4U)\r
-#define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */\r
-#define PWR_PDCRC_PC3_Pos            (3U)\r
-#define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */\r
-#define PWR_PDCRC_PC2_Pos            (2U)\r
-#define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */\r
-#define PWR_PDCRC_PC1_Pos            (1U)\r
-#define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */\r
-#define PWR_PDCRC_PC0_Pos            (0U)\r
-#define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */\r
-\r
-/********************  Bit definition for PWR_PUCRD register  ********************/\r
-#define PWR_PUCRD_PD15_Pos           (15U)\r
-#define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */\r
-#define PWR_PUCRD_PD14_Pos           (14U)\r
-#define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */\r
-#define PWR_PUCRD_PD13_Pos           (13U)\r
-#define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */\r
-#define PWR_PUCRD_PD12_Pos           (12U)\r
-#define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */\r
-#define PWR_PUCRD_PD11_Pos           (11U)\r
-#define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */\r
-#define PWR_PUCRD_PD10_Pos           (10U)\r
-#define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */\r
-#define PWR_PUCRD_PD9_Pos            (9U)\r
-#define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */\r
-#define PWR_PUCRD_PD8_Pos            (8U)\r
-#define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */\r
-#define PWR_PUCRD_PD7_Pos            (7U)\r
-#define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */\r
-#define PWR_PUCRD_PD6_Pos            (6U)\r
-#define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */\r
-#define PWR_PUCRD_PD5_Pos            (5U)\r
-#define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */\r
-#define PWR_PUCRD_PD4_Pos            (4U)\r
-#define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */\r
-#define PWR_PUCRD_PD3_Pos            (3U)\r
-#define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */\r
-#define PWR_PUCRD_PD2_Pos            (2U)\r
-#define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */\r
-#define PWR_PUCRD_PD1_Pos            (1U)\r
-#define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */\r
-#define PWR_PUCRD_PD0_Pos            (0U)\r
-#define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRD register  ********************/\r
-#define PWR_PDCRD_PD15_Pos           (15U)\r
-#define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */\r
-#define PWR_PDCRD_PD14_Pos           (14U)\r
-#define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */\r
-#define PWR_PDCRD_PD13_Pos           (13U)\r
-#define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */\r
-#define PWR_PDCRD_PD12_Pos           (12U)\r
-#define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */\r
-#define PWR_PDCRD_PD11_Pos           (11U)\r
-#define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */\r
-#define PWR_PDCRD_PD10_Pos           (10U)\r
-#define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */\r
-#define PWR_PDCRD_PD9_Pos            (9U)\r
-#define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */\r
-#define PWR_PDCRD_PD8_Pos            (8U)\r
-#define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */\r
-#define PWR_PDCRD_PD7_Pos            (7U)\r
-#define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */\r
-#define PWR_PDCRD_PD6_Pos            (6U)\r
-#define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */\r
-#define PWR_PDCRD_PD5_Pos            (5U)\r
-#define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */\r
-#define PWR_PDCRD_PD4_Pos            (4U)\r
-#define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */\r
-#define PWR_PDCRD_PD3_Pos            (3U)\r
-#define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */\r
-#define PWR_PDCRD_PD2_Pos            (2U)\r
-#define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */\r
-#define PWR_PDCRD_PD1_Pos            (1U)\r
-#define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */\r
-#define PWR_PDCRD_PD0_Pos            (0U)\r
-#define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */\r
-\r
-/********************  Bit definition for PWR_PUCRE register  ********************/\r
-#define PWR_PUCRE_PE15_Pos           (15U)\r
-#define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */\r
-#define PWR_PUCRE_PE14_Pos           (14U)\r
-#define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */\r
-#define PWR_PUCRE_PE13_Pos           (13U)\r
-#define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */\r
-#define PWR_PUCRE_PE12_Pos           (12U)\r
-#define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */\r
-#define PWR_PUCRE_PE11_Pos           (11U)\r
-#define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */\r
-#define PWR_PUCRE_PE10_Pos           (10U)\r
-#define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */\r
-#define PWR_PUCRE_PE9_Pos            (9U)\r
-#define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */\r
-#define PWR_PUCRE_PE8_Pos            (8U)\r
-#define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */\r
-#define PWR_PUCRE_PE7_Pos            (7U)\r
-#define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */\r
-#define PWR_PUCRE_PE6_Pos            (6U)\r
-#define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */\r
-#define PWR_PUCRE_PE5_Pos            (5U)\r
-#define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */\r
-#define PWR_PUCRE_PE4_Pos            (4U)\r
-#define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */\r
-#define PWR_PUCRE_PE3_Pos            (3U)\r
-#define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */\r
-#define PWR_PUCRE_PE2_Pos            (2U)\r
-#define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */\r
-#define PWR_PUCRE_PE1_Pos            (1U)\r
-#define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */\r
-#define PWR_PUCRE_PE0_Pos            (0U)\r
-#define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRE register  ********************/\r
-#define PWR_PDCRE_PE15_Pos           (15U)\r
-#define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */\r
-#define PWR_PDCRE_PE14_Pos           (14U)\r
-#define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */\r
-#define PWR_PDCRE_PE13_Pos           (13U)\r
-#define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */\r
-#define PWR_PDCRE_PE12_Pos           (12U)\r
-#define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */\r
-#define PWR_PDCRE_PE11_Pos           (11U)\r
-#define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */\r
-#define PWR_PDCRE_PE10_Pos           (10U)\r
-#define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */\r
-#define PWR_PDCRE_PE9_Pos            (9U)\r
-#define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */\r
-#define PWR_PDCRE_PE8_Pos            (8U)\r
-#define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */\r
-#define PWR_PDCRE_PE7_Pos            (7U)\r
-#define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */\r
-#define PWR_PDCRE_PE6_Pos            (6U)\r
-#define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */\r
-#define PWR_PDCRE_PE5_Pos            (5U)\r
-#define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */\r
-#define PWR_PDCRE_PE4_Pos            (4U)\r
-#define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */\r
-#define PWR_PDCRE_PE3_Pos            (3U)\r
-#define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */\r
-#define PWR_PDCRE_PE2_Pos            (2U)\r
-#define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */\r
-#define PWR_PDCRE_PE1_Pos            (1U)\r
-#define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */\r
-#define PWR_PDCRE_PE0_Pos            (0U)\r
-#define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */\r
-\r
-/********************  Bit definition for PWR_PUCRF register  ********************/\r
-#define PWR_PUCRF_PF15_Pos           (15U)\r
-#define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */\r
-#define PWR_PUCRF_PF14_Pos           (14U)\r
-#define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */\r
-#define PWR_PUCRF_PF13_Pos           (13U)\r
-#define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */\r
-#define PWR_PUCRF_PF12_Pos           (12U)\r
-#define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */\r
-#define PWR_PUCRF_PF11_Pos           (11U)\r
-#define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */\r
-#define PWR_PUCRF_PF10_Pos           (10U)\r
-#define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */\r
-#define PWR_PUCRF_PF9_Pos            (9U)\r
-#define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */\r
-#define PWR_PUCRF_PF8_Pos            (8U)\r
-#define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */\r
-#define PWR_PUCRF_PF7_Pos            (7U)\r
-#define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */\r
-#define PWR_PUCRF_PF6_Pos            (6U)\r
-#define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */\r
-#define PWR_PUCRF_PF5_Pos            (5U)\r
-#define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */\r
-#define PWR_PUCRF_PF4_Pos            (4U)\r
-#define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */\r
-#define PWR_PUCRF_PF3_Pos            (3U)\r
-#define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */\r
-#define PWR_PUCRF_PF2_Pos            (2U)\r
-#define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */\r
-#define PWR_PUCRF_PF1_Pos            (1U)\r
-#define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */\r
-#define PWR_PUCRF_PF0_Pos            (0U)\r
-#define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRF register  ********************/\r
-#define PWR_PDCRF_PF15_Pos           (15U)\r
-#define PWR_PDCRF_PF15_Msk           (0x1UL << PWR_PDCRF_PF15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */\r
-#define PWR_PDCRF_PF14_Pos           (14U)\r
-#define PWR_PDCRF_PF14_Msk           (0x1UL << PWR_PDCRF_PF14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */\r
-#define PWR_PDCRF_PF13_Pos           (13U)\r
-#define PWR_PDCRF_PF13_Msk           (0x1UL << PWR_PDCRF_PF13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */\r
-#define PWR_PDCRF_PF12_Pos           (12U)\r
-#define PWR_PDCRF_PF12_Msk           (0x1UL << PWR_PDCRF_PF12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */\r
-#define PWR_PDCRF_PF11_Pos           (11U)\r
-#define PWR_PDCRF_PF11_Msk           (0x1UL << PWR_PDCRF_PF11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */\r
-#define PWR_PDCRF_PF10_Pos           (10U)\r
-#define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */\r
-#define PWR_PDCRF_PF9_Pos            (9U)\r
-#define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */\r
-#define PWR_PDCRF_PF8_Pos            (8U)\r
-#define PWR_PDCRF_PF8_Msk            (0x1UL << PWR_PDCRF_PF8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */\r
-#define PWR_PDCRF_PF7_Pos            (7U)\r
-#define PWR_PDCRF_PF7_Msk            (0x1UL << PWR_PDCRF_PF7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */\r
-#define PWR_PDCRF_PF6_Pos            (6U)\r
-#define PWR_PDCRF_PF6_Msk            (0x1UL << PWR_PDCRF_PF6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */\r
-#define PWR_PDCRF_PF5_Pos            (5U)\r
-#define PWR_PDCRF_PF5_Msk            (0x1UL << PWR_PDCRF_PF5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */\r
-#define PWR_PDCRF_PF4_Pos            (4U)\r
-#define PWR_PDCRF_PF4_Msk            (0x1UL << PWR_PDCRF_PF4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */\r
-#define PWR_PDCRF_PF3_Pos            (3U)\r
-#define PWR_PDCRF_PF3_Msk            (0x1UL << PWR_PDCRF_PF3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */\r
-#define PWR_PDCRF_PF2_Pos            (2U)\r
-#define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */\r
-#define PWR_PDCRF_PF1_Pos            (1U)\r
-#define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */\r
-#define PWR_PDCRF_PF0_Pos            (0U)\r
-#define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */\r
-\r
-/********************  Bit definition for PWR_PUCRG register  ********************/\r
-#define PWR_PUCRG_PG15_Pos           (15U)\r
-#define PWR_PUCRG_PG15_Msk           (0x1UL << PWR_PUCRG_PG15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */\r
-#define PWR_PUCRG_PG14_Pos           (14U)\r
-#define PWR_PUCRG_PG14_Msk           (0x1UL << PWR_PUCRG_PG14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */\r
-#define PWR_PUCRG_PG13_Pos           (13U)\r
-#define PWR_PUCRG_PG13_Msk           (0x1UL << PWR_PUCRG_PG13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */\r
-#define PWR_PUCRG_PG12_Pos           (12U)\r
-#define PWR_PUCRG_PG12_Msk           (0x1UL << PWR_PUCRG_PG12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */\r
-#define PWR_PUCRG_PG11_Pos           (11U)\r
-#define PWR_PUCRG_PG11_Msk           (0x1UL << PWR_PUCRG_PG11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */\r
-#define PWR_PUCRG_PG10_Pos           (10U)\r
-#define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */\r
-#define PWR_PUCRG_PG9_Pos            (9U)\r
-#define PWR_PUCRG_PG9_Msk            (0x1UL << PWR_PUCRG_PG9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */\r
-#define PWR_PUCRG_PG8_Pos            (8U)\r
-#define PWR_PUCRG_PG8_Msk            (0x1UL << PWR_PUCRG_PG8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */\r
-#define PWR_PUCRG_PG7_Pos            (7U)\r
-#define PWR_PUCRG_PG7_Msk            (0x1UL << PWR_PUCRG_PG7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */\r
-#define PWR_PUCRG_PG6_Pos            (6U)\r
-#define PWR_PUCRG_PG6_Msk            (0x1UL << PWR_PUCRG_PG6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */\r
-#define PWR_PUCRG_PG5_Pos            (5U)\r
-#define PWR_PUCRG_PG5_Msk            (0x1UL << PWR_PUCRG_PG5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */\r
-#define PWR_PUCRG_PG4_Pos            (4U)\r
-#define PWR_PUCRG_PG4_Msk            (0x1UL << PWR_PUCRG_PG4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */\r
-#define PWR_PUCRG_PG3_Pos            (3U)\r
-#define PWR_PUCRG_PG3_Msk            (0x1UL << PWR_PUCRG_PG3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */\r
-#define PWR_PUCRG_PG2_Pos            (2U)\r
-#define PWR_PUCRG_PG2_Msk            (0x1UL << PWR_PUCRG_PG2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */\r
-#define PWR_PUCRG_PG1_Pos            (1U)\r
-#define PWR_PUCRG_PG1_Msk            (0x1UL << PWR_PUCRG_PG1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */\r
-#define PWR_PUCRG_PG0_Pos            (0U)\r
-#define PWR_PUCRG_PG0_Msk            (0x1UL << PWR_PUCRG_PG0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRG register  ********************/\r
-#define PWR_PDCRG_PG15_Pos           (15U)\r
-#define PWR_PDCRG_PG15_Msk           (0x1UL << PWR_PDCRG_PG15_Pos)             /*!< 0x00008000 */\r
-#define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */\r
-#define PWR_PDCRG_PG14_Pos           (14U)\r
-#define PWR_PDCRG_PG14_Msk           (0x1UL << PWR_PDCRG_PG14_Pos)             /*!< 0x00004000 */\r
-#define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */\r
-#define PWR_PDCRG_PG13_Pos           (13U)\r
-#define PWR_PDCRG_PG13_Msk           (0x1UL << PWR_PDCRG_PG13_Pos)             /*!< 0x00002000 */\r
-#define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */\r
-#define PWR_PDCRG_PG12_Pos           (12U)\r
-#define PWR_PDCRG_PG12_Msk           (0x1UL << PWR_PDCRG_PG12_Pos)             /*!< 0x00001000 */\r
-#define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */\r
-#define PWR_PDCRG_PG11_Pos           (11U)\r
-#define PWR_PDCRG_PG11_Msk           (0x1UL << PWR_PDCRG_PG11_Pos)             /*!< 0x00000800 */\r
-#define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */\r
-#define PWR_PDCRG_PG10_Pos           (10U)\r
-#define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */\r
-#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */\r
-#define PWR_PDCRG_PG9_Pos            (9U)\r
-#define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */\r
-#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */\r
-#define PWR_PDCRG_PG8_Pos            (8U)\r
-#define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */\r
-#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */\r
-#define PWR_PDCRG_PG7_Pos            (7U)\r
-#define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */\r
-#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */\r
-#define PWR_PDCRG_PG6_Pos            (6U)\r
-#define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */\r
-#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */\r
-#define PWR_PDCRG_PG5_Pos            (5U)\r
-#define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */\r
-#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */\r
-#define PWR_PDCRG_PG4_Pos            (4U)\r
-#define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */\r
-#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */\r
-#define PWR_PDCRG_PG3_Pos            (3U)\r
-#define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */\r
-#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */\r
-#define PWR_PDCRG_PG2_Pos            (2U)\r
-#define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */\r
-#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */\r
-#define PWR_PDCRG_PG1_Pos            (1U)\r
-#define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */\r
-#define PWR_PDCRG_PG0_Pos            (0U)\r
-#define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */\r
-\r
-/********************  Bit definition for PWR_PUCRH register  ********************/\r
-#define PWR_PUCRH_PH1_Pos            (1U)\r
-#define PWR_PUCRH_PH1_Msk            (0x1UL << PWR_PUCRH_PH1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */\r
-#define PWR_PUCRH_PH0_Pos            (0U)\r
-#define PWR_PUCRH_PH0_Msk            (0x1UL << PWR_PUCRH_PH0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */\r
-\r
-/********************  Bit definition for PWR_PDCRH register  ********************/\r
-#define PWR_PDCRH_PH1_Pos            (1U)\r
-#define PWR_PDCRH_PH1_Msk            (0x1UL << PWR_PDCRH_PH1_Pos)              /*!< 0x00000002 */\r
-#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */\r
-#define PWR_PDCRH_PH0_Pos            (0U)\r
-#define PWR_PDCRH_PH0_Msk            (0x1UL << PWR_PDCRH_PH0_Pos)              /*!< 0x00000001 */\r
-#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */\r
-\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                         Reset and Clock Control                            */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*\r
-* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)\r
-*/\r
-#define RCC_PLLSAI1_SUPPORT\r
-#define RCC_PLLP_SUPPORT\r
-#define RCC_PLLSAI2_SUPPORT\r
-\r
-/********************  Bit definition for RCC_CR register  ********************/\r
-#define RCC_CR_MSION_Pos                     (0U)\r
-#define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */\r
-#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */\r
-#define RCC_CR_MSIRDY_Pos                    (1U)\r
-#define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */\r
-#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */\r
-#define RCC_CR_MSIPLLEN_Pos                  (2U)\r
-#define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */\r
-#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */\r
-#define RCC_CR_MSIRGSEL_Pos                  (3U)\r
-#define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */\r
-#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */\r
-\r
-/*!< MSIRANGE configuration : 12 frequency ranges available */\r
-#define RCC_CR_MSIRANGE_Pos                  (4U)\r
-#define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */\r
-#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */\r
-#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */\r
-#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */\r
-#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */\r
-#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */\r
-#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */\r
-#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */\r
-#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */\r
-#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */\r
-#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */\r
-#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */\r
-#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */\r
-#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */\r
-\r
-#define RCC_CR_HSION_Pos                     (8U)\r
-#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */\r
-#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */\r
-#define RCC_CR_HSIKERON_Pos                  (9U)\r
-#define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */\r
-#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */\r
-#define RCC_CR_HSIRDY_Pos                    (10U)\r
-#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */\r
-#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */\r
-#define RCC_CR_HSIASFS_Pos                   (11U)\r
-#define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */\r
-#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */\r
-\r
-#define RCC_CR_HSEON_Pos                     (16U)\r
-#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */\r
-#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */\r
-#define RCC_CR_HSERDY_Pos                    (17U)\r
-#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */\r
-#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */\r
-#define RCC_CR_HSEBYP_Pos                    (18U)\r
-#define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */\r
-#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */\r
-#define RCC_CR_CSSON_Pos                     (19U)\r
-#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */\r
-#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */\r
-\r
-#define RCC_CR_PLLON_Pos                     (24U)\r
-#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */\r
-#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */\r
-#define RCC_CR_PLLRDY_Pos                    (25U)\r
-#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */\r
-#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */\r
-#define RCC_CR_PLLSAI1ON_Pos                 (26U)\r
-#define RCC_CR_PLLSAI1ON_Msk                 (0x1UL << RCC_CR_PLLSAI1ON_Pos)   /*!< 0x04000000 */\r
-#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */\r
-#define RCC_CR_PLLSAI1RDY_Pos                (27U)\r
-#define RCC_CR_PLLSAI1RDY_Msk                (0x1UL << RCC_CR_PLLSAI1RDY_Pos)  /*!< 0x08000000 */\r
-#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */\r
-#define RCC_CR_PLLSAI2ON_Pos                 (28U)\r
-#define RCC_CR_PLLSAI2ON_Msk                 (0x1UL << RCC_CR_PLLSAI2ON_Pos)   /*!< 0x10000000 */\r
-#define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */\r
-#define RCC_CR_PLLSAI2RDY_Pos                (29U)\r
-#define RCC_CR_PLLSAI2RDY_Msk                (0x1UL << RCC_CR_PLLSAI2RDY_Pos)  /*!< 0x20000000 */\r
-#define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */\r
-\r
-/********************  Bit definition for RCC_ICSCR register  ***************/\r
-/*!< MSICAL configuration */\r
-#define RCC_ICSCR_MSICAL_Pos                 (0U)\r
-#define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */\r
-#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */\r
-#define RCC_ICSCR_MSICAL_0                   (0x01UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000001 */\r
-#define RCC_ICSCR_MSICAL_1                   (0x02UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000002 */\r
-#define RCC_ICSCR_MSICAL_2                   (0x04UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000004 */\r
-#define RCC_ICSCR_MSICAL_3                   (0x08UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000008 */\r
-#define RCC_ICSCR_MSICAL_4                   (0x10UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000010 */\r
-#define RCC_ICSCR_MSICAL_5                   (0x20UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000020 */\r
-#define RCC_ICSCR_MSICAL_6                   (0x40UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000040 */\r
-#define RCC_ICSCR_MSICAL_7                   (0x80UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000080 */\r
-\r
-/*!< MSITRIM configuration */\r
-#define RCC_ICSCR_MSITRIM_Pos                (8U)\r
-#define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */\r
-#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */\r
-#define RCC_ICSCR_MSITRIM_0                  (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */\r
-#define RCC_ICSCR_MSITRIM_1                  (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */\r
-#define RCC_ICSCR_MSITRIM_2                  (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */\r
-#define RCC_ICSCR_MSITRIM_3                  (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */\r
-#define RCC_ICSCR_MSITRIM_4                  (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */\r
-#define RCC_ICSCR_MSITRIM_5                  (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */\r
-#define RCC_ICSCR_MSITRIM_6                  (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */\r
-#define RCC_ICSCR_MSITRIM_7                  (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */\r
-\r
-/*!< HSICAL configuration */\r
-#define RCC_ICSCR_HSICAL_Pos                 (16U)\r
-#define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */\r
-#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */\r
-#define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */\r
-#define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */\r
-#define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */\r
-#define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */\r
-#define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */\r
-#define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */\r
-#define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */\r
-#define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */\r
-\r
-/*!< HSITRIM configuration */\r
-#define RCC_ICSCR_HSITRIM_Pos                (24U)\r
-#define RCC_ICSCR_HSITRIM_Msk                (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */\r
-#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */\r
-#define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */\r
-#define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */\r
-#define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */\r
-#define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */\r
-#define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */\r
-\r
-/********************  Bit definition for RCC_CFGR register  ******************/\r
-/*!< SW configuration */\r
-#define RCC_CFGR_SW_Pos                      (0U)\r
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */\r
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */\r
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */\r
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */\r
-\r
-#define RCC_CFGR_SW_MSI                      (0x00000000UL)                    /*!< MSI oscillator selection as system clock */\r
-#define RCC_CFGR_SW_HSI                      (0x00000001UL)                    /*!< HSI16 oscillator selection as system clock */\r
-#define RCC_CFGR_SW_HSE                      (0x00000002UL)                    /*!< HSE oscillator selection as system clock */\r
-#define RCC_CFGR_SW_PLL                      (0x00000003UL)                    /*!< PLL selection as system clock */\r
-\r
-/*!< SWS configuration */\r
-#define RCC_CFGR_SWS_Pos                     (2U)\r
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */\r
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */\r
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */\r
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */\r
-\r
-#define RCC_CFGR_SWS_MSI                     (0x00000000UL)                    /*!< MSI oscillator used as system clock */\r
-#define RCC_CFGR_SWS_HSI                     (0x00000004UL)                    /*!< HSI16 oscillator used as system clock */\r
-#define RCC_CFGR_SWS_HSE                     (0x00000008UL)                    /*!< HSE oscillator used as system clock */\r
-#define RCC_CFGR_SWS_PLL                     (0x0000000CUL)                    /*!< PLL used as system clock */\r
-\r
-/*!< HPRE configuration */\r
-#define RCC_CFGR_HPRE_Pos                    (4U)\r
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */\r
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */\r
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */\r
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */\r
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */\r
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */\r
-\r
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000UL)                    /*!< SYSCLK not divided */\r
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080UL)                    /*!< SYSCLK divided by 2 */\r
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090UL)                    /*!< SYSCLK divided by 4 */\r
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0UL)                    /*!< SYSCLK divided by 8 */\r
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0UL)                    /*!< SYSCLK divided by 16 */\r
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0UL)                    /*!< SYSCLK divided by 64 */\r
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0UL)                    /*!< SYSCLK divided by 128 */\r
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0UL)                    /*!< SYSCLK divided by 256 */\r
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0UL)                    /*!< SYSCLK divided by 512 */\r
-\r
-/*!< PPRE1 configuration */\r
-#define RCC_CFGR_PPRE1_Pos                   (8U)\r
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */\r
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */\r
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */\r
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */\r
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */\r
-\r
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400UL)                    /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500UL)                    /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600UL)                    /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700UL)                    /*!< HCLK divided by 16 */\r
-\r
-/*!< PPRE2 configuration */\r
-#define RCC_CFGR_PPRE2_Pos                   (11U)\r
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */\r
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */\r
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */\r
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */\r
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */\r
-\r
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000UL)                    /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800UL)                    /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000UL)                    /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800UL)                    /*!< HCLK divided by 16 */\r
-\r
-#define RCC_CFGR_STOPWUCK_Pos                (15U)\r
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */\r
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */\r
-\r
-/*!< MCOSEL configuration */\r
-#define RCC_CFGR_MCOSEL_Pos                  (24U)\r
-#define RCC_CFGR_MCOSEL_Msk                  (0x7UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x07000000 */\r
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [2:0] bits (Clock output selection) */\r
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */\r
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */\r
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */\r
-\r
-#define RCC_CFGR_MCOPRE_Pos                  (28U)\r
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */\r
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */\r
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */\r
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */\r
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */\r
-\r
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000UL)                    /*!< MCO is divided by 1 */\r
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000UL)                    /*!< MCO is divided by 2 */\r
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000UL)                    /*!< MCO is divided by 4 */\r
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000UL)                    /*!< MCO is divided by 8 */\r
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000UL)                    /*!< MCO is divided by 16 */\r
-\r
-/* Legacy aliases */\r
-#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE\r
-#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1\r
-#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2\r
-#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4\r
-#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8\r
-#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16\r
-\r
-/********************  Bit definition for RCC_PLLCFGR register  ***************/\r
-#define RCC_PLLCFGR_PLLSRC_Pos               (0U)\r
-#define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */\r
-#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk\r
-\r
-#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)\r
-#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */\r
-#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */\r
-#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)\r
-#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */\r
-#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */\r
-#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)\r
-#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */\r
-#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */\r
-\r
-#define RCC_PLLCFGR_PLLM_Pos                 (4U)\r
-#define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000070 */\r
-#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk\r
-#define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */\r
-#define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */\r
-#define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */\r
-\r
-#define RCC_PLLCFGR_PLLN_Pos                 (8U)\r
-#define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */\r
-#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk\r
-#define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */\r
-#define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */\r
-#define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */\r
-#define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */\r
-#define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */\r
-#define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */\r
-#define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */\r
-\r
-#define RCC_PLLCFGR_PLLPEN_Pos               (16U)\r
-#define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */\r
-#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk\r
-#define RCC_PLLCFGR_PLLP_Pos                 (17U)\r
-#define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */\r
-#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk\r
-#define RCC_PLLCFGR_PLLQEN_Pos               (20U)\r
-#define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */\r
-#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk\r
-\r
-#define RCC_PLLCFGR_PLLQ_Pos                 (21U)\r
-#define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */\r
-#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk\r
-#define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */\r
-#define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */\r
-\r
-#define RCC_PLLCFGR_PLLREN_Pos               (24U)\r
-#define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */\r
-#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk\r
-#define RCC_PLLCFGR_PLLR_Pos                 (25U)\r
-#define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */\r
-#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk\r
-#define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */\r
-#define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */\r
-\r
-/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */\r
-\r
-#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)\r
-#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk\r
-#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)\r
-#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk\r
-\r
-#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)\r
-#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk\r
-#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)\r
-#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk\r
-#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */\r
-\r
-#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)\r
-#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk\r
-#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)\r
-#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk\r
-#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */\r
-#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */\r
-\r
-/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FUL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */\r
-\r
-#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)\r
-#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk\r
-#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)\r
-#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk\r
-\r
-#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)\r
-#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk\r
-#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)\r
-#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk\r
-#define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */\r
-#define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */\r
-\r
-/********************  Bit definition for RCC_CIER register  ******************/\r
-#define RCC_CIER_LSIRDYIE_Pos                (0U)\r
-#define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */\r
-#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk\r
-#define RCC_CIER_LSERDYIE_Pos                (1U)\r
-#define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */\r
-#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk\r
-#define RCC_CIER_MSIRDYIE_Pos                (2U)\r
-#define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)  /*!< 0x00000004 */\r
-#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk\r
-#define RCC_CIER_HSIRDYIE_Pos                (3U)\r
-#define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */\r
-#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk\r
-#define RCC_CIER_HSERDYIE_Pos                (4U)\r
-#define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */\r
-#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk\r
-#define RCC_CIER_PLLRDYIE_Pos                (5U)\r
-#define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */\r
-#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk\r
-#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)\r
-#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */\r
-#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk\r
-#define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)\r
-#define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1UL << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */\r
-#define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk\r
-#define RCC_CIER_LSECSSIE_Pos                (9U)\r
-#define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */\r
-#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk\r
-\r
-/********************  Bit definition for RCC_CIFR register  ******************/\r
-#define RCC_CIFR_LSIRDYF_Pos                 (0U)\r
-#define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */\r
-#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk\r
-#define RCC_CIFR_LSERDYF_Pos                 (1U)\r
-#define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */\r
-#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk\r
-#define RCC_CIFR_MSIRDYF_Pos                 (2U)\r
-#define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */\r
-#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk\r
-#define RCC_CIFR_HSIRDYF_Pos                 (3U)\r
-#define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */\r
-#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk\r
-#define RCC_CIFR_HSERDYF_Pos                 (4U)\r
-#define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */\r
-#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk\r
-#define RCC_CIFR_PLLRDYF_Pos                 (5U)\r
-#define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */\r
-#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk\r
-#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)\r
-#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */\r
-#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk\r
-#define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)\r
-#define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1UL << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */\r
-#define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk\r
-#define RCC_CIFR_CSSF_Pos                    (8U)\r
-#define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */\r
-#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk\r
-#define RCC_CIFR_LSECSSF_Pos                 (9U)\r
-#define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */\r
-#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk\r
-\r
-/********************  Bit definition for RCC_CICR register  ******************/\r
-#define RCC_CICR_LSIRDYC_Pos                 (0U)\r
-#define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */\r
-#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk\r
-#define RCC_CICR_LSERDYC_Pos                 (1U)\r
-#define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */\r
-#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk\r
-#define RCC_CICR_MSIRDYC_Pos                 (2U)\r
-#define RCC_CICR_MSIRDYC_Msk                 (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */\r
-#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk\r
-#define RCC_CICR_HSIRDYC_Pos                 (3U)\r
-#define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */\r
-#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk\r
-#define RCC_CICR_HSERDYC_Pos                 (4U)\r
-#define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */\r
-#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk\r
-#define RCC_CICR_PLLRDYC_Pos                 (5U)\r
-#define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */\r
-#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk\r
-#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)\r
-#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */\r
-#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk\r
-#define RCC_CICR_PLLSAI2RDYC_Pos             (7U)\r
-#define RCC_CICR_PLLSAI2RDYC_Msk             (0x1UL << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */\r
-#define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk\r
-#define RCC_CICR_CSSC_Pos                    (8U)\r
-#define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */\r
-#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk\r
-#define RCC_CICR_LSECSSC_Pos                 (9U)\r
-#define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */\r
-#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk\r
-\r
-/********************  Bit definition for RCC_AHB1RSTR register  **************/\r
-#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)\r
-#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk\r
-#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)\r
-#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */\r
-#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk\r
-#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)\r
-#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */\r
-#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk\r
-#define RCC_AHB1RSTR_CRCRST_Pos              (12U)\r
-#define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */\r
-#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk\r
-#define RCC_AHB1RSTR_TSCRST_Pos              (16U)\r
-#define RCC_AHB1RSTR_TSCRST_Msk              (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */\r
-#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk\r
-\r
-/********************  Bit definition for RCC_AHB2RSTR register  **************/\r
-#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)\r
-#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk\r
-#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)\r
-#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\r
-#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk\r
-#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)\r
-#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\r
-#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk\r
-#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)\r
-#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */\r
-#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk\r
-#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)\r
-#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */\r
-#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk\r
-#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)\r
-#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\r
-#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk\r
-#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)\r
-#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\r
-#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk\r
-#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)\r
-#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\r
-#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk\r
-#define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)\r
-#define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */\r
-#define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk\r
-#define RCC_AHB2RSTR_ADCRST_Pos              (13U)\r
-#define RCC_AHB2RSTR_ADCRST_Msk              (0x1UL << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */\r
-#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk\r
-#define RCC_AHB2RSTR_RNGRST_Pos              (18U)\r
-#define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */\r
-#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk\r
-\r
-/********************  Bit definition for RCC_AHB3RSTR register  **************/\r
-#define RCC_AHB3RSTR_FMCRST_Pos              (0U)\r
-#define RCC_AHB3RSTR_FMCRST_Msk              (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk\r
-#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)\r
-#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */\r
-#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk\r
-\r
-/********************  Bit definition for RCC_APB1RSTR1 register  **************/\r
-#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)\r
-#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk\r
-#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)\r
-#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */\r
-#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk\r
-#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)\r
-#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk\r
-#define RCC_APB1RSTR1_TIM5RST_Pos            (3U)\r
-#define RCC_APB1RSTR1_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */\r
-#define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk\r
-#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)\r
-#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */\r
-#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk\r
-#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)\r
-#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk\r
-#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)\r
-#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */\r
-#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk\r
-#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)\r
-#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */\r
-#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk\r
-#define RCC_APB1RSTR1_USART2RST_Pos          (17U)\r
-#define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */\r
-#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk\r
-#define RCC_APB1RSTR1_USART3RST_Pos          (18U)\r
-#define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */\r
-#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk\r
-#define RCC_APB1RSTR1_UART4RST_Pos           (19U)\r
-#define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */\r
-#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk\r
-#define RCC_APB1RSTR1_UART5RST_Pos           (20U)\r
-#define RCC_APB1RSTR1_UART5RST_Msk           (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */\r
-#define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk\r
-#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)\r
-#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */\r
-#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk\r
-#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)\r
-#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */\r
-#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk\r
-#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)\r
-#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */\r
-#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk\r
-#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)\r
-#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */\r
-#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk\r
-#define RCC_APB1RSTR1_PWRRST_Pos             (28U)\r
-#define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */\r
-#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk\r
-#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)\r
-#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */\r
-#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk\r
-#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)\r
-#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */\r
-#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk\r
-#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)\r
-#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */\r
-#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk\r
-\r
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/\r
-#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)\r
-#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk\r
-#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)\r
-#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk\r
-#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)\r
-#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk\r
-\r
-/********************  Bit definition for RCC_APB2RSTR register  **************/\r
-#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)\r
-#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */\r
-#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk\r
-#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)\r
-#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */\r
-#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk\r
-#define RCC_APB2RSTR_TIM1RST_Pos             (11U)\r
-#define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */\r
-#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk\r
-#define RCC_APB2RSTR_SPI1RST_Pos             (12U)\r
-#define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r
-#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk\r
-#define RCC_APB2RSTR_TIM8RST_Pos             (13U)\r
-#define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */\r
-#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk\r
-#define RCC_APB2RSTR_USART1RST_Pos           (14U)\r
-#define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */\r
-#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk\r
-#define RCC_APB2RSTR_TIM15RST_Pos            (16U)\r
-#define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */\r
-#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk\r
-#define RCC_APB2RSTR_TIM16RST_Pos            (17U)\r
-#define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */\r
-#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk\r
-#define RCC_APB2RSTR_TIM17RST_Pos            (18U)\r
-#define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */\r
-#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk\r
-#define RCC_APB2RSTR_SAI1RST_Pos             (21U)\r
-#define RCC_APB2RSTR_SAI1RST_Msk             (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */\r
-#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk\r
-#define RCC_APB2RSTR_SAI2RST_Pos             (22U)\r
-#define RCC_APB2RSTR_SAI2RST_Msk             (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */\r
-#define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk\r
-#define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)\r
-#define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */\r
-#define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk\r
-\r
-/********************  Bit definition for RCC_AHB1ENR register  ***************/\r
-#define RCC_AHB1ENR_DMA1EN_Pos               (0U)\r
-#define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk\r
-#define RCC_AHB1ENR_DMA2EN_Pos               (1U)\r
-#define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */\r
-#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk\r
-#define RCC_AHB1ENR_FLASHEN_Pos              (8U)\r
-#define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */\r
-#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk\r
-#define RCC_AHB1ENR_CRCEN_Pos                (12U)\r
-#define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */\r
-#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk\r
-#define RCC_AHB1ENR_TSCEN_Pos                (16U)\r
-#define RCC_AHB1ENR_TSCEN_Msk                (0x1UL << RCC_AHB1ENR_TSCEN_Pos)  /*!< 0x00010000 */\r
-#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk\r
-\r
-/********************  Bit definition for RCC_AHB2ENR register  ***************/\r
-#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)\r
-#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk\r
-#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)\r
-#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */\r
-#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk\r
-#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)\r
-#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */\r
-#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk\r
-#define RCC_AHB2ENR_GPIODEN_Pos              (3U)\r
-#define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */\r
-#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk\r
-#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)\r
-#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */\r
-#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk\r
-#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)\r
-#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */\r
-#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk\r
-#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)\r
-#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */\r
-#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk\r
-#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)\r
-#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */\r
-#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk\r
-#define RCC_AHB2ENR_OTGFSEN_Pos              (12U)\r
-#define RCC_AHB2ENR_OTGFSEN_Msk              (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */\r
-#define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk\r
-#define RCC_AHB2ENR_ADCEN_Pos                (13U)\r
-#define RCC_AHB2ENR_ADCEN_Msk                (0x1UL << RCC_AHB2ENR_ADCEN_Pos)  /*!< 0x00002000 */\r
-#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk\r
-#define RCC_AHB2ENR_RNGEN_Pos                (18U)\r
-#define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x00040000 */\r
-#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk\r
-\r
-/********************  Bit definition for RCC_AHB3ENR register  ***************/\r
-#define RCC_AHB3ENR_FMCEN_Pos                (0U)\r
-#define RCC_AHB3ENR_FMCEN_Msk                (0x1UL << RCC_AHB3ENR_FMCEN_Pos)  /*!< 0x00000001 */\r
-#define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk\r
-#define RCC_AHB3ENR_QSPIEN_Pos               (8U)\r
-#define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */\r
-#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk\r
-\r
-/********************  Bit definition for RCC_APB1ENR1 register  ***************/\r
-#define RCC_APB1ENR1_TIM2EN_Pos              (0U)\r
-#define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk\r
-#define RCC_APB1ENR1_TIM3EN_Pos              (1U)\r
-#define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */\r
-#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk\r
-#define RCC_APB1ENR1_TIM4EN_Pos              (2U)\r
-#define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk\r
-#define RCC_APB1ENR1_TIM5EN_Pos              (3U)\r
-#define RCC_APB1ENR1_TIM5EN_Msk              (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */\r
-#define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk\r
-#define RCC_APB1ENR1_TIM6EN_Pos              (4U)\r
-#define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */\r
-#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk\r
-#define RCC_APB1ENR1_TIM7EN_Pos              (5U)\r
-#define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk\r
-#define RCC_APB1ENR1_WWDGEN_Pos              (11U)\r
-#define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */\r
-#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk\r
-#define RCC_APB1ENR1_SPI2EN_Pos              (14U)\r
-#define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */\r
-#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk\r
-#define RCC_APB1ENR1_SPI3EN_Pos              (15U)\r
-#define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */\r
-#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk\r
-#define RCC_APB1ENR1_USART2EN_Pos            (17U)\r
-#define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */\r
-#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk\r
-#define RCC_APB1ENR1_USART3EN_Pos            (18U)\r
-#define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */\r
-#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk\r
-#define RCC_APB1ENR1_UART4EN_Pos             (19U)\r
-#define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */\r
-#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk\r
-#define RCC_APB1ENR1_UART5EN_Pos             (20U)\r
-#define RCC_APB1ENR1_UART5EN_Msk             (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */\r
-#define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk\r
-#define RCC_APB1ENR1_I2C1EN_Pos              (21U)\r
-#define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */\r
-#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk\r
-#define RCC_APB1ENR1_I2C2EN_Pos              (22U)\r
-#define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */\r
-#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk\r
-#define RCC_APB1ENR1_I2C3EN_Pos              (23U)\r
-#define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */\r
-#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk\r
-#define RCC_APB1ENR1_CAN1EN_Pos              (25U)\r
-#define RCC_APB1ENR1_CAN1EN_Msk              (0x1UL << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */\r
-#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk\r
-#define RCC_APB1ENR1_PWREN_Pos               (28U)\r
-#define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */\r
-#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk\r
-#define RCC_APB1ENR1_DAC1EN_Pos              (29U)\r
-#define RCC_APB1ENR1_DAC1EN_Msk              (0x1UL << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */\r
-#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk\r
-#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)\r
-#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */\r
-#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk\r
-#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)\r
-#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */\r
-#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk\r
-\r
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/\r
-#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)\r
-#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk\r
-#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)\r
-#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk\r
-#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)\r
-#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk\r
-\r
-/********************  Bit definition for RCC_APB2ENR register  ***************/\r
-#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)\r
-#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk\r
-#define RCC_APB2ENR_FWEN_Pos                 (7U)\r
-#define RCC_APB2ENR_FWEN_Msk                 (0x1UL << RCC_APB2ENR_FWEN_Pos)   /*!< 0x00000080 */\r
-#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk\r
-#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)\r
-#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */\r
-#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk\r
-#define RCC_APB2ENR_TIM1EN_Pos               (11U)\r
-#define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */\r
-#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk\r
-#define RCC_APB2ENR_SPI1EN_Pos               (12U)\r
-#define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r
-#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk\r
-#define RCC_APB2ENR_TIM8EN_Pos               (13U)\r
-#define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */\r
-#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk\r
-#define RCC_APB2ENR_USART1EN_Pos             (14U)\r
-#define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */\r
-#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk\r
-#define RCC_APB2ENR_TIM15EN_Pos              (16U)\r
-#define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */\r
-#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk\r
-#define RCC_APB2ENR_TIM16EN_Pos              (17U)\r
-#define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */\r
-#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk\r
-#define RCC_APB2ENR_TIM17EN_Pos              (18U)\r
-#define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */\r
-#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk\r
-#define RCC_APB2ENR_SAI1EN_Pos               (21U)\r
-#define RCC_APB2ENR_SAI1EN_Msk               (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */\r
-#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk\r
-#define RCC_APB2ENR_SAI2EN_Pos               (22U)\r
-#define RCC_APB2ENR_SAI2EN_Msk               (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */\r
-#define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk\r
-#define RCC_APB2ENR_DFSDM1EN_Pos             (24U)\r
-#define RCC_APB2ENR_DFSDM1EN_Msk             (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */\r
-#define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk\r
-\r
-/********************  Bit definition for RCC_AHB1SMENR register  ***************/\r
-#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)\r
-#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk\r
-#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)\r
-#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */\r
-#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk\r
-#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)\r
-#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */\r
-#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk\r
-#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)\r
-#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */\r
-#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk\r
-#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)\r
-#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */\r
-#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk\r
-#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)\r
-#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */\r
-#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk\r
-\r
-/********************  Bit definition for RCC_AHB2SMENR register  *************/\r
-#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)\r
-#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk\r
-#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)\r
-#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */\r
-#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk\r
-#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)\r
-#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */\r
-#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk\r
-#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)\r
-#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */\r
-#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk\r
-#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)\r
-#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */\r
-#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk\r
-#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)\r
-#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */\r
-#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk\r
-#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)\r
-#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */\r
-#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk\r
-#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)\r
-#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */\r
-#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk\r
-#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)\r
-#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */\r
-#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk\r
-#define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)\r
-#define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1UL << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */\r
-#define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk\r
-#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)\r
-#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */\r
-#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk\r
-#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)\r
-#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */\r
-#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk\r
-\r
-/********************  Bit definition for RCC_AHB3SMENR register  *************/\r
-#define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)\r
-#define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */\r
-#define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk\r
-#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)\r
-#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */\r
-#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk\r
-\r
-/********************  Bit definition for RCC_APB1SMENR1 register  *************/\r
-#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)\r
-#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk\r
-#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)\r
-#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */\r
-#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk\r
-#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)\r
-#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk\r
-#define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)\r
-#define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */\r
-#define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk\r
-#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)\r
-#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */\r
-#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk\r
-#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)\r
-#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk\r
-#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)\r
-#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */\r
-#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk\r
-#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)\r
-#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */\r
-#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk\r
-#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)\r
-#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */\r
-#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk\r
-#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)\r
-#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */\r
-#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk\r
-#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)\r
-#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */\r
-#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk\r
-#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)\r
-#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */\r
-#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk\r
-#define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)\r
-#define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */\r
-#define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk\r
-#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)\r
-#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */\r
-#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk\r
-#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)\r
-#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */\r
-#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk\r
-#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)\r
-#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */\r
-#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk\r
-#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)\r
-#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */\r
-#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk\r
-#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)\r
-#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */\r
-#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk\r
-#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)\r
-#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */\r
-#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk\r
-#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)\r
-#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */\r
-#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk\r
-#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)\r
-#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */\r
-#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk\r
-\r
-/********************  Bit definition for RCC_APB1SMENR2 register  *************/\r
-#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)\r
-#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk\r
-#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)\r
-#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk\r
-#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)\r
-#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk\r
-\r
-/********************  Bit definition for RCC_APB2SMENR register  *************/\r
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)\r
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk\r
-#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)\r
-#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1UL << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */\r
-#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk\r
-#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)\r
-#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */\r
-#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk\r
-#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)\r
-#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */\r
-#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk\r
-#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)\r
-#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */\r
-#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk\r
-#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)\r
-#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */\r
-#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk\r
-#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)\r
-#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */\r
-#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk\r
-#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)\r
-#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */\r
-#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk\r
-#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)\r
-#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */\r
-#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk\r
-#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)\r
-#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */\r
-#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk\r
-#define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)\r
-#define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */\r
-#define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk\r
-#define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)\r
-#define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1UL << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */\r
-#define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk\r
-\r
-/********************  Bit definition for RCC_CCIPR register  ******************/\r
-#define RCC_CCIPR_USART1SEL_Pos              (0U)\r
-#define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */\r
-#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk\r
-#define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */\r
-#define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */\r
-\r
-#define RCC_CCIPR_USART2SEL_Pos              (2U)\r
-#define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */\r
-#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk\r
-#define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */\r
-#define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */\r
-\r
-#define RCC_CCIPR_USART3SEL_Pos              (4U)\r
-#define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */\r
-#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk\r
-#define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */\r
-#define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */\r
-\r
-#define RCC_CCIPR_UART4SEL_Pos               (6U)\r
-#define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */\r
-#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk\r
-#define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */\r
-#define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */\r
-\r
-#define RCC_CCIPR_UART5SEL_Pos               (8U)\r
-#define RCC_CCIPR_UART5SEL_Msk               (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */\r
-#define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk\r
-#define RCC_CCIPR_UART5SEL_0                 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */\r
-#define RCC_CCIPR_UART5SEL_1                 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */\r
-\r
-#define RCC_CCIPR_LPUART1SEL_Pos             (10U)\r
-#define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */\r
-#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk\r
-#define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */\r
-#define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */\r
-\r
-#define RCC_CCIPR_I2C1SEL_Pos                (12U)\r
-#define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */\r
-#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk\r
-#define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */\r
-#define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */\r
-\r
-#define RCC_CCIPR_I2C2SEL_Pos                (14U)\r
-#define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */\r
-#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk\r
-#define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */\r
-#define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */\r
-\r
-#define RCC_CCIPR_I2C3SEL_Pos                (16U)\r
-#define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */\r
-#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk\r
-#define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */\r
-#define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */\r
-\r
-#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)\r
-#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */\r
-#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk\r
-#define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */\r
-#define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */\r
-\r
-#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)\r
-#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */\r
-#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk\r
-#define RCC_CCIPR_LPTIM2SEL_0                (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */\r
-#define RCC_CCIPR_LPTIM2SEL_1                (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */\r
-\r
-#define RCC_CCIPR_SAI1SEL_Pos                (22U)\r
-#define RCC_CCIPR_SAI1SEL_Msk                (0x3UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00C00000 */\r
-#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk\r
-#define RCC_CCIPR_SAI1SEL_0                  (0x1UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00400000 */\r
-#define RCC_CCIPR_SAI1SEL_1                  (0x2UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00800000 */\r
-\r
-#define RCC_CCIPR_SAI2SEL_Pos                (24U)\r
-#define RCC_CCIPR_SAI2SEL_Msk                (0x3UL << RCC_CCIPR_SAI2SEL_Pos)  /*!< 0x03000000 */\r
-#define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk\r
-#define RCC_CCIPR_SAI2SEL_0                  (0x1UL << RCC_CCIPR_SAI2SEL_Pos)  /*!< 0x01000000 */\r
-#define RCC_CCIPR_SAI2SEL_1                  (0x2UL << RCC_CCIPR_SAI2SEL_Pos)  /*!< 0x02000000 */\r
-\r
-#define RCC_CCIPR_CLK48SEL_Pos               (26U)\r
-#define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */\r
-#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk\r
-#define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */\r
-#define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */\r
-\r
-#define RCC_CCIPR_ADCSEL_Pos                 (28U)\r
-#define RCC_CCIPR_ADCSEL_Msk                 (0x3UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x30000000 */\r
-#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk\r
-#define RCC_CCIPR_ADCSEL_0                   (0x1UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x10000000 */\r
-#define RCC_CCIPR_ADCSEL_1                   (0x2UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x20000000 */\r
-\r
-#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)\r
-#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */\r
-#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk\r
-\r
-#define RCC_CCIPR_DFSDM1SEL_Pos              (31U)\r
-#define RCC_CCIPR_DFSDM1SEL_Msk              (0x1UL << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */\r
-#define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk\r
-\r
-/********************  Bit definition for RCC_BDCR register  ******************/\r
-#define RCC_BDCR_LSEON_Pos                   (0U)\r
-#define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */\r
-#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk\r
-#define RCC_BDCR_LSERDY_Pos                  (1U)\r
-#define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */\r
-#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk\r
-#define RCC_BDCR_LSEBYP_Pos                  (2U)\r
-#define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */\r
-#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk\r
-\r
-#define RCC_BDCR_LSEDRV_Pos                  (3U)\r
-#define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */\r
-#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk\r
-#define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */\r
-#define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */\r
-\r
-#define RCC_BDCR_LSECSSON_Pos                (5U)\r
-#define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */\r
-#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk\r
-#define RCC_BDCR_LSECSSD_Pos                 (6U)\r
-#define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */\r
-#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk\r
-\r
-#define RCC_BDCR_RTCSEL_Pos                  (8U)\r
-#define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */\r
-#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk\r
-#define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */\r
-#define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */\r
-\r
-#define RCC_BDCR_RTCEN_Pos                   (15U)\r
-#define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */\r
-#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk\r
-#define RCC_BDCR_BDRST_Pos                   (16U)\r
-#define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */\r
-#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk\r
-#define RCC_BDCR_LSCOEN_Pos                  (24U)\r
-#define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */\r
-#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk\r
-#define RCC_BDCR_LSCOSEL_Pos                 (25U)\r
-#define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */\r
-#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk\r
-\r
-/********************  Bit definition for RCC_CSR register  *******************/\r
-#define RCC_CSR_LSION_Pos                    (0U)\r
-#define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */\r
-#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk\r
-#define RCC_CSR_LSIRDY_Pos                   (1U)\r
-#define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */\r
-#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk\r
-\r
-#define RCC_CSR_MSISRANGE_Pos                (8U)\r
-#define RCC_CSR_MSISRANGE_Msk                (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */\r
-#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk\r
-#define RCC_CSR_MSISRANGE_1                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */\r
-#define RCC_CSR_MSISRANGE_2                  (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */\r
-#define RCC_CSR_MSISRANGE_4                  (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */\r
-#define RCC_CSR_MSISRANGE_8                  (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */\r
-\r
-#define RCC_CSR_RMVF_Pos                     (23U)\r
-#define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */\r
-#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk\r
-#define RCC_CSR_FWRSTF_Pos                   (24U)\r
-#define RCC_CSR_FWRSTF_Msk                   (0x1UL << RCC_CSR_FWRSTF_Pos)     /*!< 0x01000000 */\r
-#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk\r
-#define RCC_CSR_OBLRSTF_Pos                  (25U)\r
-#define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */\r
-#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk\r
-#define RCC_CSR_PINRSTF_Pos                  (26U)\r
-#define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */\r
-#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk\r
-#define RCC_CSR_BORRSTF_Pos                  (27U)\r
-#define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */\r
-#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk\r
-#define RCC_CSR_SFTRSTF_Pos                  (28U)\r
-#define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */\r
-#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk\r
-#define RCC_CSR_IWDGRSTF_Pos                 (29U)\r
-#define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */\r
-#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk\r
-#define RCC_CSR_WWDGRSTF_Pos                 (30U)\r
-#define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */\r
-#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk\r
-#define RCC_CSR_LPWRRSTF_Pos                 (31U)\r
-#define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */\r
-#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                    RNG                                     */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/********************  Bits definition for RNG_CR register  *******************/\r
-#define RNG_CR_RNGEN_Pos    (2U)\r
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */\r
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\r
-#define RNG_CR_IE_Pos       (3U)\r
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */\r
-#define RNG_CR_IE           RNG_CR_IE_Msk\r
-\r
-/********************  Bits definition for RNG_SR register  *******************/\r
-#define RNG_SR_DRDY_Pos     (0U)\r
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */\r
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\r
-#define RNG_SR_CECS_Pos     (1U)\r
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */\r
-#define RNG_SR_CECS         RNG_SR_CECS_Msk\r
-#define RNG_SR_SECS_Pos     (2U)\r
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */\r
-#define RNG_SR_SECS         RNG_SR_SECS_Msk\r
-#define RNG_SR_CEIS_Pos     (5U)\r
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */\r
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\r
-#define RNG_SR_SEIS_Pos     (6U)\r
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */\r
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                           Real-Time Clock (RTC)                            */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*\r
-* @brief Specific device feature definitions\r
-*/\r
-#define RTC_TAMPER1_SUPPORT\r
-#define RTC_TAMPER2_SUPPORT\r
-#define RTC_TAMPER3_SUPPORT\r
-#define RTC_WAKEUP_SUPPORT\r
-#define RTC_BACKUP_SUPPORT\r
-\r
-/********************  Bits definition for RTC_TR register  *******************/\r
-#define RTC_TR_PM_Pos                  (22U)\r
-#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */\r
-#define RTC_TR_PM                      RTC_TR_PM_Msk\r
-#define RTC_TR_HT_Pos                  (20U)\r
-#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */\r
-#define RTC_TR_HT                      RTC_TR_HT_Msk\r
-#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */\r
-#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */\r
-#define RTC_TR_HU_Pos                  (16U)\r
-#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */\r
-#define RTC_TR_HU                      RTC_TR_HU_Msk\r
-#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */\r
-#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */\r
-#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */\r
-#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */\r
-#define RTC_TR_MNT_Pos                 (12U)\r
-#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */\r
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk\r
-#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */\r
-#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */\r
-#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */\r
-#define RTC_TR_MNU_Pos                 (8U)\r
-#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */\r
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk\r
-#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */\r
-#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */\r
-#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */\r
-#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */\r
-#define RTC_TR_ST_Pos                  (4U)\r
-#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */\r
-#define RTC_TR_ST                      RTC_TR_ST_Msk\r
-#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */\r
-#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */\r
-#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */\r
-#define RTC_TR_SU_Pos                  (0U)\r
-#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */\r
-#define RTC_TR_SU                      RTC_TR_SU_Msk\r
-#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */\r
-#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */\r
-#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */\r
-#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */\r
-\r
-/********************  Bits definition for RTC_DR register  *******************/\r
-#define RTC_DR_YT_Pos                  (20U)\r
-#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */\r
-#define RTC_DR_YT                      RTC_DR_YT_Msk\r
-#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */\r
-#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */\r
-#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */\r
-#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */\r
-#define RTC_DR_YU_Pos                  (16U)\r
-#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */\r
-#define RTC_DR_YU                      RTC_DR_YU_Msk\r
-#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */\r
-#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */\r
-#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */\r
-#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */\r
-#define RTC_DR_WDU_Pos                 (13U)\r
-#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */\r
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk\r
-#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */\r
-#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */\r
-#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */\r
-#define RTC_DR_MT_Pos                  (12U)\r
-#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */\r
-#define RTC_DR_MT                      RTC_DR_MT_Msk\r
-#define RTC_DR_MU_Pos                  (8U)\r
-#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */\r
-#define RTC_DR_MU                      RTC_DR_MU_Msk\r
-#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */\r
-#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */\r
-#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */\r
-#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */\r
-#define RTC_DR_DT_Pos                  (4U)\r
-#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */\r
-#define RTC_DR_DT                      RTC_DR_DT_Msk\r
-#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */\r
-#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */\r
-#define RTC_DR_DU_Pos                  (0U)\r
-#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */\r
-#define RTC_DR_DU                      RTC_DR_DU_Msk\r
-#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */\r
-#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */\r
-#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */\r
-#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */\r
-\r
-/********************  Bits definition for RTC_CR register  *******************/\r
-#define RTC_CR_ITSE_Pos                (24U)\r
-#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */\r
-#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk\r
-#define RTC_CR_COE_Pos                 (23U)\r
-#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */\r
-#define RTC_CR_COE                     RTC_CR_COE_Msk\r
-#define RTC_CR_OSEL_Pos                (21U)\r
-#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */\r
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk\r
-#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */\r
-#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */\r
-#define RTC_CR_POL_Pos                 (20U)\r
-#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */\r
-#define RTC_CR_POL                     RTC_CR_POL_Msk\r
-#define RTC_CR_COSEL_Pos               (19U)\r
-#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */\r
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk\r
-#define RTC_CR_BKP_Pos                 (18U)\r
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */\r
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk\r
-#define RTC_CR_SUB1H_Pos               (17U)\r
-#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */\r
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk\r
-#define RTC_CR_ADD1H_Pos               (16U)\r
-#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */\r
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk\r
-#define RTC_CR_TSIE_Pos                (15U)\r
-#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */\r
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk\r
-#define RTC_CR_WUTIE_Pos               (14U)\r
-#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */\r
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk\r
-#define RTC_CR_ALRBIE_Pos              (13U)\r
-#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */\r
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk\r
-#define RTC_CR_ALRAIE_Pos              (12U)\r
-#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */\r
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk\r
-#define RTC_CR_TSE_Pos                 (11U)\r
-#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */\r
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk\r
-#define RTC_CR_WUTE_Pos                (10U)\r
-#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */\r
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk\r
-#define RTC_CR_ALRBE_Pos               (9U)\r
-#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */\r
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk\r
-#define RTC_CR_ALRAE_Pos               (8U)\r
-#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */\r
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk\r
-#define RTC_CR_FMT_Pos                 (6U)\r
-#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */\r
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk\r
-#define RTC_CR_BYPSHAD_Pos             (5U)\r
-#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */\r
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk\r
-#define RTC_CR_REFCKON_Pos             (4U)\r
-#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */\r
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk\r
-#define RTC_CR_TSEDGE_Pos              (3U)\r
-#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */\r
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk\r
-#define RTC_CR_WUCKSEL_Pos             (0U)\r
-#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */\r
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk\r
-#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */\r
-#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */\r
-#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */\r
-\r
-/* Legacy defines */\r
-#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos\r
-#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk\r
-#define RTC_CR_BCK                     RTC_CR_BKP\r
-\r
-/********************  Bits definition for RTC_ISR register  ******************/\r
-#define RTC_ISR_ITSF_Pos               (17U)\r
-#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */\r
-#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk\r
-#define RTC_ISR_RECALPF_Pos            (16U)\r
-#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */\r
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk\r
-#define RTC_ISR_TAMP3F_Pos             (15U)\r
-#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */\r
-#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk\r
-#define RTC_ISR_TAMP2F_Pos             (14U)\r
-#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */\r
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk\r
-#define RTC_ISR_TAMP1F_Pos             (13U)\r
-#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */\r
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk\r
-#define RTC_ISR_TSOVF_Pos              (12U)\r
-#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */\r
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk\r
-#define RTC_ISR_TSF_Pos                (11U)\r
-#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */\r
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk\r
-#define RTC_ISR_WUTF_Pos               (10U)\r
-#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */\r
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk\r
-#define RTC_ISR_ALRBF_Pos              (9U)\r
-#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */\r
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk\r
-#define RTC_ISR_ALRAF_Pos              (8U)\r
-#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */\r
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk\r
-#define RTC_ISR_INIT_Pos               (7U)\r
-#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */\r
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk\r
-#define RTC_ISR_INITF_Pos              (6U)\r
-#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */\r
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk\r
-#define RTC_ISR_RSF_Pos                (5U)\r
-#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */\r
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk\r
-#define RTC_ISR_INITS_Pos              (4U)\r
-#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */\r
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk\r
-#define RTC_ISR_SHPF_Pos               (3U)\r
-#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */\r
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk\r
-#define RTC_ISR_WUTWF_Pos              (2U)\r
-#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */\r
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk\r
-#define RTC_ISR_ALRBWF_Pos             (1U)\r
-#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */\r
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk\r
-#define RTC_ISR_ALRAWF_Pos             (0U)\r
-#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */\r
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk\r
-\r
-/********************  Bits definition for RTC_PRER register  *****************/\r
-#define RTC_PRER_PREDIV_A_Pos          (16U)\r
-#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */\r
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk\r
-#define RTC_PRER_PREDIV_S_Pos          (0U)\r
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */\r
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk\r
-\r
-/********************  Bits definition for RTC_WUTR register  *****************/\r
-#define RTC_WUTR_WUT_Pos               (0U)\r
-#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */\r
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk\r
-\r
-/********************  Bits definition for RTC_ALRMAR register  ***************/\r
-#define RTC_ALRMAR_MSK4_Pos            (31U)\r
-#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */\r
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk\r
-#define RTC_ALRMAR_WDSEL_Pos           (30U)\r
-#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */\r
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk\r
-#define RTC_ALRMAR_DT_Pos              (28U)\r
-#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */\r
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk\r
-#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */\r
-#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */\r
-#define RTC_ALRMAR_DU_Pos              (24U)\r
-#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */\r
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk\r
-#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */\r
-#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */\r
-#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */\r
-#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */\r
-#define RTC_ALRMAR_MSK3_Pos            (23U)\r
-#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */\r
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk\r
-#define RTC_ALRMAR_PM_Pos              (22U)\r
-#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */\r
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk\r
-#define RTC_ALRMAR_HT_Pos              (20U)\r
-#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */\r
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk\r
-#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */\r
-#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */\r
-#define RTC_ALRMAR_HU_Pos              (16U)\r
-#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */\r
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk\r
-#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */\r
-#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */\r
-#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */\r
-#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */\r
-#define RTC_ALRMAR_MSK2_Pos            (15U)\r
-#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */\r
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk\r
-#define RTC_ALRMAR_MNT_Pos             (12U)\r
-#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */\r
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk\r
-#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */\r
-#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */\r
-#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */\r
-#define RTC_ALRMAR_MNU_Pos             (8U)\r
-#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */\r
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk\r
-#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */\r
-#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */\r
-#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */\r
-#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */\r
-#define RTC_ALRMAR_MSK1_Pos            (7U)\r
-#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */\r
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk\r
-#define RTC_ALRMAR_ST_Pos              (4U)\r
-#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */\r
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk\r
-#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */\r
-#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */\r
-#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */\r
-#define RTC_ALRMAR_SU_Pos              (0U)\r
-#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */\r
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk\r
-#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */\r
-#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */\r
-#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */\r
-#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */\r
-\r
-/********************  Bits definition for RTC_ALRMBR register  ***************/\r
-#define RTC_ALRMBR_MSK4_Pos            (31U)\r
-#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */\r
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk\r
-#define RTC_ALRMBR_WDSEL_Pos           (30U)\r
-#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */\r
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk\r
-#define RTC_ALRMBR_DT_Pos              (28U)\r
-#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */\r
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk\r
-#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */\r
-#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */\r
-#define RTC_ALRMBR_DU_Pos              (24U)\r
-#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */\r
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk\r
-#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */\r
-#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */\r
-#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */\r
-#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */\r
-#define RTC_ALRMBR_MSK3_Pos            (23U)\r
-#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */\r
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk\r
-#define RTC_ALRMBR_PM_Pos              (22U)\r
-#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */\r
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk\r
-#define RTC_ALRMBR_HT_Pos              (20U)\r
-#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */\r
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk\r
-#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */\r
-#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */\r
-#define RTC_ALRMBR_HU_Pos              (16U)\r
-#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */\r
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk\r
-#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */\r
-#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */\r
-#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */\r
-#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */\r
-#define RTC_ALRMBR_MSK2_Pos            (15U)\r
-#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */\r
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk\r
-#define RTC_ALRMBR_MNT_Pos             (12U)\r
-#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */\r
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk\r
-#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */\r
-#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */\r
-#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */\r
-#define RTC_ALRMBR_MNU_Pos             (8U)\r
-#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */\r
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk\r
-#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */\r
-#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */\r
-#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */\r
-#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */\r
-#define RTC_ALRMBR_MSK1_Pos            (7U)\r
-#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */\r
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk\r
-#define RTC_ALRMBR_ST_Pos              (4U)\r
-#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */\r
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk\r
-#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */\r
-#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */\r
-#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */\r
-#define RTC_ALRMBR_SU_Pos              (0U)\r
-#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */\r
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk\r
-#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */\r
-#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */\r
-#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */\r
-#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */\r
-\r
-/********************  Bits definition for RTC_WPR register  ******************/\r
-#define RTC_WPR_KEY_Pos                (0U)\r
-#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */\r
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk\r
-\r
-/********************  Bits definition for RTC_SSR register  ******************/\r
-#define RTC_SSR_SS_Pos                 (0U)\r
-#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */\r
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk\r
-\r
-/********************  Bits definition for RTC_SHIFTR register  ***************/\r
-#define RTC_SHIFTR_SUBFS_Pos           (0U)\r
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */\r
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk\r
-#define RTC_SHIFTR_ADD1S_Pos           (31U)\r
-#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */\r
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk\r
-\r
-/********************  Bits definition for RTC_TSTR register  *****************/\r
-#define RTC_TSTR_PM_Pos                (22U)\r
-#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */\r
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk\r
-#define RTC_TSTR_HT_Pos                (20U)\r
-#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */\r
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk\r
-#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */\r
-#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */\r
-#define RTC_TSTR_HU_Pos                (16U)\r
-#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */\r
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk\r
-#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */\r
-#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */\r
-#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */\r
-#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */\r
-#define RTC_TSTR_MNT_Pos               (12U)\r
-#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */\r
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk\r
-#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */\r
-#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */\r
-#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */\r
-#define RTC_TSTR_MNU_Pos               (8U)\r
-#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */\r
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk\r
-#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */\r
-#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */\r
-#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */\r
-#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */\r
-#define RTC_TSTR_ST_Pos                (4U)\r
-#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */\r
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk\r
-#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */\r
-#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */\r
-#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */\r
-#define RTC_TSTR_SU_Pos                (0U)\r
-#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */\r
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk\r
-#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */\r
-#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */\r
-#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */\r
-#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */\r
-\r
-/********************  Bits definition for RTC_TSDR register  *****************/\r
-#define RTC_TSDR_WDU_Pos               (13U)\r
-#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */\r
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk\r
-#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */\r
-#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */\r
-#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */\r
-#define RTC_TSDR_MT_Pos                (12U)\r
-#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */\r
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk\r
-#define RTC_TSDR_MU_Pos                (8U)\r
-#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */\r
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk\r
-#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */\r
-#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */\r
-#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */\r
-#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */\r
-#define RTC_TSDR_DT_Pos                (4U)\r
-#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */\r
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk\r
-#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */\r
-#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */\r
-#define RTC_TSDR_DU_Pos                (0U)\r
-#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */\r
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk\r
-#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */\r
-#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */\r
-#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */\r
-#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */\r
-\r
-/********************  Bits definition for RTC_TSSSR register  ****************/\r
-#define RTC_TSSSR_SS_Pos               (0U)\r
-#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */\r
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk\r
-\r
-/********************  Bits definition for RTC_CAL register  *****************/\r
-#define RTC_CALR_CALP_Pos              (15U)\r
-#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */\r
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk\r
-#define RTC_CALR_CALW8_Pos             (14U)\r
-#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */\r
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk\r
-#define RTC_CALR_CALW16_Pos            (13U)\r
-#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */\r
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk\r
-#define RTC_CALR_CALM_Pos              (0U)\r
-#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */\r
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk\r
-#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */\r
-#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */\r
-#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */\r
-#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */\r
-#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */\r
-#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */\r
-#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */\r
-#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */\r
-#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */\r
-\r
-/********************  Bits definition for RTC_TAMPCR register  ***************/\r
-#define RTC_TAMPCR_TAMP3MF_Pos         (24U)\r
-#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */\r
-#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk\r
-#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)\r
-#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */\r
-#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk\r
-#define RTC_TAMPCR_TAMP3IE_Pos         (22U)\r
-#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */\r
-#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk\r
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)\r
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */\r
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk\r
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)\r
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */\r
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk\r
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)\r
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */\r
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk\r
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)\r
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */\r
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk\r
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)\r
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */\r
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk\r
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)\r
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */\r
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk\r
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)\r
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */\r
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk\r
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)\r
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */\r
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk\r
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00002000 */\r
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00004000 */\r
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)\r
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */\r
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk\r
-#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00000800 */\r
-#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001000 */\r
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)\r
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */\r
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk\r
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000100 */\r
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000200 */\r
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000400 */\r
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)\r
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */\r
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk\r
-#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)\r
-#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */\r
-#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk\r
-#define RTC_TAMPCR_TAMP3E_Pos          (5U)\r
-#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */\r
-#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk\r
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)\r
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */\r
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk\r
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)\r
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */\r
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk\r
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)\r
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */\r
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk\r
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)\r
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */\r
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk\r
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)\r
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */\r
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk\r
-\r
-/********************  Bits definition for RTC_ALRMASSR register  *************/\r
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)\r
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */\r
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk\r
-#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */\r
-#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */\r
-#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */\r
-#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */\r
-#define RTC_ALRMASSR_SS_Pos            (0U)\r
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */\r
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk\r
-\r
-/********************  Bits definition for RTC_ALRMBSSR register  *************/\r
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)\r
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */\r
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk\r
-#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */\r
-#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */\r
-#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */\r
-#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */\r
-#define RTC_ALRMBSSR_SS_Pos            (0U)\r
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */\r
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk\r
-\r
-/********************  Bits definition for RTC_0R register  *******************/\r
-#define RTC_OR_OUT_RMP_Pos             (1U)\r
-#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */\r
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk\r
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)\r
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */\r
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk\r
-\r
-\r
-/********************  Bits definition for RTC_BKP0R register  ****************/\r
-#define RTC_BKP0R_Pos                  (0U)\r
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP0R                      RTC_BKP0R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP1R register  ****************/\r
-#define RTC_BKP1R_Pos                  (0U)\r
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP1R                      RTC_BKP1R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP2R register  ****************/\r
-#define RTC_BKP2R_Pos                  (0U)\r
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP2R                      RTC_BKP2R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP3R register  ****************/\r
-#define RTC_BKP3R_Pos                  (0U)\r
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP3R                      RTC_BKP3R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP4R register  ****************/\r
-#define RTC_BKP4R_Pos                  (0U)\r
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP4R                      RTC_BKP4R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP5R register  ****************/\r
-#define RTC_BKP5R_Pos                  (0U)\r
-#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP5R                      RTC_BKP5R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP6R register  ****************/\r
-#define RTC_BKP6R_Pos                  (0U)\r
-#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP6R                      RTC_BKP6R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP7R register  ****************/\r
-#define RTC_BKP7R_Pos                  (0U)\r
-#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP7R                      RTC_BKP7R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP8R register  ****************/\r
-#define RTC_BKP8R_Pos                  (0U)\r
-#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP8R                      RTC_BKP8R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP9R register  ****************/\r
-#define RTC_BKP9R_Pos                  (0U)\r
-#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */\r
-#define RTC_BKP9R                      RTC_BKP9R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP10R register  ***************/\r
-#define RTC_BKP10R_Pos                 (0U)\r
-#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP10R                     RTC_BKP10R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP11R register  ***************/\r
-#define RTC_BKP11R_Pos                 (0U)\r
-#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP11R                     RTC_BKP11R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP12R register  ***************/\r
-#define RTC_BKP12R_Pos                 (0U)\r
-#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP12R                     RTC_BKP12R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP13R register  ***************/\r
-#define RTC_BKP13R_Pos                 (0U)\r
-#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP13R                     RTC_BKP13R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP14R register  ***************/\r
-#define RTC_BKP14R_Pos                 (0U)\r
-#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP14R                     RTC_BKP14R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP15R register  ***************/\r
-#define RTC_BKP15R_Pos                 (0U)\r
-#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP15R                     RTC_BKP15R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP16R register  ***************/\r
-#define RTC_BKP16R_Pos                 (0U)\r
-#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP16R                     RTC_BKP16R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP17R register  ***************/\r
-#define RTC_BKP17R_Pos                 (0U)\r
-#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP17R                     RTC_BKP17R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP18R register  ***************/\r
-#define RTC_BKP18R_Pos                 (0U)\r
-#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP18R                     RTC_BKP18R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP19R register  ***************/\r
-#define RTC_BKP19R_Pos                 (0U)\r
-#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP19R                     RTC_BKP19R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP20R register  ***************/\r
-#define RTC_BKP20R_Pos                 (0U)\r
-#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP20R                     RTC_BKP20R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP21R register  ***************/\r
-#define RTC_BKP21R_Pos                 (0U)\r
-#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP21R                     RTC_BKP21R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP22R register  ***************/\r
-#define RTC_BKP22R_Pos                 (0U)\r
-#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP22R                     RTC_BKP22R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP23R register  ***************/\r
-#define RTC_BKP23R_Pos                 (0U)\r
-#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP23R                     RTC_BKP23R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP24R register  ***************/\r
-#define RTC_BKP24R_Pos                 (0U)\r
-#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP24R                     RTC_BKP24R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP25R register  ***************/\r
-#define RTC_BKP25R_Pos                 (0U)\r
-#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP25R                     RTC_BKP25R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP26R register  ***************/\r
-#define RTC_BKP26R_Pos                 (0U)\r
-#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP26R                     RTC_BKP26R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP27R register  ***************/\r
-#define RTC_BKP27R_Pos                 (0U)\r
-#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP27R                     RTC_BKP27R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP28R register  ***************/\r
-#define RTC_BKP28R_Pos                 (0U)\r
-#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP28R                     RTC_BKP28R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP29R register  ***************/\r
-#define RTC_BKP29R_Pos                 (0U)\r
-#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP29R                     RTC_BKP29R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP30R register  ***************/\r
-#define RTC_BKP30R_Pos                 (0U)\r
-#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP30R                     RTC_BKP30R_Msk\r
-\r
-/********************  Bits definition for RTC_BKP31R register  ***************/\r
-#define RTC_BKP31R_Pos                 (0U)\r
-#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */\r
-#define RTC_BKP31R                     RTC_BKP31R_Msk\r
-\r
-/******************** Number of backup registers ******************************/\r
-#define RTC_BKP_NUMBER                       32U\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                          Serial Audio Interface                            */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/********************  Bit definition for SAI_GCR register  *******************/\r
-#define SAI_GCR_SYNCIN_Pos         (0U)\r
-#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */\r
-#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\r
-#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000001 */\r
-#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000002 */\r
-\r
-#define SAI_GCR_SYNCOUT_Pos        (4U)\r
-#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */\r
-#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
-#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000010 */\r
-#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000020 */\r
-\r
-/*******************  Bit definition for SAI_xCR1 register  *******************/\r
-#define SAI_xCR1_MODE_Pos          (0U)\r
-#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */\r
-#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\r
-#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000001 */\r
-#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000002 */\r
-\r
-#define SAI_xCR1_PRTCFG_Pos        (2U)\r
-#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */\r
-#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\r
-#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000004 */\r
-#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000008 */\r
-\r
-#define SAI_xCR1_DS_Pos            (5U)\r
-#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */\r
-#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\r
-#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000020 */\r
-#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000040 */\r
-#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000080 */\r
-\r
-#define SAI_xCR1_LSBFIRST_Pos      (8U)\r
-#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */\r
-#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\r
-#define SAI_xCR1_CKSTR_Pos         (9U)\r
-#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */\r
-#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\r
-\r
-#define SAI_xCR1_SYNCEN_Pos        (10U)\r
-#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */\r
-#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\r
-#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000400 */\r
-#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000800 */\r
-\r
-#define SAI_xCR1_MONO_Pos          (12U)\r
-#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */\r
-#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\r
-#define SAI_xCR1_OUTDRIV_Pos       (13U)\r
-#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */\r
-#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\r
-#define SAI_xCR1_SAIEN_Pos         (16U)\r
-#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */\r
-#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\r
-#define SAI_xCR1_DMAEN_Pos         (17U)\r
-#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */\r
-#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\r
-#define SAI_xCR1_NODIV_Pos         (19U)\r
-#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */\r
-#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\r
-\r
-#define SAI_xCR1_MCKDIV_Pos        (20U)\r
-#define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00F00000 */\r
-#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\r
-#define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */\r
-#define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */\r
-#define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */\r
-#define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */\r
-\r
-/*******************  Bit definition for SAI_xCR2 register  *******************/\r
-#define SAI_xCR2_FTH_Pos           (0U)\r
-#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */\r
-#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\r
-#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000001 */\r
-#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000002 */\r
-#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000004 */\r
-\r
-#define SAI_xCR2_FFLUSH_Pos        (3U)\r
-#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */\r
-#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\r
-#define SAI_xCR2_TRIS_Pos          (4U)\r
-#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */\r
-#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\r
-#define SAI_xCR2_MUTE_Pos          (5U)\r
-#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */\r
-#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\r
-#define SAI_xCR2_MUTEVAL_Pos       (6U)\r
-#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */\r
-#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\r
-\r
-\r
-#define SAI_xCR2_MUTECNT_Pos       (7U)\r
-#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */\r
-#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\r
-#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000080 */\r
-#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000100 */\r
-#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000200 */\r
-#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000400 */\r
-#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000800 */\r
-#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001000 */\r
-\r
-#define SAI_xCR2_CPL_Pos           (13U)\r
-#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */\r
-#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */\r
-#define SAI_xCR2_COMP_Pos          (14U)\r
-#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */\r
-#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\r
-#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                /*!< 0x00004000 */\r
-#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                /*!< 0x00008000 */\r
-\r
-\r
-/******************  Bit definition for SAI_xFRCR register  *******************/\r
-#define SAI_xFRCR_FRL_Pos          (0U)\r
-#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */\r
-#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */\r
-#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000001 */\r
-#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000002 */\r
-#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000004 */\r
-#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000008 */\r
-#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000010 */\r
-#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000020 */\r
-#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000040 */\r
-#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000080 */\r
-\r
-#define SAI_xFRCR_FSALL_Pos        (8U)\r
-#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */\r
-#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */\r
-#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000100 */\r
-#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000200 */\r
-#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000400 */\r
-#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000800 */\r
-#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00001000 */\r
-#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00002000 */\r
-#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00004000 */\r
-\r
-#define SAI_xFRCR_FSDEF_Pos        (16U)\r
-#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */\r
-#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\r
-#define SAI_xFRCR_FSPOL_Pos        (17U)\r
-#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */\r
-#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\r
-#define SAI_xFRCR_FSOFF_Pos        (18U)\r
-#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */\r
-#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\r
-\r
-/******************  Bit definition for SAI_xSLOTR register  *******************/\r
-#define SAI_xSLOTR_FBOFF_Pos       (0U)\r
-#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */\r
-#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\r
-#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000001 */\r
-#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000002 */\r
-#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000004 */\r
-#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000008 */\r
-#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000010 */\r
-\r
-#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\r
-#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */\r
-#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\r
-#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000040 */\r
-#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000080 */\r
-\r
-#define SAI_xSLOTR_NBSLOT_Pos      (8U)\r
-#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */\r
-#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\r
-#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000100 */\r
-#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000200 */\r
-#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000400 */\r
-#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000800 */\r
-\r
-#define SAI_xSLOTR_SLOTEN_Pos      (16U)\r
-#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */\r
-#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\r
-\r
-/*******************  Bit definition for SAI_xIMR register  *******************/\r
-#define SAI_xIMR_OVRUDRIE_Pos      (0U)\r
-#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */\r
-#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\r
-#define SAI_xIMR_MUTEDETIE_Pos     (1U)\r
-#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */\r
-#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\r
-#define SAI_xIMR_WCKCFGIE_Pos      (2U)\r
-#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */\r
-#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\r
-#define SAI_xIMR_FREQIE_Pos        (3U)\r
-#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */\r
-#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\r
-#define SAI_xIMR_CNRDYIE_Pos       (4U)\r
-#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */\r
-#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\r
-#define SAI_xIMR_AFSDETIE_Pos      (5U)\r
-#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */\r
-#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\r
-#define SAI_xIMR_LFSDETIE_Pos      (6U)\r
-#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */\r
-#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\r
-\r
-/********************  Bit definition for SAI_xSR register  *******************/\r
-#define SAI_xSR_OVRUDR_Pos         (0U)\r
-#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */\r
-#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\r
-#define SAI_xSR_MUTEDET_Pos        (1U)\r
-#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */\r
-#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\r
-#define SAI_xSR_WCKCFG_Pos         (2U)\r
-#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */\r
-#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\r
-#define SAI_xSR_FREQ_Pos           (3U)\r
-#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */\r
-#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\r
-#define SAI_xSR_CNRDY_Pos          (4U)\r
-#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */\r
-#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\r
-#define SAI_xSR_AFSDET_Pos         (5U)\r
-#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */\r
-#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\r
-#define SAI_xSR_LFSDET_Pos         (6U)\r
-#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */\r
-#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\r
-\r
-#define SAI_xSR_FLVL_Pos           (16U)\r
-#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */\r
-#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\r
-#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00010000 */\r
-#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00020000 */\r
-#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00040000 */\r
-\r
-/******************  Bit definition for SAI_xCLRFR register  ******************/\r
-#define SAI_xCLRFR_COVRUDR_Pos     (0U)\r
-#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */\r
-#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\r
-#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\r
-#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */\r
-#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\r
-#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\r
-#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */\r
-#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\r
-#define SAI_xCLRFR_CFREQ_Pos       (3U)\r
-#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */\r
-#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\r
-#define SAI_xCLRFR_CCNRDY_Pos      (4U)\r
-#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */\r
-#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\r
-#define SAI_xCLRFR_CAFSDET_Pos     (5U)\r
-#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */\r
-#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\r
-#define SAI_xCLRFR_CLFSDET_Pos     (6U)\r
-#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */\r
-#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\r
-\r
-/******************  Bit definition for SAI_xDR register  ******************/\r
-#define SAI_xDR_DATA_Pos           (0U)\r
-#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */\r
-#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                           SDMMC Interface                                  */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/******************  Bit definition for SDMMC_POWER register  ******************/\r
-#define SDMMC_POWER_PWRCTRL_Pos         (0U)\r
-#define SDMMC_POWER_PWRCTRL_Msk         (0x3UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000003 */\r
-#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
-#define SDMMC_POWER_PWRCTRL_0           (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */\r
-#define SDMMC_POWER_PWRCTRL_1           (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */\r
-\r
-/******************  Bit definition for SDMMC_CLKCR register  ******************/\r
-#define SDMMC_CLKCR_CLKDIV_Pos          (0U)\r
-#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000000FF */\r
-#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */\r
-#define SDMMC_CLKCR_CLKEN_Pos           (8U)\r
-#define SDMMC_CLKCR_CLKEN_Msk           (0x1UL << SDMMC_CLKCR_CLKEN_Pos)       /*!< 0x00000100 */\r
-#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */\r
-#define SDMMC_CLKCR_PWRSAV_Pos          (9U)\r
-#define SDMMC_CLKCR_PWRSAV_Msk          (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)      /*!< 0x00000200 */\r
-#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */\r
-#define SDMMC_CLKCR_BYPASS_Pos          (10U)\r
-#define SDMMC_CLKCR_BYPASS_Msk          (0x1UL << SDMMC_CLKCR_BYPASS_Pos)      /*!< 0x00000400 */\r
-#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */\r
-\r
-#define SDMMC_CLKCR_WIDBUS_Pos          (11U)\r
-#define SDMMC_CLKCR_WIDBUS_Msk          (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00001800 */\r
-#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
-#define SDMMC_CLKCR_WIDBUS_0            (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00000800 */\r
-#define SDMMC_CLKCR_WIDBUS_1            (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00001000 */\r
-\r
-#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)\r
-#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)     /*!< 0x00002000 */\r
-#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */\r
-#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)\r
-#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)     /*!< 0x00004000 */\r
-#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */\r
-\r
-/*******************  Bit definition for SDMMC_ARG register  *******************/\r
-#define SDMMC_ARG_CMDARG_Pos            (0U)\r
-#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r
-#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */\r
-\r
-/*******************  Bit definition for SDMMC_CMD register  *******************/\r
-#define SDMMC_CMD_CMDINDEX_Pos          (0U)\r
-#define SDMMC_CMD_CMDINDEX_Msk          (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)     /*!< 0x0000003F */\r
-#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */\r
-\r
-#define SDMMC_CMD_WAITRESP_Pos          (6U)\r
-#define SDMMC_CMD_WAITRESP_Msk          (0x3UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x000000C0 */\r
-#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
-#define SDMMC_CMD_WAITRESP_0            (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000040 */\r
-#define SDMMC_CMD_WAITRESP_1            (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000080 */\r
-\r
-#define SDMMC_CMD_WAITINT_Pos           (8U)\r
-#define SDMMC_CMD_WAITINT_Msk           (0x1UL << SDMMC_CMD_WAITINT_Pos)       /*!< 0x00000100 */\r
-#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */\r
-#define SDMMC_CMD_WAITPEND_Pos          (9U)\r
-#define SDMMC_CMD_WAITPEND_Msk          (0x1UL << SDMMC_CMD_WAITPEND_Pos)      /*!< 0x00000200 */\r
-#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
-#define SDMMC_CMD_CPSMEN_Pos            (10U)\r
-#define SDMMC_CMD_CPSMEN_Msk            (0x1UL << SDMMC_CMD_CPSMEN_Pos)        /*!< 0x00000400 */\r
-#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */\r
-#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)\r
-#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)   /*!< 0x00000800 */\r
-#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */\r
-\r
-/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\r
-#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)\r
-#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)  /*!< 0x0000003F */\r
-#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */\r
-\r
-/******************  Bit definition for SDMMC_RESP1 register  ******************/\r
-#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)\r
-#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r
-#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */\r
-\r
-/******************  Bit definition for SDMMC_RESP2 register  ******************/\r
-#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)\r
-#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r
-#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */\r
-\r
-/******************  Bit definition for SDMMC_RESP3 register  ******************/\r
-#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)\r
-#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r
-#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */\r
-\r
-/******************  Bit definition for SDMMC_RESP4 register  ******************/\r
-#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)\r
-#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r
-#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */\r
-\r
-/******************  Bit definition for SDMMC_DTIMER register  *****************/\r
-#define SDMMC_DTIMER_DATATIME_Pos       (0U)\r
-#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r
-#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */\r
-\r
-/******************  Bit definition for SDMMC_DLEN register  *******************/\r
-#define SDMMC_DLEN_DATALENGTH_Pos       (0U)\r
-#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r
-#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */\r
-\r
-/******************  Bit definition for SDMMC_DCTRL register  ******************/\r
-#define SDMMC_DCTRL_DTEN_Pos            (0U)\r
-#define SDMMC_DCTRL_DTEN_Msk            (0x1UL << SDMMC_DCTRL_DTEN_Pos)        /*!< 0x00000001 */\r
-#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */\r
-#define SDMMC_DCTRL_DTDIR_Pos           (1U)\r
-#define SDMMC_DCTRL_DTDIR_Msk           (0x1UL << SDMMC_DCTRL_DTDIR_Pos)       /*!< 0x00000002 */\r
-#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */\r
-#define SDMMC_DCTRL_DTMODE_Pos          (2U)\r
-#define SDMMC_DCTRL_DTMODE_Msk          (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */\r
-#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */\r
-#define SDMMC_DCTRL_DMAEN_Pos           (3U)\r
-#define SDMMC_DCTRL_DMAEN_Msk           (0x1UL << SDMMC_DCTRL_DMAEN_Pos)       /*!< 0x00000008 */\r
-#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */\r
-\r
-#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)\r
-#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x000000F0 */\r
-#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
-#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */\r
-#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */\r
-#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */\r
-#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */\r
-\r
-#define SDMMC_DCTRL_RWSTART_Pos         (8U)\r
-#define SDMMC_DCTRL_RWSTART_Msk         (0x1UL << SDMMC_DCTRL_RWSTART_Pos)     /*!< 0x00000100 */\r
-#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */\r
-#define SDMMC_DCTRL_RWSTOP_Pos          (9U)\r
-#define SDMMC_DCTRL_RWSTOP_Msk          (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)      /*!< 0x00000200 */\r
-#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */\r
-#define SDMMC_DCTRL_RWMOD_Pos           (10U)\r
-#define SDMMC_DCTRL_RWMOD_Msk           (0x1UL << SDMMC_DCTRL_RWMOD_Pos)       /*!< 0x00000400 */\r
-#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */\r
-#define SDMMC_DCTRL_SDIOEN_Pos          (11U)\r
-#define SDMMC_DCTRL_SDIOEN_Msk          (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)      /*!< 0x00000800 */\r
-#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */\r
-\r
-/******************  Bit definition for SDMMC_DCOUNT register  *****************/\r
-#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)\r
-#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r
-#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */\r
-\r
-/******************  Bit definition for SDMMC_STA register  ********************/\r
-#define SDMMC_STA_CCRCFAIL_Pos          (0U)\r
-#define SDMMC_STA_CCRCFAIL_Msk          (0x1UL << SDMMC_STA_CCRCFAIL_Pos)      /*!< 0x00000001 */\r
-#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */\r
-#define SDMMC_STA_DCRCFAIL_Pos          (1U)\r
-#define SDMMC_STA_DCRCFAIL_Msk          (0x1UL << SDMMC_STA_DCRCFAIL_Pos)      /*!< 0x00000002 */\r
-#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */\r
-#define SDMMC_STA_CTIMEOUT_Pos          (2U)\r
-#define SDMMC_STA_CTIMEOUT_Msk          (0x1UL << SDMMC_STA_CTIMEOUT_Pos)      /*!< 0x00000004 */\r
-#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */\r
-#define SDMMC_STA_DTIMEOUT_Pos          (3U)\r
-#define SDMMC_STA_DTIMEOUT_Msk          (0x1UL << SDMMC_STA_DTIMEOUT_Pos)      /*!< 0x00000008 */\r
-#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */\r
-#define SDMMC_STA_TXUNDERR_Pos          (4U)\r
-#define SDMMC_STA_TXUNDERR_Msk          (0x1UL << SDMMC_STA_TXUNDERR_Pos)      /*!< 0x00000010 */\r
-#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */\r
-#define SDMMC_STA_RXOVERR_Pos           (5U)\r
-#define SDMMC_STA_RXOVERR_Msk           (0x1UL << SDMMC_STA_RXOVERR_Pos)       /*!< 0x00000020 */\r
-#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */\r
-#define SDMMC_STA_CMDREND_Pos           (6U)\r
-#define SDMMC_STA_CMDREND_Msk           (0x1UL << SDMMC_STA_CMDREND_Pos)       /*!< 0x00000040 */\r
-#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */\r
-#define SDMMC_STA_CMDSENT_Pos           (7U)\r
-#define SDMMC_STA_CMDSENT_Msk           (0x1UL << SDMMC_STA_CMDSENT_Pos)       /*!< 0x00000080 */\r
-#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */\r
-#define SDMMC_STA_DATAEND_Pos           (8U)\r
-#define SDMMC_STA_DATAEND_Msk           (0x1UL << SDMMC_STA_DATAEND_Pos)       /*!< 0x00000100 */\r
-#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */\r
-#define SDMMC_STA_STBITERR_Pos          (9U)\r
-#define SDMMC_STA_STBITERR_Msk          (0x1UL << SDMMC_STA_STBITERR_Pos)      /*!< 0x00000200 */\r
-#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */\r
-#define SDMMC_STA_DBCKEND_Pos           (10U)\r
-#define SDMMC_STA_DBCKEND_Msk           (0x1UL << SDMMC_STA_DBCKEND_Pos)       /*!< 0x00000400 */\r
-#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */\r
-#define SDMMC_STA_CMDACT_Pos            (11U)\r
-#define SDMMC_STA_CMDACT_Msk            (0x1UL << SDMMC_STA_CMDACT_Pos)        /*!< 0x00000800 */\r
-#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */\r
-#define SDMMC_STA_TXACT_Pos             (12U)\r
-#define SDMMC_STA_TXACT_Msk             (0x1UL << SDMMC_STA_TXACT_Pos)         /*!< 0x00001000 */\r
-#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */\r
-#define SDMMC_STA_RXACT_Pos             (13U)\r
-#define SDMMC_STA_RXACT_Msk             (0x1UL << SDMMC_STA_RXACT_Pos)         /*!< 0x00002000 */\r
-#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */\r
-#define SDMMC_STA_TXFIFOHE_Pos          (14U)\r
-#define SDMMC_STA_TXFIFOHE_Msk          (0x1UL << SDMMC_STA_TXFIFOHE_Pos)      /*!< 0x00004000 */\r
-#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
-#define SDMMC_STA_RXFIFOHF_Pos          (15U)\r
-#define SDMMC_STA_RXFIFOHF_Msk          (0x1UL << SDMMC_STA_RXFIFOHF_Pos)      /*!< 0x00008000 */\r
-#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
-#define SDMMC_STA_TXFIFOF_Pos           (16U)\r
-#define SDMMC_STA_TXFIFOF_Msk           (0x1UL << SDMMC_STA_TXFIFOF_Pos)       /*!< 0x00010000 */\r
-#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */\r
-#define SDMMC_STA_RXFIFOF_Pos           (17U)\r
-#define SDMMC_STA_RXFIFOF_Msk           (0x1UL << SDMMC_STA_RXFIFOF_Pos)       /*!< 0x00020000 */\r
-#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */\r
-#define SDMMC_STA_TXFIFOE_Pos           (18U)\r
-#define SDMMC_STA_TXFIFOE_Msk           (0x1UL << SDMMC_STA_TXFIFOE_Pos)       /*!< 0x00040000 */\r
-#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */\r
-#define SDMMC_STA_RXFIFOE_Pos           (19U)\r
-#define SDMMC_STA_RXFIFOE_Msk           (0x1UL << SDMMC_STA_RXFIFOE_Pos)       /*!< 0x00080000 */\r
-#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */\r
-#define SDMMC_STA_TXDAVL_Pos            (20U)\r
-#define SDMMC_STA_TXDAVL_Msk            (0x1UL << SDMMC_STA_TXDAVL_Pos)        /*!< 0x00100000 */\r
-#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */\r
-#define SDMMC_STA_RXDAVL_Pos            (21U)\r
-#define SDMMC_STA_RXDAVL_Msk            (0x1UL << SDMMC_STA_RXDAVL_Pos)        /*!< 0x00200000 */\r
-#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */\r
-#define SDMMC_STA_SDIOIT_Pos            (22U)\r
-#define SDMMC_STA_SDIOIT_Msk            (0x1UL << SDMMC_STA_SDIOIT_Pos)        /*!< 0x00400000 */\r
-#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */\r
-\r
-/*******************  Bit definition for SDMMC_ICR register  *******************/\r
-#define SDMMC_ICR_CCRCFAILC_Pos         (0U)\r
-#define SDMMC_ICR_CCRCFAILC_Msk         (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)     /*!< 0x00000001 */\r
-#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */\r
-#define SDMMC_ICR_DCRCFAILC_Pos         (1U)\r
-#define SDMMC_ICR_DCRCFAILC_Msk         (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)     /*!< 0x00000002 */\r
-#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */\r
-#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)\r
-#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)     /*!< 0x00000004 */\r
-#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */\r
-#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)\r
-#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)     /*!< 0x00000008 */\r
-#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */\r
-#define SDMMC_ICR_TXUNDERRC_Pos         (4U)\r
-#define SDMMC_ICR_TXUNDERRC_Msk         (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)     /*!< 0x00000010 */\r
-#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */\r
-#define SDMMC_ICR_RXOVERRC_Pos          (5U)\r
-#define SDMMC_ICR_RXOVERRC_Msk          (0x1UL << SDMMC_ICR_RXOVERRC_Pos)      /*!< 0x00000020 */\r
-#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */\r
-#define SDMMC_ICR_CMDRENDC_Pos          (6U)\r
-#define SDMMC_ICR_CMDRENDC_Msk          (0x1UL << SDMMC_ICR_CMDRENDC_Pos)      /*!< 0x00000040 */\r
-#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */\r
-#define SDMMC_ICR_CMDSENTC_Pos          (7U)\r
-#define SDMMC_ICR_CMDSENTC_Msk          (0x1UL << SDMMC_ICR_CMDSENTC_Pos)      /*!< 0x00000080 */\r
-#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */\r
-#define SDMMC_ICR_DATAENDC_Pos          (8U)\r
-#define SDMMC_ICR_DATAENDC_Msk          (0x1UL << SDMMC_ICR_DATAENDC_Pos)      /*!< 0x00000100 */\r
-#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */\r
-#define SDMMC_ICR_STBITERRC_Pos         (9U)\r
-#define SDMMC_ICR_STBITERRC_Msk         (0x1UL << SDMMC_ICR_STBITERRC_Pos)     /*!< 0x00000200 */\r
-#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */\r
-#define SDMMC_ICR_DBCKENDC_Pos          (10U)\r
-#define SDMMC_ICR_DBCKENDC_Msk          (0x1UL << SDMMC_ICR_DBCKENDC_Pos)      /*!< 0x00000400 */\r
-#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */\r
-#define SDMMC_ICR_SDIOITC_Pos           (22U)\r
-#define SDMMC_ICR_SDIOITC_Msk           (0x1UL << SDMMC_ICR_SDIOITC_Pos)       /*!< 0x00400000 */\r
-#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */\r
-\r
-/******************  Bit definition for SDMMC_MASK register  *******************/\r
-#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)\r
-#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)   /*!< 0x00000001 */\r
-#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */\r
-#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)\r
-#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)   /*!< 0x00000002 */\r
-#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */\r
-#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)\r
-#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)   /*!< 0x00000004 */\r
-#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */\r
-#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)\r
-#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)   /*!< 0x00000008 */\r
-#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */\r
-#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)\r
-#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)   /*!< 0x00000010 */\r
-#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */\r
-#define SDMMC_MASK_RXOVERRIE_Pos        (5U)\r
-#define SDMMC_MASK_RXOVERRIE_Msk        (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)    /*!< 0x00000020 */\r
-#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */\r
-#define SDMMC_MASK_CMDRENDIE_Pos        (6U)\r
-#define SDMMC_MASK_CMDRENDIE_Msk        (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)    /*!< 0x00000040 */\r
-#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */\r
-#define SDMMC_MASK_CMDSENTIE_Pos        (7U)\r
-#define SDMMC_MASK_CMDSENTIE_Msk        (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)    /*!< 0x00000080 */\r
-#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */\r
-#define SDMMC_MASK_DATAENDIE_Pos        (8U)\r
-#define SDMMC_MASK_DATAENDIE_Msk        (0x1UL << SDMMC_MASK_DATAENDIE_Pos)    /*!< 0x00000100 */\r
-#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */\r
-#define SDMMC_MASK_DBCKENDIE_Pos        (10U)\r
-#define SDMMC_MASK_DBCKENDIE_Msk        (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)    /*!< 0x00000400 */\r
-#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */\r
-#define SDMMC_MASK_CMDACTIE_Pos         (11U)\r
-#define SDMMC_MASK_CMDACTIE_Msk         (0x1UL << SDMMC_MASK_CMDACTIE_Pos)     /*!< 0x00000800 */\r
-#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */\r
-#define SDMMC_MASK_TXACTIE_Pos          (12U)\r
-#define SDMMC_MASK_TXACTIE_Msk          (0x1UL << SDMMC_MASK_TXACTIE_Pos)      /*!< 0x00001000 */\r
-#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */\r
-#define SDMMC_MASK_RXACTIE_Pos          (13U)\r
-#define SDMMC_MASK_RXACTIE_Msk          (0x1UL << SDMMC_MASK_RXACTIE_Pos)      /*!< 0x00002000 */\r
-#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */\r
-#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)\r
-#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)   /*!< 0x00004000 */\r
-#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */\r
-#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)\r
-#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)   /*!< 0x00008000 */\r
-#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */\r
-#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)\r
-#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)    /*!< 0x00010000 */\r
-#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */\r
-#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)\r
-#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)    /*!< 0x00020000 */\r
-#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */\r
-#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)\r
-#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)    /*!< 0x00040000 */\r
-#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */\r
-#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)\r
-#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)    /*!< 0x00080000 */\r
-#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */\r
-#define SDMMC_MASK_TXDAVLIE_Pos         (20U)\r
-#define SDMMC_MASK_TXDAVLIE_Msk         (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)     /*!< 0x00100000 */\r
-#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */\r
-#define SDMMC_MASK_RXDAVLIE_Pos         (21U)\r
-#define SDMMC_MASK_RXDAVLIE_Msk         (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)     /*!< 0x00200000 */\r
-#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */\r
-#define SDMMC_MASK_SDIOITIE_Pos         (22U)\r
-#define SDMMC_MASK_SDIOITIE_Msk         (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */\r
-#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */\r
-\r
-/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/\r
-#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)\r
-#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\r
-#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */\r
-\r
-/******************  Bit definition for SDMMC_FIFO register  *******************/\r
-#define SDMMC_FIFO_FIFODATA_Pos         (0U)\r
-#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r
-#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                        Serial Peripheral Interface (SPI)                   */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for SPI_CR1 register  ********************/\r
-#define SPI_CR1_CPHA_Pos         (0U)\r
-#define SPI_CR1_CPHA_Msk         (0x1UL << SPI_CR1_CPHA_Pos)                   /*!< 0x00000001 */\r
-#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */\r
-#define SPI_CR1_CPOL_Pos         (1U)\r
-#define SPI_CR1_CPOL_Msk         (0x1UL << SPI_CR1_CPOL_Pos)                   /*!< 0x00000002 */\r
-#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */\r
-#define SPI_CR1_MSTR_Pos         (2U)\r
-#define SPI_CR1_MSTR_Msk         (0x1UL << SPI_CR1_MSTR_Pos)                   /*!< 0x00000004 */\r
-#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */\r
-\r
-#define SPI_CR1_BR_Pos           (3U)\r
-#define SPI_CR1_BR_Msk           (0x7UL << SPI_CR1_BR_Pos)                     /*!< 0x00000038 */\r
-#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */\r
-#define SPI_CR1_BR_0             (0x1UL << SPI_CR1_BR_Pos)                     /*!< 0x00000008 */\r
-#define SPI_CR1_BR_1             (0x2UL << SPI_CR1_BR_Pos)                     /*!< 0x00000010 */\r
-#define SPI_CR1_BR_2             (0x4UL << SPI_CR1_BR_Pos)                     /*!< 0x00000020 */\r
-\r
-#define SPI_CR1_SPE_Pos          (6U)\r
-#define SPI_CR1_SPE_Msk          (0x1UL << SPI_CR1_SPE_Pos)                    /*!< 0x00000040 */\r
-#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */\r
-#define SPI_CR1_LSBFIRST_Pos     (7U)\r
-#define SPI_CR1_LSBFIRST_Msk     (0x1UL << SPI_CR1_LSBFIRST_Pos)               /*!< 0x00000080 */\r
-#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */\r
-#define SPI_CR1_SSI_Pos          (8U)\r
-#define SPI_CR1_SSI_Msk          (0x1UL << SPI_CR1_SSI_Pos)                    /*!< 0x00000100 */\r
-#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */\r
-#define SPI_CR1_SSM_Pos          (9U)\r
-#define SPI_CR1_SSM_Msk          (0x1UL << SPI_CR1_SSM_Pos)                    /*!< 0x00000200 */\r
-#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */\r
-#define SPI_CR1_RXONLY_Pos       (10U)\r
-#define SPI_CR1_RXONLY_Msk       (0x1UL << SPI_CR1_RXONLY_Pos)                 /*!< 0x00000400 */\r
-#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */\r
-#define SPI_CR1_CRCL_Pos         (11U)\r
-#define SPI_CR1_CRCL_Msk         (0x1UL << SPI_CR1_CRCL_Pos)                   /*!< 0x00000800 */\r
-#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */\r
-#define SPI_CR1_CRCNEXT_Pos      (12U)\r
-#define SPI_CR1_CRCNEXT_Msk      (0x1UL << SPI_CR1_CRCNEXT_Pos)                /*!< 0x00001000 */\r
-#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */\r
-#define SPI_CR1_CRCEN_Pos        (13U)\r
-#define SPI_CR1_CRCEN_Msk        (0x1UL << SPI_CR1_CRCEN_Pos)                  /*!< 0x00002000 */\r
-#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */\r
-#define SPI_CR1_BIDIOE_Pos       (14U)\r
-#define SPI_CR1_BIDIOE_Msk       (0x1UL << SPI_CR1_BIDIOE_Pos)                 /*!< 0x00004000 */\r
-#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */\r
-#define SPI_CR1_BIDIMODE_Pos     (15U)\r
-#define SPI_CR1_BIDIMODE_Msk     (0x1UL << SPI_CR1_BIDIMODE_Pos)               /*!< 0x00008000 */\r
-#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */\r
-\r
-/*******************  Bit definition for SPI_CR2 register  ********************/\r
-#define SPI_CR2_RXDMAEN_Pos      (0U)\r
-#define SPI_CR2_RXDMAEN_Msk      (0x1UL << SPI_CR2_RXDMAEN_Pos)                /*!< 0x00000001 */\r
-#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */\r
-#define SPI_CR2_TXDMAEN_Pos      (1U)\r
-#define SPI_CR2_TXDMAEN_Msk      (0x1UL << SPI_CR2_TXDMAEN_Pos)                /*!< 0x00000002 */\r
-#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */\r
-#define SPI_CR2_SSOE_Pos         (2U)\r
-#define SPI_CR2_SSOE_Msk         (0x1UL << SPI_CR2_SSOE_Pos)                   /*!< 0x00000004 */\r
-#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */\r
-#define SPI_CR2_NSSP_Pos         (3U)\r
-#define SPI_CR2_NSSP_Msk         (0x1UL << SPI_CR2_NSSP_Pos)                   /*!< 0x00000008 */\r
-#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */\r
-#define SPI_CR2_FRF_Pos          (4U)\r
-#define SPI_CR2_FRF_Msk          (0x1UL << SPI_CR2_FRF_Pos)                    /*!< 0x00000010 */\r
-#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */\r
-#define SPI_CR2_ERRIE_Pos        (5U)\r
-#define SPI_CR2_ERRIE_Msk        (0x1UL << SPI_CR2_ERRIE_Pos)                  /*!< 0x00000020 */\r
-#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */\r
-#define SPI_CR2_RXNEIE_Pos       (6U)\r
-#define SPI_CR2_RXNEIE_Msk       (0x1UL << SPI_CR2_RXNEIE_Pos)                 /*!< 0x00000040 */\r
-#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */\r
-#define SPI_CR2_TXEIE_Pos        (7U)\r
-#define SPI_CR2_TXEIE_Msk        (0x1UL << SPI_CR2_TXEIE_Pos)                  /*!< 0x00000080 */\r
-#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */\r
-#define SPI_CR2_DS_Pos           (8U)\r
-#define SPI_CR2_DS_Msk           (0xFUL << SPI_CR2_DS_Pos)                     /*!< 0x00000F00 */\r
-#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */\r
-#define SPI_CR2_DS_0             (0x1UL << SPI_CR2_DS_Pos)                     /*!< 0x00000100 */\r
-#define SPI_CR2_DS_1             (0x2UL << SPI_CR2_DS_Pos)                     /*!< 0x00000200 */\r
-#define SPI_CR2_DS_2             (0x4UL << SPI_CR2_DS_Pos)                     /*!< 0x00000400 */\r
-#define SPI_CR2_DS_3             (0x8UL << SPI_CR2_DS_Pos)                     /*!< 0x00000800 */\r
-#define SPI_CR2_FRXTH_Pos        (12U)\r
-#define SPI_CR2_FRXTH_Msk        (0x1UL << SPI_CR2_FRXTH_Pos)                  /*!< 0x00001000 */\r
-#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */\r
-#define SPI_CR2_LDMARX_Pos       (13U)\r
-#define SPI_CR2_LDMARX_Msk       (0x1UL << SPI_CR2_LDMARX_Pos)                 /*!< 0x00002000 */\r
-#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */\r
-#define SPI_CR2_LDMATX_Pos       (14U)\r
-#define SPI_CR2_LDMATX_Msk       (0x1UL << SPI_CR2_LDMATX_Pos)                 /*!< 0x00004000 */\r
-#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */\r
-\r
-/********************  Bit definition for SPI_SR register  ********************/\r
-#define SPI_SR_RXNE_Pos          (0U)\r
-#define SPI_SR_RXNE_Msk          (0x1UL << SPI_SR_RXNE_Pos)                    /*!< 0x00000001 */\r
-#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */\r
-#define SPI_SR_TXE_Pos           (1U)\r
-#define SPI_SR_TXE_Msk           (0x1UL << SPI_SR_TXE_Pos)                     /*!< 0x00000002 */\r
-#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */\r
-#define SPI_SR_CHSIDE_Pos        (2U)\r
-#define SPI_SR_CHSIDE_Msk        (0x1UL << SPI_SR_CHSIDE_Pos)                  /*!< 0x00000004 */\r
-#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */\r
-#define SPI_SR_UDR_Pos           (3U)\r
-#define SPI_SR_UDR_Msk           (0x1UL << SPI_SR_UDR_Pos)                     /*!< 0x00000008 */\r
-#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */\r
-#define SPI_SR_CRCERR_Pos        (4U)\r
-#define SPI_SR_CRCERR_Msk        (0x1UL << SPI_SR_CRCERR_Pos)                  /*!< 0x00000010 */\r
-#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */\r
-#define SPI_SR_MODF_Pos          (5U)\r
-#define SPI_SR_MODF_Msk          (0x1UL << SPI_SR_MODF_Pos)                    /*!< 0x00000020 */\r
-#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */\r
-#define SPI_SR_OVR_Pos           (6U)\r
-#define SPI_SR_OVR_Msk           (0x1UL << SPI_SR_OVR_Pos)                     /*!< 0x00000040 */\r
-#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */\r
-#define SPI_SR_BSY_Pos           (7U)\r
-#define SPI_SR_BSY_Msk           (0x1UL << SPI_SR_BSY_Pos)                     /*!< 0x00000080 */\r
-#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */\r
-#define SPI_SR_FRE_Pos           (8U)\r
-#define SPI_SR_FRE_Msk           (0x1UL << SPI_SR_FRE_Pos)                     /*!< 0x00000100 */\r
-#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */\r
-#define SPI_SR_FRLVL_Pos         (9U)\r
-#define SPI_SR_FRLVL_Msk         (0x3UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000600 */\r
-#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */\r
-#define SPI_SR_FRLVL_0           (0x1UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000200 */\r
-#define SPI_SR_FRLVL_1           (0x2UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000400 */\r
-#define SPI_SR_FTLVL_Pos         (11U)\r
-#define SPI_SR_FTLVL_Msk         (0x3UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001800 */\r
-#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */\r
-#define SPI_SR_FTLVL_0           (0x1UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00000800 */\r
-#define SPI_SR_FTLVL_1           (0x2UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001000 */\r
-\r
-/********************  Bit definition for SPI_DR register  ********************/\r
-#define SPI_DR_DR_Pos            (0U)\r
-#define SPI_DR_DR_Msk            (0xFFFFUL << SPI_DR_DR_Pos)                   /*!< 0x0000FFFF */\r
-#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */\r
-\r
-/*******************  Bit definition for SPI_CRCPR register  ******************/\r
-#define SPI_CRCPR_CRCPOLY_Pos    (0U)\r
-#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)           /*!< 0x0000FFFF */\r
-#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */\r
-\r
-/******************  Bit definition for SPI_RXCRCR register  ******************/\r
-#define SPI_RXCRCR_RXCRC_Pos     (0U)\r
-#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)            /*!< 0x0000FFFF */\r
-#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */\r
-\r
-/******************  Bit definition for SPI_TXCRCR register  ******************/\r
-#define SPI_TXCRCR_TXCRC_Pos     (0U)\r
-#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)            /*!< 0x0000FFFF */\r
-#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                    QUADSPI                                 */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*****************  Bit definition for QUADSPI_CR register  *******************/\r
-#define QUADSPI_CR_EN_Pos              (0U)\r
-#define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */\r
-#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */\r
-#define QUADSPI_CR_ABORT_Pos           (1U)\r
-#define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */\r
-#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */\r
-#define QUADSPI_CR_DMAEN_Pos           (2U)\r
-#define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */\r
-#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */\r
-#define QUADSPI_CR_TCEN_Pos            (3U)\r
-#define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */\r
-#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */\r
-#define QUADSPI_CR_SSHIFT_Pos          (4U)\r
-#define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */\r
-#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */\r
-#define QUADSPI_CR_FTHRES_Pos          (8U)\r
-#define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */\r
-#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */\r
-#define QUADSPI_CR_TEIE_Pos            (16U)\r
-#define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */\r
-#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */\r
-#define QUADSPI_CR_TCIE_Pos            (17U)\r
-#define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */\r
-#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */\r
-#define QUADSPI_CR_FTIE_Pos            (18U)\r
-#define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */\r
-#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */\r
-#define QUADSPI_CR_SMIE_Pos            (19U)\r
-#define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */\r
-#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */\r
-#define QUADSPI_CR_TOIE_Pos            (20U)\r
-#define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */\r
-#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */\r
-#define QUADSPI_CR_APMS_Pos            (22U)\r
-#define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */\r
-#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */\r
-#define QUADSPI_CR_PMM_Pos             (23U)\r
-#define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */\r
-#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */\r
-#define QUADSPI_CR_PRESCALER_Pos       (24U)\r
-#define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */\r
-#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */\r
-\r
-/*****************  Bit definition for QUADSPI_DCR register  ******************/\r
-#define QUADSPI_DCR_CKMODE_Pos         (0U)\r
-#define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */\r
-#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */\r
-#define QUADSPI_DCR_CSHT_Pos           (8U)\r
-#define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */\r
-#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */\r
-#define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */\r
-#define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */\r
-#define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */\r
-#define QUADSPI_DCR_FSIZE_Pos          (16U)\r
-#define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */\r
-#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */\r
-\r
-/******************  Bit definition for QUADSPI_SR register  *******************/\r
-#define QUADSPI_SR_TEF_Pos             (0U)\r
-#define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */\r
-#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */\r
-#define QUADSPI_SR_TCF_Pos             (1U)\r
-#define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */\r
-#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */\r
-#define QUADSPI_SR_FTF_Pos             (2U)\r
-#define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */\r
-#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */\r
-#define QUADSPI_SR_SMF_Pos             (3U)\r
-#define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */\r
-#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */\r
-#define QUADSPI_SR_TOF_Pos             (4U)\r
-#define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */\r
-#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */\r
-#define QUADSPI_SR_BUSY_Pos            (5U)\r
-#define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */\r
-#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */\r
-#define QUADSPI_SR_FLEVEL_Pos          (8U)\r
-#define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */\r
-#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */\r
-\r
-/******************  Bit definition for QUADSPI_FCR register  ******************/\r
-#define QUADSPI_FCR_CTEF_Pos           (0U)\r
-#define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */\r
-#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */\r
-#define QUADSPI_FCR_CTCF_Pos           (1U)\r
-#define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */\r
-#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */\r
-#define QUADSPI_FCR_CSMF_Pos           (3U)\r
-#define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */\r
-#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */\r
-#define QUADSPI_FCR_CTOF_Pos           (4U)\r
-#define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */\r
-#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */\r
-\r
-/******************  Bit definition for QUADSPI_DLR register  ******************/\r
-#define QUADSPI_DLR_DL_Pos             (0U)\r
-#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */\r
-#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */\r
-\r
-/******************  Bit definition for QUADSPI_CCR register  ******************/\r
-#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)\r
-#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\r
-#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */\r
-#define QUADSPI_CCR_IMODE_Pos          (8U)\r
-#define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */\r
-#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */\r
-#define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */\r
-#define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */\r
-#define QUADSPI_CCR_ADMODE_Pos         (10U)\r
-#define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */\r
-#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */\r
-#define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */\r
-#define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */\r
-#define QUADSPI_CCR_ADSIZE_Pos         (12U)\r
-#define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */\r
-#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */\r
-#define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */\r
-#define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */\r
-#define QUADSPI_CCR_ABMODE_Pos         (14U)\r
-#define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */\r
-#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
-#define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */\r
-#define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */\r
-#define QUADSPI_CCR_ABSIZE_Pos         (16U)\r
-#define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */\r
-#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */\r
-#define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */\r
-#define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */\r
-#define QUADSPI_CCR_DCYC_Pos           (18U)\r
-#define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */\r
-#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */\r
-#define QUADSPI_CCR_DMODE_Pos          (24U)\r
-#define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */\r
-#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */\r
-#define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */\r
-#define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */\r
-#define QUADSPI_CCR_FMODE_Pos          (26U)\r
-#define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */\r
-#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */\r
-#define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */\r
-#define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */\r
-#define QUADSPI_CCR_SIOO_Pos           (28U)\r
-#define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */\r
-#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */\r
-#define QUADSPI_CCR_DDRM_Pos           (31U)\r
-#define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */\r
-#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */\r
-\r
-/******************  Bit definition for QUADSPI_AR register  *******************/\r
-#define QUADSPI_AR_ADDRESS_Pos         (0U)\r
-#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r
-#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */\r
-\r
-/******************  Bit definition for QUADSPI_ABR register  ******************/\r
-#define QUADSPI_ABR_ALTERNATE_Pos      (0U)\r
-#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r
-#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */\r
-\r
-/******************  Bit definition for QUADSPI_DR register  *******************/\r
-#define QUADSPI_DR_DATA_Pos            (0U)\r
-#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */\r
-#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */\r
-\r
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/\r
-#define QUADSPI_PSMKR_MASK_Pos         (0U)\r
-#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r
-#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */\r
-\r
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/\r
-#define QUADSPI_PSMAR_MATCH_Pos        (0U)\r
-#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r
-#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */\r
-\r
-/******************  Bit definition for QUADSPI_PIR register  *****************/\r
-#define QUADSPI_PIR_INTERVAL_Pos       (0U)\r
-#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */\r
-#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */\r
-\r
-/******************  Bit definition for QUADSPI_LPTR register  *****************/\r
-#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)\r
-#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */\r
-#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                 SYSCFG                                     */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\r
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)\r
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */\r
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */\r
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */\r
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */\r
-#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */\r
-\r
-#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)\r
-#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */\r
-#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */\r
-\r
-/******************  Bit definition for SYSCFG_CFGR1 register  ******************/\r
-#define SYSCFG_CFGR1_FWDIS_Pos          (0U)\r
-#define SYSCFG_CFGR1_FWDIS_Msk          (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)      /*!< 0x00000001 */\r
-#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/\r
-#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)\r
-#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */\r
-#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */\r
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)\r
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */\r
-#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */\r
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)\r
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */\r
-#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */\r
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)\r
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */\r
-#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */\r
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)\r
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */\r
-#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */\r
-#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)\r
-#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */\r
-#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */\r
-#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)\r
-#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */\r
-#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */\r
-#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)\r
-#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */\r
-#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */\r
-#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000UL)                         /*!<  Invalid operation Interrupt enable */\r
-#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000UL)                         /*!<  Divide-by-zero Interrupt enable */\r
-#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000UL)                         /*!<  Underflow Interrupt enable */\r
-#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000UL)                         /*!<  Overflow Interrupt enable */\r
-#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000UL)                         /*!<  Input denormal Interrupt enable */\r
-#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000UL)                         /*!<  Inexact Interrupt enable (interrupt disabled at reset) */\r
-\r
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)\r
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x00000007 */\r
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */\r
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)\r
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x00000070 */\r
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */\r
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)\r
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000700 */\r
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */\r
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)\r
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x00007000 */\r
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */\r
-\r
-/**\r
-  * @brief   EXTI0 configuration\r
-  */\r
-#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000UL)                     /*!<PA[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001UL)                     /*!<PB[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002UL)                     /*!<PC[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003UL)                     /*!<PD[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004UL)                     /*!<PE[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005UL)                     /*!<PF[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006UL)                     /*!<PG[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007UL)                     /*!<PH[0] pin */\r
-\r
-/**\r
-  * @brief   EXTI1 configuration\r
-  */\r
-#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000UL)                     /*!<PA[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010UL)                     /*!<PB[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020UL)                     /*!<PC[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030UL)                     /*!<PD[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040UL)                     /*!<PE[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050UL)                     /*!<PF[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060UL)                     /*!<PG[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070UL)                     /*!<PH[1] pin */\r
-\r
-/**\r
-  * @brief   EXTI2 configuration\r
-  */\r
-#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000UL)                     /*!<PA[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100UL)                     /*!<PB[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200UL)                     /*!<PC[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300UL)                     /*!<PD[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400UL)                     /*!<PE[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500UL)                     /*!<PF[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600UL)                     /*!<PG[2] pin */\r
-\r
-/**\r
-  * @brief   EXTI3 configuration\r
-  */\r
-#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000UL)                     /*!<PA[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000UL)                     /*!<PB[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000UL)                     /*!<PC[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000UL)                     /*!<PD[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000UL)                     /*!<PE[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000UL)                     /*!<PF[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000UL)                     /*!<PG[3] pin */\r
-\r
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\r
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)\r
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x00000007 */\r
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */\r
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)\r
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x00000070 */\r
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */\r
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)\r
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000700 */\r
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */\r
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)\r
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x00007000 */\r
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */\r
-/**\r
-  * @brief   EXTI4 configuration\r
-  */\r
-#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000UL)                     /*!<PA[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001UL)                     /*!<PB[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002UL)                     /*!<PC[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003UL)                     /*!<PD[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004UL)                     /*!<PE[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005UL)                     /*!<PF[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006UL)                     /*!<PG[4] pin */\r
-\r
-/**\r
-  * @brief   EXTI5 configuration\r
-  */\r
-#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000UL)                     /*!<PA[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010UL)                     /*!<PB[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020UL)                     /*!<PC[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030UL)                     /*!<PD[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040UL)                     /*!<PE[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050UL)                     /*!<PF[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060UL)                     /*!<PG[5] pin */\r
-\r
-/**\r
-  * @brief   EXTI6 configuration\r
-  */\r
-#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000UL)                     /*!<PA[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100UL)                     /*!<PB[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200UL)                     /*!<PC[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300UL)                     /*!<PD[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400UL)                     /*!<PE[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500UL)                     /*!<PF[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600UL)                     /*!<PG[6] pin */\r
-\r
-/**\r
-  * @brief   EXTI7 configuration\r
-  */\r
-#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000UL)                     /*!<PA[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000UL)                     /*!<PB[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000UL)                     /*!<PC[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000UL)                     /*!<PD[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000UL)                     /*!<PE[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000UL)                     /*!<PF[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000UL)                     /*!<PG[7] pin */\r
-\r
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\r
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)\r
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x00000007 */\r
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */\r
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)\r
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x00000070 */\r
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */\r
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)\r
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000700 */\r
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */\r
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)\r
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x00007000 */\r
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */\r
-\r
-/**\r
-  * @brief   EXTI8 configuration\r
-  */\r
-#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000UL)                     /*!<PA[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001UL)                     /*!<PB[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002UL)                     /*!<PC[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003UL)                     /*!<PD[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004UL)                     /*!<PE[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005UL)                     /*!<PF[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006UL)                     /*!<PG[8] pin */\r
-\r
-/**\r
-  * @brief   EXTI9 configuration\r
-  */\r
-#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000UL)                     /*!<PA[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010UL)                     /*!<PB[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020UL)                     /*!<PC[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030UL)                     /*!<PD[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040UL)                     /*!<PE[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050UL)                     /*!<PF[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060UL)                     /*!<PG[9] pin */\r
-\r
-/**\r
-  * @brief   EXTI10 configuration\r
-  */\r
-#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000UL)                     /*!<PA[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100UL)                     /*!<PB[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200UL)                     /*!<PC[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300UL)                     /*!<PD[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400UL)                     /*!<PE[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500UL)                     /*!<PF[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600UL)                     /*!<PG[10] pin */\r
-\r
-/**\r
-  * @brief   EXTI11 configuration\r
-  */\r
-#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000UL)                     /*!<PA[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000UL)                     /*!<PB[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000UL)                     /*!<PC[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000UL)                     /*!<PD[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000UL)                     /*!<PE[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000UL)                     /*!<PF[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000UL)                     /*!<PG[11] pin */\r
-\r
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\r
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)\r
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */\r
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */\r
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)\r
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */\r
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */\r
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)\r
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */\r
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */\r
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)\r
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */\r
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */\r
-\r
-/**\r
-  * @brief   EXTI12 configuration\r
-  */\r
-#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000UL)                     /*!<PA[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001UL)                     /*!<PB[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002UL)                     /*!<PC[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003UL)                     /*!<PD[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004UL)                     /*!<PE[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005UL)                     /*!<PF[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006UL)                     /*!<PG[12] pin */\r
-\r
-/**\r
-  * @brief   EXTI13 configuration\r
-  */\r
-#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000UL)                     /*!<PA[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010UL)                     /*!<PB[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020UL)                     /*!<PC[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030UL)                     /*!<PD[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040UL)                     /*!<PE[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050UL)                     /*!<PF[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060UL)                     /*!<PG[13] pin */\r
-\r
-/**\r
-  * @brief   EXTI14 configuration\r
-  */\r
-#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000UL)                     /*!<PA[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100UL)                     /*!<PB[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200UL)                     /*!<PC[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300UL)                     /*!<PD[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400UL)                     /*!<PE[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500UL)                     /*!<PF[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600UL)                     /*!<PG[14] pin */\r
-\r
-/**\r
-  * @brief   EXTI15 configuration\r
-  */\r
-#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000UL)                     /*!<PA[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000UL)                     /*!<PB[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000UL)                     /*!<PC[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000UL)                     /*!<PD[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000UL)                     /*!<PE[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000UL)                     /*!<PF[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000UL)                     /*!<PG[15] pin */\r
-\r
-/******************  Bit definition for SYSCFG_SCSR register  ****************/\r
-#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)\r
-#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)     /*!< 0x00000001 */\r
-#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */\r
-#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)\r
-#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)    /*!< 0x00000002 */\r
-#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */\r
-\r
-/******************  Bit definition for SYSCFG_CFGR2 register  ****************/\r
-#define SYSCFG_CFGR2_CLL_Pos            (0U)\r
-#define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */\r
-#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */\r
-#define SYSCFG_CFGR2_SPL_Pos            (1U)\r
-#define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */\r
-#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/\r
-#define SYSCFG_CFGR2_PVDL_Pos           (2U)\r
-#define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */\r
-#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */\r
-#define SYSCFG_CFGR2_ECCL_Pos           (3U)\r
-#define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */\r
-#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/\r
-#define SYSCFG_CFGR2_SPF_Pos            (8U)\r
-#define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */\r
-#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */\r
-\r
-/******************  Bit definition for SYSCFG_SWPR register  ****************/\r
-#define SYSCFG_SWPR_PAGE0_Pos           (0U)\r
-#define SYSCFG_SWPR_PAGE0_Msk           (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */\r
-#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */\r
-#define SYSCFG_SWPR_PAGE1_Pos           (1U)\r
-#define SYSCFG_SWPR_PAGE1_Msk           (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */\r
-#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */\r
-#define SYSCFG_SWPR_PAGE2_Pos           (2U)\r
-#define SYSCFG_SWPR_PAGE2_Msk           (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */\r
-#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */\r
-#define SYSCFG_SWPR_PAGE3_Pos           (3U)\r
-#define SYSCFG_SWPR_PAGE3_Msk           (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */\r
-#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */\r
-#define SYSCFG_SWPR_PAGE4_Pos           (4U)\r
-#define SYSCFG_SWPR_PAGE4_Msk           (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */\r
-#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */\r
-#define SYSCFG_SWPR_PAGE5_Pos           (5U)\r
-#define SYSCFG_SWPR_PAGE5_Msk           (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */\r
-#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */\r
-#define SYSCFG_SWPR_PAGE6_Pos           (6U)\r
-#define SYSCFG_SWPR_PAGE6_Msk           (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */\r
-#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */\r
-#define SYSCFG_SWPR_PAGE7_Pos           (7U)\r
-#define SYSCFG_SWPR_PAGE7_Msk           (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */\r
-#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */\r
-#define SYSCFG_SWPR_PAGE8_Pos           (8U)\r
-#define SYSCFG_SWPR_PAGE8_Msk           (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */\r
-#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */\r
-#define SYSCFG_SWPR_PAGE9_Pos           (9U)\r
-#define SYSCFG_SWPR_PAGE9_Msk           (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */\r
-#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */\r
-#define SYSCFG_SWPR_PAGE10_Pos          (10U)\r
-#define SYSCFG_SWPR_PAGE10_Msk          (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */\r
-#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/\r
-#define SYSCFG_SWPR_PAGE11_Pos          (11U)\r
-#define SYSCFG_SWPR_PAGE11_Msk          (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */\r
-#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/\r
-#define SYSCFG_SWPR_PAGE12_Pos          (12U)\r
-#define SYSCFG_SWPR_PAGE12_Msk          (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */\r
-#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/\r
-#define SYSCFG_SWPR_PAGE13_Pos          (13U)\r
-#define SYSCFG_SWPR_PAGE13_Msk          (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */\r
-#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/\r
-#define SYSCFG_SWPR_PAGE14_Pos          (14U)\r
-#define SYSCFG_SWPR_PAGE14_Msk          (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */\r
-#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/\r
-#define SYSCFG_SWPR_PAGE15_Pos          (15U)\r
-#define SYSCFG_SWPR_PAGE15_Msk          (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */\r
-#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/\r
-#define SYSCFG_SWPR_PAGE16_Pos          (16U)\r
-#define SYSCFG_SWPR_PAGE16_Msk          (0x1UL << SYSCFG_SWPR_PAGE16_Pos)      /*!< 0x00010000 */\r
-#define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/\r
-#define SYSCFG_SWPR_PAGE17_Pos          (17U)\r
-#define SYSCFG_SWPR_PAGE17_Msk          (0x1UL << SYSCFG_SWPR_PAGE17_Pos)      /*!< 0x00020000 */\r
-#define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/\r
-#define SYSCFG_SWPR_PAGE18_Pos          (18U)\r
-#define SYSCFG_SWPR_PAGE18_Msk          (0x1UL << SYSCFG_SWPR_PAGE18_Pos)      /*!< 0x00040000 */\r
-#define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/\r
-#define SYSCFG_SWPR_PAGE19_Pos          (19U)\r
-#define SYSCFG_SWPR_PAGE19_Msk          (0x1UL << SYSCFG_SWPR_PAGE19_Pos)      /*!< 0x00080000 */\r
-#define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/\r
-#define SYSCFG_SWPR_PAGE20_Pos          (20U)\r
-#define SYSCFG_SWPR_PAGE20_Msk          (0x1UL << SYSCFG_SWPR_PAGE20_Pos)      /*!< 0x00100000 */\r
-#define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/\r
-#define SYSCFG_SWPR_PAGE21_Pos          (21U)\r
-#define SYSCFG_SWPR_PAGE21_Msk          (0x1UL << SYSCFG_SWPR_PAGE21_Pos)      /*!< 0x00200000 */\r
-#define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/\r
-#define SYSCFG_SWPR_PAGE22_Pos          (22U)\r
-#define SYSCFG_SWPR_PAGE22_Msk          (0x1UL << SYSCFG_SWPR_PAGE22_Pos)      /*!< 0x00400000 */\r
-#define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/\r
-#define SYSCFG_SWPR_PAGE23_Pos          (23U)\r
-#define SYSCFG_SWPR_PAGE23_Msk          (0x1UL << SYSCFG_SWPR_PAGE23_Pos)      /*!< 0x00800000 */\r
-#define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/\r
-#define SYSCFG_SWPR_PAGE24_Pos          (24U)\r
-#define SYSCFG_SWPR_PAGE24_Msk          (0x1UL << SYSCFG_SWPR_PAGE24_Pos)      /*!< 0x01000000 */\r
-#define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/\r
-#define SYSCFG_SWPR_PAGE25_Pos          (25U)\r
-#define SYSCFG_SWPR_PAGE25_Msk          (0x1UL << SYSCFG_SWPR_PAGE25_Pos)      /*!< 0x02000000 */\r
-#define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/\r
-#define SYSCFG_SWPR_PAGE26_Pos          (26U)\r
-#define SYSCFG_SWPR_PAGE26_Msk          (0x1UL << SYSCFG_SWPR_PAGE26_Pos)      /*!< 0x04000000 */\r
-#define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/\r
-#define SYSCFG_SWPR_PAGE27_Pos          (27U)\r
-#define SYSCFG_SWPR_PAGE27_Msk          (0x1UL << SYSCFG_SWPR_PAGE27_Pos)      /*!< 0x08000000 */\r
-#define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/\r
-#define SYSCFG_SWPR_PAGE28_Pos          (28U)\r
-#define SYSCFG_SWPR_PAGE28_Msk          (0x1UL << SYSCFG_SWPR_PAGE28_Pos)      /*!< 0x10000000 */\r
-#define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/\r
-#define SYSCFG_SWPR_PAGE29_Pos          (29U)\r
-#define SYSCFG_SWPR_PAGE29_Msk          (0x1UL << SYSCFG_SWPR_PAGE29_Pos)      /*!< 0x20000000 */\r
-#define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/\r
-#define SYSCFG_SWPR_PAGE30_Pos          (30U)\r
-#define SYSCFG_SWPR_PAGE30_Msk          (0x1UL << SYSCFG_SWPR_PAGE30_Pos)      /*!< 0x40000000 */\r
-#define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/\r
-#define SYSCFG_SWPR_PAGE31_Pos          (31U)\r
-#define SYSCFG_SWPR_PAGE31_Msk          (0x1UL << SYSCFG_SWPR_PAGE31_Pos)      /*!< 0x80000000 */\r
-#define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/\r
-\r
-/******************  Bit definition for SYSCFG_SKR register  ****************/\r
-#define SYSCFG_SKR_KEY_Pos              (0U)\r
-#define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */\r
-#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */\r
-\r
-\r
-\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                    TIM                                     */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for TIM_CR1 register  ********************/\r
-#define TIM_CR1_CEN_Pos           (0U)\r
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */\r
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */\r
-#define TIM_CR1_UDIS_Pos          (1U)\r
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */\r
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */\r
-#define TIM_CR1_URS_Pos           (2U)\r
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */\r
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\r
-#define TIM_CR1_OPM_Pos           (3U)\r
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */\r
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */\r
-#define TIM_CR1_DIR_Pos           (4U)\r
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */\r
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */\r
-\r
-#define TIM_CR1_CMS_Pos           (5U)\r
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */\r
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */\r
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */\r
-\r
-#define TIM_CR1_ARPE_Pos          (7U)\r
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */\r
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */\r
-\r
-#define TIM_CR1_CKD_Pos           (8U)\r
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */\r
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\r
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */\r
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */\r
-\r
-#define TIM_CR1_UIFREMAP_Pos      (11U)\r
-#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */\r
-#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */\r
-\r
-/*******************  Bit definition for TIM_CR2 register  ********************/\r
-#define TIM_CR2_CCPC_Pos          (0U)\r
-#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */\r
-#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */\r
-#define TIM_CR2_CCUS_Pos          (2U)\r
-#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */\r
-#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\r
-#define TIM_CR2_CCDS_Pos          (3U)\r
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */\r
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */\r
-\r
-#define TIM_CR2_MMS_Pos           (4U)\r
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */\r
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\r
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */\r
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */\r
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */\r
-\r
-#define TIM_CR2_TI1S_Pos          (7U)\r
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */\r
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\r
-#define TIM_CR2_OIS1_Pos          (8U)\r
-#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */\r
-#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */\r
-#define TIM_CR2_OIS1N_Pos         (9U)\r
-#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */\r
-#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\r
-#define TIM_CR2_OIS2_Pos          (10U)\r
-#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */\r
-#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */\r
-#define TIM_CR2_OIS2N_Pos         (11U)\r
-#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */\r
-#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\r
-#define TIM_CR2_OIS3_Pos          (12U)\r
-#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */\r
-#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */\r
-#define TIM_CR2_OIS3N_Pos         (13U)\r
-#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */\r
-#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\r
-#define TIM_CR2_OIS4_Pos          (14U)\r
-#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */\r
-#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */\r
-#define TIM_CR2_OIS5_Pos          (16U)\r
-#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */\r
-#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */\r
-#define TIM_CR2_OIS6_Pos          (18U)\r
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */\r
-#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */\r
-\r
-#define TIM_CR2_MMS2_Pos          (20U)\r
-#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */\r
-#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\r
-#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */\r
-#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */\r
-#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */\r
-#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */\r
-\r
-/*******************  Bit definition for TIM_SMCR register  *******************/\r
-#define TIM_SMCR_SMS_Pos          (0U)\r
-#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */\r
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */\r
-#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */\r
-#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */\r
-#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */\r
-#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */\r
-\r
-#define TIM_SMCR_OCCS_Pos         (3U)\r
-#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */\r
-#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */\r
-\r
-#define TIM_SMCR_TS_Pos           (4U)\r
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000070 */\r
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */\r
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000010 */\r
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000020 */\r
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000040 */\r
-\r
-#define TIM_SMCR_MSM_Pos          (7U)\r
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */\r
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */\r
-\r
-#define TIM_SMCR_ETF_Pos          (8U)\r
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */\r
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\r
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */\r
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */\r
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */\r
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */\r
-\r
-#define TIM_SMCR_ETPS_Pos         (12U)\r
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */\r
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\r
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */\r
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */\r
-\r
-#define TIM_SMCR_ECE_Pos          (14U)\r
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */\r
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */\r
-#define TIM_SMCR_ETP_Pos          (15U)\r
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */\r
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\r
-\r
-/*******************  Bit definition for TIM_DIER register  *******************/\r
-#define TIM_DIER_UIE_Pos          (0U)\r
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */\r
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\r
-#define TIM_DIER_CC1IE_Pos        (1U)\r
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */\r
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */\r
-#define TIM_DIER_CC2IE_Pos        (2U)\r
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */\r
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */\r
-#define TIM_DIER_CC3IE_Pos        (3U)\r
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */\r
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */\r
-#define TIM_DIER_CC4IE_Pos        (4U)\r
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */\r
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */\r
-#define TIM_DIER_COMIE_Pos        (5U)\r
-#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */\r
-#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */\r
-#define TIM_DIER_TIE_Pos          (6U)\r
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */\r
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */\r
-#define TIM_DIER_BIE_Pos          (7U)\r
-#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */\r
-#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */\r
-#define TIM_DIER_UDE_Pos          (8U)\r
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */\r
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */\r
-#define TIM_DIER_CC1DE_Pos        (9U)\r
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */\r
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\r
-#define TIM_DIER_CC2DE_Pos        (10U)\r
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */\r
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\r
-#define TIM_DIER_CC3DE_Pos        (11U)\r
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */\r
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\r
-#define TIM_DIER_CC4DE_Pos        (12U)\r
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */\r
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\r
-#define TIM_DIER_COMDE_Pos        (13U)\r
-#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */\r
-#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */\r
-#define TIM_DIER_TDE_Pos          (14U)\r
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */\r
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */\r
-\r
-/********************  Bit definition for TIM_SR register  ********************/\r
-#define TIM_SR_UIF_Pos            (0U)\r
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */\r
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */\r
-#define TIM_SR_CC1IF_Pos          (1U)\r
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */\r
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */\r
-#define TIM_SR_CC2IF_Pos          (2U)\r
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */\r
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */\r
-#define TIM_SR_CC3IF_Pos          (3U)\r
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */\r
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */\r
-#define TIM_SR_CC4IF_Pos          (4U)\r
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */\r
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */\r
-#define TIM_SR_COMIF_Pos          (5U)\r
-#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */\r
-#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */\r
-#define TIM_SR_TIF_Pos            (6U)\r
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */\r
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */\r
-#define TIM_SR_BIF_Pos            (7U)\r
-#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */\r
-#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */\r
-#define TIM_SR_B2IF_Pos           (8U)\r
-#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */\r
-#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */\r
-#define TIM_SR_CC1OF_Pos          (9U)\r
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */\r
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\r
-#define TIM_SR_CC2OF_Pos          (10U)\r
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */\r
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\r
-#define TIM_SR_CC3OF_Pos          (11U)\r
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */\r
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\r
-#define TIM_SR_CC4OF_Pos          (12U)\r
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */\r
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\r
-#define TIM_SR_SBIF_Pos           (13U)\r
-#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */\r
-#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */\r
-#define TIM_SR_CC5IF_Pos          (16U)\r
-#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */\r
-#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\r
-#define TIM_SR_CC6IF_Pos          (17U)\r
-#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */\r
-#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\r
-\r
-\r
-/*******************  Bit definition for TIM_EGR register  ********************/\r
-#define TIM_EGR_UG_Pos            (0U)\r
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */\r
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */\r
-#define TIM_EGR_CC1G_Pos          (1U)\r
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */\r
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */\r
-#define TIM_EGR_CC2G_Pos          (2U)\r
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */\r
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */\r
-#define TIM_EGR_CC3G_Pos          (3U)\r
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */\r
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */\r
-#define TIM_EGR_CC4G_Pos          (4U)\r
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */\r
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */\r
-#define TIM_EGR_COMG_Pos          (5U)\r
-#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */\r
-#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\r
-#define TIM_EGR_TG_Pos            (6U)\r
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */\r
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */\r
-#define TIM_EGR_BG_Pos            (7U)\r
-#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */\r
-#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */\r
-#define TIM_EGR_B2G_Pos           (8U)\r
-#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */\r
-#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */\r
-\r
-\r
-/******************  Bit definition for TIM_CCMR1 register  *******************/\r
-#define TIM_CCMR1_CC1S_Pos        (0U)\r
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */\r
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */\r
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */\r
-\r
-#define TIM_CCMR1_OC1FE_Pos       (2U)\r
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */\r
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */\r
-#define TIM_CCMR1_OC1PE_Pos       (3U)\r
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */\r
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */\r
-\r
-#define TIM_CCMR1_OC1M_Pos        (4U)\r
-#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */\r
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
-#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */\r
-#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */\r
-#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */\r
-#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */\r
-\r
-#define TIM_CCMR1_OC1CE_Pos       (7U)\r
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */\r
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */\r
-\r
-#define TIM_CCMR1_CC2S_Pos        (8U)\r
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */\r
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */\r
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */\r
-\r
-#define TIM_CCMR1_OC2FE_Pos       (10U)\r
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */\r
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */\r
-#define TIM_CCMR1_OC2PE_Pos       (11U)\r
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */\r
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */\r
-\r
-#define TIM_CCMR1_OC2M_Pos        (12U)\r
-#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */\r
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
-#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */\r
-#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */\r
-#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */\r
-#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */\r
-\r
-#define TIM_CCMR1_OC2CE_Pos       (15U)\r
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */\r
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-#define TIM_CCMR1_IC1PSC_Pos      (2U)\r
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */\r
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */\r
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */\r
-\r
-#define TIM_CCMR1_IC1F_Pos        (4U)\r
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */\r
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */\r
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */\r
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */\r
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */\r
-\r
-#define TIM_CCMR1_IC2PSC_Pos      (10U)\r
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */\r
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */\r
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */\r
-\r
-#define TIM_CCMR1_IC2F_Pos        (12U)\r
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */\r
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */\r
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */\r
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */\r
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */\r
-\r
-/******************  Bit definition for TIM_CCMR2 register  *******************/\r
-#define TIM_CCMR2_CC3S_Pos        (0U)\r
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */\r
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */\r
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */\r
-\r
-#define TIM_CCMR2_OC3FE_Pos       (2U)\r
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */\r
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */\r
-#define TIM_CCMR2_OC3PE_Pos       (3U)\r
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */\r
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */\r
-\r
-#define TIM_CCMR2_OC3M_Pos        (4U)\r
-#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */\r
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
-#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */\r
-#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */\r
-#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */\r
-#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */\r
-\r
-#define TIM_CCMR2_OC3CE_Pos       (7U)\r
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */\r
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\r
-\r
-#define TIM_CCMR2_CC4S_Pos        (8U)\r
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */\r
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */\r
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */\r
-\r
-#define TIM_CCMR2_OC4FE_Pos       (10U)\r
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */\r
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */\r
-#define TIM_CCMR2_OC4PE_Pos       (11U)\r
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */\r
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\r
-\r
-#define TIM_CCMR2_OC4M_Pos        (12U)\r
-#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */\r
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
-#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */\r
-#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */\r
-#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */\r
-#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */\r
-\r
-#define TIM_CCMR2_OC4CE_Pos       (15U)\r
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */\r
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-#define TIM_CCMR2_IC3PSC_Pos      (2U)\r
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */\r
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */\r
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */\r
-\r
-#define TIM_CCMR2_IC3F_Pos        (4U)\r
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */\r
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */\r
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */\r
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */\r
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */\r
-\r
-#define TIM_CCMR2_IC4PSC_Pos      (10U)\r
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */\r
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */\r
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */\r
-\r
-#define TIM_CCMR2_IC4F_Pos        (12U)\r
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */\r
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */\r
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */\r
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */\r
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */\r
-\r
-/******************  Bit definition for TIM_CCMR3 register  *******************/\r
-#define TIM_CCMR3_OC5FE_Pos       (2U)\r
-#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */\r
-#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\r
-#define TIM_CCMR3_OC5PE_Pos       (3U)\r
-#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */\r
-#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\r
-\r
-#define TIM_CCMR3_OC5M_Pos        (4U)\r
-#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */\r
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */\r
-#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */\r
-#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */\r
-#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */\r
-#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */\r
-\r
-#define TIM_CCMR3_OC5CE_Pos       (7U)\r
-#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */\r
-#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\r
-\r
-#define TIM_CCMR3_OC6FE_Pos       (10U)\r
-#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */\r
-#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */\r
-#define TIM_CCMR3_OC6PE_Pos       (11U)\r
-#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */\r
-#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */\r
-\r
-#define TIM_CCMR3_OC6M_Pos        (12U)\r
-#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */\r
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */\r
-#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */\r
-#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */\r
-#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */\r
-#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */\r
-\r
-#define TIM_CCMR3_OC6CE_Pos       (15U)\r
-#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */\r
-#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */\r
-\r
-/*******************  Bit definition for TIM_CCER register  *******************/\r
-#define TIM_CCER_CC1E_Pos         (0U)\r
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */\r
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\r
-#define TIM_CCER_CC1P_Pos         (1U)\r
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */\r
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\r
-#define TIM_CCER_CC1NE_Pos        (2U)\r
-#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */\r
-#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\r
-#define TIM_CCER_CC1NP_Pos        (3U)\r
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */\r
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\r
-#define TIM_CCER_CC2E_Pos         (4U)\r
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */\r
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\r
-#define TIM_CCER_CC2P_Pos         (5U)\r
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */\r
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\r
-#define TIM_CCER_CC2NE_Pos        (6U)\r
-#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */\r
-#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\r
-#define TIM_CCER_CC2NP_Pos        (7U)\r
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */\r
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\r
-#define TIM_CCER_CC3E_Pos         (8U)\r
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */\r
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\r
-#define TIM_CCER_CC3P_Pos         (9U)\r
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */\r
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\r
-#define TIM_CCER_CC3NE_Pos        (10U)\r
-#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */\r
-#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\r
-#define TIM_CCER_CC3NP_Pos        (11U)\r
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */\r
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\r
-#define TIM_CCER_CC4E_Pos         (12U)\r
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */\r
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\r
-#define TIM_CCER_CC4P_Pos         (13U)\r
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */\r
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\r
-#define TIM_CCER_CC4NP_Pos        (15U)\r
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */\r
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\r
-#define TIM_CCER_CC5E_Pos         (16U)\r
-#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */\r
-#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\r
-#define TIM_CCER_CC5P_Pos         (17U)\r
-#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */\r
-#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\r
-#define TIM_CCER_CC6E_Pos         (20U)\r
-#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */\r
-#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\r
-#define TIM_CCER_CC6P_Pos         (21U)\r
-#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */\r
-#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\r
-\r
-/*******************  Bit definition for TIM_CNT register  ********************/\r
-#define TIM_CNT_CNT_Pos           (0U)\r
-#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */\r
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */\r
-#define TIM_CNT_UIFCPY_Pos        (31U)\r
-#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */\r
-#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */\r
-\r
-/*******************  Bit definition for TIM_PSC register  ********************/\r
-#define TIM_PSC_PSC_Pos           (0U)\r
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */\r
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */\r
-\r
-/*******************  Bit definition for TIM_ARR register  ********************/\r
-#define TIM_ARR_ARR_Pos           (0U)\r
-#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */\r
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */\r
-\r
-/*******************  Bit definition for TIM_RCR register  ********************/\r
-#define TIM_RCR_REP_Pos           (0U)\r
-#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */\r
-#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\r
-\r
-/*******************  Bit definition for TIM_CCR1 register  *******************/\r
-#define TIM_CCR1_CCR1_Pos         (0U)\r
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */\r
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */\r
-\r
-/*******************  Bit definition for TIM_CCR2 register  *******************/\r
-#define TIM_CCR2_CCR2_Pos         (0U)\r
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */\r
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */\r
-\r
-/*******************  Bit definition for TIM_CCR3 register  *******************/\r
-#define TIM_CCR3_CCR3_Pos         (0U)\r
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */\r
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */\r
-\r
-/*******************  Bit definition for TIM_CCR4 register  *******************/\r
-#define TIM_CCR4_CCR4_Pos         (0U)\r
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */\r
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */\r
-\r
-/*******************  Bit definition for TIM_CCR5 register  *******************/\r
-#define TIM_CCR5_CCR5_Pos         (0U)\r
-#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */\r
-#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\r
-#define TIM_CCR5_GC5C1_Pos        (29U)\r
-#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */\r
-#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\r
-#define TIM_CCR5_GC5C2_Pos        (30U)\r
-#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */\r
-#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\r
-#define TIM_CCR5_GC5C3_Pos        (31U)\r
-#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */\r
-#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\r
-\r
-/*******************  Bit definition for TIM_CCR6 register  *******************/\r
-#define TIM_CCR6_CCR6_Pos         (0U)\r
-#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */\r
-#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */\r
-\r
-/*******************  Bit definition for TIM_BDTR register  *******************/\r
-#define TIM_BDTR_DTG_Pos          (0U)\r
-#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */\r
-#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
-#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */\r
-#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */\r
-#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */\r
-#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */\r
-#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */\r
-#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */\r
-#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */\r
-#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */\r
-\r
-#define TIM_BDTR_LOCK_Pos         (8U)\r
-#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */\r
-#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\r
-#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */\r
-#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */\r
-\r
-#define TIM_BDTR_OSSI_Pos         (10U)\r
-#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */\r
-#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\r
-#define TIM_BDTR_OSSR_Pos         (11U)\r
-#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */\r
-#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */\r
-#define TIM_BDTR_BKE_Pos          (12U)\r
-#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */\r
-#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */\r
-#define TIM_BDTR_BKP_Pos          (13U)\r
-#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */\r
-#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */\r
-#define TIM_BDTR_AOE_Pos          (14U)\r
-#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */\r
-#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */\r
-#define TIM_BDTR_MOE_Pos          (15U)\r
-#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */\r
-#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */\r
-\r
-#define TIM_BDTR_BKF_Pos          (16U)\r
-#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */\r
-#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */\r
-#define TIM_BDTR_BK2F_Pos         (20U)\r
-#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */\r
-#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */\r
-\r
-#define TIM_BDTR_BK2E_Pos         (24U)\r
-#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */\r
-#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */\r
-#define TIM_BDTR_BK2P_Pos         (25U)\r
-#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */\r
-#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */\r
-\r
-/*******************  Bit definition for TIM_DCR register  ********************/\r
-#define TIM_DCR_DBA_Pos           (0U)\r
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */\r
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\r
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */\r
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */\r
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */\r
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */\r
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */\r
-\r
-#define TIM_DCR_DBL_Pos           (8U)\r
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */\r
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\r
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */\r
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */\r
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */\r
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */\r
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */\r
-\r
-/*******************  Bit definition for TIM_DMAR register  *******************/\r
-#define TIM_DMAR_DMAB_Pos         (0U)\r
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */\r
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */\r
-\r
-/*******************  Bit definition for TIM1_OR1 register  *******************/\r
-#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)\r
-#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000003 */\r
-#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */\r
-#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000001 */\r
-#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000002 */\r
-\r
-#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)\r
-#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x0000000C */\r
-#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */\r
-#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000004 */\r
-#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000008 */\r
-\r
-#define TIM1_OR1_TI1_RMP_Pos           (4U)\r
-#define TIM1_OR1_TI1_RMP_Msk           (0x1UL << TIM1_OR1_TI1_RMP_Pos)         /*!< 0x00000010 */\r
-#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */\r
-\r
-/*******************  Bit definition for TIM1_OR2 register  *******************/\r
-#define TIM1_OR2_BKINE_Pos             (0U)\r
-#define TIM1_OR2_BKINE_Msk             (0x1UL << TIM1_OR2_BKINE_Pos)           /*!< 0x00000001 */\r
-#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */\r
-#define TIM1_OR2_BKCMP1E_Pos           (1U)\r
-#define TIM1_OR2_BKCMP1E_Msk           (0x1UL << TIM1_OR2_BKCMP1E_Pos)         /*!< 0x00000002 */\r
-#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */\r
-#define TIM1_OR2_BKCMP2E_Pos           (2U)\r
-#define TIM1_OR2_BKCMP2E_Msk           (0x1UL << TIM1_OR2_BKCMP2E_Pos)         /*!< 0x00000004 */\r
-#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */\r
-#define TIM1_OR2_BKDF1BK0E_Pos         (8U)\r
-#define TIM1_OR2_BKDF1BK0E_Msk         (0x1UL << TIM1_OR2_BKDF1BK0E_Pos)       /*!< 0x00000100 */\r
-#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */\r
-#define TIM1_OR2_BKINP_Pos             (9U)\r
-#define TIM1_OR2_BKINP_Msk             (0x1UL << TIM1_OR2_BKINP_Pos)           /*!< 0x00000200 */\r
-#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */\r
-#define TIM1_OR2_BKCMP1P_Pos           (10U)\r
-#define TIM1_OR2_BKCMP1P_Msk           (0x1UL << TIM1_OR2_BKCMP1P_Pos)         /*!< 0x00000400 */\r
-#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */\r
-#define TIM1_OR2_BKCMP2P_Pos           (11U)\r
-#define TIM1_OR2_BKCMP2P_Msk           (0x1UL << TIM1_OR2_BKCMP2P_Pos)         /*!< 0x00000800 */\r
-#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */\r
-\r
-#define TIM1_OR2_ETRSEL_Pos            (14U)\r
-#define TIM1_OR2_ETRSEL_Msk            (0x7UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x0001C000 */\r
-#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */\r
-#define TIM1_OR2_ETRSEL_0              (0x1UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00004000 */\r
-#define TIM1_OR2_ETRSEL_1              (0x2UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00008000 */\r
-#define TIM1_OR2_ETRSEL_2              (0x4UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00010000 */\r
-\r
-/*******************  Bit definition for TIM1_OR3 register  *******************/\r
-#define TIM1_OR3_BK2INE_Pos            (0U)\r
-#define TIM1_OR3_BK2INE_Msk            (0x1UL << TIM1_OR3_BK2INE_Pos)          /*!< 0x00000001 */\r
-#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */\r
-#define TIM1_OR3_BK2CMP1E_Pos          (1U)\r
-#define TIM1_OR3_BK2CMP1E_Msk          (0x1UL << TIM1_OR3_BK2CMP1E_Pos)        /*!< 0x00000002 */\r
-#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */\r
-#define TIM1_OR3_BK2CMP2E_Pos          (2U)\r
-#define TIM1_OR3_BK2CMP2E_Msk          (0x1UL << TIM1_OR3_BK2CMP2E_Pos)        /*!< 0x00000004 */\r
-#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */\r
-#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)\r
-#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1UL << TIM1_OR3_BK2DF1BK1E_Pos)      /*!< 0x00000100 */\r
-#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */\r
-#define TIM1_OR3_BK2INP_Pos            (9U)\r
-#define TIM1_OR3_BK2INP_Msk            (0x1UL << TIM1_OR3_BK2INP_Pos)          /*!< 0x00000200 */\r
-#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */\r
-#define TIM1_OR3_BK2CMP1P_Pos          (10U)\r
-#define TIM1_OR3_BK2CMP1P_Msk          (0x1UL << TIM1_OR3_BK2CMP1P_Pos)        /*!< 0x00000400 */\r
-#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */\r
-#define TIM1_OR3_BK2CMP2P_Pos          (11U)\r
-#define TIM1_OR3_BK2CMP2P_Msk          (0x1UL << TIM1_OR3_BK2CMP2P_Pos)        /*!< 0x00000800 */\r
-#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */\r
-\r
-/*******************  Bit definition for TIM8_OR1 register  *******************/\r
-#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)\r
-#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos)    /*!< 0x00000003 */\r
-#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */\r
-#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos)    /*!< 0x00000001 */\r
-#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos)    /*!< 0x00000002 */\r
-\r
-#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)\r
-#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3UL << TIM8_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x0000000C */\r
-#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */\r
-#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1UL << TIM8_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000004 */\r
-#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2UL << TIM8_OR1_ETR_ADC3_RMP_Pos)    /*!< 0x00000008 */\r
-\r
-#define TIM8_OR1_TI1_RMP_Pos           (4U)\r
-#define TIM8_OR1_TI1_RMP_Msk           (0x1UL << TIM8_OR1_TI1_RMP_Pos)         /*!< 0x00000010 */\r
-#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */\r
-\r
-/*******************  Bit definition for TIM8_OR2 register  *******************/\r
-#define TIM8_OR2_BKINE_Pos             (0U)\r
-#define TIM8_OR2_BKINE_Msk             (0x1UL << TIM8_OR2_BKINE_Pos)           /*!< 0x00000001 */\r
-#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */\r
-#define TIM8_OR2_BKCMP1E_Pos           (1U)\r
-#define TIM8_OR2_BKCMP1E_Msk           (0x1UL << TIM8_OR2_BKCMP1E_Pos)         /*!< 0x00000002 */\r
-#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */\r
-#define TIM8_OR2_BKCMP2E_Pos           (2U)\r
-#define TIM8_OR2_BKCMP2E_Msk           (0x1UL << TIM8_OR2_BKCMP2E_Pos)         /*!< 0x00000004 */\r
-#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */\r
-#define TIM8_OR2_BKDF1BK2E_Pos         (8U)\r
-#define TIM8_OR2_BKDF1BK2E_Msk         (0x1UL << TIM8_OR2_BKDF1BK2E_Pos)       /*!< 0x00000100 */\r
-#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */\r
-#define TIM8_OR2_BKINP_Pos             (9U)\r
-#define TIM8_OR2_BKINP_Msk             (0x1UL << TIM8_OR2_BKINP_Pos)           /*!< 0x00000200 */\r
-#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */\r
-#define TIM8_OR2_BKCMP1P_Pos           (10U)\r
-#define TIM8_OR2_BKCMP1P_Msk           (0x1UL << TIM8_OR2_BKCMP1P_Pos)         /*!< 0x00000400 */\r
-#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */\r
-#define TIM8_OR2_BKCMP2P_Pos           (11U)\r
-#define TIM8_OR2_BKCMP2P_Msk           (0x1UL << TIM8_OR2_BKCMP2P_Pos)         /*!< 0x00000800 */\r
-#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */\r
-\r
-#define TIM8_OR2_ETRSEL_Pos            (14U)\r
-#define TIM8_OR2_ETRSEL_Msk            (0x7UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x0001C000 */\r
-#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */\r
-#define TIM8_OR2_ETRSEL_0              (0x1UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x00004000 */\r
-#define TIM8_OR2_ETRSEL_1              (0x2UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x00008000 */\r
-#define TIM8_OR2_ETRSEL_2              (0x4UL << TIM8_OR2_ETRSEL_Pos)          /*!< 0x00010000 */\r
-\r
-/*******************  Bit definition for TIM8_OR3 register  *******************/\r
-#define TIM8_OR3_BK2INE_Pos            (0U)\r
-#define TIM8_OR3_BK2INE_Msk            (0x1UL << TIM8_OR3_BK2INE_Pos)          /*!< 0x00000001 */\r
-#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */\r
-#define TIM8_OR3_BK2CMP1E_Pos          (1U)\r
-#define TIM8_OR3_BK2CMP1E_Msk          (0x1UL << TIM8_OR3_BK2CMP1E_Pos)        /*!< 0x00000002 */\r
-#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */\r
-#define TIM8_OR3_BK2CMP2E_Pos          (2U)\r
-#define TIM8_OR3_BK2CMP2E_Msk          (0x1UL << TIM8_OR3_BK2CMP2E_Pos)        /*!< 0x00000004 */\r
-#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */\r
-#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)\r
-#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1UL << TIM8_OR3_BK2DF1BK3E_Pos)      /*!< 0x00000100 */\r
-#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */\r
-#define TIM8_OR3_BK2INP_Pos            (9U)\r
-#define TIM8_OR3_BK2INP_Msk            (0x1UL << TIM8_OR3_BK2INP_Pos)          /*!< 0x00000200 */\r
-#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */\r
-#define TIM8_OR3_BK2CMP1P_Pos          (10U)\r
-#define TIM8_OR3_BK2CMP1P_Msk          (0x1UL << TIM8_OR3_BK2CMP1P_Pos)        /*!< 0x00000400 */\r
-#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */\r
-#define TIM8_OR3_BK2CMP2P_Pos          (11U)\r
-#define TIM8_OR3_BK2CMP2P_Msk          (0x1UL << TIM8_OR3_BK2CMP2P_Pos)        /*!< 0x00000800 */\r
-#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */\r
-\r
-/*******************  Bit definition for TIM2_OR1 register  *******************/\r
-#define TIM2_OR1_ITR1_RMP_Pos     (0U)\r
-#define TIM2_OR1_ITR1_RMP_Msk     (0x1UL << TIM2_OR1_ITR1_RMP_Pos)             /*!< 0x00000001 */\r
-#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */\r
-#define TIM2_OR1_ETR1_RMP_Pos     (1U)\r
-#define TIM2_OR1_ETR1_RMP_Msk     (0x1UL << TIM2_OR1_ETR1_RMP_Pos)             /*!< 0x00000002 */\r
-#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */\r
-\r
-#define TIM2_OR1_TI4_RMP_Pos      (2U)\r
-#define TIM2_OR1_TI4_RMP_Msk      (0x3UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x0000000C */\r
-#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */\r
-#define TIM2_OR1_TI4_RMP_0        (0x1UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000004 */\r
-#define TIM2_OR1_TI4_RMP_1        (0x2UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000008 */\r
-\r
-/*******************  Bit definition for TIM2_OR2 register  *******************/\r
-#define TIM2_OR2_ETRSEL_Pos       (14U)\r
-#define TIM2_OR2_ETRSEL_Msk       (0x7UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */\r
-#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */\r
-#define TIM2_OR2_ETRSEL_0         (0x1UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00004000 */\r
-#define TIM2_OR2_ETRSEL_1         (0x2UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00008000 */\r
-#define TIM2_OR2_ETRSEL_2         (0x4UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00010000 */\r
-\r
-/*******************  Bit definition for TIM3_OR1 register  *******************/\r
-#define TIM3_OR1_TI1_RMP_Pos      (0U)\r
-#define TIM3_OR1_TI1_RMP_Msk      (0x3UL << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000003 */\r
-#define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */\r
-#define TIM3_OR1_TI1_RMP_0        (0x1UL << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000001 */\r
-#define TIM3_OR1_TI1_RMP_1        (0x2UL << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000002 */\r
-\r
-/*******************  Bit definition for TIM3_OR2 register  *******************/\r
-#define TIM3_OR2_ETRSEL_Pos       (14U)\r
-#define TIM3_OR2_ETRSEL_Msk       (0x7UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */\r
-#define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */\r
-#define TIM3_OR2_ETRSEL_0         (0x1UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00004000 */\r
-#define TIM3_OR2_ETRSEL_1         (0x2UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00008000 */\r
-#define TIM3_OR2_ETRSEL_2         (0x4UL << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00010000 */\r
-\r
-/*******************  Bit definition for TIM15_OR1 register  ******************/\r
-#define TIM15_OR1_TI1_RMP_Pos           (0U)\r
-#define TIM15_OR1_TI1_RMP_Msk           (0x1UL << TIM15_OR1_TI1_RMP_Pos)       /*!< 0x00000001 */\r
-#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */\r
-\r
-#define TIM15_OR1_ENCODER_MODE_Pos      (1U)\r
-#define TIM15_OR1_ENCODER_MODE_Msk      (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000006 */\r
-#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */\r
-#define TIM15_OR1_ENCODER_MODE_0        (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000002 */\r
-#define TIM15_OR1_ENCODER_MODE_1        (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000004 */\r
-\r
-/*******************  Bit definition for TIM15_OR2 register  ******************/\r
-#define TIM15_OR2_BKINE_Pos             (0U)\r
-#define TIM15_OR2_BKINE_Msk             (0x1UL << TIM15_OR2_BKINE_Pos)         /*!< 0x00000001 */\r
-#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */\r
-#define TIM15_OR2_BKCMP1E_Pos           (1U)\r
-#define TIM15_OR2_BKCMP1E_Msk           (0x1UL << TIM15_OR2_BKCMP1E_Pos)       /*!< 0x00000002 */\r
-#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */\r
-#define TIM15_OR2_BKCMP2E_Pos           (2U)\r
-#define TIM15_OR2_BKCMP2E_Msk           (0x1UL << TIM15_OR2_BKCMP2E_Pos)       /*!< 0x00000004 */\r
-#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */\r
-#define TIM15_OR2_BKDF1BK0E_Pos         (8U)\r
-#define TIM15_OR2_BKDF1BK0E_Msk         (0x1UL << TIM15_OR2_BKDF1BK0E_Pos)     /*!< 0x00000100 */\r
-#define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */\r
-#define TIM15_OR2_BKINP_Pos             (9U)\r
-#define TIM15_OR2_BKINP_Msk             (0x1UL << TIM15_OR2_BKINP_Pos)         /*!< 0x00000200 */\r
-#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */\r
-#define TIM15_OR2_BKCMP1P_Pos           (10U)\r
-#define TIM15_OR2_BKCMP1P_Msk           (0x1UL << TIM15_OR2_BKCMP1P_Pos)       /*!< 0x00000400 */\r
-#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */\r
-#define TIM15_OR2_BKCMP2P_Pos           (11U)\r
-#define TIM15_OR2_BKCMP2P_Msk           (0x1UL << TIM15_OR2_BKCMP2P_Pos)       /*!< 0x00000800 */\r
-#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */\r
-\r
-/*******************  Bit definition for TIM16_OR1 register  ******************/\r
-#define TIM16_OR1_TI1_RMP_Pos      (0U)\r
-#define TIM16_OR1_TI1_RMP_Msk      (0x3UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */\r
-#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */\r
-#define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */\r
-#define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */\r
-\r
-/*******************  Bit definition for TIM16_OR2 register  ******************/\r
-#define TIM16_OR2_BKINE_Pos        (0U)\r
-#define TIM16_OR2_BKINE_Msk        (0x1UL << TIM16_OR2_BKINE_Pos)              /*!< 0x00000001 */\r
-#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */\r
-#define TIM16_OR2_BKCMP1E_Pos      (1U)\r
-#define TIM16_OR2_BKCMP1E_Msk      (0x1UL << TIM16_OR2_BKCMP1E_Pos)            /*!< 0x00000002 */\r
-#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */\r
-#define TIM16_OR2_BKCMP2E_Pos      (2U)\r
-#define TIM16_OR2_BKCMP2E_Msk      (0x1UL << TIM16_OR2_BKCMP2E_Pos)            /*!< 0x00000004 */\r
-#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */\r
-#define TIM16_OR2_BKDF1BK1E_Pos    (8U)\r
-#define TIM16_OR2_BKDF1BK1E_Msk    (0x1UL << TIM16_OR2_BKDF1BK1E_Pos)          /*!< 0x00000100 */\r
-#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */\r
-#define TIM16_OR2_BKINP_Pos        (9U)\r
-#define TIM16_OR2_BKINP_Msk        (0x1UL << TIM16_OR2_BKINP_Pos)              /*!< 0x00000200 */\r
-#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */\r
-#define TIM16_OR2_BKCMP1P_Pos      (10U)\r
-#define TIM16_OR2_BKCMP1P_Msk      (0x1UL << TIM16_OR2_BKCMP1P_Pos)            /*!< 0x00000400 */\r
-#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */\r
-#define TIM16_OR2_BKCMP2P_Pos      (11U)\r
-#define TIM16_OR2_BKCMP2P_Msk      (0x1UL << TIM16_OR2_BKCMP2P_Pos)            /*!< 0x00000800 */\r
-#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */\r
-\r
-/*******************  Bit definition for TIM17_OR1 register  ******************/\r
-#define TIM17_OR1_TI1_RMP_Pos      (0U)\r
-#define TIM17_OR1_TI1_RMP_Msk      (0x3UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */\r
-#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */\r
-#define TIM17_OR1_TI1_RMP_0        (0x1UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */\r
-#define TIM17_OR1_TI1_RMP_1        (0x2UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */\r
-\r
-/*******************  Bit definition for TIM17_OR2 register  ******************/\r
-#define TIM17_OR2_BKINE_Pos        (0U)\r
-#define TIM17_OR2_BKINE_Msk        (0x1UL << TIM17_OR2_BKINE_Pos)              /*!< 0x00000001 */\r
-#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */\r
-#define TIM17_OR2_BKCMP1E_Pos      (1U)\r
-#define TIM17_OR2_BKCMP1E_Msk      (0x1UL << TIM17_OR2_BKCMP1E_Pos)            /*!< 0x00000002 */\r
-#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */\r
-#define TIM17_OR2_BKCMP2E_Pos      (2U)\r
-#define TIM17_OR2_BKCMP2E_Msk      (0x1UL << TIM17_OR2_BKCMP2E_Pos)            /*!< 0x00000004 */\r
-#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */\r
-#define TIM17_OR2_BKDF1BK2E_Pos    (8U)\r
-#define TIM17_OR2_BKDF1BK2E_Msk    (0x1UL << TIM17_OR2_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r
-#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */\r
-#define TIM17_OR2_BKINP_Pos        (9U)\r
-#define TIM17_OR2_BKINP_Msk        (0x1UL << TIM17_OR2_BKINP_Pos)              /*!< 0x00000200 */\r
-#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */\r
-#define TIM17_OR2_BKCMP1P_Pos      (10U)\r
-#define TIM17_OR2_BKCMP1P_Msk      (0x1UL << TIM17_OR2_BKCMP1P_Pos)            /*!< 0x00000400 */\r
-#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */\r
-#define TIM17_OR2_BKCMP2P_Pos      (11U)\r
-#define TIM17_OR2_BKCMP2P_Msk      (0x1UL << TIM17_OR2_BKCMP2P_Pos)            /*!< 0x00000800 */\r
-#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                         Low Power Timer (LPTIM)                            */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/******************  Bit definition for LPTIM_ISR register  *******************/\r
-#define LPTIM_ISR_CMPM_Pos          (0U)\r
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */\r
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */\r
-#define LPTIM_ISR_ARRM_Pos          (1U)\r
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */\r
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */\r
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)\r
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */\r
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */\r
-#define LPTIM_ISR_CMPOK_Pos         (3U)\r
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */\r
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */\r
-#define LPTIM_ISR_ARROK_Pos         (4U)\r
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */\r
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */\r
-#define LPTIM_ISR_UP_Pos            (5U)\r
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */\r
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */\r
-#define LPTIM_ISR_DOWN_Pos          (6U)\r
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */\r
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */\r
-\r
-/******************  Bit definition for LPTIM_ICR register  *******************/\r
-#define LPTIM_ICR_CMPMCF_Pos        (0U)\r
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */\r
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */\r
-#define LPTIM_ICR_ARRMCF_Pos        (1U)\r
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */\r
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */\r
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)\r
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */\r
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */\r
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)\r
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */\r
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */\r
-#define LPTIM_ICR_ARROKCF_Pos       (4U)\r
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */\r
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */\r
-#define LPTIM_ICR_UPCF_Pos          (5U)\r
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */\r
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */\r
-#define LPTIM_ICR_DOWNCF_Pos        (6U)\r
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */\r
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */\r
-\r
-/******************  Bit definition for LPTIM_IER register ********************/\r
-#define LPTIM_IER_CMPMIE_Pos        (0U)\r
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */\r
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */\r
-#define LPTIM_IER_ARRMIE_Pos        (1U)\r
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */\r
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */\r
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)\r
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */\r
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */\r
-#define LPTIM_IER_CMPOKIE_Pos       (3U)\r
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */\r
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */\r
-#define LPTIM_IER_ARROKIE_Pos       (4U)\r
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */\r
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */\r
-#define LPTIM_IER_UPIE_Pos          (5U)\r
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */\r
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */\r
-#define LPTIM_IER_DOWNIE_Pos        (6U)\r
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */\r
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */\r
-\r
-/******************  Bit definition for LPTIM_CFGR register *******************/\r
-#define LPTIM_CFGR_CKSEL_Pos        (0U)\r
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */\r
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */\r
-\r
-#define LPTIM_CFGR_CKPOL_Pos        (1U)\r
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */\r
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */\r
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */\r
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */\r
-\r
-#define LPTIM_CFGR_CKFLT_Pos        (3U)\r
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */\r
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */\r
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */\r
-\r
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)\r
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */\r
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */\r
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */\r
-\r
-#define LPTIM_CFGR_PRESC_Pos        (9U)\r
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */\r
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */\r
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */\r
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */\r
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */\r
-\r
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)\r
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */\r
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */\r
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */\r
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */\r
-\r
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)\r
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */\r
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */\r
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */\r
-\r
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)\r
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */\r
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */\r
-#define LPTIM_CFGR_WAVE_Pos         (20U)\r
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */\r
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */\r
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)\r
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */\r
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */\r
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)\r
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */\r
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */\r
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)\r
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */\r
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */\r
-#define LPTIM_CFGR_ENC_Pos          (24U)\r
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */\r
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */\r
-\r
-/******************  Bit definition for LPTIM_CR register  ********************/\r
-#define LPTIM_CR_ENABLE_Pos         (0U)\r
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */\r
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */\r
-#define LPTIM_CR_SNGSTRT_Pos        (1U)\r
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */\r
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */\r
-#define LPTIM_CR_CNTSTRT_Pos        (2U)\r
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */\r
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */\r
-\r
-/******************  Bit definition for LPTIM_CMP register  *******************/\r
-#define LPTIM_CMP_CMP_Pos           (0U)\r
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */\r
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */\r
-\r
-/******************  Bit definition for LPTIM_ARR register  *******************/\r
-#define LPTIM_ARR_ARR_Pos           (0U)\r
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */\r
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */\r
-\r
-/******************  Bit definition for LPTIM_CNT register  *******************/\r
-#define LPTIM_CNT_CNT_Pos           (0U)\r
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */\r
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */\r
-\r
-/******************  Bit definition for LPTIM_OR register  ********************/\r
-#define LPTIM_OR_OR_Pos             (0U)\r
-#define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */\r
-#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */\r
-#define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */\r
-#define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                      Analog Comparators (COMP)                             */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/**********************  Bit definition for COMP_CSR register  ****************/\r
-#define COMP_CSR_EN_Pos            (0U)\r
-#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */\r
-#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */\r
-\r
-#define COMP_CSR_PWRMODE_Pos       (2U)\r
-#define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */\r
-#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */\r
-#define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */\r
-#define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */\r
-\r
-#define COMP_CSR_INMSEL_Pos        (4U)\r
-#define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */\r
-#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */\r
-#define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */\r
-#define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */\r
-#define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */\r
-\r
-#define COMP_CSR_INPSEL_Pos        (7U)\r
-#define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */\r
-#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */\r
-#define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */\r
-\r
-#define COMP_CSR_WINMODE_Pos       (9U)\r
-#define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000200 */\r
-#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */\r
-\r
-#define COMP_CSR_POLARITY_Pos      (15U)\r
-#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */\r
-#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */\r
-\r
-#define COMP_CSR_HYST_Pos          (16U)\r
-#define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */\r
-#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */\r
-#define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */\r
-#define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */\r
-\r
-#define COMP_CSR_BLANKING_Pos      (18U)\r
-#define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */\r
-#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */\r
-#define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */\r
-#define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */\r
-#define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */\r
-\r
-#define COMP_CSR_BRGEN_Pos         (22U)\r
-#define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */\r
-#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */\r
-#define COMP_CSR_SCALEN_Pos        (23U)\r
-#define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */\r
-#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */\r
-\r
-#define COMP_CSR_VALUE_Pos         (30U)\r
-#define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */\r
-#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */\r
-\r
-#define COMP_CSR_LOCK_Pos          (31U)\r
-#define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */\r
-#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                         Operational Amplifier (OPAMP)                      */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*********************  Bit definition for OPAMPx_CSR register  ***************/\r
-#define OPAMP_CSR_OPAMPxEN_Pos           (0U)\r
-#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */\r
-#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */\r
-#define OPAMP_CSR_OPALPM_Pos             (1U)\r
-#define OPAMP_CSR_OPALPM_Msk             (0x1UL << OPAMP_CSR_OPALPM_Pos)       /*!< 0x00000002 */\r
-#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */\r
-\r
-#define OPAMP_CSR_OPAMODE_Pos            (2U)\r
-#define OPAMP_CSR_OPAMODE_Msk            (0x3UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x0000000C */\r
-#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */\r
-#define OPAMP_CSR_OPAMODE_0              (0x1UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000004 */\r
-#define OPAMP_CSR_OPAMODE_1              (0x2UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000008 */\r
-\r
-#define OPAMP_CSR_PGGAIN_Pos             (4U)\r
-#define OPAMP_CSR_PGGAIN_Msk             (0x3UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000030 */\r
-#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */\r
-#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000010 */\r
-#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000020 */\r
-\r
-#define OPAMP_CSR_VMSEL_Pos              (8U)\r
-#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000300 */\r
-#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */\r
-#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000100 */\r
-#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000200 */\r
-\r
-#define OPAMP_CSR_VPSEL_Pos              (10U)\r
-#define OPAMP_CSR_VPSEL_Msk              (0x1UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x00000400 */\r
-#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */\r
-#define OPAMP_CSR_CALON_Pos              (12U)\r
-#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00001000 */\r
-#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */\r
-#define OPAMP_CSR_CALSEL_Pos             (13U)\r
-#define OPAMP_CSR_CALSEL_Msk             (0x1UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00002000 */\r
-#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */\r
-#define OPAMP_CSR_USERTRIM_Pos           (14U)\r
-#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00004000 */\r
-#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */\r
-#define OPAMP_CSR_CALOUT_Pos             (15U)\r
-#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x00008000 */\r
-#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */\r
-\r
-/*********************  Bit definition for OPAMP1_CSR register  ***************/\r
-#define OPAMP1_CSR_OPAEN_Pos              (0U)\r
-#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r
-#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */\r
-#define OPAMP1_CSR_OPALPM_Pos             (1U)\r
-#define OPAMP1_CSR_OPALPM_Msk             (0x1UL << OPAMP1_CSR_OPALPM_Pos)     /*!< 0x00000002 */\r
-#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */\r
-\r
-#define OPAMP1_CSR_OPAMODE_Pos            (2U)\r
-#define OPAMP1_CSR_OPAMODE_Msk            (0x3UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x0000000C */\r
-#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */\r
-#define OPAMP1_CSR_OPAMODE_0              (0x1UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000004 */\r
-#define OPAMP1_CSR_OPAMODE_1              (0x2UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000008 */\r
-\r
-#define OPAMP1_CSR_PGAGAIN_Pos            (4U)\r
-#define OPAMP1_CSR_PGAGAIN_Msk            (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000030 */\r
-#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */\r
-#define OPAMP1_CSR_PGAGAIN_0              (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000010 */\r
-#define OPAMP1_CSR_PGAGAIN_1              (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000020 */\r
-\r
-#define OPAMP1_CSR_VMSEL_Pos              (8U)\r
-#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000300 */\r
-#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r
-#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000100 */\r
-#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000200 */\r
-\r
-#define OPAMP1_CSR_VPSEL_Pos              (10U)\r
-#define OPAMP1_CSR_VPSEL_Msk              (0x1UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x00000400 */\r
-#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r
-#define OPAMP1_CSR_CALON_Pos              (12U)\r
-#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00001000 */\r
-#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */\r
-#define OPAMP1_CSR_CALSEL_Pos             (13U)\r
-#define OPAMP1_CSR_CALSEL_Msk             (0x1UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00002000 */\r
-#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */\r
-#define OPAMP1_CSR_USERTRIM_Pos           (14U)\r
-#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00004000 */\r
-#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */\r
-#define OPAMP1_CSR_CALOUT_Pos             (15U)\r
-#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x00008000 */\r
-#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */\r
-\r
-#define OPAMP1_CSR_OPARANGE_Pos           (31U)\r
-#define OPAMP1_CSR_OPARANGE_Msk           (0x1UL << OPAMP1_CSR_OPARANGE_Pos)   /*!< 0x80000000 */\r
-#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */\r
-\r
-/*********************  Bit definition for OPAMP2_CSR register  ***************/\r
-#define OPAMP2_CSR_OPAEN_Pos              (0U)\r
-#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r
-#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */\r
-#define OPAMP2_CSR_OPALPM_Pos             (1U)\r
-#define OPAMP2_CSR_OPALPM_Msk             (0x1UL << OPAMP2_CSR_OPALPM_Pos)     /*!< 0x00000002 */\r
-#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */\r
-\r
-#define OPAMP2_CSR_OPAMODE_Pos            (2U)\r
-#define OPAMP2_CSR_OPAMODE_Msk            (0x3UL << OPAMP2_CSR_OPAMODE_Pos)    /*!< 0x0000000C */\r
-#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */\r
-#define OPAMP2_CSR_OPAMODE_0              (0x1UL << OPAMP2_CSR_OPAMODE_Pos)    /*!< 0x00000004 */\r
-#define OPAMP2_CSR_OPAMODE_1              (0x2UL << OPAMP2_CSR_OPAMODE_Pos)    /*!< 0x00000008 */\r
-\r
-#define OPAMP2_CSR_PGAGAIN_Pos            (4U)\r
-#define OPAMP2_CSR_PGAGAIN_Msk            (0x3UL << OPAMP2_CSR_PGAGAIN_Pos)    /*!< 0x00000030 */\r
-#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */\r
-#define OPAMP2_CSR_PGAGAIN_0              (0x1UL << OPAMP2_CSR_PGAGAIN_Pos)    /*!< 0x00000010 */\r
-#define OPAMP2_CSR_PGAGAIN_1              (0x2UL << OPAMP2_CSR_PGAGAIN_Pos)    /*!< 0x00000020 */\r
-\r
-#define OPAMP2_CSR_VMSEL_Pos              (8U)\r
-#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000300 */\r
-#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r
-#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000100 */\r
-#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000200 */\r
-\r
-#define OPAMP2_CSR_VPSEL_Pos              (10U)\r
-#define OPAMP2_CSR_VPSEL_Msk              (0x1UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x00000400 */\r
-#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r
-#define OPAMP2_CSR_CALON_Pos              (12U)\r
-#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00001000 */\r
-#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */\r
-#define OPAMP2_CSR_CALSEL_Pos             (13U)\r
-#define OPAMP2_CSR_CALSEL_Msk             (0x1UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00002000 */\r
-#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */\r
-#define OPAMP2_CSR_USERTRIM_Pos           (14U)\r
-#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00004000 */\r
-#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */\r
-#define OPAMP2_CSR_CALOUT_Pos             (15U)\r
-#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x00008000 */\r
-#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */\r
-\r
-/*******************  Bit definition for OPAMP_OTR register  ******************/\r
-#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)\r
-#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
-#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */\r
-#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)\r
-#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
-#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */\r
-\r
-/*******************  Bit definition for OPAMP1_OTR register  ******************/\r
-#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)\r
-#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
-#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r
-#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)\r
-#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
-#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r
-\r
-/*******************  Bit definition for OPAMP2_OTR register  ******************/\r
-#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)\r
-#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
-#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r
-#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)\r
-#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
-#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r
-\r
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/\r
-#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)\r
-#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\r
-#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */\r
-#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)\r
-#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\r
-#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */\r
-\r
-/*******************  Bit definition for OPAMP1_LPOTR register  ****************/\r
-#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)\r
-#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\r
-#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r
-#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)\r
-#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\r
-#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r
-\r
-/*******************  Bit definition for OPAMP2_LPOTR register  ****************/\r
-#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)\r
-#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\r
-#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r
-#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)\r
-#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\r
-#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                          Touch Sensing Controller (TSC)                    */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for TSC_CR register  *********************/\r
-#define TSC_CR_TSCE_Pos          (0U)\r
-#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */\r
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */\r
-#define TSC_CR_START_Pos         (1U)\r
-#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */\r
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */\r
-#define TSC_CR_AM_Pos            (2U)\r
-#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */\r
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */\r
-#define TSC_CR_SYNCPOL_Pos       (3U)\r
-#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */\r
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */\r
-#define TSC_CR_IODEF_Pos         (4U)\r
-#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */\r
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */\r
-\r
-#define TSC_CR_MCV_Pos           (5U)\r
-#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */\r
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */\r
-#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */\r
-#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */\r
-#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */\r
-\r
-#define TSC_CR_PGPSC_Pos         (12U)\r
-#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */\r
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */\r
-#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */\r
-#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */\r
-#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */\r
-\r
-#define TSC_CR_SSPSC_Pos         (15U)\r
-#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */\r
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */\r
-#define TSC_CR_SSE_Pos           (16U)\r
-#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */\r
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */\r
-\r
-#define TSC_CR_SSD_Pos           (17U)\r
-#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */\r
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */\r
-#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */\r
-#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */\r
-#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */\r
-#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */\r
-#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */\r
-#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */\r
-#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */\r
-\r
-#define TSC_CR_CTPL_Pos          (24U)\r
-#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */\r
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */\r
-#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */\r
-#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */\r
-#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */\r
-#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */\r
-\r
-#define TSC_CR_CTPH_Pos          (28U)\r
-#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */\r
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */\r
-#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */\r
-#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */\r
-#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */\r
-#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */\r
-\r
-/*******************  Bit definition for TSC_IER register  ********************/\r
-#define TSC_IER_EOAIE_Pos        (0U)\r
-#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */\r
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */\r
-#define TSC_IER_MCEIE_Pos        (1U)\r
-#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */\r
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */\r
-\r
-/*******************  Bit definition for TSC_ICR register  ********************/\r
-#define TSC_ICR_EOAIC_Pos        (0U)\r
-#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */\r
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */\r
-#define TSC_ICR_MCEIC_Pos        (1U)\r
-#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */\r
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */\r
-\r
-/*******************  Bit definition for TSC_ISR register  ********************/\r
-#define TSC_ISR_EOAF_Pos         (0U)\r
-#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */\r
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */\r
-#define TSC_ISR_MCEF_Pos         (1U)\r
-#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */\r
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */\r
-\r
-/*******************  Bit definition for TSC_IOHCR register  ******************/\r
-#define TSC_IOHCR_G1_IO1_Pos     (0U)\r
-#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */\r
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G1_IO2_Pos     (1U)\r
-#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */\r
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G1_IO3_Pos     (2U)\r
-#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */\r
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G1_IO4_Pos     (3U)\r
-#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */\r
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G2_IO1_Pos     (4U)\r
-#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */\r
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G2_IO2_Pos     (5U)\r
-#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */\r
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G2_IO3_Pos     (6U)\r
-#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */\r
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G2_IO4_Pos     (7U)\r
-#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */\r
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G3_IO1_Pos     (8U)\r
-#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */\r
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G3_IO2_Pos     (9U)\r
-#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */\r
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G3_IO3_Pos     (10U)\r
-#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */\r
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G3_IO4_Pos     (11U)\r
-#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */\r
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G4_IO1_Pos     (12U)\r
-#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */\r
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G4_IO2_Pos     (13U)\r
-#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */\r
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G4_IO3_Pos     (14U)\r
-#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */\r
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G4_IO4_Pos     (15U)\r
-#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */\r
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G5_IO1_Pos     (16U)\r
-#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */\r
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G5_IO2_Pos     (17U)\r
-#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */\r
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G5_IO3_Pos     (18U)\r
-#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */\r
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G5_IO4_Pos     (19U)\r
-#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */\r
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G6_IO1_Pos     (20U)\r
-#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */\r
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G6_IO2_Pos     (21U)\r
-#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */\r
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G6_IO3_Pos     (22U)\r
-#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */\r
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G6_IO4_Pos     (23U)\r
-#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */\r
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G7_IO1_Pos     (24U)\r
-#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */\r
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G7_IO2_Pos     (25U)\r
-#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */\r
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G7_IO3_Pos     (26U)\r
-#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */\r
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G7_IO4_Pos     (27U)\r
-#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */\r
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G8_IO1_Pos     (28U)\r
-#define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)               /*!< 0x10000000 */\r
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G8_IO2_Pos     (29U)\r
-#define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)               /*!< 0x20000000 */\r
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G8_IO3_Pos     (30U)\r
-#define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)               /*!< 0x40000000 */\r
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */\r
-#define TSC_IOHCR_G8_IO4_Pos     (31U)\r
-#define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)               /*!< 0x80000000 */\r
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */\r
-\r
-/*******************  Bit definition for TSC_IOASCR register  *****************/\r
-#define TSC_IOASCR_G1_IO1_Pos    (0U)\r
-#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */\r
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */\r
-#define TSC_IOASCR_G1_IO2_Pos    (1U)\r
-#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */\r
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */\r
-#define TSC_IOASCR_G1_IO3_Pos    (2U)\r
-#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */\r
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */\r
-#define TSC_IOASCR_G1_IO4_Pos    (3U)\r
-#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */\r
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */\r
-#define TSC_IOASCR_G2_IO1_Pos    (4U)\r
-#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */\r
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */\r
-#define TSC_IOASCR_G2_IO2_Pos    (5U)\r
-#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */\r
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */\r
-#define TSC_IOASCR_G2_IO3_Pos    (6U)\r
-#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */\r
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */\r
-#define TSC_IOASCR_G2_IO4_Pos    (7U)\r
-#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */\r
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */\r
-#define TSC_IOASCR_G3_IO1_Pos    (8U)\r
-#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */\r
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */\r
-#define TSC_IOASCR_G3_IO2_Pos    (9U)\r
-#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */\r
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */\r
-#define TSC_IOASCR_G3_IO3_Pos    (10U)\r
-#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */\r
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */\r
-#define TSC_IOASCR_G3_IO4_Pos    (11U)\r
-#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */\r
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */\r
-#define TSC_IOASCR_G4_IO1_Pos    (12U)\r
-#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */\r
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */\r
-#define TSC_IOASCR_G4_IO2_Pos    (13U)\r
-#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */\r
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */\r
-#define TSC_IOASCR_G4_IO3_Pos    (14U)\r
-#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */\r
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */\r
-#define TSC_IOASCR_G4_IO4_Pos    (15U)\r
-#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */\r
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */\r
-#define TSC_IOASCR_G5_IO1_Pos    (16U)\r
-#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */\r
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */\r
-#define TSC_IOASCR_G5_IO2_Pos    (17U)\r
-#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */\r
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */\r
-#define TSC_IOASCR_G5_IO3_Pos    (18U)\r
-#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */\r
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */\r
-#define TSC_IOASCR_G5_IO4_Pos    (19U)\r
-#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */\r
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */\r
-#define TSC_IOASCR_G6_IO1_Pos    (20U)\r
-#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */\r
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */\r
-#define TSC_IOASCR_G6_IO2_Pos    (21U)\r
-#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */\r
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */\r
-#define TSC_IOASCR_G6_IO3_Pos    (22U)\r
-#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */\r
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */\r
-#define TSC_IOASCR_G6_IO4_Pos    (23U)\r
-#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */\r
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */\r
-#define TSC_IOASCR_G7_IO1_Pos    (24U)\r
-#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */\r
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */\r
-#define TSC_IOASCR_G7_IO2_Pos    (25U)\r
-#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */\r
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */\r
-#define TSC_IOASCR_G7_IO3_Pos    (26U)\r
-#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */\r
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */\r
-#define TSC_IOASCR_G7_IO4_Pos    (27U)\r
-#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */\r
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */\r
-#define TSC_IOASCR_G8_IO1_Pos    (28U)\r
-#define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)              /*!< 0x10000000 */\r
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */\r
-#define TSC_IOASCR_G8_IO2_Pos    (29U)\r
-#define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)              /*!< 0x20000000 */\r
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */\r
-#define TSC_IOASCR_G8_IO3_Pos    (30U)\r
-#define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)              /*!< 0x40000000 */\r
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */\r
-#define TSC_IOASCR_G8_IO4_Pos    (31U)\r
-#define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)              /*!< 0x80000000 */\r
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */\r
-\r
-/*******************  Bit definition for TSC_IOSCR register  ******************/\r
-#define TSC_IOSCR_G1_IO1_Pos     (0U)\r
-#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */\r
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */\r
-#define TSC_IOSCR_G1_IO2_Pos     (1U)\r
-#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */\r
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */\r
-#define TSC_IOSCR_G1_IO3_Pos     (2U)\r
-#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */\r
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */\r
-#define TSC_IOSCR_G1_IO4_Pos     (3U)\r
-#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */\r
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */\r
-#define TSC_IOSCR_G2_IO1_Pos     (4U)\r
-#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */\r
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */\r
-#define TSC_IOSCR_G2_IO2_Pos     (5U)\r
-#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */\r
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */\r
-#define TSC_IOSCR_G2_IO3_Pos     (6U)\r
-#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */\r
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */\r
-#define TSC_IOSCR_G2_IO4_Pos     (7U)\r
-#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */\r
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */\r
-#define TSC_IOSCR_G3_IO1_Pos     (8U)\r
-#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */\r
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */\r
-#define TSC_IOSCR_G3_IO2_Pos     (9U)\r
-#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */\r
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */\r
-#define TSC_IOSCR_G3_IO3_Pos     (10U)\r
-#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */\r
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */\r
-#define TSC_IOSCR_G3_IO4_Pos     (11U)\r
-#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */\r
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */\r
-#define TSC_IOSCR_G4_IO1_Pos     (12U)\r
-#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */\r
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */\r
-#define TSC_IOSCR_G4_IO2_Pos     (13U)\r
-#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */\r
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */\r
-#define TSC_IOSCR_G4_IO3_Pos     (14U)\r
-#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */\r
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */\r
-#define TSC_IOSCR_G4_IO4_Pos     (15U)\r
-#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */\r
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */\r
-#define TSC_IOSCR_G5_IO1_Pos     (16U)\r
-#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */\r
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */\r
-#define TSC_IOSCR_G5_IO2_Pos     (17U)\r
-#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */\r
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */\r
-#define TSC_IOSCR_G5_IO3_Pos     (18U)\r
-#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */\r
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */\r
-#define TSC_IOSCR_G5_IO4_Pos     (19U)\r
-#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */\r
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */\r
-#define TSC_IOSCR_G6_IO1_Pos     (20U)\r
-#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */\r
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */\r
-#define TSC_IOSCR_G6_IO2_Pos     (21U)\r
-#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */\r
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */\r
-#define TSC_IOSCR_G6_IO3_Pos     (22U)\r
-#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */\r
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */\r
-#define TSC_IOSCR_G6_IO4_Pos     (23U)\r
-#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */\r
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */\r
-#define TSC_IOSCR_G7_IO1_Pos     (24U)\r
-#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */\r
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */\r
-#define TSC_IOSCR_G7_IO2_Pos     (25U)\r
-#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */\r
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */\r
-#define TSC_IOSCR_G7_IO3_Pos     (26U)\r
-#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */\r
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */\r
-#define TSC_IOSCR_G7_IO4_Pos     (27U)\r
-#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */\r
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */\r
-#define TSC_IOSCR_G8_IO1_Pos     (28U)\r
-#define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)               /*!< 0x10000000 */\r
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */\r
-#define TSC_IOSCR_G8_IO2_Pos     (29U)\r
-#define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)               /*!< 0x20000000 */\r
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */\r
-#define TSC_IOSCR_G8_IO3_Pos     (30U)\r
-#define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)               /*!< 0x40000000 */\r
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */\r
-#define TSC_IOSCR_G8_IO4_Pos     (31U)\r
-#define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)               /*!< 0x80000000 */\r
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */\r
-\r
-/*******************  Bit definition for TSC_IOCCR register  ******************/\r
-#define TSC_IOCCR_G1_IO1_Pos     (0U)\r
-#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */\r
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */\r
-#define TSC_IOCCR_G1_IO2_Pos     (1U)\r
-#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */\r
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */\r
-#define TSC_IOCCR_G1_IO3_Pos     (2U)\r
-#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */\r
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */\r
-#define TSC_IOCCR_G1_IO4_Pos     (3U)\r
-#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */\r
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */\r
-#define TSC_IOCCR_G2_IO1_Pos     (4U)\r
-#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */\r
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */\r
-#define TSC_IOCCR_G2_IO2_Pos     (5U)\r
-#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */\r
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */\r
-#define TSC_IOCCR_G2_IO3_Pos     (6U)\r
-#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */\r
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */\r
-#define TSC_IOCCR_G2_IO4_Pos     (7U)\r
-#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */\r
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */\r
-#define TSC_IOCCR_G3_IO1_Pos     (8U)\r
-#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */\r
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */\r
-#define TSC_IOCCR_G3_IO2_Pos     (9U)\r
-#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */\r
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */\r
-#define TSC_IOCCR_G3_IO3_Pos     (10U)\r
-#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */\r
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */\r
-#define TSC_IOCCR_G3_IO4_Pos     (11U)\r
-#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */\r
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */\r
-#define TSC_IOCCR_G4_IO1_Pos     (12U)\r
-#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */\r
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */\r
-#define TSC_IOCCR_G4_IO2_Pos     (13U)\r
-#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */\r
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */\r
-#define TSC_IOCCR_G4_IO3_Pos     (14U)\r
-#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */\r
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */\r
-#define TSC_IOCCR_G4_IO4_Pos     (15U)\r
-#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */\r
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */\r
-#define TSC_IOCCR_G5_IO1_Pos     (16U)\r
-#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */\r
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */\r
-#define TSC_IOCCR_G5_IO2_Pos     (17U)\r
-#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */\r
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */\r
-#define TSC_IOCCR_G5_IO3_Pos     (18U)\r
-#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */\r
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */\r
-#define TSC_IOCCR_G5_IO4_Pos     (19U)\r
-#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */\r
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */\r
-#define TSC_IOCCR_G6_IO1_Pos     (20U)\r
-#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */\r
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */\r
-#define TSC_IOCCR_G6_IO2_Pos     (21U)\r
-#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */\r
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */\r
-#define TSC_IOCCR_G6_IO3_Pos     (22U)\r
-#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */\r
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */\r
-#define TSC_IOCCR_G6_IO4_Pos     (23U)\r
-#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */\r
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */\r
-#define TSC_IOCCR_G7_IO1_Pos     (24U)\r
-#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */\r
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */\r
-#define TSC_IOCCR_G7_IO2_Pos     (25U)\r
-#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */\r
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */\r
-#define TSC_IOCCR_G7_IO3_Pos     (26U)\r
-#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */\r
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */\r
-#define TSC_IOCCR_G7_IO4_Pos     (27U)\r
-#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */\r
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */\r
-#define TSC_IOCCR_G8_IO1_Pos     (28U)\r
-#define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)               /*!< 0x10000000 */\r
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */\r
-#define TSC_IOCCR_G8_IO2_Pos     (29U)\r
-#define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)               /*!< 0x20000000 */\r
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */\r
-#define TSC_IOCCR_G8_IO3_Pos     (30U)\r
-#define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)               /*!< 0x40000000 */\r
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */\r
-#define TSC_IOCCR_G8_IO4_Pos     (31U)\r
-#define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)               /*!< 0x80000000 */\r
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */\r
-\r
-/*******************  Bit definition for TSC_IOGCSR register  *****************/\r
-#define TSC_IOGCSR_G1E_Pos       (0U)\r
-#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */\r
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */\r
-#define TSC_IOGCSR_G2E_Pos       (1U)\r
-#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */\r
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */\r
-#define TSC_IOGCSR_G3E_Pos       (2U)\r
-#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */\r
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */\r
-#define TSC_IOGCSR_G4E_Pos       (3U)\r
-#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */\r
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */\r
-#define TSC_IOGCSR_G5E_Pos       (4U)\r
-#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */\r
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */\r
-#define TSC_IOGCSR_G6E_Pos       (5U)\r
-#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */\r
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */\r
-#define TSC_IOGCSR_G7E_Pos       (6U)\r
-#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */\r
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */\r
-#define TSC_IOGCSR_G8E_Pos       (7U)\r
-#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                 /*!< 0x00000080 */\r
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */\r
-#define TSC_IOGCSR_G1S_Pos       (16U)\r
-#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */\r
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */\r
-#define TSC_IOGCSR_G2S_Pos       (17U)\r
-#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */\r
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */\r
-#define TSC_IOGCSR_G3S_Pos       (18U)\r
-#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */\r
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */\r
-#define TSC_IOGCSR_G4S_Pos       (19U)\r
-#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */\r
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */\r
-#define TSC_IOGCSR_G5S_Pos       (20U)\r
-#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */\r
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */\r
-#define TSC_IOGCSR_G6S_Pos       (21U)\r
-#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */\r
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */\r
-#define TSC_IOGCSR_G7S_Pos       (22U)\r
-#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */\r
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */\r
-#define TSC_IOGCSR_G8S_Pos       (23U)\r
-#define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                 /*!< 0x00800000 */\r
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */\r
-\r
-/*******************  Bit definition for TSC_IOGXCR register  *****************/\r
-#define TSC_IOGXCR_CNT_Pos       (0U)\r
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */\r
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/******************  Bit definition for USART_CR1 register  *******************/\r
-#define USART_CR1_UE_Pos              (0U)\r
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)              /*!< 0x00000001 */\r
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */\r
-#define USART_CR1_UESM_Pos            (1U)\r
-#define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)            /*!< 0x00000002 */\r
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */\r
-#define USART_CR1_RE_Pos              (2U)\r
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)              /*!< 0x00000004 */\r
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */\r
-#define USART_CR1_TE_Pos              (3U)\r
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)              /*!< 0x00000008 */\r
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */\r
-#define USART_CR1_IDLEIE_Pos          (4U)\r
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)          /*!< 0x00000010 */\r
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */\r
-#define USART_CR1_RXNEIE_Pos          (5U)\r
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)          /*!< 0x00000020 */\r
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */\r
-#define USART_CR1_TCIE_Pos            (6U)\r
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)            /*!< 0x00000040 */\r
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */\r
-#define USART_CR1_TXEIE_Pos           (7U)\r
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)           /*!< 0x00000080 */\r
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */\r
-#define USART_CR1_PEIE_Pos            (8U)\r
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)            /*!< 0x00000100 */\r
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */\r
-#define USART_CR1_PS_Pos              (9U)\r
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)              /*!< 0x00000200 */\r
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */\r
-#define USART_CR1_PCE_Pos             (10U)\r
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)             /*!< 0x00000400 */\r
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */\r
-#define USART_CR1_WAKE_Pos            (11U)\r
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)            /*!< 0x00000800 */\r
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */\r
-#define USART_CR1_M_Pos               (12U)\r
-#define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)           /*!< 0x10001000 */\r
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */\r
-#define USART_CR1_M0_Pos              (12U)\r
-#define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)              /*!< 0x00001000 */\r
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */\r
-#define USART_CR1_MME_Pos             (13U)\r
-#define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)             /*!< 0x00002000 */\r
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */\r
-#define USART_CR1_CMIE_Pos            (14U)\r
-#define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)            /*!< 0x00004000 */\r
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */\r
-#define USART_CR1_OVER8_Pos           (15U)\r
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)           /*!< 0x00008000 */\r
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */\r
-#define USART_CR1_DEDT_Pos            (16U)\r
-#define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)           /*!< 0x001F0000 */\r
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
-#define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)           /*!< 0x00010000 */\r
-#define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)           /*!< 0x00020000 */\r
-#define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)           /*!< 0x00040000 */\r
-#define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)           /*!< 0x00080000 */\r
-#define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)           /*!< 0x00100000 */\r
-#define USART_CR1_DEAT_Pos            (21U)\r
-#define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)           /*!< 0x03E00000 */\r
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
-#define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)           /*!< 0x00200000 */\r
-#define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)           /*!< 0x00400000 */\r
-#define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)           /*!< 0x00800000 */\r
-#define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)           /*!< 0x01000000 */\r
-#define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)           /*!< 0x02000000 */\r
-#define USART_CR1_RTOIE_Pos           (26U)\r
-#define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)           /*!< 0x04000000 */\r
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */\r
-#define USART_CR1_EOBIE_Pos           (27U)\r
-#define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)           /*!< 0x08000000 */\r
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */\r
-#define USART_CR1_M1_Pos              (28U)\r
-#define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)              /*!< 0x10000000 */\r
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */\r
-\r
-/******************  Bit definition for USART_CR2 register  *******************/\r
-#define USART_CR2_ADDM7_Pos           (4U)\r
-#define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)           /*!< 0x00000010 */\r
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */\r
-#define USART_CR2_LBDL_Pos            (5U)\r
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)            /*!< 0x00000020 */\r
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */\r
-#define USART_CR2_LBDIE_Pos           (6U)\r
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)           /*!< 0x00000040 */\r
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */\r
-#define USART_CR2_LBCL_Pos            (8U)\r
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)            /*!< 0x00000100 */\r
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */\r
-#define USART_CR2_CPHA_Pos            (9U)\r
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)            /*!< 0x00000200 */\r
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */\r
-#define USART_CR2_CPOL_Pos            (10U)\r
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)            /*!< 0x00000400 */\r
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */\r
-#define USART_CR2_CLKEN_Pos           (11U)\r
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)           /*!< 0x00000800 */\r
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */\r
-#define USART_CR2_STOP_Pos            (12U)\r
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)            /*!< 0x00003000 */\r
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */\r
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)            /*!< 0x00001000 */\r
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)            /*!< 0x00002000 */\r
-#define USART_CR2_LINEN_Pos           (14U)\r
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)           /*!< 0x00004000 */\r
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */\r
-#define USART_CR2_SWAP_Pos            (15U)\r
-#define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)            /*!< 0x00008000 */\r
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */\r
-#define USART_CR2_RXINV_Pos           (16U)\r
-#define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)           /*!< 0x00010000 */\r
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */\r
-#define USART_CR2_TXINV_Pos           (17U)\r
-#define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)           /*!< 0x00020000 */\r
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */\r
-#define USART_CR2_DATAINV_Pos         (18U)\r
-#define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)         /*!< 0x00040000 */\r
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */\r
-#define USART_CR2_MSBFIRST_Pos        (19U)\r
-#define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)        /*!< 0x00080000 */\r
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */\r
-#define USART_CR2_ABREN_Pos           (20U)\r
-#define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)           /*!< 0x00100000 */\r
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/\r
-#define USART_CR2_ABRMODE_Pos         (21U)\r
-#define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00600000 */\r
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
-#define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00200000 */\r
-#define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00400000 */\r
-#define USART_CR2_RTOEN_Pos           (23U)\r
-#define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)           /*!< 0x00800000 */\r
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */\r
-#define USART_CR2_ADD_Pos             (24U)\r
-#define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)            /*!< 0xFF000000 */\r
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */\r
-\r
-/******************  Bit definition for USART_CR3 register  *******************/\r
-#define USART_CR3_EIE_Pos             (0U)\r
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)             /*!< 0x00000001 */\r
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */\r
-#define USART_CR3_IREN_Pos            (1U)\r
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)            /*!< 0x00000002 */\r
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */\r
-#define USART_CR3_IRLP_Pos            (2U)\r
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)            /*!< 0x00000004 */\r
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */\r
-#define USART_CR3_HDSEL_Pos           (3U)\r
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)           /*!< 0x00000008 */\r
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */\r
-#define USART_CR3_NACK_Pos            (4U)\r
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)            /*!< 0x00000010 */\r
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */\r
-#define USART_CR3_SCEN_Pos            (5U)\r
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)            /*!< 0x00000020 */\r
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */\r
-#define USART_CR3_DMAR_Pos            (6U)\r
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)            /*!< 0x00000040 */\r
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */\r
-#define USART_CR3_DMAT_Pos            (7U)\r
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)            /*!< 0x00000080 */\r
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */\r
-#define USART_CR3_RTSE_Pos            (8U)\r
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)            /*!< 0x00000100 */\r
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */\r
-#define USART_CR3_CTSE_Pos            (9U)\r
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)            /*!< 0x00000200 */\r
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */\r
-#define USART_CR3_CTSIE_Pos           (10U)\r
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)           /*!< 0x00000400 */\r
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */\r
-#define USART_CR3_ONEBIT_Pos          (11U)\r
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)          /*!< 0x00000800 */\r
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */\r
-#define USART_CR3_OVRDIS_Pos          (12U)\r
-#define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)          /*!< 0x00001000 */\r
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */\r
-#define USART_CR3_DDRE_Pos            (13U)\r
-#define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)            /*!< 0x00002000 */\r
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */\r
-#define USART_CR3_DEM_Pos             (14U)\r
-#define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)             /*!< 0x00004000 */\r
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */\r
-#define USART_CR3_DEP_Pos             (15U)\r
-#define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)             /*!< 0x00008000 */\r
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */\r
-#define USART_CR3_SCARCNT_Pos         (17U)\r
-#define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)         /*!< 0x000E0000 */\r
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
-#define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00020000 */\r
-#define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00040000 */\r
-#define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00080000 */\r
-#define USART_CR3_WUS_Pos             (20U)\r
-#define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)             /*!< 0x00300000 */\r
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\r
-#define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)             /*!< 0x00100000 */\r
-#define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)             /*!< 0x00200000 */\r
-#define USART_CR3_WUFIE_Pos           (22U)\r
-#define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)           /*!< 0x00400000 */\r
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */\r
-#define USART_CR3_UCESM_Pos           (23U)\r
-#define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)           /*!< 0x02000000 */\r
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< USART Clock enable in Stop mode */\r
-\r
-/******************  Bit definition for USART_BRR register  *******************/\r
-#define USART_BRR_DIV_FRACTION_Pos    (0U)\r
-#define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)    /*!< 0x0000000F */\r
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */\r
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)\r
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)  /*!< 0x0000FFF0 */\r
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */\r
-\r
-/******************  Bit definition for USART_GTPR register  ******************/\r
-#define USART_GTPR_PSC_Pos            (0U)\r
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)           /*!< 0x000000FF */\r
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */\r
-#define USART_GTPR_GT_Pos             (8U)\r
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)            /*!< 0x0000FF00 */\r
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */\r
-\r
-/*******************  Bit definition for USART_RTOR register  *****************/\r
-#define USART_RTOR_RTO_Pos            (0U)\r
-#define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)       /*!< 0x00FFFFFF */\r
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */\r
-#define USART_RTOR_BLEN_Pos           (24U)\r
-#define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)          /*!< 0xFF000000 */\r
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */\r
-\r
-/*******************  Bit definition for USART_RQR register  ******************/\r
-#define USART_RQR_ABRRQ_Pos           (0U)\r
-#define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)           /*!< 0x00000001 */\r
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */\r
-#define USART_RQR_SBKRQ_Pos           (1U)\r
-#define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)           /*!< 0x00000002 */\r
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */\r
-#define USART_RQR_MMRQ_Pos            (2U)\r
-#define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)            /*!< 0x00000004 */\r
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */\r
-#define USART_RQR_RXFRQ_Pos           (3U)\r
-#define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)           /*!< 0x00000008 */\r
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */\r
-#define USART_RQR_TXFRQ_Pos           (4U)\r
-#define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)           /*!< 0x00000010 */\r
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */\r
-\r
-/*******************  Bit definition for USART_ISR register  ******************/\r
-#define USART_ISR_PE_Pos              (0U)\r
-#define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)              /*!< 0x00000001 */\r
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */\r
-#define USART_ISR_FE_Pos              (1U)\r
-#define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)              /*!< 0x00000002 */\r
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */\r
-#define USART_ISR_NE_Pos              (2U)\r
-#define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)              /*!< 0x00000004 */\r
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise Error detected Flag */\r
-#define USART_ISR_ORE_Pos             (3U)\r
-#define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)             /*!< 0x00000008 */\r
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */\r
-#define USART_ISR_IDLE_Pos            (4U)\r
-#define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)            /*!< 0x00000010 */\r
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */\r
-#define USART_ISR_RXNE_Pos            (5U)\r
-#define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)            /*!< 0x00000020 */\r
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */\r
-#define USART_ISR_TC_Pos              (6U)\r
-#define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)              /*!< 0x00000040 */\r
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */\r
-#define USART_ISR_TXE_Pos             (7U)\r
-#define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)             /*!< 0x00000080 */\r
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */\r
-#define USART_ISR_LBDF_Pos            (8U)\r
-#define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)            /*!< 0x00000100 */\r
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */\r
-#define USART_ISR_CTSIF_Pos           (9U)\r
-#define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)           /*!< 0x00000200 */\r
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */\r
-#define USART_ISR_CTS_Pos             (10U)\r
-#define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)             /*!< 0x00000400 */\r
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */\r
-#define USART_ISR_RTOF_Pos            (11U)\r
-#define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)            /*!< 0x00000800 */\r
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */\r
-#define USART_ISR_EOBF_Pos            (12U)\r
-#define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)            /*!< 0x00001000 */\r
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */\r
-#define USART_ISR_ABRE_Pos            (14U)\r
-#define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)            /*!< 0x00004000 */\r
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */\r
-#define USART_ISR_ABRF_Pos            (15U)\r
-#define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)            /*!< 0x00008000 */\r
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */\r
-#define USART_ISR_BUSY_Pos            (16U)\r
-#define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)            /*!< 0x00010000 */\r
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */\r
-#define USART_ISR_CMF_Pos             (17U)\r
-#define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)             /*!< 0x00020000 */\r
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */\r
-#define USART_ISR_SBKF_Pos            (18U)\r
-#define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)            /*!< 0x00040000 */\r
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */\r
-#define USART_ISR_RWU_Pos             (19U)\r
-#define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)             /*!< 0x00080000 */\r
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */\r
-#define USART_ISR_WUF_Pos             (20U)\r
-#define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)             /*!< 0x00100000 */\r
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */\r
-#define USART_ISR_TEACK_Pos           (21U)\r
-#define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)           /*!< 0x00200000 */\r
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */\r
-#define USART_ISR_REACK_Pos           (22U)\r
-#define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)           /*!< 0x00400000 */\r
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */\r
-\r
-/*******************  Bit definition for USART_ICR register  ******************/\r
-#define USART_ICR_PECF_Pos            (0U)\r
-#define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)            /*!< 0x00000001 */\r
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */\r
-#define USART_ICR_FECF_Pos            (1U)\r
-#define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)            /*!< 0x00000002 */\r
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */\r
-#define USART_ICR_NECF_Pos            (2U)\r
-#define USART_ICR_NECF_Msk            (0x1UL << USART_ICR_NECF_Pos)            /*!< 0x00000004 */\r
-#define USART_ICR_NECF                USART_ICR_NECF_Msk                       /*!< Noise Error detected Clear Flag */\r
-#define USART_ICR_ORECF_Pos           (3U)\r
-#define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)           /*!< 0x00000008 */\r
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */\r
-#define USART_ICR_IDLECF_Pos          (4U)\r
-#define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)          /*!< 0x00000010 */\r
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */\r
-#define USART_ICR_TCCF_Pos            (6U)\r
-#define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)            /*!< 0x00000040 */\r
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */\r
-#define USART_ICR_LBDCF_Pos           (8U)\r
-#define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)           /*!< 0x00000100 */\r
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */\r
-#define USART_ICR_CTSCF_Pos           (9U)\r
-#define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)           /*!< 0x00000200 */\r
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */\r
-#define USART_ICR_RTOCF_Pos           (11U)\r
-#define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)           /*!< 0x00000800 */\r
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */\r
-#define USART_ICR_EOBCF_Pos           (12U)\r
-#define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)           /*!< 0x00001000 */\r
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */\r
-#define USART_ICR_CMCF_Pos            (17U)\r
-#define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)            /*!< 0x00020000 */\r
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */\r
-#define USART_ICR_WUCF_Pos            (20U)\r
-#define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)            /*!< 0x00100000 */\r
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */\r
-\r
-/* Legacy defines */\r
-#define USART_ICR_NCF_Pos             USART_ICR_NECF_Pos\r
-#define USART_ICR_NCF_Msk             USART_ICR_NECF_Msk\r
-#define USART_ICR_NCF                 USART_ICR_NECF\r
-\r
-/*******************  Bit definition for USART_RDR register  ******************/\r
-#define USART_RDR_RDR_Pos             (0U)\r
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */\r
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */\r
-\r
-/*******************  Bit definition for USART_TDR register  ******************/\r
-#define USART_TDR_TDR_Pos             (0U)\r
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */\r
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*           Single Wire Protocol Master Interface (SWPMI)                    */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-\r
-/*******************  Bit definition for SWPMI_CR register   ********************/\r
-#define SWPMI_CR_RXDMA_Pos       (0U)\r
-#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */\r
-#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */\r
-#define SWPMI_CR_TXDMA_Pos       (1U)\r
-#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */\r
-#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */\r
-#define SWPMI_CR_RXMODE_Pos      (2U)\r
-#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */\r
-#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */\r
-#define SWPMI_CR_TXMODE_Pos      (3U)\r
-#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */\r
-#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */\r
-#define SWPMI_CR_LPBK_Pos        (4U)\r
-#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */\r
-#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */\r
-#define SWPMI_CR_SWPACT_Pos      (5U)\r
-#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */\r
-#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */\r
-#define SWPMI_CR_DEACT_Pos       (10U)\r
-#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */\r
-#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */\r
-\r
-/*******************  Bit definition for SWPMI_BRR register  ********************/\r
-#define SWPMI_BRR_BR_Pos         (0U)\r
-#define SWPMI_BRR_BR_Msk         (0x3FUL << SWPMI_BRR_BR_Pos)                  /*!< 0x0000003F */\r
-#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */\r
-\r
-/*******************  Bit definition for SWPMI_ISR register  ********************/\r
-#define SWPMI_ISR_RXBFF_Pos      (0U)\r
-#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */\r
-#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */\r
-#define SWPMI_ISR_TXBEF_Pos      (1U)\r
-#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */\r
-#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */\r
-#define SWPMI_ISR_RXBERF_Pos     (2U)\r
-#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */\r
-#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */\r
-#define SWPMI_ISR_RXOVRF_Pos     (3U)\r
-#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */\r
-#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */\r
-#define SWPMI_ISR_TXUNRF_Pos     (4U)\r
-#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */\r
-#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */\r
-#define SWPMI_ISR_RXNE_Pos       (5U)\r
-#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */\r
-#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */\r
-#define SWPMI_ISR_TXE_Pos        (6U)\r
-#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */\r
-#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */\r
-#define SWPMI_ISR_TCF_Pos        (7U)\r
-#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */\r
-#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */\r
-#define SWPMI_ISR_SRF_Pos        (8U)\r
-#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */\r
-#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */\r
-#define SWPMI_ISR_SUSP_Pos       (9U)\r
-#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */\r
-#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */\r
-#define SWPMI_ISR_DEACTF_Pos     (10U)\r
-#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */\r
-#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */\r
-\r
-/*******************  Bit definition for SWPMI_ICR register  ********************/\r
-#define SWPMI_ICR_CRXBFF_Pos     (0U)\r
-#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */\r
-#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */\r
-#define SWPMI_ICR_CTXBEF_Pos     (1U)\r
-#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */\r
-#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */\r
-#define SWPMI_ICR_CRXBERF_Pos    (2U)\r
-#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */\r
-#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */\r
-#define SWPMI_ICR_CRXOVRF_Pos    (3U)\r
-#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */\r
-#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */\r
-#define SWPMI_ICR_CTXUNRF_Pos    (4U)\r
-#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */\r
-#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */\r
-#define SWPMI_ICR_CTCF_Pos       (7U)\r
-#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */\r
-#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */\r
-#define SWPMI_ICR_CSRF_Pos       (8U)\r
-#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */\r
-#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */\r
-\r
-/*******************  Bit definition for SWPMI_IER register  ********************/\r
-#define SWPMI_IER_SRIE_Pos       (8U)\r
-#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */\r
-#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */\r
-#define SWPMI_IER_TCIE_Pos       (7U)\r
-#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */\r
-#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */\r
-#define SWPMI_IER_TIE_Pos        (6U)\r
-#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */\r
-#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */\r
-#define SWPMI_IER_RIE_Pos        (5U)\r
-#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */\r
-#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */\r
-#define SWPMI_IER_TXUNRIE_Pos    (4U)\r
-#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */\r
-#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */\r
-#define SWPMI_IER_RXOVRIE_Pos    (3U)\r
-#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */\r
-#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */\r
-#define SWPMI_IER_RXBERIE_Pos    (2U)\r
-#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */\r
-#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */\r
-#define SWPMI_IER_TXBEIE_Pos     (1U)\r
-#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */\r
-#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */\r
-#define SWPMI_IER_RXBFIE_Pos     (0U)\r
-#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */\r
-#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */\r
-\r
-/*******************  Bit definition for SWPMI_RFL register  ********************/\r
-#define SWPMI_RFL_RFL_Pos        (0U)\r
-#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */\r
-#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */\r
-#define SWPMI_RFL_RFL_0_1_Pos    (0U)\r
-#define SWPMI_RFL_RFL_0_1_Msk    (0x3UL << SWPMI_RFL_RFL_0_1_Pos)              /*!< 0x00000003 */\r
-#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */\r
-\r
-/*******************  Bit definition for SWPMI_TDR register  ********************/\r
-#define SWPMI_TDR_TD_Pos         (0U)\r
-#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */\r
-#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */\r
-\r
-/*******************  Bit definition for SWPMI_RDR register  ********************/\r
-#define SWPMI_RDR_RD_Pos         (0U)\r
-#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */\r
-#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */\r
-\r
-/*******************  Bit definition for SWPMI_OR register  ********************/\r
-#define SWPMI_OR_TBYP_Pos        (0U)\r
-#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */\r
-#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */\r
-#define SWPMI_OR_CLASS_Pos       (1U)\r
-#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */\r
-#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                 VREFBUF                                    */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for VREFBUF_CSR register  ****************/\r
-#define VREFBUF_CSR_ENVR_Pos    (0U)\r
-#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */\r
-#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */\r
-#define VREFBUF_CSR_HIZ_Pos     (1U)\r
-#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */\r
-#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */\r
-#define VREFBUF_CSR_VRS_Pos     (2U)\r
-#define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */\r
-#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */\r
-#define VREFBUF_CSR_VRR_Pos     (3U)\r
-#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */\r
-#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */\r
-\r
-/*******************  Bit definition for VREFBUF_CCR register  ******************/\r
-#define VREFBUF_CCR_TRIM_Pos    (0U)\r
-#define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */\r
-#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                            Window WATCHDOG                                 */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/*******************  Bit definition for WWDG_CR register  ********************/\r
-#define WWDG_CR_T_Pos           (0U)\r
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */\r
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */\r
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */\r
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */\r
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */\r
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */\r
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */\r
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */\r
-\r
-#define WWDG_CR_WDGA_Pos        (7U)\r
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */\r
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\r
-\r
-/*******************  Bit definition for WWDG_CFR register  *******************/\r
-#define WWDG_CFR_W_Pos          (0U)\r
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */\r
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\r
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */\r
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */\r
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */\r
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */\r
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */\r
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */\r
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */\r
-\r
-#define WWDG_CFR_WDGTB_Pos      (7U)\r
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000180 */\r
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\r
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000080 */\r
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000100 */\r
-\r
-#define WWDG_CFR_EWI_Pos        (9U)\r
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */\r
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\r
-\r
-/*******************  Bit definition for WWDG_SR register  ********************/\r
-#define WWDG_SR_EWIF_Pos        (0U)\r
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */\r
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\r
-\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                 Debug MCU                                  */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/********************  Bit definition for DBGMCU_IDCODE register  *************/\r
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)\r
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk\r
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)\r
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk\r
-\r
-/********************  Bit definition for DBGMCU_CR register  *****************/\r
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)\r
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\r
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk\r
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)\r
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\r
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk\r
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)\r
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\r
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk\r
-#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)\r
-#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\r
-#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk\r
-\r
-#define DBGMCU_CR_TRACE_MODE_Pos               (6U)\r
-#define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\r
-#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk\r
-#define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\r
-#define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\r
-\r
-/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/\r
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)\r
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\r
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)\r
-#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\r
-#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)\r
-#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\r
-#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)\r
-#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\r
-#define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)\r
-#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\r
-#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)\r
-#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\r
-#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)\r
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\r
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)\r
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\r
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)\r
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\r
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)\r
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */\r
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)\r
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */\r
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)\r
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */\r
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)\r
-#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */\r
-#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk\r
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)\r
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */\r
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk\r
-\r
-/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/\r
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)\r
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */\r
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk\r
-\r
-/********************  Bit definition for DBGMCU_APB2FZ register  ************/\r
-#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)\r
-#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */\r
-#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk\r
-#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)\r
-#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */\r
-#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk\r
-#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)\r
-#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */\r
-#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk\r
-#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)\r
-#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */\r
-#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk\r
-#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)\r
-#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */\r
-#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk\r
-\r
-/******************************************************************************/\r
-/*                                                                            */\r
-/*                                       USB_OTG                              */\r
-/*                                                                            */\r
-/******************************************************************************/\r
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/\r
-#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\r
-#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\r
-#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\r
-#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\r
-#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\r
-#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\r
-#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\r
-#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r
-#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\r
-#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\r
-#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\r
-#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\r
-#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\r
-#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\r
-#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\r
-#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\r
-#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\r
-#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/\r
-\r
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\r
-#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\r
-#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */\r
-#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\r
-#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */\r
-#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\r
-#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\r
-#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\r
-#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */\r
-#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\r
-#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */\r
-#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\r
-#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */\r
-\r
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\r
-#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\r
-#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\r
-#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\r
-#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r
-#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\r
-#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\r
-#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\r
-#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\r
-#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\r
-#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\r
-#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\r
-\r
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\r
-#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\r
-#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r
-#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\r
-#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\r
-#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
-#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\r
-#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\r
-#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\r
-#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\r
-#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\r
-#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r
-#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\r
-#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\r
-#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\r
-#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\r
-#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */\r
-#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\r
-#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */\r
-#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\r
-#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */\r
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\r
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */\r
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\r
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */\r
-#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\r
-#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\r
-#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\r
-#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r
-#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */\r
-#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\r
-#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */\r
-#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\r
-#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */\r
-#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\r
-#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */\r
-#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\r
-#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */\r
-#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\r
-#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */\r
-\r
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\r
-#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\r
-#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */\r
-#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\r
-#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */\r
-#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\r
-#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\r
-#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\r
-#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */\r
-#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\r
-#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */\r
-#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\r
-#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r
-#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\r
-#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\r
-#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\r
-#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\r
-#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\r
-\r
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\r
-#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\r
-#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */\r
-#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\r
-#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */\r
-#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\r
-#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */\r
-#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\r
-#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */\r
-#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\r
-#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */\r
-#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\r
-#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */\r
-#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\r
-#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */\r
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\r
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */\r
-#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\r
-#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */\r
-#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\r
-#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */\r
-#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\r
-#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */\r
-#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\r
-#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */\r
-#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\r
-#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */\r
-#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\r
-#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */\r
-#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\r
-#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */\r
-#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\r
-#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */\r
-#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\r
-#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */\r
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\r
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */\r
-#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\r
-#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */\r
-#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\r
-#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */\r
-#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\r
-#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */\r
-#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\r
-#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r
-#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */\r
-#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\r
-#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */\r
-#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\r
-#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */\r
-#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\r
-#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */\r
-#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\r
-#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\r
-#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\r
-#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */\r
-\r
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\r
-#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\r
-#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */\r
-#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\r
-#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */\r
-#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\r
-#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */\r
-#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\r
-#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */\r
-#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\r
-#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */\r
-#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\r
-#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */\r
-#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\r
-#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */\r
-#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\r
-#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */\r
-#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\r
-#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */\r
-#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\r
-#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */\r
-#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\r
-#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */\r
-#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\r
-#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */\r
-#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\r
-#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */\r
-#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\r
-#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */\r
-#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\r
-#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */\r
-#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\r
-#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */\r
-#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\r
-#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */\r
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\r
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */\r
-#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\r
-#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */\r
-#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\r
-#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */\r
-#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\r
-#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */\r
-#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\r
-#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r
-#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */\r
-#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\r
-#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */\r
-#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\r
-#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */\r
-#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\r
-#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */\r
-#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\r
-#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\r
-#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\r
-#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */\r
-\r
-/********************  Bit definition for USB_OTG_GRXSTSR/GRXSTSP registers  ***********/\r
-/* Host mode */\r
-#define USB_OTG_CHNUM_Pos                        (0U)\r
-#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */\r
-#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\r
-#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000001 */\r
-#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000002 */\r
-#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000004 */\r
-#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)  /*!< 0x00000008 */\r
-/* Device mode */\r
-#define USB_OTG_EPNUM_Pos                        (0U)\r
-#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */\r
-#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\r
-#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000001 */\r
-#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000002 */\r
-#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000004 */\r
-#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)  /*!< 0x00000008 */\r
-#define USB_OTG_FRMNUM_Pos                       (21U)\r
-#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r
-#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\r
-#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */\r
-#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */\r
-/* Host/Device mode */\r
-#define USB_OTG_BCNT_Pos                         (4U)\r
-#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r
-#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\r
-#define USB_OTG_DPID_Pos                         (15U)\r
-#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */\r
-#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\r
-#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)   /*!< 0x00008000 */\r
-#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)   /*!< 0x00010000 */\r
-#define USB_OTG_PKTSTS_Pos                       (17U)\r
-#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r
-#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\r
-#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */\r
-\r
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\r
-#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\r
-#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r
-#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */\r
-#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\r
-#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r
-#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\r
-#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\r
-#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r
-#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\r
-#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\r
-#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r
-#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\r
-\r
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\r
-#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\r
-#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\r
-\r
-/********************  Bit definition for USB_OTG_HNPTXFSIZ/DIEPTXF0 register  *********/\r
-#define USB_OTG_NPTXFSA_Pos                      (0U)\r
-#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\r
-#define USB_OTG_NPTXFD_Pos                       (16U)\r
-#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r
-#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */\r
-#define USB_OTG_TX0FSA_Pos                       (0U)\r
-#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */\r
-#define USB_OTG_TX0FD_Pos                        (16U)\r
-#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r
-#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */\r
-\r
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\r
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\r
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r
-\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r
-\r
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/\r
-#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\r
-#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\r
-#define USB_OTG_GCCFG_PDET_Pos                   (1U)\r
-#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\r
-#define USB_OTG_GCCFG_SDET_Pos                   (2U)\r
-#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\r
-#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\r
-#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\r
-#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\r
-#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r
-#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\r
-#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\r
-#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\r
-#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\r
-#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\r
-#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\r
-#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\r
-#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\r
-#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\r
-#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\r
-#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */\r
-\r
-/********************  Bit definition for USB_OTG_CID register  ********************/\r
-#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\r
-#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r
-#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\r
-\r
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\r
-#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\r
-#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */\r
-#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\r
-#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r
-#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */\r
-#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\r
-#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */\r
-#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\r
-#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r
-#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */\r
-#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\r
-#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r
-#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */\r
-#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\r
-#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r
-#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */\r
-#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\r
-#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */\r
-#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\r
-#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r
-#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */\r
-#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\r
-#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */\r
-#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\r
-#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r
-#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */\r
-#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\r
-#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */\r
-#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\r
-#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */\r
-#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\r
-#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r
-#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */\r
-#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\r
-#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/\r
-#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\r
-#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */\r
-\r
-/* Legacy defines */\r
-#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           USB_OTG_GLPMCFG_L1RSMOK_Pos\r
-#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           USB_OTG_GLPMCFG_L1RSMOK_Msk\r
-#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1RSMOK\r
-\r
-/********************  Bit definition for USB_OTG_GPWRDN register  **********************/\r
-#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)\r
-#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1UL << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */\r
-\r
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\r
-#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\r
-#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */\r
-#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\r
-#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r
-#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */\r
-\r
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\r
-#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\r
-#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\r
-#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\r
-#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r
-#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\r
-\r
-/********************  Bit definition for USB_OTG_HCFG register  ********************/\r
-#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\r
-#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r
-#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */\r
-#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\r
-#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\r
-\r
-/********************  Bit definition for USB_OTG_HFIR register  ********************/\r
-#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\r
-#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\r
-\r
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/\r
-#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\r
-#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */\r
-#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\r
-#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r
-#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\r
-\r
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\r
-#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\r
-#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\r
-#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r
-\r
-#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\r
-#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r
-\r
-/********************  Bit definition for USB_OTG_HAINT register  ********************/\r
-#define USB_OTG_HAINT_HAINT_Pos                  (0U)\r
-#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\r
-\r
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\r
-#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\r
-#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\r
-\r
-/********************  Bit definition for USB_OTG_HPRT register  ********************/\r
-#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\r
-#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */\r
-#define USB_OTG_HPRT_PCDET_Pos                   (1U)\r
-#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */\r
-#define USB_OTG_HPRT_PENA_Pos                    (2U)\r
-#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */\r
-#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\r
-#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\r
-#define USB_OTG_HPRT_POCA_Pos                    (4U)\r
-#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */\r
-#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\r
-#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */\r
-#define USB_OTG_HPRT_PRES_Pos                    (6U)\r
-#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */\r
-#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\r
-#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */\r
-#define USB_OTG_HPRT_PRST_Pos                    (8U)\r
-#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */\r
-\r
-#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\r
-#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r
-#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */\r
-#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_HPRT_PPWR_Pos                    (12U)\r
-#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */\r
-\r
-#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\r
-#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r
-#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */\r
-#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r
-\r
-#define USB_OTG_HPRT_PSPD_Pos                    (17U)\r
-#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r
-#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */\r
-#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r
-\r
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\r
-#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\r
-#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r
-#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\r
-\r
-#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\r
-#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r
-#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\r
-#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\r
-#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\r
-#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\r
-#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\r
-\r
-#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\r
-#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r
-#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\r
-#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r
-\r
-#define USB_OTG_HCCHAR_MC_Pos                    (20U)\r
-#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r
-#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\r
-#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r
-\r
-#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\r
-#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r
-#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\r
-#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r
-#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r
-#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\r
-#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\r
-#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\r
-#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\r
-#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\r
-#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\r
-\r
-/********************  Bit definition for USB_OTG_HCINT register  ********************/\r
-#define USB_OTG_HCINT_XFRC_Pos                   (0U)\r
-#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\r
-#define USB_OTG_HCINT_CHH_Pos                    (1U)\r
-#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\r
-#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\r
-#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\r
-#define USB_OTG_HCINT_STALL_Pos                  (3U)\r
-#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\r
-#define USB_OTG_HCINT_NAK_Pos                    (4U)\r
-#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\r
-#define USB_OTG_HCINT_ACK_Pos                    (5U)\r
-#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\r
-#define USB_OTG_HCINT_NYET_Pos                   (6U)\r
-#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\r
-#define USB_OTG_HCINT_TXERR_Pos                  (7U)\r
-#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\r
-#define USB_OTG_HCINT_BBERR_Pos                  (8U)\r
-#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\r
-#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\r
-#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\r
-#define USB_OTG_HCINT_DTERR_Pos                  (10U)\r
-#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\r
-\r
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/\r
-#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\r
-#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\r
-#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\r
-#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\r
-#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\r
-#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\r
-#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\r
-#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\r
-#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\r
-#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\r
-#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\r
-#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\r
-#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\r
-#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\r
-#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\r
-#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\r
-#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\r
-#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\r
-#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\r
-#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\r
-#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\r
-#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\r
-\r
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\r
-#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\r
-#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
-#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\r
-#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\r
-#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
-#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\r
-#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\r
-#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\r
-#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\r
-#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r
-#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\r
-#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r
-\r
-/********************  Bit definition for USB_OTG_HCDMA register  *********************/\r
-#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\r
-#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
-#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\r
-\r
-/********************  Bit definition for USB_OTG_DCFG register  ********************/\r
-#define USB_OTG_DCFG_DSPD_Pos                    (0U)\r
-#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r
-#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\r
-#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\r
-#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\r
-#define USB_OTG_DCFG_DAD_Pos                     (4U)\r
-#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\r
-#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\r
-#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\r
-#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\r
-#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\r
-#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r
-\r
-/********************  Bit definition for USB_OTG_DCTL register  ********************/\r
-#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\r
-#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\r
-#define USB_OTG_DCTL_SDIS_Pos                    (1U)\r
-#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */\r
-#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\r
-#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */\r
-#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\r
-#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */\r
-#define USB_OTG_DCTL_TCTL_Pos                    (4U)\r
-#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r
-#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\r
-#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\r
-#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */\r
-#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\r
-#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */\r
-#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\r
-#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */\r
-#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\r
-#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */\r
-#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\r
-#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\r
-\r
-/********************  Bit definition for USB_OTG_DSTS register  ********************/\r
-#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\r
-#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */\r
-#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\r
-#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r
-#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\r
-#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_DSTS_EERR_Pos                    (3U)\r
-#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */\r
-#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\r
-#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r
-#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\r
-\r
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\r
-#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\r
-#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\r
-#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\r
-#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */\r
-#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\r
-#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\r
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\r
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
-#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\r
-#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */\r
-#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\r
-#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */\r
-#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\r
-#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */\r
-#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\r
-#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */\r
-\r
-/* Legacy defines */\r
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           USB_OTG_DIEPMSK_XFRCM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           USB_OTG_DIEPMSK_XFRCM_Msk\r
-#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPMSK_XFRCM\r
-#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            USB_OTG_DIEPMSK_EPDM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            USB_OTG_DIEPMSK_EPDM_Msk\r
-#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPMSK_EPDM\r
-#define USB_OTG_DIEPEACHMSK1_TOM_Pos             USB_OTG_DIEPMSK_TOM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_TOM_Msk             USB_OTG_DIEPMSK_TOM_Msk\r
-#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPMSK_TOM\r
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       USB_OTG_DIEPMSK_ITTXFEMSK_Pos\r
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       USB_OTG_DIEPMSK_ITTXFEMSK_Msk\r
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPMSK_ITTXFEMSK\r
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         USB_OTG_DIEPMSK_INEPNMM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         USB_OTG_DIEPMSK_INEPNMM_Msk\r
-#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPMSK_INEPNMM\r
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         USB_OTG_DIEPMSK_INEPNEM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         USB_OTG_DIEPMSK_INEPNEM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPMSK_INEPNEM\r
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          USB_OTG_DIEPMSK_TXFURM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          USB_OTG_DIEPMSK_TXFURM_Msk\r
-#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPMSK_TXFURM\r
-#define USB_OTG_DIEPEACHMSK1_BIM_Pos             USB_OTG_DIEPMSK_BIM_Pos\r
-#define USB_OTG_DIEPEACHMSK1_BIM_Msk             USB_OTG_DIEPMSK_BIM_Msk\r
-#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPMSK_BIM\r
-#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\r
-#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
-\r
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\r
-#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\r
-#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\r
-#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\r
-#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */\r
-#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\r
-#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */\r
-#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\r
-#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\r
-#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\r
-#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */\r
-#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\r
-#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */\r
-#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\r
-#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */\r
-\r
-/* Legacy defines */\r
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           USB_OTG_DOEPMSK_XFRCM_Pos\r
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           USB_OTG_DOEPMSK_XFRCM_Msk\r
-#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPMSK_XFRCM\r
-#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            USB_OTG_DOEPMSK_EPDM_Pos\r
-#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            USB_OTG_DOEPMSK_EPDM_Msk\r
-#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPMSK_EPDM\r
-#define USB_OTG_DOEPEACHMSK1_TOM_Pos             USB_OTG_DOEPMSK_STUPM_Pos\r
-#define USB_OTG_DOEPEACHMSK1_TOM_Msk             USB_OTG_DOEPMSK_STUPM_Msk\r
-#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPMSK_STUPM\r
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       USB_OTG_DOEPMSK_OTEPDM_Pos\r
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       USB_OTG_DOEPMSK_OTEPDM_Msk\r
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPMSK_OTEPDM\r
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\r
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         USB_OTG_DOEPMSK_B2BSTUP_Pos\r
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         USB_OTG_DOEPMSK_B2BSTUP_Msk\r
-#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPMSK_B2BSTUP\r
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          USB_OTG_DOEPMSK_OPEM_Pos\r
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          USB_OTG_DOEPMSK_OPEM_Msk\r
-#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPMSK_OPEM\r
-#define USB_OTG_DOEPEACHMSK1_BIM_Pos             USB_OTG_DOEPMSK_BOIM_Pos\r
-#define USB_OTG_DOEPEACHMSK1_BIM_Msk             USB_OTG_DOEPMSK_BOIM_Msk\r
-#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPMSK_BOIM\r
-#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\r
-#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\r
-#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\r
-#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
-#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\r
-#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\r
-\r
-/********************  Bit definition for USB_OTG_DAINT register  ********************/\r
-#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\r
-#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */\r
-#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\r
-#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r
-#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\r
-\r
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\r
-#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\r
-#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\r
-#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\r
-#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r
-#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\r
-\r
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\r
-#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\r
-#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\r
-\r
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/\r
-#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\r
-#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r
-#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r
-\r
-/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/\r
-#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\r
-#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r
-#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\r
-#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\r
-#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r
-#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\r
-#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\r
-\r
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/\r
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\r
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r
-\r
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\r
-#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\r
-#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */\r
-#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\r
-#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\r
-\r
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/\r
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\r
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */\r
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\r
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r
-\r
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\r
-#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\r
-#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
-#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */\r
-#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\r
-#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r
-#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\r
-#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r
-#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\r
-#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\r
-#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */\r
-#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\r
-#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
-#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */\r
-#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\r
-#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */\r
-#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\r
-#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r
-#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */\r
-#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r
-#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r
-#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r
-#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r
-#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\r
-#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
-#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */\r
-#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\r
-#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\r
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
-#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\r
-#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r
-#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\r
-#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r
-#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\r
-#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */\r
-\r
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\r
-#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\r
-#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r
-#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\r
-#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r
-#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\r
-#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\r
-#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\r
-#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\r
-#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\r
-#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\r
-#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\r
-#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\r
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\r
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r
-#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\r
-#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\r
-#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\r
-#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r
-#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\r
-#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\r
-#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\r
-#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\r
-\r
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\r
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\r
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r
-#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\r
-#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
-#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r
-#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\r
-#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r
-#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\r
-\r
-/********************  Bit definition for USB_OTG_DIEPDMA register  *********************/\r
-#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\r
-#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
-#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\r
-\r
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\r
-#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\r
-#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r
-#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */\r
-\r
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\r
-#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\r
-#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
-#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\r
-#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\r
-#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r
-#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\r
-#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
-#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\r
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
-#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\r
-#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r
-#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\r
-#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
-#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\r
-#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
-#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
-#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\r
-#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r
-#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\r
-#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\r
-#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r
-#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\r
-#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\r
-#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
-#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\r
-#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\r
-#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
-#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\r
-#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\r
-#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
-#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r
-#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\r
-#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\r
-\r
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\r
-#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\r
-#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r
-#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\r
-#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r
-#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\r
-#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\r
-#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\r
-#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\r
-#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\r
-#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\r
-#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\r
-#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\r
-\r
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\r
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\r
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r
-#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\r
-#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
-#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r
-#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\r
-#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r
-#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\r
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r
-\r
-/********************  Bit definition for USB_OTG_PCGCCTL register  ********************/\r
-#define USB_OTG_PCGCCTL_STPPCLK_Pos              (0U)\r
-#define USB_OTG_PCGCCTL_STPPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STPPCLK_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_PCGCCTL_STPPCLK                  USB_OTG_PCGCCTL_STPPCLK_Msk   /*!< Stop PHY clock */\r
-#define USB_OTG_PCGCCTL_GATEHCLK_Pos             (1U)\r
-#define USB_OTG_PCGCCTL_GATEHCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATEHCLK_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_PCGCCTL_GATEHCLK                 USB_OTG_PCGCCTL_GATEHCLK_Msk   /*!< Gate HCLK */\r
-#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\r
-#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\r
-\r
-/* Legacy defines */\r
-#define USB_OTG_PCGCCTL_STOPCLK_Pos              USB_OTG_PCGCCTL_STPPCLK_Pos\r
-#define USB_OTG_PCGCCTL_STOPCLK_Msk              USB_OTG_PCGCCTL_STPPCLK_Msk\r
-#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STPPCLK\r
-#define USB_OTG_PCGCCTL_GATECLK_Pos              USB_OTG_PCGCCTL_GATEHCLK_Pos\r
-#define USB_OTG_PCGCCTL_GATECLK_Msk              USB_OTG_PCGCCTL_GATEHCLK_Msk\r
-#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATEHCLK\r
-#define USB_OTG_PCGCR_STPPCLK_Pos                USB_OTG_PCGCCTL_STPPCLK_Pos\r
-#define USB_OTG_PCGCR_STPPCLK_Msk                USB_OTG_PCGCCTL_STPPCLK_Msk\r
-#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCCTL_STPPCLK\r
-#define USB_OTG_PCGCR_GATEHCLK_Pos               USB_OTG_PCGCCTL_GATEHCLK_Pos\r
-#define USB_OTG_PCGCR_GATEHCLK_Msk               USB_OTG_PCGCCTL_GATEHCLK_Msk\r
-#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCCTL_GATEHCLK\r
-#define USB_OTG_PCGCR_PHYSUSP_Pos                USB_OTG_PCGCCTL_PHYSUSP_Pos\r
-#define USB_OTG_PCGCR_PHYSUSP_Msk                USB_OTG_PCGCCTL_PHYSUSP_Msk\r
-#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCCTL_PHYSUSP\r
-#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)\r
-#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1UL << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */\r
-#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\r
-#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r
-#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\r
-#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r
-#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r
-#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r
-#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r
-#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r
-#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r
-#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r
-#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\r
-#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r
-#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\r
-#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r
-#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r
-#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r
-#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r
-#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r
-#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r
-#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r
-#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\r
-#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r
-#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\r
-#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r
-#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r
-#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\r
-#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r
-#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\r
-#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\r
-#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r
-#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup Exported_macros\r
-  * @{\r
-  */\r
-\r
-/******************************* ADC Instances ********************************/\r
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\r
-                                       ((INSTANCE) == ADC2) || \\r
-                                       ((INSTANCE) == ADC3))\r
-\r
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r
-\r
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\r
-\r
-/******************************** CAN Instances ******************************/\r
-#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)\r
-\r
-/******************************** COMP Instances ******************************/\r
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\r
-                                        ((INSTANCE) == COMP2))\r
-\r
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)\r
-\r
-/******************** COMP Instances with window mode capability **************/\r
-#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)\r
-\r
-/******************************* CRC Instances ********************************/\r
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\r
-\r
-/******************************* DAC Instances ********************************/\r
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\r
-\r
-/****************************** DFSDM Instances *******************************/\r
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\r
-                                                ((INSTANCE) == DFSDM1_Filter1) || \\r
-                                                ((INSTANCE) == DFSDM1_Filter2) || \\r
-                                                ((INSTANCE) == DFSDM1_Filter3))\r
-\r
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\r
-                                                 ((INSTANCE) == DFSDM1_Channel1) || \\r
-                                                 ((INSTANCE) == DFSDM1_Channel2) || \\r
-                                                 ((INSTANCE) == DFSDM1_Channel3) || \\r
-                                                 ((INSTANCE) == DFSDM1_Channel4) || \\r
-                                                 ((INSTANCE) == DFSDM1_Channel5) || \\r
-                                                 ((INSTANCE) == DFSDM1_Channel6) || \\r
-                                                 ((INSTANCE) == DFSDM1_Channel7))\r
-\r
-/******************************** DMA Instances *******************************/\r
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \\r
-                                       ((INSTANCE) == DMA1_Channel2) || \\r
-                                       ((INSTANCE) == DMA1_Channel3) || \\r
-                                       ((INSTANCE) == DMA1_Channel4) || \\r
-                                       ((INSTANCE) == DMA1_Channel5) || \\r
-                                       ((INSTANCE) == DMA1_Channel6) || \\r
-                                       ((INSTANCE) == DMA1_Channel7) || \\r
-                                       ((INSTANCE) == DMA2_Channel1) || \\r
-                                       ((INSTANCE) == DMA2_Channel2) || \\r
-                                       ((INSTANCE) == DMA2_Channel3) || \\r
-                                       ((INSTANCE) == DMA2_Channel4) || \\r
-                                       ((INSTANCE) == DMA2_Channel5) || \\r
-                                       ((INSTANCE) == DMA2_Channel6) || \\r
-                                       ((INSTANCE) == DMA2_Channel7))\r
-\r
-/******************************* GPIO Instances *******************************/\r
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\r
-                                        ((INSTANCE) == GPIOB) || \\r
-                                        ((INSTANCE) == GPIOC) || \\r
-                                        ((INSTANCE) == GPIOD) || \\r
-                                        ((INSTANCE) == GPIOE) || \\r
-                                        ((INSTANCE) == GPIOF) || \\r
-                                        ((INSTANCE) == GPIOG) || \\r
-                                        ((INSTANCE) == GPIOH))\r
-\r
-/******************************* GPIO AF Instances ****************************/\r
-/* On L4, all GPIO Bank support AF */\r
-#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)\r
-\r
-/**************************** GPIO Lock Instances *****************************/\r
-/* On L4, all GPIO Bank support the Lock mechanism */\r
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
-\r
-/******************************** I2C Instances *******************************/\r
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
-                                       ((INSTANCE) == I2C2) || \\r
-                                       ((INSTANCE) == I2C3))\r
-\r
-/****************** I2C Instances : wakeup capability from stop modes *********/\r
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\r
-\r
-/******************************* HCD Instances *******************************/\r
-#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)\r
-\r
-/****************************** OPAMP Instances *******************************/\r
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\r
-                                         ((INSTANCE) == OPAMP2))\r
-\r
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\r
-\r
-/******************************* PCD Instances *******************************/\r
-#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)\r
-\r
-/******************************* QSPI Instances *******************************/\r
-#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)\r
-\r
-/******************************* RNG Instances ********************************/\r
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\r
-\r
-/****************************** RTC Instances *********************************/\r
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\r
-\r
-/******************************** SAI Instances *******************************/\r
-#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \\r
-                                       ((INSTANCE) == SAI1_Block_B) || \\r
-                                       ((INSTANCE) == SAI2_Block_A) || \\r
-                                       ((INSTANCE) == SAI2_Block_B))\r
-\r
-/****************************** SDMMC Instances *******************************/\r
-#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)\r
-\r
-/****************************** SMBUS Instances *******************************/\r
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
-                                         ((INSTANCE) == I2C2) || \\r
-                                         ((INSTANCE) == I2C3))\r
-\r
-/******************************** SPI Instances *******************************/\r
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\r
-                                       ((INSTANCE) == SPI2) || \\r
-                                       ((INSTANCE) == SPI3))\r
-\r
-/******************************** SWPMI Instances *****************************/\r
-#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)\r
-\r
-/****************** LPTIM Instances : All supported instances *****************/\r
-#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\r
-                                         ((INSTANCE) == LPTIM2))\r
-\r
-/****************** LPTIM Instances : supporting the encoder mode *************/\r
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)\r
-\r
-/****************** TIM Instances : All supported instances *******************/\r
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\r
-                                         ((INSTANCE) == TIM2)   || \\r
-                                         ((INSTANCE) == TIM3)   || \\r
-                                         ((INSTANCE) == TIM4)   || \\r
-                                         ((INSTANCE) == TIM5)   || \\r
-                                         ((INSTANCE) == TIM6)   || \\r
-                                         ((INSTANCE) == TIM7)   || \\r
-                                         ((INSTANCE) == TIM8)   || \\r
-                                         ((INSTANCE) == TIM15)  || \\r
-                                         ((INSTANCE) == TIM16)  || \\r
-                                         ((INSTANCE) == TIM17))\r
-\r
-/****************** TIM Instances : supporting 32 bits counter ****************/\r
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \\r
-                                               ((INSTANCE) == TIM5))\r
-\r
-/****************** TIM Instances : supporting the break function *************/\r
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\r
-                                            ((INSTANCE) == TIM8)    || \\r
-                                            ((INSTANCE) == TIM15)   || \\r
-                                            ((INSTANCE) == TIM16)   || \\r
-                                            ((INSTANCE) == TIM17))\r
-\r
-/************** TIM Instances : supporting Break source selection *************/\r
-#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
-                                               ((INSTANCE) == TIM8)   || \\r
-                                               ((INSTANCE) == TIM15)  || \\r
-                                               ((INSTANCE) == TIM16)  || \\r
-                                               ((INSTANCE) == TIM17))\r
-\r
-/****************** TIM Instances : supporting 2 break inputs *****************/\r
-#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\r
-                                            ((INSTANCE) == TIM8))\r
-\r
-/************* TIM Instances : at least 1 capture/compare channel *************/\r
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
-                                         ((INSTANCE) == TIM2)   || \\r
-                                         ((INSTANCE) == TIM3)   || \\r
-                                         ((INSTANCE) == TIM4)   || \\r
-                                         ((INSTANCE) == TIM5)   || \\r
-                                         ((INSTANCE) == TIM8)   || \\r
-                                         ((INSTANCE) == TIM15)  || \\r
-                                         ((INSTANCE) == TIM16)  || \\r
-                                         ((INSTANCE) == TIM17))\r
-\r
-/************ TIM Instances : at least 2 capture/compare channels *************/\r
-#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
-                                         ((INSTANCE) == TIM2)   || \\r
-                                         ((INSTANCE) == TIM3)   || \\r
-                                         ((INSTANCE) == TIM4)   || \\r
-                                         ((INSTANCE) == TIM5)   || \\r
-                                         ((INSTANCE) == TIM8)   || \\r
-                                         ((INSTANCE) == TIM15))\r
-\r
-/************ TIM Instances : at least 3 capture/compare channels *************/\r
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
-                                         ((INSTANCE) == TIM2)   || \\r
-                                         ((INSTANCE) == TIM3)   || \\r
-                                         ((INSTANCE) == TIM4)   || \\r
-                                         ((INSTANCE) == TIM5)   || \\r
-                                         ((INSTANCE) == TIM8))\r
-\r
-/************ TIM Instances : at least 4 capture/compare channels *************/\r
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
-                                         ((INSTANCE) == TIM2)   || \\r
-                                         ((INSTANCE) == TIM3)   || \\r
-                                         ((INSTANCE) == TIM4)   || \\r
-                                         ((INSTANCE) == TIM5)   || \\r
-                                         ((INSTANCE) == TIM8))\r
-\r
-/****************** TIM Instances : at least 5 capture/compare channels *******/\r
-#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
-                                         ((INSTANCE) == TIM8))\r
-\r
-/****************** TIM Instances : at least 6 capture/compare channels *******/\r
-#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
-                                         ((INSTANCE) == TIM8))\r
-\r
-/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/\r
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \\r
-                                            ((INSTANCE) == TIM8)   || \\r
-                                            ((INSTANCE) == TIM15)  || \\r
-                                            ((INSTANCE) == TIM16)  || \\r
-                                            ((INSTANCE) == TIM17))\r
-\r
-/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/\r
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\r
-                                            ((INSTANCE) == TIM2)   || \\r
-                                            ((INSTANCE) == TIM3)   || \\r
-                                            ((INSTANCE) == TIM4)   || \\r
-                                            ((INSTANCE) == TIM5)   || \\r
-                                            ((INSTANCE) == TIM6)   || \\r
-                                            ((INSTANCE) == TIM7)   || \\r
-                                            ((INSTANCE) == TIM8)   || \\r
-                                            ((INSTANCE) == TIM15)  || \\r
-                                            ((INSTANCE) == TIM16)  || \\r
-                                            ((INSTANCE) == TIM17))\r
-\r
-/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/\r
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\r
-                                            ((INSTANCE) == TIM2)   || \\r
-                                            ((INSTANCE) == TIM3)   || \\r
-                                            ((INSTANCE) == TIM4)   || \\r
-                                            ((INSTANCE) == TIM5)   || \\r
-                                            ((INSTANCE) == TIM8)   || \\r
-                                            ((INSTANCE) == TIM15)  || \\r
-                                            ((INSTANCE) == TIM16)  || \\r
-                                            ((INSTANCE) == TIM17))\r
-\r
-/******************** TIM Instances : DMA burst feature ***********************/\r
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
-                                            ((INSTANCE) == TIM2)   || \\r
-                                            ((INSTANCE) == TIM3)   || \\r
-                                            ((INSTANCE) == TIM4)   || \\r
-                                            ((INSTANCE) == TIM5)   || \\r
-                                            ((INSTANCE) == TIM8)   || \\r
-                                            ((INSTANCE) == TIM15)  || \\r
-                                            ((INSTANCE) == TIM16)  || \\r
-                                            ((INSTANCE) == TIM17))\r
-\r
-/******************* TIM Instances : output(s) available **********************/\r
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\r
-    ((((INSTANCE) == TIM1) &&                  \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_4) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_5) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_6)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM2) &&                  \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM3) &&                  \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM4) &&                  \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM5) &&                  \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_4)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM8) &&                  \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_4) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_5) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_6)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM15) &&                 \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \\r
-      ((CHANNEL) == TIM_CHANNEL_2)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM16) &&                 \\r
-     (((CHANNEL) == TIM_CHANNEL_1)))           \\r
-     ||                                        \\r
-     (((INSTANCE) == TIM17) &&                 \\r
-      (((CHANNEL) == TIM_CHANNEL_1))))\r
-\r
-/****************** TIM Instances : supporting complementary output(s) ********/\r
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\r
-   ((((INSTANCE) == TIM1) &&                    \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \\r
-      ((CHANNEL) == TIM_CHANNEL_3)))            \\r
-    ||                                          \\r
-    (((INSTANCE) == TIM8) &&                    \\r
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \\r
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \\r
-      ((CHANNEL) == TIM_CHANNEL_3)))            \\r
-    ||                                          \\r
-    (((INSTANCE) == TIM15) &&                   \\r
-     ((CHANNEL) == TIM_CHANNEL_1))              \\r
-    ||                                          \\r
-    (((INSTANCE) == TIM16) &&                   \\r
-     ((CHANNEL) == TIM_CHANNEL_1))              \\r
-    ||                                          \\r
-    (((INSTANCE) == TIM17) &&                   \\r
-     ((CHANNEL) == TIM_CHANNEL_1)))\r
-\r
-/****************** TIM Instances : supporting clock division *****************/\r
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \\r
-                                                    ((INSTANCE) == TIM2)    || \\r
-                                                    ((INSTANCE) == TIM3)    || \\r
-                                                    ((INSTANCE) == TIM4)    || \\r
-                                                    ((INSTANCE) == TIM5)    || \\r
-                                                    ((INSTANCE) == TIM8)    || \\r
-                                                    ((INSTANCE) == TIM15)   || \\r
-                                                    ((INSTANCE) == TIM16)   || \\r
-                                                    ((INSTANCE) == TIM17))\r
-\r
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\r
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
-                                                        ((INSTANCE) == TIM2) || \\r
-                                                        ((INSTANCE) == TIM3) || \\r
-                                                        ((INSTANCE) == TIM4) || \\r
-                                                        ((INSTANCE) == TIM5) || \\r
-                                                        ((INSTANCE) == TIM8) || \\r
-                                                        ((INSTANCE) == TIM15))\r
-\r
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\r
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
-                                                        ((INSTANCE) == TIM2) || \\r
-                                                        ((INSTANCE) == TIM3) || \\r
-                                                        ((INSTANCE) == TIM4) || \\r
-                                                        ((INSTANCE) == TIM5) || \\r
-                                                        ((INSTANCE) == TIM8))\r
-\r
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\r
-                                                        ((INSTANCE) == TIM2) || \\r
-                                                        ((INSTANCE) == TIM3) || \\r
-                                                        ((INSTANCE) == TIM4) || \\r
-                                                        ((INSTANCE) == TIM5) || \\r
-                                                        ((INSTANCE) == TIM8) || \\r
-                                                        ((INSTANCE) == TIM15))\r
-\r
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\r
-                                                        ((INSTANCE) == TIM2) || \\r
-                                                        ((INSTANCE) == TIM3) || \\r
-                                                        ((INSTANCE) == TIM4) || \\r
-                                                        ((INSTANCE) == TIM5) || \\r
-                                                        ((INSTANCE) == TIM8) || \\r
-                                                        ((INSTANCE) == TIM15))\r
-\r
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
-                                                     ((INSTANCE) == TIM8))\r
-\r
-/****************** TIM Instances : supporting commutation event generation ***/\r
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
-                                                     ((INSTANCE) == TIM8)   || \\r
-                                                     ((INSTANCE) == TIM15)  || \\r
-                                                     ((INSTANCE) == TIM16)  || \\r
-                                                     ((INSTANCE) == TIM17))\r
-\r
-/****************** TIM Instances : supporting counting mode selection ********/\r
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\r
-                                                        ((INSTANCE) == TIM2) || \\r
-                                                        ((INSTANCE) == TIM3) || \\r
-                                                        ((INSTANCE) == TIM4) || \\r
-                                                        ((INSTANCE) == TIM5) || \\r
-                                                        ((INSTANCE) == TIM8))\r
-\r
-/****************** TIM Instances : supporting encoder interface **************/\r
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\r
-                                                      ((INSTANCE) == TIM2)  || \\r
-                                                      ((INSTANCE) == TIM3)  || \\r
-                                                      ((INSTANCE) == TIM4)  || \\r
-                                                      ((INSTANCE) == TIM5)  || \\r
-                                                      ((INSTANCE) == TIM8))\r
-\r
-/****************** TIM Instances : supporting Hall sensor interface **********/\r
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\r
-                                                         ((INSTANCE) == TIM2)   || \\r
-                                                         ((INSTANCE) == TIM3)   || \\r
-                                                         ((INSTANCE) == TIM4)   || \\r
-                                                         ((INSTANCE) == TIM5)   || \\r
-                                                         ((INSTANCE) == TIM8))\r
-\r
-/**************** TIM Instances : external trigger input available ************/\r
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \\r
-                                            ((INSTANCE) == TIM2)  || \\r
-                                            ((INSTANCE) == TIM3)  || \\r
-                                            ((INSTANCE) == TIM4)  || \\r
-                                            ((INSTANCE) == TIM5)  || \\r
-                                            ((INSTANCE) == TIM8))\r
-\r
-/************* TIM Instances : supporting ETR source selection ***************/\r
-#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\r
-                                             ((INSTANCE) == TIM2)  || \\r
-                                             ((INSTANCE) == TIM3)  || \\r
-                                             ((INSTANCE) == TIM8))\r
-\r
-/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/\r
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\r
-                                            ((INSTANCE) == TIM2)  || \\r
-                                            ((INSTANCE) == TIM3)  || \\r
-                                            ((INSTANCE) == TIM4)  || \\r
-                                            ((INSTANCE) == TIM5)  || \\r
-                                            ((INSTANCE) == TIM6)  || \\r
-                                            ((INSTANCE) == TIM7)  || \\r
-                                            ((INSTANCE) == TIM8)  || \\r
-                                            ((INSTANCE) == TIM15))\r
-\r
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\r
-                                            ((INSTANCE) == TIM2)  || \\r
-                                            ((INSTANCE) == TIM3)  || \\r
-                                            ((INSTANCE) == TIM4)  || \\r
-                                            ((INSTANCE) == TIM5)  || \\r
-                                            ((INSTANCE) == TIM8)  || \\r
-                                            ((INSTANCE) == TIM15))\r
-\r
-/****************** TIM Instances : supporting OCxREF clear *******************/\r
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\r
-                                                       ((INSTANCE) == TIM2) || \\r
-                                                       ((INSTANCE) == TIM3) || \\r
-                                                       ((INSTANCE) == TIM4) || \\r
-                                                       ((INSTANCE) == TIM5) || \\r
-                                                       ((INSTANCE) == TIM8))\r
-\r
-/****************** TIM Instances : remapping capability **********************/\r
-#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\r
-                                            ((INSTANCE) == TIM2)  || \\r
-                                            ((INSTANCE) == TIM3)  || \\r
-                                            ((INSTANCE) == TIM8)  || \\r
-                                            ((INSTANCE) == TIM15) || \\r
-                                            ((INSTANCE) == TIM16) || \\r
-                                            ((INSTANCE) == TIM17))\r
-\r
-/****************** TIM Instances : supporting repetition counter *************/\r
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\r
-                                                       ((INSTANCE) == TIM8)  || \\r
-                                                       ((INSTANCE) == TIM15) || \\r
-                                                       ((INSTANCE) == TIM16) || \\r
-                                                       ((INSTANCE) == TIM17))\r
-\r
-/****************** TIM Instances : supporting synchronization ****************/\r
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)\r
-\r
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r
-#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\r
-                                            ((INSTANCE) == TIM8))\r
-\r
-/******************* TIM Instances : Timer input XOR function *****************/\r
-#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\r
-                                            ((INSTANCE) == TIM2)   || \\r
-                                            ((INSTANCE) == TIM3)   || \\r
-                                            ((INSTANCE) == TIM4)   || \\r
-                                            ((INSTANCE) == TIM5)   || \\r
-                                            ((INSTANCE) == TIM8)   || \\r
-                                            ((INSTANCE) == TIM15))\r
-\r
-/****************** TIM Instances : Advanced timer instances *******************/\r
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\r
-                                                  ((INSTANCE) == TIM8))\r
-\r
-/****************************** TSC Instances *********************************/\r
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)\r
-\r
-/******************** USART Instances : Synchronous mode **********************/\r
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
-                                     ((INSTANCE) == USART2) || \\r
-                                     ((INSTANCE) == USART3))\r
-\r
-/******************** UART Instances : Asynchronous mode **********************/\r
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
-                                    ((INSTANCE) == USART2) || \\r
-                                    ((INSTANCE) == USART3) || \\r
-                                    ((INSTANCE) == UART4)  || \\r
-                                    ((INSTANCE) == UART5))\r
-\r
-/****************** UART Instances : Auto Baud Rate detection ****************/\r
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
-                                                            ((INSTANCE) == USART2) || \\r
-                                                            ((INSTANCE) == USART3) || \\r
-                                                            ((INSTANCE) == UART4)  || \\r
-                                                            ((INSTANCE) == UART5))\r
-\r
-/****************** UART Instances : Driver Enable *****************/\r
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \\r
-                                                      ((INSTANCE) == USART2) || \\r
-                                                      ((INSTANCE) == USART3) || \\r
-                                                      ((INSTANCE) == UART4)  || \\r
-                                                      ((INSTANCE) == UART5)  || \\r
-                                                      ((INSTANCE) == LPUART1))\r
-\r
-/******************** UART Instances : Half-Duplex mode **********************/\r
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\r
-                                                 ((INSTANCE) == USART2) || \\r
-                                                 ((INSTANCE) == USART3) || \\r
-                                                 ((INSTANCE) == UART4)  || \\r
-                                                 ((INSTANCE) == UART5)  || \\r
-                                                 ((INSTANCE) == LPUART1))\r
-\r
-/****************** UART Instances : Hardware Flow control ********************/\r
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
-                                           ((INSTANCE) == USART2) || \\r
-                                           ((INSTANCE) == USART3) || \\r
-                                           ((INSTANCE) == UART4)  || \\r
-                                           ((INSTANCE) == UART5)  || \\r
-                                           ((INSTANCE) == LPUART1))\r
-\r
-/******************** UART Instances : LIN mode **********************/\r
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\r
-                                          ((INSTANCE) == USART2) || \\r
-                                          ((INSTANCE) == USART3) || \\r
-                                          ((INSTANCE) == UART4)  || \\r
-                                          ((INSTANCE) == UART5))\r
-\r
-/******************** UART Instances : Wake-up from Stop mode **********************/\r
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\r
-                                                      ((INSTANCE) == USART2) || \\r
-                                                      ((INSTANCE) == USART3) || \\r
-                                                      ((INSTANCE) == UART4)  || \\r
-                                                      ((INSTANCE) == UART5)  || \\r
-                                                      ((INSTANCE) == LPUART1))\r
-\r
-/*********************** UART Instances : IRDA mode ***************************/\r
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
-                                    ((INSTANCE) == USART2) || \\r
-                                    ((INSTANCE) == USART3) || \\r
-                                    ((INSTANCE) == UART4)  || \\r
-                                    ((INSTANCE) == UART5))\r
-\r
-/********************* USART Instances : Smard card mode ***********************/\r
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
-                                         ((INSTANCE) == USART2) || \\r
-                                         ((INSTANCE) == USART3))\r
-\r
-/******************** LPUART Instance *****************************************/\r
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)\r
-\r
-/****************************** IWDG Instances ********************************/\r
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\r
-\r
-/****************************** WWDG Instances ********************************/\r
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/******************************************************************************/\r
-/*  For a painless codes migration between the STM32L4xx device product       */\r
-/*  lines, the aliases defined below are put in place to overcome the         */\r
-/*  differences in the interrupt handlers and IRQn definitions.               */\r
-/*  No need to update developed interrupt code when moving across             */\r
-/*  product lines within the same STM32L4 Family                              */\r
-/******************************************************************************/\r
-\r
-/* Aliases for __IRQn */\r
-#define TIM6_IRQn                      TIM6_DAC_IRQn\r
-#define ADC1_IRQn                      ADC1_2_IRQn\r
-#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn\r
-#define TIM8_IRQn                      TIM8_UP_IRQn\r
-#define HASH_RNG_IRQn                  RNG_IRQn\r
-#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn\r
-#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn\r
-#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn\r
-#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn\r
-\r
-/* Aliases for __IRQHandler */\r
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler\r
-#define ADC1_IRQHandler                ADC1_2_IRQHandler\r
-#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler\r
-#define TIM8_IRQHandler                TIM8_UP_IRQHandler\r
-#define HASH_RNG_IRQHandler            RNG_IRQHandler\r
-#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler\r
-#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler\r
-#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler\r
-#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif /* __cplusplus */\r
-\r
-#endif /* __STM32L475xx_H */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-  /**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h
deleted file mode 100644 (file)
index 0bf6c83..0000000
+++ /dev/null
@@ -1,248 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx.h\r
-  * @author  MCD Application Team\r
-  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.\r
-  *\r
-  *          The file is the unique include file that the application programmer\r
-  *          is using in the C source code, usually in main.c. This file contains:\r
-  *           - Configuration section that allows to select:\r
-  *              - The STM32L4xx device used in the target application\r
-  *              - To use or not the peripheral\92s drivers in application code(i.e.\r
-  *                code will be based on direct access to peripheral\92s registers\r
-  *                rather than drivers API), this option is controlled by\r
-  *                "#define USE_HAL_DRIVER"\r
-  *\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/** @addtogroup CMSIS\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup stm32l4xx\r
-  * @{\r
-  */\r
-\r
-#ifndef __STM32L4xx_H\r
-#define __STM32L4xx_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif /* __cplusplus */\r
-\r
-/** @addtogroup Library_configuration_section\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief STM32 Family\r
-  */\r
-#if !defined (STM32L4)\r
-#define STM32L4\r
-#endif /* STM32L4 */\r
-\r
-/* Uncomment the line below according to the target STM32L4 device used in your\r
-   application\r
-  */\r
-\r
-#if !defined (STM32L412xx) && !defined (STM32L422xx) && \\r
-    !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \\r
-    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \\r
-    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \\r
-    !defined (STM32L496xx) && !defined (STM32L4A6xx) && \\r
-    !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)\r
-  /* #define STM32L412xx */   /*!< STM32L412xx Devices */\r
-  /* #define STM32L422xx */   /*!< STM32L422xx Devices */\r
-  /* #define STM32L431xx */   /*!< STM32L431xx Devices */\r
-  /* #define STM32L432xx */   /*!< STM32L432xx Devices */\r
-  /* #define STM32L433xx */   /*!< STM32L433xx Devices */\r
-  /* #define STM32L442xx */   /*!< STM32L442xx Devices */\r
-  /* #define STM32L443xx */   /*!< STM32L443xx Devices */\r
-  /* #define STM32L451xx */   /*!< STM32L451xx Devices */\r
-  /* #define STM32L452xx */   /*!< STM32L452xx Devices */\r
-  /* #define STM32L462xx */   /*!< STM32L462xx Devices */\r
-  /* #define STM32L471xx */   /*!< STM32L471xx Devices */\r
-  /* #define STM32L475xx */   /*!< STM32L475xx Devices */\r
-  /* #define STM32L476xx */   /*!< STM32L476xx Devices */\r
-  /* #define STM32L485xx */   /*!< STM32L485xx Devices */\r
-  /* #define STM32L486xx */   /*!< STM32L486xx Devices */\r
-  /* #define STM32L496xx */   /*!< STM32L496xx Devices */\r
-  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */\r
-  /* #define STM32L4R5xx */   /*!< STM32L4R5xx Devices */\r
-  /* #define STM32L4R7xx */   /*!< STM32L4R7xx Devices */\r
-  /* #define STM32L4R9xx */   /*!< STM32L4R9xx Devices */\r
-  /* #define STM32L4S5xx */   /*!< STM32L4S5xx Devices */\r
-  /* #define STM32L4S7xx */   /*!< STM32L4S7xx Devices */\r
-  /* #define STM32L4S9xx */   /*!< STM32L4S9xx Devices */\r
-#endif\r
-\r
-/*  Tip: To avoid modifying this file each time you need to switch between these\r
-        devices, you can define the device in your toolchain compiler preprocessor.\r
-  */\r
-#if !defined  (USE_HAL_DRIVER)\r
-/**\r
- * @brief Comment the line below if you will not use the peripherals drivers.\r
-   In this case, these drivers will not be included and the application code will\r
-   be based on direct access to peripherals registers\r
-   */\r
-  /*#define USE_HAL_DRIVER */\r
-#endif /* USE_HAL_DRIVER */\r
-\r
-/**\r
-  * @brief CMSIS Device version number\r
-  */\r
-#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */\r
-#define __STM32L4_CMSIS_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */\r
-#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */\r
-#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */\r
-#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\\r
-                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\\r
-                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\\r
-                                       |(__STM32L4_CMSIS_VERSION_RC))\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup Device_Included\r
-  * @{\r
-  */\r
-\r
-#if defined(STM32L412xx)\r
-  #include "stm32l412xx.h"\r
-#elif defined(STM32L422xx)\r
-  #include "stm32l422xx.h"\r
-#elif defined(STM32L431xx)\r
-  #include "stm32l431xx.h"\r
-#elif defined(STM32L432xx)\r
-  #include "stm32l432xx.h"\r
-#elif defined(STM32L433xx)\r
-  #include "stm32l433xx.h"\r
-#elif defined(STM32L442xx)\r
-  #include "stm32l442xx.h"\r
-#elif defined(STM32L443xx)\r
-  #include "stm32l443xx.h"\r
-#elif defined(STM32L451xx)\r
-  #include "stm32l451xx.h"\r
-#elif defined(STM32L452xx)\r
-  #include "stm32l452xx.h"\r
-#elif defined(STM32L462xx)\r
-  #include "stm32l462xx.h"\r
-#elif defined(STM32L471xx)\r
-  #include "stm32l471xx.h"\r
-#elif defined(STM32L475xx)\r
-  #include "stm32l475xx.h"\r
-#elif defined(STM32L476xx)\r
-  #include "stm32l476xx.h"\r
-#elif defined(STM32L485xx)\r
-  #include "stm32l485xx.h"\r
-#elif defined(STM32L486xx)\r
-  #include "stm32l486xx.h"\r
-#elif defined(STM32L496xx)\r
-  #include "stm32l496xx.h"\r
-#elif defined(STM32L4A6xx)\r
-  #include "stm32l4a6xx.h"\r
-#elif defined(STM32L4R5xx)\r
-  #include "stm32l4r5xx.h"\r
-#elif defined(STM32L4R7xx)\r
-  #include "stm32l4r7xx.h"\r
-#elif defined(STM32L4R9xx)\r
-  #include "stm32l4r9xx.h"\r
-#elif defined(STM32L4S5xx)\r
-  #include "stm32l4s5xx.h"\r
-#elif defined(STM32L4S7xx)\r
-  #include "stm32l4s7xx.h"\r
-#elif defined(STM32L4S9xx)\r
-  #include "stm32l4s9xx.h"\r
-#else\r
- #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup Exported_types\r
-  * @{\r
-  */\r
-typedef enum\r
-{\r
-  RESET = 0,\r
-  SET = !RESET\r
-} FlagStatus, ITStatus;\r
-\r
-typedef enum\r
-{\r
-  DISABLE = 0,\r
-  ENABLE = !DISABLE\r
-} FunctionalState;\r
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
-\r
-typedef enum\r
-{\r
-  SUCCESS = 0,\r
-  ERROR = !SUCCESS\r
-} ErrorStatus;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @addtogroup Exported_macros\r
-  * @{\r
-  */\r
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\r
-\r
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\r
-\r
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))\r
-\r
-#define CLEAR_REG(REG)        ((REG) = (0x0))\r
-\r
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\r
-\r
-#define READ_REG(REG)         ((REG))\r
-\r
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
-\r
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined (USE_HAL_DRIVER)\r
- #include "stm32l4xx_hal.h"\r
-#endif /* USE_HAL_DRIVER */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif /* __cplusplus */\r
-\r
-#endif /* __STM32L4xx_H */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h
deleted file mode 100644 (file)
index 9eceb00..0000000
+++ /dev/null
@@ -1,107 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    system_stm32l4xx.h\r
-  * @author  MCD Application Team\r
-  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/** @addtogroup CMSIS\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup stm32l4xx_system\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Define to prevent recursive inclusion\r
-  */\r
-#ifndef __SYSTEM_STM32L4XX_H\r
-#define __SYSTEM_STM32L4XX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/** @addtogroup STM32L4xx_System_Includes\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @addtogroup STM32L4xx_System_Exported_Variables\r
-  * @{\r
-  */\r
-  /* The SystemCoreClock variable is updated in three ways:\r
-      1) by calling CMSIS function SystemCoreClockUpdate()\r
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
-         Note: If you use this function to configure the system clock; then there\r
-               is no need to call the 2 first functions listed above, since SystemCoreClock\r
-               variable is updated automatically.\r
-  */\r
-extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */\r
-\r
-extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\r
-extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\r
-extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Exported_Constants\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Exported_Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32L4xx_System_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-extern void SystemInit(void);\r
-extern void SystemCoreClockUpdate(void);\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__SYSTEM_STM32L4XX_H */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_armcc.h
deleted file mode 100644 (file)
index 7d751fb..0000000
+++ /dev/null
@@ -1,865 +0,0 @@
-/**************************************************************************//**\r
- * @file     cmsis_armcc.h\r
- * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file\r
- * @version  V5.0.4\r
- * @date     10. January 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#ifndef __CMSIS_ARMCC_H\r
-#define __CMSIS_ARMCC_H\r
-\r
-\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
-  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* CMSIS compiler control architecture macros */\r
-#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \\r
-     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )\r
-  #define __ARM_ARCH_6M__           1\r
-#endif\r
-\r
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))\r
-  #define __ARM_ARCH_7M__           1\r
-#endif\r
-\r
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\r
-  #define __ARM_ARCH_7EM__          1\r
-#endif\r
-\r
-  /* __ARM_ARCH_8M_BASE__  not applicable */\r
-  /* __ARM_ARCH_8M_MAIN__  not applicable */\r
-\r
-\r
-/* CMSIS compiler specific defines */\r
-#ifndef   __ASM\r
-  #define __ASM                                  __asm\r
-#endif\r
-#ifndef   __INLINE\r
-  #define __INLINE                               __inline\r
-#endif\r
-#ifndef   __STATIC_INLINE\r
-  #define __STATIC_INLINE                        static __inline\r
-#endif\r
-#ifndef   __STATIC_FORCEINLINE                 \r
-  #define __STATIC_FORCEINLINE                   static __forceinline\r
-#endif           \r
-#ifndef   __NO_RETURN\r
-  #define __NO_RETURN                            __declspec(noreturn)\r
-#endif\r
-#ifndef   __USED\r
-  #define __USED                                 __attribute__((used))\r
-#endif\r
-#ifndef   __WEAK\r
-  #define __WEAK                                 __attribute__((weak))\r
-#endif\r
-#ifndef   __PACKED\r
-  #define __PACKED                               __attribute__((packed))\r
-#endif\r
-#ifndef   __PACKED_STRUCT\r
-  #define __PACKED_STRUCT                        __packed struct\r
-#endif\r
-#ifndef   __PACKED_UNION\r
-  #define __PACKED_UNION                         __packed union\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32        /* deprecated */\r
-  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT16_WRITE\r
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT16_READ\r
-  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32_WRITE\r
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32_READ\r
-  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))\r
-#endif\r
-#ifndef   __ALIGNED\r
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
-#endif\r
-#ifndef   __RESTRICT\r
-  #define __RESTRICT                             __restrict\r
-#endif\r
-\r
-/* ###########################  Core Function Access  ########################### */\r
-/** \ingroup  CMSIS_Core_FunctionInterface\r
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Enable IRQ Interrupts\r
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-/* intrinsic void __enable_irq();     */\r
-\r
-\r
-/**\r
-  \brief   Disable IRQ Interrupts\r
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-/* intrinsic void __disable_irq();    */\r
-\r
-/**\r
-  \brief   Get Control Register\r
-  \details Returns the content of the Control Register.\r
-  \return               Control Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
-  register uint32_t __regControl         __ASM("control");\r
-  return(__regControl);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Control Register\r
-  \details Writes the given value to the Control Register.\r
-  \param [in]    control  Control Register value to set\r
- */\r
-__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
-  register uint32_t __regControl         __ASM("control");\r
-  __regControl = control;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get IPSR Register\r
-  \details Returns the content of the IPSR Register.\r
-  \return               IPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
-  register uint32_t __regIPSR          __ASM("ipsr");\r
-  return(__regIPSR);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get APSR Register\r
-  \details Returns the content of the APSR Register.\r
-  \return               APSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
-  register uint32_t __regAPSR          __ASM("apsr");\r
-  return(__regAPSR);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get xPSR Register\r
-  \details Returns the content of the xPSR Register.\r
-  \return               xPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
-  register uint32_t __regXPSR          __ASM("xpsr");\r
-  return(__regXPSR);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Process Stack Pointer\r
-  \details Returns the current value of the Process Stack Pointer (PSP).\r
-  \return               PSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
-  register uint32_t __regProcessStackPointer  __ASM("psp");\r
-  return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Process Stack Pointer\r
-  \details Assigns the given value to the Process Stack Pointer (PSP).\r
-  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
-  register uint32_t __regProcessStackPointer  __ASM("psp");\r
-  __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Main Stack Pointer\r
-  \details Returns the current value of the Main Stack Pointer (MSP).\r
-  \return               MSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
-  register uint32_t __regMainStackPointer     __ASM("msp");\r
-  return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Main Stack Pointer\r
-  \details Assigns the given value to the Main Stack Pointer (MSP).\r
-  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
-  register uint32_t __regMainStackPointer     __ASM("msp");\r
-  __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Mask\r
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
-  \return               Priority Mask value\r
- */\r
-__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
-  register uint32_t __regPriMask         __ASM("primask");\r
-  return(__regPriMask);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Priority Mask\r
-  \details Assigns the given value to the Priority Mask Register.\r
-  \param [in]    priMask  Priority Mask\r
- */\r
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
-  register uint32_t __regPriMask         __ASM("primask");\r
-  __regPriMask = (priMask);\r
-}\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
-\r
-/**\r
-  \brief   Enable FIQ\r
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq                __enable_fiq\r
-\r
-\r
-/**\r
-  \brief   Disable FIQ\r
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq               __disable_fiq\r
-\r
-\r
-/**\r
-  \brief   Get Base Priority\r
-  \details Returns the current value of the Base Priority register.\r
-  \return               Base Priority register value\r
- */\r
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)\r
-{\r
-  register uint32_t __regBasePri         __ASM("basepri");\r
-  return(__regBasePri);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Base Priority\r
-  \details Assigns the given value to the Base Priority register.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
-  register uint32_t __regBasePri         __ASM("basepri");\r
-  __regBasePri = (basePri & 0xFFU);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Base Priority with condition\r
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
-           or the new value increases the BASEPRI priority level.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
-{\r
-  register uint32_t __regBasePriMax      __ASM("basepri_max");\r
-  __regBasePriMax = (basePri & 0xFFU);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Fault Mask\r
-  \details Returns the current value of the Fault Mask register.\r
-  \return               Fault Mask register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
-  register uint32_t __regFaultMask       __ASM("faultmask");\r
-  return(__regFaultMask);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Fault Mask\r
-  \details Assigns the given value to the Fault Mask register.\r
-  \param [in]    faultMask  Fault Mask value to set\r
- */\r
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
-  register uint32_t __regFaultMask       __ASM("faultmask");\r
-  __regFaultMask = (faultMask & (uint32_t)1U);\r
-}\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
-\r
-\r
-/**\r
-  \brief   Get FPSCR\r
-  \details Returns the current value of the Floating Point Status/Control register.\r
-  \return               Floating Point Status/Control register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-  register uint32_t __regfpscr         __ASM("fpscr");\r
-  return(__regfpscr);\r
-#else\r
-   return(0U);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set FPSCR\r
-  \details Assigns the given value to the Floating Point Status/Control register.\r
-  \param [in]    fpscr  Floating Point Status/Control value to set\r
- */\r
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-  register uint32_t __regfpscr         __ASM("fpscr");\r
-  __regfpscr = (fpscr);\r
-#else\r
-  (void)fpscr;\r
-#endif\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ##########################  Core Instruction Access  ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
-  Access to dedicated instructions\r
-  @{\r
-*/\r
-\r
-/**\r
-  \brief   No Operation\r
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP                             __nop\r
-\r
-\r
-/**\r
-  \brief   Wait For Interrupt\r
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-#define __WFI                             __wfi\r
-\r
-\r
-/**\r
-  \brief   Wait For Event\r
-  \details Wait For Event is a hint instruction that permits the processor to enter\r
-           a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE                             __wfe\r
-\r
-\r
-/**\r
-  \brief   Send Event\r
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV                             __sev\r
-\r
-\r
-/**\r
-  \brief   Instruction Synchronization Barrier\r
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
-           so that all instructions following the ISB are fetched from cache or memory,\r
-           after the instruction has been completed.\r
- */\r
-#define __ISB() do {\\r
-                   __schedule_barrier();\\r
-                   __isb(0xF);\\r
-                   __schedule_barrier();\\r
-                } while (0U)\r
-\r
-/**\r
-  \brief   Data Synchronization Barrier\r
-  \details Acts as a special kind of Data Memory Barrier.\r
-           It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() do {\\r
-                   __schedule_barrier();\\r
-                   __dsb(0xF);\\r
-                   __schedule_barrier();\\r
-                } while (0U)\r
-\r
-/**\r
-  \brief   Data Memory Barrier\r
-  \details Ensures the apparent order of the explicit memory operations before\r
-           and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() do {\\r
-                   __schedule_barrier();\\r
-                   __dmb(0xF);\\r
-                   __schedule_barrier();\\r
-                } while (0U)\r
-\r
-                  \r
-/**\r
-  \brief   Reverse byte order (32 bit)\r
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#define __REV                             __rev\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (16 bit)\r
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
-  rev16 r0, r0\r
-  bx lr\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (16 bit)\r
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\r
-{\r
-  revsh r0, r0\r
-  bx lr\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Rotate Right in unsigned value (32 bit)\r
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-  \param [in]    op1  Value to rotate\r
-  \param [in]    op2  Number of Bits to rotate\r
-  \return               Rotated value\r
- */\r
-#define __ROR                             __ror\r
-\r
-\r
-/**\r
-  \brief   Breakpoint\r
-  \details Causes the processor to enter Debug state.\r
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-  \param [in]    value  is ignored by the processor.\r
-                 If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value)                       __breakpoint(value)\r
-\r
-\r
-/**\r
-  \brief   Reverse bit order of value\r
-  \details Reverses the bit order of the given value.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
-  #define __RBIT                          __rbit\r
-#else\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
-  uint32_t result;\r
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
-\r
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r
-  for (value >>= 1U; value != 0U; value >>= 1U)\r
-  {\r
-    result <<= 1U;\r
-    result |= value & 1U;\r
-    s--;\r
-  }\r
-  result <<= s;                        /* shift when v's highest bits are zero */\r
-  return result;\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Count leading zeros\r
-  \details Counts the number of leading zeros of a data value.\r
-  \param [in]  value  Value to count the leading zeros\r
-  \return             number of leading zeros in value\r
- */\r
-#define __CLZ                             __clz\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
-\r
-/**\r
-  \brief   LDR Exclusive (8 bit)\r
-  \details Executes a exclusive LDR instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\r
-#else\r
-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   LDR Exclusive (16 bit)\r
-  \details Executes a exclusive LDR instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\r
-#else\r
-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   LDR Exclusive (32 bit)\r
-  \details Executes a exclusive LDR instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\r
-#else\r
-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (8 bit)\r
-  \details Executes a exclusive STR instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\r
-#else\r
-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (16 bit)\r
-  \details Executes a exclusive STR instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\r
-#else\r
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (32 bit)\r
-  \details Executes a exclusive STR instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\r
-#else\r
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Remove the exclusive lock\r
-  \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-#define __CLREX                           __clrex\r
-\r
-\r
-/**\r
-  \brief   Signed Saturate\r
-  \details Saturates a signed value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (1..32)\r
-  \return             Saturated value\r
- */\r
-#define __SSAT                            __ssat\r
-\r
-\r
-/**\r
-  \brief   Unsigned Saturate\r
-  \details Saturates an unsigned value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (0..31)\r
-  \return             Saturated value\r
- */\r
-#define __USAT                            __usat\r
-\r
-\r
-/**\r
-  \brief   Rotate Right with Extend (32 bit)\r
-  \details Moves each bit of a bitstring right by one bit.\r
-           The carry input is shifted in at the left end of the bitstring.\r
-  \param [in]    value  Value to rotate\r
-  \return               Rotated value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
-{\r
-  rrx r0, r0\r
-  bx lr\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (8 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (16 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (32 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (8 bit)\r
-  \details Executes a Unprivileged STRT instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-#define __STRBT(value, ptr)               __strt(value, ptr)\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (16 bit)\r
-  \details Executes a Unprivileged STRT instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-#define __STRHT(value, ptr)               __strt(value, ptr)\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (32 bit)\r
-  \details Executes a Unprivileged STRT instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-#define __STRT(value, ptr)                __strt(value, ptr)\r
-\r
-#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
-\r
-/**\r
-  \brief   Signed Saturate\r
-  \details Saturates a signed value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (1..32)\r
-  \return             Saturated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
-{\r
-  if ((sat >= 1U) && (sat <= 32U))\r
-  {\r
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
-    const int32_t min = -1 - max ;\r
-    if (val > max)\r
-    {\r
-      return max;\r
-    }\r
-    else if (val < min)\r
-    {\r
-      return min;\r
-    }\r
-  }\r
-  return val;\r
-}\r
-\r
-/**\r
-  \brief   Unsigned Saturate\r
-  \details Saturates an unsigned value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (0..31)\r
-  \return             Saturated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
-{\r
-  if (sat <= 31U)\r
-  {\r
-    const uint32_t max = ((1U << sat) - 1U);\r
-    if (val > (int32_t)max)\r
-    {\r
-      return max;\r
-    }\r
-    else if (val < 0)\r
-    {\r
-      return 0U;\r
-    }\r
-  }\r
-  return (uint32_t)val;\r
-}\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ###################  Compiler specific Intrinsics  ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
-  Access to dedicated SIMD instructions\r
-  @{\r
-*/\r
-\r
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\r
-\r
-#define __SADD8                           __sadd8\r
-#define __QADD8                           __qadd8\r
-#define __SHADD8                          __shadd8\r
-#define __UADD8                           __uadd8\r
-#define __UQADD8                          __uqadd8\r
-#define __UHADD8                          __uhadd8\r
-#define __SSUB8                           __ssub8\r
-#define __QSUB8                           __qsub8\r
-#define __SHSUB8                          __shsub8\r
-#define __USUB8                           __usub8\r
-#define __UQSUB8                          __uqsub8\r
-#define __UHSUB8                          __uhsub8\r
-#define __SADD16                          __sadd16\r
-#define __QADD16                          __qadd16\r
-#define __SHADD16                         __shadd16\r
-#define __UADD16                          __uadd16\r
-#define __UQADD16                         __uqadd16\r
-#define __UHADD16                         __uhadd16\r
-#define __SSUB16                          __ssub16\r
-#define __QSUB16                          __qsub16\r
-#define __SHSUB16                         __shsub16\r
-#define __USUB16                          __usub16\r
-#define __UQSUB16                         __uqsub16\r
-#define __UHSUB16                         __uhsub16\r
-#define __SASX                            __sasx\r
-#define __QASX                            __qasx\r
-#define __SHASX                           __shasx\r
-#define __UASX                            __uasx\r
-#define __UQASX                           __uqasx\r
-#define __UHASX                           __uhasx\r
-#define __SSAX                            __ssax\r
-#define __QSAX                            __qsax\r
-#define __SHSAX                           __shsax\r
-#define __USAX                            __usax\r
-#define __UQSAX                           __uqsax\r
-#define __UHSAX                           __uhsax\r
-#define __USAD8                           __usad8\r
-#define __USADA8                          __usada8\r
-#define __SSAT16                          __ssat16\r
-#define __USAT16                          __usat16\r
-#define __UXTB16                          __uxtb16\r
-#define __UXTAB16                         __uxtab16\r
-#define __SXTB16                          __sxtb16\r
-#define __SXTAB16                         __sxtab16\r
-#define __SMUAD                           __smuad\r
-#define __SMUADX                          __smuadx\r
-#define __SMLAD                           __smlad\r
-#define __SMLADX                          __smladx\r
-#define __SMLALD                          __smlald\r
-#define __SMLALDX                         __smlaldx\r
-#define __SMUSD                           __smusd\r
-#define __SMUSDX                          __smusdx\r
-#define __SMLSD                           __smlsd\r
-#define __SMLSDX                          __smlsdx\r
-#define __SMLSLD                          __smlsld\r
-#define __SMLSLDX                         __smlsldx\r
-#define __SEL                             __sel\r
-#define __QADD                            __qadd\r
-#define __QSUB                            __qsub\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\r
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\r
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r
-\r
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\r
-\r
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#endif /* __CMSIS_ARMCC_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_armclang.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_armclang.h
deleted file mode 100644 (file)
index d8031b0..0000000
+++ /dev/null
@@ -1,1869 +0,0 @@
-/**************************************************************************//**\r
- * @file     cmsis_armclang.h\r
- * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\r
- * @version  V5.0.4\r
- * @date     10. January 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\r
-\r
-#ifndef __CMSIS_ARMCLANG_H\r
-#define __CMSIS_ARMCLANG_H\r
-\r
-#pragma clang system_header   /* treat file as system include file */\r
-\r
-#ifndef __ARM_COMPAT_H\r
-#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */\r
-#endif\r
-\r
-/* CMSIS compiler specific defines */\r
-#ifndef   __ASM\r
-  #define __ASM                                  __asm\r
-#endif\r
-#ifndef   __INLINE\r
-  #define __INLINE                               __inline\r
-#endif\r
-#ifndef   __STATIC_INLINE\r
-  #define __STATIC_INLINE                        static __inline\r
-#endif\r
-#ifndef   __STATIC_FORCEINLINE                 \r
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\r
-#endif                                           \r
-#ifndef   __NO_RETURN\r
-  #define __NO_RETURN                            __attribute__((__noreturn__))\r
-#endif\r
-#ifndef   __USED\r
-  #define __USED                                 __attribute__((used))\r
-#endif\r
-#ifndef   __WEAK\r
-  #define __WEAK                                 __attribute__((weak))\r
-#endif\r
-#ifndef   __PACKED\r
-  #define __PACKED                               __attribute__((packed, aligned(1)))\r
-#endif\r
-#ifndef   __PACKED_STRUCT\r
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\r
-#endif\r
-#ifndef   __PACKED_UNION\r
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32        /* deprecated */\r
-  #pragma clang diagnostic push\r
-  #pragma clang diagnostic ignored "-Wpacked"\r
-/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\r
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
-  #pragma clang diagnostic pop\r
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
-#endif\r
-#ifndef   __UNALIGNED_UINT16_WRITE\r
-  #pragma clang diagnostic push\r
-  #pragma clang diagnostic ignored "-Wpacked"\r
-/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\r
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
-  #pragma clang diagnostic pop\r
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT16_READ\r
-  #pragma clang diagnostic push\r
-  #pragma clang diagnostic ignored "-Wpacked"\r
-/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\r
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
-  #pragma clang diagnostic pop\r
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32_WRITE\r
-  #pragma clang diagnostic push\r
-  #pragma clang diagnostic ignored "-Wpacked"\r
-/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\r
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
-  #pragma clang diagnostic pop\r
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32_READ\r
-  #pragma clang diagnostic push\r
-  #pragma clang diagnostic ignored "-Wpacked"\r
-/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\r
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
-  #pragma clang diagnostic pop\r
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
-#endif\r
-#ifndef   __ALIGNED\r
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
-#endif\r
-#ifndef   __RESTRICT\r
-  #define __RESTRICT                             __restrict\r
-#endif\r
-\r
-\r
-/* ###########################  Core Function Access  ########################### */\r
-/** \ingroup  CMSIS_Core_FunctionInterface\r
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Enable IRQ Interrupts\r
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-/* intrinsic void __enable_irq();  see arm_compat.h */\r
-\r
-\r
-/**\r
-  \brief   Disable IRQ Interrupts\r
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-/* intrinsic void __disable_irq();  see arm_compat.h */\r
-\r
-\r
-/**\r
-  \brief   Get Control Register\r
-  \details Returns the content of the Control Register.\r
-  \return               Control Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Control Register (non-secure)\r
-  \details Returns the content of the non-secure Control Register when in secure mode.\r
-  \return               non-secure Control Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Control Register\r
-  \details Writes the given value to the Control Register.\r
-  \param [in]    control  Control Register value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
-{\r
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Control Register (non-secure)\r
-  \details Writes the given value to the non-secure Control Register when in secure state.\r
-  \param [in]    control  Control Register value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
-{\r
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get IPSR Register\r
-  \details Returns the content of the IPSR Register.\r
-  \return               IPSR Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get APSR Register\r
-  \details Returns the content of the APSR Register.\r
-  \return               APSR Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get xPSR Register\r
-  \details Returns the content of the xPSR Register.\r
-  \return               xPSR Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Process Stack Pointer\r
-  \details Returns the current value of the Process Stack Pointer (PSP).\r
-  \return               PSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Process Stack Pointer (non-secure)\r
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
-  \return               PSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Process Stack Pointer\r
-  \details Assigns the given value to the Process Stack Pointer (PSP).\r
-  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Process Stack Pointer (non-secure)\r
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
-  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
-{\r
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get Main Stack Pointer\r
-  \details Returns the current value of the Main Stack Pointer (MSP).\r
-  \return               MSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Main Stack Pointer (non-secure)\r
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
-  \return               MSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Main Stack Pointer\r
-  \details Assigns the given value to the Main Stack Pointer (MSP).\r
-  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Main Stack Pointer (non-secure)\r
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
-  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
-{\r
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
-}\r
-#endif\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Stack Pointer (non-secure)\r
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
-  \return               SP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Stack Pointer (non-secure)\r
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
-  \param [in]    topOfStack  Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
-{\r
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get Priority Mask\r
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
-  \return               Priority Mask value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Priority Mask (non-secure)\r
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
-  \return               Priority Mask value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Priority Mask\r
-  \details Assigns the given value to the Priority Mask Register.\r
-  \param [in]    priMask  Priority Mask\r
- */\r
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Priority Mask (non-secure)\r
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
-  \param [in]    priMask  Priority Mask\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
-{\r
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
-/**\r
-  \brief   Enable FIQ\r
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */\r
-\r
-\r
-/**\r
-  \brief   Disable FIQ\r
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */\r
-\r
-\r
-/**\r
-  \brief   Get Base Priority\r
-  \details Returns the current value of the Base Priority register.\r
-  \return               Base Priority register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Base Priority (non-secure)\r
-  \details Returns the current value of the non-secure Base Priority register when in secure state.\r
-  \return               Base Priority register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Base Priority\r
-  \details Assigns the given value to the Base Priority register.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Base Priority (non-secure)\r
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
-{\r
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Base Priority with condition\r
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
-           or the new value increases the BASEPRI priority level.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
-{\r
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Fault Mask\r
-  \details Returns the current value of the Fault Mask register.\r
-  \return               Fault Mask register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Fault Mask (non-secure)\r
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
-  \return               Fault Mask register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Fault Mask\r
-  \details Assigns the given value to the Fault Mask register.\r
-  \param [in]    faultMask  Fault Mask value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Fault Mask (non-secure)\r
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
-  \param [in]    faultMask  Fault Mask value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
-{\r
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
-}\r
-#endif\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
-\r
-\r
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-\r
-/**\r
-  \brief   Get Process Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always in non-secure\r
-  mode.\r
-  \r
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
-  \return               PSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-\r
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Process Stack Pointer Limit (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always in non-secure\r
-  mode.\r
-\r
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
-  \return               PSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Process Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
-  mode.\r
-  \r
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  (void)ProcStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
-#endif\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
-/**\r
-  \brief   Set Process Stack Pointer (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
-  mode.\r
-\r
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  (void)ProcStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
-#endif\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get Main Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always.\r
-\r
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
-  \return               MSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
-/**\r
-  \brief   Get Main Stack Pointer Limit (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always.\r
-\r
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
-  \return               MSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Main Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored.\r
-\r
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  (void)MainStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
-#endif\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
-/**\r
-  \brief   Set Main Stack Pointer Limit (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored.\r
-\r
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  (void)MainStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
-#endif\r
-}\r
-#endif\r
-\r
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
-\r
-/**\r
-  \brief   Get FPSCR\r
-  \details Returns the current value of the Floating Point Status/Control register.\r
-  \return               Floating Point Status/Control register value\r
- */\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\r
-#else\r
-#define __get_FPSCR()      ((uint32_t)0U)\r
-#endif\r
-\r
-/**\r
-  \brief   Set FPSCR\r
-  \details Assigns the given value to the Floating Point Status/Control register.\r
-  \param [in]    fpscr  Floating Point Status/Control value to set\r
- */\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-#define __set_FPSCR      __builtin_arm_set_fpscr\r
-#else\r
-#define __set_FPSCR(x)      ((void)(x))\r
-#endif\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ##########################  Core Instruction Access  ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
-  Access to dedicated instructions\r
-  @{\r
-*/\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constraint "l"\r
- * Otherwise, use general registers, specified by constraint "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/**\r
-  \brief   No Operation\r
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP          __builtin_arm_nop\r
-\r
-/**\r
-  \brief   Wait For Interrupt\r
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-#define __WFI          __builtin_arm_wfi\r
-\r
-\r
-/**\r
-  \brief   Wait For Event\r
-  \details Wait For Event is a hint instruction that permits the processor to enter\r
-           a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE          __builtin_arm_wfe\r
-\r
-\r
-/**\r
-  \brief   Send Event\r
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV          __builtin_arm_sev\r
-\r
-\r
-/**\r
-  \brief   Instruction Synchronization Barrier\r
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
-           so that all instructions following the ISB are fetched from cache or memory,\r
-           after the instruction has been completed.\r
- */\r
-#define __ISB()        __builtin_arm_isb(0xF);\r
-\r
-/**\r
-  \brief   Data Synchronization Barrier\r
-  \details Acts as a special kind of Data Memory Barrier.\r
-           It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB()        __builtin_arm_dsb(0xF);\r
-\r
-\r
-/**\r
-  \brief   Data Memory Barrier\r
-  \details Ensures the apparent order of the explicit memory operations before\r
-           and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB()        __builtin_arm_dmb(0xF);\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (32 bit)\r
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#define __REV(value)   __builtin_bswap32(value)\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (16 bit)\r
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#define __REV16(value) __ROR(__REV(value), 16)\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (16 bit)\r
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#define __REVSH(value) (int16_t)__builtin_bswap16(value)\r
-\r
-\r
-/**\r
-  \brief   Rotate Right in unsigned value (32 bit)\r
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-  \param [in]    op1  Value to rotate\r
-  \param [in]    op2  Number of Bits to rotate\r
-  \return               Rotated value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
-  op2 %= 32U;\r
-  if (op2 == 0U)\r
-  {\r
-    return op1;\r
-  }\r
-  return (op1 >> op2) | (op1 << (32U - op2));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Breakpoint\r
-  \details Causes the processor to enter Debug state.\r
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-  \param [in]    value  is ignored by the processor.\r
-                 If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value)     __ASM volatile ("bkpt "#value)\r
-\r
-\r
-/**\r
-  \brief   Reverse bit order of value\r
-  \details Reverses the bit order of the given value.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-#define __RBIT            __builtin_arm_rbit\r
-\r
-/**\r
-  \brief   Count leading zeros\r
-  \details Counts the number of leading zeros of a data value.\r
-  \param [in]  value  Value to count the leading zeros\r
-  \return             number of leading zeros in value\r
- */\r
-#define __CLZ             (uint8_t)__builtin_clz\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-/**\r
-  \brief   LDR Exclusive (8 bit)\r
-  \details Executes a exclusive LDR instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex\r
-\r
-\r
-/**\r
-  \brief   LDR Exclusive (16 bit)\r
-  \details Executes a exclusive LDR instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex\r
-\r
-\r
-/**\r
-  \brief   LDR Exclusive (32 bit)\r
-  \details Executes a exclusive LDR instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (8 bit)\r
-  \details Executes a exclusive STR instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#define __STREXB        (uint32_t)__builtin_arm_strex\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (16 bit)\r
-  \details Executes a exclusive STR instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#define __STREXH        (uint32_t)__builtin_arm_strex\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (32 bit)\r
-  \details Executes a exclusive STR instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#define __STREXW        (uint32_t)__builtin_arm_strex\r
-\r
-\r
-/**\r
-  \brief   Remove the exclusive lock\r
-  \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-#define __CLREX             __builtin_arm_clrex\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
-\r
-/**\r
-  \brief   Signed Saturate\r
-  \details Saturates a signed value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (1..32)\r
-  \return             Saturated value\r
- */\r
-#define __SSAT             __builtin_arm_ssat\r
-\r
-\r
-/**\r
-  \brief   Unsigned Saturate\r
-  \details Saturates an unsigned value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (0..31)\r
-  \return             Saturated value\r
- */\r
-#define __USAT             __builtin_arm_usat\r
-\r
-\r
-/**\r
-  \brief   Rotate Right with Extend (32 bit)\r
-  \details Moves each bit of a bitstring right by one bit.\r
-           The carry input is shifted in at the left end of the bitstring.\r
-  \param [in]    value  Value to rotate\r
-  \return               Rotated value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (8 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-  return ((uint8_t) result);    /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (16 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-  return ((uint16_t) result);    /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (32 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (8 bit)\r
-  \details Executes a Unprivileged STRT instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
-{\r
-  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (16 bit)\r
-  \details Executes a Unprivileged STRT instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
-{\r
-  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (32 bit)\r
-  \details Executes a Unprivileged STRT instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
-{\r
-  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
-}\r
-\r
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
-\r
-/**\r
-  \brief   Signed Saturate\r
-  \details Saturates a signed value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (1..32)\r
-  \return             Saturated value\r
- */\r
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
-{\r
-  if ((sat >= 1U) && (sat <= 32U))\r
-  {\r
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
-    const int32_t min = -1 - max ;\r
-    if (val > max)\r
-    {\r
-      return max;\r
-    }\r
-    else if (val < min)\r
-    {\r
-      return min;\r
-    }\r
-  }\r
-  return val;\r
-}\r
-\r
-/**\r
-  \brief   Unsigned Saturate\r
-  \details Saturates an unsigned value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (0..31)\r
-  \return             Saturated value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
-{\r
-  if (sat <= 31U)\r
-  {\r
-    const uint32_t max = ((1U << sat) - 1U);\r
-    if (val > (int32_t)max)\r
-    {\r
-      return max;\r
-    }\r
-    else if (val < 0)\r
-    {\r
-      return 0U;\r
-    }\r
-  }\r
-  return (uint32_t)val;\r
-}\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
-\r
-\r
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-/**\r
-  \brief   Load-Acquire (8 bit)\r
-  \details Executes a LDAB instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-  return ((uint8_t) result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire (16 bit)\r
-  \details Executes a LDAH instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-  return ((uint16_t) result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire (32 bit)\r
-  \details Executes a LDA instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release (8 bit)\r
-  \details Executes a STLB instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
-{\r
-  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release (16 bit)\r
-  \details Executes a STLH instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
-{\r
-  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release (32 bit)\r
-  \details Executes a STL instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
-{\r
-  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire Exclusive (8 bit)\r
-  \details Executes a LDAB exclusive instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire Exclusive (16 bit)\r
-  \details Executes a LDAH exclusive instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire Exclusive (32 bit)\r
-  \details Executes a LDA exclusive instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\r
-\r
-\r
-/**\r
-  \brief   Store-Release Exclusive (8 bit)\r
-  \details Executes a STLB exclusive instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\r
-\r
-\r
-/**\r
-  \brief   Store-Release Exclusive (16 bit)\r
-  \details Executes a STLH exclusive instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\r
-\r
-\r
-/**\r
-  \brief   Store-Release Exclusive (32 bit)\r
-  \details Executes a STL exclusive instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex\r
-\r
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ###################  Compiler specific Intrinsics  ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
-  Access to dedicated SIMD instructions\r
-  @{\r
-*/\r
-\r
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
-\r
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-\r
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-\r
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-#define __SSAT16(ARG1,ARG2) \\r
-({                          \\r
-  int32_t __RES, __ARG1 = (ARG1); \\r
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
-  __RES; \\r
- })\r
-\r
-#define __USAT16(ARG1,ARG2) \\r
-({                          \\r
-  uint32_t __RES, __ARG1 = (ARG1); \\r
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
-  __RES; \\r
- })\r
-\r
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r
-{\r
-  int32_t result;\r
-\r
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r
-{\r
-  int32_t result;\r
-\r
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-#if 0\r
-#define __PKHBT(ARG1,ARG2,ARG3) \\r
-({                          \\r
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
-  __RES; \\r
- })\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) \\r
-({                          \\r
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
-  if (ARG3 == 0) \\r
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \\r
-  else \\r
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
-  __RES; \\r
- })\r
-#endif\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\r
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\r
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r
-\r
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
-{\r
-  int32_t result;\r
-\r
-  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-#endif /* (__ARM_FEATURE_DSP == 1) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#endif /* __CMSIS_ARMCLANG_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_compiler.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_compiler.h
deleted file mode 100644 (file)
index 79a2cac..0000000
+++ /dev/null
@@ -1,266 +0,0 @@
-/**************************************************************************//**\r
- * @file     cmsis_compiler.h\r
- * @brief    CMSIS compiler generic header file\r
- * @version  V5.0.4\r
- * @date     10. January 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#ifndef __CMSIS_COMPILER_H\r
-#define __CMSIS_COMPILER_H\r
-\r
-#include <stdint.h>\r
-\r
-/*\r
- * Arm Compiler 4/5\r
- */\r
-#if   defined ( __CC_ARM )\r
-  #include "cmsis_armcc.h"\r
-\r
-\r
-/*\r
- * Arm Compiler 6 (armclang)\r
- */\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #include "cmsis_armclang.h"\r
-\r
-\r
-/*\r
- * GNU Compiler\r
- */\r
-#elif defined ( __GNUC__ )\r
-  #include "cmsis_gcc.h"\r
-\r
-\r
-/*\r
- * IAR Compiler\r
- */\r
-#elif defined ( __ICCARM__ )\r
-  #include <cmsis_iccarm.h>\r
-\r
-\r
-/*\r
- * TI Arm Compiler\r
- */\r
-#elif defined ( __TI_ARM__ )\r
-  #include <cmsis_ccs.h>\r
-\r
-  #ifndef   __ASM\r
-    #define __ASM                                  __asm\r
-  #endif\r
-  #ifndef   __INLINE\r
-    #define __INLINE                               inline\r
-  #endif\r
-  #ifndef   __STATIC_INLINE\r
-    #define __STATIC_INLINE                        static inline\r
-  #endif\r
-  #ifndef   __STATIC_FORCEINLINE\r
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\r
-  #endif\r
-  #ifndef   __NO_RETURN\r
-    #define __NO_RETURN                            __attribute__((noreturn))\r
-  #endif\r
-  #ifndef   __USED\r
-    #define __USED                                 __attribute__((used))\r
-  #endif\r
-  #ifndef   __WEAK\r
-    #define __WEAK                                 __attribute__((weak))\r
-  #endif\r
-  #ifndef   __PACKED\r
-    #define __PACKED                               __attribute__((packed))\r
-  #endif\r
-  #ifndef   __PACKED_STRUCT\r
-    #define __PACKED_STRUCT                        struct __attribute__((packed))\r
-  #endif\r
-  #ifndef   __PACKED_UNION\r
-    #define __PACKED_UNION                         union __attribute__((packed))\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */\r
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT16_WRITE\r
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT16_READ\r
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32_WRITE\r
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32_READ\r
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
-  #endif\r
-  #ifndef   __ALIGNED\r
-    #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
-  #endif\r
-  #ifndef   __RESTRICT\r
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
-    #define __RESTRICT\r
-  #endif\r
-\r
-\r
-/*\r
- * TASKING Compiler\r
- */\r
-#elif defined ( __TASKING__ )\r
-  /*\r
-   * The CMSIS functions have been implemented as intrinsics in the compiler.\r
-   * Please use "carm -?i" to get an up to date list of all intrinsics,\r
-   * Including the CMSIS ones.\r
-   */\r
-\r
-  #ifndef   __ASM\r
-    #define __ASM                                  __asm\r
-  #endif\r
-  #ifndef   __INLINE\r
-    #define __INLINE                               inline\r
-  #endif\r
-  #ifndef   __STATIC_INLINE\r
-    #define __STATIC_INLINE                        static inline\r
-  #endif\r
-  #ifndef   __STATIC_FORCEINLINE\r
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\r
-  #endif\r
-  #ifndef   __NO_RETURN\r
-    #define __NO_RETURN                            __attribute__((noreturn))\r
-  #endif\r
-  #ifndef   __USED\r
-    #define __USED                                 __attribute__((used))\r
-  #endif\r
-  #ifndef   __WEAK\r
-    #define __WEAK                                 __attribute__((weak))\r
-  #endif\r
-  #ifndef   __PACKED\r
-    #define __PACKED                               __packed__\r
-  #endif\r
-  #ifndef   __PACKED_STRUCT\r
-    #define __PACKED_STRUCT                        struct __packed__\r
-  #endif\r
-  #ifndef   __PACKED_UNION\r
-    #define __PACKED_UNION                         union __packed__\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */\r
-    struct __packed__ T_UINT32 { uint32_t v; };\r
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT16_WRITE\r
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT16_READ\r
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32_WRITE\r
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32_READ\r
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
-  #endif\r
-  #ifndef   __ALIGNED\r
-    #define __ALIGNED(x)              __align(x)\r
-  #endif\r
-  #ifndef   __RESTRICT\r
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
-    #define __RESTRICT\r
-  #endif\r
-\r
-\r
-/*\r
- * COSMIC Compiler\r
- */\r
-#elif defined ( __CSMC__ )\r
-   #include <cmsis_csm.h>\r
-\r
- #ifndef   __ASM\r
-    #define __ASM                                  _asm\r
-  #endif\r
-  #ifndef   __INLINE\r
-    #define __INLINE                               inline\r
-  #endif\r
-  #ifndef   __STATIC_INLINE\r
-    #define __STATIC_INLINE                        static inline\r
-  #endif\r
-  #ifndef   __STATIC_FORCEINLINE\r
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\r
-  #endif\r
-  #ifndef   __NO_RETURN\r
-    // NO RETURN is automatically detected hence no warning here\r
-    #define __NO_RETURN\r
-  #endif\r
-  #ifndef   __USED\r
-    #warning No compiler specific solution for __USED. __USED is ignored.\r
-    #define __USED\r
-  #endif\r
-  #ifndef   __WEAK\r
-    #define __WEAK                                 __weak\r
-  #endif\r
-  #ifndef   __PACKED\r
-    #define __PACKED                               @packed\r
-  #endif\r
-  #ifndef   __PACKED_STRUCT\r
-    #define __PACKED_STRUCT                        @packed struct\r
-  #endif\r
-  #ifndef   __PACKED_UNION\r
-    #define __PACKED_UNION                         @packed union\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */\r
-    @packed struct T_UINT32 { uint32_t v; };\r
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT16_WRITE\r
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT16_READ\r
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32_WRITE\r
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
-  #endif\r
-  #ifndef   __UNALIGNED_UINT32_READ\r
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
-  #endif\r
-  #ifndef   __ALIGNED\r
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
-    #define __ALIGNED(x)\r
-  #endif\r
-  #ifndef   __RESTRICT\r
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
-    #define __RESTRICT\r
-  #endif\r
-\r
-\r
-#else\r
-  #error Unknown compiler.\r
-#endif\r
-\r
-\r
-#endif /* __CMSIS_COMPILER_H */\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_gcc.h
deleted file mode 100644 (file)
index 1bd41a4..0000000
+++ /dev/null
@@ -1,2085 +0,0 @@
-/**************************************************************************//**\r
- * @file     cmsis_gcc.h\r
- * @brief    CMSIS compiler GCC header file\r
- * @version  V5.0.4\r
- * @date     09. April 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#ifndef __CMSIS_GCC_H\r
-#define __CMSIS_GCC_H\r
-\r
-/* ignore some GCC warnings */\r
-#pragma GCC diagnostic push\r
-#pragma GCC diagnostic ignored "-Wsign-conversion"\r
-#pragma GCC diagnostic ignored "-Wconversion"\r
-#pragma GCC diagnostic ignored "-Wunused-parameter"\r
-\r
-/* Fallback for __has_builtin */\r
-#ifndef __has_builtin\r
-  #define __has_builtin(x) (0)\r
-#endif\r
-\r
-/* CMSIS compiler specific defines */\r
-#ifndef   __ASM\r
-  #define __ASM                                  __asm\r
-#endif\r
-#ifndef   __INLINE\r
-  #define __INLINE                               inline\r
-#endif\r
-#ifndef   __STATIC_INLINE\r
-  #define __STATIC_INLINE                        static inline\r
-#endif\r
-#ifndef   __STATIC_FORCEINLINE                 \r
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\r
-#endif                                           \r
-#ifndef   __NO_RETURN\r
-  #define __NO_RETURN                            __attribute__((__noreturn__))\r
-#endif\r
-#ifndef   __USED\r
-  #define __USED                                 __attribute__((used))\r
-#endif\r
-#ifndef   __WEAK\r
-  #define __WEAK                                 __attribute__((weak))\r
-#endif\r
-#ifndef   __PACKED\r
-  #define __PACKED                               __attribute__((packed, aligned(1)))\r
-#endif\r
-#ifndef   __PACKED_STRUCT\r
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\r
-#endif\r
-#ifndef   __PACKED_UNION\r
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32        /* deprecated */\r
-  #pragma GCC diagnostic push\r
-  #pragma GCC diagnostic ignored "-Wpacked"\r
-  #pragma GCC diagnostic ignored "-Wattributes"\r
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
-  #pragma GCC diagnostic pop\r
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\r
-#endif\r
-#ifndef   __UNALIGNED_UINT16_WRITE\r
-  #pragma GCC diagnostic push\r
-  #pragma GCC diagnostic ignored "-Wpacked"\r
-  #pragma GCC diagnostic ignored "-Wattributes"\r
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
-  #pragma GCC diagnostic pop\r
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT16_READ\r
-  #pragma GCC diagnostic push\r
-  #pragma GCC diagnostic ignored "-Wpacked"\r
-  #pragma GCC diagnostic ignored "-Wattributes"\r
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
-  #pragma GCC diagnostic pop\r
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32_WRITE\r
-  #pragma GCC diagnostic push\r
-  #pragma GCC diagnostic ignored "-Wpacked"\r
-  #pragma GCC diagnostic ignored "-Wattributes"\r
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
-  #pragma GCC diagnostic pop\r
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
-#endif\r
-#ifndef   __UNALIGNED_UINT32_READ\r
-  #pragma GCC diagnostic push\r
-  #pragma GCC diagnostic ignored "-Wpacked"\r
-  #pragma GCC diagnostic ignored "-Wattributes"\r
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
-  #pragma GCC diagnostic pop\r
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
-#endif\r
-#ifndef   __ALIGNED\r
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))\r
-#endif\r
-#ifndef   __RESTRICT\r
-  #define __RESTRICT                             __restrict\r
-#endif\r
-\r
-\r
-/* ###########################  Core Function Access  ########################### */\r
-/** \ingroup  CMSIS_Core_FunctionInterface\r
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Enable IRQ Interrupts\r
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-__STATIC_FORCEINLINE void __enable_irq(void)\r
-{\r
-  __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable IRQ Interrupts\r
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-__STATIC_FORCEINLINE void __disable_irq(void)\r
-{\r
-  __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Control Register\r
-  \details Returns the content of the Control Register.\r
-  \return               Control Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Control Register (non-secure)\r
-  \details Returns the content of the non-secure Control Register when in secure mode.\r
-  \return               non-secure Control Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Control Register\r
-  \details Writes the given value to the Control Register.\r
-  \param [in]    control  Control Register value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
-{\r
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Control Register (non-secure)\r
-  \details Writes the given value to the non-secure Control Register when in secure state.\r
-  \param [in]    control  Control Register value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
-{\r
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get IPSR Register\r
-  \details Returns the content of the IPSR Register.\r
-  \return               IPSR Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get APSR Register\r
-  \details Returns the content of the APSR Register.\r
-  \return               APSR Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get xPSR Register\r
-  \details Returns the content of the xPSR Register.\r
-  \return               xPSR Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Process Stack Pointer\r
-  \details Returns the current value of the Process Stack Pointer (PSP).\r
-  \return               PSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Process Stack Pointer (non-secure)\r
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
-  \return               PSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Process Stack Pointer\r
-  \details Assigns the given value to the Process Stack Pointer (PSP).\r
-  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Process Stack Pointer (non-secure)\r
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
-  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
-{\r
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get Main Stack Pointer\r
-  \details Returns the current value of the Main Stack Pointer (MSP).\r
-  \return               MSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Main Stack Pointer (non-secure)\r
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
-  \return               MSP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Main Stack Pointer\r
-  \details Assigns the given value to the Main Stack Pointer (MSP).\r
-  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Main Stack Pointer (non-secure)\r
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
-  \param [in]    topOfMainStack  Main Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
-{\r
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
-}\r
-#endif\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Stack Pointer (non-secure)\r
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
-  \return               SP Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Stack Pointer (non-secure)\r
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
-  \param [in]    topOfStack  Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
-{\r
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get Priority Mask\r
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
-  \return               Priority Mask value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Priority Mask (non-secure)\r
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
-  \return               Priority Mask value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Priority Mask\r
-  \details Assigns the given value to the Priority Mask Register.\r
-  \param [in]    priMask  Priority Mask\r
- */\r
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Priority Mask (non-secure)\r
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
-  \param [in]    priMask  Priority Mask\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
-{\r
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
-/**\r
-  \brief   Enable FIQ\r
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-__STATIC_FORCEINLINE void __enable_fault_irq(void)\r
-{\r
-  __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable FIQ\r
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
-           Can only be executed in Privileged modes.\r
- */\r
-__STATIC_FORCEINLINE void __disable_fault_irq(void)\r
-{\r
-  __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Base Priority\r
-  \details Returns the current value of the Base Priority register.\r
-  \return               Base Priority register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Base Priority (non-secure)\r
-  \details Returns the current value of the non-secure Base Priority register when in secure state.\r
-  \return               Base Priority register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Base Priority\r
-  \details Assigns the given value to the Base Priority register.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Base Priority (non-secure)\r
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
-{\r
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Base Priority with condition\r
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
-           or the new value increases the BASEPRI priority level.\r
-  \param [in]    basePri  Base Priority value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
-{\r
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Fault Mask\r
-  \details Returns the current value of the Fault Mask register.\r
-  \return               Fault Mask register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
-  return(result);\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Fault Mask (non-secure)\r
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
-  \return               Fault Mask register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
-  return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Fault Mask\r
-  \details Assigns the given value to the Fault Mask register.\r
-  \param [in]    faultMask  Fault Mask value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Set Fault Mask (non-secure)\r
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
-  \param [in]    faultMask  Fault Mask value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
-{\r
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
-}\r
-#endif\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
-\r
-\r
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-\r
-/**\r
-  \brief   Get Process Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always in non-secure\r
-  mode.\r
-  \r
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
-  \return               PSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-\r
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
-/**\r
-  \brief   Get Process Stack Pointer Limit (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always.\r
-\r
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
-  \return               PSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Process Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
-  mode.\r
-  \r
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  (void)ProcStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
-#endif\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
-/**\r
-  \brief   Set Process Stack Pointer (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored.\r
-\r
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-  (void)ProcStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
-#endif\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Get Main Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always in non-secure\r
-  mode.\r
-\r
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
-  \return               MSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
-/**\r
-  \brief   Get Main Stack Pointer Limit (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence zero is returned always.\r
-\r
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
-  \return               MSPLIM Register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  return 0U;\r
-#else\r
-  uint32_t result;\r
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
-  return result;\r
-#endif\r
-}\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Main Stack Pointer Limit\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored in non-secure\r
-  mode.\r
-\r
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  (void)MainStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
-#endif\r
-}\r
-\r
-\r
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\r
-/**\r
-  \brief   Set Main Stack Pointer Limit (non-secure)\r
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
-  Stack Pointer Limit register hence the write is silently ignored.\r
-\r
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set\r
- */\r
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
-{\r
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
-  // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-  (void)MainStackPtrLimit;\r
-#else\r
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
-#endif\r
-}\r
-#endif\r
-\r
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
-\r
-\r
-/**\r
-  \brief   Get FPSCR\r
-  \details Returns the current value of the Floating Point Status/Control register.\r
-  \return               Floating Point Status/Control register value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-#if __has_builtin(__builtin_arm_get_fpscr) \r
-// Re-enable using built-in when GCC has been fixed\r
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
-  return __builtin_arm_get_fpscr();\r
-#else\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
-  return(result);\r
-#endif\r
-#else\r
-  return(0U);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set FPSCR\r
-  \details Assigns the given value to the Floating Point Status/Control register.\r
-  \param [in]    fpscr  Floating Point Status/Control value to set\r
- */\r
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-#if __has_builtin(__builtin_arm_set_fpscr)\r
-// Re-enable using built-in when GCC has been fixed\r
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
-  __builtin_arm_set_fpscr(fpscr);\r
-#else\r
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");\r
-#endif\r
-#else\r
-  (void)fpscr;\r
-#endif\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ##########################  Core Instruction Access  ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
-  Access to dedicated instructions\r
-  @{\r
-*/\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constraint "l"\r
- * Otherwise, use general registers, specified by constraint "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/**\r
-  \brief   No Operation\r
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP()                             __ASM volatile ("nop")\r
-\r
-/**\r
-  \brief   Wait For Interrupt\r
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-#define __WFI()                             __ASM volatile ("wfi")\r
-\r
-\r
-/**\r
-  \brief   Wait For Event\r
-  \details Wait For Event is a hint instruction that permits the processor to enter\r
-           a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE()                             __ASM volatile ("wfe")\r
-\r
-\r
-/**\r
-  \brief   Send Event\r
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV()                             __ASM volatile ("sev")\r
-\r
-\r
-/**\r
-  \brief   Instruction Synchronization Barrier\r
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
-           so that all instructions following the ISB are fetched from cache or memory,\r
-           after the instruction has been completed.\r
- */\r
-__STATIC_FORCEINLINE void __ISB(void)\r
-{\r
-  __ASM volatile ("isb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Data Synchronization Barrier\r
-  \details Acts as a special kind of Data Memory Barrier.\r
-           It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__STATIC_FORCEINLINE void __DSB(void)\r
-{\r
-  __ASM volatile ("dsb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Data Memory Barrier\r
-  \details Ensures the apparent order of the explicit memory operations before\r
-           and after the instruction, without ensuring their completion.\r
- */\r
-__STATIC_FORCEINLINE void __DMB(void)\r
-{\r
-  __ASM volatile ("dmb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (32 bit)\r
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
-  return __builtin_bswap32(value);\r
-#else\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
-  return result;\r
-#endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (16 bit)\r
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
-  return result;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Reverse byte order (16 bit)\r
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
-  return (int16_t)__builtin_bswap16(value);\r
-#else\r
-  int16_t result;\r
-\r
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
-  return result;\r
-#endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Rotate Right in unsigned value (32 bit)\r
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-  \param [in]    op1  Value to rotate\r
-  \param [in]    op2  Number of Bits to rotate\r
-  \return               Rotated value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
-  op2 %= 32U;\r
-  if (op2 == 0U)\r
-  {\r
-    return op1;\r
-  }\r
-  return (op1 >> op2) | (op1 << (32U - op2));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Breakpoint\r
-  \details Causes the processor to enter Debug state.\r
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-  \param [in]    value  is ignored by the processor.\r
-                 If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)\r
-\r
-\r
-/**\r
-  \brief   Reverse bit order of value\r
-  \details Reverses the bit order of the given value.\r
-  \param [in]    value  Value to reverse\r
-  \return               Reversed value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\r
-{\r
-  uint32_t result;\r
-\r
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
-#else\r
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
-\r
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r
-  for (value >>= 1U; value != 0U; value >>= 1U)\r
-  {\r
-    result <<= 1U;\r
-    result |= value & 1U;\r
-    s--;\r
-  }\r
-  result <<= s;                        /* shift when v's highest bits are zero */\r
-#endif\r
-  return result;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Count leading zeros\r
-  \details Counts the number of leading zeros of a data value.\r
-  \param [in]  value  Value to count the leading zeros\r
-  \return             number of leading zeros in value\r
- */\r
-#define __CLZ             (uint8_t)__builtin_clz\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-/**\r
-  \brief   LDR Exclusive (8 bit)\r
-  \details Executes a exclusive LDR instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
-    uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
-       accepted by assembler. So has to use following less efficient pattern.\r
-    */\r
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
-   return ((uint8_t) result);    /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDR Exclusive (16 bit)\r
-  \details Executes a exclusive LDR instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
-    uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
-       accepted by assembler. So has to use following less efficient pattern.\r
-    */\r
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
-   return ((uint16_t) result);    /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDR Exclusive (32 bit)\r
-  \details Executes a exclusive LDR instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (8 bit)\r
-  \details Executes a exclusive STR instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
-   uint32_t result;\r
-\r
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (16 bit)\r
-  \details Executes a exclusive STR instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
-   uint32_t result;\r
-\r
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   STR Exclusive (32 bit)\r
-  \details Executes a exclusive STR instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
-   uint32_t result;\r
-\r
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Remove the exclusive lock\r
-  \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-__STATIC_FORCEINLINE void __CLREX(void)\r
-{\r
-  __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
-\r
-\r
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
-/**\r
-  \brief   Signed Saturate\r
-  \details Saturates a signed value.\r
-  \param [in]  ARG1  Value to be saturated\r
-  \param [in]  ARG2  Bit position to saturate to (1..32)\r
-  \return             Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-__extension__ \\r
-({                          \\r
-  int32_t __RES, __ARG1 = (ARG1); \\r
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
-  __RES; \\r
- })\r
-\r
-\r
-/**\r
-  \brief   Unsigned Saturate\r
-  \details Saturates an unsigned value.\r
-  \param [in]  ARG1  Value to be saturated\r
-  \param [in]  ARG2  Bit position to saturate to (0..31)\r
-  \return             Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
- __extension__ \\r
-({                          \\r
-  uint32_t __RES, __ARG1 = (ARG1); \\r
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
-  __RES; \\r
- })\r
-\r
-\r
-/**\r
-  \brief   Rotate Right with Extend (32 bit)\r
-  \details Moves each bit of a bitstring right by one bit.\r
-           The carry input is shifted in at the left end of the bitstring.\r
-  \param [in]    value  Value to rotate\r
-  \return               Rotated value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
-  return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (8 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-#else\r
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
-       accepted by assembler. So has to use following less efficient pattern.\r
-    */\r
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
-#endif\r
-   return ((uint8_t) result);    /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (16 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-#else\r
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
-       accepted by assembler. So has to use following less efficient pattern.\r
-    */\r
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
-#endif\r
-   return ((uint16_t) result);    /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
-  \brief   LDRT Unprivileged (32 bit)\r
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (8 bit)\r
-  \details Executes a Unprivileged STRT instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
-{\r
-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (16 bit)\r
-  \details Executes a Unprivileged STRT instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
-{\r
-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   STRT Unprivileged (32 bit)\r
-  \details Executes a Unprivileged STRT instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
-{\r
-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
-}\r
-\r
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
-\r
-/**\r
-  \brief   Signed Saturate\r
-  \details Saturates a signed value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (1..32)\r
-  \return             Saturated value\r
- */\r
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
-{\r
-  if ((sat >= 1U) && (sat <= 32U))\r
-  {\r
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
-    const int32_t min = -1 - max ;\r
-    if (val > max)\r
-    {\r
-      return max;\r
-    }\r
-    else if (val < min)\r
-    {\r
-      return min;\r
-    }\r
-  }\r
-  return val;\r
-}\r
-\r
-/**\r
-  \brief   Unsigned Saturate\r
-  \details Saturates an unsigned value.\r
-  \param [in]  value  Value to be saturated\r
-  \param [in]    sat  Bit position to saturate to (0..31)\r
-  \return             Saturated value\r
- */\r
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
-{\r
-  if (sat <= 31U)\r
-  {\r
-    const uint32_t max = ((1U << sat) - 1U);\r
-    if (val > (int32_t)max)\r
-    {\r
-      return max;\r
-    }\r
-    else if (val < 0)\r
-    {\r
-      return 0U;\r
-    }\r
-  }\r
-  return (uint32_t)val;\r
-}\r
-\r
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
-\r
-\r
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-/**\r
-  \brief   Load-Acquire (8 bit)\r
-  \details Executes a LDAB instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-   return ((uint8_t) result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire (16 bit)\r
-  \details Executes a LDAH instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-   return ((uint16_t) result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire (32 bit)\r
-  \details Executes a LDA instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release (8 bit)\r
-  \details Executes a STLB instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
-{\r
-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release (16 bit)\r
-  \details Executes a STLH instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
-{\r
-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release (32 bit)\r
-  \details Executes a STL instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
- */\r
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
-{\r
-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire Exclusive (8 bit)\r
-  \details Executes a LDAB exclusive instruction for 8 bit value.\r
-  \param [in]    ptr  Pointer to data\r
-  \return             value of type uint8_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-   return ((uint8_t) result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire Exclusive (16 bit)\r
-  \details Executes a LDAH exclusive instruction for 16 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint16_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-   return ((uint16_t) result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Load-Acquire Exclusive (32 bit)\r
-  \details Executes a LDA exclusive instruction for 32 bit values.\r
-  \param [in]    ptr  Pointer to data\r
-  \return        value of type uint32_t at (*ptr)\r
- */\r
-__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\r
-{\r
-    uint32_t result;\r
-\r
-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release Exclusive (8 bit)\r
-  \details Executes a STLB exclusive instruction for 8 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
-{\r
-   uint32_t result;\r
-\r
-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release Exclusive (16 bit)\r
-  \details Executes a STLH exclusive instruction for 16 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
-{\r
-   uint32_t result;\r
-\r
-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-   return(result);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Store-Release Exclusive (32 bit)\r
-  \details Executes a STL exclusive instruction for 32 bit values.\r
-  \param [in]  value  Value to store\r
-  \param [in]    ptr  Pointer to location\r
-  \return          0  Function succeeded\r
-  \return          1  Function failed\r
- */\r
-__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
-{\r
-   uint32_t result;\r
-\r
-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-   return(result);\r
-}\r
-\r
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ###################  Compiler specific Intrinsics  ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
-  Access to dedicated SIMD instructions\r
-  @{\r
-*/\r
-\r
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
-\r
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-\r
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-\r
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-#define __SSAT16(ARG1,ARG2) \\r
-({                          \\r
-  int32_t __RES, __ARG1 = (ARG1); \\r
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
-  __RES; \\r
- })\r
-\r
-#define __USAT16(ARG1,ARG2) \\r
-({                          \\r
-  uint32_t __RES, __ARG1 = (ARG1); \\r
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
-  __RES; \\r
- })\r
-\r
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
-  union llreg_u{\r
-    uint32_t w32[2];\r
-    uint64_t w64;\r
-  } llr;\r
-  llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__   /* Little endian */\r
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else               /* Big endian */\r
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
-  return(llr.w64);\r
-}\r
-\r
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r
-{\r
-  uint32_t result;\r
-\r
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r
-{\r
-  int32_t result;\r
-\r
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r
-{\r
-  int32_t result;\r
-\r
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
-  return(result);\r
-}\r
-\r
-#if 0\r
-#define __PKHBT(ARG1,ARG2,ARG3) \\r
-({                          \\r
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
-  __RES; \\r
- })\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) \\r
-({                          \\r
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
-  if (ARG3 == 0) \\r
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \\r
-  else \\r
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
-  __RES; \\r
- })\r
-#endif\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\r
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\r
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r
-\r
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__ARM_FEATURE_DSP == 1) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#pragma GCC diagnostic pop\r
-\r
-#endif /* __CMSIS_GCC_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_iccarm.h
deleted file mode 100644 (file)
index 3c90a2c..0000000
+++ /dev/null
@@ -1,935 +0,0 @@
-/**************************************************************************//**\r
- * @file     cmsis_iccarm.h\r
- * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
- * @version  V5.0.7\r
- * @date     19. June 2018\r
- ******************************************************************************/\r
-\r
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2017-2018 IAR Systems\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License")\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-//     http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-#ifndef __CMSIS_ICCARM_H__\r
-#define __CMSIS_ICCARM_H__\r
-\r
-#ifndef __ICCARM__\r
-  #error This file should only be compiled by ICCARM\r
-#endif\r
-\r
-#pragma system_include\r
-\r
-#define __IAR_FT _Pragma("inline=forced") __intrinsic\r
-\r
-#if (__VER__ >= 8000000)\r
-  #define __ICCARM_V8 1\r
-#else\r
-  #define __ICCARM_V8 0\r
-#endif\r
-\r
-#ifndef __ALIGNED\r
-  #if __ICCARM_V8\r
-    #define __ALIGNED(x) __attribute__((aligned(x)))\r
-  #elif (__VER__ >= 7080000)\r
-    /* Needs IAR language extensions */\r
-    #define __ALIGNED(x) __attribute__((aligned(x)))\r
-  #else\r
-    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\r
-    #define __ALIGNED(x)\r
-  #endif\r
-#endif\r
-\r
-\r
-/* Define compiler macros for CPU architecture, used in CMSIS 5.\r
- */\r
-#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\r
-/* Macros already defined */\r
-#else\r
-  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\r
-    #define __ARM_ARCH_8M_MAIN__ 1\r
-  #elif defined(__ARM8M_BASELINE__)\r
-    #define __ARM_ARCH_8M_BASE__ 1\r
-  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\r
-    #if __ARM_ARCH == 6\r
-      #define __ARM_ARCH_6M__ 1\r
-    #elif __ARM_ARCH == 7\r
-      #if __ARM_FEATURE_DSP\r
-        #define __ARM_ARCH_7EM__ 1\r
-      #else\r
-        #define __ARM_ARCH_7M__ 1\r
-      #endif\r
-    #endif /* __ARM_ARCH */\r
-  #endif /* __ARM_ARCH_PROFILE == 'M' */\r
-#endif\r
-\r
-/* Alternativ core deduction for older ICCARM's */\r
-#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\r
-    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\r
-  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\r
-    #define __ARM_ARCH_6M__ 1\r
-  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\r
-    #define __ARM_ARCH_7M__ 1\r
-  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\r
-    #define __ARM_ARCH_7EM__  1\r
-  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\r
-    #define __ARM_ARCH_8M_BASE__ 1\r
-  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\r
-    #define __ARM_ARCH_8M_MAIN__ 1\r
-  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\r
-    #define __ARM_ARCH_8M_MAIN__ 1\r
-  #else\r
-    #error "Unknown target."\r
-  #endif\r
-#endif\r
-\r
-\r
-\r
-#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\r
-  #define __IAR_M0_FAMILY  1\r
-#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\r
-  #define __IAR_M0_FAMILY  1\r
-#else\r
-  #define __IAR_M0_FAMILY  0\r
-#endif\r
-\r
-\r
-#ifndef __ASM\r
-  #define __ASM __asm\r
-#endif\r
-\r
-#ifndef __INLINE\r
-  #define __INLINE inline\r
-#endif\r
-\r
-#ifndef   __NO_RETURN\r
-  #if __ICCARM_V8\r
-    #define __NO_RETURN __attribute__((__noreturn__))\r
-  #else\r
-    #define __NO_RETURN _Pragma("object_attribute=__noreturn")\r
-  #endif\r
-#endif\r
-\r
-#ifndef   __PACKED\r
-  #if __ICCARM_V8\r
-    #define __PACKED __attribute__((packed, aligned(1)))\r
-  #else\r
-    /* Needs IAR language extensions */\r
-    #define __PACKED __packed\r
-  #endif\r
-#endif\r
-\r
-#ifndef   __PACKED_STRUCT\r
-  #if __ICCARM_V8\r
-    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
-  #else\r
-    /* Needs IAR language extensions */\r
-    #define __PACKED_STRUCT __packed struct\r
-  #endif\r
-#endif\r
-\r
-#ifndef   __PACKED_UNION\r
-  #if __ICCARM_V8\r
-    #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
-  #else\r
-    /* Needs IAR language extensions */\r
-    #define __PACKED_UNION __packed union\r
-  #endif\r
-#endif\r
-\r
-#ifndef   __RESTRICT\r
-  #define __RESTRICT            __restrict\r
-#endif\r
-\r
-#ifndef   __STATIC_INLINE\r
-  #define __STATIC_INLINE       static inline\r
-#endif\r
-\r
-#ifndef   __FORCEINLINE\r
-  #define __FORCEINLINE         _Pragma("inline=forced")\r
-#endif\r
-\r
-#ifndef   __STATIC_FORCEINLINE\r
-  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE\r
-#endif\r
-\r
-#ifndef __UNALIGNED_UINT16_READ\r
-#pragma language=save\r
-#pragma language=extended\r
-__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\r
-{\r
-  return *(__packed uint16_t*)(ptr);\r
-}\r
-#pragma language=restore\r
-#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\r
-#endif\r
-\r
-\r
-#ifndef __UNALIGNED_UINT16_WRITE\r
-#pragma language=save\r
-#pragma language=extended\r
-__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\r
-{\r
-  *(__packed uint16_t*)(ptr) = val;;\r
-}\r
-#pragma language=restore\r
-#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\r
-#endif\r
-\r
-#ifndef __UNALIGNED_UINT32_READ\r
-#pragma language=save\r
-#pragma language=extended\r
-__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\r
-{\r
-  return *(__packed uint32_t*)(ptr);\r
-}\r
-#pragma language=restore\r
-#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\r
-#endif\r
-\r
-#ifndef __UNALIGNED_UINT32_WRITE\r
-#pragma language=save\r
-#pragma language=extended\r
-__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\r
-{\r
-  *(__packed uint32_t*)(ptr) = val;;\r
-}\r
-#pragma language=restore\r
-#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\r
-#endif\r
-\r
-#ifndef __UNALIGNED_UINT32   /* deprecated */\r
-#pragma language=save\r
-#pragma language=extended\r
-__packed struct  __iar_u32 { uint32_t v; };\r
-#pragma language=restore\r
-#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\r
-#endif\r
-\r
-#ifndef   __USED\r
-  #if __ICCARM_V8\r
-    #define __USED __attribute__((used))\r
-  #else\r
-    #define __USED _Pragma("__root")\r
-  #endif\r
-#endif\r
-\r
-#ifndef   __WEAK\r
-  #if __ICCARM_V8\r
-    #define __WEAK __attribute__((weak))\r
-  #else\r
-    #define __WEAK _Pragma("__weak")\r
-  #endif\r
-#endif\r
-\r
-\r
-#ifndef __ICCARM_INTRINSICS_VERSION__\r
-  #define __ICCARM_INTRINSICS_VERSION__  0\r
-#endif\r
-\r
-#if __ICCARM_INTRINSICS_VERSION__ == 2\r
-\r
-  #if defined(__CLZ)\r
-    #undef __CLZ\r
-  #endif\r
-  #if defined(__REVSH)\r
-    #undef __REVSH\r
-  #endif\r
-  #if defined(__RBIT)\r
-    #undef __RBIT\r
-  #endif\r
-  #if defined(__SSAT)\r
-    #undef __SSAT\r
-  #endif\r
-  #if defined(__USAT)\r
-    #undef __USAT\r
-  #endif\r
-\r
-  #include "iccarm_builtin.h"\r
-\r
-  #define __disable_fault_irq __iar_builtin_disable_fiq\r
-  #define __disable_irq       __iar_builtin_disable_interrupt\r
-  #define __enable_fault_irq  __iar_builtin_enable_fiq\r
-  #define __enable_irq        __iar_builtin_enable_interrupt\r
-  #define __arm_rsr           __iar_builtin_rsr\r
-  #define __arm_wsr           __iar_builtin_wsr\r
-\r
-\r
-  #define __get_APSR()                (__arm_rsr("APSR"))\r
-  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))\r
-  #define __get_CONTROL()             (__arm_rsr("CONTROL"))\r
-  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))\r
-\r
-  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-    #define __get_FPSCR()             (__arm_rsr("FPSCR"))\r
-    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))\r
-  #else\r
-    #define __get_FPSCR()             ( 0 )\r
-    #define __set_FPSCR(VALUE)        ((void)VALUE)\r
-  #endif\r
-\r
-  #define __get_IPSR()                (__arm_rsr("IPSR"))\r
-  #define __get_MSP()                 (__arm_rsr("MSP"))\r
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-    // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-    #define __get_MSPLIM()            (0U)\r
-  #else\r
-    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))\r
-  #endif\r
-  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))\r
-  #define __get_PSP()                 (__arm_rsr("PSP"))\r
-\r
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-    #define __get_PSPLIM()            (0U)\r
-  #else\r
-    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))\r
-  #endif\r
-\r
-  #define __get_xPSR()                (__arm_rsr("xPSR"))\r
-\r
-  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))\r
-  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))\r
-  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))\r
-  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))\r
-  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))\r
-\r
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-    // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-    #define __set_MSPLIM(VALUE)       ((void)(VALUE))\r
-  #else\r
-    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))\r
-  #endif\r
-  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))\r
-  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))\r
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-    #define __set_PSPLIM(VALUE)       ((void)(VALUE))\r
-  #else\r
-    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))\r
-  #endif\r
-\r
-  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))\r
-  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))\r
-  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))\r
-  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))\r
-  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))\r
-  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))\r
-  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))\r
-  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))\r
-  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))\r
-  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))\r
-  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))\r
-  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))\r
-  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))\r
-  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
-\r
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
-    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-    #define __TZ_get_PSPLIM_NS()      (0U)\r
-    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\r
-  #else\r
-    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))\r
-    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
-  #endif\r
-\r
-  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))\r
-  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))\r
-\r
-  #define __NOP     __iar_builtin_no_operation\r
-\r
-  #define __CLZ     __iar_builtin_CLZ\r
-  #define __CLREX   __iar_builtin_CLREX\r
-\r
-  #define __DMB     __iar_builtin_DMB\r
-  #define __DSB     __iar_builtin_DSB\r
-  #define __ISB     __iar_builtin_ISB\r
-\r
-  #define __LDREXB  __iar_builtin_LDREXB\r
-  #define __LDREXH  __iar_builtin_LDREXH\r
-  #define __LDREXW  __iar_builtin_LDREX\r
-\r
-  #define __RBIT    __iar_builtin_RBIT\r
-  #define __REV     __iar_builtin_REV\r
-  #define __REV16   __iar_builtin_REV16\r
-\r
-  __IAR_FT int16_t __REVSH(int16_t val)\r
-  {\r
-    return (int16_t) __iar_builtin_REVSH(val);\r
-  }\r
-\r
-  #define __ROR     __iar_builtin_ROR\r
-  #define __RRX     __iar_builtin_RRX\r
-\r
-  #define __SEV     __iar_builtin_SEV\r
-\r
-  #if !__IAR_M0_FAMILY\r
-    #define __SSAT    __iar_builtin_SSAT\r
-  #endif\r
-\r
-  #define __STREXB  __iar_builtin_STREXB\r
-  #define __STREXH  __iar_builtin_STREXH\r
-  #define __STREXW  __iar_builtin_STREX\r
-\r
-  #if !__IAR_M0_FAMILY\r
-    #define __USAT    __iar_builtin_USAT\r
-  #endif\r
-\r
-  #define __WFE     __iar_builtin_WFE\r
-  #define __WFI     __iar_builtin_WFI\r
-\r
-  #if __ARM_MEDIA__\r
-    #define __SADD8   __iar_builtin_SADD8\r
-    #define __QADD8   __iar_builtin_QADD8\r
-    #define __SHADD8  __iar_builtin_SHADD8\r
-    #define __UADD8   __iar_builtin_UADD8\r
-    #define __UQADD8  __iar_builtin_UQADD8\r
-    #define __UHADD8  __iar_builtin_UHADD8\r
-    #define __SSUB8   __iar_builtin_SSUB8\r
-    #define __QSUB8   __iar_builtin_QSUB8\r
-    #define __SHSUB8  __iar_builtin_SHSUB8\r
-    #define __USUB8   __iar_builtin_USUB8\r
-    #define __UQSUB8  __iar_builtin_UQSUB8\r
-    #define __UHSUB8  __iar_builtin_UHSUB8\r
-    #define __SADD16  __iar_builtin_SADD16\r
-    #define __QADD16  __iar_builtin_QADD16\r
-    #define __SHADD16 __iar_builtin_SHADD16\r
-    #define __UADD16  __iar_builtin_UADD16\r
-    #define __UQADD16 __iar_builtin_UQADD16\r
-    #define __UHADD16 __iar_builtin_UHADD16\r
-    #define __SSUB16  __iar_builtin_SSUB16\r
-    #define __QSUB16  __iar_builtin_QSUB16\r
-    #define __SHSUB16 __iar_builtin_SHSUB16\r
-    #define __USUB16  __iar_builtin_USUB16\r
-    #define __UQSUB16 __iar_builtin_UQSUB16\r
-    #define __UHSUB16 __iar_builtin_UHSUB16\r
-    #define __SASX    __iar_builtin_SASX\r
-    #define __QASX    __iar_builtin_QASX\r
-    #define __SHASX   __iar_builtin_SHASX\r
-    #define __UASX    __iar_builtin_UASX\r
-    #define __UQASX   __iar_builtin_UQASX\r
-    #define __UHASX   __iar_builtin_UHASX\r
-    #define __SSAX    __iar_builtin_SSAX\r
-    #define __QSAX    __iar_builtin_QSAX\r
-    #define __SHSAX   __iar_builtin_SHSAX\r
-    #define __USAX    __iar_builtin_USAX\r
-    #define __UQSAX   __iar_builtin_UQSAX\r
-    #define __UHSAX   __iar_builtin_UHSAX\r
-    #define __USAD8   __iar_builtin_USAD8\r
-    #define __USADA8  __iar_builtin_USADA8\r
-    #define __SSAT16  __iar_builtin_SSAT16\r
-    #define __USAT16  __iar_builtin_USAT16\r
-    #define __UXTB16  __iar_builtin_UXTB16\r
-    #define __UXTAB16 __iar_builtin_UXTAB16\r
-    #define __SXTB16  __iar_builtin_SXTB16\r
-    #define __SXTAB16 __iar_builtin_SXTAB16\r
-    #define __SMUAD   __iar_builtin_SMUAD\r
-    #define __SMUADX  __iar_builtin_SMUADX\r
-    #define __SMMLA   __iar_builtin_SMMLA\r
-    #define __SMLAD   __iar_builtin_SMLAD\r
-    #define __SMLADX  __iar_builtin_SMLADX\r
-    #define __SMLALD  __iar_builtin_SMLALD\r
-    #define __SMLALDX __iar_builtin_SMLALDX\r
-    #define __SMUSD   __iar_builtin_SMUSD\r
-    #define __SMUSDX  __iar_builtin_SMUSDX\r
-    #define __SMLSD   __iar_builtin_SMLSD\r
-    #define __SMLSDX  __iar_builtin_SMLSDX\r
-    #define __SMLSLD  __iar_builtin_SMLSLD\r
-    #define __SMLSLDX __iar_builtin_SMLSLDX\r
-    #define __SEL     __iar_builtin_SEL\r
-    #define __QADD    __iar_builtin_QADD\r
-    #define __QSUB    __iar_builtin_QSUB\r
-    #define __PKHBT   __iar_builtin_PKHBT\r
-    #define __PKHTB   __iar_builtin_PKHTB\r
-  #endif\r
-\r
-#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
-\r
-  #if __IAR_M0_FAMILY\r
-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
-    #define __CLZ  __cmsis_iar_clz_not_active\r
-    #define __SSAT __cmsis_iar_ssat_not_active\r
-    #define __USAT __cmsis_iar_usat_not_active\r
-    #define __RBIT __cmsis_iar_rbit_not_active\r
-    #define __get_APSR  __cmsis_iar_get_APSR_not_active\r
-  #endif\r
-\r
-\r
-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\r
-    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\r
-    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\r
-  #endif\r
-\r
-  #ifdef __INTRINSICS_INCLUDED\r
-  #error intrinsics.h is already included previously!\r
-  #endif\r
-\r
-  #include <intrinsics.h>\r
-\r
-  #if __IAR_M0_FAMILY\r
-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
-    #undef __CLZ\r
-    #undef __SSAT\r
-    #undef __USAT\r
-    #undef __RBIT\r
-    #undef __get_APSR\r
-\r
-    __STATIC_INLINE uint8_t __CLZ(uint32_t data)\r
-    {\r
-      if (data == 0U) { return 32U; }\r
-\r
-      uint32_t count = 0U;\r
-      uint32_t mask = 0x80000000U;\r
-\r
-      while ((data & mask) == 0U)\r
-      {\r
-        count += 1U;\r
-        mask = mask >> 1U;\r
-      }\r
-      return count;\r
-    }\r
-\r
-    __STATIC_INLINE uint32_t __RBIT(uint32_t v)\r
-    {\r
-      uint8_t sc = 31U;\r
-      uint32_t r = v;\r
-      for (v >>= 1U; v; v >>= 1U)\r
-      {\r
-        r <<= 1U;\r
-        r |= v & 1U;\r
-        sc--;\r
-      }\r
-      return (r << sc);\r
-    }\r
-\r
-    __STATIC_INLINE  uint32_t __get_APSR(void)\r
-    {\r
-      uint32_t res;\r
-      __asm("MRS      %0,APSR" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-  #endif\r
-\r
-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\r
-    #undef __get_FPSCR\r
-    #undef __set_FPSCR\r
-    #define __get_FPSCR()       (0)\r
-    #define __set_FPSCR(VALUE)  ((void)VALUE)\r
-  #endif\r
-\r
-  #pragma diag_suppress=Pe940\r
-  #pragma diag_suppress=Pe177\r
-\r
-  #define __enable_irq    __enable_interrupt\r
-  #define __disable_irq   __disable_interrupt\r
-  #define __NOP           __no_operation\r
-\r
-  #define __get_xPSR      __get_PSR\r
-\r
-  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\r
-\r
-    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\r
-    {\r
-      return __LDREX((unsigned long *)ptr);\r
-    }\r
-\r
-    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\r
-    {\r
-      return __STREX(value, (unsigned long *)ptr);\r
-    }\r
-  #endif\r
-\r
-\r
-  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
-  #if (__CORTEX_M >= 0x03)\r
-\r
-    __IAR_FT uint32_t __RRX(uint32_t value)\r
-    {\r
-      uint32_t result;\r
-      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");\r
-      return(result);\r
-    }\r
-\r
-    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));\r
-    }\r
-\r
-\r
-    #define __enable_fault_irq  __enable_fiq\r
-    #define __disable_fault_irq __disable_fiq\r
-\r
-\r
-  #endif /* (__CORTEX_M >= 0x03) */\r
-\r
-  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-  {\r
-    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\r
-  }\r
-\r
-  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-\r
-   __IAR_FT uint32_t __get_MSPLIM(void)\r
-    {\r
-      uint32_t res;\r
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
-      // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-      res = 0U;\r
-    #else\r
-      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));\r
-    #endif\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __set_MSPLIM(uint32_t value)\r
-    {\r
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
-      // without main extensions, the non-secure MSPLIM is RAZ/WI\r
-      (void)value;\r
-    #else\r
-      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));\r
-    #endif\r
-    }\r
-\r
-    __IAR_FT uint32_t __get_PSPLIM(void)\r
-    {\r
-      uint32_t res;\r
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
-      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-      res = 0U;\r
-    #else\r
-      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));\r
-    #endif\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __set_PSPLIM(uint32_t value)\r
-    {\r
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
-      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-      (void)value;\r
-    #else\r
-      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));\r
-    #endif\r
-    }\r
-\r
-    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_SP_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,SP_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      SP_NS,%0" :: "r" (value));\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)\r
-    {\r
-      uint32_t res;\r
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
-      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-      res = 0U;\r
-    #else\r
-      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));\r
-    #endif\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)\r
-    {\r
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
-      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
-      (void)value;\r
-    #else\r
-      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));\r
-    #endif\r
-    }\r
-\r
-    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)\r
-    {\r
-      uint32_t res;\r
-      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));\r
-      return res;\r
-    }\r
-\r
-    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)\r
-    {\r
-      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));\r
-    }\r
-\r
-  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
-\r
-#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
-\r
-#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))\r
-\r
-#if __IAR_M0_FAMILY\r
-  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
-  {\r
-    if ((sat >= 1U) && (sat <= 32U))\r
-    {\r
-      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
-      const int32_t min = -1 - max ;\r
-      if (val > max)\r
-      {\r
-        return max;\r
-      }\r
-      else if (val < min)\r
-      {\r
-        return min;\r
-      }\r
-    }\r
-    return val;\r
-  }\r
-\r
-  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
-  {\r
-    if (sat <= 31U)\r
-    {\r
-      const uint32_t max = ((1U << sat) - 1U);\r
-      if (val > (int32_t)max)\r
-      {\r
-        return max;\r
-      }\r
-      else if (val < 0)\r
-      {\r
-        return 0U;\r
-      }\r
-    }\r
-    return (uint32_t)val;\r
-  }\r
-#endif\r
-\r
-#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
-\r
-  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\r
-  {\r
-    uint32_t res;\r
-    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
-    return ((uint8_t)res);\r
-  }\r
-\r
-  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\r
-  {\r
-    uint32_t res;\r
-    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
-    return ((uint16_t)res);\r
-  }\r
-\r
-  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\r
-  {\r
-    uint32_t res;\r
-    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
-    return res;\r
-  }\r
-\r
-  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\r
-  {\r
-    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
-  }\r
-\r
-  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\r
-  {\r
-    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
-  }\r
-\r
-  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\r
-  {\r
-    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");\r
-  }\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\r
-\r
-\r
-  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
-    return ((uint8_t)res);\r
-  }\r
-\r
-  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
-    return ((uint16_t)res);\r
-  }\r
-\r
-  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
-    return res;\r
-  }\r
-\r
-  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
-  {\r
-    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
-  }\r
-\r
-  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
-  {\r
-    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
-  }\r
-\r
-  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
-  {\r
-    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
-  }\r
-\r
-  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
-    return ((uint8_t)res);\r
-  }\r
-\r
-  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
-    return ((uint16_t)res);\r
-  }\r
-\r
-  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
-    return res;\r
-  }\r
-\r
-  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
-    return res;\r
-  }\r
-\r
-  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
-    return res;\r
-  }\r
-\r
-  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
-  {\r
-    uint32_t res;\r
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
-    return res;\r
-  }\r
-\r
-#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
-\r
-#undef __IAR_FT\r
-#undef __IAR_M0_FAMILY\r
-#undef __ICCARM_V8\r
-\r
-#pragma diag_default=Pe940\r
-#pragma diag_default=Pe177\r
-\r
-#endif /* __CMSIS_ICCARM_H__ */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_version.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/cmsis_version.h
deleted file mode 100644 (file)
index ae3f2e3..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
-/**************************************************************************//**\r
- * @file     cmsis_version.h\r
- * @brief    CMSIS Core(M) Version definitions\r
- * @version  V5.0.2\r
- * @date     19. April 2017\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CMSIS_VERSION_H\r
-#define __CMSIS_VERSION_H\r
-\r
-/*  CMSIS Version definitions */\r
-#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\r
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\r
-#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\r
-                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\r
-#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_armv8mbl.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_armv8mbl.h
deleted file mode 100644 (file)
index ec76ab2..0000000
+++ /dev/null
@@ -1,1918 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_armv8mbl.h\r
- * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\r
- * @version  V5.0.7\r
- * @date     22. June 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_ARMV8MBL_H_GENERIC\r
-#define __CORE_ARMV8MBL_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_ARMv8MBL\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/*  CMSIS definitions */\r
-#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\r
-                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_ARMV8MBL_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT\r
-#define __CORE_ARMV8MBL_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __ARMv8MBL_REV\r
-    #define __ARMv8MBL_REV               0x0000U\r
-    #warning "__ARMv8MBL_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __FPU_PRESENT\r
-    #define __FPU_PRESENT             0U\r
-    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __SAUREGION_PRESENT\r
-    #define __SAUREGION_PRESENT       0U\r
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __VTOR_PRESENT\r
-    #define __VTOR_PRESENT            0U\r
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          2U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __ETM_PRESENT\r
-    #define __ETM_PRESENT             0U\r
-    #warning "__ETM_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MTB_PRESENT\r
-    #define __MTB_PRESENT             0U\r
-    #warning "__MTB_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group ARMv8MBL */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
-  - Core SAU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[16U];\r
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[16U];\r
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[16U];\r
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[16U];\r
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[16U];\r
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
-        uint32_t RESERVED5[16U];\r
-  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
-}  NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-#else\r
-        uint32_t RESERVED0;\r
-#endif\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-        uint32_t RESERVED1;\r
-  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
-\r
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
-\r
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
-\r
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
-\r
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
-\r
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
-\r
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
-\r
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-        uint32_t RESERVED0[6U];\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-        uint32_t RESERVED3[1U];\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-        uint32_t RESERVED5[1U];\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED6[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-        uint32_t RESERVED7[1U];\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-        uint32_t RESERVED8[1U];\r
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
-        uint32_t RESERVED9[1U];\r
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
-        uint32_t RESERVED10[1U];\r
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
-        uint32_t RESERVED11[1U];\r
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
-        uint32_t RESERVED12[1U];\r
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
-        uint32_t RESERVED13[1U];\r
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
-        uint32_t RESERVED14[1U];\r
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
-        uint32_t RESERVED15[1U];\r
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
-        uint32_t RESERVED16[1U];\r
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
-        uint32_t RESERVED17[1U];\r
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
-        uint32_t RESERVED18[1U];\r
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
-        uint32_t RESERVED19[1U];\r
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
-        uint32_t RESERVED20[1U];\r
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
-        uint32_t RESERVED21[1U];\r
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
-        uint32_t RESERVED22[1U];\r
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
-        uint32_t RESERVED23[1U];\r
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
-        uint32_t RESERVED24[1U];\r
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
-        uint32_t RESERVED25[1U];\r
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
-        uint32_t RESERVED26[1U];\r
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
-        uint32_t RESERVED27[1U];\r
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
-        uint32_t RESERVED28[1U];\r
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
-        uint32_t RESERVED29[1U];\r
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
-        uint32_t RESERVED30[1U];\r
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
-        uint32_t RESERVED31[1U];\r
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
-\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
-\r
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
-        uint32_t RESERVED3[809U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\r
-        uint32_t RESERVED4[4U];\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\r
-#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI Periodic Synchronization Control Register Definitions */\r
-#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\r
-#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\r
-\r
-/* TPI Software Lock Status Register Definitions */\r
-#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\r
-#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\r
-\r
-#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\r
-#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\r
-\r
-#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\r
-#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\r
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
-        uint32_t RESERVED0[7U];\r
-  union {\r
-  __IOM uint32_t MAIR[2];\r
-  struct {\r
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
-  };\r
-  };\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  1U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
-\r
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
-\r
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
-\r
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
-\r
-/* MPU Region Limit Address Register Definitions */\r
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
-\r
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
-\r
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\r
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 0 Definitions */\r
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
-\r
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
-\r
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
-\r
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 1 Definitions */\r
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
-\r
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
-\r
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
-\r
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
-  \brief    Type definitions for the Security Attribution Unit (SAU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Security Attribution Unit (SAU).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
-#endif\r
-} SAU_Type;\r
-\r
-/* SAU Control Register Definitions */\r
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
-\r
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
-\r
-/* SAU Type Register Definitions */\r
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
-\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-/* SAU Region Number Register Definitions */\r
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
-\r
-/* SAU Region Base Address Register Definitions */\r
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
-\r
-/* SAU Region Limit Address Register Definitions */\r
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
-\r
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
-\r
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
-\r
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
-\r
-/*@} end of group CMSIS_SAU */\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\r
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/* Debug Authentication Control Register Definitions */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
-\r
-/* Debug Security Control and Status Register Definitions */\r
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
-\r
-\r
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
-  #endif\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
-\r
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
-  #endif\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
-\r
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\r
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
-\r
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
-\r
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
-#else\r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
-#endif\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
-\r
-#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
-#define __NVIC_GetPriorityGrouping()  (0U)\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Get Interrupt Target State\r
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-  \return             1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Target State\r
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Interrupt Target State\r
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-           If VTOR is not present address 0 must be mapped to SRAM.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                 SCB_AIRCR_SYSRESETREQ_Msk);\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Enable Interrupt (non-secure)\r
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status (non-secure)\r
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt (non-secure)\r
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt (non-secure)\r
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt (non-secure)\r
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt (non-secure)\r
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt (non-secure)\r
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority (non-secure)\r
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every non-secure processor exception.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority (non-secure)\r
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv8.h"\r
-\r
-#endif\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##########################   SAU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
-  \brief    Functions that configure the SAU.\r
-  @{\r
- */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-\r
-/**\r
-  \brief   Enable SAU\r
-  \details Enables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Enable(void)\r
-{\r
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-\r
-\r
-/**\r
-  \brief   Disable SAU\r
-  \details Disables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Disable(void)\r
-{\r
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_SAUFunctions */\r
-\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   System Tick Configuration (non-secure)\r
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                         /* Reload value impossible */\r
-  }\r
-\r
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                      SysTick_CTRL_TICKINT_Msk   |\r
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                           /* Function successful */\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_armv8mml.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_armv8mml.h
deleted file mode 100644 (file)
index 2d0f106..0000000
+++ /dev/null
@@ -1,2927 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_armv8mml.h\r
- * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\r
- * @version  V5.0.7\r
- * @date     06. July 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_ARMV8MML_H_GENERIC\r
-#define __CORE_ARMV8MML_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_ARMv8MML\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/*  CMSIS Armv8MML definitions */\r
-#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\r
-                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined(__ARM_FEATURE_DSP)\r
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined(__ARM_FEATURE_DSP)\r
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined(__ARM_FEATURE_DSP)\r
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined(__ARM_FEATURE_DSP)\r
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_ARMV8MML_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_ARMV8MML_H_DEPENDANT\r
-#define __CORE_ARMV8MML_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __ARMv8MML_REV\r
-    #define __ARMv8MML_REV               0x0000U\r
-    #warning "__ARMv8MML_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __FPU_PRESENT\r
-    #define __FPU_PRESENT             0U\r
-    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __SAUREGION_PRESENT\r
-    #define __SAUREGION_PRESENT       0U\r
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __DSP_PRESENT\r
-    #define __DSP_PRESENT             0U\r
-    #warning "__DSP_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          3U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group ARMv8MML */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
-  - Core SAU Register\r
-  - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\r
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\r
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\r
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\r
-\r
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[16U];\r
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[16U];\r
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[16U];\r
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[16U];\r
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[16U];\r
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
-        uint32_t RESERVED5[16U];\r
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
-        uint32_t RESERVED6[580U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
-}  NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\r
-        uint32_t RESERVED3[92U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r
-        uint32_t RESERVED4[15U];\r
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\r
-        uint32_t RESERVED5[1U];\r
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r
-        uint32_t RESERVED6[1U];\r
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r
-        uint32_t RESERVED7[6U];\r
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r
-        uint32_t RESERVED8[1U];\r
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
-\r
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
-\r
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
-\r
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
-\r
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
-\r
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
-\r
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\r
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\r
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\r
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
-\r
-/* SCB Non-Secure Access Control Register Definitions */\r
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\r
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\r
-\r
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\r
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\r
-\r
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\r
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\r
-\r
-/* SCB Cache Level ID Register Definitions */\r
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r
-\r
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r
-\r
-/* SCB Cache Type Register Definitions */\r
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r
-\r
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r
-\r
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r
-\r
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r
-\r
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r
-\r
-/* SCB Cache Size ID Register Definitions */\r
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r
-\r
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r
-\r
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r
-\r
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r
-\r
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r
-\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r
-\r
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r
-\r
-/* SCB Cache Size Selection Register Definitions */\r
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r
-\r
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r
-\r
-/* SCB Software Triggered Interrupt Register Definitions */\r
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r
-\r
-/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r
-\r
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r
-\r
-/* SCB D-Cache Clean by Set-way Register Definitions */\r
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r
-\r
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r
-\r
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r
-\r
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r
-\r
-/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r
-\r
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r
-\r
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r
-\r
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r
-\r
-/* Data Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r
-\r
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r
-\r
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r
-\r
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r
-\r
-/* AHBP Control Register Definitions */\r
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r
-\r
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r
-\r
-/* L1 Cache Control Register Definitions */\r
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r
-\r
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r
-\r
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r
-\r
-/* AHBS Control Register Definitions */\r
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r
-\r
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r
-\r
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r
-\r
-/* Auxiliary Bus Fault Status Register Definitions */\r
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r
-\r
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r
-\r
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r
-\r
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r
-\r
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r
-\r
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
-  __OM  union\r
-  {\r
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
-        uint32_t RESERVED0[864U];\r
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
-        uint32_t RESERVED1[15U];\r
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
-        uint32_t RESERVED2[15U];\r
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
-        uint32_t RESERVED3[29U];\r
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
-        uint32_t RESERVED4[43U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
-        uint32_t RESERVED5[1U];\r
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\r
-        uint32_t RESERVED6[4U];\r
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Stimulus Port Register Definitions */\r
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\r
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\r
-\r
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\r
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\r
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\r
-\r
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\r
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-        uint32_t RESERVED3[1U];\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-        uint32_t RESERVED5[1U];\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED6[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-        uint32_t RESERVED7[1U];\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-        uint32_t RESERVED8[1U];\r
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
-        uint32_t RESERVED9[1U];\r
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
-        uint32_t RESERVED10[1U];\r
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
-        uint32_t RESERVED11[1U];\r
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
-        uint32_t RESERVED12[1U];\r
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
-        uint32_t RESERVED13[1U];\r
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
-        uint32_t RESERVED14[1U];\r
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
-        uint32_t RESERVED15[1U];\r
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
-        uint32_t RESERVED16[1U];\r
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
-        uint32_t RESERVED17[1U];\r
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
-        uint32_t RESERVED18[1U];\r
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
-        uint32_t RESERVED19[1U];\r
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
-        uint32_t RESERVED20[1U];\r
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
-        uint32_t RESERVED21[1U];\r
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
-        uint32_t RESERVED22[1U];\r
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
-        uint32_t RESERVED23[1U];\r
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
-        uint32_t RESERVED24[1U];\r
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
-        uint32_t RESERVED25[1U];\r
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
-        uint32_t RESERVED26[1U];\r
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
-        uint32_t RESERVED27[1U];\r
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
-        uint32_t RESERVED28[1U];\r
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
-        uint32_t RESERVED29[1U];\r
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
-        uint32_t RESERVED30[1U];\r
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
-        uint32_t RESERVED31[1U];\r
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
-        uint32_t RESERVED32[934U];\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r
-        uint32_t RESERVED33[1U];\r
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\r
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
-\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
-\r
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
-        uint32_t RESERVED3[809U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\r
-        uint32_t RESERVED4[4U];\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\r
-#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI Periodic Synchronization Control Register Definitions */\r
-#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\r
-#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\r
-\r
-/* TPI Software Lock Status Register Definitions */\r
-#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\r
-#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\r
-\r
-#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\r
-#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\r
-\r
-#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\r
-#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\r
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\r
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\r
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\r
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\r
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\r
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\r
-        uint32_t RESERVED0[1];\r
-  union {\r
-  __IOM uint32_t MAIR[2];\r
-  struct {\r
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
-  };\r
-  };\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  4U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
-\r
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
-\r
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
-\r
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
-\r
-/* MPU Region Limit Address Register Definitions */\r
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
-\r
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
-\r
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\r
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 0 Definitions */\r
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
-\r
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
-\r
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
-\r
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 1 Definitions */\r
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
-\r
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
-\r
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
-\r
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
-  \brief    Type definitions for the Security Attribution Unit (SAU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Security Attribution Unit (SAU).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
-#else\r
-        uint32_t RESERVED0[3];\r
-#endif\r
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\r
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\r
-} SAU_Type;\r
-\r
-/* SAU Control Register Definitions */\r
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
-\r
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
-\r
-/* SAU Type Register Definitions */\r
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
-\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-/* SAU Region Number Register Definitions */\r
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
-\r
-/* SAU Region Base Address Register Definitions */\r
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
-\r
-/* SAU Region Limit Address Register Definitions */\r
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
-\r
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
-\r
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
-\r
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
-\r
-/* Secure Fault Status Register Definitions */\r
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\r
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\r
-\r
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\r
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\r
-\r
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\r
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\r
-\r
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\r
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\r
-\r
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\r
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\r
-\r
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\r
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\r
-\r
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\r
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\r
-\r
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\r
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\r
-\r
-/*@} end of group CMSIS_SAU */\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
-  \brief    Type definitions for the Floating Point Unit (FPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\r
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\r
-\r
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\r
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\r
-\r
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\r
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\r
-\r
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\r
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\r
-\r
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\r
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\r
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\r
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\r
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/* Debug Authentication Control Register Definitions */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
-\r
-/* Debug Security Control and Status Register Definitions */\r
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\r
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
-\r
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\r
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\r
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
-  #endif\r
-\r
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\r
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
-\r
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\r
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
-  #endif\r
-\r
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\r
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Debug Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
-\r
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\r
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
-\r
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
-\r
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
-#else\r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Priority Grouping\r
-  \details Sets the priority grouping field using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r
-  SCB->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping\r
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Get Interrupt Target State\r
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-  \return             1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Target State\r
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Interrupt Target State\r
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Set Priority Grouping (non-secure)\r
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r
-  SCB_NS->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping (non-secure)\r
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
-{\r
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt (non-secure)\r
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status (non-secure)\r
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt (non-secure)\r
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt (non-secure)\r
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt (non-secure)\r
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt (non-secure)\r
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt (non-secure)\r
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority (non-secure)\r
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every non-secure processor exception.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority (non-secure)\r
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv8.h"\r
-\r
-#endif\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-  uint32_t mvfr0;\r
-\r
-  mvfr0 = FPU->MVFR0;\r
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
-  {\r
-    return 2U;           /* Double + Single precision FPU */\r
-  }\r
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
-  {\r
-    return 1U;           /* Single precision FPU */\r
-  }\r
-  else\r
-  {\r
-    return 0U;           /* No FPU */\r
-  }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##########################   SAU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
-  \brief    Functions that configure the SAU.\r
-  @{\r
- */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-\r
-/**\r
-  \brief   Enable SAU\r
-  \details Enables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Enable(void)\r
-{\r
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-\r
-\r
-/**\r
-  \brief   Disable SAU\r
-  \details Disables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Disable(void)\r
-{\r
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_SAUFunctions */\r
-\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   System Tick Configuration (non-secure)\r
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                         /* Reload value impossible */\r
-  }\r
-\r
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                      SysTick_CTRL_TICKINT_Msk   |\r
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                           /* Function successful */\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
-  \brief    Functions that access the ITM debug interface.\r
-  @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
-  \brief   ITM Send Character\r
-  \details Transmits a character via the ITM channel 0, and\r
-           \li Just returns when no debugger is connected that has booked the output.\r
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-  \param [in]     ch  Character to transmit.\r
-  \returns            Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
-  {\r
-    while (ITM->PORT[0U].u32 == 0UL)\r
-    {\r
-      __NOP();\r
-    }\r
-    ITM->PORT[0U].u8 = (uint8_t)ch;\r
-  }\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Receive Character\r
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
-  \return             Received character.\r
-  \return         -1  No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
-  int32_t ch = -1;                           /* no character available */\r
-\r
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
-  {\r
-    ch = ITM_RxBuffer;\r
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
-  }\r
-\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Check Character\r
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-  \return          0  No character available.\r
-  \return          1  Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
-  {\r
-    return (0);                              /* no character available */\r
-  }\r
-  else\r
-  {\r
-    return (1);                              /*    character available */\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm0.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm0.h
deleted file mode 100644 (file)
index 6f82227..0000000
+++ /dev/null
@@ -1,949 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm0.h\r
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
- * @version  V5.0.5\r
- * @date     28. May 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM0_H_GENERIC\r
-#define __CORE_CM0_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_M0\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
\r
-/*  CMSIS CM0 definitions */\r
-#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\r
-                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0_H_DEPENDANT\r
-#define __CORE_CM0_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM0_REV\r
-    #define __CM0_REV               0x0000U\r
-    #warning "__CM0_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          2U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M0 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[31U];\r
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[31U];\r
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[31U];\r
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[31U];\r
-        uint32_t RESERVED4[64U];\r
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
-}  NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-        uint32_t RESERVED0;\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-        uint32_t RESERVED1;\r
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
-            Therefore they are not covered by the Cortex-M0 header file.\r
-  @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
-\r
-#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
-#define __NVIC_GetPriorityGrouping()  (0U)\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           Address 0 must be mapped to SRAM.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                 SCB_AIRCR_SYSRESETREQ_Msk);\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm0plus.h
deleted file mode 100644 (file)
index b9377e8..0000000
+++ /dev/null
@@ -1,1083 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm0plus.h\r
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
- * @version  V5.0.6\r
- * @date     28. May 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM0PLUS_H_GENERIC\r
-#define __CORE_CM0PLUS_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex-M0+\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
\r
-/*  CMSIS CM0+ definitions */\r
-#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\r
-                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0PLUS_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
-#define __CORE_CM0PLUS_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM0PLUS_REV\r
-    #define __CM0PLUS_REV             0x0000U\r
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __VTOR_PRESENT\r
-    #define __VTOR_PRESENT            0U\r
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          2U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex-M0+ */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[31U];\r
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[31U];\r
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[31U];\r
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[31U];\r
-        uint32_t RESERVED4[64U];\r
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
-}  NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-#else\r
-        uint32_t RESERVED0;\r
-#endif\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-        uint32_t RESERVED1;\r
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  1U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
-            Therefore they are not covered by the Cortex-M0+ header file.\r
-  @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
-\r
-#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
-#define __NVIC_GetPriorityGrouping()  (0U)\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-           If VTOR is not present address 0 must be mapped to SRAM.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
-    uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                 SCB_AIRCR_SYSRESETREQ_Msk);\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm1.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm1.h
deleted file mode 100644 (file)
index fd1c407..0000000
+++ /dev/null
@@ -1,976 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm1.h\r
- * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File\r
- * @version  V1.0.0\r
- * @date     23. July 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM1_H_GENERIC\r
-#define __CORE_CM1_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_M1\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
\r
-/*  CMSIS CM1 definitions */\r
-#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\r
-                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM1_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM1_H_DEPENDANT\r
-#define __CORE_CM1_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM1_REV\r
-    #define __CM1_REV               0x0100U\r
-    #warning "__CM1_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          2U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M1 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[31U];\r
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[31U];\r
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[31U];\r
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[31U];\r
-        uint32_t RESERVED4[64U];\r
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
-}  NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-        uint32_t RESERVED0;\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-        uint32_t RESERVED1;\r
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\r
-#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\r
-\r
-#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\r
-#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
-            Therefore they are not covered by the Cortex-M1 header file.\r
-  @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
-\r
-#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
-#define __NVIC_GetPriorityGrouping()  (0U)\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           Address 0 must be mapped to SRAM.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                 SCB_AIRCR_SYSRESETREQ_Msk);\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM1_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm23.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm23.h
deleted file mode 100644 (file)
index 8202a8d..0000000
+++ /dev/null
@@ -1,1993 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm23.h\r
- * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File\r
- * @version  V5.0.7\r
- * @date     22. June 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM23_H_GENERIC\r
-#define __CORE_CM23_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_M23\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/*  CMSIS definitions */\r
-#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\r
-                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM23_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM23_H_DEPENDANT\r
-#define __CORE_CM23_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM23_REV\r
-    #define __CM23_REV                0x0000U\r
-    #warning "__CM23_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __FPU_PRESENT\r
-    #define __FPU_PRESENT             0U\r
-    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __SAUREGION_PRESENT\r
-    #define __SAUREGION_PRESENT       0U\r
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __VTOR_PRESENT\r
-    #define __VTOR_PRESENT            0U\r
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          2U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __ETM_PRESENT\r
-    #define __ETM_PRESENT             0U\r
-    #warning "__ETM_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MTB_PRESENT\r
-    #define __MTB_PRESENT             0U\r
-    #warning "__MTB_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M23 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
-  - Core SAU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[16U];\r
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[16U];\r
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[16U];\r
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[16U];\r
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[16U];\r
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
-        uint32_t RESERVED5[16U];\r
-  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
-}  NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-#else\r
-        uint32_t RESERVED0;\r
-#endif\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-        uint32_t RESERVED1;\r
-  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
-\r
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
-\r
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
-\r
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
-\r
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
-\r
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
-\r
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
-\r
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-        uint32_t RESERVED0[6U];\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-        uint32_t RESERVED3[1U];\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-        uint32_t RESERVED5[1U];\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED6[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-        uint32_t RESERVED7[1U];\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-        uint32_t RESERVED8[1U];\r
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
-        uint32_t RESERVED9[1U];\r
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
-        uint32_t RESERVED10[1U];\r
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
-        uint32_t RESERVED11[1U];\r
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
-        uint32_t RESERVED12[1U];\r
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
-        uint32_t RESERVED13[1U];\r
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
-        uint32_t RESERVED14[1U];\r
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
-        uint32_t RESERVED15[1U];\r
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
-        uint32_t RESERVED16[1U];\r
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
-        uint32_t RESERVED17[1U];\r
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
-        uint32_t RESERVED18[1U];\r
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
-        uint32_t RESERVED19[1U];\r
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
-        uint32_t RESERVED20[1U];\r
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
-        uint32_t RESERVED21[1U];\r
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
-        uint32_t RESERVED22[1U];\r
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
-        uint32_t RESERVED23[1U];\r
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
-        uint32_t RESERVED24[1U];\r
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
-        uint32_t RESERVED25[1U];\r
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
-        uint32_t RESERVED26[1U];\r
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
-        uint32_t RESERVED27[1U];\r
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
-        uint32_t RESERVED28[1U];\r
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
-        uint32_t RESERVED29[1U];\r
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
-        uint32_t RESERVED30[1U];\r
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
-        uint32_t RESERVED31[1U];\r
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
-\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
-\r
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
-        uint32_t RESERVED3[759U];\r
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
-  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\r
-  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\r
-        uint32_t RESERVED4[1U];\r
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\r
-  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\r
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
-        uint32_t RESERVED5[39U];\r
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
-        uint32_t RESERVED7[8U];\r
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
-\r
-/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
-#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\r
-#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
-\r
-#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\r
-#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\r
-#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\r
-#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
-\r
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
-\r
-/* TPI Integration Test ATB Control Register 0 Definitions */\r
-#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\r
-#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
-\r
-#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\r
-#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\r
-#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\r
-#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\r
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
-        uint32_t RESERVED0[7U];\r
-  union {\r
-  __IOM uint32_t MAIR[2];\r
-  struct {\r
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
-  };\r
-  };\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  1U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
-\r
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
-\r
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
-\r
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
-\r
-/* MPU Region Limit Address Register Definitions */\r
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
-\r
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
-\r
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\r
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 0 Definitions */\r
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
-\r
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
-\r
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
-\r
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 1 Definitions */\r
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
-\r
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
-\r
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
-\r
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
-  \brief    Type definitions for the Security Attribution Unit (SAU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Security Attribution Unit (SAU).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
-#endif\r
-} SAU_Type;\r
-\r
-/* SAU Control Register Definitions */\r
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
-\r
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
-\r
-/* SAU Type Register Definitions */\r
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
-\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-/* SAU Region Number Register Definitions */\r
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
-\r
-/* SAU Region Base Address Register Definitions */\r
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
-\r
-/* SAU Region Limit Address Register Definitions */\r
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
-\r
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
-\r
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
-\r
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
-\r
-/*@} end of group CMSIS_SAU */\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\r
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/* Debug Authentication Control Register Definitions */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
-\r
-/* Debug Security Control and Status Register Definitions */\r
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
-\r
-\r
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
-  #endif\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
-\r
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
-  #endif\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */\r
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
-\r
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \r
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
-\r
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
-\r
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
-#else \r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
-#endif\r
-\r
-       \r
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
-\r
-#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
-#define __NVIC_GetPriorityGrouping()  (0U)\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Get Interrupt Target State\r
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-  \return             1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Target State\r
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Interrupt Target State\r
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-           If VTOR is not present address 0 must be mapped to SRAM.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-#else\r
-  uint32_t *vectors = (uint32_t *)0x0U;\r
-#endif\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                 SCB_AIRCR_SYSRESETREQ_Msk);\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Enable Interrupt (non-secure)\r
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status (non-secure)\r
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt (non-secure)\r
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt (non-secure)\r
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt (non-secure)\r
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt (non-secure)\r
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt (non-secure)\r
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority (non-secure)\r
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every non-secure processor exception.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority (non-secure)\r
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv8.h"\r
-\r
-#endif\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##########################   SAU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
-  \brief    Functions that configure the SAU.\r
-  @{\r
- */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-\r
-/**\r
-  \brief   Enable SAU\r
-  \details Enables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Enable(void)\r
-{\r
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-\r
-\r
-/**\r
-  \brief   Disable SAU\r
-  \details Disables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Disable(void)\r
-{\r
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_SAUFunctions */\r
-\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   System Tick Configuration (non-secure)\r
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                         /* Reload value impossible */\r
-  }\r
-\r
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                      SysTick_CTRL_TICKINT_Msk   |\r
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                           /* Function successful */\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM23_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm3.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm3.h
deleted file mode 100644 (file)
index b0dfbd3..0000000
+++ /dev/null
@@ -1,1941 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm3.h\r
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version  V5.0.8\r
- * @date     04. June 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM3_H_GENERIC\r
-#define __CORE_CM3_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_M3\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/*  CMSIS CM3 definitions */\r
-#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
-                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM3_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM3_H_DEPENDANT\r
-#define __CORE_CM3_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM3_REV\r
-    #define __CM3_REV               0x0200U\r
-    #warning "__CM3_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          3U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M3 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
-    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[24U];\r
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[24U];\r
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[24U];\r
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[24U];\r
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[56U];\r
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
-        uint32_t RESERVED5[644U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
-}  NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
-        uint32_t RESERVED0[5U];\r
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\r
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
-#else\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\r
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
-#else\r
-        uint32_t RESERVED1[1U];\r
-#endif\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
-  __OM  union\r
-  {\r
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
-        uint32_t RESERVED0[864U];\r
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
-        uint32_t RESERVED1[15U];\r
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
-        uint32_t RESERVED2[15U];\r
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
-        uint32_t RESERVED3[29U];\r
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
-        uint32_t RESERVED4[43U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
-        uint32_t RESERVED5[6U];\r
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
-        uint32_t RESERVED3[759U];\r
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
-        uint32_t RESERVED4[1U];\r
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
-        uint32_t RESERVED5[39U];\r
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
-        uint32_t RESERVED7[8U];\r
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  4U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Debug Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-\r
-\r
-/**\r
-  \brief   Set Priority Grouping\r
-  \details Sets the priority grouping field using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */\r
-  SCB->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping\r
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
-  \brief    Functions that access the ITM debug interface.\r
-  @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
-  \brief   ITM Send Character\r
-  \details Transmits a character via the ITM channel 0, and\r
-           \li Just returns when no debugger is connected that has booked the output.\r
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-  \param [in]     ch  Character to transmit.\r
-  \returns            Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
-  {\r
-    while (ITM->PORT[0U].u32 == 0UL)\r
-    {\r
-      __NOP();\r
-    }\r
-    ITM->PORT[0U].u8 = (uint8_t)ch;\r
-  }\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Receive Character\r
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
-  \return             Received character.\r
-  \return         -1  No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
-  int32_t ch = -1;                           /* no character available */\r
-\r
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
-  {\r
-    ch = ITM_RxBuffer;\r
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
-  }\r
-\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Check Character\r
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-  \return          0  No character available.\r
-  \return          1  Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
-  {\r
-    return (0);                              /* no character available */\r
-  }\r
-  else\r
-  {\r
-    return (1);                              /*    character available */\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM3_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm33.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm33.h
deleted file mode 100644 (file)
index 02f82e2..0000000
+++ /dev/null
@@ -1,3002 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm33.h\r
- * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File\r
- * @version  V5.0.9\r
- * @date     06. July 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM33_H_GENERIC\r
-#define __CORE_CM33_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_M33\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/*  CMSIS CM33 definitions */\r
-#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\r
-                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
-  #if defined (__TARGET_FPU_VFP)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined (__ARM_PCS_VFP)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined (__ARMVFP__)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
-      #define __DSP_USED       1U\r
-    #else\r
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
-      #define __DSP_USED         0U\r
-    #endif\r
-  #else\r
-    #define __DSP_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined (__TI_VFP_SUPPORT__)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined (__FPU_VFP__)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM33_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM33_H_DEPENDANT\r
-#define __CORE_CM33_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM33_REV\r
-    #define __CM33_REV                0x0000U\r
-    #warning "__CM33_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __FPU_PRESENT\r
-    #define __FPU_PRESENT             0U\r
-    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __SAUREGION_PRESENT\r
-    #define __SAUREGION_PRESENT       0U\r
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __DSP_PRESENT\r
-    #define __DSP_PRESENT             0U\r
-    #warning "__DSP_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          3U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M33 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
-  - Core SAU Register\r
-  - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\r
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\r
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\r
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\r
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\r
-\r
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[16U];\r
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[16U];\r
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[16U];\r
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[16U];\r
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[16U];\r
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\r
-        uint32_t RESERVED5[16U];\r
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
-        uint32_t RESERVED6[580U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
-}  NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\r
-        uint32_t RESERVED3[92U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r
-        uint32_t RESERVED4[15U];\r
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\r
-        uint32_t RESERVED5[1U];\r
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r
-        uint32_t RESERVED6[1U];\r
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r
-        uint32_t RESERVED7[6U];\r
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r
-        uint32_t RESERVED8[1U];\r
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\r
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\r
-\r
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
-\r
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\r
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\r
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\r
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\r
-\r
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\r
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\r
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\r
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\r
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\r
-\r
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\r
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\r
-\r
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\r
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\r
-\r
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\r
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\r
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\r
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\r
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\r
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\r
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
-\r
-/* SCB Non-Secure Access Control Register Definitions */\r
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\r
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\r
-\r
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\r
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\r
-\r
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\r
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\r
-\r
-/* SCB Cache Level ID Register Definitions */\r
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r
-\r
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r
-\r
-/* SCB Cache Type Register Definitions */\r
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r
-\r
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r
-\r
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r
-\r
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r
-\r
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r
-\r
-/* SCB Cache Size ID Register Definitions */\r
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r
-\r
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r
-\r
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r
-\r
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r
-\r
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r
-\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r
-\r
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r
-\r
-/* SCB Cache Size Selection Register Definitions */\r
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r
-\r
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r
-\r
-/* SCB Software Triggered Interrupt Register Definitions */\r
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r
-\r
-/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r
-\r
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r
-\r
-/* SCB D-Cache Clean by Set-way Register Definitions */\r
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r
-\r
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r
-\r
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r
-\r
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r
-\r
-/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r
-\r
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r
-\r
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r
-\r
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r
-\r
-/* Data Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r
-\r
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r
-\r
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r
-\r
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r
-\r
-/* AHBP Control Register Definitions */\r
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r
-\r
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r
-\r
-/* L1 Cache Control Register Definitions */\r
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r
-\r
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r
-\r
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r
-\r
-/* AHBS Control Register Definitions */\r
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r
-\r
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r
-\r
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r
-\r
-/* Auxiliary Bus Fault Status Register Definitions */\r
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r
-\r
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r
-\r
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r
-\r
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r
-\r
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r
-\r
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
-  __OM  union\r
-  {\r
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
-        uint32_t RESERVED0[864U];\r
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
-        uint32_t RESERVED1[15U];\r
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
-        uint32_t RESERVED2[15U];\r
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
-        uint32_t RESERVED3[29U];\r
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
-        uint32_t RESERVED4[43U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
-        uint32_t RESERVED5[1U];\r
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\r
-        uint32_t RESERVED6[4U];\r
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Stimulus Port Register Definitions */\r
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\r
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\r
-\r
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\r
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\r
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\r
-\r
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\r
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-        uint32_t RESERVED3[1U];\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-        uint32_t RESERVED5[1U];\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED6[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-        uint32_t RESERVED7[1U];\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-        uint32_t RESERVED8[1U];\r
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\r
-        uint32_t RESERVED9[1U];\r
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\r
-        uint32_t RESERVED10[1U];\r
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\r
-        uint32_t RESERVED11[1U];\r
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\r
-        uint32_t RESERVED12[1U];\r
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\r
-        uint32_t RESERVED13[1U];\r
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\r
-        uint32_t RESERVED14[1U];\r
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\r
-        uint32_t RESERVED15[1U];\r
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\r
-        uint32_t RESERVED16[1U];\r
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\r
-        uint32_t RESERVED17[1U];\r
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\r
-        uint32_t RESERVED18[1U];\r
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\r
-        uint32_t RESERVED19[1U];\r
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\r
-        uint32_t RESERVED20[1U];\r
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\r
-        uint32_t RESERVED21[1U];\r
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\r
-        uint32_t RESERVED22[1U];\r
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\r
-        uint32_t RESERVED23[1U];\r
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\r
-        uint32_t RESERVED24[1U];\r
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\r
-        uint32_t RESERVED25[1U];\r
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\r
-        uint32_t RESERVED26[1U];\r
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\r
-        uint32_t RESERVED27[1U];\r
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\r
-        uint32_t RESERVED28[1U];\r
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\r
-        uint32_t RESERVED29[1U];\r
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\r
-        uint32_t RESERVED30[1U];\r
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\r
-        uint32_t RESERVED31[1U];\r
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\r
-        uint32_t RESERVED32[934U];\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r
-        uint32_t RESERVED33[1U];\r
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\r
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\r
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\r
-\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\r
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\r
-\r
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\r
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\r
-        uint32_t RESERVED3[759U];\r
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
-  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\r
-  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\r
-        uint32_t RESERVED4[1U];\r
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\r
-  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\r
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
-        uint32_t RESERVED5[39U];\r
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
-        uint32_t RESERVED7[8U];\r
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\r
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
-\r
-/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
-#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\r
-#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
-\r
-#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\r
-#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\r
-#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\r
-#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
-\r
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
-\r
-/* TPI Integration Test ATB Control Register 0 Definitions */\r
-#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\r
-#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
-\r
-#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\r
-#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\r
-#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\r
-#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\r
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\r
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\r
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\r
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\r
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\r
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\r
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\r
-        uint32_t RESERVED0[1];\r
-  union {\r
-  __IOM uint32_t MAIR[2];\r
-  struct {\r
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\r
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\r
-  };\r
-  };\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  4U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\r
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\r
-\r
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\r
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\r
-\r
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\r
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\r
-\r
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\r
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\r
-\r
-/* MPU Region Limit Address Register Definitions */\r
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\r
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\r
-\r
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\r
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\r
-\r
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\r
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 0 Definitions */\r
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\r
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\r
-\r
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\r
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\r
-\r
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\r
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\r
-\r
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\r
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 1 Definitions */\r
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\r
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\r
-\r
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\r
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\r
-\r
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\r
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\r
-\r
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\r
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)\r
-  \brief    Type definitions for the Security Attribution Unit (SAU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Security Attribution Unit (SAU).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\r
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\r
-#else\r
-        uint32_t RESERVED0[3];\r
-#endif\r
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\r
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\r
-} SAU_Type;\r
-\r
-/* SAU Control Register Definitions */\r
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\r
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\r
-\r
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\r
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\r
-\r
-/* SAU Type Register Definitions */\r
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\r
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\r
-\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-/* SAU Region Number Register Definitions */\r
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\r
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\r
-\r
-/* SAU Region Base Address Register Definitions */\r
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\r
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\r
-\r
-/* SAU Region Limit Address Register Definitions */\r
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\r
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\r
-\r
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\r
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\r
-\r
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\r
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\r
-\r
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
-\r
-/* Secure Fault Status Register Definitions */\r
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\r
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\r
-\r
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\r
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\r
-\r
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\r
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\r
-\r
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\r
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\r
-\r
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\r
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\r
-\r
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\r
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\r
-\r
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\r
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\r
-\r
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\r
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\r
-\r
-/*@} end of group CMSIS_SAU */\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
-  \brief    Type definitions for the Floating Point Unit (FPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\r
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\r
-\r
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\r
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\r
-\r
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\r
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\r
-\r
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\r
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\r
-\r
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\r
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\r
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\r
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\r
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-        uint32_t RESERVED4[1U];\r
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\r
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/* Debug Authentication Control Register Definitions */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
-\r
-/* Debug Security Control and Status Register Definitions */\r
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\r
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\r
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\r
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\r
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\r
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\r
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\r
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\r
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\r
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\r
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\r
-\r
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\r
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\r
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\r
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\r
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\r
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\r
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\r
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\r
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\r
-  #endif\r
-\r
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\r
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\r
-  #endif\r
-\r
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\r
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\r
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\r
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\r
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\r
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\r
-\r
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\r
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\r
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\r
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\r
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\r
-\r
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\r
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\r
-  #endif\r
-\r
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\r
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Debug Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\r
-\r
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \r
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\r
-\r
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\r
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\r
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\r
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\r
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\r
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\r
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
-\r
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\r
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\r
-#else \r
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\r
-#endif\r
-\r
-\r
-/**\r
-  \brief   Set Priority Grouping\r
-  \details Sets the priority grouping field using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */\r
-  SCB->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping\r
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Get Interrupt Target State\r
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-  \return             1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Target State\r
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Interrupt Target State\r
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  if interrupt is assigned to Secure\r
-                      1  if interrupt is assigned to Non Secure\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   Set Priority Grouping (non-secure)\r
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\r
-  SCB_NS->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping (non-secure)\r
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
-{\r
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt (non-secure)\r
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status (non-secure)\r
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt (non-secure)\r
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt (non-secure)\r
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt (non-secure)\r
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt (non-secure)\r
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt (non-secure)\r
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority (non-secure)\r
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every non-secure processor exception.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority (non-secure)\r
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv8.h"\r
-\r
-#endif\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-  uint32_t mvfr0;\r
-\r
-  mvfr0 = FPU->MVFR0;\r
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
-  {\r
-    return 2U;           /* Double + Single precision FPU */\r
-  }\r
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
-  {\r
-    return 1U;           /* Single precision FPU */\r
-  }\r
-  else\r
-  {\r
-    return 0U;           /* No FPU */\r
-  }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##########################   SAU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
-  \brief    Functions that configure the SAU.\r
-  @{\r
- */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-\r
-/**\r
-  \brief   Enable SAU\r
-  \details Enables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Enable(void)\r
-{\r
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-\r
-\r
-/**\r
-  \brief   Disable SAU\r
-  \details Disables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Disable(void)\r
-{\r
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_SAUFunctions */\r
-\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
-  \brief   System Tick Configuration (non-secure)\r
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                         /* Reload value impossible */\r
-  }\r
-\r
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\r
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\r
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                      SysTick_CTRL_TICKINT_Msk   |\r
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                           /* Function successful */\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
-  \brief    Functions that access the ITM debug interface.\r
-  @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
-  \brief   ITM Send Character\r
-  \details Transmits a character via the ITM channel 0, and\r
-           \li Just returns when no debugger is connected that has booked the output.\r
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-  \param [in]     ch  Character to transmit.\r
-  \returns            Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
-  {\r
-    while (ITM->PORT[0U].u32 == 0UL)\r
-    {\r
-      __NOP();\r
-    }\r
-    ITM->PORT[0U].u8 = (uint8_t)ch;\r
-  }\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Receive Character\r
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
-  \return             Received character.\r
-  \return         -1  No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
-  int32_t ch = -1;                           /* no character available */\r
-\r
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
-  {\r
-    ch = ITM_RxBuffer;\r
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
-  }\r
-\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Check Character\r
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-  \return          0  No character available.\r
-  \return          1  Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
-  {\r
-    return (0);                              /* no character available */\r
-  }\r
-  else\r
-  {\r
-    return (1);                              /*    character available */\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM33_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm4.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm4.h
deleted file mode 100644 (file)
index 308b868..0000000
+++ /dev/null
@@ -1,2129 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm4.h\r
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
- * @version  V5.0.8\r
- * @date     04. June 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM4_H_GENERIC\r
-#define __CORE_CM4_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_M4\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/* CMSIS CM4 definitions */\r
-#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
-                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM4_H_DEPENDANT\r
-#define __CORE_CM4_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM4_REV\r
-    #define __CM4_REV               0x0000U\r
-    #warning "__CM4_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __FPU_PRESENT\r
-    #define __FPU_PRESENT             0U\r
-    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          3U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M4 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
-  - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[24U];\r
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[24U];\r
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[24U];\r
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[24U];\r
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[56U];\r
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
-        uint32_t RESERVED5[644U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
-}  NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
-        uint32_t RESERVED0[5U];\r
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\r
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\r
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
-  __OM  union\r
-  {\r
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
-        uint32_t RESERVED0[864U];\r
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
-        uint32_t RESERVED1[15U];\r
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
-        uint32_t RESERVED2[15U];\r
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
-        uint32_t RESERVED3[29U];\r
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
-        uint32_t RESERVED4[43U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
-        uint32_t RESERVED5[6U];\r
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
-        uint32_t RESERVED3[759U];\r
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
-        uint32_t RESERVED4[1U];\r
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
-        uint32_t RESERVED5[39U];\r
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
-        uint32_t RESERVED7[8U];\r
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  4U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
-  \brief    Type definitions for the Floating Point Unit (FPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Debug Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\r
-#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\r
-#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\r
-\r
-\r
-/**\r
-  \brief   Set Priority Grouping\r
-  \details Sets the priority grouping field using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\r
-  SCB->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping\r
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-  uint32_t mvfr0;\r
-\r
-  mvfr0 = FPU->MVFR0;\r
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
-  {\r
-    return 1U;           /* Single precision FPU */\r
-  }\r
-  else\r
-  {\r
-    return 0U;           /* No FPU */\r
-  }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
-  \brief    Functions that access the ITM debug interface.\r
-  @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
-  \brief   ITM Send Character\r
-  \details Transmits a character via the ITM channel 0, and\r
-           \li Just returns when no debugger is connected that has booked the output.\r
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-  \param [in]     ch  Character to transmit.\r
-  \returns            Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
-  {\r
-    while (ITM->PORT[0U].u32 == 0UL)\r
-    {\r
-      __NOP();\r
-    }\r
-    ITM->PORT[0U].u8 = (uint8_t)ch;\r
-  }\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Receive Character\r
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
-  \return             Received character.\r
-  \return         -1  No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
-  int32_t ch = -1;                           /* no character available */\r
-\r
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
-  {\r
-    ch = ITM_RxBuffer;\r
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
-  }\r
-\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Check Character\r
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-  \return          0  No character available.\r
-  \return          1  Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
-  {\r
-    return (0);                              /* no character available */\r
-  }\r
-  else\r
-  {\r
-    return (1);                              /*    character available */\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm7.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_cm7.h
deleted file mode 100644 (file)
index ada6c2a..0000000
+++ /dev/null
@@ -1,2671 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_cm7.h\r
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
- * @version  V5.0.8\r
- * @date     04. June 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM7_H_GENERIC\r
-#define __CORE_CM7_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup Cortex_M7\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/* CMSIS CM7 definitions */\r
-#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
-                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
-      #define __FPU_USED       1U\r
-    #else\r
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-      #define __FPU_USED       0U\r
-    #endif\r
-  #else\r
-    #define __FPU_USED         0U\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM7_H_DEPENDANT\r
-#define __CORE_CM7_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __CM7_REV\r
-    #define __CM7_REV               0x0000U\r
-    #warning "__CM7_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __FPU_PRESENT\r
-    #define __FPU_PRESENT             0U\r
-    #warning "__FPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __ICACHE_PRESENT\r
-    #define __ICACHE_PRESENT          0U\r
-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __DCACHE_PRESENT\r
-    #define __DCACHE_PRESENT          0U\r
-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __DTCM_PRESENT\r
-    #define __DTCM_PRESENT            0U\r
-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          3U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M7 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
-  - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[24U];\r
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[24U];\r
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[24U];\r
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[24U];\r
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[56U];\r
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
-        uint32_t RESERVED5[644U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
-}  NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
-  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
-  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
-  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
-        uint32_t RESERVED0[1U];\r
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
-        uint32_t RESERVED3[93U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r
-        uint32_t RESERVED4[15U];\r
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\r
-        uint32_t RESERVED5[1U];\r
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r
-        uint32_t RESERVED6[1U];\r
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r
-        uint32_t RESERVED7[6U];\r
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r
-        uint32_t RESERVED8[1U];\r
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\r
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\r
-\r
-#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\r
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\r
-\r
-#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\r
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\r
-\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
-\r
-/* SCB Cache Level ID Register Definitions */\r
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r
-\r
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r
-\r
-/* SCB Cache Type Register Definitions */\r
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r
-\r
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r
-\r
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r
-\r
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r
-\r
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r
-\r
-/* SCB Cache Size ID Register Definitions */\r
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r
-\r
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r
-\r
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r
-\r
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r
-\r
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r
-\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r
-\r
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r
-\r
-/* SCB Cache Size Selection Register Definitions */\r
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r
-\r
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r
-\r
-/* SCB Software Triggered Interrupt Register Definitions */\r
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r
-\r
-/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r
-\r
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r
-\r
-/* SCB D-Cache Clean by Set-way Register Definitions */\r
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r
-\r
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r
-\r
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r
-\r
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r
-\r
-/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r
-\r
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r
-\r
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r
-\r
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r
-\r
-/* Data Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r
-\r
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r
-\r
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r
-\r
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r
-\r
-/* AHBP Control Register Definitions */\r
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r
-\r
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r
-\r
-/* L1 Cache Control Register Definitions */\r
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r
-\r
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r
-\r
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r
-\r
-/* AHBS Control Register Definitions */\r
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r
-\r
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r
-\r
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r
-\r
-/* Auxiliary Bus Fault Status Register Definitions */\r
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r
-\r
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r
-\r
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r
-\r
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r
-\r
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r
-\r
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\r
-\r
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\r
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\r
-\r
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\r
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
-  __OM  union\r
-  {\r
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
-        uint32_t RESERVED0[864U];\r
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
-        uint32_t RESERVED1[15U];\r
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
-        uint32_t RESERVED2[15U];\r
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
-        uint32_t RESERVED3[29U];\r
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
-        uint32_t RESERVED4[43U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
-        uint32_t RESERVED5[6U];\r
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-        uint32_t RESERVED3[981U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
-        uint32_t RESERVED3[759U];\r
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
-        uint32_t RESERVED4[1U];\r
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
-        uint32_t RESERVED5[39U];\r
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
-        uint32_t RESERVED7[8U];\r
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES                  4U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)\r
-  \brief    Type definitions for the Floating Point Unit (FPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/* Media and FP Feature Register 2 Definitions */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Debug Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\r
-#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\r
-#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\r
-\r
-\r
-/**\r
-  \brief   Set Priority Grouping\r
-  \details Sets the priority grouping field using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\r
-  SCB->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping\r
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ##########################  MPU functions  #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv7.h"\r
-\r
-#endif\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-  uint32_t mvfr0;\r
-\r
-  mvfr0 = SCB->MVFR0;\r
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
-  {\r
-    return 2U;           /* Double + Single precision FPU */\r
-  }\r
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
-  {\r
-    return 1U;           /* Single precision FPU */\r
-  }\r
-  else\r
-  {\r
-    return 0U;           /* No FPU */\r
-  }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##########################  Cache functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
-  \brief    Functions that configure Instruction and Data cache.\r
-  @{\r
- */\r
-\r
-/* Cache Size ID Register Macros */\r
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\r
-\r
-\r
-/**\r
-  \brief   Enable I-Cache\r
-  \details Turns on I-Cache\r
-  */\r
-__STATIC_INLINE void SCB_EnableICache (void)\r
-{\r
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
-    __DSB();\r
-    __ISB();\r
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r
-    __DSB();\r
-    __ISB();\r
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable I-Cache\r
-  \details Turns off I-Cache\r
-  */\r
-__STATIC_INLINE void SCB_DisableICache (void)\r
-{\r
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
-    __DSB();\r
-    __ISB();\r
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\r
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Invalidate I-Cache\r
-  \details Invalidates I-Cache\r
-  */\r
-__STATIC_INLINE void SCB_InvalidateICache (void)\r
-{\r
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
-    __DSB();\r
-    __ISB();\r
-    SCB->ICIALLU = 0UL;\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable D-Cache\r
-  \details Turns on D-Cache\r
-  */\r
-__STATIC_INLINE void SCB_EnableDCache (void)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-    uint32_t ccsidr;\r
-    uint32_t sets;\r
-    uint32_t ways;\r
-\r
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
-    __DSB();\r
-\r
-    ccsidr = SCB->CCSIDR;\r
-\r
-                                            /* invalidate D-Cache */\r
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
-    do {\r
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
-      do {\r
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r
-        #if defined ( __CC_ARM )\r
-          __schedule_barrier();\r
-        #endif\r
-      } while (ways-- != 0U);\r
-    } while(sets-- != 0U);\r
-    __DSB();\r
-\r
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable D-Cache\r
-  \details Turns off D-Cache\r
-  */\r
-__STATIC_INLINE void SCB_DisableDCache (void)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-    uint32_t ccsidr;\r
-    uint32_t sets;\r
-    uint32_t ways;\r
-\r
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
-    __DSB();\r
-\r
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\r
-    __DSB();\r
-\r
-    ccsidr = SCB->CCSIDR;\r
-\r
-                                            /* clean & invalidate D-Cache */\r
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
-    do {\r
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
-      do {\r
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r
-        #if defined ( __CC_ARM )\r
-          __schedule_barrier();\r
-        #endif\r
-      } while (ways-- != 0U);\r
-    } while(sets-- != 0U);\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Invalidate D-Cache\r
-  \details Invalidates D-Cache\r
-  */\r
-__STATIC_INLINE void SCB_InvalidateDCache (void)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-    uint32_t ccsidr;\r
-    uint32_t sets;\r
-    uint32_t ways;\r
-\r
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
-    __DSB();\r
-\r
-    ccsidr = SCB->CCSIDR;\r
-\r
-                                            /* invalidate D-Cache */\r
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
-    do {\r
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
-      do {\r
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r
-        #if defined ( __CC_ARM )\r
-          __schedule_barrier();\r
-        #endif\r
-      } while (ways-- != 0U);\r
-    } while(sets-- != 0U);\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clean D-Cache\r
-  \details Cleans D-Cache\r
-  */\r
-__STATIC_INLINE void SCB_CleanDCache (void)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-    uint32_t ccsidr;\r
-    uint32_t sets;\r
-    uint32_t ways;\r
-\r
-     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
-   __DSB();\r
-\r
-    ccsidr = SCB->CCSIDR;\r
-\r
-                                            /* clean D-Cache */\r
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
-    do {\r
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
-      do {\r
-        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
-                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\r
-        #if defined ( __CC_ARM )\r
-          __schedule_barrier();\r
-        #endif\r
-      } while (ways-- != 0U);\r
-    } while(sets-- != 0U);\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clean & Invalidate D-Cache\r
-  \details Cleans and Invalidates D-Cache\r
-  */\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-    uint32_t ccsidr;\r
-    uint32_t sets;\r
-    uint32_t ways;\r
-\r
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\r
-    __DSB();\r
-\r
-    ccsidr = SCB->CCSIDR;\r
-\r
-                                            /* clean & invalidate D-Cache */\r
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
-    do {\r
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
-      do {\r
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r
-        #if defined ( __CC_ARM )\r
-          __schedule_barrier();\r
-        #endif\r
-      } while (ways-- != 0U);\r
-    } while(sets-- != 0U);\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   D-Cache Invalidate by address\r
-  \details Invalidates D-Cache for the given address\r
-  \param[in]   addr    address (aligned to 32-byte boundary)\r
-  \param[in]   dsize   size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-     int32_t op_size = dsize;\r
-    uint32_t op_addr = (uint32_t)addr;\r
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
-    __DSB();\r
-\r
-    while (op_size > 0) {\r
-      SCB->DCIMVAC = op_addr;\r
-      op_addr += (uint32_t)linesize;\r
-      op_size -=           linesize;\r
-    }\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   D-Cache Clean by address\r
-  \details Cleans D-Cache for the given address\r
-  \param[in]   addr    address (aligned to 32-byte boundary)\r
-  \param[in]   dsize   size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-     int32_t op_size = dsize;\r
-    uint32_t op_addr = (uint32_t) addr;\r
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
-    __DSB();\r
-\r
-    while (op_size > 0) {\r
-      SCB->DCCMVAC = op_addr;\r
-      op_addr += (uint32_t)linesize;\r
-      op_size -=           linesize;\r
-    }\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/**\r
-  \brief   D-Cache Clean and Invalidate by address\r
-  \details Cleans and invalidates D_Cache for the given address\r
-  \param[in]   addr    address (aligned to 32-byte boundary)\r
-  \param[in]   dsize   size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
-     int32_t op_size = dsize;\r
-    uint32_t op_addr = (uint32_t) addr;\r
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
-    __DSB();\r
-\r
-    while (op_size > 0) {\r
-      SCB->DCCIMVAC = op_addr;\r
-      op_addr += (uint32_t)linesize;\r
-      op_size -=           linesize;\r
-    }\r
-\r
-    __DSB();\r
-    __ISB();\r
-  #endif\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_CacheFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
-  \brief    Functions that access the ITM debug interface.\r
-  @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
-  \brief   ITM Send Character\r
-  \details Transmits a character via the ITM channel 0, and\r
-           \li Just returns when no debugger is connected that has booked the output.\r
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-  \param [in]     ch  Character to transmit.\r
-  \returns            Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
-  {\r
-    while (ITM->PORT[0U].u32 == 0UL)\r
-    {\r
-      __NOP();\r
-    }\r
-    ITM->PORT[0U].u8 = (uint8_t)ch;\r
-  }\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Receive Character\r
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
-  \return             Received character.\r
-  \return         -1  No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
-  int32_t ch = -1;                           /* no character available */\r
-\r
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
-  {\r
-    ch = ITM_RxBuffer;\r
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
-  }\r
-\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Check Character\r
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-  \return          0  No character available.\r
-  \return          1  Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
-  {\r
-    return (0);                              /* no character available */\r
-  }\r
-  else\r
-  {\r
-    return (1);                              /*    character available */\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_sc000.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_sc000.h
deleted file mode 100644 (file)
index 9086c64..0000000
+++ /dev/null
@@ -1,1022 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_sc000.h\r
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\r
- * @version  V5.0.5\r
- * @date     28. May 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_SC000_H_GENERIC\r
-#define __CORE_SC000_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup SC000\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/*  CMSIS SC000 definitions */\r
-#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\r
-                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC000_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_SC000_H_DEPENDANT\r
-#define __CORE_SC000_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __SC000_REV\r
-    #define __SC000_REV             0x0000U\r
-    #warning "__SC000_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          2U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group SC000 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[31U];\r
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[31U];\r
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[31U];\r
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[31U];\r
-        uint32_t RESERVED4[64U];\r
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r
-}  NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-        uint32_t RESERVED1[154U];\r
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
-            Therefore they are not covered by the SC000 header file.\r
-  @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */\r
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-\r
-\r
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-  else\r
-  {\r
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                 SCB_AIRCR_SYSRESETREQ_Msk);\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC000_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_sc300.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/core_sc300.h
deleted file mode 100644 (file)
index 665822d..0000000
+++ /dev/null
@@ -1,1915 +0,0 @@
-/**************************************************************************//**\r
- * @file     core_sc300.h\r
- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\r
- * @version  V5.0.6\r
- * @date     04. June 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_SC300_H_GENERIC\r
-#define __CORE_SC300_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r
-  CMSIS violates the following MISRA-C:2004 rules:\r
-\r
-   \li Required Rule 8.5, object/function definition in header file.<br>\r
-     Function definitions in header files are used to allow 'inlining'.\r
-\r
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
-     Unions are used for effective representation of core registers.\r
-\r
-   \li Advisory Rule 19.7, Function-like macro defined.<br>\r
-     Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- *                 CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
-  \ingroup SC3000\r
-  @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/*  CMSIS SC300 definitions */\r
-#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */\r
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\r
-                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
-    This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED       0U\r
-\r
-#if defined ( __CC_ARM )\r
-  #if defined __TARGET_FPU_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
-  #if defined __ARM_PCS_VFP\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __GNUC__ )\r
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
-  #if defined __ARMVFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
-  #if defined __TI_VFP_SUPPORT__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __TASKING__ )\r
-  #if defined __FPU_VFP__\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#elif defined ( __CSMC__ )\r
-  #if ( __CSMC__ & 0x400U)\r
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
-  #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC300_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_SC300_H_DEPENDANT\r
-#define __CORE_SC300_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
-  #ifndef __SC300_REV\r
-    #define __SC300_REV               0x0000U\r
-    #warning "__SC300_REV not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __MPU_PRESENT\r
-    #define __MPU_PRESENT             0U\r
-    #warning "__MPU_PRESENT not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __NVIC_PRIO_BITS\r
-    #define __NVIC_PRIO_BITS          3U\r
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
-  #endif\r
-\r
-  #ifndef __Vendor_SysTickConfig\r
-    #define __Vendor_SysTickConfig    0U\r
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
-  #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
-    \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
-    <strong>IO Type Qualifiers</strong> are used\r
-    \li to specify the access to peripheral variables.\r
-    \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
-  #define   __I     volatile             /*!< Defines 'read only' permissions */\r
-#else\r
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r
-#endif\r
-#define     __O     volatile             /*!< Defines 'write only' permissions */\r
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group SC300 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                 Register Abstraction\r
-  Core Register contain:\r
-  - Core Register\r
-  - Core NVIC Register\r
-  - Core SCB Register\r
-  - Core SysTick Register\r
-  - Core Debug Register\r
-  - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_core_register Defines and Type Definitions\r
-  \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_CORE  Status and Control Registers\r
-  \brief      Core Register type definitions.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r
-    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\r
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r
-\r
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r
-\r
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
-  \brief  Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
-  struct\r
-  {\r
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r
-  } b;                                   /*!< Structure used for bit  access */\r
-  uint32_t w;                            /*!< Type      used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r
-  \brief      Type definitions for the NVIC Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r
-        uint32_t RESERVED0[24U];\r
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r
-        uint32_t RSERVED1[24U];\r
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r
-        uint32_t RESERVED2[24U];\r
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r
-        uint32_t RESERVED3[24U];\r
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r
-        uint32_t RESERVED4[56U];\r
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r
-        uint32_t RESERVED5[644U];\r
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r
-}  NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCB     System Control Block (SCB)\r
-  \brief    Type definitions for the System Control Block Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r
-        uint32_t RESERVED0[5U];\r
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r
-        uint32_t RESERVED1[129U];\r
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
-  \brief    Type definitions for the System Control and ID Register not in the SCB\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
-        uint32_t RESERVED0[1U];\r
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r
-        uint32_t RESERVED1[1U];\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r
-  \brief    Type definitions for the System Timer Registers.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
-  __OM  union\r
-  {\r
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r
-        uint32_t RESERVED0[864U];\r
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r
-        uint32_t RESERVED1[15U];\r
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r
-        uint32_t RESERVED2[15U];\r
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r
-        uint32_t RESERVED3[29U];\r
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r
-        uint32_t RESERVED4[43U];\r
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r
-        uint32_t RESERVED5[6U];\r
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r
-        uint32_t RESERVED0[1U];\r
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r
-        uint32_t RESERVED1[1U];\r
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r
-        uint32_t RESERVED2[1U];\r
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)\r
-  \brief    Type definitions for the Trace Port Interface (TPI)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r
-        uint32_t RESERVED0[2U];\r
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r
-        uint32_t RESERVED1[55U];\r
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r
-        uint32_t RESERVED2[131U];\r
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r
-        uint32_t RESERVED3[759U];\r
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r
-        uint32_t RESERVED4[1U];\r
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r
-        uint32_t RESERVED5[39U];\r
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r
-        uint32_t RESERVED7[8U];\r
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r
-  \brief    Type definitions for the Memory Protection Unit (MPU)\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
-  \ingroup  CMSIS_core_register\r
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r
-  \brief    Type definitions for the Core Debug Registers\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief  Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros\r
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   Mask and shift a bit field value for use in a register bit range.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
-  \brief     Mask and shift a register value to extract a bit filed value.\r
-  \param[in] field  Name of the register bit field.\r
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r
-  \return           Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
-  \ingroup    CMSIS_core_register\r
-  \defgroup   CMSIS_core_base     Core Definitions\r
-  \brief      Definitions for base addresses, unions, and structures.\r
-  @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- *                Hardware Abstraction Layer\r
-  Core Function Interface contains:\r
-  - Core NVIC Functions\r
-  - Core SysTick Functions\r
-  - Core Debug Functions\r
-  - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ##########################   NVIC functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
-  \brief    Functions that manage interrupts and exceptions via the NVIC.\r
-  @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
-  #endif\r
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r
-  #define NVIC_GetActive              __NVIC_GetActive\r
-  #define NVIC_SetPriority            __NVIC_SetPriority\r
-  #define NVIC_GetPriority            __NVIC_GetPriority\r
-  #define NVIC_SystemReset            __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
-  #endif\r
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
-  #define NVIC_SetVector              __NVIC_SetVector\r
-  #define NVIC_GetVector              __NVIC_GetVector\r
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET          16\r
-\r
-\r
-/* The following EXC_RETURN values are saved the LR on exception entry */\r
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r
-\r
-\r
-\r
-/**\r
-  \brief   Set Priority Grouping\r
-  \details Sets the priority grouping field using the required unlock sequence.\r
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
-           Only values from 0..7 are used.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]      PriorityGroup  Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r
-\r
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r
-  reg_value  =  (reg_value                                   |\r
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r
-  SCB->AIRCR =  reg_value;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Priority Grouping\r
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
-  \brief   Enable Interrupt\r
-  \details Enables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Enable status\r
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt is not enabled.\r
-  \return             1  Interrupt is enabled.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Disable Interrupt\r
-  \details Disables a device specific interrupt in the NVIC interrupt controller.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-    __DSB();\r
-    __ISB();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Pending Interrupt\r
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not pending.\r
-  \return             1  Interrupt status is pending.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Pending Interrupt\r
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Clear Pending Interrupt\r
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Active Interrupt\r
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
-  \param [in]      IRQn  Device specific interrupt number.\r
-  \return             0  Interrupt status is not active.\r
-  \return             1  Interrupt status is active.\r
-  \note    IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-  }\r
-  else\r
-  {\r
-    return(0U);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Priority\r
-  \details Sets the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]      IRQn  Interrupt number.\r
-  \param [in]  priority  Priority to set.\r
-  \note    The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-  else\r
-  {\r
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Priority\r
-  \details Reads the priority of a device specific interrupt or a processor exception.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn  Interrupt number.\r
-  \return             Interrupt Priority.\r
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
-  if ((int32_t)(IRQn) >= 0)\r
-  {\r
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-  else\r
-  {\r
-    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  \brief   Encode Priority\r
-  \details Encodes the priority for an interrupt with the given priority group,\r
-           preemptive priority value, and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [in]       SubPriority  Subpriority value (starting from 0).\r
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  return (\r
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r
-         );\r
-}\r
-\r
-\r
-/**\r
-  \brief   Decode Priority\r
-  \details Decodes an interrupt priority value with a given priority group to\r
-           preemptive priority value and subpriority value.\r
-           In case of a conflict between priority grouping and available\r
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
-  \param [in]     PriorityGroup  Used priority group.\r
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r
-  \param [out]     pSubPriority  Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r
-  uint32_t PreemptPriorityBits;\r
-  uint32_t SubPriorityBits;\r
-\r
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
-  \brief   Set Interrupt Vector\r
-  \details Sets an interrupt vector in SRAM based interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-           VTOR must been relocated to SRAM before.\r
-  \param [in]   IRQn      Interrupt number\r
-  \param [in]   vector    Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
-  \brief   Get Interrupt Vector\r
-  \details Reads an interrupt vector from interrupt vector table.\r
-           The interrupt number can be positive to specify a device specific interrupt,\r
-           or negative to specify a processor exception.\r
-  \param [in]   IRQn      Interrupt number.\r
-  \return                 Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
-  \brief   System Reset\r
-  \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
-  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
-                                                                       buffered write are completed before reset */\r
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
-  __DSB();                                                          /* Ensure completion of memory access */\r
-\r
-  for(;;)                                                           /* wait until reset */\r
-  {\r
-    __NOP();\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ##########################  FPU functions  #################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
-  \brief    Function that provides FPU type.\r
-  @{\r
- */\r
-\r
-/**\r
-  \brief   get FPU type\r
-  \details returns the FPU type\r
-  \returns\r
-   - \b  0: No FPU\r
-   - \b  1: Single precision FPU\r
-   - \b  2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
-    return 0U;           /* No FPU */\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ##################################    SysTick function  ############################################ */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
-  \brief    Functions that configure the System.\r
-  @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
-  \brief   System Tick Configuration\r
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
-           Counter is in free running mode to generate periodic interrupts.\r
-  \param [in]  ticks  Number of ticks between two interrupts.\r
-  \return          0  Function succeeded.\r
-  \return          1  Function failed.\r
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
-           must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
-  {\r
-    return (1UL);                                                   /* Reload value impossible */\r
-  }\r
-\r
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_TICKINT_Msk   |\r
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0UL);                                                     /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
-  \ingroup  CMSIS_Core_FunctionInterface\r
-  \defgroup CMSIS_core_DebugFunctions ITM Functions\r
-  \brief    Functions that access the ITM debug interface.\r
-  @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
-  \brief   ITM Send Character\r
-  \details Transmits a character via the ITM channel 0, and\r
-           \li Just returns when no debugger is connected that has booked the output.\r
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-  \param [in]     ch  Character to transmit.\r
-  \returns            Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r
-  {\r
-    while (ITM->PORT[0U].u32 == 0UL)\r
-    {\r
-      __NOP();\r
-    }\r
-    ITM->PORT[0U].u8 = (uint8_t)ch;\r
-  }\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Receive Character\r
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
-  \return             Received character.\r
-  \return         -1  No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
-  int32_t ch = -1;                           /* no character available */\r
-\r
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
-  {\r
-    ch = ITM_RxBuffer;\r
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
-  }\r
-\r
-  return (ch);\r
-}\r
-\r
-\r
-/**\r
-  \brief   ITM Check Character\r
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-  \return          0  No character available.\r
-  \return          1  Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
-  {\r
-    return (0);                              /* no character available */\r
-  }\r
-  else\r
-  {\r
-    return (1);                              /*    character available */\r
-  }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC300_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/mpu_armv7.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/mpu_armv7.h
deleted file mode 100644 (file)
index 7d4b600..0000000
+++ /dev/null
@@ -1,270 +0,0 @@
-/******************************************************************************\r
- * @file     mpu_armv7.h\r
- * @brief    CMSIS MPU API for Armv7-M MPU\r
- * @version  V5.0.4\r
- * @date     10. January 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header    /* treat file as system include file */\r
-#endif\r
\r
-#ifndef ARM_MPU_ARMV7_H\r
-#define ARM_MPU_ARMV7_H\r
-\r
-#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\r
-#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\r
-#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\r
-#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\r
-#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\r
-#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\r
-#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\r
-#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\r
-#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\r
-#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\r
-#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\r
-#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\r
-#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\r
-#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\r
-#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\r
-#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\r
-#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\r
-#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\r
-#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\r
-#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\r
-#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\r
-#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\r
-#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\r
-#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\r
-#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\r
-#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\r
-#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\r
-#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\r
-\r
-#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\r
-#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\r
-#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only\r
-#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\r
-#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only\r
-#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access\r
-\r
-/** MPU Region Base Address Register Value\r
-*\r
-* \param Region The region to be configured, number 0 to 15.\r
-* \param BaseAddress The base address for the region.\r
-*/\r
-#define ARM_MPU_RBAR(Region, BaseAddress) \\r
-  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \\r
-   ((Region) & MPU_RBAR_REGION_Msk)    |  \\r
-   (MPU_RBAR_VALID_Msk))\r
-\r
-/**\r
-* MPU Memory Access Attributes\r
-* \r
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
-* \param IsShareable       Region is shareable between multiple bus masters.\r
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\r
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
-*/  \r
-#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \\r
-  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \\r
-   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \\r
-   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \\r
-   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\r
-\r
-/**\r
-* MPU Region Attribute and Size Register Value\r
-* \r
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\r
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
-* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.\r
-* \param SubRegionDisable  Sub-region disable field.\r
-* \param Size              Region size of the region to be configured, for example 4K, 8K.\r
-*/\r
-#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \\r
-  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \\r
-   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \\r
-   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))\r
-  \r
-/**\r
-* MPU Region Attribute and Size Register Value\r
-* \r
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\r
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
-* \param IsShareable       Region is shareable between multiple bus masters.\r
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\r
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
-* \param SubRegionDisable  Sub-region disable field.\r
-* \param Size              Region size of the region to be configured, for example 4K, 8K.\r
-*/                         \r
-#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\r
-  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\r
-\r
-/**\r
-* MPU Memory Access Attribute for strongly ordered memory.\r
-*  - TEX: 000b\r
-*  - Shareable\r
-*  - Non-cacheable\r
-*  - Non-bufferable\r
-*/ \r
-#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\r
-\r
-/**\r
-* MPU Memory Access Attribute for device memory.\r
-*  - TEX: 000b (if non-shareable) or 010b (if shareable)\r
-*  - Shareable or non-shareable\r
-*  - Non-cacheable\r
-*  - Bufferable (if shareable) or non-bufferable (if non-shareable)\r
-*\r
-* \param IsShareable Configures the device memory as shareable or non-shareable.\r
-*/ \r
-#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\r
-\r
-/**\r
-* MPU Memory Access Attribute for normal memory.\r
-*  - TEX: 1BBb (reflecting outer cacheability rules)\r
-*  - Shareable or non-shareable\r
-*  - Cacheable or non-cacheable (reflecting inner cacheability rules)\r
-*  - Bufferable or non-bufferable (reflecting inner cacheability rules)\r
-*\r
-* \param OuterCp Configures the outer cache policy.\r
-* \param InnerCp Configures the inner cache policy.\r
-* \param IsShareable Configures the memory as shareable or non-shareable.\r
-*/ \r
-#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\r
-\r
-/**\r
-* MPU Memory Access Attribute non-cacheable policy.\r
-*/\r
-#define ARM_MPU_CACHEP_NOCACHE 0U\r
-\r
-/**\r
-* MPU Memory Access Attribute write-back, write and read allocate policy.\r
-*/\r
-#define ARM_MPU_CACHEP_WB_WRA 1U\r
-\r
-/**\r
-* MPU Memory Access Attribute write-through, no write allocate policy.\r
-*/\r
-#define ARM_MPU_CACHEP_WT_NWA 2U\r
-\r
-/**\r
-* MPU Memory Access Attribute write-back, no write allocate policy.\r
-*/\r
-#define ARM_MPU_CACHEP_WB_NWA 3U\r
-\r
-\r
-/**\r
-* Struct for a single MPU Region\r
-*/\r
-typedef struct {\r
-  uint32_t RBAR; //!< The region base address register value (RBAR)\r
-  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR\r
-} ARM_MPU_Region_t;\r
-    \r
-/** Enable the MPU.\r
-* \param MPU_Control Default access permissions for unconfigured regions.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
-{\r
-  __DSB();\r
-  __ISB();\r
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
-#endif\r
-}\r
-\r
-/** Disable the MPU.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Disable(void)\r
-{\r
-  __DSB();\r
-  __ISB();\r
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
-#endif\r
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r
-}\r
-\r
-/** Clear and disable the given MPU region.\r
-* \param rnr Region number to be cleared.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
-{\r
-  MPU->RNR = rnr;\r
-  MPU->RASR = 0U;\r
-}\r
-\r
-/** Configure an MPU region.\r
-* \param rbar Value for RBAR register.\r
-* \param rsar Value for RSAR register.\r
-*/   \r
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\r
-{\r
-  MPU->RBAR = rbar;\r
-  MPU->RASR = rasr;\r
-}\r
-\r
-/** Configure the given MPU region.\r
-* \param rnr Region number to be configured.\r
-* \param rbar Value for RBAR register.\r
-* \param rsar Value for RSAR register.\r
-*/   \r
-__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\r
-{\r
-  MPU->RNR = rnr;\r
-  MPU->RBAR = rbar;\r
-  MPU->RASR = rasr;\r
-}\r
-\r
-/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
-* \param dst Destination data is copied to.\r
-* \param src Source data is copied from.\r
-* \param len Amount of data words to be copied.\r
-*/\r
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
-{\r
-  uint32_t i;\r
-  for (i = 0U; i < len; ++i) \r
-  {\r
-    dst[i] = src[i];\r
-  }\r
-}\r
-\r
-/** Load the given number of MPU regions from a table.\r
-* \param table Pointer to the MPU configuration table.\r
-* \param cnt Amount of regions to be configured.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \r
-{\r
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
-  while (cnt > MPU_TYPE_RALIASES) {\r
-    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\r
-    table += MPU_TYPE_RALIASES;\r
-    cnt -= MPU_TYPE_RALIASES;\r
-  }\r
-  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\r
-}\r
-\r
-#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/mpu_armv8.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/mpu_armv8.h
deleted file mode 100644 (file)
index 99ee9f9..0000000
+++ /dev/null
@@ -1,333 +0,0 @@
-/******************************************************************************\r
- * @file     mpu_armv8.h\r
- * @brief    CMSIS MPU API for Armv8-M MPU\r
- * @version  V5.0.4\r
- * @date     10. January 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header    /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef ARM_MPU_ARMV8_H\r
-#define ARM_MPU_ARMV8_H\r
-\r
-/** \brief Attribute for device memory (outer only) */\r
-#define ARM_MPU_ATTR_DEVICE                           ( 0U )\r
-\r
-/** \brief Attribute for non-cacheable, normal memory */\r
-#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\r
-\r
-/** \brief Attribute for normal memory (outer and inner)\r
-* \param NT Non-Transient: Set to 1 for non-transient data.\r
-* \param WB Write-Back: Set to 1 to use write-back update policy.\r
-* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.\r
-* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.\r
-*/\r
-#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\r
-  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\r
-\r
-/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\r
-#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\r
-\r
-/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\r
-#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)\r
-\r
-/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\r
-#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)\r
-\r
-/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\r
-#define ARM_MPU_ATTR_DEVICE_GRE    (3U)\r
-\r
-/** \brief Memory Attribute\r
-* \param O Outer memory attributes\r
-* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\r
-*/\r
-#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\r
-\r
-/** \brief Normal memory non-shareable  */\r
-#define ARM_MPU_SH_NON   (0U)\r
-\r
-/** \brief Normal memory outer shareable  */\r
-#define ARM_MPU_SH_OUTER (2U)\r
-\r
-/** \brief Normal memory inner shareable  */\r
-#define ARM_MPU_SH_INNER (3U)\r
-\r
-/** \brief Memory access permissions\r
-* \param RO Read-Only: Set to 1 for read-only memory.\r
-* \param NP Non-Privileged: Set to 1 for non-privileged memory.\r
-*/\r
-#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\r
-\r
-/** \brief Region Base Address Register value\r
-* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\r
-* \param SH Defines the Shareability domain for this memory region.\r
-* \param RO Read-Only: Set to 1 for a read-only memory region.\r
-* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.\r
-* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r
-*/\r
-#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\r
-  ((BASE & MPU_RBAR_BASE_Msk) | \\r
-  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\r
-  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\r
-  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r
-\r
-/** \brief Region Limit Address Register value\r
-* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
-* \param IDX The attribute index to be associated with this memory region.\r
-*/\r
-#define ARM_MPU_RLAR(LIMIT, IDX) \\r
-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
-  (MPU_RLAR_EN_Msk))\r
-\r
-/**\r
-* Struct for a single MPU Region\r
-*/\r
-typedef struct {\r
-  uint32_t RBAR;                   /*!< Region Base Address Register value */\r
-  uint32_t RLAR;                   /*!< Region Limit Address Register value */\r
-} ARM_MPU_Region_t;\r
-    \r
-/** Enable the MPU.\r
-* \param MPU_Control Default access permissions for unconfigured regions.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
-{\r
-  __DSB();\r
-  __ISB();\r
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
-#endif\r
-}\r
-\r
-/** Disable the MPU.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Disable(void)\r
-{\r
-  __DSB();\r
-  __ISB();\r
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
-#endif\r
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r
-}\r
-\r
-#ifdef MPU_NS\r
-/** Enable the Non-secure MPU.\r
-* \param MPU_Control Default access permissions for unconfigured regions.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r
-{\r
-  __DSB();\r
-  __ISB();\r
-  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
-  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
-#endif\r
-}\r
-\r
-/** Disable the Non-secure MPU.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Disable_NS(void)\r
-{\r
-  __DSB();\r
-  __ISB();\r
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
-  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
-#endif\r
-  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r
-}\r
-#endif\r
-\r
-/** Set the memory attribute encoding to the given MPU.\r
-* \param mpu Pointer to the MPU to be configured.\r
-* \param idx The attribute index to be set [0-7]\r
-* \param attr The attribute value to be set.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\r
-{\r
-  const uint8_t reg = idx / 4U;\r
-  const uint32_t pos = ((idx % 4U) * 8U);\r
-  const uint32_t mask = 0xFFU << pos;\r
-  \r
-  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\r
-    return; // invalid index\r
-  }\r
-  \r
-  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\r
-}\r
-\r
-/** Set the memory attribute encoding.\r
-* \param idx The attribute index to be set [0-7]\r
-* \param attr The attribute value to be set.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\r
-{\r
-  ARM_MPU_SetMemAttrEx(MPU, idx, attr);\r
-}\r
-\r
-#ifdef MPU_NS\r
-/** Set the memory attribute encoding to the Non-secure MPU.\r
-* \param idx The attribute index to be set [0-7]\r
-* \param attr The attribute value to be set.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\r
-{\r
-  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\r
-}\r
-#endif\r
-\r
-/** Clear and disable the given MPU region of the given MPU.\r
-* \param mpu Pointer to MPU to be used.\r
-* \param rnr Region number to be cleared.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\r
-{\r
-  mpu->RNR = rnr;\r
-  mpu->RLAR = 0U;\r
-}\r
-\r
-/** Clear and disable the given MPU region.\r
-* \param rnr Region number to be cleared.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
-{\r
-  ARM_MPU_ClrRegionEx(MPU, rnr);\r
-}\r
-\r
-#ifdef MPU_NS\r
-/** Clear and disable the given Non-secure MPU region.\r
-* \param rnr Region number to be cleared.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\r
-{  \r
-  ARM_MPU_ClrRegionEx(MPU_NS, rnr);\r
-}\r
-#endif\r
-\r
-/** Configure the given MPU region of the given MPU.\r
-* \param mpu Pointer to MPU to be used.\r
-* \param rnr Region number to be configured.\r
-* \param rbar Value for RBAR register.\r
-* \param rlar Value for RLAR register.\r
-*/   \r
-__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
-{\r
-  mpu->RNR = rnr;\r
-  mpu->RBAR = rbar;\r
-  mpu->RLAR = rlar;\r
-}\r
-\r
-/** Configure the given MPU region.\r
-* \param rnr Region number to be configured.\r
-* \param rbar Value for RBAR register.\r
-* \param rlar Value for RLAR register.\r
-*/   \r
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
-{\r
-  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\r
-}\r
-\r
-#ifdef MPU_NS\r
-/** Configure the given Non-secure MPU region.\r
-* \param rnr Region number to be configured.\r
-* \param rbar Value for RBAR register.\r
-* \param rlar Value for RLAR register.\r
-*/   \r
-__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
-{\r
-  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  \r
-}\r
-#endif\r
-\r
-/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
-* \param dst Destination data is copied to.\r
-* \param src Source data is copied from.\r
-* \param len Amount of data words to be copied.\r
-*/\r
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
-{\r
-  uint32_t i;\r
-  for (i = 0U; i < len; ++i) \r
-  {\r
-    dst[i] = src[i];\r
-  }\r
-}\r
-\r
-/** Load the given number of MPU regions from a table to the given MPU.\r
-* \param mpu Pointer to the MPU registers to be used.\r
-* \param rnr First region number to be configured.\r
-* \param table Pointer to the MPU configuration table.\r
-* \param cnt Amount of regions to be configured.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
-{\r
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
-  if (cnt == 1U) {\r
-    mpu->RNR = rnr;\r
-    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
-  } else {\r
-    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\r
-    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r
-    \r
-    mpu->RNR = rnrBase;\r
-    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r
-      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r
-      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
-      table += c;\r
-      cnt -= c;\r
-      rnrOffset = 0U;\r
-      rnrBase += MPU_TYPE_RALIASES;\r
-      mpu->RNR = rnrBase;\r
-    }\r
-    \r
-    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
-  }\r
-}\r
-\r
-/** Load the given number of MPU regions from a table.\r
-* \param rnr First region number to be configured.\r
-* \param table Pointer to the MPU configuration table.\r
-* \param cnt Amount of regions to be configured.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
-{\r
-  ARM_MPU_LoadEx(MPU, rnr, table, cnt);\r
-}\r
-\r
-#ifdef MPU_NS\r
-/** Load the given number of MPU regions from a table to the Non-secure MPU.\r
-* \param rnr First region number to be configured.\r
-* \param table Pointer to the MPU configuration table.\r
-* \param cnt Amount of regions to be configured.\r
-*/\r
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
-{\r
-  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\r
-}\r
-#endif\r
-\r
-#endif\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/tz_context.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/CMSIS/Include/tz_context.h
deleted file mode 100644 (file)
index d4c1474..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
-/******************************************************************************\r
- * @file     tz_context.h\r
- * @brief    Context Management for Armv8-M TrustZone\r
- * @version  V1.0.1\r
- * @date     10. January 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if   defined ( __ICCARM__ )\r
-  #pragma system_include         /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
-  #pragma clang system_header   /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef TZ_CONTEXT_H\r
-#define TZ_CONTEXT_H\r
\r
-#include <stdint.h>\r
\r
-#ifndef TZ_MODULEID_T\r
-#define TZ_MODULEID_T\r
-/// \details Data type that identifies secure software modules called by a process.\r
-typedef uint32_t TZ_ModuleId_t;\r
-#endif\r
\r
-/// \details TZ Memory ID identifies an allocated memory slot.\r
-typedef uint32_t TZ_MemoryId_t;\r
-  \r
-/// Initialize secure context memory system\r
-/// \return execution status (1: success, 0: error)\r
-uint32_t TZ_InitContextSystem_S (void);\r
\r
-/// Allocate context memory for calling secure software modules in TrustZone\r
-/// \param[in]  module   identifies software modules called from non-secure mode\r
-/// \return value != 0 id TrustZone memory slot identifier\r
-/// \return value 0    no memory available or internal error\r
-TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\r
\r
-/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S\r
-/// \param[in]  id  TrustZone memory slot identifier\r
-/// \return execution status (1: success, 0: error)\r
-uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\r
\r
-/// Load secure context (called on RTOS thread context switch)\r
-/// \param[in]  id  TrustZone memory slot identifier\r
-/// \return execution status (1: success, 0: error)\r
-uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\r
\r
-/// Store secure context (called on RTOS thread context switch)\r
-/// \param[in]  id  TrustZone memory slot identifier\r
-/// \return execution status (1: success, 0: error)\r
-uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\r
\r
-#endif  // TZ_CONTEXT_H\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644 (file)
index 359e92f..0000000
+++ /dev/null
@@ -1,3533 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32_hal_legacy.h\r
-  * @author  MCD Application Team\r
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants\r
-  *          macros and functions maintained for legacy purpose.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32_HAL_LEGACY\r
-#define STM32_HAL_LEGACY\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR\r
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR\r
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF\r
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR\r
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B\r
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B\r
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B\r
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B\r
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN\r
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED\r
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV\r
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV\r
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV\r
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP\r
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP\r
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP\r
-#define AWD_EVENT                       ADC_AWD_EVENT\r
-#define AWD1_EVENT                      ADC_AWD1_EVENT\r
-#define AWD2_EVENT                      ADC_AWD2_EVENT\r
-#define AWD3_EVENT                      ADC_AWD3_EVENT\r
-#define OVR_EVENT                       ADC_OVR_EVENT\r
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT\r
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS\r
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS\r
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS\r
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR\r
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8\r
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO\r
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2\r
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO\r
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4\r
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO\r
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11\r
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1\r
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE\r
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING\r
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING\r
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5\r
-\r
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY\r
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY\r
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC\r
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC\r
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL\r
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL\r
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1\r
-\r
-#if defined(STM32H7)\r
-#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT\r
-#endif /* STM32H7 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE\r
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE\r
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1\r
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2\r
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3\r
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4\r
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5\r
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6\r
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7\r
-#if defined(STM32L0)\r
-#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */\r
-#endif\r
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR\r
-#if defined(STM32F373xC) || defined(STM32F378xx)\r
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1\r
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR\r
-#endif /* STM32F373xC || STM32F378xx */\r
-\r
-#if defined(STM32L0) || defined(STM32L4)\r
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r
-\r
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1\r
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2\r
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3\r
-#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4\r
-#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5\r
-#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6\r
-\r
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT\r
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT\r
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT\r
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT\r
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1\r
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2\r
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1\r
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2\r
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1\r
-#if defined(STM32L0)\r
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */\r
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */\r
-/* to the second dedicated IO (only for COMP2).                               */\r
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2\r
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2\r
-#else\r
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2\r
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3\r
-#endif\r
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4\r
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5\r
-\r
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW\r
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH\r
-\r
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */\r
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */\r
-#if defined(COMP_CSR_LOCK)\r
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK\r
-#elif defined(COMP_CSR_COMP1LOCK)\r
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK\r
-#elif defined(COMP_CSR_COMPxLOCK)\r
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK\r
-#endif\r
-\r
-#if defined(STM32L4)\r
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1\r
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1\r
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1\r
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2\r
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2\r
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2\r
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE\r
-#endif\r
-\r
-#if defined(STM32L0)\r
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED\r
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER\r
-#else\r
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED\r
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED\r
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER\r
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER\r
-#endif\r
-\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE\r
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1\r
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2\r
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1\r
-#define DAC_WAVE_NONE                                   0x00000000U\r
-#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0\r
-#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1\r
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE\r
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE\r
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE\r
-\r
-#if defined(STM32G4)\r
-#define DAC_CHIPCONNECT_DISABLE       (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)\r
-#define DAC_CHIPCONNECT_ENABLE        (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)\r
-#endif\r
-\r
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5)\r
-#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID\r
-#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2\r
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4\r
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5\r
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4\r
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2\r
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32\r
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6\r
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7\r
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67\r
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67\r
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76\r
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6\r
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7\r
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6\r
-\r
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP\r
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE\r
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE\r
-\r
-#if defined(STM32L4)\r
-\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT\r
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE\r
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT\r
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT\r
-\r
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT\r
-#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING\r
-#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING\r
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
-\r
-#endif /* STM32L4 */\r
-\r
-#if defined(STM32H7)\r
-\r
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1\r
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2\r
-\r
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX\r
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX\r
-\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT\r
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0\r
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO\r
-\r
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT\r
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT\r
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP\r
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0\r
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2\r
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT\r
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT\r
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT\r
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT\r
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT\r
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT\r
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT\r
-\r
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT\r
-#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING\r
-#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING\r
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
-\r
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT\r
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT\r
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT\r
-\r
-#endif /* STM32H7 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE\r
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD\r
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD\r
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD\r
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS\r
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES\r
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES\r
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE\r
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE\r
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE\r
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE\r
-#define OBEX_PCROP                    OPTIONBYTE_PCROP\r
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG\r
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE\r
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE\r
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE\r
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD\r
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD\r
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE\r
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD\r
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD\r
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE\r
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD\r
-#define PAGESIZE                      FLASH_PAGE_SIZE\r
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE\r
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD\r
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD\r
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1\r
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2\r
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3\r
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4\r
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST\r
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST\r
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA\r
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB\r
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA\r
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB\r
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE\r
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN\r
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE\r
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN\r
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE\r
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD\r
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG\r
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS\r
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP\r
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV\r
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR\r
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG\r
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION\r
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA\r
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE\r
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE\r
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS\r
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS\r
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST\r
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR\r
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO\r
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION\r
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS\r
-#define OB_WDG_SW                     OB_IWDG_SW\r
-#define OB_WDG_HW                     OB_IWDG_HW\r
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET\r
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET\r
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET\r
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET\r
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR\r
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0\r
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1\r
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2\r
-#if defined(STM32G0)\r
-#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE\r
-#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH\r
-#else\r
-#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE\r
-#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE\r
-#endif\r
-#if defined(STM32H7)\r
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1\r
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1\r
-#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1\r
-#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2\r
-#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2\r
-#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#if defined(STM32H7)\r
-#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE\r
-#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE\r
-#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET\r
-#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET\r
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE\r
-#endif /* STM32H7 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3\r
-#if defined(STM32G4)\r
-\r
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster\r
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster\r
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD\r
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD\r
-#endif /* STM32G4 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
-  * @{\r
-  */\r
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)\r
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE\r
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE\r
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8\r
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16\r
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)\r
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef\r
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX\r
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX\r
-\r
-#if defined(STM32F4)\r
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO\r
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO\r
-#endif\r
-\r
-#if defined(STM32F7)\r
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r
-#endif\r
-\r
-#if defined(STM32L4)\r
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r
-#endif\r
-\r
-#if defined(STM32H7)\r
-#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1\r
-#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1\r
-#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1\r
-#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2\r
-#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2\r
-#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2\r
-#endif\r
-\r
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1\r
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1\r
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1\r
-\r
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)\r
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW\r
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM\r
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH\r
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH\r
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/\r
-\r
-#if defined(STM32L1)\r
- #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW\r
- #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM\r
- #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH\r
- #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH\r
-#endif /* STM32L1 */\r
-\r
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r
- #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW\r
- #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
- #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH\r
-#endif /* STM32F0 || STM32F3 || STM32F1 */\r
-\r
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r
-\r
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER\r
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER\r
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD\r
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD\r
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE\r
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE\r
-\r
-#if defined(STM32G4)\r
-#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig\r
-#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable\r
-#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable\r
-#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset\r
-#endif /* STM32G4 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE\r
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE\r
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE\r
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE\r
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE\r
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE\r
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE\r
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE\r
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX\r
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX\r
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX\r
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX\r
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX\r
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE\r
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD\r
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE\r
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE\r
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
-\r
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING\r
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING\r
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING\r
-\r
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
-\r
-/* The following 3 definition have also been present in a temporary version of lptim.h */\r
-/* They need to be renamed also to the right name, just in case */\r
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b\r
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b\r
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b\r
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b\r
-\r
-#define NAND_AddressTypedef             NAND_AddressTypeDef\r
-\r
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS\r
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE\r
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE\r
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE\r
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef\r
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS\r
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING\r
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR\r
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT\r
-\r
-#define __NOR_WRITE                    NOR_WRITE\r
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0\r
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1\r
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2\r
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3\r
-\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3\r
-\r
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0\r
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1\r
-\r
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0\r
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1\r
-\r
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0\r
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1\r
-\r
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1\r
-\r
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO\r
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0\r
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1\r
-\r
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5)\r
-#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID\r
-#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID\r
-#endif\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS\r
-\r
-#if defined(STM32H7)\r
-  #define I2S_IT_TXE               I2S_IT_TXP\r
-  #define I2S_IT_RXNE              I2S_IT_RXP\r
-\r
-  #define I2S_FLAG_TXE             I2S_FLAG_TXP\r
-  #define I2S_FLAG_RXNE            I2S_FLAG_RXP\r
-#endif\r
-\r
-#if defined(STM32F7)\r
-  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-/* Compact Flash-ATA registers description */\r
-#define CF_DATA                       ATA_DATA\r
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT\r
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER\r
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW\r
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH\r
-#define CF_CARD_HEAD                  ATA_CARD_HEAD\r
-#define CF_STATUS_CMD                 ATA_STATUS_CMD\r
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE\r
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA\r
-\r
-/* Compact Flash-ATA commands */\r
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD\r
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD\r
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD\r
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD\r
-\r
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef\r
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS\r
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING\r
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR\r
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define FORMAT_BIN                  RTC_FORMAT_BIN\r
-#define FORMAT_BCD                  RTC_FORMAT_BCD\r
-\r
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE\r
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE\r
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE\r
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE\r
-\r
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE\r
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE\r
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE\r
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT\r
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT\r
-\r
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT\r
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1\r
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2\r
-\r
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE\r
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1\r
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1\r
-\r
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT\r
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1\r
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE\r
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE\r
-\r
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
-\r
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE\r
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE\r
-\r
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE\r
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE\r
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE\r
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE\r
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE\r
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE\r
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE\r
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE\r
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE\r
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE\r
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE\r
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE\r
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE\r
-\r
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE\r
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE\r
-\r
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE\r
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE\r
-\r
-#if defined(STM32H7)\r
-\r
- #define SPI_FLAG_TXE                    SPI_FLAG_TXP\r
- #define SPI_FLAG_RXNE                   SPI_FLAG_RXP\r
-\r
- #define SPI_IT_TXE                      SPI_IT_TXP\r
- #define SPI_IT_RXNE                     SPI_IT_RXP\r
-\r
- #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET\r
- #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET\r
- #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET\r
- #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET\r
-\r
-#endif /* STM32H7 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK\r
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK\r
-\r
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1\r
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2\r
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR\r
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER\r
-#define TIM_DMABase_SR                   TIM_DMABASE_SR\r
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR\r
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1\r
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2\r
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER\r
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT\r
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC\r
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR\r
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR\r
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1\r
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2\r
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3\r
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4\r
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR\r
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR\r
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR\r
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1\r
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3\r
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5\r
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6\r
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2\r
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3\r
-#define TIM_DMABase_OR                   TIM_DMABASE_OR\r
-\r
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE\r
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1\r
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2\r
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3\r
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4\r
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM\r
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER\r
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK\r
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2\r
-\r
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER\r
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS\r
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS\r
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS\r
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS\r
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS\r
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS\r
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS\r
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS\r
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS\r
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS\r
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS\r
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS\r
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS\r
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS\r
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS\r
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS\r
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS\r
-\r
-#if defined(STM32L0)\r
-#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO\r
-#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO\r
-#endif\r
-\r
-#if defined(STM32F3)\r
-#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE\r
-#endif\r
-\r
-#if defined(STM32H7)\r
-#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1\r
-#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2\r
-#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1\r
-#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2\r
-#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1\r
-#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2\r
-#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1\r
-#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1\r
-#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2\r
-#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1\r
-#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2\r
-#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2\r
-#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1\r
-#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2\r
-#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING\r
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE\r
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE\r
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE\r
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE\r
-\r
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
-\r
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16\r
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16\r
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16\r
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16\r
-\r
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8\r
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8\r
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8\r
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8\r
-\r
-#define __DIV_LPUART                    UART_DIV_LPUART\r
-\r
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE\r
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE\r
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE\r
-\r
-#define USARTNACK_ENABLED               USART_NACK_ENABLE\r
-#define USARTNACK_DISABLED              USART_NACK_DISABLE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define CFR_BASE                    WWDG_CFR_BASE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0\r
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1\r
-#define CAN_IT_RQCP0                CAN_IT_TME\r
-#define CAN_IT_RQCP1                CAN_IT_TME\r
-#define CAN_IT_RQCP2                CAN_IT_TME\r
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE\r
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE\r
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)\r
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)\r
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define VLAN_TAG                ETH_VLAN_TAG\r
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD\r
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD\r
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD\r
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK\r
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK\r
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK\r
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK\r
-\r
-#define ETH_MMCCR              0x00000100U\r
-#define ETH_MMCRIR             0x00000104U\r
-#define ETH_MMCTIR             0x00000108U\r
-#define ETH_MMCRIMR            0x0000010CU\r
-#define ETH_MMCTIMR            0x00000110U\r
-#define ETH_MMCTGFSCCR         0x0000014CU\r
-#define ETH_MMCTGFMSCCR        0x00000150U\r
-#define ETH_MMCTGFCR           0x00000168U\r
-#define ETH_MMCRFCECR          0x00000194U\r
-#define ETH_MMCRFAECR          0x00000198U\r
-#define ETH_MMCRGUFCR          0x000001C4U\r
-\r
-#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */\r
-#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */\r
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */\r
-#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */\r
-#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
-#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
-#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
-#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */\r
-#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */\r
-#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */\r
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
-#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */\r
-#if defined(STM32F1)\r
-#else\r
-#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */\r
-#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */\r
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
-#endif\r
-#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */\r
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */\r
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */\r
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */\r
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */\r
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */\r
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR\r
-#define DCMI_IT_OVF             DCMI_IT_OVR\r
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI\r
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI\r
-\r
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop\r
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop\r
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \\r
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \\r
-  || defined(STM32H7)\r
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888\r
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888\r
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565\r
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555\r
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444\r
-\r
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888\r
-#define CM_RGB888               DMA2D_INPUT_RGB888\r
-#define CM_RGB565               DMA2D_INPUT_RGB565\r
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555\r
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444\r
-#define CM_L8                   DMA2D_INPUT_L8\r
-#define CM_AL44                 DMA2D_INPUT_AL44\r
-#define CM_AL88                 DMA2D_INPUT_AL88\r
-#define CM_L4                   DMA2D_INPUT_L4\r
-#define CM_A8                   DMA2D_INPUT_A8\r
-#define CM_A4                   DMA2D_INPUT_A4\r
-/**\r
-  * @}\r
-  */\r
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */\r
-\r
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef\r
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef\r
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish\r
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish\r
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish\r
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish\r
-\r
-/*HASH Algorithm Selection*/\r
-\r
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1\r
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224\r
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256\r
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5\r
-\r
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH\r
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC\r
-\r
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY\r
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect\r
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
-#if defined(STM32L0)\r
-#else\r
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
-#endif\r
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram\r
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown\r
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown\r
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock\r
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock\r
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase\r
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program\r
-\r
- /**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter\r
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter\r
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter\r
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter\r
-\r
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
-\r
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)\r
-#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT\r
-#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT\r
-#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT\r
-#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT\r
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA\r
-#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA\r
-#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA\r
-#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA\r
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */\r
-\r
-#if defined(STM32F4)\r
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT\r
-#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT\r
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT\r
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT\r
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA\r
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA\r
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA\r
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA\r
-#endif /* STM32F4 */\r
- /**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD\r
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg\r
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown\r
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor\r
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg\r
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown\r
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor\r
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler\r
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD\r
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler\r
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback\r
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive\r
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive\r
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC\r
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC\r
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM\r
-\r
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL\r
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING\r
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING\r
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING\r
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING\r
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING\r
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING\r
-\r
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB\r
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB\r
-#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER\r
-#define CR_PMODE_BB                                   CR_VOS_BB\r
-\r
-#define DBP_BitNumber                                 DBP_BIT_NUMBER\r
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER\r
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER\r
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER\r
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER\r
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER\r
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER\r
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER\r
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER\r
-#define BRE_BitNumber                                 BRE_BIT_NUMBER\r
-\r
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL\r
-\r
- /**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT\r
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback\r
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt\r
-#define HAL_TIM_DMAError                                TIM_DMAError\r
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt\r
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt\r
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)\r
-#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro\r
-#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT\r
-#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback\r
-#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent\r
-#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT\r
-#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA\r
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4  || STM32L0 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r
-#define HAL_LTDC_Relaod           HAL_LTDC_Reload\r
-#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig\r
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros ------------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define AES_IT_CC                      CRYP_IT_CC\r
-#define AES_IT_ERR                     CRYP_IT_ERR\r
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE\r
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH\r
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM\r
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC\r
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM\r
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC\r
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK\r
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG\r
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG\r
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE\r
-\r
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY\r
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48\r
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS\r
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER\r
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE\r
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE\r
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS\r
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS\r
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE\r
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE\r
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR\r
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING\r
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE\r
-\r
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION\r
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK\r
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT\r
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR\r
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION\r
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE\r
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM\r
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT\r
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS\r
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN\r
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ\r
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET\r
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET\r
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL\r
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL\r
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET\r
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET\r
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD\r
-\r
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION\r
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER\r
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI\r
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE\r
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE\r
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER\r
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE\r
-\r
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT\r
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT\r
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL\r
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM\r
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET\r
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE\r
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE\r
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER\r
-\r
-#define __HAL_ADC_SQR1                                   ADC_SQR1\r
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1\r
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2\r
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK\r
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK\r
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK\r
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS\r
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS\r
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV\r
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection\r
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq\r
-#define __HAL_ADC_JSQR                                   ADC_JSQR\r
-\r
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL\r
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF\r
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT\r
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS\r
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN\r
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR\r
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT\r
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT\r
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT\r
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
-\r
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
-\r
-\r
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
-#if defined(STM32H7)\r
-  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1\r
-  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1\r
-  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1\r
-  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1\r
-#else\r
-  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
-  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
-  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
-  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
-#endif /* STM32H7 */\r
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#if defined(STM32F3)\r
-#define COMP_START                                       __HAL_COMP_ENABLE\r
-#define COMP_STOP                                        __HAL_COMP_DISABLE\r
-#define COMP_LOCK                                        __HAL_COMP_LOCK\r
-\r
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
-# endif\r
-# if defined(STM32F302xE) || defined(STM32F302xC)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
-# endif\r
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\r
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\r
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\r
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r
-# endif\r
-# if defined(STM32F373xC) ||defined(STM32F378xx)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
-# endif\r
-#else\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
-#endif\r
-\r
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE\r
-\r
-#if defined(STM32L0) || defined(STM32L4)\r
-/* Note: On these STM32 families, the only argument of this macro             */\r
-/*       is COMP_FLAG_LOCK.                                                   */\r
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */\r
-/*       argument.                                                            */\r
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(STM32L0) || defined(STM32L4)\r
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
-/**\r
-  * @}\r
-  */\r
-#endif\r
-\r
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
-                          ((WAVE) == DAC_WAVE_NOISE)|| \\r
-                          ((WAVE) == DAC_WAVE_TRIANGLE))\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define IS_WRPAREA          IS_OB_WRPAREA\r
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM\r
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE\r
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS\r
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2\r
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START\r
-#if defined(STM32F1)\r
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE\r
-#else\r
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE\r
-#endif /* STM32F1 */\r
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME\r
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD\r
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST\r
-#define __HAL_I2C_SPEED                 I2C_SPEED\r
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE\r
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ\r
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS\r
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE\r
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ\r
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB\r
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB\r
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE\r
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT\r
-\r
-#if defined(STM32H7)\r
-  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE\r
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE\r
-\r
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE\r
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION\r
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE\r
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION\r
-\r
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS\r
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT\r
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT\r
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD\r
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX\r
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX\r
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX\r
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX\r
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L\r
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H\r
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM\r
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES\r
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX\r
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT\r
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION\r
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE\r
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE\r
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine\r
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine\r
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig\r
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig\r
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention\r
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention\r
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2\r
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2\r
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB\r
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB\r
-\r
-#if defined (STM32F4)\r
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()\r
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
-#else\r
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT\r
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT\r
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG\r
-#endif /* STM32F4 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI\r
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI\r
-\r
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
-\r
-#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE\r
-#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE\r
-#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
-#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
-#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET\r
-#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET\r
-#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE\r
-#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE\r
-#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET\r
-#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET\r
-#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE\r
-#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE\r
-#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE\r
-#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE\r
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE\r
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE\r
-#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET\r
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET\r
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE\r
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE\r
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET\r
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET\r
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE\r
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE\r
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET\r
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET\r
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE\r
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE\r
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET\r
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET\r
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE\r
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE\r
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET\r
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET\r
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
-\r
-#if defined(STM32WB)\r
-#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE\r
-#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE\r
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET\r
-#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET\r
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED\r
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED\r
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED\r
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED\r
-#define QSPI_IRQHandler QUADSPI_IRQHandler\r
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */\r
-\r
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
-#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE\r
-#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE\r
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
-#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET\r
-#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET\r
-#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE\r
-#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE\r
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
-#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET\r
-#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET\r
-#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE\r
-#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE\r
-#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET\r
-#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET\r
-#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE\r
-#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE\r
-#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET\r
-#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET\r
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE\r
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE\r
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET\r
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
-\r
-#if defined(STM32H7)\r
-#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE\r
-#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE\r
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE\r
-\r
-#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/\r
-#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/\r
-\r
-\r
-#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED\r
-#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED\r
-#endif\r
-\r
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
-\r
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE\r
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE\r
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET\r
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET\r
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE\r
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE\r
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET\r
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET\r
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
-\r
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE\r
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE\r
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE\r
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE\r
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE\r
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE\r
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET\r
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET\r
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE\r
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE\r
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE\r
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET\r
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET\r
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE\r
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE\r
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE\r
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET\r
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET\r
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE\r
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE\r
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE\r
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET\r
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET\r
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE\r
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE\r
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE\r
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE\r
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE\r
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE\r
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE\r
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE\r
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE\r
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE\r
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE\r
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE\r
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE\r
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET\r
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET\r
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE\r
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE\r
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE\r
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET\r
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET\r
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE\r
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE\r
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE\r
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET\r
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET\r
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE\r
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE\r
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE\r
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET\r
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET\r
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE\r
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE\r
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE\r
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET\r
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE\r
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE\r
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE\r
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE\r
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE\r
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET\r
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET\r
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE\r
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE\r
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE\r
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET\r
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET\r
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE\r
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE\r
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE\r
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET\r
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET\r
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE\r
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED\r
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE\r
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE\r
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE\r
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE\r
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE\r
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET\r
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET\r
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE\r
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET\r
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET\r
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE\r
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE\r
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET\r
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET\r
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
-\r
-/* alias define maintained for legacy */\r
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
-\r
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE\r
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE\r
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE\r
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE\r
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE\r
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE\r
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE\r
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE\r
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE\r
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE\r
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE\r
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE\r
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE\r
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE\r
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE\r
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE\r
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE\r
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE\r
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE\r
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE\r
-\r
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET\r
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET\r
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET\r
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET\r
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET\r
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET\r
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET\r
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET\r
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET\r
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET\r
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET\r
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET\r
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET\r
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET\r
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET\r
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET\r
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET\r
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET\r
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET\r
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET\r
-\r
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED\r
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED\r
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED\r
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED\r
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED\r
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED\r
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED\r
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED\r
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED\r
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED\r
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED\r
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED\r
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED\r
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED\r
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED\r
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED\r
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED\r
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED\r
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED\r
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED\r
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED\r
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED\r
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED\r
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED\r
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED\r
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED\r
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED\r
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED\r
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED\r
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED\r
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED\r
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED\r
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED\r
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED\r
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED\r
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED\r
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED\r
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED\r
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED\r
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED\r
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED\r
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED\r
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED\r
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED\r
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED\r
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED\r
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED\r
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED\r
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED\r
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED\r
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED\r
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED\r
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED\r
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED\r
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED\r
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED\r
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED\r
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED\r
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED\r
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED\r
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED\r
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED\r
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED\r
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED\r
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED\r
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED\r
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED\r
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED\r
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED\r
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED\r
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED\r
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED\r
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED\r
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED\r
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED\r
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED\r
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED\r
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED\r
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED\r
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED\r
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED\r
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED\r
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED\r
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED\r
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED\r
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED\r
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED\r
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED\r
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED\r
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED\r
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED\r
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED\r
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED\r
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED\r
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED\r
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED\r
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED\r
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED\r
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED\r
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED\r
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED\r
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED\r
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED\r
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED\r
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED\r
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED\r
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED\r
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED\r
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED\r
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED\r
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED\r
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED\r
-\r
-#if defined(STM32L1)\r
-#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE\r
-#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE\r
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET\r
-#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET\r
-#endif /* STM32L1 */\r
-\r
-#if defined(STM32F4)\r
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET\r
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE\r
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE\r
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED\r
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED\r
-#define Sdmmc1ClockSelection               SdioClockSelection\r
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO\r
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48\r
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK\r
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG\r
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE\r
-#endif\r
-\r
-#if defined(STM32F7) || defined(STM32L4)\r
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET\r
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET\r
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE\r
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE\r
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r
-#define SdioClockSelection                 Sdmmc1ClockSelection\r
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1\r
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG\r
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE\r
-#endif\r
-\r
-#if defined(STM32F7)\r
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48\r
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK\r
-#endif\r
-\r
-#if defined(STM32H7)\r
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()\r
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()\r
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()\r
-\r
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()\r
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()\r
-#endif\r
-\r
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG\r
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG\r
-\r
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE\r
-\r
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE\r
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE\r
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK\r
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK\r
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK\r
-\r
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY\r
-\r
-#define RCC_IT_CSSLSE               RCC_IT_LSECSS\r
-#define RCC_IT_CSSHSE               RCC_IT_CSS\r
-\r
-#define RCC_PLLMUL_3                RCC_PLL_MUL3\r
-#define RCC_PLLMUL_4                RCC_PLL_MUL4\r
-#define RCC_PLLMUL_6                RCC_PLL_MUL6\r
-#define RCC_PLLMUL_8                RCC_PLL_MUL8\r
-#define RCC_PLLMUL_12               RCC_PLL_MUL12\r
-#define RCC_PLLMUL_16               RCC_PLL_MUL16\r
-#define RCC_PLLMUL_24               RCC_PLL_MUL24\r
-#define RCC_PLLMUL_32               RCC_PLL_MUL32\r
-#define RCC_PLLMUL_48               RCC_PLL_MUL48\r
-\r
-#define RCC_PLLDIV_2                RCC_PLL_DIV2\r
-#define RCC_PLLDIV_3                RCC_PLL_DIV3\r
-#define RCC_PLLDIV_4                RCC_PLL_DIV4\r
-\r
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE\r
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG\r
-#define RCC_MCO_NODIV               RCC_MCODIV_1\r
-#define RCC_MCO_DIV1                RCC_MCODIV_1\r
-#define RCC_MCO_DIV2                RCC_MCODIV_2\r
-#define RCC_MCO_DIV4                RCC_MCODIV_4\r
-#define RCC_MCO_DIV8                RCC_MCODIV_8\r
-#define RCC_MCO_DIV16               RCC_MCODIV_16\r
-#define RCC_MCO_DIV32               RCC_MCODIV_32\r
-#define RCC_MCO_DIV64               RCC_MCODIV_64\r
-#define RCC_MCO_DIV128              RCC_MCODIV_128\r
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK\r
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI\r
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE\r
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK\r
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI\r
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14\r
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48\r
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE\r
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK\r
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK\r
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2\r
-\r
-#if defined(STM32L4)\r
-#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE\r
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)\r
-#else\r
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK\r
-#endif\r
-\r
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1\r
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL\r
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI\r
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL\r
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL\r
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5\r
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2\r
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3\r
-\r
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER\r
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER\r
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER\r
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER\r
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER\r
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER\r
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER\r
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER\r
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER\r
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER\r
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER\r
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER\r
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER\r
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER\r
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER\r
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER\r
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER\r
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER\r
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER\r
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER\r
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER\r
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER\r
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER\r
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER\r
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER\r
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS\r
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS\r
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS\r
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS\r
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE\r
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE\r
-\r
-#define CR_HSION_BB            RCC_CR_HSION_BB\r
-#define CR_CSSON_BB            RCC_CR_CSSON_BB\r
-#define CR_PLLON_BB            RCC_CR_PLLON_BB\r
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB\r
-#define CR_MSION_BB            RCC_CR_MSION_BB\r
-#define CSR_LSION_BB           RCC_CSR_LSION_BB\r
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB\r
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB\r
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB\r
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB\r
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB\r
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB\r
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB\r
-#define CR_HSEON_BB            RCC_CR_HSEON_BB\r
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB\r
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB\r
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB\r
-\r
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r
-\r
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT\r
-\r
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN\r
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF\r
-\r
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48\r
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ\r
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP\r
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ\r
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE\r
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48\r
-\r
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE\r
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE\r
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET\r
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET\r
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r
-#define DfsdmClockSelection         Dfsdm1ClockSelection\r
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1\r
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2\r
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK\r
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG\r
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE\r
-#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2\r
-#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1\r
-#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1\r
-#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1\r
-\r
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1\r
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2\r
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1\r
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2\r
-#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2\r
-#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2\r
-#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)\r
-#else\r
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG\r
-#endif\r
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT\r
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT\r
-\r
-#if defined (STM32F1)\r
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
-\r
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
-\r
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
-\r
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
-\r
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
-#else\r
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
-                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \\r
-                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
-#endif   /* STM32F1 */\r
-\r
-#define IS_ALARM                                  IS_RTC_ALARM\r
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK\r
-#define IS_TAMPER                                 IS_RTC_TAMPER\r
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE\r
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER\r
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT\r
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE\r
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION\r
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE\r
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ\r
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER\r
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK\r
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER\r
-\r
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE\r
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE\r
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS\r
-\r
-#if defined(STM32F4) || defined(STM32F2)\r
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED\r
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY\r
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED\r
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION\r
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND\r
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT\r
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED\r
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE\r
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE\r
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE\r
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL\r
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT\r
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT\r
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG\r
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG\r
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT\r
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT\r
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS\r
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT\r
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND\r
-/* alias CMSIS */\r
-#define  SDMMC1_IRQn                SDIO_IRQn\r
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler\r
-#endif\r
-\r
-#if defined(STM32F7) || defined(STM32L4)\r
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED\r
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY\r
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED\r
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION\r
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND\r
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT\r
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED\r
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE\r
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE\r
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE\r
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE\r
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT\r
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT\r
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG\r
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG\r
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT\r
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT\r
-#define  SDIO_STATIC_FLAGS             SDMMC_STATIC_FLAGS\r
-#define  SDIO_CMD0TIMEOUT                SDMMC_CMD0TIMEOUT\r
-#define  SD_SDIO_SEND_IF_COND        SD_SDMMC_SEND_IF_COND\r
-/* alias CMSIS for compatibilities */\r
-#define  SDIO_IRQn                  SDMMC1_IRQn\r
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler\r
-#endif\r
-\r
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)\r
-#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef\r
-#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef\r
-#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef\r
-#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef\r
-#endif\r
-\r
-#if defined(STM32H7)\r
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback\r
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback\r
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback\r
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback\r
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback\r
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback\r
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback\r
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback\r
-#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT\r
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT\r
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE\r
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE\r
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
-\r
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE\r
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE\r
-\r
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1\r
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2\r
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START\r
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH\r
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR\r
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE\r
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE\r
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX\r
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX\r
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE\r
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION\r
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE\r
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION\r
-\r
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD\r
-\r
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE\r
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT\r
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT\r
-#define __USART_ENABLE                  __HAL_USART_ENABLE\r
-#define __USART_DISABLE                 __HAL_USART_DISABLE\r
-\r
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE\r
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE\r
-\r
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE\r
-\r
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE\r
-\r
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-\r
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
-\r
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
-\r
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup\r
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup\r
-\r
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo\r
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE\r
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
-\r
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE\r
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT\r
-\r
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE\r
-\r
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN\r
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER\r
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER\r
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER\r
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD\r
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD\r
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION\r
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION\r
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER\r
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER\r
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE\r
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE\r
-\r
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
-\r
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE\r
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE\r
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define __HAL_LTDC_LAYER LTDC_LAYER\r
-#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE\r
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE\r
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE\r
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE\r
-#define SAI_STREOMODE                     SAI_STEREOMODE\r
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY\r
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL\r
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL\r
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL\r
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL\r
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL\r
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE\r
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1\r
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#if defined(STM32H7)\r
-#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow\r
-#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT\r
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose\r
-  * @{\r
-  */\r
-#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)\r
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT\r
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA\r
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart\r
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT\r
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA\r
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-#if defined (STM32L4)\r
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32_HAL_LEGACY */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h
deleted file mode 100644 (file)
index b0eca91..0000000
+++ /dev/null
@@ -1,701 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal.h\r
-  * @author  MCD Application Team\r
-  * @brief   This file contains all the functions prototypes for the HAL\r
-  *          module driver.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_H\r
-#define STM32L4xx_HAL_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_conf.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup HAL\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Exported_Constants HAL Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup HAL_TICK_FREQ Tick Frequency\r
-  * @{\r
-  */\r
-#define  HAL_TICK_FREQ_10HZ         100U\r
-#define  HAL_TICK_FREQ_100HZ        10U\r
-#define  HAL_TICK_FREQ_1KHZ         1U\r
-#define  HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup SYSCFG_BootMode Boot Mode\r
-  * @{\r
-  */\r
-#define SYSCFG_BOOT_MAINFLASH          0U\r
-#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
-       /* STM32L496xx || STM32L4A6xx || */\r
-       /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define SYSCFG_BOOT_OCTOPSPI1          (SYSCFG_MEMRMP_MEM_MODE_2)\r
-#define SYSCFG_BOOT_OCTOPSPI2          (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0)\r
-#else\r
-#define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts\r
-  * @{\r
-  */\r
-#define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */\r
-#define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */\r
-#define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */\r
-#define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */\r
-#define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */\r
-#define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)\r
-  * @{\r
-  */\r
-#define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */\r
-#define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */\r
-#define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */\r
-#define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */\r
-#define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */\r
-#define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */\r
-#define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */\r
-#define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */\r
-#define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */\r
-#define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */\r
-#define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */\r
-#define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */\r
-#define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */\r
-#define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */\r
-#define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */\r
-#define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */\r
-#if defined(SYSCFG_SWPR_PAGE31)\r
-#define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */\r
-#define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */\r
-#define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */\r
-#define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */\r
-#define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */\r
-#define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */\r
-#define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */\r
-#define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */\r
-#define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */\r
-#define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */\r
-#define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */\r
-#define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */\r
-#define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */\r
-#define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */\r
-#define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */\r
-#define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */\r
-#endif /* SYSCFG_SWPR_PAGE31 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(SYSCFG_SWPR2_PAGE63)\r
-/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)\r
-  * @{\r
-  */\r
-#define SYSCFG_SRAM2WRP_PAGE32         SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */\r
-#define SYSCFG_SRAM2WRP_PAGE33         SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */\r
-#define SYSCFG_SRAM2WRP_PAGE34         SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */\r
-#define SYSCFG_SRAM2WRP_PAGE35         SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */\r
-#define SYSCFG_SRAM2WRP_PAGE36         SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */\r
-#define SYSCFG_SRAM2WRP_PAGE37         SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */\r
-#define SYSCFG_SRAM2WRP_PAGE38         SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */\r
-#define SYSCFG_SRAM2WRP_PAGE39         SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */\r
-#define SYSCFG_SRAM2WRP_PAGE40         SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */\r
-#define SYSCFG_SRAM2WRP_PAGE41         SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */\r
-#define SYSCFG_SRAM2WRP_PAGE42         SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */\r
-#define SYSCFG_SRAM2WRP_PAGE43         SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */\r
-#define SYSCFG_SRAM2WRP_PAGE44         SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */\r
-#define SYSCFG_SRAM2WRP_PAGE45         SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */\r
-#define SYSCFG_SRAM2WRP_PAGE46         SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */\r
-#define SYSCFG_SRAM2WRP_PAGE47         SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */\r
-#define SYSCFG_SRAM2WRP_PAGE48         SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */\r
-#define SYSCFG_SRAM2WRP_PAGE49         SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */\r
-#define SYSCFG_SRAM2WRP_PAGE50         SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */\r
-#define SYSCFG_SRAM2WRP_PAGE51         SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */\r
-#define SYSCFG_SRAM2WRP_PAGE52         SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */\r
-#define SYSCFG_SRAM2WRP_PAGE53         SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */\r
-#define SYSCFG_SRAM2WRP_PAGE54         SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */\r
-#define SYSCFG_SRAM2WRP_PAGE55         SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */\r
-#define SYSCFG_SRAM2WRP_PAGE56         SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */\r
-#define SYSCFG_SRAM2WRP_PAGE57         SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */\r
-#define SYSCFG_SRAM2WRP_PAGE58         SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */\r
-#define SYSCFG_SRAM2WRP_PAGE59         SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */\r
-#define SYSCFG_SRAM2WRP_PAGE60         SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */\r
-#define SYSCFG_SRAM2WRP_PAGE61         SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */\r
-#define SYSCFG_SRAM2WRP_PAGE62         SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */\r
-#define SYSCFG_SRAM2WRP_PAGE63         SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* SYSCFG_SWPR2_PAGE63 */\r
-\r
-#if defined(VREFBUF)\r
-/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale\r
-  * @{\r
-  */\r
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0U               /*!< Voltage reference scale 0 (VREF_OUT1) */\r
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS  /*!< Voltage reference scale 1 (VREF_OUT2) */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance\r
-  * @{\r
-  */\r
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0U               /*!< VREF_plus pin is internally connected to Voltage reference buffer output */\r
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ  /*!< VREF_plus pin is high impedance */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* VREFBUF */\r
-\r
-/** @defgroup SYSCFG_flags_definition Flags\r
-  * @{\r
-  */\r
-\r
-#define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */\r
-#define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO\r
-  * @{\r
-  */\r
-\r
-/** @brief  Fast-mode Plus driving capability on a specific GPIO\r
-  */\r
-#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */\r
-#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */\r
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)\r
-#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */\r
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */\r
-#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)\r
-#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */\r
-#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-\r
-/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Freeze/Unfreeze Peripherals in Debug mode\r
-  */\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
-#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
-#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
-#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
-#define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_CAN2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_CAN2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
-#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Main Flash memory mapped at 0x00000000.\r
-  */\r
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
-\r
-/** @brief  System Flash memory mapped at 0x00000000.\r
-  */\r
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)\r
-\r
-/** @brief  Embedded SRAM mapped at 0x00000000.\r
-  */\r
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-\r
-/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.\r
-  */\r
-#define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
-       /* STM32L496xx || STM32L4A6xx || */\r
-       /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-\r
-/** @brief  OCTOSPI mapped at 0x00000000.\r
-  */\r
-#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1()    MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2))\r
-#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2()    MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0))\r
-\r
-#else\r
-\r
-/** @brief  QUADSPI mapped at 0x00000000.\r
-  */\r
-#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
-  * @brief  Return the boot mode as configured by user.\r
-  * @retval The boot mode as configured by user. The returned value can be one\r
-  *         of the following values:\r
-  *           @arg @ref SYSCFG_BOOT_MAINFLASH\r
-  *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH\r
-  @if STM32L486xx\r
-  *           @arg @ref SYSCFG_BOOT_FMC\r
-  @endif\r
-  *           @arg @ref SYSCFG_BOOT_SRAM\r
-  *           @arg @ref SYSCFG_BOOT_QUADSPI\r
-  */\r
-#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
-\r
-/** @brief  SRAM2 page 0 to 31 write protection enable macro\r
-  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP\r
-  * @note   Write protection can only be disabled by a system reset\r
-  */\r
-#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\\r
-                                                                SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\\r
-                                                            }while(0)\r
-\r
-#if defined(SYSCFG_SWPR2_PAGE63)\r
-/** @brief  SRAM2 page 32 to 63 write protection enable macro\r
-  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63\r
-  * @note   Write protection can only be disabled by a system reset\r
-  */\r
-#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\\r
-                                                                SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\\r
-                                                            }while(0)\r
-#endif /* SYSCFG_SWPR2_PAGE63 */\r
-\r
-/** @brief  SRAM2 page write protection unlock prior to erase\r
-  * @note   Writing a wrong key reactivates the write protection\r
-  */\r
-#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\\r
-                                                 SYSCFG->SKR = 0x53;\\r
-                                                }while(0)\r
-\r
-/** @brief  SRAM2 erase\r
-  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase\r
-  */\r
-#define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)\r
-\r
-/** @brief  Floating Point Unit interrupt enable/disable macros\r
-  * @param __INTERRUPT__  This parameter can be a value of @ref SYSCFG_FPU_Interrupts\r
-  */\r
-#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\\r
-                                                                SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\\r
-                                                            }while(0)\r
-\r
-#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\\r
-                                                                CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\\r
-                                                            }while(0)\r
-\r
-/** @brief  SYSCFG Break ECC lock.\r
-  *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.\r
-  * @note   The selected configuration is locked and can be unlocked only by system reset.\r
-  */\r
-#define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)\r
-\r
-/** @brief  SYSCFG Break Cortex-M4 Lockup lock.\r
-  *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.\r
-  * @note   The selected configuration is locked and can be unlocked only by system reset.\r
-  */\r
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)\r
-\r
-/** @brief  SYSCFG Break PVD lock.\r
-  *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.\r
-  * @note   The selected configuration is locked and can be unlocked only by system reset.\r
-  */\r
-#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)\r
-\r
-/** @brief  SYSCFG Break SRAM2 parity lock.\r
-  *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.\r
-  * @note   The selected configuration is locked and can be unlocked by system reset.\r
-  */\r
-#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)\r
-\r
-/** @brief  Check SYSCFG flag is set or not.\r
-  * @param  __FLAG__  specifies the flag to check.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag\r
-  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing\r
-  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)\r
-\r
-/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.\r
-  */\r
-#define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)\r
-\r
-/** @brief  Fast-mode Plus driving capability enable/disable macros\r
-  * @param __FASTMODEPLUS__  This parameter can be a value of :\r
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6\r
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7\r
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8\r
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9\r
-  */\r
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\\r
-                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\\r
-                                                               }while(0)\r
-\r
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\\r
-                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\\r
-                                                               }while(0)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup HAL_Private_Macros HAL Private Macros\r
-  * @{\r
-  */\r
-\r
-#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ)  || \\r
-                               ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \\r
-                               ((__FREQ__) == HAL_TICK_FREQ_1KHZ))\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros\r
-  * @{\r
-  */\r
-\r
-#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \\r
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \\r
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \\r
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \\r
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \\r
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))\r
-\r
-#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \\r
-                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \\r
-                                            ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \\r
-                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))\r
-\r
-#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))\r
-\r
-#if defined(VREFBUF)\r
-#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \\r
-                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))\r
-\r
-#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \\r
-                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))\r
-\r
-#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))\r
-#endif /* VREFBUF */\r
-\r
-#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))\r
-#elif defined(SYSCFG_FASTMODEPLUS_PB8)\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))\r
-#elif defined(SYSCFG_FASTMODEPLUS_PB9)\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))\r
-#else\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported variables --------------------------------------------------------*/\r
-\r
-/** @addtogroup HAL_Exported_Variables\r
-  * @{\r
-  */\r
-extern __IO uint32_t uwTick;\r
-extern uint32_t uwTickPrio;\r
-extern uint32_t uwTickFreq;\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup HAL_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-\r
-/* Initialization and de-initialization functions  ******************************/\r
-HAL_StatusTypeDef HAL_Init(void);\r
-HAL_StatusTypeDef HAL_DeInit(void);\r
-void              HAL_MspInit(void);\r
-void              HAL_MspDeInit(void);\r
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-\r
-/* Peripheral Control functions  ************************************************/\r
-void               HAL_IncTick(void);\r
-void               HAL_Delay(uint32_t Delay);\r
-uint32_t           HAL_GetTick(void);\r
-uint32_t           HAL_GetTickPrio(void);\r
-HAL_StatusTypeDef  HAL_SetTickFreq(uint32_t Freq);\r
-uint32_t           HAL_GetTickFreq(void);\r
-void               HAL_SuspendTick(void);\r
-void               HAL_ResumeTick(void);\r
-uint32_t           HAL_GetHalVersion(void);\r
-uint32_t           HAL_GetREVID(void);\r
-uint32_t           HAL_GetDEVID(void);\r
-uint32_t           HAL_GetUIDw0(void);\r
-uint32_t           HAL_GetUIDw1(void);\r
-uint32_t           HAL_GetUIDw2(void);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group3\r
-  * @{\r
-  */\r
-\r
-/* DBGMCU Peripheral Control functions  *****************************************/\r
-void              HAL_DBGMCU_EnableDBGSleepMode(void);\r
-void              HAL_DBGMCU_DisableDBGSleepMode(void);\r
-void              HAL_DBGMCU_EnableDBGStopMode(void);\r
-void              HAL_DBGMCU_DisableDBGStopMode(void);\r
-void              HAL_DBGMCU_EnableDBGStandbyMode(void);\r
-void              HAL_DBGMCU_DisableDBGStandbyMode(void);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group4\r
-  * @{\r
-  */\r
-\r
-/* SYSCFG Control functions  ****************************************************/\r
-void              HAL_SYSCFG_SRAM2Erase(void);\r
-void              HAL_SYSCFG_EnableMemorySwappingBank(void);\r
-void              HAL_SYSCFG_DisableMemorySwappingBank(void);\r
-\r
-#if defined(VREFBUF)\r
-void              HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);\r
-void              HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);\r
-void              HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);\r
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);\r
-void              HAL_SYSCFG_DisableVREFBUF(void);\r
-#endif /* VREFBUF */\r
-\r
-void              HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);\r
-void              HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
deleted file mode 100644 (file)
index af333b8..0000000
+++ /dev/null
@@ -1,417 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_cortex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of CORTEX HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_CORTEX_H\r
-#define __STM32L4xx_HAL_CORTEX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup CORTEX CORTEX\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types\r
-  * @{\r
-  */\r
-\r
-#if (__MPU_PRESENT == 1)\r
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
-  * @{\r
-  */\r
-typedef struct\r
-{\r
-  uint8_t                Enable;                /*!< Specifies the status of the region.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */\r
-  uint8_t                Number;                /*!< Specifies the number of the region to protect.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */\r
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */\r
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */\r
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.\r
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */\r
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */\r
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */\r
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */\r
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */\r
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */\r
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.\r
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */\r
-}MPU_Region_InitTypeDef;\r
-/**\r
-  * @}\r
-  */\r
-#endif /* __MPU_PRESENT */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r
-  * @{\r
-  */\r
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,\r
-                                                                 4 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,\r
-                                                                 3 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,\r
-                                                                 2 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,\r
-                                                                 1 bit  for subpriority */\r
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,\r
-                                                                 0 bit  for subpriority */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source\r
-  * @{\r
-  */\r
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)\r
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if (__MPU_PRESENT == 1)\r
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control\r
-  * @{\r
-  */\r
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)\r
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)\r
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)\r
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
-  * @{\r
-  */\r
-#define  MPU_REGION_ENABLE           ((uint8_t)0x01)\r
-#define  MPU_REGION_DISABLE          ((uint8_t)0x00)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
-  * @{\r
-  */\r
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)\r
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
-  * @{\r
-  */\r
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)\r
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
-  * @{\r
-  */\r
-#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)\r
-#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
-  * @{\r
-  */\r
-#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)\r
-#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels\r
-  * @{\r
-  */\r
-#define  MPU_TEX_LEVEL0              ((uint8_t)0x00)\r
-#define  MPU_TEX_LEVEL1              ((uint8_t)0x01)\r
-#define  MPU_TEX_LEVEL2              ((uint8_t)0x02)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
-  * @{\r
-  */\r
-#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)\r
-#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)\r
-#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)\r
-#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)\r
-#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)\r
-#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)\r
-#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)\r
-#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)\r
-#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)\r
-#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)\r
-#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)\r
-#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)\r
-#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)\r
-#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)\r
-#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)\r
-#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)\r
-#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)\r
-#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)\r
-#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)\r
-#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)\r
-#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)\r
-#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)\r
-#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)\r
-#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)\r
-#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)\r
-#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)\r
-#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)\r
-#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes\r
-  * @{\r
-  */\r
-#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)\r
-#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)\r
-#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)\r
-#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)\r
-#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)\r
-#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
-  * @{\r
-  */\r
-#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)\r
-#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)\r
-#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)\r
-#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)\r
-#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)\r
-#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)\r
-#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)\r
-#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)\r
-/**\r
-  * @}\r
-  */\r
-#endif /* __MPU_PRESENT */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions\r
-  * @brief    Initialization and Configuration functions\r
-  * @{\r
-  */\r
-/* Initialization and Configuration functions *****************************/\r
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_SystemReset(void);\r
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
-  * @brief   Cortex control functions\r
-  * @{\r
-  */\r
-/* Peripheral Control functions ***********************************************/\r
-uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
-void HAL_SYSTICK_IRQHandler(void);\r
-void HAL_SYSTICK_Callback(void);\r
-\r
-#if (__MPU_PRESENT == 1)\r
-void HAL_MPU_Enable(uint32_t MPU_Control);\r
-void HAL_MPU_Disable(void);\r
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
-#endif /* __MPU_PRESENT */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private constants ---------------------------------------------------------*/\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
-  * @{\r
-  */\r
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))\r
-\r
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)\r
-\r
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
-\r
-#if (__MPU_PRESENT == 1)\r
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
-                                     ((STATE) == MPU_REGION_DISABLE))\r
-\r
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
-\r
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
-\r
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
-\r
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
-\r
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \\r
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \\r
-                                ((TYPE) == MPU_TEX_LEVEL2))\r
-\r
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \\r
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \\r
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \\r
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
-\r
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \\r
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \\r
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \\r
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \\r
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \\r
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \\r
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \\r
-                                         ((NUMBER) == MPU_REGION_NUMBER7))\r
-\r
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \\r
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))\r
-\r
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)\r
-#endif /* __MPU_PRESENT */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_CORTEX_H */\r
-\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
deleted file mode 100644 (file)
index e96526d..0000000
+++ /dev/null
@@ -1,197 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_def.h\r
-  * @author  MCD Application Team\r
-  * @brief   This file contains HAL common defines, enumeration, macros and\r
-  *          structures definitions.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_DEF_H\r
-#define STM32L4xx_HAL_DEF_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx.h"\r
-#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */\r
-#include <stddef.h>\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/**\r
-  * @brief  HAL Status structures definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_OK       = 0x00,\r
-  HAL_ERROR    = 0x01,\r
-  HAL_BUSY     = 0x02,\r
-  HAL_TIMEOUT  = 0x03\r
-} HAL_StatusTypeDef;\r
-\r
-/**\r
-  * @brief  HAL Lock structures definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_UNLOCKED = 0x00,\r
-  HAL_LOCKED   = 0x01\r
-} HAL_LockTypeDef;\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-\r
-#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */\r
-\r
-#define HAL_MAX_DELAY      0xFFFFFFFFU\r
-\r
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))\r
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)\r
-\r
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \\r
-                        do{                                                      \\r
-                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\r
-                            (__DMA_HANDLE__).Parent = (__HANDLE__);              \\r
-                        } while(0)\r
-\r
-/** @brief Reset the Handle's State field.\r
-  * @param __HANDLE__: specifies the Peripheral Handle.\r
-  * @note  This macro can be used for the following purpose:\r
-  *          - When the Handle is declared as local variable; before passing it as parameter\r
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro\r
-  *            to set to 0 the Handle's "State" field.\r
-  *            Otherwise, "State" field may have any random value and the first time the function\r
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
-  *            (i.e. HAL_PPP_MspInit() will not be executed).\r
-  *          - When there is a need to reconfigure the low level hardware: instead of calling\r
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
-  * @retval None\r
-  */\r
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)\r
-\r
-#if (USE_RTOS == 1)\r
-  /* Reserved for future use */\r
-  #error " USE_RTOS should be 0 in the current HAL release "\r
-#else\r
-  #define __HAL_LOCK(__HANDLE__)                                           \\r
-                                do{                                        \\r
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\r
-                                    {                                      \\r
-                                       return HAL_BUSY;                    \\r
-                                    }                                      \\r
-                                    else                                   \\r
-                                    {                                      \\r
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\r
-                                    }                                      \\r
-                                  }while (0)\r
-\r
-  #define __HAL_UNLOCK(__HANDLE__)                                          \\r
-                                  do{                                       \\r
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\r
-                                    }while (0)\r
-#endif /* USE_RTOS */\r
-\r
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
-  #ifndef __weak\r
-    #define __weak   __attribute__((weak))\r
-  #endif /* __weak */\r
-  #ifndef __packed\r
-    #define __packed __attribute__((__packed__))\r
-  #endif /* __packed */\r
-#endif /* __GNUC__ */\r
-\r
-\r
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
-  #ifndef __ALIGN_END\r
-    #define __ALIGN_END    __attribute__ ((aligned (4)))\r
-  #endif /* __ALIGN_END */\r
-  #ifndef __ALIGN_BEGIN\r
-    #define __ALIGN_BEGIN\r
-  #endif /* __ALIGN_BEGIN */\r
-#else\r
-  #ifndef __ALIGN_END\r
-    #define __ALIGN_END\r
-  #endif /* __ALIGN_END */\r
-  #ifndef __ALIGN_BEGIN\r
-    #if defined   (__CC_ARM)      /* ARM Compiler */\r
-      #define __ALIGN_BEGIN    __align(4)\r
-    #elif defined (__ICCARM__)    /* IAR Compiler */\r
-      #define __ALIGN_BEGIN\r
-    #endif /* __CC_ARM */\r
-  #endif /* __ALIGN_BEGIN */\r
-#endif /* __GNUC__ */\r
-\r
-/**\r
-  * @brief  __RAM_FUNC definition\r
-  */\r
-#if defined ( __CC_ARM   )\r
-/* ARM Compiler\r
-   ------------\r
-   RAM functions are defined using the toolchain options.\r
-   Functions that are executed in RAM should reside in a separate source module.\r
-   Using the 'Options for File' dialog you can simply change the 'Code / Const'\r
-   area of a module to a memory space in physical RAM.\r
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
-   dialog.\r
-*/\r
-#define __RAM_FUNC HAL_StatusTypeDef\r
-\r
-#elif defined ( __ICCARM__ )\r
-/* ICCARM Compiler\r
-   ---------------\r
-   RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
-*/\r
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef\r
-\r
-#elif defined   (  __GNUC__  )\r
-/* GNU Compiler\r
-   ------------\r
-  RAM functions are defined using a specific toolchain attribute\r
-   "__attribute__((section(".RamFunc")))".\r
-*/\r
-#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))\r
-\r
-#endif\r
-\r
-/**\r
-  * @brief  __NOINLINE definition\r
-  */\r
-#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )\r
-/* ARM & GNUCompiler\r
-   ----------------\r
-*/\r
-#define __NOINLINE __attribute__ ( (noinline) )\r
-\r
-#elif defined ( __ICCARM__ )\r
-/* ICCARM Compiler\r
-   ---------------\r
-*/\r
-#define __NOINLINE _Pragma("optimize = no_inline")\r
-\r
-#endif\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_DEF_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h
deleted file mode 100644 (file)
index 50ce0b2..0000000
+++ /dev/null
@@ -1,887 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_dfsdm.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of DFSDM HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_DFSDM_H\r
-#define STM32L4xx_HAL_DFSDM_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
-    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
-    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
-    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup DFSDM\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup DFSDM_Exported_Types DFSDM Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  HAL DFSDM Channel states definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */\r
-  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */\r
-  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */\r
-} HAL_DFSDM_Channel_StateTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM channel output clock structure definition\r
-  */\r
-typedef struct\r
-{\r
-  FunctionalState Activation; /*!< Output clock enable/disable */\r
-  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.\r
-                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */\r
-  uint32_t        Divider;    /*!< Output clock divider.\r
-                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */\r
-} DFSDM_Channel_OutputClockTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM channel input structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.\r
-                             ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,\r
-                             STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx,\r
-                             STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products.\r
-                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */\r
-  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.\r
-                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */\r
-  uint32_t Pins;        /*!< Input pins are taken from same or following channel.\r
-                             This parameter can be a value of @ref DFSDM_Channel_InputPins */\r
-} DFSDM_Channel_InputTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM channel serial interface structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Type;     /*!< SPI or Manchester modes.\r
-                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */\r
-  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).\r
-                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */\r
-} DFSDM_Channel_SerialInterfaceTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM channel analog watchdog structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.\r
-                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */\r
-  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.\r
-                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
-} DFSDM_Channel_AwdTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM channel init structure definition\r
-  */\r
-typedef struct\r
-{\r
-  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */\r
-  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */\r
-  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */\r
-  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */\r
-  int32_t                              Offset;          /*!< DFSDM channel offset.\r
-                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
-  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.\r
-                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
-} DFSDM_Channel_InitTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM channel handle structure definition\r
-  */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-typedef struct __DFSDM_Channel_HandleTypeDef\r
-#else\r
-typedef struct\r
-#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
-{\r
-  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */\r
-  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */\r
-  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);       /*!< DFSDM channel clock absence detection callback */\r
-  void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);        /*!< DFSDM channel short circuit detection callback */\r
-  void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);    /*!< DFSDM channel MSP init callback */\r
-  void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);  /*!< DFSDM channel MSP de-init callback */\r
-#endif\r
-} DFSDM_Channel_HandleTypeDef;\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  DFSDM channel callback ID enumeration definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_DFSDM_CHANNEL_CKAB_CB_ID      = 0x00U, /*!< DFSDM channel clock absence detection callback ID */\r
-  HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U, /*!< DFSDM channel short circuit detection callback ID */\r
-  HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U, /*!< DFSDM channel MSP init callback ID */\r
-  HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U  /*!< DFSDM channel MSP de-init callback ID */\r
-} HAL_DFSDM_Channel_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM channel callback pointer definition\r
-  */\r
-typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-#endif\r
-\r
-/**\r
-  * @brief  HAL DFSDM Filter states definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */\r
-  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */\r
-  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */\r
-  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */\r
-  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */\r
-  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */\r
-} HAL_DFSDM_Filter_StateTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM filter regular conversion parameters structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.\r
-                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
-  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */\r
-  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */\r
-} DFSDM_Filter_RegularParamTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM filter injected conversion parameters structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.\r
-                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
-  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */\r
-  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */\r
-  uint32_t        ExtTrigger;     /*!< External trigger.\r
-                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */\r
-  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.\r
-                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */\r
-} DFSDM_Filter_InjectedParamTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM filter parameters structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t SincOrder;       /*!< Sinc filter order.\r
-                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */\r
-  uint32_t Oversampling;    /*!< Filter oversampling ratio.\r
-                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */\r
-  uint32_t IntOversampling; /*!< Integrator oversampling ratio.\r
-                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */\r
-} DFSDM_Filter_FilterParamTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM filter init structure definition\r
-  */\r
-typedef struct\r
-{\r
-  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */\r
-  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */\r
-  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */\r
-} DFSDM_Filter_InitTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM filter handle structure definition\r
-  */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-typedef struct __DFSDM_Filter_HandleTypeDef\r
-#else\r
-typedef struct\r
-#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
-{\r
-  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */\r
-  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */\r
-  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */\r
-  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */\r
-  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */\r
-  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */\r
-  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */\r
-  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */\r
-  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */\r
-  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */\r
-  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */\r
-  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */\r
-  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                      uint32_t Channel, uint32_t Threshold);                            /*!< DFSDM filter analog watchdog callback */\r
-  void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter regular conversion complete callback */\r
-  void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half regular conversion complete callback */\r
-  void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter injected conversion complete callback */\r
-  void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half injected conversion complete callback */\r
-  void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);            /*!< DFSDM filter error callback */\r
-  void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);          /*!< DFSDM filter MSP init callback */\r
-  void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);        /*!< DFSDM filter MSP de-init callback */\r
-#endif\r
-} DFSDM_Filter_HandleTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM filter analog watchdog parameters structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.\r
-                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */\r
-  uint32_t Channel;         /*!< Analog watchdog channel selection.\r
-                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */\r
-  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.\r
-                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
-  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.\r
-                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
-  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.\r
-                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
-  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.\r
-                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
-} DFSDM_Filter_AwdParamTypeDef;\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  DFSDM filter callback ID enumeration definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID     = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */\r
-  HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */\r
-  HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID     = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */\r
-  HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */\r
-  HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U, /*!< DFSDM filter error callback ID */\r
-  HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U, /*!< DFSDM filter MSP init callback ID */\r
-  HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U  /*!< DFSDM filter MSP de-init callback ID */\r
-} HAL_DFSDM_Filter_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  DFSDM filter callback pointer definition\r
-  */\r
-typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported types -----------------------------------------------------*/\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection\r
-  * @{\r
-  */\r
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U             /*!< Source for ouput clock is system clock */\r
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer\r
-  * @{\r
-  */\r
-#define DFSDM_CHANNEL_EXTERNAL_INPUTS    0x00000000U             /*!< Data are taken from external inputs */\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
-    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
-    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-#define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing\r
-  * @{\r
-  */\r
-#define DFSDM_CHANNEL_STANDARD_MODE         0x00000000U             /*!< Standard data packing mode */\r
-#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */\r
-#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins\r
-  * @{\r
-  */\r
-#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U             /*!< Input from pins on same channel */\r
-#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type\r
-  * @{\r
-  */\r
-#define DFSDM_CHANNEL_SPI_RISING         0x00000000U             /*!< SPI with rising edge */\r
-#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */\r
-#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */\r
-#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection\r
-  * @{\r
-  */\r
-#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U              /*!< External SPI clock */\r
-#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */\r
-#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */\r
-#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order\r
-  * @{\r
-  */\r
-#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U             /*!< FastSinc filter type */\r
-#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */\r
-#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */\r
-#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger\r
-  * @{\r
-  */\r
-#define DFSDM_FILTER_SW_TRIGGER   0x00000000U /*!< Software trigger */\r
-#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */\r
-#define DFSDM_FILTER_EXT_TRIGGER  0x00000002U /*!< External trigger (only for injected conversion) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger\r
-  * @{\r
-  */\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
-#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \\r
-                                          DFSDM_FLTCR1_JEXTSEL_2)                          /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  DFSDM_FLTCR1_JEXTSEL_3                            /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_EXTI15     (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
-                                          DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */\r
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
-                                          DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */\r
-#else\r
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 0, 1 and 2 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
-#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge\r
-  * @{\r
-  */\r
-#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */\r
-#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */\r
-#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order\r
-  * @{\r
-  */\r
-#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                                 /*!< FastSinc filter type */\r
-#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */\r
-#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */\r
-#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */\r
-#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */\r
-#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source\r
-  * @{\r
-  */\r
-#define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U             /*!< From digital filter */\r
-#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code\r
-  * @{\r
-  */\r
-#define DFSDM_FILTER_ERROR_NONE             0x00000000U /*!< No error */\r
-#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U /*!< Overrun occurs during regular conversion */\r
-#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */\r
-#define DFSDM_FILTER_ERROR_DMA              0x00000003U /*!< DMA error occurs */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_BreakSignals DFSDM break signals\r
-  * @{\r
-  */\r
-#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */\r
-#define DFSDM_BREAK_SIGNAL_0  0x00000001U /*!< Break signal 0 */\r
-#define DFSDM_BREAK_SIGNAL_1  0x00000002U /*!< Break signal 1 */\r
-#define DFSDM_BREAK_SIGNAL_2  0x00000004U /*!< Break signal 2 */\r
-#define DFSDM_BREAK_SIGNAL_3  0x00000008U /*!< Break signal 3 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection\r
-  * @{\r
-  */\r
-/* DFSDM Channels ------------------------------------------------------------*/\r
-/* The DFSDM channels are defined as follows:\r
-   - in 16-bit LSB the channel mask is set\r
-   - in 16-bit MSB the channel number is set\r
-   e.g. for channel 5 definition:\r
-        - the channel mask is 0x00000020 (bit 5 is set)\r
-        - the channel number 5 is 0x00050000\r
-        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-#define DFSDM_CHANNEL_0                              0x00000001U\r
-#define DFSDM_CHANNEL_1                              0x00010002U\r
-#define DFSDM_CHANNEL_2                              0x00020004U\r
-#define DFSDM_CHANNEL_3                              0x00030008U\r
-#else\r
-#define DFSDM_CHANNEL_0                              0x00000001U\r
-#define DFSDM_CHANNEL_1                              0x00010002U\r
-#define DFSDM_CHANNEL_2                              0x00020004U\r
-#define DFSDM_CHANNEL_3                              0x00030008U\r
-#define DFSDM_CHANNEL_4                              0x00040010U\r
-#define DFSDM_CHANNEL_5                              0x00050020U\r
-#define DFSDM_CHANNEL_6                              0x00060040U\r
-#define DFSDM_CHANNEL_7                              0x00070080U\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode\r
-  * @{\r
-  */\r
-#define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U /*!< Conversion are not continuous */\r
-#define DFSDM_CONTINUOUS_CONV_ON             0x00000001U /*!< Conversion are continuous */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold\r
-  * @{\r
-  */\r
-#define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U /*!< Analog watchdog high threshold */\r
-#define DFSDM_AWD_LOW_THRESHOLD             0x00000001U /*!< Analog watchdog low threshold */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported constants -------------------------------------------------*/\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros\r
- * @{\r
- */\r
-\r
-/** @brief  Reset DFSDM channel handle state.\r
-  * @param  __HANDLE__ DFSDM channel handle.\r
-  * @retval None\r
-  */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \\r
-                                                               (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \\r
-                                                               (__HANDLE__)->MspInitCallback = NULL;                \\r
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;              \\r
-                                                             } while(0)\r
-#else\r
-#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)\r
-#endif\r
-\r
-/** @brief  Reset DFSDM filter handle state.\r
-  * @param  __HANDLE__ DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \\r
-                                                              (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \\r
-                                                              (__HANDLE__)->MspInitCallback = NULL;               \\r
-                                                              (__HANDLE__)->MspDeInitCallback = NULL;             \\r
-                                                            } while(0)\r
-#else\r
-#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported macros ----------------------------------------------------*/\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-/* Include DFSDM HAL Extension module */\r
-#include "stm32l4xx_hal_dfsdm_ex.h"\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r
-  * @{\r
-  */\r
-/* Channel initialization and de-initialization functions *********************/\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-/* Channel callbacks register/unregister functions ****************************/\r
-HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
-                                                     HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,\r
-                                                     pDFSDM_Channel_CallbackTypeDef      pCallback);\r
-HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
-                                                       HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r
-  * @{\r
-  */\r
-/* Channel operation functions ************************************************/\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-\r
-int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);\r
-\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
-\r
-void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r
-  * @{\r
-  */\r
-/* Channel state function *****************************************************/\r
-HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r
-  * @{\r
-  */\r
-/* Filter initialization and de-initialization functions *********************/\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-/* Filter callbacks register/unregister functions ****************************/\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
-                                                    HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,\r
-                                                    pDFSDM_Filter_CallbackTypeDef      pCallback);\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
-                                                      HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,\r
-                                                       pDFSDM_Filter_AwdCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r
-  * @{\r
-  */\r
-/* Filter control functions *********************/\r
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                   uint32_t                    Channel,\r
-                                                   uint32_t                    ContinuousMode);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                   uint32_t                    Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r
-  * @{\r
-  */\r
-/* Filter operation functions *********************/\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                              DFSDM_Filter_AwdParamTypeDef *awdParam);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-\r
-int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
-int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
-int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
-int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
-uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-\r
-void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-\r
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
-\r
-void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
-void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r
-  * @{\r
-  */\r
-/* Filter state functions *****************************************************/\r
-HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported functions -------------------------------------------------*/\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup DFSDM_Private_Macros DFSDM Private Macros\r
-* @{\r
-*/\r
-#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \\r
-                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))\r
-#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
-    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
-    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
-                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \\r
-                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
-#else\r
-#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
-                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
-/* STM32L496xx || STM32L4A6xx ||                */\r
-/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \\r
-                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \\r
-                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))\r
-#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \\r
-                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))\r
-#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \\r
-                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \\r
-                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \\r
-                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))\r
-#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \\r
-                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \\r
-                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \\r
-                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))\r
-#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))\r
-#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))\r
-#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
-#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)\r
-#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)\r
-#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))\r
-#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
-#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))\r
-#else\r
-#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
-                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \\r
-                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \\r
-                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))\r
-#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \\r
-                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))\r
-#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))\r
-#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))\r
-#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \\r
-                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))\r
-#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
-#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_3))\r
-#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))\r
-#else\r
-#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \\r
-                                                       ((CHANNEL) == DFSDM_CHANNEL_7))\r
-#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \\r
-                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))\r
-/**\r
-  * @}\r
-  */\r
-/* End of private macros -----------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
-/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
-/* STM32L496xx || STM32L4A6xx || */\r
-/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_DFSDM_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
deleted file mode 100644 (file)
index f165a5d..0000000
+++ /dev/null
@@ -1,749 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_dma.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of DMA HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_DMA_H\r
-#define STM32L4xx_HAL_DMA_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup DMA\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup DMA_Exported_Types DMA Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  DMA Configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.\r
-                                           This parameter can be a value of @ref DMA_request */\r
-\r
-  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,\r
-                                           from memory to memory or from peripheral to memory.\r
-                                           This parameter can be a value of @ref DMA_Data_transfer_direction */\r
-\r
-  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.\r
-                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
-\r
-  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.\r
-                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
-\r
-  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.\r
-                                           This parameter can be a value of @ref DMA_Peripheral_data_size */\r
-\r
-  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.\r
-                                           This parameter can be a value of @ref DMA_Memory_data_size */\r
-\r
-  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.\r
-                                           This parameter can be a value of @ref DMA_mode\r
-                                           @note The circular buffer mode cannot be used if the memory-to-memory\r
-                                                 data transfer is configured on the selected Channel */\r
-\r
-  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.\r
-                                           This parameter can be a value of @ref DMA_Priority_level */\r
-} DMA_InitTypeDef;\r
-\r
-/**\r
-  * @brief  HAL DMA State structures definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */\r
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */\r
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */\r
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */\r
-}HAL_DMA_StateTypeDef;\r
-\r
-/**\r
-  * @brief  HAL DMA Error Code structure definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */\r
-  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */\r
-}HAL_DMA_LevelCompleteTypeDef;\r
-\r
-\r
-/**\r
-  * @brief  HAL DMA Callback ID structure definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */\r
-  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */\r
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */\r
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */\r
-  HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */\r
-}HAL_DMA_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  DMA handle Structure definition\r
-  */\r
-typedef struct __DMA_HandleTypeDef\r
-{\r
-  DMA_Channel_TypeDef    *Instance;                                                     /*!< Register base address                */\r
-\r
-  DMA_InitTypeDef       Init;                                                           /*!< DMA communication parameters         */\r
-\r
-  HAL_LockTypeDef       Lock;                                                           /*!< DMA locking object                   */\r
-\r
-  __IO HAL_DMA_StateTypeDef  State;                                                     /*!< DMA transfer state                   */\r
-\r
-  void                  *Parent;                                                        /*!< Parent object state                  */\r
-\r
-  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer complete callback       */\r
-\r
-  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA Half transfer complete callback  */\r
-\r
-  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer error callback          */\r
-\r
-  void                  (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer abort callback          */\r
-\r
-  __IO uint32_t         ErrorCode;                                                      /*!< DMA Error code                       */\r
-\r
-  DMA_TypeDef           *DmaBaseAddress;                                                /*!< DMA Channel Base Address             */\r
-\r
-  uint32_t              ChannelIndex;                                                   /*!< DMA Channel Index                    */\r
-\r
-#if defined(DMAMUX1)\r
-  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                      /*!< Register base address                */\r
-\r
-  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                /*!< DMAMUX Channels Status Base Address  */\r
-\r
-  uint32_t                         DMAmuxChannelStatusMask;                             /*!< DMAMUX Channel Status Mask           */\r
-\r
-  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                   /*!< DMAMUX request generator Base Address */\r
-\r
-  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                             /*!< DMAMUX request generator Address     */\r
-\r
-  uint32_t                         DMAmuxRequestGenStatusMask;                          /*!< DMAMUX request generator Status mask */\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-}DMA_HandleTypeDef;\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DMA_Error_Code DMA Error Code\r
-  * @{\r
-  */\r
-#define HAL_DMA_ERROR_NONE                 0x00000000U    /*!< No error                                */\r
-#define HAL_DMA_ERROR_TE                   0x00000001U    /*!< Transfer error                          */\r
-#define HAL_DMA_ERROR_NO_XFER              0x00000004U    /*!< Abort requested with no Xfer ongoing    */\r
-#define HAL_DMA_ERROR_TIMEOUT              0x00000020U    /*!< Timeout error                           */\r
-#define HAL_DMA_ERROR_NOT_SUPPORTED        0x00000100U    /*!< Not supported mode                      */\r
-#define HAL_DMA_ERROR_SYNC                 0x00000200U    /*!< DMAMUX sync overrun  error              */\r
-#define HAL_DMA_ERROR_REQGEN               0x00000400U    /*!< DMAMUX request generator overrun  error */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_request DMA request\r
-  * @{\r
-  */\r
-#if !defined (DMAMUX1)\r
-\r
-#define DMA_REQUEST_0                     0U\r
-#define DMA_REQUEST_1                     1U\r
-#define DMA_REQUEST_2                     2U\r
-#define DMA_REQUEST_3                     3U\r
-#define DMA_REQUEST_4                     4U\r
-#define DMA_REQUEST_5                     5U\r
-#define DMA_REQUEST_6                     6U\r
-#define DMA_REQUEST_7                     7U\r
-\r
-#endif\r
-\r
-#if defined(DMAMUX1)\r
-\r
-#define DMA_REQUEST_MEM2MEM                 0U  /*!< memory to memory transfer   */\r
-\r
-#define DMA_REQUEST_GENERATOR0              1U  /*!< DMAMUX1 request generator 0 */\r
-#define DMA_REQUEST_GENERATOR1              2U  /*!< DMAMUX1 request generator 1 */\r
-#define DMA_REQUEST_GENERATOR2              3U  /*!< DMAMUX1 request generator 2 */\r
-#define DMA_REQUEST_GENERATOR3              4U  /*!< DMAMUX1 request generator 3 */\r
-\r
-#define DMA_REQUEST_ADC1                    5U  /*!< DMAMUX1 ADC1 request      */\r
-\r
-#define DMA_REQUEST_DAC1_CH1                6U  /*!< DMAMUX1 DAC1 CH1 request  */\r
-#define DMA_REQUEST_DAC1_CH2                7U  /*!< DMAMUX1 DAC1 CH2 request  */\r
-\r
-#define DMA_REQUEST_TIM6_UP                 8U  /*!< DMAMUX1 TIM6 UP request   */\r
-#define DMA_REQUEST_TIM7_UP                 9U  /*!< DMAMUX1 TIM7 UP request   */\r
-\r
-#define DMA_REQUEST_SPI1_RX                10U  /*!< DMAMUX1 SPI1 RX request   */\r
-#define DMA_REQUEST_SPI1_TX                11U  /*!< DMAMUX1 SPI1 TX request   */\r
-#define DMA_REQUEST_SPI2_RX                12U  /*!< DMAMUX1 SPI2 RX request   */\r
-#define DMA_REQUEST_SPI2_TX                13U  /*!< DMAMUX1 SPI2 TX request   */\r
-#define DMA_REQUEST_SPI3_RX                14U  /*!< DMAMUX1 SPI3 RX request   */\r
-#define DMA_REQUEST_SPI3_TX                15U  /*!< DMAMUX1 SPI3 TX request   */\r
-\r
-#define DMA_REQUEST_I2C1_RX                16U  /*!< DMAMUX1 I2C1 RX request   */\r
-#define DMA_REQUEST_I2C1_TX                17U  /*!< DMAMUX1 I2C1 TX request   */\r
-#define DMA_REQUEST_I2C2_RX                18U  /*!< DMAMUX1 I2C2 RX request   */\r
-#define DMA_REQUEST_I2C2_TX                19U  /*!< DMAMUX1 I2C2 TX request   */\r
-#define DMA_REQUEST_I2C3_RX                20U  /*!< DMAMUX1 I2C3 RX request   */\r
-#define DMA_REQUEST_I2C3_TX                21U  /*!< DMAMUX1 I2C3 TX request   */\r
-#define DMA_REQUEST_I2C4_RX                22U  /*!< DMAMUX1 I2C4 RX request   */\r
-#define DMA_REQUEST_I2C4_TX                23U  /*!< DMAMUX1 I2C4 TX request   */\r
-\r
-#define DMA_REQUEST_USART1_RX              24U  /*!< DMAMUX1 USART1 RX request */\r
-#define DMA_REQUEST_USART1_TX              25U  /*!< DMAMUX1 USART1 TX request */\r
-#define DMA_REQUEST_USART2_RX              26U  /*!< DMAMUX1 USART2 RX request */\r
-#define DMA_REQUEST_USART2_TX              27U  /*!< DMAMUX1 USART2 TX request */\r
-#define DMA_REQUEST_USART3_RX              28U  /*!< DMAMUX1 USART3 RX request */\r
-#define DMA_REQUEST_USART3_TX              29U  /*!< DMAMUX1 USART3 TX request */\r
-\r
-#define DMA_REQUEST_UART4_RX               30U  /*!< DMAMUX1 UART4 RX request  */\r
-#define DMA_REQUEST_UART4_TX               31U  /*!< DMAMUX1 UART4 TX request  */\r
-#define DMA_REQUEST_UART5_RX               32U  /*!< DMAMUX1 UART5 RX request  */\r
-#define DMA_REQUEST_UART5_TX               33U  /*!< DMAMUX1 UART5 TX request  */\r
-\r
-#define DMA_REQUEST_LPUART1_RX             34U  /*!< DMAMUX1 LP_UART1_RX request */\r
-#define DMA_REQUEST_LPUART1_TX             35U  /*!< DMAMUX1 LP_UART1_RX request */\r
-\r
-#define DMA_REQUEST_SAI1_A                 36U  /*!< DMAMUX1 SAI1 A request    */\r
-#define DMA_REQUEST_SAI1_B                 37U  /*!< DMAMUX1 SAI1 B request    */\r
-#define DMA_REQUEST_SAI2_A                 38U  /*!< DMAMUX1 SAI2 A request    */\r
-#define DMA_REQUEST_SAI2_B                 39U  /*!< DMAMUX1 SAI2 B request    */\r
-\r
-#define DMA_REQUEST_OCTOSPI1               40U  /*!< DMAMUX1 OCTOSPI1 request  */\r
-#define DMA_REQUEST_OCTOSPI2               41U  /*!< DMAMUX1 OCTOSPI2 request  */\r
-\r
-#define DMA_REQUEST_TIM1_CH1               42U  /*!< DMAMUX1 TIM1 CH1 request  */\r
-#define DMA_REQUEST_TIM1_CH2               43U  /*!< DMAMUX1 TIM1 CH2 request  */\r
-#define DMA_REQUEST_TIM1_CH3               44U  /*!< DMAMUX1 TIM1 CH3 request  */\r
-#define DMA_REQUEST_TIM1_CH4               45U  /*!< DMAMUX1 TIM1 CH4 request  */\r
-#define DMA_REQUEST_TIM1_UP                46U  /*!< DMAMUX1 TIM1 UP  request  */\r
-#define DMA_REQUEST_TIM1_TRIG              47U  /*!< DMAMUX1 TIM1 TRIG request */\r
-#define DMA_REQUEST_TIM1_COM               48U  /*!< DMAMUX1 TIM1 COM request  */\r
-\r
-#define DMA_REQUEST_TIM8_CH1               49U  /*!< DMAMUX1 TIM8 CH1 request  */\r
-#define DMA_REQUEST_TIM8_CH2               50U  /*!< DMAMUX1 TIM8 CH2 request  */\r
-#define DMA_REQUEST_TIM8_CH3               51U  /*!< DMAMUX1 TIM8 CH3 request  */\r
-#define DMA_REQUEST_TIM8_CH4               52U  /*!< DMAMUX1 TIM8 CH4 request  */\r
-#define DMA_REQUEST_TIM8_UP                53U  /*!< DMAMUX1 TIM8 UP  request  */\r
-#define DMA_REQUEST_TIM8_TRIG              54U  /*!< DMAMUX1 TIM8 TRIG request */\r
-#define DMA_REQUEST_TIM8_COM               55U  /*!< DMAMUX1 TIM8 COM request  */\r
-\r
-#define DMA_REQUEST_TIM2_CH1               56U  /*!< DMAMUX1 TIM2 CH1 request  */\r
-#define DMA_REQUEST_TIM2_CH2               57U  /*!< DMAMUX1 TIM2 CH2 request  */\r
-#define DMA_REQUEST_TIM2_CH3               58U  /*!< DMAMUX1 TIM2 CH3 request  */\r
-#define DMA_REQUEST_TIM2_CH4               59U  /*!< DMAMUX1 TIM2 CH4 request  */\r
-#define DMA_REQUEST_TIM2_UP                60U  /*!< DMAMUX1 TIM2 UP  request  */\r
-\r
-#define DMA_REQUEST_TIM3_CH1               61U  /*!< DMAMUX1 TIM3 CH1 request  */\r
-#define DMA_REQUEST_TIM3_CH2               62U  /*!< DMAMUX1 TIM3 CH2 request  */\r
-#define DMA_REQUEST_TIM3_CH3               63U  /*!< DMAMUX1 TIM3 CH3 request  */\r
-#define DMA_REQUEST_TIM3_CH4               64U  /*!< DMAMUX1 TIM3 CH4 request  */\r
-#define DMA_REQUEST_TIM3_UP                65U  /*!< DMAMUX1 TIM3 UP  request  */\r
-#define DMA_REQUEST_TIM3_TRIG              66U  /*!< DMAMUX1 TIM3 TRIG request */\r
-\r
-#define DMA_REQUEST_TIM4_CH1               67U  /*!< DMAMUX1 TIM4 CH1 request  */\r
-#define DMA_REQUEST_TIM4_CH2               68U  /*!< DMAMUX1 TIM4 CH2 request  */\r
-#define DMA_REQUEST_TIM4_CH3               69U  /*!< DMAMUX1 TIM4 CH3 request  */\r
-#define DMA_REQUEST_TIM4_CH4               70U  /*!< DMAMUX1 TIM4 CH4 request  */\r
-#define DMA_REQUEST_TIM4_UP                71U  /*!< DMAMUX1 TIM4 UP  request  */\r
-\r
-#define DMA_REQUEST_TIM5_CH1               72U  /*!< DMAMUX1 TIM5 CH1 request  */\r
-#define DMA_REQUEST_TIM5_CH2               73U  /*!< DMAMUX1 TIM5 CH2 request  */\r
-#define DMA_REQUEST_TIM5_CH3               74U  /*!< DMAMUX1 TIM5 CH3 request  */\r
-#define DMA_REQUEST_TIM5_CH4               75U  /*!< DMAMUX1 TIM5 CH4 request  */\r
-#define DMA_REQUEST_TIM5_UP                76U  /*!< DMAMUX1 TIM5 UP  request  */\r
-#define DMA_REQUEST_TIM5_TRIG              77U  /*!< DMAMUX1 TIM5 TRIG request */\r
-\r
-#define DMA_REQUEST_TIM15_CH1              78U  /*!< DMAMUX1 TIM15 CH1 request */\r
-#define DMA_REQUEST_TIM15_UP               79U  /*!< DMAMUX1 TIM15 UP  request */\r
-#define DMA_REQUEST_TIM15_TRIG             80U  /*!< DMAMUX1 TIM15 TRIG request */\r
-#define DMA_REQUEST_TIM15_COM              81U  /*!< DMAMUX1 TIM15 COM request */\r
-\r
-#define DMA_REQUEST_TIM16_CH1              82U  /*!< DMAMUX1 TIM16 CH1 request */\r
-#define DMA_REQUEST_TIM16_UP               83U  /*!< DMAMUX1 TIM16 UP  request */\r
-#define DMA_REQUEST_TIM17_CH1              84U  /*!< DMAMUX1 TIM17 CH1 request */\r
-#define DMA_REQUEST_TIM17_UP               85U  /*!< DMAMUX1 TIM17 UP  request */\r
-\r
-#define DMA_REQUEST_DFSDM1_FLT0            86U  /*!< DMAMUX1 DFSDM1 Filter0 request */\r
-#define DMA_REQUEST_DFSDM1_FLT1            87U  /*!< DMAMUX1 DFSDM1 Filter1 request */\r
-#define DMA_REQUEST_DFSDM1_FLT2            88U  /*!< DMAMUX1 DFSDM1 Filter2 request */\r
-#define DMA_REQUEST_DFSDM1_FLT3            89U  /*!< DMAMUX1 DFSDM1 Filter3 request */\r
-\r
-#define DMA_REQUEST_DCMI                   90U  /*!< DMAMUX1 DCMI request      */\r
-\r
-#define DMA_REQUEST_AES_IN                 91U  /*!< DMAMUX1 AES IN request    */\r
-#define DMA_REQUEST_AES_OUT                92U  /*!< DMAMUX1 AES OUT request   */\r
-\r
-#define DMA_REQUEST_HASH_IN                93U  /*!< DMAMUX1 HASH IN request   */\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
-  * @{\r
-  */\r
-#define DMA_PERIPH_TO_MEMORY         0x00000000U        /*!< Peripheral to memory direction */\r
-#define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR        /*!< Memory to peripheral direction */\r
-#define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM    /*!< Memory to memory direction     */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
-  * @{\r
-  */\r
-#define DMA_PINC_ENABLE              DMA_CCR_PINC  /*!< Peripheral increment mode Enable */\r
-#define DMA_PINC_DISABLE             0x00000000U   /*!< Peripheral increment mode Disable */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
-  * @{\r
-  */\r
-#define DMA_MINC_ENABLE              DMA_CCR_MINC   /*!< Memory increment mode Enable  */\r
-#define DMA_MINC_DISABLE             0x00000000U    /*!< Memory increment mode Disable */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
-  * @{\r
-  */\r
-#define DMA_PDATAALIGN_BYTE          0x00000000U       /*!< Peripheral data alignment : Byte     */\r
-#define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0   /*!< Peripheral data alignment : HalfWord */\r
-#define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1   /*!< Peripheral data alignment : Word     */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Memory_data_size DMA Memory data size\r
-  * @{\r
-  */\r
-#define DMA_MDATAALIGN_BYTE          0x00000000U       /*!< Memory data alignment : Byte     */\r
-#define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0   /*!< Memory data alignment : HalfWord */\r
-#define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1   /*!< Memory data alignment : Word     */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_mode DMA mode\r
-  * @{\r
-  */\r
-#define DMA_NORMAL                   0x00000000U     /*!< Normal mode                  */\r
-#define DMA_CIRCULAR                 DMA_CCR_CIRC    /*!< Circular mode                */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Priority_level DMA Priority level\r
-  * @{\r
-  */\r
-#define DMA_PRIORITY_LOW             0x00000000U     /*!< Priority level : Low       */\r
-#define DMA_PRIORITY_MEDIUM          DMA_CCR_PL_0    /*!< Priority level : Medium    */\r
-#define DMA_PRIORITY_HIGH            DMA_CCR_PL_1    /*!< Priority level : High      */\r
-#define DMA_PRIORITY_VERY_HIGH       DMA_CCR_PL      /*!< Priority level : Very_High */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
-  * @{\r
-  */\r
-#define DMA_IT_TC                         DMA_CCR_TCIE\r
-#define DMA_IT_HT                         DMA_CCR_HTIE\r
-#define DMA_IT_TE                         DMA_CCR_TEIE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_flag_definitions DMA flag definitions\r
-  * @{\r
-  */\r
-#define DMA_FLAG_GL1                      DMA_ISR_GIF1\r
-#define DMA_FLAG_TC1                      DMA_ISR_TCIF1\r
-#define DMA_FLAG_HT1                      DMA_ISR_HTIF1\r
-#define DMA_FLAG_TE1                      DMA_ISR_TEIF1\r
-#define DMA_FLAG_GL2                      DMA_ISR_GIF2\r
-#define DMA_FLAG_TC2                      DMA_ISR_TCIF2\r
-#define DMA_FLAG_HT2                      DMA_ISR_HTIF2\r
-#define DMA_FLAG_TE2                      DMA_ISR_TEIF2\r
-#define DMA_FLAG_GL3                      DMA_ISR_GIF3\r
-#define DMA_FLAG_TC3                      DMA_ISR_TCIF3\r
-#define DMA_FLAG_HT3                      DMA_ISR_HTIF3\r
-#define DMA_FLAG_TE3                      DMA_ISR_TEIF3\r
-#define DMA_FLAG_GL4                      DMA_ISR_GIF4\r
-#define DMA_FLAG_TC4                      DMA_ISR_TCIF4\r
-#define DMA_FLAG_HT4                      DMA_ISR_HTIF4\r
-#define DMA_FLAG_TE4                      DMA_ISR_TEIF4\r
-#define DMA_FLAG_GL5                      DMA_ISR_GIF5\r
-#define DMA_FLAG_TC5                      DMA_ISR_TCIF5\r
-#define DMA_FLAG_HT5                      DMA_ISR_HTIF5\r
-#define DMA_FLAG_TE5                      DMA_ISR_TEIF5\r
-#define DMA_FLAG_GL6                      DMA_ISR_GIF6\r
-#define DMA_FLAG_TC6                      DMA_ISR_TCIF6\r
-#define DMA_FLAG_HT6                      DMA_ISR_HTIF6\r
-#define DMA_FLAG_TE6                      DMA_ISR_TEIF6\r
-#define DMA_FLAG_GL7                      DMA_ISR_GIF7\r
-#define DMA_FLAG_TC7                      DMA_ISR_TCIF7\r
-#define DMA_FLAG_HT7                      DMA_ISR_HTIF7\r
-#define DMA_FLAG_TE7                      DMA_ISR_TEIF7\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup DMA_Exported_Macros DMA Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Reset DMA handle state.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval None\r
-  */\r
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
-\r
-/**\r
-  * @brief  Enable the specified DMA Channel.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval None\r
-  */\r
-#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)\r
-\r
-/**\r
-  * @brief  Disable the specified DMA Channel.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval None\r
-  */\r
-#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)\r
-\r
-\r
-/* Interrupt & Flag management */\r
-\r
-/**\r
-  * @brief  Return the current DMA Channel transfer complete flag.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval The specified transfer complete flag index.\r
-  */\r
-\r
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\\r
-   DMA_FLAG_TC7)\r
-\r
-/**\r
-  * @brief  Return the current DMA Channel half transfer complete flag.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval The specified half transfer complete flag index.\r
-  */\r
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\\r
-   DMA_FLAG_HT7)\r
-\r
-/**\r
-  * @brief  Return the current DMA Channel transfer error flag.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval The specified transfer error flag index.\r
-  */\r
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\\r
-   DMA_FLAG_TE7)\r
-\r
-/**\r
-  * @brief  Return the current DMA Channel Global interrupt flag.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval The specified transfer error flag index.\r
-  */\r
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\\r
-   DMA_ISR_GIF7)\r
-\r
-/**\r
-  * @brief  Get the DMA Channel pending flags.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @param  __FLAG__ Get the specified flag.\r
-  *          This parameter can be any combination of the following values:\r
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag\r
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag\r
-  *            @arg DMA_FLAG_TEx:  Transfer error flag\r
-  *            @arg DMA_FLAG_GLx:  Global interrupt flag\r
-  *         Where x can be from 1 to 7 to select the DMA Channel x flag.\r
-  * @retval The state of FLAG (SET or RESET).\r
-  */\r
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
- (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))\r
-\r
-/**\r
-  * @brief  Clear the DMA Channel pending flags.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @param  __FLAG__ specifies the flag to clear.\r
-  *          This parameter can be any combination of the following values:\r
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag\r
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag\r
-  *            @arg DMA_FLAG_TEx:  Transfer error flag\r
-  *            @arg DMA_FLAG_GLx:  Global interrupt flag\r
-  *         Where x can be from 1 to 7 to select the DMA Channel x flag.\r
-  * @retval None\r
-  */\r
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
- (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))\r
-\r
-/**\r
-  * @brief  Enable the specified DMA Channel interrupts.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
-  *          This parameter can be any combination of the following values:\r
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask\r
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask\r
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask\r
-  * @retval None\r
-  */\r
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))\r
-\r
-/**\r
-  * @brief  Disable the specified DMA Channel interrupts.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
-  *          This parameter can be any combination of the following values:\r
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask\r
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask\r
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask\r
-  * @retval None\r
-  */\r
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))\r
-\r
-/**\r
-  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask\r
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask\r
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask\r
-  * @retval The state of DMA_IT (SET or RESET).\r
-  */\r
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))\r
-\r
-/**\r
-  * @brief  Return the number of remaining data units in the current DMA Channel transfer.\r
-  * @param  __HANDLE__ DMA handle\r
-  * @retval The number of remaining data units in the current DMA Channel transfer.\r
-  */\r
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(DMAMUX1)\r
-/* Include DMA HAL Extension module */\r
-#include "stm32l4xx_hal_dma_ex.h"\r
-#endif /* DMAMUX1 */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup DMA_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup DMA_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-/* Initialization and de-initialization functions *****************************/\r
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup DMA_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-/* IO operation functions *****************************************************/\r
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));\r
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup DMA_Exported_Functions_Group3\r
-  * @{\r
-  */\r
-/* Peripheral State and Error functions ***************************************/\r
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup DMA_Private_Macros DMA Private Macros\r
-  * @{\r
-  */\r
-\r
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \\r
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))\r
-\r
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))\r
-\r
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
-                                            ((STATE) == DMA_PINC_DISABLE))\r
-\r
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \\r
-                                        ((STATE) == DMA_MINC_DISABLE))\r
-\r
-#if !defined (DMAMUX1)\r
-\r
-#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \\r
-                                     ((REQUEST) == DMA_REQUEST_1) || \\r
-                                     ((REQUEST) == DMA_REQUEST_2) || \\r
-                                     ((REQUEST) == DMA_REQUEST_3) || \\r
-                                     ((REQUEST) == DMA_REQUEST_4) || \\r
-                                     ((REQUEST) == DMA_REQUEST_5) || \\r
-                                     ((REQUEST) == DMA_REQUEST_6) || \\r
-                                     ((REQUEST) == DMA_REQUEST_7))\r
-#endif\r
-\r
-#if defined(DMAMUX1)\r
-\r
-#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \\r
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))\r
-\r
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \\r
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))\r
-\r
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \\r
-                           ((MODE) == DMA_CIRCULAR))\r
-\r
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \\r
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \\r
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_DMA_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h
deleted file mode 100644 (file)
index 81da436..0000000
+++ /dev/null
@@ -1,282 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_dma_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of DMA HAL extension module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_DMA_EX_H\r
-#define STM32L4xx_HAL_DMA_EX_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#if defined(DMAMUX1)\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup DMAEx\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  HAL DMA Synchro definition\r
-  */\r
-\r
-\r
-/**\r
-  * @brief  HAL DMAMUX Synchronization configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.\r
-                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */\r
-\r
-  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.\r
-                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */\r
-\r
-  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled\r
-                                    This parameter can take the value ENABLE or DISABLE*/\r
-\r
-\r
-  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.\r
-                                       This parameter can take the value ENABLE or DISABLE */\r
-\r
-  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event\r
-                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
-\r
-\r
-}HAL_DMA_MuxSyncConfigTypeDef;\r
-\r
-\r
-/**\r
-  * @brief  HAL DMAMUX request generator parameters structure definition\r
-  */\r
-typedef struct\r
-{\r
- uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator\r
-                              This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */\r
-\r
-  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.\r
-                             This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */\r
-\r
-  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event\r
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
-\r
-}HAL_DMA_MuxRequestGeneratorConfigTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection\r
-  * @{\r
-  */\r
-#define HAL_DMAMUX1_SYNC_EXTI0                0U           /*!<  Synchronization Signal is EXTI0  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI1                1U           /*!<  Synchronization Signal is EXTI1  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI2                2U           /*!<  Synchronization Signal is EXTI2  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI3                3U           /*!<  Synchronization Signal is EXTI3  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI4                4U           /*!<  Synchronization Signal is EXTI4  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI5                5U           /*!<  Synchronization Signal is EXTI5  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI6                6U           /*!<  Synchronization Signal is EXTI6  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI7                7U           /*!<  Synchronization Signal is EXTI7  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI8                8U           /*!<  Synchronization Signal is EXTI8  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI9                9U           /*!<  Synchronization Signal is EXTI9  IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI10              10U           /*!<  Synchronization Signal is EXTI10 IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI11              11U           /*!<  Synchronization Signal is EXTI11 IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI12              12U           /*!<  Synchronization Signal is EXTI12 IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI13              13U           /*!<  Synchronization Signal is EXTI13 IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI14              14U           /*!<  Synchronization Signal is EXTI14 IT   */\r
-#define HAL_DMAMUX1_SYNC_EXTI15              15U           /*!<  Synchronization Signal is EXTI15 IT   */\r
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT     16U           /*!<  Synchronization Signal is DMAMUX1 Channel0 Event  */\r
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT     17U           /*!<  Synchronization Signal is DMAMUX1 Channel1 Event  */\r
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT     18U           /*!<  Synchronization Signal is DMAMUX1 Channel2 Event  */\r
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT     19U           /*!<  Synchronization Signal is DMAMUX1 Channel3 Event  */\r
-#define HAL_DMAMUX1_SYNC_LPTIM1_OUT          20U           /*!<  Synchronization Signal is LPTIM1 OUT */\r
-#define HAL_DMAMUX1_SYNC_LPTIM2_OUT          21U           /*!<  Synchronization Signal is LPTIM2 OUT */\r
-#define HAL_DMAMUX1_SYNC_DSI_TE              22U           /*!<  Synchronization Signal is DSI Tearing Effect      */\r
-#define HAL_DMAMUX1_SYNC_DSI_EOT             23U           /*!<  Synchronization Signal is DSI End of refresh      */\r
-#define HAL_DMAMUX1_SYNC_DMA2D_EOT           24U           /*!<  Synchronization Signal is DMA2D End of Transfer   */\r
-#define HAL_DMAMUX1_SYNC_LDTC_IT             25U           /*!<  Synchronization Signal is LDTC IT    */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection\r
-  * @{\r
-  */\r
-#define HAL_DMAMUX_SYNC_NO_EVENT                               0U    /*!< block synchronization events        */\r
-#define HAL_DMAMUX_SYNC_RISING                 DMAMUX_CxCR_SPOL_0    /*!< synchronize with rising edge events */\r
-#define HAL_DMAMUX_SYNC_FALLING                DMAMUX_CxCR_SPOL_1    /*!< synchronize with falling edge events */\r
-#define HAL_DMAMUX_SYNC_RISING_FALLING         DMAMUX_CxCR_SPOL      /*!< synchronize with rising and falling edge events */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection\r
-  * @{\r
-  */\r
-\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI0                0U        /*!< Request generator Signal is EXTI0 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI1                1U        /*!< Request generator Signal is EXTI1 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI2                2U        /*!< Request generator Signal is EXTI2 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI3                3U        /*!< Request generator Signal is EXTI3 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI4                4U        /*!< Request generator Signal is EXTI4 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI5                5U        /*!< Request generator Signal is EXTI5 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI6                6U        /*!< Request generator Signal is EXTI6 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI7                7U        /*!< Request generator Signal is EXTI7 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI8                8U        /*!< Request generator Signal is EXTI8 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI9                9U        /*!< Request generator Signal is EXTI9 IT    */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI10              10U        /*!< Request generator Signal is EXTI10 IT   */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI11              11U        /*!< Request generator Signal is EXTI11 IT   */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI12              12U        /*!< Request generator Signal is EXTI12 IT   */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI13              13U        /*!< Request generator Signal is EXTI13 IT   */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI14              14U        /*!< Request generator Signal is EXTI14 IT   */\r
-#define HAL_DMAMUX1_REQ_GEN_EXTI15              15U        /*!< Request generator Signal is EXTI15 IT   */\r
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT     16U        /*!< Request generator Signal is DMAMUX1 Channel0 Event */\r
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT     17U        /*!< Request generator Signal is DMAMUX1 Channel1 Event */\r
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT     18U        /*!< Request generator Signal is DMAMUX1 Channel2 Event */\r
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT     19U        /*!< Request generator Signal is DMAMUX1 Channel3 Event */\r
-#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT          20U        /*!< Request generator Signal is LPTIM1 OUT  */\r
-#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT          21U        /*!< Request generator Signal is LPTIM2 OUT  */\r
-#define HAL_DMAMUX1_REQ_GEN_DSI_TE              22U        /*!< Request generator Signal is DSI Tearing Effect      */\r
-#define HAL_DMAMUX1_REQ_GEN_DSI_EOT             23U        /*!< Request generator Signal is DSI End of refresh      */\r
-#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT           24U        /*!< Request generator Signal is DMA2D End of Transfer   */\r
-#define HAL_DMAMUX1_REQ_GEN_LTDC_IT             25U        /*!< Request generator Signal is LTDC IT     */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection\r
-  * @{\r
-  */\r
-#define HAL_DMAMUX_REQ_GEN_NO_EVENT       0U                     /*!< block request generator events        */\r
-#define HAL_DMAMUX_REQ_GEN_RISING         DMAMUX_RGxCR_GPOL_0    /*!< generate request on rising edge events */\r
-#define HAL_DMAMUX_REQ_GEN_FALLING        DMAMUX_RGxCR_GPOL_1    /*!< generate request on falling edge events */\r
-#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL      /*!< generate request on rising and falling edge events */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup DMAEx_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/* IO operation functions *****************************************************/\r
-/** @addtogroup DMAEx_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-\r
-/* ------------------------- REQUEST -----------------------------------------*/\r
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,\r
-             HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);\r
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);\r
-/* -------------------------------------------------------------------------- */\r
-\r
-/* ------------------------- SYNCHRO -----------------------------------------*/\r
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);\r
-/* -------------------------------------------------------------------------- */\r
-\r
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup DMAEx_Private_Macros DMAEx Private Macros\r
-  * @brief    DMAEx private macros\r
-  * @{\r
-  */\r
-\r
-#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT)\r
-\r
-#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))\r
-\r
-#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \\r
-                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \\r
-                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \\r
-                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))\r
-\r
-#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))\r
-\r
-#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \\r
-                                     ((EVENT) == ENABLE))\r
-\r
-#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT)\r
-\r
-#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))\r
-\r
-#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)   || \\r
-                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \\r
-                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \\r
-                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_DMA_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h
deleted file mode 100644 (file)
index c90e9d0..0000000
+++ /dev/null
@@ -1,860 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_exti.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of EXTI HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_EXTI_H\r
-#define STM32L4xx_HAL_EXTI_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup EXTI EXTI\r
-  * @brief EXTI HAL module driver\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup EXTI_Exported_Types EXTI Exported Types\r
-  * @{\r
-  */\r
-typedef enum\r
-{\r
-  HAL_EXTI_COMMON_CB_ID          = 0x00U,\r
-  HAL_EXTI_RISING_CB_ID          = 0x01U,\r
-  HAL_EXTI_FALLING_CB_ID         = 0x02U,\r
-} EXTI_CallbackIDTypeDef;\r
-\r
-\r
-/**\r
-  * @brief  EXTI Handle structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Line;                    /*!<  Exti line number */\r
-  void (* PendingCallback)(void);   /*!<  Exti pending callback */\r
-} EXTI_HandleTypeDef;\r
-\r
-/**\r
-  * @brief  EXTI Configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Line;      /*!< The Exti line to be configured. This parameter\r
-                           can be a value of @ref EXTI_Line */\r
-  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.\r
-                           This parameter can be a combination of @ref EXTI_Mode */\r
-  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter\r
-                           can be a value of @ref EXTI_Trigger */\r
-  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.\r
-                           This parameter is only possible for line 0 to 15. It\r
-                           can be a value of @ref EXTI_GPIOSel */\r
-} EXTI_ConfigTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup EXTI_Line  EXTI Line\r
-  * @{\r
-  */\r
-#if defined(STM32L412xx) || defined(STM32L422xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_RESERVED | EXTI_REG1              | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
-\r
-#endif /* STM32L412xx || STM32L422xx */\r
-\r
-#if defined(STM32L431xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1              | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2              | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
-\r
-#endif /* STM32L431xx */\r
-\r
-#if defined(STM32L432xx) || defined(STM32L442xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_RESERVED | EXTI_REG1              | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_RESERVED | EXTI_REG1              | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
-\r
-#endif /* STM32L432xx || STM32L442xx */\r
-\r
-#if defined(STM32L433xx) || defined(STM32L443xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1              | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
-\r
-#endif /* STM32L433xx || STM32L443xx */\r
-\r
-#if defined(STM32L451xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1              | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2              | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
-\r
-#endif /* STM32L451xx */\r
-\r
-#if defined(STM32L452xx) || defined(STM32L462xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1              | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_RESERVED | EXTI_REG2              | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
-\r
-#endif /* STM32L452xx || STM32L462xx */\r
-\r
-#if defined(STM32L471xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1              | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2              | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
-\r
-#endif /* STM32L471xx */\r
-\r
-#if defined(STM32L475xx) || defined(STM32L485xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
-\r
-#endif /* STM32L475xx || STM32L485xx  */\r
-\r
-#if defined(STM32L476xx) || defined(STM32L486xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_RESERVED | EXTI_REG2              | 0x08u)\r
-\r
-#endif /*  STM32L476xx || STM32L486xx */\r
-\r
-#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
-\r
-#endif /*  STM32L496xx || STM32L4A6xx */\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-\r
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02u)\r
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07u)\r
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08u)\r
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09u)\r
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Au)\r
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Bu)\r
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Cu)\r
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Du)\r
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Eu)\r
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0Fu)\r
-#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x10u)\r
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11u)\r
-#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x12u)\r
-#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x13u)\r
-#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14u)\r
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15u)\r
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x16u)\r
-#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17u)\r
-#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18u)\r
-#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19u)\r
-#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Au)\r
-#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Bu)\r
-#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Cu)\r
-#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Du)\r
-#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Eu)\r
-#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1Fu)\r
-#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00u)\r
-#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01u)\r
-#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2              | 0x02u)\r
-#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x03u)\r
-#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x04u)\r
-#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x05u)\r
-#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x06u)\r
-#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2              | 0x07u)\r
-#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x08u)\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup EXTI_Mode  EXTI Mode\r
-  * @{\r
-  */\r
-#define EXTI_MODE_NONE                      0x00000000u\r
-#define EXTI_MODE_INTERRUPT                 0x00000001u\r
-#define EXTI_MODE_EVENT                     0x00000002u\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup EXTI_Trigger  EXTI Trigger\r
-  * @{\r
-  */\r
-#define EXTI_TRIGGER_NONE                   0x00000000u\r
-#define EXTI_TRIGGER_RISING                 0x00000001u\r
-#define EXTI_TRIGGER_FALLING                0x00000002u\r
-#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup EXTI_GPIOSel  EXTI GPIOSel\r
-  * @brief\r
-  * @{\r
-  */\r
-#define EXTI_GPIOA                          0x00000000u\r
-#define EXTI_GPIOB                          0x00000001u\r
-#define EXTI_GPIOC                          0x00000002u\r
-#define EXTI_GPIOD                          0x00000003u\r
-#define EXTI_GPIOE                          0x00000004u\r
-#define EXTI_GPIOF                          0x00000005u\r
-#define EXTI_GPIOG                          0x00000005u\r
-#define EXTI_GPIOH                          0x00000007u\r
-#define EXTI_GPIOI                          0x00000008u\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private constants --------------------------------------------------------*/\r
-/** @defgroup EXTI_Private_Constants EXTI Private Constants\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  EXTI Line property definition\r
-  */\r
-#define EXTI_PROPERTY_SHIFT                  24u\r
-#define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)\r
-#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)\r
-#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)\r
-#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)\r
-#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)\r
-\r
-/**\r
-  * @brief  EXTI Event presence definition\r
-  */\r
-#define EXTI_EVENT_PRESENCE_SHIFT           28u\r
-#define EXTI_EVENT                          (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)\r
-#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)\r
-\r
-/**\r
-  * @brief  EXTI Register and bit usage\r
-  */\r
-#define EXTI_REG_SHIFT                      16u\r
-#define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)\r
-#define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)\r
-#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)\r
-#define EXTI_PIN_MASK                       0x0000001Fu\r
-\r
-/**\r
-  * @brief  EXTI Mask for interrupt & event mode\r
-  */\r
-#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)\r
-\r
-/**\r
-  * @brief  EXTI Mask for trigger possibilities\r
-  */\r
-#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)\r
-\r
-/**\r
-  * @brief  EXTI Line number\r
-  */\r
-#define EXTI_LINE_NB                        41u\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup EXTI_Private_Macros EXTI Private Macros\r
-  * @{\r
-  */\r
-#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \\r
-                                        ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \\r
-                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \\r
-                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \\r
-                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \\r
-                                         (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))\r
-\r
-#define IS_EXTI_MODE(__LINE__)          ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \\r
-                                         (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))\r
-\r
-#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)\r
-\r
-#define IS_EXTI_PENDING_EDGE(__LINE__)  ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)\r
-\r
-#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00u)\r
-\r
-#if defined(STM32L412xx) || defined(STM32L422xx)\r
-\r
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
-                                         ((__PORT__) == EXTI_GPIOB) || \\r
-                                         ((__PORT__) == EXTI_GPIOC) || \\r
-                                         ((__PORT__) == EXTI_GPIOD) || \\r
-                                         ((__PORT__) == EXTI_GPIOH))\r
-\r
-#endif /* STM32L412xx || STM32L422xx */\r
-\r
-#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)\r
-\r
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
-                                         ((__PORT__) == EXTI_GPIOB) || \\r
-                                         ((__PORT__) == EXTI_GPIOC) || \\r
-                                         ((__PORT__) == EXTI_GPIOD) || \\r
-                                         ((__PORT__) == EXTI_GPIOE) || \\r
-                                         ((__PORT__) == EXTI_GPIOH))\r
-\r
-#endif /* STM32L431xx || STM32L433xx || STM32L443xx */\r
-\r
-#if defined(STM32L432xx) || defined(STM32L442xx)\r
-\r
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
-                                         ((__PORT__) == EXTI_GPIOB) || \\r
-                                         ((__PORT__) == EXTI_GPIOC) || \\r
-                                         ((__PORT__) == EXTI_GPIOH))\r
-\r
-#endif /* STM32L432xx || STM32L442xx */\r
-\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-\r
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
-                                         ((__PORT__) == EXTI_GPIOB) || \\r
-                                         ((__PORT__) == EXTI_GPIOC) || \\r
-                                         ((__PORT__) == EXTI_GPIOD) || \\r
-                                         ((__PORT__) == EXTI_GPIOE) || \\r
-                                         ((__PORT__) == EXTI_GPIOH))\r
-\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-\r
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
-                                         ((__PORT__) == EXTI_GPIOB) || \\r
-                                         ((__PORT__) == EXTI_GPIOC) || \\r
-                                         ((__PORT__) == EXTI_GPIOD) || \\r
-                                         ((__PORT__) == EXTI_GPIOE) || \\r
-                                         ((__PORT__) == EXTI_GPIOF) || \\r
-                                         ((__PORT__) == EXTI_GPIOG) || \\r
-                                         ((__PORT__) == EXTI_GPIOH))\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
-\r
-#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
-\r
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
-                                         ((__PORT__) == EXTI_GPIOB) || \\r
-                                         ((__PORT__) == EXTI_GPIOC) || \\r
-                                         ((__PORT__) == EXTI_GPIOD) || \\r
-                                         ((__PORT__) == EXTI_GPIOE) || \\r
-                                         ((__PORT__) == EXTI_GPIOF) || \\r
-                                         ((__PORT__) == EXTI_GPIOG) || \\r
-                                         ((__PORT__) == EXTI_GPIOH) || \\r
-                                         ((__PORT__) == EXTI_GPIOI))\r
-\r
-#endif /* STM32L496xx || STM32L4A6xx */\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-\r
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\r
-                                         ((__PORT__) == EXTI_GPIOB) || \\r
-                                         ((__PORT__) == EXTI_GPIOC) || \\r
-                                         ((__PORT__) == EXTI_GPIOD) || \\r
-                                         ((__PORT__) == EXTI_GPIOE) || \\r
-                                         ((__PORT__) == EXTI_GPIOF) || \\r
-                                         ((__PORT__) == EXTI_GPIOG) || \\r
-                                         ((__PORT__) == EXTI_GPIOH) || \\r
-                                         ((__PORT__) == EXTI_GPIOI))\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16u)\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions\r
-  * @brief    EXTI Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions\r
-  * @brief    Configuration functions\r
-  * @{\r
-  */\r
-/* Configuration functions ****************************************************/\r
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\r
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\r
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);\r
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));\r
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions\r
-  * @brief    IO operation functions\r
-  * @{\r
-  */\r
-/* IO operation functions *****************************************************/\r
-void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);\r
-uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\r
-void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\r
-void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_EXTI_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
deleted file mode 100644 (file)
index afe5626..0000000
+++ /dev/null
@@ -1,1041 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_flash.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of FLASH HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_FLASH_H\r
-#define __STM32L4xx_HAL_FLASH_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup FLASH\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  FLASH Erase structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t TypeErase;   /*!< Mass erase or page erase.\r
-                             This parameter can be a value of @ref FLASH_Type_Erase */\r
-  uint32_t Banks;       /*!< Select bank to erase.\r
-                             This parameter must be a value of @ref FLASH_Banks\r
-                             (FLASH_BANK_BOTH should be used only for mass erase) */\r
-  uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled\r
-                             This parameter must be a value between 0 and (max number of pages in the bank - 1)\r
-                             (eg : 255 for 1MB dual bank) */\r
-  uint32_t NbPages;     /*!< Number of pages to be erased.\r
-                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/\r
-} FLASH_EraseInitTypeDef;\r
-\r
-/**\r
-  * @brief  FLASH Option Bytes Program structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t OptionType;     /*!< Option byte to be configured.\r
-                                This parameter can be a combination of the values of @ref FLASH_OB_Type */\r
-  uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).\r
-                                Only one WRP area could be programmed at the same time.\r
-                                This parameter can be value of @ref FLASH_OB_WRP_Area */\r
-  uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).\r
-                                This parameter must be a value between 0 and (max number of pages in the bank - 1)\r
-                                (eg : 25 for 1MB dual bank) */\r
-  uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).\r
-                                This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */\r
-  uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).\r
-                                This parameter can be a value of @ref FLASH_OB_Read_Protection */\r
-  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).\r
-                                This parameter can be a combination of @ref FLASH_OB_USER_Type */\r
-  uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).\r
-                                This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,\r
-                                @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,\r
-                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,\r
-                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,\r
-                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,\r
-                                @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,\r
-                                @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */\r
-  uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).\r
-                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)\r
-                                and @ref FLASH_OB_PCROP_RDP */\r
-  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).\r
-                                This parameter must be a value between begin and end of bank\r
-                                => Be careful of the bank swapping for the address */\r
-  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).\r
-                                This parameter must be a value between PCROP Start address and end of bank */\r
-} FLASH_OBProgramInitTypeDef;\r
-\r
-/**\r
-  * @brief  FLASH Procedure structure definition\r
-  */\r
-typedef enum\r
-{\r
-  FLASH_PROC_NONE = 0,\r
-  FLASH_PROC_PAGE_ERASE,\r
-  FLASH_PROC_MASS_ERASE,\r
-  FLASH_PROC_PROGRAM,\r
-  FLASH_PROC_PROGRAM_LAST\r
-} FLASH_ProcedureTypeDef;\r
-\r
-/**\r
-  * @brief  FLASH Cache structure definition\r
-  */\r
-typedef enum\r
-{\r
-  FLASH_CACHE_DISABLED = 0,\r
-  FLASH_CACHE_ICACHE_ENABLED,\r
-  FLASH_CACHE_DCACHE_ENABLED,\r
-  FLASH_CACHE_ICACHE_DCACHE_ENABLED\r
-} FLASH_CacheTypeDef;\r
-\r
-/**\r
-  * @brief  FLASH handle Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  HAL_LockTypeDef             Lock;              /* FLASH locking object */\r
-  __IO uint32_t               ErrorCode;         /* FLASH error code */\r
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */\r
-  __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */\r
-  __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */\r
-  __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */\r
-  __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */\r
-  __IO FLASH_CacheTypeDef     CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */\r
-}FLASH_ProcessTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup FLASH_Error FLASH Error\r
-  * @{\r
-  */\r
-#define HAL_FLASH_ERROR_NONE      0x00000000U\r
-#define HAL_FLASH_ERROR_OP        FLASH_FLAG_OPERR\r
-#define HAL_FLASH_ERROR_PROG      FLASH_FLAG_PROGERR\r
-#define HAL_FLASH_ERROR_WRP       FLASH_FLAG_WRPERR\r
-#define HAL_FLASH_ERROR_PGA       FLASH_FLAG_PGAERR\r
-#define HAL_FLASH_ERROR_SIZ       FLASH_FLAG_SIZERR\r
-#define HAL_FLASH_ERROR_PGS       FLASH_FLAG_PGSERR\r
-#define HAL_FLASH_ERROR_MIS       FLASH_FLAG_MISERR\r
-#define HAL_FLASH_ERROR_FAST      FLASH_FLAG_FASTERR\r
-#define HAL_FLASH_ERROR_RD        FLASH_FLAG_RDERR\r
-#define HAL_FLASH_ERROR_OPTV      FLASH_FLAG_OPTVERR\r
-#define HAL_FLASH_ERROR_ECCD      FLASH_FLAG_ECCD\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \\r
-    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \\r
-    defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define HAL_FLASH_ERROR_PEMPTY    FLASH_FLAG_PEMPTY\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Type_Erase FLASH Erase Type\r
-  * @{\r
-  */\r
-#define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/\r
-#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)  /*!<Flash mass erase activation*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Banks FLASH Banks\r
-  * @{\r
-  */\r
-#define FLASH_BANK_1              ((uint32_t)0x01)                          /*!< Bank 1   */\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define FLASH_BANK_2              ((uint32_t)0x02)                          /*!< Bank 2   */\r
-#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */\r
-#else\r
-#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1))                /*!< Bank 1   */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup FLASH_Type_Program FLASH Program Type\r
-  * @{\r
-  */\r
-#define FLASH_TYPEPROGRAM_DOUBLEWORD    ((uint32_t)0x00)  /*!<Program a double-word (64-bit) at a specified address.*/\r
-#define FLASH_TYPEPROGRAM_FAST          ((uint32_t)0x01)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.\r
-                                                                 And another 32 row double-word (64-bit) will be programmed */\r
-#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.\r
-                                                                 And this is the last 32 row double-word (64-bit) programmed */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_Type FLASH Option Bytes Type\r
-  * @{\r
-  */\r
-#define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!< WRP option byte configuration */\r
-#define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!< RDP option byte configuration */\r
-#define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!< USER option byte configuration */\r
-#define OPTIONBYTE_PCROP          ((uint32_t)0x08)  /*!< PCROP option byte configuration */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area\r
-  * @{\r
-  */\r
-#define OB_WRPAREA_BANK1_AREAA    ((uint32_t)0x00)  /*!< Flash Bank 1 Area A */\r
-#define OB_WRPAREA_BANK1_AREAB    ((uint32_t)0x01)  /*!< Flash Bank 1 Area B */\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define OB_WRPAREA_BANK2_AREAA    ((uint32_t)0x02)  /*!< Flash Bank 2 Area A */\r
-#define OB_WRPAREA_BANK2_AREAB    ((uint32_t)0x04)  /*!< Flash Bank 2 Area B */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection\r
-  * @{\r
-  */\r
-#define OB_RDP_LEVEL_0            ((uint32_t)0xAA)\r
-#define OB_RDP_LEVEL_1            ((uint32_t)0xBB)\r
-#define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2\r
-                                                        it's no more possible to go back to level 1 or 0 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type\r
-  * @{\r
-  */\r
-#define OB_USER_BOR_LEV           ((uint32_t)0x0001)                   /*!< BOR reset Level */\r
-#define OB_USER_nRST_STOP         ((uint32_t)0x0002)                   /*!< Reset generated when entering the stop mode */\r
-#define OB_USER_nRST_STDBY        ((uint32_t)0x0004)                   /*!< Reset generated when entering the standby mode */\r
-#define OB_USER_IWDG_SW           ((uint32_t)0x0008)                   /*!< Independent watchdog selection */\r
-#define OB_USER_IWDG_STOP         ((uint32_t)0x0010)                   /*!< Independent watchdog counter freeze in stop mode */\r
-#define OB_USER_IWDG_STDBY        ((uint32_t)0x0020)                   /*!< Independent watchdog counter freeze in standby mode */\r
-#define OB_USER_WWDG_SW           ((uint32_t)0x0040)                   /*!< Window watchdog selection */\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define OB_USER_BFB2              ((uint32_t)0x0080)                   /*!< Dual-bank boot */\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 1MB or 512kB Flash memory devices */\r
-#else\r
-#define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 512KB or 256KB Flash memory devices */\r
-#endif\r
-#endif\r
-#define OB_USER_nBOOT1            ((uint32_t)0x0200)                   /*!< Boot configuration */\r
-#define OB_USER_SRAM2_PE          ((uint32_t)0x0400)                   /*!< SRAM2 parity check enable */\r
-#define OB_USER_SRAM2_RST         ((uint32_t)0x0800)                   /*!< SRAM2 Erase when system reset */\r
-#define OB_USER_nRST_SHDW         ((uint32_t)0x1000)                   /*!< Reset generated when entering the shutdown mode */\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
-    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define OB_USER_nSWBOOT0          ((uint32_t)0x2000)                   /*!< Software BOOT0 */\r
-#define OB_USER_nBOOT0            ((uint32_t)0x4000)                   /*!< nBOOT0 option bit */\r
-#endif\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define OB_USER_DBANK             ((uint32_t)0x8000)                   /*!< Single bank with 128-bits data or two banks with 64-bits data */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level\r
-  * @{\r
-  */\r
-#define OB_BOR_LEVEL_0            ((uint32_t)FLASH_OPTR_BOR_LEV_0)     /*!< Reset level threshold is around 1.7V */\r
-#define OB_BOR_LEVEL_1            ((uint32_t)FLASH_OPTR_BOR_LEV_1)     /*!< Reset level threshold is around 2.0V */\r
-#define OB_BOR_LEVEL_2            ((uint32_t)FLASH_OPTR_BOR_LEV_2)     /*!< Reset level threshold is around 2.2V */\r
-#define OB_BOR_LEVEL_3            ((uint32_t)FLASH_OPTR_BOR_LEV_3)     /*!< Reset level threshold is around 2.5V */\r
-#define OB_BOR_LEVEL_4            ((uint32_t)FLASH_OPTR_BOR_LEV_4)     /*!< Reset level threshold is around 2.8V */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop\r
-  * @{\r
-  */\r
-#define OB_STOP_RST               ((uint32_t)0x0000)                   /*!< Reset generated when entering the stop mode */\r
-#define OB_STOP_NORST             ((uint32_t)FLASH_OPTR_nRST_STOP)     /*!< No reset generated when entering the stop mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby\r
-  * @{\r
-  */\r
-#define OB_STANDBY_RST            ((uint32_t)0x0000)                   /*!< Reset generated when entering the standby mode */\r
-#define OB_STANDBY_NORST          ((uint32_t)FLASH_OPTR_nRST_STDBY)    /*!< No reset generated when entering the standby mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown\r
-  * @{\r
-  */\r
-#define OB_SHUTDOWN_RST           ((uint32_t)0x0000)                   /*!< Reset generated when entering the shutdown mode */\r
-#define OB_SHUTDOWN_NORST         ((uint32_t)FLASH_OPTR_nRST_SHDW)     /*!< No reset generated when entering the shutdown mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type\r
-  * @{\r
-  */\r
-#define OB_IWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware independent watchdog */\r
-#define OB_IWDG_SW                ((uint32_t)FLASH_OPTR_IWDG_SW)       /*!< Software independent watchdog */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop\r
-  * @{\r
-  */\r
-#define OB_IWDG_STOP_FREEZE       ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Stop mode */\r
-#define OB_IWDG_STOP_RUN          ((uint32_t)FLASH_OPTR_IWDG_STOP)     /*!< Independent watchdog counter is running in Stop mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby\r
-  * @{\r
-  */\r
-#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Standby mode */\r
-#define OB_IWDG_STDBY_RUN         ((uint32_t)FLASH_OPTR_IWDG_STDBY)    /*!< Independent watchdog counter is running in Standby mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type\r
-  * @{\r
-  */\r
-#define OB_WWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware window watchdog */\r
-#define OB_WWDG_SW                ((uint32_t)FLASH_OPTR_WWDG_SW)       /*!< Software window watchdog */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode\r
-  * @{\r
-  */\r
-#define OB_BFB2_DISABLE           ((uint32_t)0x000000)                 /*!< Dual-bank boot disable */\r
-#define OB_BFB2_ENABLE            ((uint32_t)FLASH_OPTR_BFB2)          /*!< Dual-bank boot enable */\r
-/**\r
-  * @}\r
-  */\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type\r
-  * @{\r
-  */\r
-#define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 1 MB/512 kB Single-bank Flash */\r
-#define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DB1M)          /*!< 1 MB/512 kB Dual-bank Flash */\r
-/**\r
-  * @}\r
-  */\r
-#else\r
-/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type\r
-  * @{\r
-  */\r
-#define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 256 KB/512 KB Single-bank Flash */\r
-#define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DUALBANK)      /*!< 256 KB/512 KB Dual-bank Flash */\r
-/**\r
-  * @}\r
-  */\r
-#endif\r
-#endif\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type\r
-  * @{\r
-  */\r
-#define OB_DBANK_128_BITS         ((uint32_t)0x000000)                 /*!< Single-bank with 128-bits data */\r
-#define OB_DBANK_64_BITS          ((uint32_t)FLASH_OPTR_DBANK)         /*!< Dual-bank with 64-bits data */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type\r
-  * @{\r
-  */\r
-#define OB_BOOT1_SRAM             ((uint32_t)0x000000)                 /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */\r
-#define OB_BOOT1_SYSTEM           ((uint32_t)FLASH_OPTR_nBOOT1)        /*!< System memory is selected as boot space (if BOOT0=1) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type\r
-  * @{\r
-  */\r
-#define OB_SRAM2_PARITY_ENABLE    ((uint32_t)0x0000000)                /*!< SRAM2 parity check enable */\r
-#define OB_SRAM2_PARITY_DISABLE   ((uint32_t)FLASH_OPTR_SRAM2_PE)      /*!< SRAM2 parity check disable */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type\r
-  * @{\r
-  */\r
-#define OB_SRAM2_RST_ERASE        ((uint32_t)0x0000000)                /*!< SRAM2 erased when a system reset occurs */\r
-#define OB_SRAM2_RST_NOT_ERASE    ((uint32_t)FLASH_OPTR_SRAM2_RST)     /*!< SRAM2 is not erased when a system reset occurs */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
-    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-/** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0\r
-  * @{\r
-  */\r
-#define OB_BOOT0_FROM_OB          ((uint32_t)0x0000000)                /*!< BOOT0 taken from the option bit nBOOT0 */\r
-#define OB_BOOT0_FROM_PIN         ((uint32_t)FLASH_OPTR_nSWBOOT0)      /*!< BOOT0 taken from PH3/BOOT0 pin */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit\r
-  * @{\r
-  */\r
-#define OB_BOOT0_RESET            ((uint32_t)0x0000000)                /*!< nBOOT0 = 0 */\r
-#define OB_BOOT0_SET              ((uint32_t)FLASH_OPTR_nBOOT0)        /*!< nBOOT0 = 1 */\r
-/**\r
-  * @}\r
-  */\r
-#endif\r
-\r
-/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type\r
-  * @{\r
-  */\r
-#define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level\r
-                                                                            is decreased from Level 1 to Level 0 */\r
-#define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is\r
-                                                                            decreased from Level 1 to Level 0 (full mass erase) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Latency FLASH Latency\r
-  * @{\r
-  */\r
-#define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS                /*!< FLASH Zero wait state */\r
-#define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS                /*!< FLASH One wait state */\r
-#define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS                /*!< FLASH Two wait states */\r
-#define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS                /*!< FLASH Three wait states */\r
-#define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS                /*!< FLASH Four wait states */\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define FLASH_LATENCY_5           FLASH_ACR_LATENCY_5WS                /*!< FLASH Five wait state */\r
-#define FLASH_LATENCY_6           FLASH_ACR_LATENCY_6WS                /*!< FLASH Six wait state */\r
-#define FLASH_LATENCY_7           FLASH_ACR_LATENCY_7WS                /*!< FLASH Seven wait states */\r
-#define FLASH_LATENCY_8           FLASH_ACR_LATENCY_8WS                /*!< FLASH Eight wait states */\r
-#define FLASH_LATENCY_9           FLASH_ACR_LATENCY_9WS                /*!< FLASH Nine wait states */\r
-#define FLASH_LATENCY_10          FLASH_ACR_LATENCY_10WS               /*!< FLASH Ten wait state */\r
-#define FLASH_LATENCY_11          FLASH_ACR_LATENCY_11WS               /*!< FLASH Eleven wait state */\r
-#define FLASH_LATENCY_12          FLASH_ACR_LATENCY_12WS               /*!< FLASH Twelve wait states */\r
-#define FLASH_LATENCY_13          FLASH_ACR_LATENCY_13WS               /*!< FLASH Thirteen wait states */\r
-#define FLASH_LATENCY_14          FLASH_ACR_LATENCY_14WS               /*!< FLASH Fourteen wait states */\r
-#define FLASH_LATENCY_15          FLASH_ACR_LATENCY_15WS               /*!< FLASH Fifteen wait states */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Keys FLASH Keys\r
-  * @{\r
-  */\r
-#define FLASH_KEY1                0x45670123U                          /*!< Flash key1 */\r
-#define FLASH_KEY2                0xCDEF89ABU                          /*!< Flash key2: used with FLASH_KEY1\r
-                                                                            to unlock the FLASH registers access */\r
-\r
-#define FLASH_PDKEY1              0x04152637U                          /*!< Flash power down key1 */\r
-#define FLASH_PDKEY2              0xFAFBFCFDU                          /*!< Flash power down key2: used with FLASH_PDKEY1\r
-                                                                            to unlock the RUN_PD bit in FLASH_ACR */\r
-\r
-#define FLASH_OPTKEY1             0x08192A3BU                          /*!< Flash option byte key1 */\r
-#define FLASH_OPTKEY2             0x4C5D6E7FU                          /*!< Flash option byte key2: used with FLASH_OPTKEY1\r
-                                                                            to allow option bytes operations */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Flags FLASH Flags Definition\r
-  * @{\r
-  */\r
-#define FLASH_FLAG_EOP            FLASH_SR_EOP                         /*!< FLASH End of operation flag */\r
-#define FLASH_FLAG_OPERR          FLASH_SR_OPERR                       /*!< FLASH Operation error flag */\r
-#define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR                     /*!< FLASH Programming error flag */\r
-#define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR                      /*!< FLASH Write protection error flag */\r
-#define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR                      /*!< FLASH Programming alignment error flag */\r
-#define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR                      /*!< FLASH Size error flag  */\r
-#define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR                      /*!< FLASH Programming sequence error flag */\r
-#define FLASH_FLAG_MISERR         FLASH_SR_MISERR                      /*!< FLASH Fast programming data miss error flag */\r
-#define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR                     /*!< FLASH Fast programming error flag */\r
-#define FLASH_FLAG_RDERR          FLASH_SR_RDERR                       /*!< FLASH PCROP read error flag */\r
-#define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR                     /*!< FLASH Option validity error flag  */\r
-#define FLASH_FLAG_BSY            FLASH_SR_BSY                         /*!< FLASH Busy flag */\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \\r
-    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \\r
-    defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define FLASH_FLAG_PEMPTY         FLASH_SR_PEMPTY                      /*!< FLASH Program empty */\r
-#define FLASH_FLAG_SR_ERRORS      (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \\r
-                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \\r
-                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \\r
-                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY)\r
-#else\r
-#define FLASH_FLAG_SR_ERRORS      (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \\r
-                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \\r
-                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \\r
-                                   FLASH_FLAG_OPTVERR)\r
-#endif\r
-#define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC                      /*!< FLASH ECC correction */\r
-#define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD                      /*!< FLASH ECC detection */\r
-\r
-#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \\r
-                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \\r
-                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \\r
-                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition\r
-  * @brief FLASH Interrupt definition\r
-  * @{\r
-  */\r
-#define FLASH_IT_EOP              FLASH_CR_EOPIE                       /*!< End of FLASH Operation Interrupt source */\r
-#define FLASH_IT_OPERR            FLASH_CR_ERRIE                       /*!< Error Interrupt source */\r
-#define FLASH_IT_RDERR            FLASH_CR_RDERRIE                     /*!< PCROP Read Error Interrupt source*/\r
-#define FLASH_IT_ECCC             (FLASH_ECCR_ECCIE >> 24)             /*!< ECC Correction Interrupt source */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
- *  @brief macros to control FLASH features\r
- *  @{\r
- */\r
-\r
-/**\r
-  * @brief  Set the FLASH Latency.\r
-  * @param  __LATENCY__: FLASH Latency\r
-  *         This parameter can be one of the following values :\r
-  *     @arg FLASH_LATENCY_0: FLASH Zero wait state\r
-  *     @arg FLASH_LATENCY_1: FLASH One wait state\r
-  *     @arg FLASH_LATENCY_2: FLASH Two wait states\r
-  *     @arg FLASH_LATENCY_3: FLASH Three wait states\r
-  *     @arg FLASH_LATENCY_4: FLASH Four wait states\r
-  * @retval None\r
-  */\r
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))\r
-\r
-/**\r
-  * @brief  Get the FLASH Latency.\r
-  * @retval FLASH Latency\r
-  *         This parameter can be one of the following values :\r
-  *     @arg FLASH_LATENCY_0: FLASH Zero wait state\r
-  *     @arg FLASH_LATENCY_1: FLASH One wait state\r
-  *     @arg FLASH_LATENCY_2: FLASH Two wait states\r
-  *     @arg FLASH_LATENCY_3: FLASH Three wait states\r
-  *     @arg FLASH_LATENCY_4: FLASH Four wait states\r
-  */\r
-#define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)\r
-\r
-/**\r
-  * @brief  Enable the FLASH prefetch buffer.\r
-  * @retval None\r
-  */\r
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)\r
-\r
-/**\r
-  * @brief  Disable the FLASH prefetch buffer.\r
-  * @retval None\r
-  */\r
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)\r
-\r
-/**\r
-  * @brief  Enable the FLASH instruction cache.\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)\r
-\r
-/**\r
-  * @brief  Disable the FLASH instruction cache.\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)\r
-\r
-/**\r
-  * @brief  Enable the FLASH data cache.\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)\r
-\r
-/**\r
-  * @brief  Disable the FLASH data cache.\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)\r
-\r
-/**\r
-  * @brief  Reset the FLASH instruction Cache.\r
-  * @note   This function must be used only when the Instruction Cache is disabled.\r
-  * @retval None\r
-  */\r
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \\r
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \\r
-                                                   } while (0)\r
-\r
-/**\r
-  * @brief  Reset the FLASH data Cache.\r
-  * @note   This function must be used only when the data Cache is disabled.\r
-  * @retval None\r
-  */\r
-#define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \\r
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \\r
-                                                   } while (0)\r
-\r
-/**\r
-  * @brief  Enable the FLASH power down during Low-power run mode.\r
-  * @note   Writing this bit  to 0 this bit, automatically the keys are\r
-  *         loss and a new unlock sequence is necessary to re-write it to 1.\r
-  */\r
-#define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \\r
-                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \\r
-                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \\r
-                                                   } while (0)\r
-\r
-/**\r
-  * @brief  Disable the FLASH power down during Low-power run mode.\r
-  * @note   Writing this bit  to 0 this bit, automatically the keys are\r
-  *         loss and a new unlock sequence is necessary to re-write it to 1.\r
-  */\r
-#define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \\r
-                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \\r
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \\r
-                                                   } while (0)\r
-\r
-/**\r
-  * @brief  Enable the FLASH power down during Low-Power sleep mode\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)\r
-\r
-/**\r
-  * @brief  Disable the FLASH power down during Low-Power sleep mode\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Interrupt FLASH Interrupts Macros\r
- *  @brief macros to handle FLASH interrupts\r
- * @{\r
- */\r
-\r
-/**\r
-  * @brief  Enable the specified FLASH interrupt.\r
-  * @param  __INTERRUPT__: FLASH interrupt\r
-  *         This parameter can be any combination of the following values:\r
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
-  *     @arg FLASH_IT_OPERR: Error Interrupt\r
-  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt\r
-  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\\r
-                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\\r
-                                                   } while(0)\r
-\r
-/**\r
-  * @brief  Disable the specified FLASH interrupt.\r
-  * @param  __INTERRUPT__: FLASH interrupt\r
-  *         This parameter can be any combination of the following values:\r
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
-  *     @arg FLASH_IT_OPERR: Error Interrupt\r
-  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt\r
-  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt\r
-  * @retval none\r
-  */\r
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\\r
-                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\\r
-                                                   } while(0)\r
-\r
-/**\r
-  * @brief  Check whether the specified FLASH flag is set or not.\r
-  * @param  __FLAG__: specifies the FLASH flag to check.\r
-  *   This parameter can be one of the following values:\r
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
-  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag\r
-  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag\r
-  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag\r
-  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag\r
-  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag\r
-  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag\r
-  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag\r
-  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag\r
-  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag\r
-  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
-  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag\r
-  *     @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)\r
-  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected\r
-  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected\r
-  * @retval The new state of FLASH_FLAG (SET or RESET).\r
-  */\r
-#define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \\r
-                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))          : \\r
-                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))\r
-\r
-/**\r
-  * @brief  Clear the FLASH's pending flags.\r
-  * @param  __FLAG__: specifies the FLASH flags to clear.\r
-  *   This parameter can be any combination of the following values:\r
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
-  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag\r
-  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag\r
-  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag\r
-  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag\r
-  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag\r
-  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag\r
-  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag\r
-  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag\r
-  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag\r
-  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag\r
-  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected\r
-  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected\r
-  *     @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags\r
-  * @retval None\r
-  */\r
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\\r
-                                                     if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\\r
-                                                   } while(0)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include FLASH HAL Extended module */\r
-#include "stm32l4xx_hal_flash_ex.h"\r
-#include "stm32l4xx_hal_flash_ramfunc.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup FLASH_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/* Program operation functions  ***********************************************/\r
-/** @addtogroup FLASH_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
-HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
-/* FLASH IRQ handler method */\r
-void               HAL_FLASH_IRQHandler(void);\r
-/* Callbacks in non blocking modes */\r
-void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
-void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Peripheral Control functions  **********************************************/\r
-/** @addtogroup FLASH_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef  HAL_FLASH_Unlock(void);\r
-HAL_StatusTypeDef  HAL_FLASH_Lock(void);\r
-/* Option bytes control */\r
-HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);\r
-HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);\r
-HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Peripheral State functions  ************************************************/\r
-/** @addtogroup FLASH_Exported_Functions_Group3\r
-  * @{\r
-  */\r
-uint32_t HAL_FLASH_GetError(void);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/** @addtogroup FLASH_Private_Variables FLASH Private Variables\r
- * @{\r
- */\r
-extern FLASH_ProcessTypeDef pFlash;\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private function ----------------------------------------------------------*/\r
-/** @addtogroup FLASH_Private_Functions FLASH Private Functions\r
- * @{\r
- */\r
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private constants --------------------------------------------------------*/\r
-/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
-  * @{\r
-  */\r
-#define FLASH_SIZE_DATA_REGISTER           ((uint32_t)0x1FFF75E0)\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \\r
-                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
-#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
-#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \\r
-                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
-#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)\r
-#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \\r
-                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
-#elif defined (STM32L412xx) || defined (STM32L422xx)\r
-#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) :  \\r
-                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
-#else\r
-#define FLASH_SIZE                         (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \\r
-                                            (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))\r
-#endif\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define FLASH_BANK_SIZE                    (FLASH_SIZE >> 1U)\r
-#else\r
-#define FLASH_BANK_SIZE                    (FLASH_SIZE)\r
-#endif\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define FLASH_PAGE_SIZE                    ((uint32_t)0x1000)\r
-#define FLASH_PAGE_SIZE_128_BITS           ((uint32_t)0x2000)\r
-#else\r
-#define FLASH_PAGE_SIZE                    ((uint32_t)0x800)\r
-#endif\r
-\r
-#define FLASH_TIMEOUT_VALUE                ((uint32_t)50000)/* 50 s */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
- *  @{\r
- */\r
-\r
-#define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \\r
-                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \\r
-                                            ((BANK) == FLASH_BANK_2)  || \\r
-                                            ((BANK) == FLASH_BANK_BOTH))\r
-\r
-#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \\r
-                                            ((BANK) == FLASH_BANK_2))\r
-#else\r
-#define IS_FLASH_BANK(BANK)                ((BANK) == FLASH_BANK_1)\r
-\r
-#define IS_FLASH_BANK_EXCLUSIVE(BANK)      ((BANK) == FLASH_BANK_1)\r
-#endif\r
-\r
-#define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \\r
-                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \\r
-                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU)))\r
-#else\r
-#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE))         && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \\r
-                                            ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \\r
-                                            ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \\r
-                                            ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \\r
-                                            ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)))))))\r
-#endif\r
-\r
-#define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))\r
-\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_FLASH_PAGE(PAGE)                ((PAGE) < 256U)\r
-#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \\r
-                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \\r
-                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U)  : \\r
-                                            ((PAGE) < 256U)))))\r
-#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
-#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \\r
-                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \\r
-                                            ((PAGE) < 256U))))\r
-#else\r
-#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \\r
-                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U)  ? ((PAGE) < 64U)  : \\r
-                                            ((PAGE) < 128U))))\r
-#endif\r
-\r
-#define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \\r
-                                            ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))\r
-#else\r
-#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))\r
-#endif\r
-\r
-#define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\\r
-                                            ((LEVEL) == OB_RDP_LEVEL_1)/* ||\\r
-                                            ((LEVEL) == OB_RDP_LEVEL_2)*/)\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U))\r
-#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U))\r
-#else\r
-#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U))\r
-#endif\r
-\r
-#define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \\r
-                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \\r
-                                            ((LEVEL) == OB_BOR_LEVEL_4))\r
-\r
-#define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))\r
-\r
-#define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))\r
-\r
-#define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))\r
-\r
-#define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))\r
-\r
-#define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))\r
-\r
-#define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))\r
-\r
-#define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))\r
-\r
-#define IS_OB_USER_DUALBANK(VALUE)         (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))\r
-#endif\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_OB_USER_DBANK(VALUE)            (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))\r
-#endif\r
-\r
-#define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))\r
-\r
-#define IS_OB_USER_SRAM2_PARITY(VALUE)     (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))\r
-\r
-#define IS_OB_USER_SRAM2_RST(VALUE)        (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))\r
-\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
-    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \\r
-    defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_OB_USER_SWBOOT0(VALUE)          (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))\r
-\r
-#define IS_OB_USER_BOOT0(VALUE)            (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))\r
-#endif\r
-\r
-#define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))\r
-#else\r
-#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_1) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_2) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_3) || \\r
-                                            ((LATENCY) == FLASH_LATENCY_4))\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_FLASH_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
deleted file mode 100644 (file)
index 5c4f6c8..0000000
+++ /dev/null
@@ -1,128 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_flash_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of FLASH HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_FLASH_EX_H\r
-#define __STM32L4xx_HAL_FLASH_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup FLASHEx\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-#if defined (FLASH_CFGR_LVEN)\r
-/** @addtogroup FLASHEx_Exported_Constants\r
-  * @{\r
-  */\r
-/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration\r
-  * @{\r
-  */\r
-#define FLASH_LVE_PIN_CTRL     0x00000000U       /*!< LVE FLASH pin controlled by power controller       */\r
-#define FLASH_LVE_PIN_FORCED   FLASH_CFGR_LVEN   /*!< LVE FLASH pin enforced to low (external SMPS used) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* FLASH_CFGR_LVEN */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup FLASHEx_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/* Extended Program operation functions  *************************************/\r
-/** @addtogroup FLASHEx_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined (FLASH_CFGR_LVEN)\r
-/** @addtogroup FLASHEx_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE);\r
-/**\r
-  * @}\r
-  */\r
-#endif /* FLASH_CFGR_LVEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private function ----------------------------------------------------------*/\r
-/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions\r
- * @{\r
- */\r
-void FLASH_PageErase(uint32_t Page, uint32_t Banks);\r
-void FLASH_FlushCaches(void);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/**\r
-  @cond 0\r
-  */\r
-#if defined (FLASH_CFGR_LVEN)\r
-#define IS_FLASH_LVE_PIN(CFG)  (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED))\r
-#endif /* FLASH_CFGR_LVEN */\r
-/**\r
-  @endcond\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_FLASH_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
deleted file mode 100644 (file)
index 0c719e2..0000000
+++ /dev/null
@@ -1,77 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_flash_ramfunc.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of FLASH RAMFUNC driver.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_FLASH_RAMFUNC_H\r
-#define __STM32L4xx_FLASH_RAMFUNC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup FLASH_RAMFUNC\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-/* Peripheral Control functions  ************************************************/\r
-__RAM_FUNC  HAL_FLASHEx_EnableRunPowerDown(void);\r
-__RAM_FUNC  HAL_FLASHEx_DisableRunPowerDown(void);\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-__RAM_FUNC  HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_FLASH_RAMFUNC_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
deleted file mode 100644 (file)
index 7d50932..0000000
+++ /dev/null
@@ -1,300 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_gpio.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of GPIO HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_GPIO_H\r
-#define __STM32L4xx_HAL_GPIO_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup GPIO\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
-  * @{\r
-  */\r
-/**\r
-  * @brief   GPIO Init structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.\r
-                           This parameter can be any value of @ref GPIO_pins */\r
-\r
-  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.\r
-                           This parameter can be a value of @ref GPIO_mode */\r
-\r
-  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
-                           This parameter can be a value of @ref GPIO_pull */\r
-\r
-  uint32_t Speed;      /*!< Specifies the speed for the selected pins.\r
-                           This parameter can be a value of @ref GPIO_speed */\r
-\r
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins\r
-                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */\r
-}GPIO_InitTypeDef;\r
-\r
-/**\r
-  * @brief  GPIO Bit SET and Bit RESET enumeration\r
-  */\r
-typedef enum\r
-{\r
-  GPIO_PIN_RESET = 0U,\r
-  GPIO_PIN_SET\r
-}GPIO_PinState;\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
-  * @{\r
-  */\r
-/** @defgroup GPIO_pins GPIO pins\r
-  * @{\r
-  */\r
-#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */\r
-#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */\r
-#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */\r
-#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */\r
-#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */\r
-#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */\r
-#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */\r
-#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */\r
-#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */\r
-#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */\r
-#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */\r
-#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */\r
-#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */\r
-#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */\r
-#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */\r
-#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */\r
-#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */\r
-\r
-#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup GPIO_mode GPIO mode\r
-  * @brief GPIO Configuration Mode\r
-  *        Elements values convention: 0xX0yz00YZ\r
-  *           - X  : GPIO mode or EXTI Mode\r
-  *           - y  : External IT or Event trigger detection\r
-  *           - z  : IO configuration on External IT or Event\r
-  *           - Y  : Output type (Push Pull or Open Drain)\r
-  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)\r
-  * @{\r
-  */\r
-#define  GPIO_MODE_INPUT                        (0x00000000u)   /*!< Input Floating Mode                   */\r
-#define  GPIO_MODE_OUTPUT_PP                    (0x00000001u)   /*!< Output Push Pull Mode                 */\r
-#define  GPIO_MODE_OUTPUT_OD                    (0x00000011u)   /*!< Output Open Drain Mode                */\r
-#define  GPIO_MODE_AF_PP                        (0x00000002u)   /*!< Alternate Function Push Pull Mode     */\r
-#define  GPIO_MODE_AF_OD                        (0x00000012u)   /*!< Alternate Function Open Drain Mode    */\r
-#define  GPIO_MODE_ANALOG                       (0x00000003u)   /*!< Analog Mode  */\r
-#define  GPIO_MODE_ANALOG_ADC_CONTROL           (0x0000000Bu)   /*!< Analog Mode for ADC conversion */\r
-#define  GPIO_MODE_IT_RISING                    (0x10110000u)   /*!< External Interrupt Mode with Rising edge trigger detection          */\r
-#define  GPIO_MODE_IT_FALLING                   (0x10210000u)   /*!< External Interrupt Mode with Falling edge trigger detection         */\r
-#define  GPIO_MODE_IT_RISING_FALLING            (0x10310000u)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */\r
-#define  GPIO_MODE_EVT_RISING                   (0x10120000u)   /*!< External Event Mode with Rising edge trigger detection              */\r
-#define  GPIO_MODE_EVT_FALLING                  (0x10220000u)   /*!< External Event Mode with Falling edge trigger detection             */\r
-#define  GPIO_MODE_EVT_RISING_FALLING           (0x10320000u)   /*!< External Event Mode with Rising/Falling edge trigger detection      */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup GPIO_speed GPIO speed\r
-  * @brief GPIO Output Maximum frequency\r
-  * @{\r
-  */\r
-#define  GPIO_SPEED_FREQ_LOW        (0x00000000u)   /*!< range up to 5 MHz, please refer to the product datasheet */\r
-#define  GPIO_SPEED_FREQ_MEDIUM     (0x00000001u)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */\r
-#define  GPIO_SPEED_FREQ_HIGH       (0x00000002u)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */\r
-#define  GPIO_SPEED_FREQ_VERY_HIGH  (0x00000003u)   /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */\r
-/**\r
-  * @}\r
-  */\r
-\r
- /** @defgroup GPIO_pull GPIO pull\r
-   * @brief GPIO Pull-Up or Pull-Down Activation\r
-   * @{\r
-   */\r
-#define  GPIO_NOPULL        (0x00000000u)   /*!< No Pull-up or Pull-down activation  */\r
-#define  GPIO_PULLUP        (0x00000001u)   /*!< Pull-up activation                  */\r
-#define  GPIO_PULLDOWN      (0x00000002u)   /*!< Pull-down activation                */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Check whether the specified EXTI line flag is set or not.\r
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.\r
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)\r
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
-  */\r
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))\r
-\r
-/**\r
-  * @brief  Clear the EXTI's line pending flags.\r
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.\r
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
-  * @retval None\r
-  */\r
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))\r
-\r
-/**\r
-  * @brief  Check whether the specified EXTI line is asserted or not.\r
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.\r
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
-  */\r
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))\r
-\r
-/**\r
-  * @brief  Clear the EXTI's line pending bits.\r
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.\r
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
-  * @retval None\r
-  */\r
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))\r
-\r
-/**\r
-  * @brief  Generate a Software interrupt on selected EXTI line.\r
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.\r
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r
-  * @retval None\r
-  */\r
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @addtogroup GPIO_Private_Macros GPIO Private Macros\r
-  * @{\r
-  */\r
-#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
-\r
-#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\\r
-                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))\r
-\r
-#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\\r
-                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\\r
-                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\\r
-                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\\r
-                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\\r
-                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\\r
-                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\\r
-                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\\r
-                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\\r
-                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\\r
-                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
-                                     ((__MODE__) == GPIO_MODE_ANALOG)             ||\\r
-                                     ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))\r
-\r
-#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\\r
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\\r
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\\r
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))\r
-\r
-#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\\r
-                                     ((__PULL__) == GPIO_PULLUP)   || \\r
-                                     ((__PULL__) == GPIO_PULLDOWN))\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include GPIO HAL Extended module */\r
-#include "stm32l4xx_hal_gpio_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions\r
- *  @brief    Initialization and Configuration functions\r
- * @{\r
- */\r
-\r
-/* Initialization and de-initialization functions *****************************/\r
-void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
-void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions\r
- * @{\r
- */\r
-\r
-/* IO operation functions *****************************************************/\r
-GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
-void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
-void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
-void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_GPIO_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
deleted file mode 100644 (file)
index 85281c4..0000000
+++ /dev/null
@@ -1,909 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_gpio_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of GPIO HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_GPIO_EX_H\r
-#define __STM32L4xx_HAL_GPIO_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup GPIOEx GPIOEx\r
-  * @brief GPIO Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection\r
-  * @{\r
-  */\r
-\r
-#if defined(STM32L412xx) || defined(STM32L422xx)\r
-/*--------------STM32L412xx/STM32L422xx---*/\r
-/**\r
-  * @brief   AF 0 selection\r
-  */\r
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
-\r
-/**\r
-  * @brief   AF 1 selection\r
-  */\r
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
-#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 2 selection\r
-  */\r
-#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 3 selection\r
-  */\r
-#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART1 Alternate Function mapping */\r
-#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 4 selection\r
-  */\r
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 5 selection\r
-  */\r
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 6 selection\r
-  */\r
-#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 7 selection\r
-  */\r
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
-\r
-/**\r
-  * @brief   AF 8 selection\r
-  */\r
-#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 9 selection\r
-  */\r
-#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 10 selection\r
-  */\r
-#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */\r
-#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 12 selection\r
-  */\r
-#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
-\r
-\r
-/**\r
-  * @brief   AF 14 selection\r
-  */\r
-#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
-#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
-#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 15 selection\r
-  */\r
-#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
-\r
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
-\r
-#endif /* STM32L412xx || STM32L422xx */\r
-\r
-#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)\r
-/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/\r
-/**\r
-  * @brief   AF 0 selection\r
-  */\r
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
-#if defined(STM32L433xx) || defined(STM32L443xx)\r
-#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                          */\r
-#endif /* STM32L433xx || STM32L443xx */\r
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
-\r
-/**\r
-  * @brief   AF 1 selection\r
-  */\r
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
-#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 2 selection\r
-  */\r
-#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 3 selection\r
-  */\r
-#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART1 Alternate Function mapping */\r
-#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 4 selection\r
-  */\r
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 5 selection\r
-  */\r
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 6 selection\r
-  */\r
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
-#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 7 selection\r
-  */\r
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
-\r
-/**\r
-  * @brief   AF 8 selection\r
-  */\r
-#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 9 selection\r
-  */\r
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */\r
-#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 10 selection\r
-  */\r
-#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)\r
-#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */\r
-#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
-#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
-\r
-#if defined(STM32L433xx) || defined(STM32L443xx)\r
-/**\r
-  * @brief   AF 11 selection\r
-  */\r
-#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */\r
-#endif /* STM32L433xx || STM32L443xx */\r
-\r
-/**\r
-  * @brief   AF 12 selection\r
-  */\r
-#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */\r
-#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
-#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
-#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 13 selection\r
-  */\r
-#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 14 selection\r
-  */\r
-#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
-#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
-#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 15 selection\r
-  */\r
-#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
-\r
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
-\r
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
-\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/\r
-/**\r
-  * @brief   AF 0 selection\r
-  */\r
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
-\r
-/**\r
-  * @brief   AF 1 selection\r
-  */\r
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
-#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 2 selection\r
-  */\r
-#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
-#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 3 selection\r
-  */\r
-#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping     */\r
-#define GPIO_AF3_CAN1          ((uint8_t)0x03)  /* CAN1 Alternate Function mapping  */\r
-#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 4 selection\r
-  */\r
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 5 selection\r
-  */\r
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
-#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 6 selection\r
-  */\r
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
-#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 7 selection\r
-  */\r
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
-\r
-/**\r
-  * @brief   AF 8 selection\r
-  */\r
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
-#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
-#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping  */\r
-\r
-\r
-/**\r
-  * @brief   AF 9 selection\r
-  */\r
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
-#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 10 selection\r
-  */\r
-#if defined(STM32L452xx) || defined(STM32L462xx)\r
-#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */\r
-#endif /* STM32L452xx || STM32L462xx */\r
-#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
-#define GPIO_AF10_CAN1         ((uint8_t)0x0A)  /* CAN1 Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 11 selection\r
-  */\r
-\r
-/**\r
-  * @brief   AF 12 selection\r
-  */\r
-#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
-#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
-#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 13 selection\r
-  */\r
-#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 14 selection\r
-  */\r
-#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
-#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
-#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */\r
-#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 15 selection\r
-  */\r
-#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
-\r
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
-\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/\r
-/**\r
-  * @brief   AF 0 selection\r
-  */\r
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
-#if defined(STM32L476xx) || defined(STM32L486xx)\r
-#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                        */\r
-#endif /* STM32L476xx || STM32L486xx */\r
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
-\r
-/**\r
-  * @brief   AF 1 selection\r
-  */\r
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */\r
-#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */\r
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
-#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 2 selection\r
-  */\r
-#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\r
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 3 selection\r
-  */\r
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\r
-#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 4 selection\r
-  */\r
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 5 selection\r
-  */\r
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 6 selection\r
-  */\r
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 7 selection\r
-  */\r
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
-\r
-/**\r
-  * @brief   AF 8 selection\r
-  */\r
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */\r
-#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
-\r
-\r
-/**\r
-  * @brief   AF 9 selection\r
-  */\r
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
-#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 10 selection\r
-  */\r
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\r
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
-#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
-\r
-#if defined(STM32L476xx) || defined(STM32L486xx)\r
-/**\r
-  * @brief   AF 11 selection\r
-  */\r
-#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */\r
-#endif /* STM32L476xx || STM32L486xx */\r
-\r
-/**\r
-  * @brief   AF 12 selection\r
-  */\r
-#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */\r
-#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */\r
-#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
-#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
-#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 13 selection\r
-  */\r
-#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
-#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */\r
-#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 14 selection\r
-  */\r
-#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
-#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
-#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */\r
-#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 15 selection\r
-  */\r
-#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
-\r
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
-\r
-#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
-/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/\r
-/**\r
-  * @brief   AF 0 selection\r
-  */\r
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
-\r
-/**\r
-  * @brief   AF 1 selection\r
-  */\r
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */\r
-#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */\r
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
-#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 2 selection\r
-  */\r
-#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\r
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\r
-#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 3 selection\r
-  */\r
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\r
-#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_CAN2          ((uint8_t)0x03)  /* CAN2 Alternate Function mapping    */\r
-#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */\r
-#define GPIO_AF3_QUADSPI       ((uint8_t)0x03)  /* QUADSPI Alternate Function mapping */\r
-#define GPIO_AF3_SPI2          ((uint8_t)0x03)  /* SPI2 Alternate Function mapping */\r
-#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 4 selection\r
-  */\r
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */\r
-#define GPIO_AF4_DCMI          ((uint8_t)0x04)  /* DCMI Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 5 selection\r
-  */\r
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r
-#define GPIO_AF5_DCMI          ((uint8_t)0x05)  /* DCMI Alternate Function mapping   */\r
-#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping */\r
-#define GPIO_AF5_QUADSPI       ((uint8_t)0x05)  /* QUADSPI Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 6 selection\r
-  */\r
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
-#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /* I2C3 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 7 selection\r
-  */\r
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\r
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\r
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\r
-\r
-/**\r
-  * @brief   AF 8 selection\r
-  */\r
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */\r
-#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
-#define GPIO_AF8_CAN2          ((uint8_t)0x08)  /* CAN2 Alternate Function mapping    */\r
-\r
-/**\r
-  * @brief   AF 9 selection\r
-  */\r
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
-#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 10 selection\r
-  */\r
-#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\r
-#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */\r
-#define GPIO_AF10_CAN2         ((uint8_t)0x0A)  /* CAN2 Alternate Function mapping */\r
-#define GPIO_AF10_DCMI         ((uint8_t)0x0A)  /* DCMI Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 11 selection\r
-  */\r
-#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 12 selection\r
-  */\r
-#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */\r
-#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */\r
-#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
-#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
-#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
-#define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-#define GPIO_AF12_TIM8_COMP2   ((uint8_t)0x0C)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 13 selection\r
-  */\r
-#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
-#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */\r
-#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 14 selection\r
-  */\r
-#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */\r
-#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */\r
-#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */\r
-#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 15 selection\r
-  */\r
-#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
-\r
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
-\r
-#endif /* STM32L496xx || STM32L4A6xx */\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-/*---STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx--*/\r
-/**\r
-  * @brief   AF 0 selection\r
-  */\r
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\r
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\r
-\r
-/**\r
-  * @brief   AF 1 selection\r
-  */\r
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */\r
-#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */\r
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r
-#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 2 selection\r
-  */\r
-#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */\r
-#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */\r
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\r
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\r
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 3 selection\r
-  */\r
-#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping   */\r
-#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OctoSPI Manager Port 1 Alternate Function mapping */\r
-#define GPIO_AF3_SAI1          ((uint8_t)0x03)  /* SAI1 Alternate Function mapping */\r
-#define GPIO_AF3_SPI2          ((uint8_t)0x03)  /* SPI2 Alternate Function mapping   */\r
-#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */\r
-#define GPIO_AF3_TIM8_COMP1    ((uint8_t)0x03)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_TIM8_COMP2    ((uint8_t)0x03)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 4 selection\r
-  */\r
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r
-#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */\r
-#define GPIO_AF4_DCMI          ((uint8_t)0x04)  /* DCMI Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 5 selection\r
-  */\r
-#define GPIO_AF5_DCMI          ((uint8_t)0x05)  /* DCMI Alternate Function mapping     */\r
-#define GPIO_AF5_DFSDM1        ((uint8_t)0x05)  /* DFSDM1 Alternate Function mapping   */\r
-#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping     */\r
-#define GPIO_AF5_OCTOSPIM_P1   ((uint8_t)0x05)  /* OctoSPI Manager Port 1 Alternate Function mapping */\r
-#define GPIO_AF5_OCTOSPIM_P2   ((uint8_t)0x05)  /* OctoSPI Manager Port 2 Alternate Function mapping */\r
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping     */\r
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping     */\r
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping     */\r
-\r
-/**\r
-  * @brief   AF 6 selection\r
-  */\r
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */\r
-#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /* I2C3 Alternate Function mapping   */\r
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 7 selection\r
-  */\r
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */\r
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */\r
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 8 selection\r
-  */\r
-#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */\r
-#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping  */\r
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */\r
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 9 selection\r
-  */\r
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\r
-#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping  */\r
-#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 10 selection\r
-  */\r
-#define GPIO_AF10_DCMI         ((uint8_t)0x0A)  /* DCMI Alternate Function mapping     */\r
-#define GPIO_AF10_OCTOSPIM_P1  ((uint8_t)0x0A)  /* OctoSPI Manager Port 1 Alternate Function mapping */\r
-#define GPIO_AF10_OCTOSPIM_P2  ((uint8_t)0x0A)  /* OctoSPI Manager Port 2 Alternate Function mapping */\r
-#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 11 selection\r
-  */\r
-#define GPIO_AF11_DSI          ((uint8_t)0x0B)  /* DSI Alternate Function mapping  */\r
-#define GPIO_AF11_LTDC         ((uint8_t)0x0B)  /* LTDC Alternate Function mapping */\r
-\r
-/**\r
-  * @brief   AF 12 selection\r
-  */\r
-#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r
-#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r
-#define GPIO_AF12_DSI          ((uint8_t)0x0C)  /* DSI Alternate Function mapping     */\r
-#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */\r
-#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r
-#define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */\r
-#define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */\r
-#define GPIO_AF12_TIM8_COMP2   ((uint8_t)0x0C)  /* TIM8/COMP2 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 13 selection\r
-  */\r
-#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */\r
-#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */\r
-#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */\r
-\r
-/**\r
-  * @brief   AF 14 selection\r
-  */\r
-#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping  */\r
-#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping  */\r
-#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping  */\r
-#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */\r
-#define GPIO_AF14_TIM8_COMP2   ((uint8_t)0x0E)  /* TIM8/COMP2 Break in Alternate Function mapping   */\r
-\r
-/**\r
-  * @brief   AF 15 selection\r
-  */\r
-#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r
-\r
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index\r
-* @{\r
-  */\r
-#if defined(STM32L412xx) || defined(STM32L422xx)\r
-\r
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
-                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
-                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
-                                      ((__GPIOx__) == (GPIOD))? 3uL : 7uL)\r
-\r
-#endif /* STM32L412xx || STM32L422xx */\r
-\r
-#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)\r
-\r
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
-                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
-                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
-                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
-                                      ((__GPIOx__) == (GPIOE))? 4uL : 7uL)\r
-\r
-#endif /* STM32L431xx || STM32L433xx || STM32L443xx */\r
-\r
-#if defined(STM32L432xx) || defined(STM32L442xx)\r
-\r
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
-                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
-                                      ((__GPIOx__) == (GPIOC))? 2uL : 7uL)\r
-\r
-#endif /* STM32L432xx || STM32L442xx */\r
-\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-\r
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
-                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
-                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
-                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
-                                      ((__GPIOx__) == (GPIOE))? 4uL : 7uL)\r
-\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-\r
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
-                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
-                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
-                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
-                                      ((__GPIOx__) == (GPIOE))? 4uL :\\r
-                                      ((__GPIOx__) == (GPIOF))? 5uL :\\r
-                                      ((__GPIOx__) == (GPIOG))? 6uL : 7uL)\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
-\r
-#if defined(STM32L496xx) || defined(STM32L4A6xx)\r
-\r
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
-                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
-                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
-                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
-                                      ((__GPIOx__) == (GPIOE))? 4uL :\\r
-                                      ((__GPIOx__) == (GPIOF))? 5uL :\\r
-                                      ((__GPIOx__) == (GPIOG))? 6uL :\\r
-                                      ((__GPIOx__) == (GPIOH))? 7uL : 8uL)\r
-\r
-#endif /* STM32L496xx || STM32L4A6xx */\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-\r
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\\r
-                                      ((__GPIOx__) == (GPIOB))? 1uL :\\r
-                                      ((__GPIOx__) == (GPIOC))? 2uL :\\r
-                                      ((__GPIOx__) == (GPIOD))? 3uL :\\r
-                                      ((__GPIOx__) == (GPIOE))? 4uL :\\r
-                                      ((__GPIOx__) == (GPIOF))? 5uL :\\r
-                                      ((__GPIOx__) == (GPIOG))? 6uL :\\r
-                                      ((__GPIOx__) == (GPIOH))? 7uL : 8uL)\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_GPIO_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
deleted file mode 100644 (file)
index d69ccd1..0000000
+++ /dev/null
@@ -1,782 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_i2c.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of I2C HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_I2C_H\r
-#define STM32L4xx_HAL_I2C_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup I2C\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup I2C_Exported_Types I2C Exported Types\r
-  * @{\r
-  */\r
-\r
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r
-  * @brief  I2C Configuration Structure definition\r
-  * @{\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.\r
-                                  This parameter calculated by referring to I2C initialization\r
-                                         section in Reference manual */\r
-\r
-  uint32_t OwnAddress1;         /*!< Specifies the first device own address.\r
-                                  This parameter can be a 7-bit or 10-bit address. */\r
-\r
-  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r
-                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */\r
-\r
-  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.\r
-                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */\r
-\r
-  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected\r
-                                  This parameter can be a 7-bit address. */\r
-\r
-  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected\r
-                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */\r
-\r
-  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.\r
-                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */\r
-\r
-  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.\r
-                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */\r
-\r
-} I2C_InitTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_state_structure_definition HAL state structure definition\r
-  * @brief  HAL State structure definition\r
-  * @note  HAL I2C State value coding follow below described bitmap :\n\r
-  *          b7-b6  Error information\n\r
-  *             00 : No Error\n\r
-  *             01 : Abort (Abort user request on going)\n\r
-  *             10 : Timeout\n\r
-  *             11 : Error\n\r
-  *          b5     Peripheral initialization status\n\r
-  *             0  : Reset (peripheral not initialized)\n\r
-  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n\r
-  *          b4     (not used)\n\r
-  *             x  : Should be set to 0\n\r
-  *          b3\n\r
-  *             0  : Ready or Busy (No Listen mode ongoing)\n\r
-  *             1  : Listen (peripheral in Address Listen Mode)\n\r
-  *          b2     Intrinsic process state\n\r
-  *             0  : Ready\n\r
-  *             1  : Busy (peripheral busy with some configuration or internal operations)\n\r
-  *          b1     Rx state\n\r
-  *             0  : Ready (no Rx operation ongoing)\n\r
-  *             1  : Busy (Rx operation ongoing)\n\r
-  *          b0     Tx state\n\r
-  *             0  : Ready (no Tx operation ongoing)\n\r
-  *             1  : Busy (Tx operation ongoing)\r
-  * @{\r
-  */\r
-typedef enum\r
-{\r
-  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */\r
-  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */\r
-  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */\r
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */\r
-  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */\r
-  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */\r
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission\r
-                                                 process is ongoing                         */\r
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception\r
-                                                 process is ongoing                         */\r
-  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */\r
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */\r
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */\r
-\r
-} HAL_I2C_StateTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition\r
-  * @brief  HAL Mode structure definition\r
-  * @note  HAL I2C Mode value coding follow below described bitmap :\n\r
-  *          b7     (not used)\n\r
-  *             x  : Should be set to 0\n\r
-  *          b6\n\r
-  *             0  : None\n\r
-  *             1  : Memory (HAL I2C communication is in Memory Mode)\n\r
-  *          b5\n\r
-  *             0  : None\n\r
-  *             1  : Slave (HAL I2C communication is in Slave Mode)\n\r
-  *          b4\n\r
-  *             0  : None\n\r
-  *             1  : Master (HAL I2C communication is in Master Mode)\n\r
-  *          b3-b2-b1-b0  (not used)\n\r
-  *             xxxx : Should be set to 0000\r
-  * @{\r
-  */\r
-typedef enum\r
-{\r
-  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */\r
-  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */\r
-  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */\r
-  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */\r
-\r
-} HAL_I2C_ModeTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r
-  * @brief  I2C Error Code definition\r
-  * @{\r
-  */\r
-#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */\r
-#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */\r
-#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */\r
-#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */\r
-#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */\r
-#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */\r
-#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */\r
-#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */\r
-#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\r
-  * @brief  I2C handle Structure definition\r
-  * @{\r
-  */\r
-typedef struct __I2C_HandleTypeDef\r
-{\r
-  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */\r
-\r
-  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */\r
-\r
-  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */\r
-\r
-  uint16_t                   XferSize;       /*!< I2C transfer size                         */\r
-\r
-  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */\r
-\r
-  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can\r
-                                                  be a value of @ref I2C_XFEROPTIONS */\r
-\r
-  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */\r
-\r
-  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */\r
-\r
-  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */\r
-\r
-  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */\r
-\r
-  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */\r
-\r
-  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */\r
-\r
-  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */\r
-\r
-  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */\r
-\r
-  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */\r
-\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */\r
-  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */\r
-  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */\r
-  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */\r
-  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */\r
-  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */\r
-  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */\r
-  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */\r
-  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */\r
-\r
-  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */\r
-\r
-  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */\r
-  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */\r
-\r
-#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-} I2C_HandleTypeDef;\r
-\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  HAL I2C Callback ID enumeration definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */\r
-  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */\r
-  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */\r
-  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */\r
-  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */\r
-  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */\r
-  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */\r
-  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */\r
-  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */\r
-\r
-  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */\r
-  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */\r
-\r
-} HAL_I2C_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  HAL I2C Callback pointer definition\r
-  */\r
-typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */\r
-typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */\r
-\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup I2C_Exported_Constants I2C Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options\r
-  * @{\r
-  */\r
-#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)\r
-#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
-#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
-#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)\r
-#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)\r
-#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)\r
-\r
-/* List of XferOptions in usage of :\r
- * 1- Restart condition in all use cases (direction change or not)\r
- */\r
-#define  I2C_OTHER_FRAME                (0x000000AAU)\r
-#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode\r
-  * @{\r
-  */\r
-#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)\r
-#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode\r
-  * @{\r
-  */\r
-#define I2C_DUALADDRESS_DISABLE         (0x00000000U)\r
-#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks\r
-  * @{\r
-  */\r
-#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)\r
-#define I2C_OA2_MASK01                  ((uint8_t)0x01U)\r
-#define I2C_OA2_MASK02                  ((uint8_t)0x02U)\r
-#define I2C_OA2_MASK03                  ((uint8_t)0x03U)\r
-#define I2C_OA2_MASK04                  ((uint8_t)0x04U)\r
-#define I2C_OA2_MASK05                  ((uint8_t)0x05U)\r
-#define I2C_OA2_MASK06                  ((uint8_t)0x06U)\r
-#define I2C_OA2_MASK07                  ((uint8_t)0x07U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode\r
-  * @{\r
-  */\r
-#define I2C_GENERALCALL_DISABLE         (0x00000000U)\r
-#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode\r
-  * @{\r
-  */\r
-#define I2C_NOSTRETCH_DISABLE           (0x00000000U)\r
-#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size\r
-  * @{\r
-  */\r
-#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)\r
-#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View\r
-  * @{\r
-  */\r
-#define I2C_DIRECTION_TRANSMIT          (0x00000000U)\r
-#define I2C_DIRECTION_RECEIVE           (0x00000001U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode\r
-  * @{\r
-  */\r
-#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD\r
-#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND\r
-#define  I2C_SOFTEND_MODE               (0x00000000U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode\r
-  * @{\r
-  */\r
-#define  I2C_NO_STARTSTOP               (0x00000000U)\r
-#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)\r
-#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)\r
-#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r
-  * @brief I2C Interrupt definition\r
-  *        Elements values convention: 0xXXXXXXXX\r
-  *           - XXXXXXXX  : Interrupt control mask\r
-  * @{\r
-  */\r
-#define I2C_IT_ERRI                     I2C_CR1_ERRIE\r
-#define I2C_IT_TCI                      I2C_CR1_TCIE\r
-#define I2C_IT_STOPI                    I2C_CR1_STOPIE\r
-#define I2C_IT_NACKI                    I2C_CR1_NACKIE\r
-#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE\r
-#define I2C_IT_RXI                      I2C_CR1_RXIE\r
-#define I2C_IT_TXI                      I2C_CR1_TXIE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_Flag_definition I2C Flag definition\r
-  * @{\r
-  */\r
-#define I2C_FLAG_TXE                    I2C_ISR_TXE\r
-#define I2C_FLAG_TXIS                   I2C_ISR_TXIS\r
-#define I2C_FLAG_RXNE                   I2C_ISR_RXNE\r
-#define I2C_FLAG_ADDR                   I2C_ISR_ADDR\r
-#define I2C_FLAG_AF                     I2C_ISR_NACKF\r
-#define I2C_FLAG_STOPF                  I2C_ISR_STOPF\r
-#define I2C_FLAG_TC                     I2C_ISR_TC\r
-#define I2C_FLAG_TCR                    I2C_ISR_TCR\r
-#define I2C_FLAG_BERR                   I2C_ISR_BERR\r
-#define I2C_FLAG_ARLO                   I2C_ISR_ARLO\r
-#define I2C_FLAG_OVR                    I2C_ISR_OVR\r
-#define I2C_FLAG_PECERR                 I2C_ISR_PECERR\r
-#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT\r
-#define I2C_FLAG_ALERT                  I2C_ISR_ALERT\r
-#define I2C_FLAG_BUSY                   I2C_ISR_BUSY\r
-#define I2C_FLAG_DIR                    I2C_ISR_DIR\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-\r
-/** @defgroup I2C_Exported_Macros I2C Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief Reset I2C handle state.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @retval None\r
-  */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \\r
-                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \\r
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \\r
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \\r
-                                                                  } while(0)\r
-#else\r
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r
-#endif\r
-\r
-/** @brief  Enable the specified I2C interrupt.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.\r
-  *        This parameter can be one of the following values:\r
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r
-\r
-/** @brief  Disable the specified I2C interrupt.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.\r
-  *        This parameter can be one of the following values:\r
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r
-\r
-/** @brief  Check whether the specified I2C interrupt source is enabled or not.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r
-  *\r
-  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
-  */\r
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
-\r
-/** @brief  Check whether the specified I2C flag is set or not.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @param  __FLAG__ specifies the flag to check.\r
-  *        This parameter can be one of the following values:\r
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r
-  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status\r
-  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty\r
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r
-  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)\r
-  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload\r
-  *            @arg @ref I2C_FLAG_BERR    Bus error\r
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun\r
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r
-  *            @arg @ref I2C_FLAG_BUSY    Bus busy\r
-  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)\r
-  *\r
-  * @retval The new state of __FLAG__ (SET or RESET).\r
-  */\r
-#define I2C_FLAG_MASK  (0x0001FFFFU)\r
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)\r
-\r
-/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @param  __FLAG__ specifies the flag to clear.\r
-  *          This parameter can be any combination of the following values:\r
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r
-  *            @arg @ref I2C_FLAG_BERR    Bus error\r
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun\r
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \\r
-                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))\r
-\r
-/** @brief  Enable the specified I2C peripheral.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))\r
-\r
-/** @brief  Disable the specified I2C peripheral.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
-\r
-/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.\r
-  * @param  __HANDLE__ specifies the I2C Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include I2C HAL Extended module */\r
-#include "stm32l4xx_hal_i2c_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup I2C_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  * @{\r
-  */\r
-/* Initialization and de-initialization functions******************************/\r
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r
-\r
-/* Callbacks Register/UnRegister functions  ***********************************/\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);\r
-\r
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
-  * @{\r
-  */\r
-/* IO operation functions  ****************************************************/\r
-/******* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r
-\r
-/******* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
-\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\r
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\r
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\r
-\r
-/******* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
-\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
- * @{\r
- */\r
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\r
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
-  * @{\r
-  */\r
-/* Peripheral State, Mode and Error functions  *********************************/\r
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r
-HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\r
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup I2C_Private_Constants I2C Private Constants\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup I2C_Private_Macro I2C Private Macros\r
-  * @{\r
-  */\r
-\r
-#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\r
-                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r
-\r
-#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\r
-                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r
-\r
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \\r
-                                         ((MASK) == I2C_OA2_MASK01) || \\r
-                                         ((MASK) == I2C_OA2_MASK02) || \\r
-                                         ((MASK) == I2C_OA2_MASK03) || \\r
-                                         ((MASK) == I2C_OA2_MASK04) || \\r
-                                         ((MASK) == I2C_OA2_MASK05) || \\r
-                                         ((MASK) == I2C_OA2_MASK06) || \\r
-                                         ((MASK) == I2C_OA2_MASK07))\r
-\r
-#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \\r
-                                         ((CALL) == I2C_GENERALCALL_ENABLE))\r
-\r
-#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\r
-                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r
-\r
-#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\r
-                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r
-\r
-#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \\r
-                                         ((MODE) == I2C_AUTOEND_MODE) || \\r
-                                         ((MODE) == I2C_SOFTEND_MODE))\r
-\r
-#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \\r
-                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \\r
-                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \\r
-                                         ((REQUEST) == I2C_NO_STARTSTOP))\r
-\r
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \\r
-                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \\r
-                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \\r
-                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \\r
-                                                   ((REQUEST) == I2C_LAST_FRAME)           || \\r
-                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \\r
-                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))\r
-\r
-#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \\r
-                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))\r
-\r
-#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r
-\r
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))\r
-#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))\r
-#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)\r
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))\r
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))\r
-\r
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)\r
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)\r
-\r
-#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))\r
-#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))\r
-\r
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\r
-                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r
-\r
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)\r
-#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private Functions ---------------------------------------------------------*/\r
-/** @defgroup I2C_Private_Functions I2C Private Functions\r
-  * @{\r
-  */\r
-/* Private functions are defined in stm32l4xx_hal_i2c.c file */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* STM32L4xx_HAL_I2C_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
deleted file mode 100644 (file)
index 690623d..0000000
+++ /dev/null
@@ -1,173 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_i2c_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of I2C HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_I2C_EX_H\r
-#define STM32L4xx_HAL_I2C_EX_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup I2CEx\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter\r
-  * @{\r
-  */\r
-#define I2C_ANALOGFILTER_ENABLE         0x00000000U\r
-#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus\r
-  * @{\r
-  */\r
-#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */\r
-#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */\r
-#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */\r
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)\r
-#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */\r
-#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */\r
-#else\r
-#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */\r
-#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */\r
-#endif\r
-#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */\r
-#if defined(SYSCFG_CFGR1_I2C2_FMP)\r
-#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */\r
-#else\r
-#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */\r
-#endif\r
-#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */\r
-#if defined(SYSCFG_CFGR1_I2C4_FMP)\r
-#define I2C_FASTMODEPLUS_I2C4           SYSCFG_CFGR1_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */\r
-#else\r
-#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions\r
-  * @brief    Extended features functions\r
-  * @{\r
-  */\r
-\r
-/* Peripheral Control functions  ************************************************/\r
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);\r
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);\r
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);\r
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);\r
-\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros\r
-  * @{\r
-  */\r
-#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\r
-                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r
-\r
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)\r
-\r
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \\r
-                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \\r
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \\r
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \\r
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \\r
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \\r
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \\r
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)    || \\r
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))\r
-\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private Functions ---------------------------------------------------------*/\r
-/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions\r
-  * @{\r
-  */\r
-/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_I2C_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h
deleted file mode 100644 (file)
index bc1975a..0000000
+++ /dev/null
@@ -1,1004 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pcd.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of PCD HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_PCD_H\r
-#define STM32L4xx_HAL_PCD_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_ll_usb.h"\r
-\r
-#if defined (USB) || defined (USB_OTG_FS)\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup PCD\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup PCD_Exported_Types PCD Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  PCD State structure definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_PCD_STATE_RESET   = 0x00,\r
-  HAL_PCD_STATE_READY   = 0x01,\r
-  HAL_PCD_STATE_ERROR   = 0x02,\r
-  HAL_PCD_STATE_BUSY    = 0x03,\r
-  HAL_PCD_STATE_TIMEOUT = 0x04\r
-} PCD_StateTypeDef;\r
-\r
-/* Device LPM suspend state */\r
-typedef enum\r
-{\r
-  LPM_L0 = 0x00, /* on */\r
-  LPM_L1 = 0x01, /* LPM L1 sleep */\r
-  LPM_L2 = 0x02, /* suspend */\r
-  LPM_L3 = 0x03, /* off */\r
-} PCD_LPM_StateTypeDef;\r
-\r
-typedef enum\r
-{\r
-  PCD_LPM_L0_ACTIVE = 0x00, /* on */\r
-  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */\r
-} PCD_LPM_MsgTypeDef;\r
-\r
-typedef enum\r
-{\r
-  PCD_BCD_ERROR                     = 0xFF,\r
-  PCD_BCD_CONTACT_DETECTION         = 0xFE,\r
-  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,\r
-  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,\r
-  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,\r
-  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,\r
-\r
-} PCD_BCD_MsgTypeDef;\r
-\r
-#if defined (USB)\r
-\r
-#endif /* defined (USB) */\r
-#if defined (USB_OTG_FS)\r
-typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;\r
-typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;\r
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;\r
-#endif /* defined (USB_OTG_FS) */\r
-#if defined (USB)\r
-typedef USB_TypeDef        PCD_TypeDef;\r
-typedef USB_CfgTypeDef     PCD_InitTypeDef;\r
-typedef USB_EPTypeDef      PCD_EPTypeDef;\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @brief  PCD Handle Structure definition\r
-  */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-typedef struct __PCD_HandleTypeDef\r
-#else\r
-typedef struct\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-{\r
-  PCD_TypeDef             *Instance;   /*!< Register base address              */\r
-  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */\r
-  __IO uint8_t            USB_Address; /*!< USB Address                        */\r
-#if defined (USB_OTG_FS)\r
-  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */\r
-  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */\r
-#endif /* defined (USB_OTG_FS) */\r
-#if defined (USB)\r
-  PCD_EPTypeDef           IN_ep[8];   /*!< IN endpoint parameters             */\r
-  PCD_EPTypeDef           OUT_ep[8];  /*!< OUT endpoint parameters            */\r
-#endif /* defined (USB) */\r
-  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */\r
-  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */\r
-  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */\r
-  uint32_t                Setup[12];   /*!< Setup packet buffer                */\r
-  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */\r
-  uint32_t                BESL;\r
-\r
-\r
-  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .\r
-                                       This parameter can be set to ENABLE or DISABLE        */\r
-\r
-  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.\r
-                                       This parameter can be set to ENABLE or DISABLE        */\r
-  void                    *pData;      /*!< Pointer to upper stack Handler */\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */\r
-  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */\r
-  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */\r
-  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */\r
-  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */\r
-  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */\r
-  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */\r
-\r
-  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */\r
-  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */\r
-  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */\r
-  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */\r
-  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */\r
-  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */\r
-\r
-  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */\r
-  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-} PCD_HandleTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include PCD HAL Extended module */\r
-#include "stm32l4xx_hal_pcd_ex.h"\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup PCD_Exported_Constants PCD Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PCD_Speed PCD Speed\r
-  * @{\r
-  */\r
-#define PCD_SPEED_FULL               USBD_FS_SPEED\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PCD_PHY_Module PCD PHY Module\r
-  * @{\r
-  */\r
-#define PCD_PHY_ULPI                 1U\r
-#define PCD_PHY_EMBEDDED             2U\r
-#define PCD_PHY_UTMI                 3U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PCD_Error_Code_definition PCD Error Code definition\r
-  * @brief  PCD Error Code definition\r
-  * @{\r
-  */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup PCD_Exported_Macros PCD Exported Macros\r
- *  @brief macros to handle interrupts and specific clock configurations\r
- * @{\r
- */\r
-#if defined (USB_OTG_FS)\r
-#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)\r
-#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)\r
-\r
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))\r
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)\r
-\r
-\r
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \\r
-                                                          ~(USB_OTG_PCGCCTL_STOPCLK)\r
-\r
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK\r
-\r
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)\r
-\r
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE\r
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-#define __HAL_PCD_ENABLE(__HANDLE__)                                  (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)\r
-#define __HAL_PCD_DISABLE(__HANDLE__)                                 (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)\r
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))\r
-\r
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE\r
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions\r
-  * @{\r
-  */\r
-\r
-/* Initialization/de-initialization functions  ********************************/\r
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);\r
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition\r
-  * @brief  HAL USB OTG PCD Callback ID enumeration definition\r
-  * @{\r
-  */\r
-typedef enum\r
-{\r
-  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */\r
-  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */\r
-  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */\r
-  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */\r
-  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */\r
-  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */\r
-  HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */\r
-\r
-  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */\r
-  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */\r
-\r
-} HAL_PCD_CallbackIDTypeDef;\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition\r
-  * @brief  HAL USB OTG PCD Callback pointer definition\r
-  * @{\r
-  */\r
-\r
-typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */\r
-typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */\r
-typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */\r
-typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */\r
-typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */\r
-typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */\r
-typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);\r
-\r
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);\r
-\r
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);\r
-\r
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);\r
-\r
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);\r
-\r
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);\r
-\r
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* I/O operation functions  ***************************************************/\r
-/* Non-Blocking mode: Interrupt */\r
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);\r
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);\r
-\r
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);\r
-\r
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Peripheral Control functions  **********************************************/\r
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);\r
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);\r
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);\r
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);\r
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r
-uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Peripheral State functions  ************************************************/\r
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions\r
-  * @{\r
-  */\r
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup PCD_Private_Constants PCD Private Constants\r
-  * @{\r
-  */\r
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt\r
-  * @{\r
-  */\r
-#if defined (USB_OTG_FS)\r
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U\r
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU\r
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U\r
-\r
-#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 17)  /*!< USB FS EXTI Line WakeUp Interrupt */\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-#define  USB_WAKEUP_EXTI_LINE                                         (0x1U << 17)  /*!< USB FS EXTI Line WakeUp Interrupt */\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#if defined (USB)\r
-/** @defgroup PCD_EP0_MPS PCD EP0 MPS\r
-  * @{\r
-  */\r
-#define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64\r
-#define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32\r
-#define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16\r
-#define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PCD_ENDP PCD ENDP\r
-  * @{\r
-  */\r
-#define PCD_ENDP0                                                     0U\r
-#define PCD_ENDP1                                                     1U\r
-#define PCD_ENDP2                                                     2U\r
-#define PCD_ENDP3                                                     3U\r
-#define PCD_ENDP4                                                     4U\r
-#define PCD_ENDP5                                                     5U\r
-#define PCD_ENDP6                                                     6U\r
-#define PCD_ENDP7                                                     7U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind\r
-  * @{\r
-  */\r
-#define PCD_SNG_BUF                                                   0U\r
-#define PCD_DBL_BUF                                                   1U\r
-/**\r
-  * @}\r
-  */\r
-#endif /* defined (USB) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined (USB_OTG_FS)\r
-#ifndef USB_OTG_DOEPINT_OTEPSPR\r
-#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */\r
-#endif\r
-\r
-#ifndef USB_OTG_DOEPMSK_OTEPSPRM\r
-#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */\r
-#endif\r
-\r
-#ifndef USB_OTG_DOEPINT_NAK\r
-#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */\r
-#endif\r
-\r
-#ifndef USB_OTG_DOEPMSK_NAKM\r
-#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */\r
-#endif\r
-\r
-#ifndef USB_OTG_DOEPINT_STPKTRX\r
-#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */\r
-#endif\r
-\r
-#ifndef USB_OTG_DOEPMSK_NYETM\r
-#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */\r
-#endif\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup PCD_Private_Macros PCD Private Macros\r
- * @{\r
- */\r
-#if defined (USB)\r
-/********************  Bit definition for USB_COUNTn_RX register  *************/\r
-#define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)\r
-#define USB_CNTRX_BLSIZE                      (0x1U << 15)\r
-\r
-/* SetENDPOINT */\r
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue)  (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))\r
-\r
-/* GetENDPOINT */\r
-#define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))\r
-\r
-/* ENDPOINT transfer */\r
-#define USB_EP0StartXfer                          USB_EPStartXfer\r
-\r
-/**\r
-  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wType Endpoint Type.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \\r
-                                             ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))\r
-\r
-/**\r
-  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval Endpoint Type\r
-  */\r
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)\r
-\r
-/**\r
-  * @brief free buffer used from the application realizing it to the line\r
-  *         toggles bit SW_BUF in the double buffered endpoint register\r
-  * @param USBx USB device.\r
-  * @param   bEpNum, bDir\r
-  * @retval None\r
-  */\r
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \\r
-  if ((bDir) == 0U) \\r
-  { \\r
-    /* OUT double buffered endpoint */ \\r
-    PCD_TX_DTOG((USBx), (bEpNum)); \\r
-  } \\r
-  else if ((bDir) == 1U) \\r
-  { \\r
-    /* IN double buffered endpoint */ \\r
-    PCD_RX_DTOG((USBx), (bEpNum)); \\r
-  } \\r
-} while(0)\r
-\r
-/**\r
-  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wState new state\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \\r
-   register uint16_t _wRegVal; \\r
-   \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \\r
-   /* toggle first bit ? */ \\r
-   if ((USB_EPTX_DTOG1 & (wState))!= 0U) \\r
-   { \\r
-      _wRegVal ^= USB_EPTX_DTOG1; \\r
-   } \\r
-   /* toggle second bit ?  */ \\r
-   if ((USB_EPTX_DTOG2 & (wState))!= 0U) \\r
-   { \\r
-      _wRegVal ^= USB_EPTX_DTOG2; \\r
-   } \\r
-   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
-  } while(0) /* PCD_SET_EP_TX_STATUS */\r
-\r
-/**\r
-  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wState new state\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \\r
-    /* toggle first bit ? */ \\r
-    if ((USB_EPRX_DTOG1 & (wState))!= 0U) \\r
-    { \\r
-       _wRegVal ^= USB_EPRX_DTOG1; \\r
-    } \\r
-    /* toggle second bit ? */ \\r
-    if ((USB_EPRX_DTOG2 & (wState))!= 0U) \\r
-    { \\r
-       _wRegVal ^= USB_EPRX_DTOG2; \\r
-    } \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
-  } while(0) /* PCD_SET_EP_RX_STATUS */\r
-\r
-/**\r
-  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wStaterx new state.\r
-  * @param  wStatetx new state.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \\r
-    /* toggle first bit ? */ \\r
-    if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \\r
-    { \\r
-      _wRegVal ^= USB_EPRX_DTOG1; \\r
-    } \\r
-    /* toggle second bit ? */ \\r
-    if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \\r
-    { \\r
-      _wRegVal ^= USB_EPRX_DTOG2; \\r
-    } \\r
-    /* toggle first bit ? */ \\r
-    if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \\r
-    { \\r
-      _wRegVal ^= USB_EPTX_DTOG1; \\r
-    } \\r
-    /* toggle second bit ?  */ \\r
-    if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \\r
-    { \\r
-      _wRegVal ^= USB_EPTX_DTOG2; \\r
-    } \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
-  } while(0) /* PCD_SET_EP_TXRX_STATUS */\r
-\r
-/**\r
-  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]\r
-  *         /STAT_RX[1:0])\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval status\r
-  */\r
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)\r
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)\r
-\r
-/**\r
-  * @brief  sets directly the VALID tx/rx-status into the endpoint register\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))\r
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))\r
-\r
-/**\r
-  * @brief  checks stall condition in an endpoint.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval TRUE = endpoint in stall condition.\r
-  */\r
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \\r
-                                   == USB_EP_TX_STALL)\r
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \\r
-                                   == USB_EP_RX_STALL)\r
-\r
-/**\r
-  * @brief  set & clear EP_KIND bit.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_KIND(USBx, bEpNum) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \\r
-  } while(0) /* PCD_SET_EP_KIND */\r
-\r
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
-  } while(0) /* PCD_CLEAR_EP_KIND */\r
-\r
-/**\r
-  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))\r
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))\r
-\r
-/**\r
-  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))\r
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))\r
-\r
-/**\r
-  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \\r
-  } while(0) /* PCD_CLEAR_RX_EP_CTR */\r
-\r
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \\r
-  } while(0) /* PCD_CLEAR_TX_EP_CTR */\r
-\r
-/**\r
-  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_RX_DTOG(USBx, bEpNum) do { \\r
-    register uint16_t _wEPVal; \\r
-    \\r
-    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \\r
-  } while(0) /* PCD_RX_DTOG */\r
-\r
-#define PCD_TX_DTOG(USBx, bEpNum) do { \\r
-    register uint16_t _wEPVal; \\r
-    \\r
-    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \\r
-  } while(0) /* PCD_TX_DTOG */\r
-/**\r
-  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \\r
-    \\r
-    if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\\r
-    { \\r
-      PCD_RX_DTOG((USBx), (bEpNum)); \\r
-    } \\r
-  } while(0) /* PCD_CLEAR_RX_DTOG */\r
-\r
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \\r
-    \\r
-    if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\\r
-    { \\r
-      PCD_TX_DTOG((USBx), (bEpNum)); \\r
-    } \\r
-  } while(0) /* PCD_CLEAR_TX_DTOG */\r
-\r
-/**\r
-  * @brief  Sets address in an endpoint register.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  bAddr Address.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \\r
-    register uint16_t _wRegVal; \\r
-    \\r
-    _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \\r
-    \\r
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \\r
-  } while(0) /* PCD_SET_EP_ADDRESS */\r
-\r
-/**\r
-  * @brief  Gets address in an endpoint register.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))\r
-\r
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))\r
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))\r
-\r
-/**\r
-  * @brief  sets address of the tx/rx buffer.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wAddr address to be set (must be word aligned).\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \\r
-  register uint16_t *_wRegVal; \\r
-  register uint32_t _wRegBase = (uint32_t)USBx; \\r
-  \\r
-  _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
-  _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \\r
-  *_wRegVal = ((wAddr) >> 1) << 1; \\r
-} while(0) /* PCD_SET_EP_TX_ADDRESS */\r
-\r
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \\r
-  register uint16_t *_wRegVal; \\r
-  register uint32_t _wRegBase = (uint32_t)USBx; \\r
-  \\r
-  _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
-  _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \\r
-  *_wRegVal = ((wAddr) >> 1) << 1; \\r
-} while(0) /* PCD_SET_EP_RX_ADDRESS */\r
-\r
-/**\r
-  * @brief  Gets address of the tx/rx buffer.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval address of the buffer.\r
-  */\r
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))\r
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))\r
-\r
-/**\r
-  * @brief  Sets counter of rx buffer with no. of blocks.\r
-  * @param  pdwReg Register pointer\r
-  * @param  wCount Counter.\r
-  * @param  wNBlocks no. of Blocks.\r
-  * @retval None\r
-  */\r
-#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \\r
-    (wNBlocks) = (wCount) >> 5; \\r
-    *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \\r
-  } while(0) /* PCD_CALC_BLK32 */\r
-\r
-#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \\r
-    (wNBlocks) = (wCount) >> 1; \\r
-    if (((wCount) & 0x1U) != 0U) \\r
-    { \\r
-      (wNBlocks)++; \\r
-    } \\r
-    *(pdwReg) = (uint16_t)((wNBlocks) << 10); \\r
-  } while(0) /* PCD_CALC_BLK2 */\r
-\r
-#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount)  do { \\r
-    uint32_t wNBlocks; \\r
-    if ((wCount) == 0U) \\r
-    { \\r
-      *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \\r
-      *(pdwReg) |= USB_CNTRX_BLSIZE; \\r
-    } \\r
-    else if((wCount) < 62U) \\r
-    { \\r
-      PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \\r
-    } \\r
-    else \\r
-    { \\r
-      PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \\r
-    } \\r
-  } while(0) /* PCD_SET_EP_CNT_RX_REG */\r
-\r
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \\r
-     register uint32_t _wRegBase = (uint32_t)(USBx); \\r
-     uint16_t *pdwReg; \\r
-     \\r
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
-    pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \\r
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  sets counter for the tx/rx buffer.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wCount Counter value.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \\r
-    register uint32_t _wRegBase = (uint32_t)(USBx); \\r
-    uint16_t *_wRegVal; \\r
-    \\r
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
-    _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \\r
-    *_wRegVal = (uint16_t)(wCount); \\r
-} while(0)\r
-\r
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \\r
-    register uint32_t _wRegBase = (uint32_t)(USBx); \\r
-    uint16_t *_wRegVal; \\r
-    \\r
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \\r
-    _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \\r
-    PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \\r
-} while(0)\r
-\r
-/**\r
-  * @brief  gets counter of the tx buffer.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval Counter value\r
-  */\r
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)\r
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)\r
-\r
-/**\r
-  * @brief  Sets buffer 0/1 address in a double buffer endpoint.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wBuf0Addr buffer 0 address.\r
-  * @retval Counter value\r
-  */\r
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \\r
-    PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \\r
-  } while(0) /* PCD_SET_EP_DBUF0_ADDR */\r
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \\r
-    PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \\r
-  } while(0) /* PCD_SET_EP_DBUF1_ADDR */\r
-\r
-/**\r
-  * @brief  Sets addresses in a double buffer endpoint.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  wBuf0Addr: buffer 0 address.\r
-  * @param  wBuf1Addr = buffer 1 address.\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \\r
-    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \\r
-    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \\r
-  } while(0) /* PCD_SET_EP_DBUF_ADDR */\r
-\r
-/**\r
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))\r
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))\r
-\r
-/**\r
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @param  bDir endpoint dir  EP_DBUF_OUT = OUT\r
-  *         EP_DBUF_IN  = IN\r
-  * @param  wCount: Counter value\r
-  * @retval None\r
-  */\r
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \\r
-    if ((bDir) == 0U) \\r
-      /* OUT endpoint */ \\r
-    { \\r
-      PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \\r
-    } \\r
-    else \\r
-    { \\r
-      if ((bDir) == 1U) \\r
-      { \\r
-        /* IN endpoint */ \\r
-        PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \\r
-      } \\r
-    } \\r
-  } while(0) /* SetEPDblBuf0Count*/\r
-\r
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \\r
-    register uint32_t _wBase = (uint32_t)(USBx); \\r
-    uint16_t *_wEPRegVal; \\r
-    \\r
-    if ((bDir) == 0U) \\r
-    { \\r
-      /* OUT endpoint */ \\r
-      PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \\r
-    } \\r
-    else \\r
-    { \\r
-      if ((bDir) == 1U) \\r
-      { \\r
-        /* IN endpoint */ \\r
-        _wBase += (uint32_t)(USBx)->BTABLE; \\r
-        _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \\r
-        *_wEPRegVal = (uint16_t)(wCount); \\r
-      } \\r
-    } \\r
-  } while(0) /* SetEPDblBuf1Count */\r
-\r
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \\r
-    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \\r
-    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \\r
-  } while(0) /* PCD_SET_EP_DBUF_CNT  */\r
-\r
-/**\r
-  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.\r
-  * @param  USBx USB peripheral instance register address.\r
-  * @param  bEpNum Endpoint Number.\r
-  * @retval None\r
-  */\r
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))\r
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))\r
-\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* defined (USB) || defined (USB_OTG_FS) */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_PCD_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h
deleted file mode 100644 (file)
index ac1529e..0000000
+++ /dev/null
@@ -1,97 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pcd_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of PCD HAL Extension module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_PCD_EX_H\r
-#define STM32L4xx_HAL_PCD_EX_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-#if defined (USB) || defined (USB_OTG_FS)\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup PCDEx\r
-  * @{\r
-  */\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-/* Exported macros -----------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions\r
-  * @{\r
-  */\r
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r
-  * @{\r
-  */\r
-\r
-#if defined (USB_OTG_FS)\r
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);\r
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,\r
-                                       uint16_t ep_addr,\r
-                                       uint16_t ep_kind,\r
-                                       uint32_t pmaadress);\r
-#endif /* defined (USB) */\r
-\r
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);\r
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);\r
-\r
-\r
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);\r
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);\r
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);\r
-\r
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);\r
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* defined (USB) || defined (USB_OTG_FS) */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* STM32L4xx_HAL_PCD_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
deleted file mode 100644 (file)
index 1e20ff7..0000000
+++ /dev/null
@@ -1,414 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pwr.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of PWR HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_PWR_H\r
-#define __STM32L4xx_HAL_PWR_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup PWR\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Exported_Types PWR Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  PWR PVD configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.\r
-                            This parameter can be a value of @ref PWR_PVD_detection_level. */\r
-\r
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.\r
-                           This parameter can be a value of @ref PWR_PVD_Mode. */\r
-}PWR_PVDTypeDef;\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
-  * @{\r
-  */\r
-\r
-\r
-/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels\r
-  * @{\r
-  */\r
-#define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */\r
-#define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */\r
-#define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */\r
-#define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */\r
-#define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */\r
-#define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */\r
-#define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */\r
-#define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode\r
-  * @{\r
-  */\r
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */\r
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */\r
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */\r
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */\r
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */\r
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-\r
-\r
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode\r
-  * @{\r
-  */\r
-#define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */\r
-#define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry\r
-  * @{\r
-  */\r
-#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */\r
-#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry\r
-  * @{\r
-  */\r
-#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */\r
-#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line\r
-  * @{\r
-  */\r
-#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line\r
-  * @{\r
-  */\r
-#define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup PWR_Exported_Macros  PWR Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Check whether or not a specific PWR flag is set.\r
-  * @param  __FLAG__: specifies the flag to check.\r
-  *           This parameter can be one of the following values:\r
-  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 1.\r
-  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 2.\r
-  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 3.\r
-  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 4.\r
-  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 5.\r
-  *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system\r
-  *                  entered StandBy mode.\r
-  *            @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates\r
-  *                 that external switch can be closed to connect to the external SMPS, when the Range 2\r
-  *                 of internal regulator is ready.\r
-  *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on\r
-  *                 the internal wakeup line.\r
-  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the\r
-  *                 low-power regulator is ready.\r
-  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the\r
-  *                 regulator is ready in main mode or is in low-power mode.\r
-  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready\r
-  *                 in the selected voltage range or is still changing to the required voltage level.\r
-  *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is\r
-  *                  below or above the selected PVD threshold.\r
-  *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is\r
-  *                  is below or above PVM1 threshold (applicable when USB feature is supported).\r
-  @if STM32L486xx\r
-  *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is\r
-  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device).\r
-  @endif\r
-  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is\r
-  *                  is below or above PVM3 threshold.\r
-  *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is\r
-  *                  is below or above PVM4 threshold.\r
-  *\r
-  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\\r
-                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\\r
-                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )\r
-\r
-/** @brief  Clear a specific PWR flag.\r
-  * @param  __FLAG__: specifies the flag to clear.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 1.\r
-  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 2.\r
-  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 3.\r
-  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 4.\r
-  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event\r
-  *                  was received from the WKUP pin 5.\r
-  *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.\r
-  *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system\r
-  *                  entered Standby mode.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\\r
-                                         (PWR->SCR  = (__FLAG__)) :\\r
-                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )\r
-/**\r
-  * @brief Enable the PVD Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
-  * @brief Disable the PVD Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
-  * @brief Enable the PVD Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)\r
-\r
-/**\r
-  * @brief Disable the PVD Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)\r
-\r
-/**\r
-  * @brief Enable the PVD Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
-  * @brief Enable the PVD Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)\r
-\r
-\r
-/**\r
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)\r
-\r
-\r
-/**\r
-  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                   \\r
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                    \\r
-    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Generate a Software interrupt on selected EXTI line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
-  * @brief Check whether or not the PVD EXTI interrupt flag is set.\r
-  * @retval EXTI PVD Line Status.\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
-  * @brief Clear the PVD EXTI interrupt flag.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/* Private macros --------------------------------------------------------*/\r
-/** @addtogroup  PWR_Private_Macros   PWR Private Macros\r
-  * @{\r
-  */\r
-\r
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
-\r
-#define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\\r
-                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\\r
-                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\\r
-                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\\r
-                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\\r
-                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\\r
-                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))\r
-\r
-#define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
-                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
-\r
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
-\r
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include PWR HAL Extended module */\r
-#include "stm32l4xx_hal_pwr_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  * @{\r
-  */\r
-\r
-/* Initialization and de-initialization functions *******************************/\r
-void HAL_PWR_DeInit(void);\r
-void HAL_PWR_EnableBkUpAccess(void);\r
-void HAL_PWR_DisableBkUpAccess(void);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
-  * @{\r
-  */\r
-\r
-/* Peripheral Control functions  ************************************************/\r
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
-void HAL_PWR_EnablePVD(void);\r
-void HAL_PWR_DisablePVD(void);\r
-\r
-\r
-/* WakeUp pins configuration functions ****************************************/\r
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
-\r
-/* Low Power modes configuration functions ************************************/\r
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
-void HAL_PWR_EnterSTANDBYMode(void);\r
-\r
-void HAL_PWR_EnableSleepOnExit(void);\r
-void HAL_PWR_DisableSleepOnExit(void);\r
-void HAL_PWR_EnableSEVOnPend(void);\r
-void HAL_PWR_DisableSEVOnPend(void);\r
-\r
-void HAL_PWR_PVDCallback(void);\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* __STM32L4xx_HAL_PWR_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
deleted file mode 100644 (file)
index b6364c5..0000000
+++ /dev/null
@@ -1,907 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pwr_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of PWR HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_PWR_EX_H\r
-#define __STM32L4xx_HAL_PWR_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup PWREx\r
-  * @{\r
-  */\r
-\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup PWREx_Exported_Types PWR Extended Exported Types\r
-  * @{\r
-  */\r
-\r
-\r
-/**\r
-  * @brief  PWR PVM configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.\r
-                           This parameter can be a value of @ref PWREx_PVM_Type.\r
-                           @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).\r
-@if STM32L486xx\r
-                           @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).\r
-@endif\r
-                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.\r
-                           @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */\r
-\r
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.\r
-                           This parameter can be a value of @ref PWREx_PVM_Mode. */\r
-}PWR_PVMTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants\r
-  * @{\r
-  */\r
-#define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins\r
-  * @{\r
-  */\r
-#define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */\r
-#define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */\r
-#define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */\r
-#define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */\r
-#define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */\r
-#define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type\r
-  * @{\r
-  */\r
-#if defined(PWR_CR2_PVME1)\r
-#define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */\r
-#endif /* PWR_CR2_PVME1 */\r
-#if defined(PWR_CR2_PVME2)\r
-#define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */\r
-#endif /* PWR_CR2_PVME2 */\r
-#define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */\r
-#define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode\r
-  * @{\r
-  */\r
-#define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */\r
-#define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */\r
-#define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */\r
-#define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
-#define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */\r
-#define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */\r
-#define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-\r
-/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale\r
-  * @{\r
-  */\r
-#if defined(PWR_CR5_R1MODE)\r
-#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST  ((uint32_t)0x00000000)  /*!< Voltage scaling range 1 boost mode  */\r
-#endif\r
-#define PWR_REGULATOR_VOLTAGE_SCALE1        PWR_CR1_VOS_0           /*!< Voltage scaling range 1 normal mode */\r
-#define PWR_REGULATOR_VOLTAGE_SCALE2        PWR_CR1_VOS_1           /*!< Voltage scaling range 2             */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection\r
-  * @{\r
-  */\r
-#define PWR_BATTERY_CHARGING_RESISTOR_5          ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor   */\r
-#define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging\r
-  * @{\r
-  */\r
-#define PWR_BATTERY_CHARGING_DISABLE        ((uint32_t)0x00000000)\r
-#define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode\r
-  * @{\r
-  */\r
-#define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */\r
-#define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */\r
-#define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */\r
-#define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */\r
-#define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */\r
-#define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */\r
-#define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */\r
-#define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */\r
-#define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */\r
-#define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */\r
-#define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */\r
-#define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */\r
-#define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */\r
-#define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */\r
-#define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */\r
-#define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_GPIO GPIO port\r
-  * @{\r
-  */\r
-#define PWR_GPIO_A   0x00000000U      /*!< GPIO port A */\r
-#define PWR_GPIO_B   0x00000001U      /*!< GPIO port B */\r
-#define PWR_GPIO_C   0x00000002U      /*!< GPIO port C */\r
-#if defined(GPIOD_BASE)\r
-#define PWR_GPIO_D   0x00000003U      /*!< GPIO port D */\r
-#endif\r
-#if defined(GPIOE_BASE)\r
-#define PWR_GPIO_E   0x00000004U      /*!< GPIO port E */\r
-#endif\r
-#if defined(GPIOF_BASE)\r
-#define PWR_GPIO_F   0x00000005U      /*!< GPIO port F */\r
-#endif\r
-#if defined(GPIOG_BASE)\r
-#define PWR_GPIO_G   0x00000006U      /*!< GPIO port G */\r
-#endif\r
-#define PWR_GPIO_H   0x00000007U      /*!< GPIO port H */\r
-#if defined(GPIOI_BASE)\r
-#define PWR_GPIO_I   0x00000008U      /*!< GPIO port I */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines\r
-  * @{\r
-  */\r
-#if defined(PWR_CR2_PVME1)\r
-#define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */\r
-#endif /* PWR_CR2_PVME1 */\r
-#if defined(PWR_CR2_PVME2)\r
-#define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */\r
-#endif /* PWR_CR2_PVME2 */\r
-#define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */\r
-#define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines\r
-  * @{\r
-  */\r
-#if defined(PWR_CR2_PVME1)\r
-#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */\r
-#endif /* PWR_CR2_PVME1 */\r
-#if defined(PWR_CR2_PVME2)\r
-#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */\r
-#endif /* PWR_CR2_PVME2 */\r
-#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */\r
-#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_Flag  PWR Status Flags\r
-  *        Elements values convention: 0000 0000 0XXY YYYYb\r
-  *           - Y YYYY  : Flag position in the XX register (5 bits)\r
-  *           - XX  : Status register (2 bits)\r
-  *                 - 01: SR1 register\r
-  *                 - 10: SR2 register\r
-  *        The only exception is PWR_FLAG_WU, encompassing all\r
-  *        wake-up flags and set to PWR_SR1_WUF.\r
-  * @{\r
-  */\r
-#define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */\r
-#define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */\r
-#define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */\r
-#define PWR_FLAG_WUF4                       ((uint32_t)0x0023)   /*!< Wakeup event on wakeup pin 4 */\r
-#define PWR_FLAG_WUF5                       ((uint32_t)0x0024)   /*!< Wakeup event on wakeup pin 5 */\r
-#define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */\r
-#define PWR_FLAG_SB                         ((uint32_t)0x0028)   /*!< Standby flag */\r
-#if defined(PWR_SR1_EXT_SMPS_RDY)\r
-#define PWR_FLAG_EXT_SMPS                   ((uint32_t)0x002D)   /*!< Switching to external SMPS ready flag */\r
-#endif /* PWR_SR1_EXT_SMPS_RDY */\r
-#define PWR_FLAG_WUFI                       ((uint32_t)0x002F)   /*!< Wakeup on internal wakeup line */\r
-\r
-#define PWR_FLAG_REGLPS                     ((uint32_t)0x0048)   /*!< Low-power regulator start flag */\r
-#define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */\r
-#define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */\r
-#define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */\r
-#if defined(PWR_CR2_PVME1)\r
-#define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */\r
-#endif /* PWR_CR2_PVME1 */\r
-#if defined(PWR_CR2_PVME2)\r
-#define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */\r
-#endif /* PWR_CR2_PVME2 */\r
-#define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */\r
-#define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros\r
- * @{\r
- */\r
-\r
-#if defined(PWR_CR2_PVME1)\r
-/**\r
-  * @brief Enable the PVM1 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Disable the PVM1 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Enable the PVM1 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Disable the PVM1 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Enable the PVM1 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Disable the PVM1 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Enable the PVM1 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)\r
-\r
-\r
-/**\r
-  * @brief Disable the PVM1 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)\r
-\r
-\r
-/**\r
-  * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                    \\r
-    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                     \\r
-    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Generate a Software interrupt on selected EXTI line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.\r
-  * @retval EXTI PVM1 Line Status.\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)\r
-\r
-/**\r
-  * @brief Clear the PVM1 EXTI flag.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)\r
-\r
-#endif /* PWR_CR2_PVME1 */\r
-\r
-\r
-#if defined(PWR_CR2_PVME2)\r
-/**\r
-  * @brief Enable the PVM2 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Disable the PVM2 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Enable the PVM2 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Disable the PVM2 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Enable the PVM2 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Disable the PVM2 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Enable the PVM2 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)\r
-\r
-\r
-/**\r
-  * @brief Disable the PVM2 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)\r
-\r
-\r
-/**\r
-  * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                    \\r
-    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                     \\r
-    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Generate a Software interrupt on selected EXTI line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.\r
-  * @retval EXTI PVM2 Line Status.\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)\r
-\r
-/**\r
-  * @brief Clear the PVM2 EXTI flag.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)\r
-\r
-#endif /* PWR_CR2_PVME2 */\r
-\r
-\r
-/**\r
-  * @brief Enable the PVM3 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Disable the PVM3 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Enable the PVM3 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Disable the PVM3 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Enable the PVM3 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Disable the PVM3 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Enable the PVM3 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)\r
-\r
-\r
-/**\r
-  * @brief Disable the PVM3 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)\r
-\r
-\r
-/**\r
-  * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                    \\r
-    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                     \\r
-    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Generate a Software interrupt on selected EXTI line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.\r
-  * @retval EXTI PVM3 Line Status.\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)\r
-\r
-/**\r
-  * @brief Clear the PVM3 EXTI flag.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)\r
-\r
-\r
-\r
-\r
-/**\r
-  * @brief Enable the PVM4 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Disable the PVM4 Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Enable the PVM4 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Disable the PVM4 Event Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Enable the PVM4 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Disable the PVM4 Extended Interrupt Rising Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Enable the PVM4 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)\r
-\r
-\r
-/**\r
-  * @brief Disable the PVM4 Extended Interrupt Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)\r
-\r
-\r
-/**\r
-  * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                    \\r
-    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                     \\r
-    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \\r
-    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Generate a Software interrupt on selected EXTI line.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.\r
-  * @retval EXTI PVM4 Line Status.\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)\r
-\r
-/**\r
-  * @brief Clear the PVM4 EXTI flag.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)\r
-\r
-\r
-/**\r
-  * @brief Configure the main internal regulator output voltage.\r
-  * @param  __REGULATOR__: specifies the regulator output voltage to achieve\r
-  *         a tradeoff between performance and power consumption.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,\r
-  *                                                typical output voltage at 1.2 V,\r
-  *                                                system frequency up to 80 MHz.\r
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,\r
-  *                                                typical output voltage at 1.0 V,\r
-  *                                                system frequency up to 26 MHz.\r
-  * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check\r
-  *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User\r
-  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.\r
-  * @retval None\r
-  */\r
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \\r
-                                                            __IO uint32_t tmpreg;                               \\r
-                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \\r
-                                                            /* Delay after an RCC peripheral clock enabling */  \\r
-                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \\r
-                                                            UNUSED(tmpreg);                                     \\r
-                                                          } while(0)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros --------------------------------------------------------*/\r
-/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros\r
-  * @{\r
-  */\r
-\r
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN2) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN3) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN4) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN5) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \\r
-                                ((PIN) == PWR_WAKEUP_PIN5_LOW))\r
-\r
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx)                                                   || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\\r
-                               ((TYPE) == PWR_PVM_2) ||\\r
-                               ((TYPE) == PWR_PVM_3) ||\\r
-                               ((TYPE) == PWR_PVM_4))\r
-#elif defined (STM32L471xx)\r
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\\r
-                               ((TYPE) == PWR_PVM_3) ||\\r
-                               ((TYPE) == PWR_PVM_4))\r
-#endif\r
-\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\\r
-                               ((TYPE) == PWR_PVM_3) ||\\r
-                               ((TYPE) == PWR_PVM_4))\r
-#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)\r
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\\r
-                               ((TYPE) == PWR_PVM_4))\r
-#endif\r
-\r
-#define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\\r
-                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\\r
-                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\\r
-                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\\r
-                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\\r
-                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\\r
-                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))\r
-\r
-#if defined(PWR_CR5_R1MODE)\r
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \\r
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1)       || \\r
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))\r
-#else\r
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\r
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))\r
-#endif\r
-\r
-\r
-#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\\r
-                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))\r
-\r
-#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\\r
-                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))\r
-\r
-#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)\r
-\r
-\r
-#if defined (STM32L412xx) || defined (STM32L422xx)\r
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
-                           ((GPIO) == PWR_GPIO_B) ||\\r
-                           ((GPIO) == PWR_GPIO_C) ||\\r
-                           ((GPIO) == PWR_GPIO_D) ||\\r
-                           ((GPIO) == PWR_GPIO_H))\r
-#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \\r
-      defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
-                           ((GPIO) == PWR_GPIO_B) ||\\r
-                           ((GPIO) == PWR_GPIO_C) ||\\r
-                           ((GPIO) == PWR_GPIO_D) ||\\r
-                           ((GPIO) == PWR_GPIO_E) ||\\r
-                           ((GPIO) == PWR_GPIO_H))\r
-#elif defined (STM32L432xx) || defined (STM32L442xx)\r
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
-                           ((GPIO) == PWR_GPIO_B) ||\\r
-                           ((GPIO) == PWR_GPIO_C) ||\\r
-                           ((GPIO) == PWR_GPIO_H))\r
-#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)\r
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
-                           ((GPIO) == PWR_GPIO_B) ||\\r
-                           ((GPIO) == PWR_GPIO_C) ||\\r
-                           ((GPIO) == PWR_GPIO_D) ||\\r
-                           ((GPIO) == PWR_GPIO_E) ||\\r
-                           ((GPIO) == PWR_GPIO_F) ||\\r
-                           ((GPIO) == PWR_GPIO_G) ||\\r
-                           ((GPIO) == PWR_GPIO_H))\r
-#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-      defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\\r
-                           ((GPIO) == PWR_GPIO_B) ||\\r
-                           ((GPIO) == PWR_GPIO_C) ||\\r
-                           ((GPIO) == PWR_GPIO_D) ||\\r
-                           ((GPIO) == PWR_GPIO_E) ||\\r
-                           ((GPIO) == PWR_GPIO_F) ||\\r
-                           ((GPIO) == PWR_GPIO_G) ||\\r
-                           ((GPIO) == PWR_GPIO_H) ||\\r
-                           ((GPIO) == PWR_GPIO_I))\r
-#endif\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions\r
-  * @{\r
-  */\r
-\r
-\r
-/* Peripheral Control functions  **********************************************/\r
-uint32_t HAL_PWREx_GetVoltageRange(void);\r
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);\r
-void HAL_PWREx_DisableBatteryCharging(void);\r
-#if defined(PWR_CR2_USV)\r
-void HAL_PWREx_EnableVddUSB(void);\r
-void HAL_PWREx_DisableVddUSB(void);\r
-#endif /* PWR_CR2_USV */\r
-#if defined(PWR_CR2_IOSV)\r
-void HAL_PWREx_EnableVddIO2(void);\r
-void HAL_PWREx_DisableVddIO2(void);\r
-#endif /* PWR_CR2_IOSV */\r
-void HAL_PWREx_EnableInternalWakeUpLine(void);\r
-void HAL_PWREx_DisableInternalWakeUpLine(void);\r
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);\r
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);\r
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);\r
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);\r
-void HAL_PWREx_EnablePullUpPullDownConfig(void);\r
-void HAL_PWREx_DisablePullUpPullDownConfig(void);\r
-void HAL_PWREx_EnableSRAM2ContentRetention(void);\r
-void HAL_PWREx_DisableSRAM2ContentRetention(void);\r
-#if defined(PWR_CR1_RRSTP)\r
-void HAL_PWREx_EnableSRAM3ContentRetention(void);\r
-void HAL_PWREx_DisableSRAM3ContentRetention(void);\r
-#endif /* PWR_CR1_RRSTP */\r
-#if defined(PWR_CR3_DSIPDEN)\r
-void HAL_PWREx_EnableDSIPinsPDActivation(void);\r
-void HAL_PWREx_DisableDSIPinsPDActivation(void);\r
-#endif /* PWR_CR3_DSIPDEN */\r
-#if defined(PWR_CR2_PVME1)\r
-void HAL_PWREx_EnablePVM1(void);\r
-void HAL_PWREx_DisablePVM1(void);\r
-#endif /* PWR_CR2_PVME1 */\r
-#if defined(PWR_CR2_PVME2)\r
-void HAL_PWREx_EnablePVM2(void);\r
-void HAL_PWREx_DisablePVM2(void);\r
-#endif /* PWR_CR2_PVME2 */\r
-void HAL_PWREx_EnablePVM3(void);\r
-void HAL_PWREx_DisablePVM3(void);\r
-void HAL_PWREx_EnablePVM4(void);\r
-void HAL_PWREx_DisablePVM4(void);\r
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);\r
-#if defined(PWR_CR3_ENULP)\r
-void HAL_PWREx_EnableBORPVD_ULP(void);\r
-void HAL_PWREx_DisableBORPVD_ULP(void);\r
-#endif /* PWR_CR3_ENULP */\r
-#if defined(PWR_CR4_EXT_SMPS_ON)\r
-void HAL_PWREx_EnableExtSMPS_0V95(void);\r
-void HAL_PWREx_DisableExtSMPS_0V95(void);\r
-#endif /* PWR_CR4_EXT_SMPS_ON */\r
-\r
-\r
-/* Low Power modes configuration functions ************************************/\r
-void HAL_PWREx_EnableLowPowerRunMode(void);\r
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);\r
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);\r
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);\r
-void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);\r
-void HAL_PWREx_EnterSHUTDOWNMode(void);\r
-\r
-void HAL_PWREx_PVD_PVM_IRQHandler(void);\r
-#if defined(PWR_CR2_PVME1)\r
-void HAL_PWREx_PVM1Callback(void);\r
-#endif /* PWR_CR2_PVME1 */\r
-#if defined(PWR_CR2_PVME2)\r
-void HAL_PWREx_PVM2Callback(void);\r
-#endif /* PWR_CR2_PVME2 */\r
-void HAL_PWREx_PVM3Callback(void);\r
-void HAL_PWREx_PVM4Callback(void);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* __STM32L4xx_HAL_PWR_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h
deleted file mode 100644 (file)
index f0729a5..0000000
+++ /dev/null
@@ -1,769 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_qspi.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of QSPI HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_QSPI_H\r
-#define STM32L4xx_HAL_QSPI_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-#if defined(QUADSPI)\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup QSPI\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup QSPI_Exported_Types QSPI Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  QSPI Init structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.\r
-                                  This parameter can be a number between 0 and 255 */\r
-  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)\r
-                                  This parameter can be a value between 1 and 16 */\r
-  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to\r
-                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)\r
-                                  This parameter can be a value of @ref QSPI_SampleShifting */\r
-  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits\r
-                                  required to address the flash memory. The flash capacity can be up to 4GB\r
-                                  (addressed using 32 bits) in indirect mode, but the addressable space in\r
-                                  memory-mapped mode is limited to 256MB\r
-                                  This parameter can be a number between 0 and 31 */\r
-  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number\r
-                                  of clock cycles which the chip select must remain high between commands.\r
-                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */\r
-  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.\r
-                                  This parameter can be a value of @ref QSPI_ClockMode */\r
-#if defined(QUADSPI_CR_DFM)\r
-  uint32_t FlashID;            /* Specifies the Flash which will be used,\r
-                                  This parameter can be a value of @ref QSPI_Flash_Select */\r
-  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State\r
-                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */\r
-#endif\r
-}QSPI_InitTypeDef;\r
-\r
-/**\r
-  * @brief HAL QSPI State structures definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */\r
-  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */\r
-  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */\r
-  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */\r
-  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */\r
-  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */\r
-  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */\r
-  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */\r
-  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */\r
-}HAL_QSPI_StateTypeDef;\r
-\r
-/**\r
-  * @brief  QSPI Handle Structure definition\r
-  */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-typedef struct __QSPI_HandleTypeDef\r
-#else\r
-typedef struct\r
-#endif\r
-{\r
-  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */\r
-  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */\r
-  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */\r
-  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */\r
-  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */\r
-  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */\r
-  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */\r
-  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */\r
-  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */\r
-  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */\r
-  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */\r
-  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */\r
-  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-  void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* RxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* TxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);\r
-\r
-  void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);\r
-  void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);\r
-#endif\r
-}QSPI_HandleTypeDef;\r
-\r
-/**\r
-  * @brief  QSPI Command structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Instruction;        /* Specifies the Instruction to be sent\r
-                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */\r
-  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)\r
-                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
-  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)\r
-                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
-  uint32_t AddressSize;        /* Specifies the Address Size\r
-                                  This parameter can be a value of @ref QSPI_AddressSize */\r
-  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size\r
-                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */\r
-  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.\r
-                                  This parameter can be a number between 0 and 31 */\r
-  uint32_t InstructionMode;    /* Specifies the Instruction Mode\r
-                                  This parameter can be a value of @ref QSPI_InstructionMode */\r
-  uint32_t AddressMode;        /* Specifies the Address Mode\r
-                                  This parameter can be a value of @ref QSPI_AddressMode */\r
-  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode\r
-                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */\r
-  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)\r
-                                  This parameter can be a value of @ref QSPI_DataMode */\r
-  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)\r
-                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length\r
-                                  until end of memory)*/\r
-  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase\r
-                                  This parameter can be a value of @ref QSPI_DdrMode */\r
-  uint32_t DdrHoldHalfCycle;   /* Specifies if the DDR hold is enabled. When enabled it delays the data\r
-                                  output by one half of system clock in DDR mode.\r
-                                  Not available on all devices.\r
-                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */\r
-  uint32_t SIOOMode;           /* Specifies the send instruction only once mode\r
-                                  This parameter can be a value of @ref QSPI_SIOOMode */\r
-}QSPI_CommandTypeDef;\r
-\r
-/**\r
-  * @brief  QSPI Auto Polling mode configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.\r
-                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r
-  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.\r
-                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r
-  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.\r
-                                  This parameter can be any value between 0 and 0xFFFF */\r
-  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.\r
-                                  This parameter can be any value between 1 and 4 */\r
-  uint32_t MatchMode;          /* Specifies the method used for determining a match.\r
-                                  This parameter can be a value of @ref QSPI_MatchMode */\r
-  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.\r
-                                  This parameter can be a value of @ref QSPI_AutomaticStop */\r
-}QSPI_AutoPollingTypeDef;\r
-\r
-/**\r
-  * @brief  QSPI Memory Mapped mode configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.\r
-                                  This parameter can be any value between 0 and 0xFFFF */\r
-  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.\r
-                                  This parameter can be a value of @ref QSPI_TimeOutActivation */\r
-}QSPI_MemoryMappedTypeDef;\r
-\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  HAL QSPI Callback ID enumeration definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */\r
-  HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */\r
-  HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */\r
-  HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */\r
-  HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */\r
-  HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */\r
-  HAL_QSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< QSPI Rx Half Complete Callback ID */\r
-  HAL_QSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< QSPI Tx Half Complete Callback ID */\r
-  HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */\r
-  HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */\r
-\r
-  HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */\r
-  HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */\r
-}HAL_QSPI_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  HAL QSPI Callback pointer definition\r
-  */\r
-typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup QSPI_Exported_Constants QSPI Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup QSPI_ErrorCode QSPI Error Code\r
-  * @{\r
-  */\r
-#define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */\r
-#define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */\r
-#define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */\r
-#define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */\r
-#define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_SampleShifting QSPI Sample Shifting\r
-  * @{\r
-  */\r
-#define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/\r
-#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time\r
-  * @{\r
-  */\r
-#define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/\r
-#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/\r
-#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/\r
-#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/\r
-#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/\r
-#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/\r
-#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/\r
-#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_ClockMode QSPI Clock Mode\r
-  * @{\r
-  */\r
-#define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/\r
-#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(QUADSPI_CR_DFM)\r
-/** @defgroup QSPI_Flash_Select QSPI Flash Select\r
-  * @{\r
-  */\r
-#define QSPI_FLASH_ID_1                0x00000000U                 /*!<FLASH 1 selected*/\r
-#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode\r
-  * @{\r
-  */\r
-#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/\r
-#define QSPI_DUALFLASH_DISABLE         0x00000000U                /*!<Dual-flash mode disabled*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif\r
-/** @defgroup QSPI_AddressSize QSPI Address Size\r
-  * @{\r
-  */\r
-#define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/\r
-#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/\r
-#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/\r
-#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size\r
-  * @{\r
-  */\r
-#define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/\r
-#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/\r
-#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/\r
-#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_InstructionMode QSPI Instruction Mode\r
-* @{\r
-*/\r
-#define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/\r
-#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/\r
-#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/\r
-#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_AddressMode QSPI Address Mode\r
-* @{\r
-*/\r
-#define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/\r
-#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/\r
-#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/\r
-#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode\r
-* @{\r
-*/\r
-#define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/\r
-#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/\r
-#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/\r
-#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_DataMode QSPI Data Mode\r
-  * @{\r
-  */\r
-#define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/\r
-#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/\r
-#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/\r
-#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_DdrMode QSPI DDR Mode\r
-  * @{\r
-  */\r
-#define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/\r
-#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay\r
-  * @{\r
-  */\r
-#define QSPI_DDR_HHC_ANALOG_DELAY      0x00000000U                  /*!<Delay the data output using analog delay in DDR mode*/\r
-#if defined(QUADSPI_CCR_DHHC)\r
-#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode\r
-  * @{\r
-  */\r
-#define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/\r
-#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_MatchMode QSPI Match Mode\r
-  * @{\r
-  */\r
-#define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/\r
-#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop\r
-  * @{\r
-  */\r
-#define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/\r
-#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation\r
-  * @{\r
-  */\r
-#define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/\r
-#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_Flags QSPI Flags\r
-  * @{\r
-  */\r
-#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/\r
-#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/\r
-#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/\r
-#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/\r
-#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/\r
-#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_Interrupts QSPI Interrupts\r
-  * @{\r
-  */\r
-#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/\r
-#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/\r
-#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/\r
-#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/\r
-#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_Timeout_definition QSPI Timeout definition\r
-  * @brief QSPI Timeout definition\r
-  * @{\r
-  */\r
-#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup QSPI_Exported_Macros QSPI Exported Macros\r
-  * @{\r
-  */\r
-/** @brief Reset QSPI handle state.\r
-  * @param  __HANDLE__ : QSPI handle.\r
-  * @retval None\r
-  */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \\r
-                                                                  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \\r
-                                                                  (__HANDLE__)->MspInitCallback = NULL;       \\r
-                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \\r
-                                                               } while(0)\r
-#else\r
-#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)\r
-#endif\r
-\r
-/** @brief  Enable the QSPI peripheral.\r
-  * @param  __HANDLE__ : specifies the QSPI Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
-\r
-/** @brief  Disable the QSPI peripheral.\r
-  * @param  __HANDLE__ : specifies the QSPI Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
-\r
-/** @brief  Enable the specified QSPI interrupt.\r
-  * @param  __HANDLE__ : specifies the QSPI Handle.\r
-  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to enable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
-  * @retval None\r
-  */\r
-#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
-\r
-\r
-/** @brief  Disable the specified QSPI interrupt.\r
-  * @param  __HANDLE__ : specifies the QSPI Handle.\r
-  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to disable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
-  * @retval None\r
-  */\r
-#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
-\r
-/** @brief  Check whether the specified QSPI interrupt source is enabled or not.\r
-  * @param  __HANDLE__ : specifies the QSPI Handle.\r
-  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))\r
-\r
-/**\r
-  * @brief  Check whether the selected QSPI flag is set or not.\r
-  * @param  __HANDLE__ : specifies the QSPI Handle.\r
-  * @param  __FLAG__ : specifies the QSPI flag to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag\r
-  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag\r
-  *            @arg QSPI_FLAG_SM:   QSPI Status match flag\r
-  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag\r
-  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag\r
-  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag\r
-  * @retval None\r
-  */\r
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)\r
-\r
-/** @brief  Clears the specified QSPI's flag status.\r
-  * @param  __HANDLE__ : specifies the QSPI Handle.\r
-  * @param  __FLAG__ : specifies the QSPI clear register flag that needs to be set\r
-  *          This parameter can be one of the following values:\r
-  *            @arg QSPI_FLAG_TO: QSPI Timeout flag\r
-  *            @arg QSPI_FLAG_SM: QSPI Status match flag\r
-  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r
-  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag\r
-  * @retval None\r
-  */\r
-#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup QSPI_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup QSPI_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-/* Initialization/de-initialization functions  ********************************/\r
-HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);\r
-HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup QSPI_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-/* IO operation functions *****************************************************/\r
-/* QSPI IRQ handler method */\r
-void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);\r
-\r
-/* QSPI indirect mode */\r
-HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);\r
-HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
-HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
-HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);\r
-HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
-HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
-HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
-HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
-\r
-/* QSPI status flag polling mode */\r
-HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);\r
-HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);\r
-\r
-/* QSPI memory-mapped mode */\r
-HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);\r
-\r
-/* Callback functions in non-blocking modes ***********************************/\r
-void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);\r
-\r
-/* QSPI indirect mode */\r
-void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r
-\r
-/* QSPI status flag polling mode */\r
-void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);\r
-\r
-/* QSPI memory-mapped mode */\r
-void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);\r
-\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-/* QSPI callback registering/unregistering */\r
-HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);\r
-HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup QSPI_Exported_Functions_Group3\r
-  * @{\r
-  */\r
-/* Peripheral Control and State functions  ************************************/\r
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);\r
-uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);\r
-HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);\r
-HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);\r
-void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);\r
-HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);\r
-uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);\r
-#if defined(QUADSPI_CR_DFM)\r
-HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported functions -------------------------------------------------*/\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup QSPI_Private_Macros QSPI Private Macros\r
-  * @{\r
-  */\r
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)\r
-\r
-#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 16U))\r
-\r
-#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \\r
-                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))\r
-\r
-#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))\r
-\r
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \\r
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \\r
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \\r
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \\r
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \\r
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \\r
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \\r
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))\r
-\r
-#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \\r
-                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))\r
-\r
-#if defined(QUADSPI_CR_DFM)\r
-#define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \\r
-                                            ((FLASH_ID) == QSPI_FLASH_ID_2))\r
-\r
-#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \\r
-                                            ((MODE) == QSPI_DUALFLASH_DISABLE))\r
-\r
-#endif\r
-#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)\r
-\r
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \\r
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \\r
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \\r
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))\r
-\r
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \\r
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \\r
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \\r
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))\r
-\r
-#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)\r
-\r
-#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \\r
-                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \\r
-                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \\r
-                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))\r
-\r
-#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \\r
-                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \\r
-                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \\r
-                                            ((MODE) == QSPI_ADDRESS_4_LINES))\r
-\r
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \\r
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \\r
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \\r
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))\r
-\r
-#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \\r
-                                            ((MODE) == QSPI_DATA_1_LINE)  || \\r
-                                            ((MODE) == QSPI_DATA_2_LINES) || \\r
-                                            ((MODE) == QSPI_DATA_4_LINES))\r
-\r
-#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \\r
-                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))\r
-\r
-#if defined(QUADSPI_CCR_DHHC)\r
-#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \\r
-                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))\r
-\r
-#else\r
-#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))\r
-\r
-#endif\r
-#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \\r
-                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))\r
-\r
-#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)\r
-\r
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))\r
-\r
-#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \\r
-                                            ((MODE) == QSPI_MATCH_MODE_OR))\r
-\r
-#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \\r
-                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))\r
-\r
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \\r
-                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))\r
-\r
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)\r
-/**\r
-* @}\r
-*/\r
-/* End of private macros -----------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_QSPI_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
deleted file mode 100644 (file)
index 5111e73..0000000
+++ /dev/null
@@ -1,4743 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_rcc.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of RCC HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_RCC_H\r
-#define __STM32L4xx_HAL_RCC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup RCC\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup RCC_Exported_Types RCC Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  RCC PLL configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t PLLState;   /*!< The new state of the PLL.\r
-                            This parameter can be a value of @ref RCC_PLL_Config                      */\r
-\r
-  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.\r
-                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */\r
-\r
-  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.\r
-                            This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
-                            This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */\r
-\r
-  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.\r
-                            This parameter must be a number between Min_Data = 8 and Max_Data = 86    */\r
-\r
-#if defined(RCC_PLLP_SUPPORT)\r
-  uint32_t PLLP;       /*!< PLLP: Division factor for SAI clock.\r
-                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */\r
-#endif /* RCC_PLLP_SUPPORT */\r
-\r
-  uint32_t PLLQ;       /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.\r
-                            This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */\r
-\r
-  uint32_t PLLR;       /*!< PLLR: Division for the main system clock.\r
-                            User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ\r
-                            on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices.\r
-                            This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */\r
-\r
-}RCC_PLLInitTypeDef;\r
-\r
-/**\r
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.\r
-                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */\r
-\r
-  uint32_t HSEState;             /*!< The new state of the HSE.\r
-                                      This parameter can be a value of @ref RCC_HSE_Config                        */\r
-\r
-  uint32_t LSEState;             /*!< The new state of the LSE.\r
-                                      This parameter can be a value of @ref RCC_LSE_Config                        */\r
-\r
-  uint32_t HSIState;             /*!< The new state of the HSI.\r
-                                      This parameter can be a value of @ref RCC_HSI_Config                        */\r
-\r
-  uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.\r
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */\r
-\r
-  uint32_t LSIState;             /*!< The new state of the LSI.\r
-                                      This parameter can be a value of @ref RCC_LSI_Config                        */\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-\r
-  uint32_t LSIDiv;               /*!< The division factor of the LSI.\r
-                                      This parameter can be a value of @ref RCC_LSI_Div                           */\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-  uint32_t MSIState;             /*!< The new state of the MSI.\r
-                                      This parameter can be a value of @ref RCC_MSI_Config */\r
-\r
-  uint32_t MSICalibrationValue;  /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).\r
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
-\r
-  uint32_t MSIClockRange;        /*!< The MSI frequency range.\r
-                                      This parameter can be a value of @ref RCC_MSI_Clock_Range  */\r
-\r
-  uint32_t HSI48State;             /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).\r
-                                        This parameter can be a value of @ref RCC_HSI48_Config */\r
-\r
-  RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */\r
-\r
-}RCC_OscInitTypeDef;\r
-\r
-/**\r
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t ClockType;             /*!< The clock to be configured.\r
-                                       This parameter can be a value of @ref RCC_System_Clock_Type      */\r
-\r
-  uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).\r
-                                       This parameter can be a value of @ref RCC_System_Clock_Source    */\r
-\r
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */\r
-\r
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
-\r
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
-\r
-}RCC_ClkInitTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup RCC_Timeout_Value Timeout Values\r
-  * @{\r
-  */\r
-#define RCC_DBP_TIMEOUT_VALUE          2U            /* 2 ms (minimum Tick + 1) */\r
-#define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_Oscillator_Type Oscillator Type\r
-  * @{\r
-  */\r
-#define RCC_OSCILLATORTYPE_NONE        0x00000000U   /*!< Oscillator configuration unchanged */\r
-#define RCC_OSCILLATORTYPE_HSE         0x00000001U   /*!< HSE to configure */\r
-#define RCC_OSCILLATORTYPE_HSI         0x00000002U   /*!< HSI to configure */\r
-#define RCC_OSCILLATORTYPE_LSE         0x00000004U   /*!< LSE to configure */\r
-#define RCC_OSCILLATORTYPE_LSI         0x00000008U   /*!< LSI to configure */\r
-#define RCC_OSCILLATORTYPE_MSI         0x00000010U   /*!< MSI to configure */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_OSCILLATORTYPE_HSI48       0x00000020U   /*!< HSI48 to configure */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_HSE_Config HSE Config\r
-  * @{\r
-  */\r
-#define RCC_HSE_OFF                    0x00000000U                    /*!< HSE clock deactivation */\r
-#define RCC_HSE_ON                     RCC_CR_HSEON                   /*!< HSE clock activation */\r
-#define RCC_HSE_BYPASS                 (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_LSE_Config LSE Config\r
-  * @{\r
-  */\r
-#define RCC_LSE_OFF                    0x00000000U                           /*!< LSE clock deactivation */\r
-#define RCC_LSE_ON                     RCC_BDCR_LSEON                        /*!< LSE clock activation */\r
-#define RCC_LSE_BYPASS                 (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)    /*!< External clock source for LSE clock */\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-#define RCC_LSE_ON_RTC_ONLY            (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */\r
-#define RCC_LSE_BYPASS_RTC_ONLY        (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_HSI_Config HSI Config\r
-  * @{\r
-  */\r
-#define RCC_HSI_OFF                    0x00000000U   /*!< HSI clock deactivation */\r
-#define RCC_HSI_ON                     RCC_CR_HSION  /*!< HSI clock activation */\r
-\r
-#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \\r
-    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-#define RCC_HSICALIBRATION_DEFAULT     0x10U         /* Default HSI calibration trimming value */\r
-#else\r
-#define RCC_HSICALIBRATION_DEFAULT     0x40U         /* Default HSI calibration trimming value */\r
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */\r
-       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx    */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_LSI_Config LSI Config\r
-  * @{\r
-  */\r
-#define RCC_LSI_OFF                    0x00000000U   /*!< LSI clock deactivation */\r
-#define RCC_LSI_ON                     RCC_CSR_LSION /*!< LSI clock activation */\r
-/**\r
-  * @}\r
-  */\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-\r
-/** @defgroup RCC_LSI_Div LSI Div\r
-  * @{\r
-  */\r
-#define RCC_LSI_DIV1                   0x00000000U       /*!< LSI clock not divided    */\r
-#define RCC_LSI_DIV128                 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-/** @defgroup RCC_MSI_Config MSI Config\r
-  * @{\r
-  */\r
-#define RCC_MSI_OFF                    0x00000000U   /*!< MSI clock deactivation */\r
-#define RCC_MSI_ON                     RCC_CR_MSION  /*!< MSI clock activation */\r
-\r
-#define RCC_MSICALIBRATION_DEFAULT     0U            /*!< Default MSI calibration trimming value */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-/** @defgroup RCC_HSI48_Config HSI48 Config\r
-  * @{\r
-  */\r
-#define RCC_HSI48_OFF                  0x00000000U       /*!< HSI48 clock deactivation */\r
-#define RCC_HSI48_ON                   RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */\r
-/**\r
-  * @}\r
-  */\r
-#else\r
-/** @defgroup RCC_HSI48_Config HSI48 Config\r
-  * @{\r
-  */\r
-#define RCC_HSI48_OFF                  0x00000000U   /*!< HSI48 clock deactivation */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-/** @defgroup RCC_PLL_Config PLL Config\r
-  * @{\r
-  */\r
-#define RCC_PLL_NONE                   0x00000000U   /*!< PLL configuration unchanged */\r
-#define RCC_PLL_OFF                    0x00000001U   /*!< PLL deactivation */\r
-#define RCC_PLL_ON                     0x00000002U   /*!< PLL activation */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(RCC_PLLP_SUPPORT)\r
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r
-  * @{\r
-  */\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-#define RCC_PLLP_DIV2                  0x00000002U   /*!< PLLP division factor = 2  */\r
-#define RCC_PLLP_DIV3                  0x00000003U   /*!< PLLP division factor = 3  */\r
-#define RCC_PLLP_DIV4                  0x00000004U   /*!< PLLP division factor = 4  */\r
-#define RCC_PLLP_DIV5                  0x00000005U   /*!< PLLP division factor = 5  */\r
-#define RCC_PLLP_DIV6                  0x00000006U   /*!< PLLP division factor = 6  */\r
-#define RCC_PLLP_DIV7                  0x00000007U   /*!< PLLP division factor = 7  */\r
-#define RCC_PLLP_DIV8                  0x00000008U   /*!< PLLP division factor = 8  */\r
-#define RCC_PLLP_DIV9                  0x00000009U   /*!< PLLP division factor = 9  */\r
-#define RCC_PLLP_DIV10                 0x0000000AU   /*!< PLLP division factor = 10 */\r
-#define RCC_PLLP_DIV11                 0x0000000BU   /*!< PLLP division factor = 11 */\r
-#define RCC_PLLP_DIV12                 0x0000000CU   /*!< PLLP division factor = 12 */\r
-#define RCC_PLLP_DIV13                 0x0000000DU   /*!< PLLP division factor = 13 */\r
-#define RCC_PLLP_DIV14                 0x0000000EU   /*!< PLLP division factor = 14 */\r
-#define RCC_PLLP_DIV15                 0x0000000FU   /*!< PLLP division factor = 15 */\r
-#define RCC_PLLP_DIV16                 0x00000010U   /*!< PLLP division factor = 16 */\r
-#define RCC_PLLP_DIV17                 0x00000011U   /*!< PLLP division factor = 17 */\r
-#define RCC_PLLP_DIV18                 0x00000012U   /*!< PLLP division factor = 18 */\r
-#define RCC_PLLP_DIV19                 0x00000013U   /*!< PLLP division factor = 19 */\r
-#define RCC_PLLP_DIV20                 0x00000014U   /*!< PLLP division factor = 20 */\r
-#define RCC_PLLP_DIV21                 0x00000015U   /*!< PLLP division factor = 21 */\r
-#define RCC_PLLP_DIV22                 0x00000016U   /*!< PLLP division factor = 22 */\r
-#define RCC_PLLP_DIV23                 0x00000017U   /*!< PLLP division factor = 23 */\r
-#define RCC_PLLP_DIV24                 0x00000018U   /*!< PLLP division factor = 24 */\r
-#define RCC_PLLP_DIV25                 0x00000019U   /*!< PLLP division factor = 25 */\r
-#define RCC_PLLP_DIV26                 0x0000001AU   /*!< PLLP division factor = 26 */\r
-#define RCC_PLLP_DIV27                 0x0000001BU   /*!< PLLP division factor = 27 */\r
-#define RCC_PLLP_DIV28                 0x0000001CU   /*!< PLLP division factor = 28 */\r
-#define RCC_PLLP_DIV29                 0x0000001DU   /*!< PLLP division factor = 29 */\r
-#define RCC_PLLP_DIV30                 0x0000001EU   /*!< PLLP division factor = 30 */\r
-#define RCC_PLLP_DIV31                 0x0000001FU   /*!< PLLP division factor = 31 */\r
-#else\r
-#define RCC_PLLP_DIV7                  0x00000007U   /*!< PLLP division factor = 7  */\r
-#define RCC_PLLP_DIV17                 0x00000011U   /*!< PLLP division factor = 17 */\r
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* RCC_PLLP_SUPPORT */\r
-\r
-/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider\r
-  * @{\r
-  */\r
-#define RCC_PLLQ_DIV2                  0x00000002U   /*!< PLLQ division factor = 2 */\r
-#define RCC_PLLQ_DIV4                  0x00000004U   /*!< PLLQ division factor = 4 */\r
-#define RCC_PLLQ_DIV6                  0x00000006U   /*!< PLLQ division factor = 6 */\r
-#define RCC_PLLQ_DIV8                  0x00000008U   /*!< PLLQ division factor = 8 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider\r
-  * @{\r
-  */\r
-#define RCC_PLLR_DIV2                  0x00000002U   /*!< PLLR division factor = 2 */\r
-#define RCC_PLLR_DIV4                  0x00000004U   /*!< PLLR division factor = 4 */\r
-#define RCC_PLLR_DIV6                  0x00000006U   /*!< PLLR division factor = 6 */\r
-#define RCC_PLLR_DIV8                  0x00000008U   /*!< PLLR division factor = 8 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
-  * @{\r
-  */\r
-#define RCC_PLLSOURCE_NONE             0x00000000U             /*!< No clock selected as PLL entry clock source  */\r
-#define RCC_PLLSOURCE_MSI              RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */\r
-#define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */\r
-#define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_PLL_Clock_Output PLL Clock Output\r
-  * @{\r
-  */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#define RCC_PLL_SAI3CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_PLL_SAI2CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-#define RCC_PLL_48M1CLK                RCC_PLLCFGR_PLLQEN      /*!< PLL48M1CLK selection from main PLL */\r
-#define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */\r
-/**\r
-  * @}\r
-  */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output\r
-  * @{\r
-  */\r
-#define RCC_PLLSAI1_SAI1CLK            RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */\r
-#define RCC_PLLSAI1_48M2CLK            RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */\r
-#define RCC_PLLSAI1_ADC1CLK            RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output\r
-  * @{\r
-  */\r
-#define RCC_PLLSAI2_SAI2CLK            RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-#define RCC_PLLSAI2_DSICLK             RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2  */\r
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-#define RCC_PLLSAI2_ADC2CLK            RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */\r
-#else\r
-#define RCC_PLLSAI2_LTDCCLK            RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-/** @defgroup RCC_MSI_Clock_Range MSI Clock Range\r
-  * @{\r
-  */\r
-#define RCC_MSIRANGE_0                 RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */\r
-#define RCC_MSIRANGE_1                 RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */\r
-#define RCC_MSIRANGE_2                 RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */\r
-#define RCC_MSIRANGE_3                 RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */\r
-#define RCC_MSIRANGE_4                 RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */\r
-#define RCC_MSIRANGE_5                 RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */\r
-#define RCC_MSIRANGE_6                 RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */\r
-#define RCC_MSIRANGE_7                 RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */\r
-#define RCC_MSIRANGE_8                 RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */\r
-#define RCC_MSIRANGE_9                 RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */\r
-#define RCC_MSIRANGE_10                RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */\r
-#define RCC_MSIRANGE_11                RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_System_Clock_Type System Clock Type\r
-  * @{\r
-  */\r
-#define RCC_CLOCKTYPE_SYSCLK           0x00000001U   /*!< SYSCLK to configure */\r
-#define RCC_CLOCKTYPE_HCLK             0x00000002U   /*!< HCLK to configure */\r
-#define RCC_CLOCKTYPE_PCLK1            0x00000004U   /*!< PCLK1 to configure */\r
-#define RCC_CLOCKTYPE_PCLK2            0x00000008U   /*!< PCLK2 to configure */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_System_Clock_Source System Clock Source\r
-  * @{\r
-  */\r
-#define RCC_SYSCLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */\r
-#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */\r
-#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */\r
-#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
-  * @{\r
-  */\r
-#define RCC_SYSCLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source\r
-  * @{\r
-  */\r
-#define RCC_SYSCLK_DIV1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */\r
-#define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */\r
-#define RCC_SYSCLK_DIV4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */\r
-#define RCC_SYSCLK_DIV8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */\r
-#define RCC_SYSCLK_DIV16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */\r
-#define RCC_SYSCLK_DIV64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */\r
-#define RCC_SYSCLK_DIV128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\r
-#define RCC_SYSCLK_DIV256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\r
-#define RCC_SYSCLK_DIV512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_HCLK_DIV1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */\r
-#define RCC_HCLK_DIV2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */\r
-#define RCC_HCLK_DIV4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */\r
-#define RCC_HCLK_DIV8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */\r
-#define RCC_HCLK_DIV16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source\r
-  * @{\r
-  */\r
-#define RCC_RTCCLKSOURCE_NONE          0x00000000U          /*!< No clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0    /*!< LSE oscillator clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1    /*!< LSI oscillator clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL      /*!< HSE oscillator clock divided by 32 used as RTC clock */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_MCO_Index MCO Index\r
-  * @{\r
-  */\r
-#define RCC_MCO1                       0x00000000U\r
-#define RCC_MCO                        RCC_MCO1      /*!< MCO1 to be compliant with other families with 2 MCOs*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_MCO1SOURCE_NOCLOCK         0x00000000U                            /*!< MCO1 output disabled, no clock on MCO1 */\r
-#define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_MSI             RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_MCO1SOURCE_HSI48           RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler\r
-  * @{\r
-  */\r
-#define RCC_MCODIV_1                   RCC_CFGR_MCOPRE_DIV1     /*!< MCO not divided  */\r
-#define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_DIV2     /*!< MCO divided by 2 */\r
-#define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_DIV4     /*!< MCO divided by 4 */\r
-#define RCC_MCODIV_8                   RCC_CFGR_MCOPRE_DIV8     /*!< MCO divided by 8 */\r
-#define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_DIV16    /*!< MCO divided by 16 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_Interrupt Interrupts\r
-  * @{\r
-  */\r
-#define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */\r
-#define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */\r
-#define RCC_IT_MSIRDY                  RCC_CIFR_MSIRDYF      /*!< MSI Ready Interrupt flag */\r
-#define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF      /*!< HSI16 Ready Interrupt flag */\r
-#define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */\r
-#define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_IT_PLLSAI1RDY              RCC_CIFR_PLLSAI1RDYF  /*!< PLLSAI1 Ready Interrupt flag */\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#define RCC_IT_PLLSAI2RDY              RCC_CIFR_PLLSAI2RDYF  /*!< PLLSAI2 Ready Interrupt flag */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-#define RCC_IT_CSS                     RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */\r
-#define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_IT_HSI48RDY                RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_Flag Flags\r
-  *        Elements values convention: XXXYYYYYb\r
-  *           - YYYYY  : Flag position in the register\r
-  *           - XXX  : Register index\r
-  *                 - 001: CR register\r
-  *                 - 010: BDCR register\r
-  *                 - 011: CSR register\r
-  *                 - 100: CRRCR register\r
-  * @{\r
-  */\r
-/* Flags in the CR register */\r
-#define RCC_FLAG_MSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */\r
-#define RCC_FLAG_HSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */\r
-#define RCC_FLAG_HSERDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */\r
-#define RCC_FLAG_PLLRDY                ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_FLAG_PLLSAI1RDY            ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#define RCC_FLAG_PLLSAI2RDY            ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-/* Flags in the BDCR register */\r
-#define RCC_FLAG_LSERDY                ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)  /*!< LSE Ready flag */\r
-#define RCC_FLAG_LSECSSD               ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */\r
-\r
-/* Flags in the CSR register */\r
-#define RCC_FLAG_LSIRDY                ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)    /*!< LSI Ready flag */\r
-#define RCC_FLAG_FWRST                 ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)    /*!< Firewall reset flag */\r
-#define RCC_FLAG_OBLRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)   /*!< Option Byte Loader reset flag */\r
-#define RCC_FLAG_PINRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)   /*!< PIN reset flag */\r
-#define RCC_FLAG_BORRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)   /*!< BOR reset flag */\r
-#define RCC_FLAG_SFTRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)   /*!< Software Reset flag */\r
-#define RCC_FLAG_IWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)  /*!< Independent Watchdog reset flag */\r
-#define RCC_FLAG_WWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)  /*!< Window watchdog reset flag */\r
-#define RCC_FLAG_LPWRRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)  /*!< Low-Power reset flag */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-/* Flags in the CRRCR register */\r
-#define RCC_FLAG_HSI48RDY              ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_LSEDrive_Config LSE Drive Config\r
-  * @{\r
-  */\r
-#define RCC_LSEDRIVE_LOW                 0x00000000U         /*!< LSE low drive capability */\r
-#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0   /*!< LSE medium low drive capability */\r
-#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1   /*!< LSE medium high drive capability */\r
-#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV     /*!< LSE high drive capability */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock\r
-  * @{\r
-  */\r
-#define RCC_STOP_WAKEUPCLOCK_MSI       0x00000000U           /*!< MSI selection after wake-up from STOP */\r
-#define RCC_STOP_WAKEUPCLOCK_HSI       RCC_CFGR_STOPWUCK     /*!< HSI selection after wake-up from STOP */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r
-  * @brief  Enable or disable the AHB1 peripheral clock.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_DMA1_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_DMA2_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_ENABLE()         do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_CRC_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_TSC_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)\r
-\r
-#define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_DISABLE()        CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)\r
-\r
-#define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)\r
-\r
-#define __HAL_RCC_TSC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_DISABLE()         CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\r
-  * @brief  Enable or disable the AHB2 peripheral clock.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()      do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */\r
-\r
-\r
-#define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()     CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_DISABLE()         CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN)\r
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable\r
-  * @brief  Enable or disable the AHB3 peripheral clock.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_DISABLE()          CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_DISABLE()          CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN)\r
-#endif /* OCTOSPI2 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r
-  * @brief  Enable or disable the APB1 peripheral clock.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_TIM2_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#define __HAL_RCC_WWDG_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-\r
-#define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\r
-  * @brief  Enable or disable the APB2 peripheral clock.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_FIREWALL_CLK_ENABLE()        do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_SPI1_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-\r
-#define __HAL_RCC_TIM15_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#define __HAL_RCC_TIM16_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_ENABLE()           do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_ENABLE()          do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_ENABLE()            do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_ENABLE()             do { \\r
-                                                 __IO uint32_t tmpreg; \\r
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \\r
-                                                 /* Delay after an RCC peripheral clock enabling */ \\r
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \\r
-                                                 UNUSED(tmpreg); \\r
-                                               } while(0)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)\r
-\r
-#define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)\r
-\r
-#define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)\r
-\r
-#define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_DISABLE()            CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN)\r
-#endif /* DSI */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status\r
-  * @brief  Check whether the AHB1 peripheral clock is enabled or not.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED()    (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status\r
-  * @brief  Check whether the AHB2 peripheral clock is enabled or not.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)\r
-\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status\r
-  * @brief  Check whether the AHB3 peripheral clock is enabled or not.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)\r
-#endif /* QUADSPI */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status\r
-  * @brief  Check whether the APB1 peripheral clock is enabled or not.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)\r
-\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status\r
-  * @brief  Check whether the APB2 peripheral clock is enabled or not.\r
-  * @note   After reset, the peripheral clock (used for registers read/write access)\r
-  *         is disabled and the application software has to enable this clock before\r
-  *         using it.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)\r
-\r
-#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_ENABLED()         (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_DISABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U)\r
-#endif /* DSI */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset\r
-  * @brief  Force or release AHB1 peripheral reset.\r
-  * @{\r
-  */\r
-#define __HAL_RCC_AHB1_FORCE_RESET()           WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)\r
-\r
-#define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_FORCE_RESET()        SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)\r
-\r
-#define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)\r
-\r
-#define __HAL_RCC_TSC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_FORCE_RESET()         SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_AHB1_RELEASE_RESET()         WRITE_REG(RCC->AHB1RSTR, 0x00000000U)\r
-\r
-#define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)\r
-\r
-#define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_RELEASE_RESET()      CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)\r
-\r
-#define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)\r
-\r
-#define __HAL_RCC_TSC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_RELEASE_RESET()       CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset\r
-  * @brief  Force or release AHB2 peripheral reset.\r
-  * @{\r
-  */\r
-#define __HAL_RCC_AHB2_FORCE_RESET()           WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)\r
-\r
-#define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)\r
-\r
-#define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()     SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_FORCE_RESET()         SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */\r
-\r
-\r
-#define __HAL_RCC_AHB2_RELEASE_RESET()         WRITE_REG(RCC->AHB2RSTR, 0x00000000U)\r
-\r
-#define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)\r
-\r
-#define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)\r
-\r
-#define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()   CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_RELEASE_RESET()       CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset\r
-  * @brief  Force or release AHB3 peripheral reset.\r
-  * @{\r
-  */\r
-#define __HAL_RCC_AHB3_FORCE_RESET()           WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_FORCE_RESET()            SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_FORCE_RESET()           SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_FORCE_RESET()          SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_FORCE_RESET()          SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)\r
-#endif /* OCTOSPI2 */\r
-\r
-#define __HAL_RCC_AHB3_RELEASE_RESET()         WRITE_REG(RCC->AHB3RSTR, 0x00000000U)\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_RELEASE_RESET()        CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_RELEASE_RESET()        CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)\r
-#endif /* OCTOSPI2 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset\r
-  * @brief  Force or release APB1 peripheral reset.\r
-  * @{\r
-  */\r
-#define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)\r
-#endif /* LCD */\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)\r
-\r
-#define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)\r
-\r
-#define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)\r
-\r
-\r
-#define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APB1RSTR1, 0x00000000U)\r
-\r
-#define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)\r
-#endif /* LCD */\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)\r
-\r
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)\r
-\r
-#define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset\r
-  * @brief  Force or release APB2 peripheral reset.\r
-  * @{\r
-  */\r
-#define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */\r
-\r
-#define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)\r
-\r
-#define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)\r
-\r
-#define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)\r
-\r
-#define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_FORCE_RESET()            SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APB2RSTR, 0x00000000U)\r
-\r
-#define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */\r
-\r
-#define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)\r
-\r
-#define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)\r
-\r
-#define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)\r
-\r
-#define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_RELEASE_RESET()          CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)\r
-#endif /* DSI */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable\r
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)\r
-\r
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)\r
-\r
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)\r
-\r
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)\r
-\r
-#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)\r
-\r
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)\r
-\r
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)\r
-\r
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)\r
-\r
-#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable\r
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-\r
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable\r
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)\r
-#endif /* FMC_BANK1 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable\r
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)\r
-\r
-\r
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable\r
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)\r
-\r
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)\r
-\r
-#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)\r
-\r
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)\r
-\r
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)\r
-\r
-#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)\r
-\r
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)\r
-#endif /* DSI */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status\r
-  * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)\r
-\r
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)\r
-\r
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status\r
-  * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status\r
-  * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status\r
-  * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U)\r
-\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status\r
-  * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r
-  *         power consumption.\r
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r
-  * @{\r
-  */\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U)\r
-#endif /* DSI */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset\r
-  * @{\r
-  */\r
-\r
-/** @brief  Macros to force or release the Backup domain reset.\r
-  * @note   This function resets the RTC peripheral (including the backup registers)\r
-  *         and the RTC clock source selection in RCC_CSR register.\r
-  * @note   The BKPSRAM is not affected by this reset.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
-\r
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration\r
-  * @{\r
-  */\r
-\r
-/** @brief  Macros to enable or disable the RTC clock.\r
-  * @note   As the RTC is in the Backup domain and write access is denied to\r
-  *         this domain after reset, you have to enable write access using\r
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC\r
-  *         (to be done once after reset).\r
-  * @note   These macros must be used after the RTC clock source was selected.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
-\r
-#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @brief  Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).\r
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
-  *         It is used (enabled by hardware) as system clock source after startup\r
-  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
-  *         of the HSE used directly or indirectly as system clock (if the Clock\r
-  *         Security System CSS is enabled).\r
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,\r
-  *         you have to select another source of the system clock then stop the HSI.\r
-  * @note   After enabling the HSI, the application software should wait on HSIRDY\r
-  *         flag to be set indicating that HSI clock is stable and can be used as\r
-  *         system clock source.\r
-  *         This parameter can be: ENABLE or DISABLE.\r
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
-  *         clock cycles.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)\r
-\r
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)\r
-\r
-/** @brief  Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.\r
-  * @note   The calibration is used to compensate for the variations in voltage\r
-  *         and temperature that influence the frequency of the internal HSI RC.\r
-  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value\r
-  *         (default is RCC_HSICALIBRATION_DEFAULT).\r
-  *         This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \\r
-                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)\r
-\r
-/**\r
-  * @brief    Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)\r
-  *           in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.\r
-  * @note     The enable of this function has not effect on the HSION bit.\r
-  *           This parameter can be: ENABLE or DISABLE.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIASFS)\r
-\r
-#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE()  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)\r
-\r
-/**\r
-  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)\r
-  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.\r
-  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication\r
-  *           speed because of the HSI startup time.\r
-  * @note     The enable of this function has not effect on the HSION bit.\r
-  *           This parameter can be: ENABLE or DISABLE.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)\r
-\r
-#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)\r
-\r
-/**\r
-  * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).\r
-  * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
-  *           It is used (enabled by hardware) as system clock source after\r
-  *           startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
-  *           of failure of the HSE used directly or indirectly as system clock\r
-  *           (if the Clock Security System CSS is enabled).\r
-  * @note     MSI can not be stopped if it is used as system clock source.\r
-  *           In this case, you have to select another source of the system\r
-  *           clock then stop the MSI.\r
-  * @note     After enabling the MSI, the application software should wait on\r
-  *           MSIRDY flag to be set indicating that MSI clock is stable and can\r
-  *           be used as system clock source.\r
-  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
-  *         clock cycles.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)\r
-\r
-#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)\r
-\r
-/** @brief  Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
-  * @note   The calibration is used to compensate for the variations in voltage\r
-  *         and temperature that influence the frequency of the internal MSI RC.\r
-  *         Refer to the Application Note AN3300 for more details on how to\r
-  *         calibrate the MSI.\r
-  * @param  __MSICALIBRATIONVALUE__ specifies the calibration trimming value\r
-  *         (default is RCC_MSICALIBRATION_DEFAULT).\r
-  *         This parameter must be a number between 0 and 255.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \\r
-                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)\r
-\r
-/**\r
-  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode\r
-  * @note     After restart from Reset , the MSI clock is around 4 MHz.\r
-  *           After stop the startup clock can be MSI (at any of its possible\r
-  *           frequencies, the one that was used before entering stop mode) or HSI.\r
-  *          After Standby its frequency can be selected between 4 possible values\r
-  *          (1, 2, 4 or 8 MHz).\r
-  * @note     MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready\r
-  *          (MSIRDY=1).\r
-  * @note    The MSI clock range after reset can be modified on the fly.\r
-  * @param  __MSIRANGEVALUE__ specifies the MSI clock range.\r
-  *         This parameter must be one of the following values:\r
-  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz\r
-  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz\r
-  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz\r
-  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz\r
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz\r
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz\r
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)\r
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz\r
-  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz\r
-  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz\r
-  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz\r
-  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \\r
-                  do {                                                         \\r
-                    SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \\r
-                    MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \\r
-                  } while(0)\r
-\r
-/**\r
-  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode\r
-  *         After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).\r
-  * @param  __MSIRANGEVALUE__ specifies the MSI clock range.\r
-  *         This parameter must be one of the following values:\r
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz\r
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz\r
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)\r
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \\r
-                  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)\r
-\r
-/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode\r
-  * @retval MSI clock range.\r
-  *         This parameter must be one of the following values:\r
-  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz\r
-  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz\r
-  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz\r
-  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz\r
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz\r
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz\r
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)\r
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz\r
-  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz\r
-  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz\r
-  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz\r
-  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz\r
-  */\r
-#define __HAL_RCC_GET_MSI_RANGE()                                              \\r
-                  ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ?             \\r
-                   READ_BIT(RCC->CR, RCC_CR_MSIRANGE) :                        \\r
-                   (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U))\r
-\r
-/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).\r
-  * @note   After enabling the LSI, the application software should wait on\r
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can\r
-  *         be used to clock the IWDG and/or the RTC.\r
-  * @note   LSI can not be disabled if the IWDG is running.\r
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
-  *         clock cycles.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)\r
-\r
-#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)\r
-\r
-/**\r
-  * @brief  Macro to configure the External High Speed oscillator (HSE).\r
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
-  *         supported by this macro. User should request a transition to HSE Off\r
-  *         first and then HSE On or HSE Bypass.\r
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
-  *         software should wait on HSERDY flag to be set indicating that HSE clock\r
-  *         is stable and can be used to clock the PLL and/or system clock.\r
-  * @note   HSE state can not be changed if it is used directly or through the\r
-  *         PLL as system clock. In this case, you have to select another source\r
-  *         of the system clock then change the HSE state (ex. disable it).\r
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)\r
-  *         was previously enabled you have to enable it again after calling this\r
-  *         function.\r
-  * @param  __STATE__ specifies the new state of the HSE.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after\r
-  *                              6 HSE oscillator clock cycles.\r
-  *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.\r
-  *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_HSE_CONFIG(__STATE__)                      \\r
-                    do {                                     \\r
-                      if((__STATE__) == RCC_HSE_ON)          \\r
-                      {                                      \\r
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \\r
-                      }                                      \\r
-                      else if((__STATE__) == RCC_HSE_BYPASS) \\r
-                      {                                      \\r
-                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \\r
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \\r
-                      }                                      \\r
-                      else                                   \\r
-                      {                                      \\r
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \\r
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \\r
-                      }                                      \\r
-                    } while(0)\r
-\r
-/**\r
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).\r
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
-  *         supported by this macro. User should request a transition to LSE Off\r
-  *         first and then LSE On or LSE Bypass.\r
-  * @note   As the LSE is in the Backup domain and write access is denied to\r
-  *         this domain after reset, you have to enable write access using\r
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
-  *         (to be done once after reset).\r
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
-  *         software should wait on LSERDY flag to be set indicating that LSE clock\r
-  *         is stable and can be used to clock the RTC.\r
-  * @param  __STATE__ specifies the new state of the LSE.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after\r
-  *                              6 LSE oscillator clock cycles.\r
-  *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.\r
-  *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LSE_CONFIG(__STATE__)                        \\r
-                    do {                                       \\r
-                      if((__STATE__) == RCC_LSE_ON)            \\r
-                      {                                        \\r
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\r
-                      }                                        \\r
-                      else if((__STATE__) == RCC_LSE_BYPASS)   \\r
-                      {                                        \\r
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \\r
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\r
-                      }                                        \\r
-                      else                                     \\r
-                      {                                        \\r
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \\r
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
-                      }                                        \\r
-                    } while(0)\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-\r
-/** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).\r
-  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.\r
-  * @note   After enabling the HSI48, the application software should wait on HSI48RDY\r
-  *         flag to be set indicating that HSI48 clock is stable.\r
-  *         This parameter can be: ENABLE or DISABLE.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_HSI48_ENABLE()  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)\r
-\r
-#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)\r
-\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-/** @brief  Macros to configure the RTC clock (RTCCLK).\r
-  * @note   As the RTC clock configuration bits are in the Backup domain and write\r
-  *         access is denied to this domain after reset, you have to enable write\r
-  *         access using the Power Backup Access macro before to configure\r
-  *         the RTC clock source (to be done once after reset).\r
-  * @note   Once the RTC clock is configured it cannot be changed unless the\r
-  *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by\r
-  *         a Power On Reset (POR).\r
-  *\r
-  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.\r
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.\r
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.\r
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected\r
-  *\r
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to\r
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.\r
-  *         However, when the HSE clock is used as RTC clock source, the RTC\r
-  *         cannot be used in STOP and STANDBY modes.\r
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
-  *         RTC clock source).\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \\r
-                  MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))\r
-\r
-\r
-/** @brief  Macro to get the RTC clock source.\r
-  * @retval The returned value can be one of the following:\r
-  *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.\r
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.\r
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.\r
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected\r
-  */\r
-#define  __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))\r
-\r
-/** @brief  Macros to enable or disable the main PLL.\r
-  * @note   After enabling the main PLL, the application software should wait on\r
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can\r
-  *         be used as system clock source.\r
-  * @note   The main PLL can not be disabled if it is used as system clock source\r
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)\r
-\r
-#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r
-\r
-/** @brief  Macro to configure the PLL clock source.\r
-  * @note   This function must be used only when the main PLL is disabled.\r
-  * @param  __PLLSOURCE__ specifies the PLL entry clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry\r
-  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry\r
-  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry\r
-  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry\r
-  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).\r
-  * @retval None\r
-  *\r
-  */\r
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \\r
-                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r
-\r
-/** @brief  Macro to configure the PLL source division factor M.\r
-  * @note   This function must be used only when the main PLL is disabled.\r
-  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\r
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.\r
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r
-  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency\r
-  *         of 16 MHz to limit PLL jitter.\r
-  * @retval None\r
-  *\r
-  */\r
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \\r
-                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)\r
-\r
-/**\r
-  * @brief  Macro to configure the main PLL clock source, multiplication and division factors.\r
-  * @note   This function must be used only when the main PLL is disabled.\r
-  *\r
-  * @param  __PLLSOURCE__ specifies the PLL entry clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry\r
-  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry\r
-  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry\r
-  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry\r
-  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).\r
-  *\r
-  * @param  __PLLM__ specifies the division factor for PLL VCO input clock.\r
-  *          This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
-  *          This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.\r
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r
-  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency\r
-  *         of 16 MHz to limit PLL jitter.\r
-  *\r
-  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock.\r
-  *          This parameter must be a number between 8 and 86.\r
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\r
-  *         output frequency is between 64 and 344 MHz.\r
-  *\r
-  * @param  __PLLP__ specifies the division factor for SAI clock when SAI available on device.\r
-  *          This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x\r
-  *          else (2 to 31).\r
-  *\r
-  * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.\r
-  *          This parameter must be in the range (2, 4, 6 or 8).\r
-  * @note   If the USB OTG FS is used in your application, you have to set the\r
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
-  *         the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work\r
-  *         correctly.\r
-  * @param  __PLLR__ specifies the division factor for the main system clock.\r
-  * @note   You have to set the PLLR parameter correctly to not exceed 80MHZ.\r
-  *          This parameter must be in the range (2, 4, 6 or 8).\r
-  * @retval None\r
-  */\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-\r
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \\r
-                  MODIFY_REG(RCC->PLLCFGR, \\r
-                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
-                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \\r
-                             ((__PLLSOURCE__) | \\r
-                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
-                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
-                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
-                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \\r
-                              ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))\r
-\r
-#elif defined(RCC_PLLP_SUPPORT)\r
-\r
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \\r
-                  MODIFY_REG(RCC->PLLCFGR, \\r
-                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
-                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \\r
-                             ((__PLLSOURCE__) | \\r
-                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
-                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
-                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
-                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \\r
-                              (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos)))\r
-\r
-#else\r
-\r
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \\r
-                  MODIFY_REG(RCC->PLLCFGR, \\r
-                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
-                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \\r
-                             ((__PLLSOURCE__) | \\r
-                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
-                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
-                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
-                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))\r
-\r
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
-\r
-/** @brief  Macro to get the oscillator used as PLL clock source.\r
-  * @retval The oscillator used as PLL clock source. The returned value can be one\r
-  *         of the following:\r
-  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.\r
-  *              - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.\r
-  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r
-  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r
-  */\r
-#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))\r
-\r
-/**\r
-  * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)\r
-  * @note   Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime\r
-  *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot\r
-  *         be stopped if used as System Clock.\r
-  * @param  __PLLCLOCKOUT__ specifies the PLL clock to be output.\r
-  *          This parameter can be one or a combination of the following values:\r
-  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                   high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),\r
-  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
-  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
-\r
-#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
-\r
-/**\r
-  * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)\r
-  * @param  __PLLCLOCKOUT__ specifies the output PLL clock to be checked.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                   high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),\r
-  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
-  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)\r
-  * @retval SET / RESET\r
-  */\r
-#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
-\r
-/**\r
-  * @brief  Macro to configure the system clock source.\r
-  * @param  __SYSCLKSOURCE__ specifies the system clock source.\r
-  *          This parameter can be one of the following values:\r
-  *              - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.\r
-  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r
-  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r
-  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))\r
-\r
-/** @brief  Macro to get the clock source used as system clock.\r
-  * @retval The clock source used as system clock. The returned value can be one\r
-  *         of the following:\r
-  *              - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.\r
-  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r
-  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r
-  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r
-  */\r
-#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))\r
-\r
-/**\r
-  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.\r
-  * @note   As the LSE is in the Backup domain and write access is denied to\r
-  *         this domain after reset, you have to enable write access using\r
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
-  *         (to be done once after reset).\r
-  * @param  __LSEDRIVE__ specifies the new state of the LSE drive capability.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.\r
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.\r
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.\r
-  *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \\r
-                  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))\r
-\r
-/**\r
-  * @brief  Macro to configure the wake up from stop clock.\r
-  * @param  __STOPWUCLK__ specifies the clock source used after wake up from stop.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI selected as system clock source\r
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI selected as system clock source\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \\r
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))\r
-\r
-\r
-/** @brief  Macro to configure the MCO clock.\r
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled\r
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee\r
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48\r
-  @endif\r
-  * @param  __MCODIV__ specifies the MCO clock prescaler.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1\r
-  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2\r
-  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4\r
-  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8\r
-  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16\r
-  */\r
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
-                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r
-\r
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
-  * @brief macros to manage the specified RCC Flags and interrupts.\r
-  * @{\r
-  */\r
-\r
-/** @brief  Enable RCC interrupt(s).\r
-  * @param  __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.\r
-  *         This parameter can be any combination of the following values:\r
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
-  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))\r
-\r
-/** @brief Disable RCC interrupt(s).\r
-  * @param  __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.\r
-  *         This parameter can be any combination of the following values:\r
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
-  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))\r
-\r
-/** @brief  Clear the RCC's interrupt pending bits.\r
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\r
-  *         This parameter can be any combination of the following values:\r
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
-  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
-  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt\r
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))\r
-\r
-/** @brief  Check whether the RCC interrupt has occurred or not.\r
-  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt\r
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt\r
-  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt\r
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt\r
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt\r
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt for devices with PLLSAI1\r
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2\r
-  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt\r
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
-  @endif\r
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))\r
-\r
-/** @brief Set RMVF bit to clear the reset flags.\r
-  *        The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,\r
-  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r
-  * @retval None\r
- */\r
-#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)\r
-\r
-/** @brief  Check whether the selected RCC flag is set or not.\r
-  * @param  __FLAG__ specifies the flag to check.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_FLAG_MSIRDY  MSI oscillator clock ready\r
-  *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready\r
-  *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready\r
-  *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready\r
-  *            @arg @ref RCC_FLAG_PLLSAI1RDY  PLLSAI1 clock ready for devices with PLLSAI1\r
-  *            @arg @ref RCC_FLAG_PLLSAI2RDY  PLLSAI2 clock ready for devices with PLLSAI2\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48\r
-  @endif\r
-  *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready\r
-  *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection\r
-  *            @arg @ref RCC_FLAG_LSIRDY  LSI oscillator clock ready\r
-  *            @arg @ref RCC_FLAG_BORRST  BOR reset\r
-  *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset\r
-  *            @arg @ref RCC_FLAG_PINRST  Pin reset\r
-  *            @arg @ref RCC_FLAG_FWRST  FIREWALL reset\r
-  *            @arg @ref RCC_FLAG_SFTRST  Software reset\r
-  *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset\r
-  *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset\r
-  *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset\r
-  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
-  */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \\r
-                                        ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR :                 \\r
-                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \\r
-                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) &   \\r
-                                          (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)\r
-#else\r
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \\r
-                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \\r
-                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) &    \\r
-                                          (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Constants RCC Private Constants\r
-  * @{\r
-  */\r
-/* Defines used for Flags */\r
-#define CR_REG_INDEX              1U\r
-#define BDCR_REG_INDEX            2U\r
-#define CSR_REG_INDEX             3U\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define CRRCR_REG_INDEX           4U\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define RCC_FLAG_MASK             0x1FU\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @addtogroup RCC_Private_Macros\r
-  * @{\r
-  */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)   == RCC_OSCILLATORTYPE_MSI)   || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE))\r
-#else\r
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \\r
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \\r
-                              ((__HSE__) == RCC_HSE_BYPASS))\r
-\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \\r
-                              ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS))\r
-#else\r
-#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \\r
-                              ((__LSE__) == RCC_LSE_BYPASS))\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-\r
-#define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))\r
-\r
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))\r
-\r
-#define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))\r
-\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-#define IS_RCC_LSIDIV(__LSIDIV__)  (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-#define IS_RCC_MSI(__MSI__)  (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))\r
-\r
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \\r
-                             ((__PLL__) == RCC_PLL_ON))\r
-\r
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \\r
-                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \\r
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \\r
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))\r
-\r
-#if defined(RCC_PLLM_DIV_1_16_SUPPORT)\r
-#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))\r
-#else\r
-#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))\r
-#endif /*RCC_PLLM_DIV_1_16_SUPPORT */\r
-\r
-#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))\r
-\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))\r
-#else\r
-#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))\r
-#endif /*RCC_PLLP_DIV_2_31_SUPPORT */\r
-\r
-#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
-                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-\r
-#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
-                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \\r
-                                                  (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK)  || \\r
-                                                  (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \\r
-                                                 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK)  || \\r
-                                                  (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \\r
-                                                 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))\r
-#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK)  || \\r
-                                                  (((__VALUE__) & RCC_PLLSAI2_DSICLK)  == RCC_PLLSAI2_DSICLK)   || \\r
-                                                  (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \\r
-                                                 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U))\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_1)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_2)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_3)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_4)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_5)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_6)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_7)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_8)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_9)  || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_10) || \\r
-                                           ((__RANGE__) == RCC_MSIRANGE_11))\r
-\r
-#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4)  || \\r
-                                                   ((__RANGE__) == RCC_MSIRANGE_5)  || \\r
-                                                   ((__RANGE__) == RCC_MSIRANGE_6)  || \\r
-                                                   ((__RANGE__) == RCC_MSIRANGE_7))\r
-\r
-#define IS_RCC_CLOCKTYPE(__CLK__)  ((1U <= (__CLK__)) && ((__CLK__) <= 15U))\r
-\r
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \\r
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \\r
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \\r
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))\r
-\r
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \\r
-                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \\r
-                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \\r
-                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \\r
-                               ((__HCLK__) == RCC_SYSCLK_DIV512))\r
-\r
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \\r
-                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \\r
-                               ((__PCLK__) == RCC_HCLK_DIV16))\r
-\r
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE)   || \\r
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \\r
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \\r
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))\r
-\r
-#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))\r
-#else\r
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \\r
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE))\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \\r
-                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \\r
-                                ((__DIV__) == RCC_MCODIV_16))\r
-\r
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \\r
-                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \\r
-                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \\r
-                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))\r
-\r
-#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \\r
-                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include RCC HAL Extended module */\r
-#include "stm32l4xx_hal_rcc_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup RCC_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-\r
-/** @addtogroup RCC_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-\r
-/* Initialization and de-initialization functions  ******************************/\r
-HAL_StatusTypeDef HAL_RCC_DeInit(void);\r
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup RCC_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-\r
-/* Peripheral Control functions  ************************************************/\r
-void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
-void              HAL_RCC_EnableCSS(void);\r
-uint32_t          HAL_RCC_GetSysClockFreq(void);\r
-uint32_t          HAL_RCC_GetHCLKFreq(void);\r
-uint32_t          HAL_RCC_GetPCLK1Freq(void);\r
-uint32_t          HAL_RCC_GetPCLK2Freq(void);\r
-void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
-void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
-/* CSS NMI IRQ handler */\r
-void              HAL_RCC_NMI_IRQHandler(void);\r
-/* User Callbacks in non blocking mode (IT mode) */\r
-void              HAL_RCC_CSSCallback(void);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_RCC_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
deleted file mode 100644 (file)
index 8f5a2fb..0000000
+++ /dev/null
@@ -1,3125 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_rcc_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of RCC HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_RCC_EX_H\r
-#define __STM32L4xx_HAL_RCC_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup RCCEx\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
-  * @{\r
-  */\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-/**\r
-  * @brief  PLLSAI1 Clock structure definition\r
-  */\r
-typedef struct\r
-{\r
-\r
-  uint32_t PLLSAI1Source;    /*!< PLLSAI1Source: PLLSAI1 entry clock source.\r
-                                  This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
-\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-  uint32_t PLLSAI1M;         /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.\r
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r
-#else\r
-  uint32_t PLLSAI1M;         /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.\r
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 8 */\r
-#endif\r
-\r
-  uint32_t PLLSAI1N;         /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.\r
-                                  This parameter must be a number between 8 and 86 or 127 depending on devices. */\r
-\r
-  uint32_t PLLSAI1P;         /*!< PLLSAI1P: specifies the division factor for SAI clock.\r
-                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
-\r
-  uint32_t PLLSAI1Q;         /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.\r
-                                  This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */\r
-\r
-  uint32_t PLLSAI1R;         /*!< PLLSAI1R: specifies the division factor for ADC clock.\r
-                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */\r
-\r
-  uint32_t PLLSAI1ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.\r
-                                  This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */\r
-}RCC_PLLSAI1InitTypeDef;\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-/**\r
-  * @brief  PLLSAI2 Clock structure definition\r
-  */\r
-typedef struct\r
-{\r
-\r
-  uint32_t PLLSAI2Source;    /*!< PLLSAI2Source: PLLSAI2 entry clock source.\r
-                                  This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
-\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-  uint32_t PLLSAI2M;         /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.\r
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r
-#else\r
-  uint32_t PLLSAI2M;         /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.\r
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 8 */\r
-#endif\r
-\r
-  uint32_t PLLSAI2N;         /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.\r
-                                  This parameter must be a number between 8 and 86 or 127 depending on devices. */\r
-\r
-  uint32_t PLLSAI2P;         /*!< PLLSAI2P: specifies the division factor for SAI clock.\r
-                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
-\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-  uint32_t PLLSAI2Q;         /*!< PLLSAI2Q: specifies the division factor for DSI clock.\r
-                                  This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */\r
-#endif\r
-\r
-  uint32_t PLLSAI2R;         /*!< PLLSAI2R: specifies the division factor for ADC clock.\r
-                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */\r
-\r
-  uint32_t PLLSAI2ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.\r
-                                  This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */\r
-}RCC_PLLSAI2InitTypeDef;\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-/**\r
-  * @brief  RCC extended clocks structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.\r
-                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-  RCC_PLLSAI1InitTypeDef PLLSAI1;  /*!< PLLSAI1 structure parameters.\r
-                                        This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-  RCC_PLLSAI2InitTypeDef PLLSAI2;  /*!< PLLSAI2 structure parameters.\r
-                                        This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-  uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source */\r
-\r
-  uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source */\r
-\r
-#if defined(USART3)\r
-\r
-  uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_USART3_Clock_Source */\r
-\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-\r
-  uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_UART4_Clock_Source */\r
-\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-\r
-  uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_UART5_Clock_Source */\r
-\r
-#endif /* UART5 */\r
-\r
-  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */\r
-\r
-  uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */\r
-\r
-#if defined(I2C2)\r
-\r
-  uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */\r
-\r
-#endif /* I2C2 */\r
-\r
-  uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */\r
-\r
-#if defined(I2C4)\r
-\r
-  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r
-\r
-#endif /* I2C4 */\r
-\r
-  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r
-\r
-  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */\r
-#if defined(SAI1)\r
-\r
-  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-\r
-  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\r
-\r
-#endif /* SAI2 */\r
-\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-\r
-  uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).\r
-                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source */\r
-\r
-#endif /* USB_OTG_FS || USB */\r
-\r
-#if defined(SDMMC1)\r
-\r
-  uint32_t Sdmmc1ClockSelection;   /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).\r
-                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */\r
-\r
-#endif /* SDMMC1 */\r
-\r
-  uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).\r
-                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source */\r
-\r
-#if !defined(STM32L412xx) && !defined(STM32L422xx)\r
-  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.\r
-                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source */\r
-#endif /* !STM32L412xx && !STM32L422xx */\r
-\r
-#if defined(SWPMI1)\r
-\r
-  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */\r
-\r
-#endif /* SWPMI1 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-\r
-  uint32_t Dfsdm1ClockSelection;   /*!< Specifies DFSDM1 clock source.\r
-                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-  uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source.\r
-                                        This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-\r
-  uint32_t LtdcClockSelection;     /*!< Specifies LTDC clock source.\r
-                                        This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */\r
-\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-\r
-  uint32_t DsiClockSelection;      /*!< Specifies DSI clock source.\r
-                                        This parameter can be a value of @ref RCCEx_DSI_Clock_Source */\r
-\r
-#endif /* DSI */\r
-\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-\r
-  uint32_t OspiClockSelection;     /*!< Specifies OctoSPI clock source.\r
-                                        This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */\r
-\r
-#endif\r
-\r
-  uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.\r
-                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */\r
-}RCC_PeriphCLKInitTypeDef;\r
-\r
-#if defined(CRS)\r
-\r
-/**\r
-  * @brief RCC_CRS Init structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.\r
-                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */\r
-\r
-  uint32_t Source;                /*!< Specifies the SYNC signal source.\r
-                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource */\r
-\r
-  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.\r
-                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */\r
-\r
-  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.\r
-                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)\r
-                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/\r
-\r
-  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.\r
-                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */\r
-\r
-  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.\r
-                                     This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise,\r
-                                     or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */\r
-\r
-}RCC_CRSInitTypeDef;\r
-\r
-/**\r
-  * @brief RCC_CRS Synchronization structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.\r
-                                     This parameter must be a number between 0 and 0xFFFF */\r
-\r
-  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.\r
-                                     This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */\r
-\r
-  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter\r
-                                                                    value latched in the time of the last SYNC event.\r
-                                    This parameter must be a number between 0 and 0xFFFF */\r
-\r
-  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the\r
-                                                                    frequency error counter latched in the time of the last SYNC event.\r
-                                                                    It shows whether the actual frequency is below or above the target.\r
-                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/\r
-\r
-}RCC_CRSSynchroInfoTypeDef;\r
-\r
-#endif /* CRS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source\r
-  * @{\r
-  */\r
-#define RCC_LSCOSOURCE_LSI             0x00000000U         /*!< LSI selection for low speed clock output */\r
-#define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL    /*!< LSE selection for low speed clock output */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection\r
-  * @{\r
-  */\r
-#define RCC_PERIPHCLK_USART1           0x00000001U\r
-#define RCC_PERIPHCLK_USART2           0x00000002U\r
-#if defined(USART3)\r
-#define RCC_PERIPHCLK_USART3           0x00000004U\r
-#endif\r
-#if defined(UART4)\r
-#define RCC_PERIPHCLK_UART4            0x00000008U\r
-#endif\r
-#if defined(UART5)\r
-#define RCC_PERIPHCLK_UART5            0x00000010U\r
-#endif\r
-#define RCC_PERIPHCLK_LPUART1          0x00000020U\r
-#define RCC_PERIPHCLK_I2C1             0x00000040U\r
-#if defined(I2C2)\r
-#define RCC_PERIPHCLK_I2C2             0x00000080U\r
-#endif\r
-#define RCC_PERIPHCLK_I2C3             0x00000100U\r
-#define RCC_PERIPHCLK_LPTIM1           0x00000200U\r
-#define RCC_PERIPHCLK_LPTIM2           0x00000400U\r
-#if defined(SAI1)\r
-#define RCC_PERIPHCLK_SAI1             0x00000800U\r
-#endif\r
-#if defined(SAI2)\r
-#define RCC_PERIPHCLK_SAI2             0x00001000U\r
-#endif\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-#define RCC_PERIPHCLK_USB              0x00002000U\r
-#endif\r
-#define RCC_PERIPHCLK_ADC              0x00004000U\r
-#if defined(SWPMI1)\r
-#define RCC_PERIPHCLK_SWPMI1           0x00008000U\r
-#endif\r
-#if defined(DFSDM1_Filter0)\r
-#define RCC_PERIPHCLK_DFSDM1           0x00010000U\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define RCC_PERIPHCLK_DFSDM1AUDIO      0x00200000U\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-#endif\r
-#define RCC_PERIPHCLK_RTC              0x00020000U\r
-#define RCC_PERIPHCLK_RNG              0x00040000U\r
-#if defined(SDMMC1)\r
-#define RCC_PERIPHCLK_SDMMC1           0x00080000U\r
-#endif\r
-#if defined(I2C4)\r
-#define RCC_PERIPHCLK_I2C4             0x00100000U\r
-#endif\r
-#if defined(LTDC)\r
-#define RCC_PERIPHCLK_LTDC             0x00400000U\r
-#endif\r
-#if defined(DSI)\r
-#define RCC_PERIPHCLK_DSI              0x00800000U\r
-#endif\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-#define RCC_PERIPHCLK_OSPI             0x01000000U\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_USART1CLKSOURCE_PCLK2      0x00000000U\r
-#define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0\r
-#define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1\r
-#define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_USART2CLKSOURCE_PCLK1      0x00000000U\r
-#define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0\r
-#define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1\r
-#define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(USART3)\r
-/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_USART3CLKSOURCE_PCLK1      0x00000000U\r
-#define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0\r
-#define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1\r
-#define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)\r
-/**\r
-  * @}\r
-  */\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_UART4CLKSOURCE_PCLK1       0x00000000U\r
-#define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0\r
-#define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1\r
-#define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)\r
-/**\r
-  * @}\r
-  */\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_UART5CLKSOURCE_PCLK1       0x00000000U\r
-#define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0\r
-#define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1\r
-#define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)\r
-/**\r
-  * @}\r
-  */\r
-#endif /* UART5 */\r
-\r
-/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_LPUART1CLKSOURCE_PCLK1     0x00000000U\r
-#define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0\r
-#define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1\r
-#define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_I2C1CLKSOURCE_PCLK1        0x00000000U\r
-#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0\r
-#define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(I2C2)\r
-/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_I2C2CLKSOURCE_PCLK1        0x00000000U\r
-#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0\r
-#define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1\r
-/**\r
-  * @}\r
-  */\r
-#endif /* I2C2 */\r
-\r
-/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_I2C3CLKSOURCE_PCLK1        0x00000000U\r
-#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0\r
-#define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(I2C4)\r
-/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_I2C4CLKSOURCE_PCLK1        0x00000000U\r
-#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_CCIPR2_I2C4SEL_0\r
-#define RCC_I2C4CLKSOURCE_HSI          RCC_CCIPR2_I2C4SEL_1\r
-/**\r
-  * @}\r
-  */\r
-#endif /* I2C4 */\r
-\r
-#if defined(SAI1)\r
-/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_SAI1CLKSOURCE_PLLSAI1      0x00000000U\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR2_SAI1SEL_0\r
-#else\r
-#define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI1SEL_0\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR2_SAI1SEL_1\r
-#define RCC_SAI1CLKSOURCE_PIN          (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)\r
-#define RCC_SAI1CLKSOURCE_HSI          RCC_CCIPR2_SAI1SEL_2\r
-#else\r
-#define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_1\r
-#define RCC_SAI1CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_SAI2CLKSOURCE_PLLSAI1      0x00000000U\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR2_SAI2SEL_0\r
-#define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR2_SAI2SEL_1\r
-#define RCC_SAI2CLKSOURCE_PIN          (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)\r
-#define RCC_SAI2CLKSOURCE_HSI          RCC_CCIPR2_SAI2SEL_2\r
-#else\r
-#define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI2SEL_0\r
-#define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR_SAI2SEL_1\r
-#define RCC_SAI2CLKSOURCE_PIN          RCC_CCIPR_SAI2SEL\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* SAI2 */\r
-\r
-/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_LPTIM1CLKSOURCE_PCLK1      0x00000000U\r
-#define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0\r
-#define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1\r
-#define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_LPTIM2CLKSOURCE_PCLK1      0x00000000U\r
-#define RCC_LPTIM2CLKSOURCE_LSI        RCC_CCIPR_LPTIM2SEL_0\r
-#define RCC_LPTIM2CLKSOURCE_HSI        RCC_CCIPR_LPTIM2SEL_1\r
-#define RCC_LPTIM2CLKSOURCE_LSE        RCC_CCIPR_LPTIM2SEL\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(SDMMC1)\r
-/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source\r
-  * @{\r
-  */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_SDMMC1CLKSOURCE_HSI48      0x00000000U  /*!< HSI48 clock selected as SDMMC1 clock          */\r
-#else\r
-#define RCC_SDMMC1CLKSOURCE_NONE       0x00000000U  /*!< No clock selected as SDMMC1 clock             */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-#define RCC_SDMMC1CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0     /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock    */\r
-#define RCC_SDMMC1CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1     /*!< PLL "Q" clock selected as SDMMC1 clock        */\r
-#define RCC_SDMMC1CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL       /*!< MSI clock selected as SDMMC1 clock            */\r
-#if defined(RCC_CCIPR2_SDMMCSEL)\r
-#define RCC_SDMMC1CLKSOURCE_PLLP       RCC_CCIPR2_SDMMCSEL      /*!< PLL "P" clock selected as SDMMC1 kernel clock */\r
-#endif /* RCC_CCIPR2_SDMMCSEL */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* SDMMC1 */\r
-\r
-/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source\r
-  * @{\r
-  */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_RNGCLKSOURCE_HSI48         0x00000000U\r
-#else\r
-#define RCC_RNGCLKSOURCE_NONE          0x00000000U\r
-#endif /* RCC_HSI48_SUPPORT */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_RNGCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1\r
-#define RCC_RNGCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-/** @defgroup RCCEx_USB_Clock_Source USB Clock Source\r
-  * @{\r
-  */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_USBCLKSOURCE_HSI48         0x00000000U\r
-#else\r
-#define RCC_USBCLKSOURCE_NONE          0x00000000U\r
-#endif /* RCC_HSI48_SUPPORT */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_USBCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1\r
-#define RCC_USBCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL\r
-/**\r
-  * @}\r
-  */\r
-#endif /* USB_OTG_FS || USB */\r
-\r
-/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source\r
-  * @{\r
-  */\r
-#define RCC_ADCCLKSOURCE_NONE         0x00000000U\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_ADCCLKSOURCE_PLLSAI1      RCC_CCIPR_ADCSEL_0\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-#define RCC_ADCCLKSOURCE_PLLSAI2      RCC_CCIPR_ADCSEL_1\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-#if defined(RCC_CCIPR_ADCSEL)\r
-#define RCC_ADCCLKSOURCE_SYSCLK       RCC_CCIPR_ADCSEL\r
-#else\r
-#define RCC_ADCCLKSOURCE_SYSCLK       0x30000000U\r
-#endif /* RCC_CCIPR_ADCSEL */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(SWPMI1)\r
-/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_SWPMI1CLKSOURCE_PCLK1      0x00000000U\r
-#define RCC_SWPMI1CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL\r
-/**\r
-  * @}\r
-  */\r
-#endif /* SWPMI1 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source\r
-  * @{\r
-  */\r
-#define RCC_DFSDM1CLKSOURCE_PCLK2      0x00000000U\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define RCC_DFSDM1CLKSOURCE_SYSCLK     RCC_CCIPR2_DFSDM1SEL\r
-#else\r
-#define RCC_DFSDM1CLKSOURCE_SYSCLK     RCC_CCIPR_DFSDM1SEL\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source\r
-  * @{\r
-  */\r
-#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1   0x00000000U\r
-#define RCC_DFSDM1AUDIOCLKSOURCE_HSI    RCC_CCIPR2_ADFSDM1SEL_0\r
-#define RCC_DFSDM1AUDIOCLKSOURCE_MSI    RCC_CCIPR2_ADFSDM1SEL_1\r
-/**\r
-  * @}\r
-  */\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source\r
-  * @{\r
-  */\r
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2  0x00000000U\r
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4  RCC_CCIPR2_PLLSAI2DIVR_0\r
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8  RCC_CCIPR2_PLLSAI2DIVR_1\r
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR\r
-/**\r
-  * @}\r
-  */\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source\r
-  * @{\r
-  */\r
-#define RCC_DSICLKSOURCE_DSIPHY        0x00000000U\r
-#define RCC_DSICLKSOURCE_PLLSAI2       RCC_CCIPR2_DSISEL\r
-/**\r
-  * @}\r
-  */\r
-#endif /* DSI */\r
-\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source\r
-  * @{\r
-  */\r
-#define RCC_OSPICLKSOURCE_SYSCLK    0x00000000U\r
-#define RCC_OSPICLKSOURCE_MSI       RCC_CCIPR2_OSPISEL_0\r
-#define RCC_OSPICLKSOURCE_PLL       RCC_CCIPR2_OSPISEL_1\r
-/**\r
-  * @}\r
-  */\r
-#endif /* OCTOSPI1 || OCTOSPI2 */\r
-\r
-/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line\r
-  * @{\r
-  */\r
-#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(CRS)\r
-\r
-/** @defgroup RCCEx_CRS_Status RCCEx CRS Status\r
-  * @{\r
-  */\r
-#define RCC_CRS_NONE                   0x00000000U\r
-#define RCC_CRS_TIMEOUT                0x00000001U\r
-#define RCC_CRS_SYNCOK                 0x00000002U\r
-#define RCC_CRS_SYNCWARN               0x00000004U\r
-#define RCC_CRS_SYNCERR                0x00000008U\r
-#define RCC_CRS_SYNCMISS               0x00000010U\r
-#define RCC_CRS_TRIMOVF                0x00000020U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource\r
-  * @{\r
-  */\r
-#define RCC_CRS_SYNC_SOURCE_GPIO       0x00000000U             /*!< Synchro Signal source GPIO */\r
-#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */\r
-#define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider\r
-  * @{\r
-  */\r
-#define RCC_CRS_SYNC_DIV1        0x00000000U                               /*!< Synchro Signal not divided (default) */\r
-#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */\r
-#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */\r
-#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */\r
-#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */\r
-#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */\r
-#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */\r
-#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity\r
-  * @{\r
-  */\r
-#define RCC_CRS_SYNC_POLARITY_RISING   0x00000000U         /*!< Synchro Active on rising edge (default) */\r
-#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL    /*!< Synchro Active on falling edge */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault\r
-  * @{\r
-  */\r
-#define RCC_CRS_RELOADVALUE_DEFAULT    0x0000BB7FU   /*!< The reset value of the RELOAD field corresponds\r
-                                                          to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault\r
-  * @{\r
-  */\r
-#define RCC_CRS_ERRORLIMIT_DEFAULT     0x00000022U   /*!< Default Frequency error limit */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault\r
-  * @{\r
-  */\r
-#if defined(STM32L412xx) || defined(STM32L422xx)\r
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval.\r
-                                                          The trimming step is specified in the product datasheet. A higher TRIM value\r
-                                                          corresponds to a higher output frequency */\r
-#else\r
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval.\r
-                                                          The trimming step is specified in the product datasheet. A higher TRIM value\r
-                                                          corresponds to a higher output frequency */\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection\r
-  * @{\r
-  */\r
-#define RCC_CRS_FREQERRORDIR_UP        0x00000000U   /*!< Upcounting direction, the actual frequency is above the target */\r
-#define RCC_CRS_FREQERRORDIR_DOWN      CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources\r
-  * @{\r
-  */\r
-#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */\r
-#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */\r
-#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */\r
-#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */\r
-#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */\r
-#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */\r
-#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags\r
-  * @{\r
-  */\r
-#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */\r
-#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */\r
-#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */\r
-#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */\r
-#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */\r
-#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/\r
-#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* CRS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
- * @{\r
- */\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-/**\r
-  * @brief  Macro to configure the PLLSAI1 clock multiplication and division factors.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI1 is disabled.\r
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  @if STM32L4S9xx\r
-  * @param  __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock.\r
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
-  *\r
-  @endif\r
-  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.\r
-  *         This parameter must be a number between 8 and 86.\r
-  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO\r
-  *         output frequency is between 64 and 344 MHz.\r
-  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N\r
-  *\r
-  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.\r
-  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx\r
-  *         else (2 to 31).\r
-  *         SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P\r
-  *\r
-  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.\r
-  *         This parameter must be in the range (2, 4, 6 or 8).\r
-  *         USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q\r
-  *\r
-  * @param  __PLLSAI1R__ specifies the division factor for SAR ADC clock.\r
-  *         This parameter must be in the range (2, 4, 6 or 8).\r
-  *         ADC clock frequency = f(PLLSAI1) / PLLSAI1R\r
-  *\r
-  * @retval None\r
-  */\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-\r
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
-                             (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
-                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \\r
-                             ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \\r
-                              ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
-                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
-                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
-                              ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))\r
-\r
-#else\r
-\r
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
-                             (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
-                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \\r
-                             ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \\r
-                              ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
-                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
-                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
-                              (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))\r
-\r
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
-\r
-#else\r
-\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-\r
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
-                             (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
-                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \\r
-                             (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
-                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
-                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
-                              ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))\r
-\r
-#else\r
-\r
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, \\r
-                             (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \\r
-                              RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \\r
-                             (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \\r
-                              ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \\r
-                              ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \\r
-                              (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))\r
-\r
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
-\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-\r
-/**\r
-  * @brief  Macro to configure the PLLSAI1 clock multiplication factor N.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI1 is disabled.\r
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.\r
-  *          This parameter must be a number between 8 and 86.\r
-  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO\r
-  *         output frequency is between 64 and 344 MHz.\r
-  *         Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)\r
-\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-\r
-/** @brief  Macro to configure the PLLSAI1 input clock division factor M.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI1 is disabled.\r
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI1M__ specifies the division factor for PLLSAI1 clock.\r
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
-  *\r
-  * @retval None\r
-  */\r
-\r
-#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)\r
-\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-\r
-/** @brief  Macro to configure the PLLSAI1 clock division factor P.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI1 is disabled.\r
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.\r
-  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx\r
-  *         else (2 to 31).\r
-  *         Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P\r
-  *\r
-  * @retval None\r
-  */\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-\r
-#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)\r
-\r
-#else\r
-\r
-#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)\r
-\r
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
-\r
-/** @brief  Macro to configure the PLLSAI1 clock division factor Q.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI1 is disabled.\r
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.\r
-  *         This parameter must be in the range (2, 4, 6 or 8).\r
-  *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)\r
-\r
-/** @brief  Macro to configure the PLLSAI1 clock division factor R.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI1 is disabled.\r
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI1R__ specifies the division factor for ADC clock.\r
-  *         This parameter must be in the range (2, 4, 6 or 8)\r
-  *         Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \\r
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)\r
-\r
-/**\r
-  * @brief  Macros to enable or disable the PLLSAI1.\r
-  * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.\r
-  * @retval None\r
-  */\r
-\r
-#define __HAL_RCC_PLLSAI1_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)\r
-\r
-#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)\r
-\r
-/**\r
-  * @brief  Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).\r
-  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.\r
-  *         This is mainly used to save Power.\r
-  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.\r
-  *         This parameter can be one or a combination of the following values:\r
-  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                   high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),\r
-  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
-  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.\r
-  * @retval None\r
-  */\r
-\r
-#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__)   SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))\r
-\r
-#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__)  CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))\r
-\r
-/**\r
-  * @brief  Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).\r
-  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                   high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),\r
-  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
-  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.\r
-  * @retval SET / RESET\r
-  */\r
-#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__)  READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-/**\r
-  * @brief  Macro to configure the PLLSAI2 clock multiplication and division factors.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI2 is disabled.\r
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  @if STM32L4S9xx\r
-  * @param  __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock.\r
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
-  *\r
-  @endif\r
-  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.\r
-  *          This parameter must be a number between 8 and 86.\r
-  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO\r
-  *         output frequency is between 64 and 344 MHz.\r
-  *\r
-  * @param  __PLLSAI2P__ specifies the division factor for SAI clock.\r
-  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx\r
-  *         else (2 to 31).\r
-  *         SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P\r
-  *\r
-  @if STM32L4S9xx\r
-  * @param  __PLLSAI2Q__ specifies the division factor for DSI clock.\r
-  *         This parameter must be in the range (2, 4, 6 or 8).\r
-  *         DSI clock frequency = f(PLLSAI2) / PLLSAI2Q\r
-  *\r
-  @endif\r
-  * @param  __PLLSAI2R__ specifies the division factor for SAR ADC clock.\r
-  *         This parameter must be in the range (2, 4, 6 or 8).\r
-  *\r
-  * @retval None\r
-  */\r
-\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-\r
-# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-\r
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
-                             (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
-                              RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
-                             ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \\r
-                              ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
-                              ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \\r
-                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
-                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
-\r
-# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
-\r
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
-                             (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
-                              RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
-                             ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \\r
-                              ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
-                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
-                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
-\r
-# else\r
-\r
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
-                             (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
-                              RCC_PLLSAI2CFGR_PLLSAI2R), \\r
-                             ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \\r
-                              ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
-                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
-                              (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))\r
-\r
-# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
-\r
-#else\r
-\r
-#  if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-\r
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
-                             (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
-                              RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
-                             (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
-                              ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \\r
-                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
-                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
-\r
-# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
-\r
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
-                             (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
-                              RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \\r
-                             (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
-                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
-                              ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))\r
-\r
-# else\r
-\r
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, \\r
-                             (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \\r
-                              RCC_PLLSAI2CFGR_PLLSAI2R), \\r
-                             (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \\r
-                              ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \\r
-                              (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))\r
-\r
-# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
-\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
-\r
-\r
-/**\r
-  * @brief  Macro to configure the PLLSAI2 clock multiplication factor N.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI2 is disabled.\r
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.\r
-  *          This parameter must be a number between 8 and 86.\r
-  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO\r
-  *         output frequency is between 64 and 344 MHz.\r
-  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)\r
-\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-\r
-/** @brief  Macro to configure the PLLSAI2 input clock division factor M.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI2 is disabled.\r
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI2M__ specifies the division factor for PLLSAI2 clock.\r
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
-  *\r
-  * @retval None\r
-  */\r
-\r
-#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M,  ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)\r
-\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
-\r
-/** @brief  Macro to configure the PLLSAI2 clock division factor P.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI2 is disabled.\r
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI2P__ specifies the division factor.\r
-  *         This parameter must be a number in the range (7 or 17).\r
-  *         Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)\r
-\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-\r
-/** @brief  Macro to configure the PLLSAI2 clock division factor Q.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI2 is disabled.\r
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock.\r
-  *         This parameter must be in the range (2, 4, 6 or 8).\r
-  *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)\r
-\r
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
-\r
-/** @brief  Macro to configure the PLLSAI2 clock division factor R.\r
-  *\r
-  * @note   This function must be used only when the PLLSAI2 is disabled.\r
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through\r
-  *         __HAL_RCC_PLL_CONFIG() macro)\r
-  *\r
-  * @param  __PLLSAI2R__ specifies the division factor.\r
-  *         This parameter must be in the range (2, 4, 6 or 8).\r
-  *         Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__\r
-  *\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \\r
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)\r
-\r
-/**\r
-  * @brief  Macros to enable or disable the PLLSAI2.\r
-  * @note   The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.\r
-  * @retval None\r
-  */\r
-\r
-#define __HAL_RCC_PLLSAI2_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)\r
-\r
-#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)\r
-\r
-/**\r
-  * @brief  Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).\r
-  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.\r
-  *         This is mainly used to save Power.\r
-  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.\r
-  *         This parameter can be one or a combination of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                           high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                           high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                           high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI2_DSICLK   Clock used to clock DSI peripheral.\r
-  @endif\r
-  * @retval None\r
-  */\r
-\r
-#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__)  SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))\r
-\r
-#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))\r
-\r
-/**\r
-  * @brief  Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).\r
-  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.\r
-  *          This parameter can be one of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                           high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                           high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve\r
-  *                                           high-quality audio performance on SAI interface in case.\r
-  *            @arg @ref RCC_PLLSAI2_DSICLK   Clock used to clock DSI peripheral.\r
-  @endif\r
-  * @retval SET / RESET\r
-  */\r
-#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__)  READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#if defined(SAI1)\r
-\r
-/**\r
-  * @brief  Macro to configure the SAI1 clock source.\r
-  * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived\r
-  *         from the PLLSAI1, system PLL or external clock (through a dedicated pin).\r
-  *          This parameter can be one of the following values:\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
-  @if STM32L486xx\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2\r
-  @endif\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)\r
-  @if STM32L4S9xx\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_HSI  SAI1 clock = HSI16\r
-  @endif\r
-  *\r
-  @if STM32L443xx\r
-  * @note  HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.\r
-  @endif\r
-  *\r
-  * @retval None\r
-  */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__))\r
-#else\r
-#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/** @brief  Macro to get the SAI1 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
-  @if STM32L486xx\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2\r
-  @endif\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)\r
-  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)\r
-  *\r
-  * @note  Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1\r
-  *        clock source when PLLs are disabled for devices without PLLSAI2.\r
-  *\r
-  */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))\r
-#else\r
-#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-\r
-/**\r
-  * @brief  Macro to configure the SAI2 clock source.\r
-  * @param  __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived\r
-  *         from the PLLSAI2, system PLL or external clock (through a dedicated pin).\r
-  *          This parameter can be one of the following values:\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)\r
-  @if STM32L4S9xx\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_HSI  SAI2 clock = HSI16\r
-  @endif\r
-  *\r
-  * @retval None\r
-  */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__))\r
-#else\r
-#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/** @brief  Macro to get the SAI2 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)\r
-  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)\r
-  */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))\r
-#else\r
-#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* SAI2 */\r
-\r
-/** @brief  Macro to configure the I2C1 clock (I2C1CLK).\r
-  *\r
-  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock\r
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock\r
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the I2C1 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock\r
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock\r
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock\r
-  */\r
-#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))\r
-\r
-#if defined(I2C2)\r
-\r
-/** @brief  Macro to configure the I2C2 clock (I2C2CLK).\r
-  *\r
-  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock\r
-  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock\r
-  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the I2C2 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock\r
-  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock\r
-  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock\r
-  */\r
-#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))\r
-\r
-#endif /* I2C2 */\r
-\r
-/** @brief  Macro to configure the I2C3 clock (I2C3CLK).\r
-  *\r
-  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock\r
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock\r
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the I2C3 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock\r
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock\r
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock\r
-  */\r
-#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))\r
-\r
-#if defined(I2C4)\r
-\r
-/** @brief  Macro to configure the I2C4 clock (I2C4CLK).\r
-  *\r
-  * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock\r
-  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock\r
-  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the I2C4 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock\r
-  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock\r
-  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock\r
-  */\r
-#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))\r
-\r
-#endif /* I2C4 */\r
-\r
-\r
-/** @brief  Macro to configure the USART1 clock (USART1CLK).\r
-  *\r
-  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock\r
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock\r
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock\r
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE  SE selected as USART1 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the USART1 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock\r
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock\r
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock\r
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock\r
-  */\r
-#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))\r
-\r
-/** @brief  Macro to configure the USART2 clock (USART2CLK).\r
-  *\r
-  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock\r
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock\r
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock\r
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the USART2 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock\r
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock\r
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock\r
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock\r
-  */\r
-#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))\r
-\r
-#if defined(USART3)\r
-\r
-/** @brief  Macro to configure the USART3 clock (USART3CLK).\r
-  *\r
-  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock\r
-  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock\r
-  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock\r
-  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the USART3 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock\r
-  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock\r
-  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock\r
-  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock\r
-  */\r
-#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))\r
-\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-\r
-/** @brief  Macro to configure the UART4 clock (UART4CLK).\r
-  *\r
-  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock\r
-  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock\r
-  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock\r
-  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the UART4 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock\r
-  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock\r
-  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock\r
-  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock\r
-  */\r
-#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))\r
-\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-\r
-/** @brief  Macro to configure the UART5 clock (UART5CLK).\r
-  *\r
-  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock\r
-  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock\r
-  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock\r
-  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the UART5 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock\r
-  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock\r
-  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock\r
-  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock\r
-  */\r
-#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))\r
-\r
-#endif /* UART5 */\r
-\r
-/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).\r
-  *\r
-  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the LPUART1 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
-  */\r
-#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))\r
-\r
-/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).\r
-  *\r
-  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the LPTIM1 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
-  */\r
-#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))\r
-\r
-/** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).\r
-  *\r
-  * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPTIM2 clock\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPTIM2 clock\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  LSI selected as LPTIM2 clock\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPTIM2 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the LPTIM2 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  System Clock selected as LPUART1 clock\r
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPUART1 clock\r
-  */\r
-#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))\r
-\r
-#if defined(SDMMC1)\r
-\r
-/** @brief  Macro to configure the SDMMC1 clock.\r
-  *\r
-  @if STM32L486xx\r
-  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
-  @endif\r
-  *\r
-  @if STM32L443xx\r
-  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
-  @endif\r
-  *\r
-  * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.\r
-  *         This parameter can be one of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" Clock selected as SDMMC1 clock\r
-  @endif\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" Clock selected as SDMMC1 clock\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" Clock selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLP  PLL "P" Clock selected as SDMMC1 clock\r
-  @endif\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" Clock selected as SDMMC1 clock\r
-  * @retval None\r
-  */\r
-#if defined(RCC_CCIPR2_SDMMCSEL)\r
-#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\r
-                  do \\r
-                  {  \\r
-                    if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \\r
-                    { \\r
-                      SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \\r
-                    } \\r
-                    else \\r
-                    { \\r
-                      CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \\r
-                      MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \\r
-                    } \\r
-                  } while(0)\r
-#else\r
-#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))\r
-#endif /* RCC_CCIPR2_SDMMCSEL */\r
-\r
-/** @brief  Macro to get the SDMMC1 clock.\r
-  * @retval The clock source can be one of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock\r
-  @endif\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLP  PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock\r
-  @endif\r
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock\r
-  */\r
-#if defined(RCC_CCIPR2_SDMMCSEL)\r
-#define __HAL_RCC_GET_SDMMC1_SOURCE() \\r
-                  ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))\r
-#else\r
-#define __HAL_RCC_GET_SDMMC1_SOURCE() \\r
-                  (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))\r
-#endif /* RCC_CCIPR2_SDMMCSEL */\r
-\r
-#endif /* SDMMC1 */\r
-\r
-/** @brief  Macro to configure the RNG clock.\r
-  *\r
-  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
-  *\r
-  * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.\r
-  *         This parameter can be one of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48\r
-  @endif\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48\r
-  @endif\r
-  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock\r
-  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as RNG clock\r
-  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the RNG clock.\r
-  * @retval The clock source can be one of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48\r
-  @endif\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48\r
-  @endif\r
-  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock\r
-  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock\r
-  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as RNG clock\r
-  */\r
-#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))\r
-\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-\r
-/** @brief  Macro to configure the USB clock (USBCLK).\r
-  *\r
-  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.\r
-  *\r
-  * @param  __USB_CLKSOURCE__ specifies the USB clock source.\r
-  *         This parameter can be one of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48\r
-  @endif\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48\r
-  @endif\r
-  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock\r
-  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock\r
-  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the USB clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48\r
-  @endif\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48\r
-  @endif\r
-  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock\r
-  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock\r
-  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock\r
-  */\r
-#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))\r
-\r
-#endif /* USB_OTG_FS || USB */\r
-\r
-#if defined(RCC_CCIPR_ADCSEL)\r
-\r
-/** @brief  Macro to configure the ADC interface clock.\r
-  * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock\r
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices\r
-  @endif\r
-  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the ADC clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock\r
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices\r
-  @endif\r
-  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock\r
-  */\r
-#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))\r
-#else\r
-\r
-/** @brief  Macro to get the ADC clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock\r
-  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock\r
-  */\r
-#define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE)\r
-\r
-#endif /* RCC_CCIPR_ADCSEL */\r
-\r
-#if defined(SWPMI1)\r
-\r
-/** @brief  Macro to configure the SWPMI1 clock.\r
-  * @param  __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1  PCLK1 Clock selected as SWPMI1 clock\r
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the SWPMI1 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1  PCLK1 Clock selected as SWPMI1 clock\r
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock\r
-  */\r
-#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))\r
-\r
-#endif /* SWPMI1 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-/** @brief  Macro to configure the DFSDM1 clock.\r
-  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2  PCLK2 Clock selected as DFSDM1 clock\r
-  *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock\r
-  * @retval None\r
-  */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))\r
-#else\r
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/** @brief  Macro to get the DFSDM1 clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2  PCLK2 Clock selected as DFSDM1 clock\r
-  *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock\r
-  */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))\r
-#else\r
-#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-\r
-/** @brief  Macro to configure the DFSDM1 audio clock.\r
-  * @param  __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1  SAI1 clock selected as DFSDM1 audio clock\r
-  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI   HSI clock selected as DFSDM1 audio clock\r
-  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI   MSI clock selected as DFSDM1 audio clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the DFSDM1 audio clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1  SAI1 clock selected as DFSDM1 audio clock\r
-  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI   HSI clock selected as DFSDM1 audio clock\r
-  *            @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI   MSI clock selected as DFSDM1 audio clock\r
-  */\r
-#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-\r
-/** @brief  Macro to configure the LTDC clock.\r
-  * @param  __LTDC_CLKSOURCE__ specifies the DSI clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2   PLLSAI2 divider R divided by 2 clock selected as LTDC clock\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4   PLLSAI2 divider R divided by 4 clock selected as LTDC clock\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8   PLLSAI2 divider R divided by 8 clock selected as LTDC clock\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16  PLLSAI2 divider R divided by 16 clock selected as LTDC clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the LTDC clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2   PLLSAI2 divider R divided by 2 clock selected as LTDC clock\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4   PLLSAI2 divider R divided by 4 clock selected as LTDC clock\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8   PLLSAI2 divider R divided by 8 clock selected as LTDC clock\r
-  *            @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16  PLLSAI2 divider R divided by 16 clock selected as LTDC clock\r
-  */\r
-#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))\r
-\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-\r
-/** @brief  Macro to configure the DSI clock.\r
-  * @param  __DSI_CLKSOURCE__ specifies the DSI clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_DSICLKSOURCE_DSIPHY  DSI-PHY clock selected as DSI clock\r
-  *            @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the DSI clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_DSICLKSOURCE_DSIPHY  DSI-PHY clock selected as DSI clock\r
-  *            @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock\r
-  */\r
-#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))\r
-\r
-#endif /* DSI */\r
-\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-\r
-/** @brief  Macro to configure the OctoSPI clock.\r
-  * @param  __OSPI_CLKSOURCE__ specifies the OctoSPI clock source.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_OSPICLKSOURCE_SYSCLK  System Clock selected as OctoSPI clock\r
-  *            @arg @ref RCC_OSPICLKSOURCE_MSI     MSI clock selected as OctoSPI clock\r
-  *            @arg @ref RCC_OSPICLKSOURCE_PLL     PLL Q divider clock selected as OctoSPI clock\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \\r
-                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__))\r
-\r
-/** @brief  Macro to get the OctoSPI clock source.\r
-  * @retval The clock source can be one of the following values:\r
-  *            @arg @ref RCC_OSPICLKSOURCE_SYSCLK  System Clock selected as OctoSPI clock\r
-  *            @arg @ref RCC_OSPICLKSOURCE_MSI     MSI clock selected as OctoSPI clock\r
-  *            @arg @ref RCC_OSPICLKSOURCE_PLL     PLL Q divider clock selected as OctoSPI clock\r
-  */\r
-#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))\r
-\r
-#endif /* OCTOSPI1 || OCTOSPI2 */\r
-\r
-/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management\r
-  * @brief macros to manage the specified RCC Flags and interrupts.\r
-  * @{\r
-  */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-/** @brief Enable PLLSAI1RDY interrupt.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI1_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)\r
-\r
-/** @brief Disable PLLSAI1RDY interrupt.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)\r
-\r
-/** @brief Clear the PLLSAI1RDY interrupt pending bit.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI1_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)\r
-\r
-/** @brief Check whether PLLSAI1RDY interrupt has occurred or not.\r
-  * @retval TRUE or FALSE.\r
-  */\r
-#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)\r
-\r
-/** @brief  Check whether the PLLSAI1RDY flag is set or not.\r
-  * @retval TRUE or FALSE.\r
-  */\r
-#define __HAL_RCC_PLLSAI1_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-/** @brief Enable PLLSAI2RDY interrupt.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI2_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)\r
-\r
-/** @brief Disable PLLSAI2RDY interrupt.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)\r
-\r
-/** @brief Clear the PLLSAI2RDY interrupt pending bit.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_PLLSAI2_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)\r
-\r
-/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.\r
-  * @retval TRUE or FALSE.\r
-  */\r
-#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)\r
-\r
-/** @brief  Check whether the PLLSAI2RDY flag is set or not.\r
-  * @retval TRUE or FALSE.\r
-  */\r
-#define __HAL_RCC_PLLSAI2_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-\r
-/**\r
-  * @brief Enable the RCC LSE CSS Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-/**\r
-  * @brief Disable the RCC LSE CSS Extended Interrupt Line.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-/**\r
-  * @brief Enable the RCC LSE CSS Event Line.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-/**\r
-  * @brief Disable the RCC LSE CSS Event Line.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-\r
-/**\r
-  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-\r
-/**\r
-  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-\r
-/**\r
-  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-/**\r
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-/**\r
-  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                      \\r
-    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \\r
-    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \\r
-  do {                                                       \\r
-    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \\r
-    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.\r
-  * @retval EXTI RCC LSE CSS Line Status.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)\r
-\r
-/**\r
-  * @brief Clear the RCC LSE CSS EXTI flag.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)\r
-\r
-/**\r
-  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.\r
-  * @retval None.\r
-  */\r
-#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)\r
-\r
-\r
-#if defined(CRS)\r
-\r
-/**\r
-  * @brief  Enable the specified CRS interrupts.\r
-  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.\r
-  *          This parameter can be any combination of the following values:\r
-  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
-  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
-  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
-  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))\r
-\r
-/**\r
-  * @brief  Disable the specified CRS interrupts.\r
-  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.\r
-  *          This parameter can be any combination of the following values:\r
-  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
-  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
-  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
-  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))\r
-\r
-/** @brief  Check whether the CRS interrupt has occurred or not.\r
-  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.\r
-  *         This parameter can be one of the following values:\r
-  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
-  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
-  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
-  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
-  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
-  */\r
-#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)\r
-\r
-/** @brief  Clear the CRS interrupt pending bits\r
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\r
-  *         This parameter can be any combination of the following values:\r
-  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt\r
-  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt\r
-  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt\r
-  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt\r
-  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt\r
-  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt\r
-  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt\r
-  */\r
-/* CRS IT Error Mask */\r
-#define  RCC_CRS_IT_ERROR_MASK                 (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)\r
-\r
-#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \\r
-                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \\r
-                                                 { \\r
-                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \\r
-                                                 } \\r
-                                                 else \\r
-                                                 { \\r
-                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \\r
-                                                 } \\r
-                                               } while(0)\r
-\r
-/**\r
-  * @brief  Check whether the specified CRS flag is set or not.\r
-  * @param  __FLAG__ specifies the flag to check.\r
-  *          This parameter can be one of the following values:\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning\r
-  *              @arg @ref RCC_CRS_FLAG_ERR  Error\r
-  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC\r
-  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed\r
-  * @retval The new state of _FLAG_ (TRUE or FALSE).\r
-  */\r
-#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))\r
-\r
-/**\r
-  * @brief  Clear the CRS specified FLAG.\r
-  * @param __FLAG__ specifies the flag to clear.\r
-  *          This parameter can be one of the following values:\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning\r
-  *              @arg @ref RCC_CRS_FLAG_ERR  Error\r
-  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC\r
-  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error\r
-  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed\r
-  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR\r
-  * @retval None\r
-  */\r
-\r
-/* CRS Flag Error Mask */\r
-#define RCC_CRS_FLAG_ERROR_MASK                (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)\r
-\r
-#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \\r
-                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \\r
-                                                 { \\r
-                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \\r
-                                                 } \\r
-                                                 else \\r
-                                                 { \\r
-                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \\r
-                                                 } \\r
-                                               } while(0)\r
-\r
-#endif /* CRS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(CRS)\r
-\r
-/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Enable the oscillator clock for frequency error counter.\r
-  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)\r
-\r
-/**\r
-  * @brief  Disable the oscillator clock for frequency error counter.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)\r
-\r
-/**\r
-  * @brief  Enable the automatic hardware adjustement of TRIM bits.\r
-  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)\r
-\r
-/**\r
-  * @brief  Enable or disable the automatic hardware adjustement of TRIM bits.\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)\r
-\r
-/**\r
-  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies\r
-  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency\r
-  *             of the synchronization source after prescaling. It is then decreased by one in order to\r
-  *             reach the expected synchronization on the zero value. The formula is the following:\r
-  *             RELOAD = (fTARGET / fSYNC) -1\r
-  * @param  __FTARGET__ Target frequency (value in Hz)\r
-  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)\r
-  * @retval None\r
-  */\r
-#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* CRS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup RCCEx_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup RCCEx_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-\r
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r
-void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r
-uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup RCCEx_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init);\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init);\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);\r
-void              HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);\r
-void              HAL_RCCEx_EnableLSECSS(void);\r
-void              HAL_RCCEx_DisableLSECSS(void);\r
-void              HAL_RCCEx_EnableLSECSS_IT(void);\r
-void              HAL_RCCEx_LSECSS_IRQHandler(void);\r
-void              HAL_RCCEx_LSECSS_Callback(void);\r
-void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);\r
-void              HAL_RCCEx_DisableLSCO(void);\r
-void              HAL_RCCEx_EnableMSIPLLMode(void);\r
-void              HAL_RCCEx_DisableMSIPLLMode(void);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(CRS)\r
-\r
-/** @addtogroup RCCEx_Exported_Functions_Group3\r
-  * @{\r
-  */\r
-\r
-void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);\r
-void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);\r
-void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);\r
-uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);\r
-void              HAL_RCCEx_CRS_IRQHandler(void);\r
-void              HAL_RCCEx_CRS_SyncOkCallback(void);\r
-void              HAL_RCCEx_CRS_SyncWarnCallback(void);\r
-void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);\r
-void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* CRS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @addtogroup RCCEx_Private_Macros\r
-  * @{\r
-  */\r
-\r
-#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \\r
-                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))\r
-\r
-#if defined(STM32L412xx) || defined(STM32L422xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG))\r
-\r
-#elif defined(STM32L431xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
-\r
-#elif defined(STM32L432xx) || defined(STM32L442xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG))\r
-\r
-#elif defined(STM32L433xx) || defined(STM32L443xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
-\r
-#elif defined(STM32L451xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
-\r
-#elif defined(STM32L452xx) || defined(STM32L462xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
-\r
-#elif defined(STM32L471xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
-\r
-#elif defined(STM32L496xx) || defined(STM32L4A6xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
-\r
-#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)      == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)         == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)      == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_OSPI)        == RCC_PERIPHCLK_OSPI))\r
-\r
-#elif defined(STM32L4R7xx) || defined(STM32L4S7xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)      == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)         == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)      == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_OSPI)        == RCC_PERIPHCLK_OSPI) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC))\r
-\r
-#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)      == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)         == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)      == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_OSPI)        == RCC_PERIPHCLK_OSPI)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DSI)         == RCC_PERIPHCLK_DSI))\r
-\r
-#else\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \\r
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \\r
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))\r
-\r
-#endif /* STM32L412xx || STM32L422xx */\r
-\r
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \\r
-                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \\r
-                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \\r
-                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))\r
-\r
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \\r
-                ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \\r
-                ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \\r
-                ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))\r
-\r
-#if defined(USART3)\r
-\r
-#define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \\r
-                ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \\r
-                ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \\r
-                ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))\r
-\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-\r
-#define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \\r
-                ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \\r
-                ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \\r
-                ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))\r
-\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-\r
-#define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \\r
-                ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \\r
-                ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \\r
-                ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))\r
-\r
-#endif /* UART5 */\r
-\r
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \\r
-                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \\r
-                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \\r
-                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))\r
-\r
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \\r
-                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \\r
-                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))\r
-\r
-#if defined(I2C2)\r
-\r
-#define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \\r
-                ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \\r
-                ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))\r
-\r
-#endif /* I2C2 */\r
-\r
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \\r
-                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \\r
-                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))\r
-\r
-#if defined(I2C4)\r
-\r
-#define IS_RCC_I2C4CLKSOURCE(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \\r
-                ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \\r
-                ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))\r
-\r
-#endif /* I2C4 */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define IS_RCC_SAI1CLK(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)     || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))\r
-#else\r
-#define IS_RCC_SAI1CLK(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-#define IS_RCC_SAI1CLK(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define IS_RCC_SAI2CLK(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \\r
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)     || \\r
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))\r
-#else\r
-#define IS_RCC_SAI2CLK(__SOURCE__)   \\r
-               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \\r
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#define IS_RCC_LPTIM1CLK(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \\r
-                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)   || \\r
-                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)   || \\r
-                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))\r
-\r
-#define IS_RCC_LPTIM2CLK(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \\r
-                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)   || \\r
-                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)   || \\r
-                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))\r
-\r
-#if defined(SDMMC1)\r
-#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL)\r
-\r
-#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP)    || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48)   || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))\r
-\r
-#elif defined(RCC_HSI48_SUPPORT)\r
-\r
-#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48)   || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))\r
-#else\r
-\r
-#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE)    || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))\r
-\r
-#endif /* RCC_HSI48_SUPPORT */\r
-#endif /* SDMMC1 */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))\r
-#else\r
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#else\r
-\r
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)    || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))\r
-\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-#if defined(RCC_HSI48_SUPPORT)\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))\r
-#else\r
-#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#else\r
-\r
-#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_USBCLKSOURCE_NONE)    || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \\r
-                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))\r
-\r
-#endif /* RCC_HSI48_SUPPORT */\r
-#endif /* USB_OTG_FS || USB */\r
-\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-\r
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \\r
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \\r
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))\r
-\r
-#else\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \\r
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \\r
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))\r
-#else\r
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \\r
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-\r
-#if defined(SWPMI1)\r
-\r
-#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \\r
-                ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))\r
-\r
-#endif /* SWPMI1 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-\r
-#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \\r
-                ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-\r
-#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \\r
-                ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \\r
-                ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI))\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-\r
-#define IS_RCC_LTDCCLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \\r
-                ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \\r
-                ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \\r
-                ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16))\r
-\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-\r
-#define IS_RCC_DSICLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \\r
-                ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2))\r
-\r
-#endif /* DSI */\r
-\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-\r
-#define IS_RCC_OSPICLKSOURCE(__SOURCE__)  \\r
-               (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \\r
-                ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \\r
-                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL))\r
-\r
-#endif /* OCTOSPI1 || OCTOSPI2 */\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-#define IS_RCC_PLLSAI1SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)\r
-\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-#define IS_RCC_PLLSAI1M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))\r
-#else\r
-#define IS_RCC_PLLSAI1M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-\r
-#define IS_RCC_PLLSAI1N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))\r
-\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-#define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))\r
-#else\r
-#define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))\r
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
-\r
-#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
-                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-\r
-#define IS_RCC_PLLSAI1R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
-                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-#define IS_RCC_PLLSAI2SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)\r
-\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-#define IS_RCC_PLLSAI2M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))\r
-#else\r
-#define IS_RCC_PLLSAI2M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
-\r
-#define IS_RCC_PLLSAI2N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))\r
-\r
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
-#define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))\r
-#else\r
-#define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))\r
-#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
-                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
-\r
-#define IS_RCC_PLLSAI2R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
-                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#if defined(CRS)\r
-\r
-#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \\r
-                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \\r
-                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))\r
-\r
-#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \\r
-                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \\r
-                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \\r
-                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))\r
-\r
-#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \\r
-                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))\r
-\r
-#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))\r
-\r
-#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))\r
-\r
-#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))\r
-\r
-#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \\r
-                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))\r
-\r
-#endif /* CRS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_RCC_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h
deleted file mode 100644 (file)
index cd35f17..0000000
+++ /dev/null
@@ -1,846 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_spi.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of SPI HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_SPI_H\r
-#define STM32L4xx_HAL_SPI_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup SPI\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup SPI_Exported_Types SPI Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  SPI Configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Mode;                /*!< Specifies the SPI operating mode.\r
-                                     This parameter can be a value of @ref SPI_Mode */\r
-\r
-  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.\r
-                                     This parameter can be a value of @ref SPI_Direction */\r
-\r
-  uint32_t DataSize;            /*!< Specifies the SPI data size.\r
-                                     This parameter can be a value of @ref SPI_Data_Size */\r
-\r
-  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.\r
-                                     This parameter can be a value of @ref SPI_Clock_Polarity */\r
-\r
-  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.\r
-                                     This parameter can be a value of @ref SPI_Clock_Phase */\r
-\r
-  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by\r
-                                     hardware (NSS pin) or by software using the SSI bit.\r
-                                     This parameter can be a value of @ref SPI_Slave_Select_management */\r
-\r
-  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be\r
-                                     used to configure the transmit and receive SCK clock.\r
-                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
-                                     @note The communication clock is derived from the master\r
-                                     clock. The slave clock does not need to be set. */\r
-\r
-  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.\r
-                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
-\r
-  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.\r
-                                     This parameter can be a value of @ref SPI_TI_mode */\r
-\r
-  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.\r
-                                     This parameter can be a value of @ref SPI_CRC_Calculation */\r
-\r
-  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.\r
-                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */\r
-\r
-  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.\r
-                                     CRC Length is only used with Data8 and Data16, not other data size\r
-                                     This parameter can be a value of @ref SPI_CRC_length */\r
-\r
-  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .\r
-                                     This parameter can be a value of @ref SPI_NSSP_Mode\r
-                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and\r
-                                     it takes effect only if the SPI interface is configured as Motorola SPI\r
-                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,\r
-                                     CPOL setting is ignored).. */\r
-} SPI_InitTypeDef;\r
-\r
-/**\r
-  * @brief  HAL SPI State structure definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */\r
-  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */\r
-  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */\r
-  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */\r
-  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */\r
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */\r
-  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */\r
-  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */\r
-} HAL_SPI_StateTypeDef;\r
-\r
-/**\r
-  * @brief  SPI handle Structure definition\r
-  */\r
-typedef struct __SPI_HandleTypeDef\r
-{\r
-  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */\r
-\r
-  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */\r
-\r
-  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */\r
-\r
-  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */\r
-\r
-  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */\r
-\r
-  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */\r
-\r
-  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */\r
-\r
-  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */\r
-\r
-  uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */\r
-\r
-  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */\r
-\r
-  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */\r
-\r
-  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */\r
-\r
-  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */\r
-\r
-  HAL_LockTypeDef            Lock;           /*!< Locking object                           */\r
-\r
-  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */\r
-\r
-  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */\r
-  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */\r
-  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */\r
-  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */\r
-  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */\r
-  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */\r
-  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */\r
-  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */\r
-  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */\r
-  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */\r
-\r
-#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-} SPI_HandleTypeDef;\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-/**\r
-  * @brief  HAL SPI Callback ID enumeration definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */\r
-  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */\r
-  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */\r
-  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */\r
-  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */\r
-  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */\r
-  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */\r
-  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */\r
-  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */\r
-  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */\r
-\r
-} HAL_SPI_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  HAL SPI Callback pointer definition\r
-  */\r
-typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */\r
-\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup SPI_Exported_Constants SPI Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup SPI_Error_Code SPI Error Code\r
-  * @{\r
-  */\r
-#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */\r
-#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */\r
-#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */\r
-#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */\r
-#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */\r
-#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */\r
-#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */\r
-#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Mode SPI Mode\r
-  * @{\r
-  */\r
-#define SPI_MODE_SLAVE                  (0x00000000U)\r
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Direction SPI Direction Mode\r
-  * @{\r
-  */\r
-#define SPI_DIRECTION_2LINES            (0x00000000U)\r
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY\r
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Data_Size SPI Data Size\r
-  * @{\r
-  */\r
-#define SPI_DATASIZE_4BIT               (0x00000300U)\r
-#define SPI_DATASIZE_5BIT               (0x00000400U)\r
-#define SPI_DATASIZE_6BIT               (0x00000500U)\r
-#define SPI_DATASIZE_7BIT               (0x00000600U)\r
-#define SPI_DATASIZE_8BIT               (0x00000700U)\r
-#define SPI_DATASIZE_9BIT               (0x00000800U)\r
-#define SPI_DATASIZE_10BIT              (0x00000900U)\r
-#define SPI_DATASIZE_11BIT              (0x00000A00U)\r
-#define SPI_DATASIZE_12BIT              (0x00000B00U)\r
-#define SPI_DATASIZE_13BIT              (0x00000C00U)\r
-#define SPI_DATASIZE_14BIT              (0x00000D00U)\r
-#define SPI_DATASIZE_15BIT              (0x00000E00U)\r
-#define SPI_DATASIZE_16BIT              (0x00000F00U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\r
-  * @{\r
-  */\r
-#define SPI_POLARITY_LOW                (0x00000000U)\r
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Clock_Phase SPI Clock Phase\r
-  * @{\r
-  */\r
-#define SPI_PHASE_1EDGE                 (0x00000000U)\r
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management\r
-  * @{\r
-  */\r
-#define SPI_NSS_SOFT                    SPI_CR1_SSM\r
-#define SPI_NSS_HARD_INPUT              (0x00000000U)\r
-#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode\r
-  * @{\r
-  */\r
-#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP\r
-#define SPI_NSS_PULSE_DISABLE           (0x00000000U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\r
-  * @{\r
-  */\r
-#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)\r
-#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)\r
-#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)\r
-#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)\r
-#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)\r
-#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)\r
-#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)\r
-#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission\r
-  * @{\r
-  */\r
-#define SPI_FIRSTBIT_MSB                (0x00000000U)\r
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_TI_mode SPI TI Mode\r
-  * @{\r
-  */\r
-#define SPI_TIMODE_DISABLE              (0x00000000U)\r
-#define SPI_TIMODE_ENABLE               SPI_CR2_FRF\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\r
-  * @{\r
-  */\r
-#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)\r
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_CRC_length SPI CRC Length\r
-  * @{\r
-  * This parameter can be one of the following values:\r
-  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size\r
-  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit\r
-  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit\r
-  */\r
-#define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)\r
-#define SPI_CRC_LENGTH_8BIT             (0x00000001U)\r
-#define SPI_CRC_LENGTH_16BIT            (0x00000002U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold\r
-  * @{\r
-  * This parameter can be one of the following values:\r
-  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :\r
-  *          RXNE event is generated if the FIFO\r
-  *          level is greater or equal to 1/4(8-bits).\r
-  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO\r
-  *          level is greater or equal to 1/2(16 bits). */\r
-#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH\r
-#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH\r
-#define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition\r
-  * @{\r
-  */\r
-#define SPI_IT_TXE                      SPI_CR2_TXEIE\r
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE\r
-#define SPI_IT_ERR                      SPI_CR2_ERRIE\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Flags_definition SPI Flags Definition\r
-  * @{\r
-  */\r
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */\r
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */\r
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */\r
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */\r
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */\r
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */\r
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */\r
-#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */\r
-#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */\r
-#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level\r
-  * @{\r
-  */\r
-#define SPI_FTLVL_EMPTY                 (0x00000000U)\r
-#define SPI_FTLVL_QUARTER_FULL          (0x00000800U)\r
-#define SPI_FTLVL_HALF_FULL             (0x00001000U)\r
-#define SPI_FTLVL_FULL                  (0x00001800U)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level\r
-  * @{\r
-  */\r
-#define SPI_FRLVL_EMPTY                 (0x00000000U)\r
-#define SPI_FRLVL_QUARTER_FULL          (0x00000200U)\r
-#define SPI_FRLVL_HALF_FULL             (0x00000400U)\r
-#define SPI_FRLVL_FULL                  (0x00000600U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup SPI_Exported_Macros SPI Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Reset SPI handle state.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \\r
-                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \\r
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \\r
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \\r
-                                                                  } while(0)\r
-#else\r
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\r
-#endif\r
-\r
-/** @brief  Enable the specified SPI interrupts.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
-  *            @arg SPI_IT_ERR: Error interrupt enable\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))\r
-\r
-/** @brief  Disable the specified SPI interrupts.\r
-  * @param  __HANDLE__ specifies the SPI handle.\r
-  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
-  *            @arg SPI_IT_ERR: Error interrupt enable\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))\r
-\r
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
-  *            @arg SPI_IT_ERR: Error interrupt enable\r
-  * @retval The new state of __IT__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
-\r
-/** @brief  Check whether the specified SPI flag is set or not.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @param  __FLAG__ specifies the flag to check.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\r
-  *            @arg SPI_FLAG_CRCERR: CRC error flag\r
-  *            @arg SPI_FLAG_MODF: Mode fault flag\r
-  *            @arg SPI_FLAG_OVR: Overrun flag\r
-  *            @arg SPI_FLAG_BSY: Busy flag\r
-  *            @arg SPI_FLAG_FRE: Frame format error flag\r
-  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r
-  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level\r
-  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
-\r
-/** @brief  Clear the SPI CRCERR pending flag.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\r
-\r
-/** @brief  Clear the SPI MODF pending flag.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \\r
-  do{                                                    \\r
-    __IO uint32_t tmpreg_modf = 0x00U;                   \\r
-    tmpreg_modf = (__HANDLE__)->Instance->SR;            \\r
-    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \\r
-    UNUSED(tmpreg_modf);                                 \\r
-  } while(0U)\r
-\r
-/** @brief  Clear the SPI OVR pending flag.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \\r
-  do{                                              \\r
-    __IO uint32_t tmpreg_ovr = 0x00U;              \\r
-    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \\r
-    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \\r
-    UNUSED(tmpreg_ovr);                            \\r
-  } while(0U)\r
-\r
-/** @brief  Clear the SPI FRE pending flag.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \\r
-  do{                                              \\r
-  __IO uint32_t tmpreg_fre = 0x00U;                \\r
-  tmpreg_fre = (__HANDLE__)->Instance->SR;         \\r
-  UNUSED(tmpreg_fre);                              \\r
-  }while(0U)\r
-\r
-/** @brief  Enable the SPI peripheral.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)\r
-\r
-/** @brief  Disable the SPI peripheral.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup SPI_Private_Macros SPI Private Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Set the SPI transmit-only mode.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)\r
-\r
-/** @brief  Set the SPI receive-only mode.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)\r
-\r
-/** @brief  Reset the CRC calculation of the SPI.\r
-  * @param  __HANDLE__ specifies the SPI Handle.\r
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
-  * @retval None\r
-  */\r
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\\r
-                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)\r
-\r
-/** @brief  Check whether the specified SPI flag is set or not.\r
-  * @param  __SR__  copy of SPI SR regsiter.\r
-  * @param  __FLAG__ specifies the flag to check.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\r
-  *            @arg SPI_FLAG_CRCERR: CRC error flag\r
-  *            @arg SPI_FLAG_MODF: Mode fault flag\r
-  *            @arg SPI_FLAG_OVR: Overrun flag\r
-  *            @arg SPI_FLAG_BSY: Busy flag\r
-  *            @arg SPI_FLAG_FRE: Frame format error flag\r
-  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r
-  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level\r
-  * @retval SET or RESET.\r
-  */\r
-#define SPI_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)\r
-\r
-/** @brief  Check whether the specified SPI Interrupt is set or not.\r
-  * @param  __CR2__  copy of SPI CR2 regsiter.\r
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
-  *            @arg SPI_IT_ERR: Error interrupt enable\r
-  * @retval SET or RESET.\r
-  */\r
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
-\r
-/** @brief  Checks if SPI Mode parameter is in allowed range.\r
-  * @param  __MODE__ specifies the SPI Mode.\r
-  *         This parameter can be a value of @ref SPI_Mode\r
-  * @retval None\r
-  */\r
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \\r
-                               ((__MODE__) == SPI_MODE_MASTER))\r
-\r
-/** @brief  Checks if SPI Direction Mode parameter is in allowed range.\r
-  * @param  __MODE__ specifies the SPI Direction Mode.\r
-  *         This parameter can be a value of @ref SPI_Direction\r
-  * @retval None\r
-  */\r
-#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \\r
-                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \\r
-                                    ((__MODE__) == SPI_DIRECTION_1LINE))\r
-\r
-/** @brief  Checks if SPI Direction Mode parameter is 2 lines.\r
-  * @param  __MODE__ specifies the SPI Direction Mode.\r
-  * @retval None\r
-  */\r
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)\r
-\r
-/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.\r
-  * @param  __MODE__ specifies the SPI Direction Mode.\r
-  * @retval None\r
-  */\r
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \\r
-                                                    ((__MODE__) == SPI_DIRECTION_1LINE))\r
-\r
-/** @brief  Checks if SPI Data Size parameter is in allowed range.\r
-  * @param  __DATASIZE__ specifies the SPI Data Size.\r
-  *         This parameter can be a value of @ref SPI_Data_Size\r
-  * @retval None\r
-  */\r
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \\r
-                                       ((__DATASIZE__) == SPI_DATASIZE_4BIT))\r
-\r
-/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.\r
-  * @param  __CPOL__ specifies the SPI serial clock steady state.\r
-  *         This parameter can be a value of @ref SPI_Clock_Polarity\r
-  * @retval None\r
-  */\r
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \\r
-                               ((__CPOL__) == SPI_POLARITY_HIGH))\r
-\r
-/** @brief  Checks if SPI Clock Phase parameter is in allowed range.\r
-  * @param  __CPHA__ specifies the SPI Clock Phase.\r
-  *         This parameter can be a value of @ref SPI_Clock_Phase\r
-  * @retval None\r
-  */\r
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \\r
-                               ((__CPHA__) == SPI_PHASE_2EDGE))\r
-\r
-/** @brief  Checks if SPI Slave Select parameter is in allowed range.\r
-  * @param  __NSS__ specifies the SPI Slave Select management parameter.\r
-  *         This parameter can be a value of @ref SPI_Slave_Select_management\r
-  * @retval None\r
-  */\r
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT)       || \\r
-                             ((__NSS__) == SPI_NSS_HARD_INPUT) || \\r
-                             ((__NSS__) == SPI_NSS_HARD_OUTPUT))\r
-\r
-/** @brief  Checks if SPI NSS Pulse parameter is in allowed range.\r
-  * @param  __NSSP__ specifies the SPI NSS Pulse Mode parameter.\r
-  *         This parameter can be a value of @ref SPI_NSSP_Mode\r
-  * @retval None\r
-  */\r
-#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \\r
-                               ((__NSSP__) == SPI_NSS_PULSE_DISABLE))\r
-\r
-/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.\r
-  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.\r
-  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
-  * @retval None\r
-  */\r
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \\r
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \\r
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \\r
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \\r
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \\r
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \\r
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \\r
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))\r
-\r
-/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.\r
-  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).\r
-  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission\r
-  * @retval None\r
-  */\r
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \\r
-                                   ((__BIT__) == SPI_FIRSTBIT_LSB))\r
-\r
-/** @brief  Checks if SPI TI mode parameter is in allowed range.\r
-  * @param  __MODE__ specifies the SPI TI mode.\r
-  *         This parameter can be a value of @ref SPI_TI_mode\r
-  * @retval None\r
-  */\r
-#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \\r
-                                 ((__MODE__) == SPI_TIMODE_ENABLE))\r
-\r
-/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.\r
-  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.\r
-  *         This parameter can be a value of @ref SPI_CRC_Calculation\r
-  * @retval None\r
-  */\r
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \\r
-                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))\r
-\r
-/** @brief  Checks if SPI CRC length is in allowed range.\r
-  * @param  __LENGTH__ specifies the SPI CRC length.\r
-  *         This parameter can be a value of @ref SPI_CRC_length\r
-  * @retval None\r
-  */\r
-#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\\r
-                                       ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)  ||   \\r
-                                       ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))\r
-\r
-/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.\r
-  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.\r
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535\r
-  * @retval None\r
-  */\r
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))\r
-\r
-/** @brief  Checks if DMA handle is valid.\r
-  * @param  __HANDLE__ specifies a DMA Handle.\r
-  * @retval None\r
-  */\r
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include SPI HAL Extended module */\r
-#include "stm32l4xx_hal_spi_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup SPI_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup SPI_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-/* Initialization/de-initialization functions  ********************************/\r
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\r
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\r
-\r
-/* Callbacks Register/UnRegister functions  ***********************************/\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup SPI_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-/* I/O operation functions  ***************************************************/\r
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\r
-                                          uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r
-                                             uint16_t Size);\r
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r
-                                              uint16_t Size);\r
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\r
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\r
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\r
-/* Transfer Abort functions */\r
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);\r
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);\r
-\r
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\r
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup SPI_Exported_Functions_Group3\r
-  * @{\r
-  */\r
-/* Peripheral State and Error functions ***************************************/\r
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\r
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_SPI_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h
deleted file mode 100644 (file)
index c7f6edb..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_spi_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of SPI HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_SPI_EX_H\r
-#define STM32L4xx_HAL_SPI_EX_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup SPIEx\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-/* Exported macros -----------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup SPIEx_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/* Initialization and de-initialization functions  ****************************/\r
-/* IO operation functions *****************************************************/\r
-/** @addtogroup SPIEx_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_SPI_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
deleted file mode 100644 (file)
index 42cb4ea..0000000
+++ /dev/null
@@ -1,2141 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_tim.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of TIM HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_TIM_H\r
-#define STM32L4xx_HAL_TIM_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup TIM\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup TIM_Exported_Types TIM Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  TIM Time base Configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.\r
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-\r
-  uint32_t CounterMode;       /*!< Specifies the counter mode.\r
-                                   This parameter can be a value of @ref TIM_Counter_Mode */\r
-\r
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active\r
-                                   Auto-Reload Register at the next update event.\r
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */\r
-\r
-  uint32_t ClockDivision;     /*!< Specifies the clock division.\r
-                                   This parameter can be a value of @ref TIM_ClockDivision */\r
-\r
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
-                                    reaches zero, an update event is generated and counting restarts\r
-                                    from the RCR value (N).\r
-                                    This means in PWM mode that (N+1) corresponds to:\r
-                                        - the number of PWM periods in edge-aligned mode\r
-                                        - the number of half PWM period in center-aligned mode\r
-                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.\r
-                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
-\r
-  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.\r
-                                   This parameter can be a value of @ref TIM_AutoReloadPreload */\r
-} TIM_Base_InitTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Output Compare Configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t OCMode;        /*!< Specifies the TIM mode.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
-\r
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-\r
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
-\r
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
-                               @note This parameter is valid only for timer instances supporting break feature. */\r
-\r
-  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.\r
-                               This parameter can be a value of @ref TIM_Output_Fast_State\r
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */\r
-\r
-\r
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
-                               @note This parameter is valid only for timer instances supporting break feature. */\r
-\r
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
-                               @note This parameter is valid only for timer instances supporting break feature. */\r
-} TIM_OC_InitTypeDef;\r
-\r
-/**\r
-  * @brief  TIM One Pulse Mode Configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t OCMode;        /*!< Specifies the TIM mode.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
-\r
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-\r
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
-\r
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
-                               @note This parameter is valid only for timer instances supporting break feature. */\r
-\r
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
-                               @note This parameter is valid only for timer instances supporting break feature. */\r
-\r
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
-                               @note This parameter is valid only for timer instances supporting break feature. */\r
-\r
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.\r
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
-  uint32_t ICSelection;   /*!< Specifies the input.\r
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.\r
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_OnePulse_InitTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Input Capture Configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.\r
-                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
-  uint32_t ICSelection;  /*!< Specifies the input.\r
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.\r
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.\r
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_IC_InitTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Encoder Configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.\r
-                               This parameter can be a value of @ref TIM_Encoder_Mode */\r
-\r
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.\r
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
-  uint32_t IC1Selection;  /*!< Specifies the input.\r
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.\r
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.\r
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-\r
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.\r
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
-  uint32_t IC2Selection;  /*!< Specifies the input.\r
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.\r
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.\r
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_Encoder_InitTypeDef;\r
-\r
-/**\r
-  * @brief  Clock Configuration Handle Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t ClockSource;     /*!< TIM clock sources\r
-                                 This parameter can be a value of @ref TIM_Clock_Source */\r
-  uint32_t ClockPolarity;   /*!< TIM clock polarity\r
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */\r
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler\r
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */\r
-  uint32_t ClockFilter;     /*!< TIM clock filter\r
-                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_ClockConfigTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Clear Input Configuration Handle Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t ClearInputState;      /*!< TIM clear Input state\r
-                                      This parameter can be ENABLE or DISABLE */\r
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources\r
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */\r
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity\r
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */\r
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler\r
-                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
-  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter\r
-                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_ClearInputConfigTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Master configuration Structure definition\r
-  * @note   Advanced timers provide TRGO2 internal line which is redirected\r
-  *         to the ADC\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection\r
-                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */\r
-  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection\r
-                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */\r
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection\r
-                                        This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
-} TIM_MasterConfigTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Slave configuration Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t  SlaveMode;         /*!< Slave mode selection\r
-                                    This parameter can be a value of @ref TIM_Slave_Mode */\r
-  uint32_t  InputTrigger;      /*!< Input Trigger source\r
-                                    This parameter can be a value of @ref TIM_Trigger_Selection */\r
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity\r
-                                    This parameter can be a value of @ref TIM_Trigger_Polarity */\r
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler\r
-                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */\r
-  uint32_t  TriggerFilter;     /*!< Input trigger filter\r
-                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */\r
-\r
-} TIM_SlaveConfigTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Break input(s) and Dead time configuration Structure definition\r
-  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable\r
-  *        filter and polarity.\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t OffStateRunMode;      /*!< TIM off state in run mode\r
-                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
-  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode\r
-                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
-  uint32_t LockLevel;            /*!< TIM Lock level\r
-                                      This parameter can be a value of @ref TIM_Lock_level */\r
-  uint32_t DeadTime;             /*!< TIM dead Time\r
-                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
-  uint32_t BreakState;           /*!< TIM Break State\r
-                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
-  uint32_t BreakPolarity;        /*!< TIM Break input polarity\r
-                                      This parameter can be a value of @ref TIM_Break_Polarity */\r
-  uint32_t BreakFilter;          /*!< Specifies the break input filter.\r
-                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-  uint32_t Break2State;          /*!< TIM Break2 State\r
-                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */\r
-  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity\r
-                                      This parameter can be a value of @ref TIM_Break2_Polarity */\r
-  uint32_t Break2Filter;         /*!< TIM break2 input filter.\r
-                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state\r
-                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
-} TIM_BreakDeadTimeConfigTypeDef;\r
-\r
-/**\r
-  * @brief  HAL State structures definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */\r
-  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r
-  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */\r
-  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */\r
-  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */\r
-} HAL_TIM_StateTypeDef;\r
-\r
-/**\r
-  * @brief  HAL Active channel structures definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */\r
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */\r
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */\r
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */\r
-  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */\r
-  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */\r
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */\r
-} HAL_TIM_ActiveChannel;\r
-\r
-/**\r
-  * @brief  TIM Time Base Handle Structure definition\r
-  */\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-typedef struct __TIM_HandleTypeDef\r
-#else\r
-typedef struct\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-{\r
-  TIM_TypeDef                 *Instance;     /*!< Register base address             */\r
-  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */\r
-  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */\r
-  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array\r
-                                                  This array is accessed by a @ref DMA_Handle_index */\r
-  HAL_LockTypeDef             Lock;          /*!< Locking object                    */\r
-  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */\r
-  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */\r
-  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */\r
-  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */\r
-  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */\r
-  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */\r
-  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */\r
-  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */\r
-  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */\r
-  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */\r
-  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */\r
-  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */\r
-  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */\r
-  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */\r
-  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */\r
-  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */\r
-  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */\r
-  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */\r
-  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */\r
-  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */\r
-  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */\r
-  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */\r
-  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */\r
-  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */\r
-  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */\r
-  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */\r
-  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */\r
-  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-} TIM_HandleTypeDef;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  HAL TIM Callback ID enumeration definition\r
-  */\r
-typedef enum\r
-{\r
-   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */\r
-  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */\r
-  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */\r
-  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */\r
-  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */\r
-  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */\r
-  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */\r
-  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */\r
-  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */\r
-  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */\r
-  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */\r
-  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */\r
-  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */\r
-  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */\r
-  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */\r
-  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */\r
-  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */\r
-  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */\r
-\r
-  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */\r
-  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */\r
-  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */\r
-  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */\r
-  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */\r
-  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */\r
-  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */\r
-  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */\r
-  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */\r
-  ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */\r
-} HAL_TIM_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  HAL TIM Callback pointer definition\r
-  */\r
-typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */\r
-\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported types -----------------------------------------------------*/\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup TIM_Exported_Constants TIM Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source\r
-  * @{\r
-  */\r
-#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */\r
-#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */\r
-#define TIM_CLEARINPUTSOURCE_OCREFCLR       0x00000002U   /*!< OCREF_CLR is connected to OCREF_CLR_INT */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address\r
-  * @{\r
-  */\r
-#define TIM_DMABASE_CR1                    0x00000000U\r
-#define TIM_DMABASE_CR2                    0x00000001U\r
-#define TIM_DMABASE_SMCR                   0x00000002U\r
-#define TIM_DMABASE_DIER                   0x00000003U\r
-#define TIM_DMABASE_SR                     0x00000004U\r
-#define TIM_DMABASE_EGR                    0x00000005U\r
-#define TIM_DMABASE_CCMR1                  0x00000006U\r
-#define TIM_DMABASE_CCMR2                  0x00000007U\r
-#define TIM_DMABASE_CCER                   0x00000008U\r
-#define TIM_DMABASE_CNT                    0x00000009U\r
-#define TIM_DMABASE_PSC                    0x0000000AU\r
-#define TIM_DMABASE_ARR                    0x0000000BU\r
-#define TIM_DMABASE_RCR                    0x0000000CU\r
-#define TIM_DMABASE_CCR1                   0x0000000DU\r
-#define TIM_DMABASE_CCR2                   0x0000000EU\r
-#define TIM_DMABASE_CCR3                   0x0000000FU\r
-#define TIM_DMABASE_CCR4                   0x00000010U\r
-#define TIM_DMABASE_BDTR                   0x00000011U\r
-#define TIM_DMABASE_DCR                    0x00000012U\r
-#define TIM_DMABASE_DMAR                   0x00000013U\r
-#define TIM_DMABASE_OR1                    0x00000014U\r
-#define TIM_DMABASE_CCMR3                  0x00000015U\r
-#define TIM_DMABASE_CCR5                   0x00000016U\r
-#define TIM_DMABASE_CCR6                   0x00000017U\r
-#define TIM_DMABASE_OR2                    0x00000018U\r
-#define TIM_DMABASE_OR3                    0x00000019U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Event_Source TIM Event Source\r
-  * @{\r
-  */\r
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */\r
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */\r
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */\r
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */\r
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */\r
-#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */\r
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */\r
-#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */\r
-#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity\r
-  * @{\r
-  */\r
-#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */\r
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */\r
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\r
-  * @{\r
-  */\r
-#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */\r
-#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\r
-  * @{\r
-  */\r
-#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */\r
-#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */\r
-#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */\r
-#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Counter_Mode TIM Counter Mode\r
-  * @{\r
-  */\r
-#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */\r
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */\r
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */\r
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */\r
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_ClockDivision TIM Clock Division\r
-  * @{\r
-  */\r
-#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */\r
-#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */\r
-#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r
-  * @{\r
-  */\r
-#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */\r
-#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\r
-  * @{\r
-  */\r
-#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */\r
-#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State\r
-  * @{\r
-  */\r
-#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */\r
-#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r
-  * @{\r
-  */\r
-#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */\r
-#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity\r
-  * @{\r
-  */\r
-#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */\r
-#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r
-  * @{\r
-  */\r
-#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */\r
-#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State\r
-  * @{\r
-  */\r
-#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */\r
-#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State\r
-  * @{\r
-  */\r
-#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */\r
-#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity\r
-  * @{\r
-  */\r
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */\r
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */\r
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\r
-  * @{\r
-  */\r
-#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
-                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */\r
-#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
-                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */\r
-#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\r
-  * @{\r
-  */\r
-#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */\r
-#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */\r
-#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */\r
-#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r
-  * @{\r
-  */\r
-#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */\r
-#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r
-  * @{\r
-  */\r
-#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */\r
-#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */\r
-#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition\r
-  * @{\r
-  */\r
-#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */\r
-#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */\r
-#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */\r
-#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */\r
-#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */\r
-#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */\r
-#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */\r
-#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Commutation_Source  TIM Commutation Source\r
-  * @{\r
-  */\r
-#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */\r
-#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_DMA_sources TIM DMA Sources\r
-  * @{\r
-  */\r
-#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */\r
-#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */\r
-#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */\r
-#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */\r
-#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */\r
-#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */\r
-#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Flag_definition TIM Flag Definition\r
-  * @{\r
-  */\r
-#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */\r
-#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */\r
-#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */\r
-#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */\r
-#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */\r
-#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */\r
-#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */\r
-#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */\r
-#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */\r
-#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */\r
-#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */\r
-#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */\r
-#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */\r
-#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */\r
-#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */\r
-#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Channel TIM Channel\r
-  * @{\r
-  */\r
-#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */\r
-#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */\r
-#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */\r
-#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */\r
-#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */\r
-#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */\r
-#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Clock_Source TIM Clock Source\r
-  * @{\r
-  */\r
-#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */\r
-#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */\r
-#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */\r
-#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */\r
-#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */\r
-#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */\r
-#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */\r
-#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */\r
-#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */\r
-#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\r
-  * @{\r
-  */\r
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */\r
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */\r
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */\r
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */\r
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\r
-  * @{\r
-  */\r
-#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */\r
-#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r
-#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r
-#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\r
-  * @{\r
-  */\r
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */\r
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r
-  * @{\r
-  */\r
-#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */\r
-#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r
-#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r
-#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\r
-  * @{\r
-  */\r
-#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */\r
-#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\r
-  * @{\r
-  */\r
-#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */\r
-#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
-/**\r
-  * @}\r
-  */\r
-/** @defgroup TIM_Lock_level  TIM Lock level\r
-  * @{\r
-  */\r
-#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */\r
-#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */\r
-#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */\r
-#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable\r
-  * @{\r
-  */\r
-#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */\r
-#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity\r
-  * @{\r
-  */\r
-#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */\r
-#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable\r
-  * @{\r
-  */\r
-#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */\r
-#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity\r
-  * @{\r
-  */\r
-#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */\r
-#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable\r
-  * @{\r
-  */\r
-#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */\r
-#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event \r
-                                                                                    (if none of the break inputs BRK and BRK2 is active) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3\r
-  * @{\r
-  */\r
-#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r
-#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */\r
-#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */\r
-#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r
-  * @{\r
-  */\r
-#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */\r
-#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */\r
-#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */\r
-#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */\r
-#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */\r
-#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */\r
-#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */\r
-#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)\r
-  * @{\r
-  */\r
-#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */\r
-#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */\r
-#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */\r
-#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */\r
-#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */\r
-#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */\r
-#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */\r
-#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */\r
-#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */\r
-#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */\r
-#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */\r
-#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */\r
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */\r
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */\r
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */\r
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode\r
-  * @{\r
-  */\r
-#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */\r
-#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Slave_Mode TIM Slave mode\r
-  * @{\r
-  */\r
-#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */\r
-#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */\r
-#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */\r
-#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */\r
-#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */\r
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes\r
-  * @{\r
-  */\r
-#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */\r
-#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */\r
-#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */\r
-#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */\r
-#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */\r
-#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */\r
-#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */\r
-#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */\r
-#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */\r
-#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */\r
-#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */\r
-#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */\r
-#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */\r
-#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\r
-  * @{\r
-  */\r
-#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */\r
-#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */\r
-#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */\r
-#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */\r
-#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */\r
-#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */\r
-#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */\r
-#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */\r
-#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r
-  * @{\r
-  */\r
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */\r
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */\r
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r
-  * @{\r
-  */\r
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */\r
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection\r
-  * @{\r
-  */\r
-#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */\r
-#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length\r
-  * @{\r
-  */\r
-#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */\r
-#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */\r
-#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Handle_index TIM DMA Handle Index\r
-  * @{\r
-  */\r
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */\r
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r
-#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */\r
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State\r
-  * @{\r
-  */\r
-#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */\r
-#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */\r
-#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */\r
-#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Break_System TIM Break System\r
-  * @{\r
-  */\r
-#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */\r
-#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */\r
-#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR  SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */\r
-#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported constants -------------------------------------------------*/\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup TIM_Exported_Macros TIM Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Reset TIM handle state.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @retval None\r
-  */\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \\r
-                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \\r
-                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \\r
-                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \\r
-                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \\r
-                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \\r
-                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \\r
-                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \\r
-                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \\r
-                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \\r
-                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \\r
-                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \\r
-                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \\r
-                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \\r
-                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \\r
-                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \\r
-                                                     } while(0)\r
-#else\r
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @brief  Enable the TIM peripheral.\r
-  * @param  __HANDLE__ TIM handle\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r
-\r
-/**\r
-  * @brief  Enable the TIM main Output.\r
-  * @param  __HANDLE__ TIM handle\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r
-\r
-/**\r
-  * @brief  Disable the TIM peripheral.\r
-  * @param  __HANDLE__ TIM handle\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_DISABLE(__HANDLE__) \\r
-  do { \\r
-    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
-    { \\r
-      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
-      { \\r
-        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\r
-      } \\r
-    } \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Disable the TIM main Output.\r
-  * @param  __HANDLE__ TIM handle\r
-  * @retval None\r
-  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled\r
-  */\r
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\r
-  do { \\r
-    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
-    { \\r
-      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
-      { \\r
-        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\r
-      } \\r
-    } \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Disable the TIM main Output.\r
-  * @param  __HANDLE__ TIM handle\r
-  * @retval None\r
-  * @note The Main Output Enable of a timer instance is disabled unconditionally\r
-  */\r
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)\r
-\r
-/** @brief  Enable the specified TIM interrupt.\r
-  * @param  __HANDLE__ specifies the TIM Handle.\r
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_IT_UPDATE: Update interrupt\r
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
-  *            @arg TIM_IT_COM:   Commutation interrupt\r
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
-  *            @arg TIM_IT_BREAK: Break interrupt\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r
-\r
-/** @brief  Disable the specified TIM interrupt.\r
-  * @param  __HANDLE__ specifies the TIM Handle.\r
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_IT_UPDATE: Update interrupt\r
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
-  *            @arg TIM_IT_COM:   Commutation interrupt\r
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
-  *            @arg TIM_IT_BREAK: Break interrupt\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r
-\r
-/** @brief  Enable the specified DMA request.\r
-  * @param  __HANDLE__ specifies the TIM Handle.\r
-  * @param  __DMA__ specifies the TIM DMA request to enable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_DMA_UPDATE: Update DMA request\r
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\r
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\r
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\r
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\r
-  *            @arg TIM_DMA_COM:   Commutation DMA request\r
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))\r
-\r
-/** @brief  Disable the specified DMA request.\r
-  * @param  __HANDLE__ specifies the TIM Handle.\r
-  * @param  __DMA__ specifies the TIM DMA request to disable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_DMA_UPDATE: Update DMA request\r
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\r
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\r
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\r
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\r
-  *            @arg TIM_DMA_COM:   Commutation DMA request\r
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r
-\r
-/** @brief  Check whether the specified TIM interrupt flag is set or not.\r
-  * @param  __HANDLE__ specifies the TIM Handle.\r
-  * @param  __FLAG__ specifies the TIM interrupt flag to check.\r
-  *        This parameter can be one of the following values:\r
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\r
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
-  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
-  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
-  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\r
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag\r
-  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
-  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
-  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r
-\r
-/** @brief  Clear the specified TIM interrupt flag.\r
-  * @param  __HANDLE__ specifies the TIM Handle.\r
-  * @param  __FLAG__ specifies the TIM interrupt flag to clear.\r
-  *        This parameter can be one of the following values:\r
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\r
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
-  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
-  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
-  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\r
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag\r
-  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
-  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
-  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
-\r
-/**\r
-  * @brief  Check whether the specified TIM interrupt source is enabled or not.\r
-  * @param  __HANDLE__ TIM handle\r
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_IT_UPDATE: Update interrupt\r
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
-  *            @arg TIM_IT_COM:   Commutation interrupt\r
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
-  *            @arg TIM_IT_BREAK: Break interrupt\r
-  * @retval The state of TIM_IT (SET or RESET).\r
-  */\r
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \\r
-                                                             == (__INTERRUPT__)) ? SET : RESET)\r
-\r
-/** @brief Clear the TIM interrupt pending bits.\r
-  * @param  __HANDLE__ TIM handle\r
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_IT_UPDATE: Update interrupt\r
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r
-  *            @arg TIM_IT_COM:   Commutation interrupt\r
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r
-  *            @arg TIM_IT_BREAK: Break interrupt\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r
-\r
-/**\r
-  * @brief  Indicates whether or not the TIM Counter is used as downcounter.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\r
-  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder\r
-mode.\r
-  */\r
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r
-\r
-/**\r
-  * @brief  Set the TIM Prescaler on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __PRESC__ specifies the Prescaler new value.\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))\r
-\r
-/**\r
-  * @brief  Set the TIM Counter Register value on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __COUNTER__ specifies the Counter register new value.\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r
-\r
-/**\r
-  * @brief  Get the TIM Counter Register value on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)\r
-  */\r
-#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)\r
-\r
-/**\r
-  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __AUTORELOAD__ specifies the Counter register new value.\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\r
-  do{                                                    \\r
-    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \\r
-    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Get the TIM Autoreload Register value on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)\r
-  */\r
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)\r
-\r
-/**\r
-  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CKD__ specifies the clock division value.\r
-  *          This parameter can be one of the following value:\r
-  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
-  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
-  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\r
-  do{                                                   \\r
-    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \\r
-    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \\r
-    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Get the TIM Clock Division value on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @retval The clock division can be one of the following values:\r
-  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
-  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
-  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
-  */\r
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r
-\r
-/**\r
-  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CHANNEL__ TIM Channels to be configured.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICPSC_DIV1: no prescaler\r
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
-  do{                                                    \\r
-    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \\r
-    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\r
-  } while(0)\r
-\r
-/**\r
-  * @brief  Get the TIM Input Capture prescaler on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CHANNEL__ TIM Channels to be configured.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r
-  * @retval The input capture prescaler can be one of the following values:\r
-  *            @arg TIM_ICPSC_DIV1: no prescaler\r
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
-  */\r
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\r
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)\r
-\r
-/**\r
-  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CHANNEL__ TIM Channels to be configured.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @param  __COMPARE__ specifies the Capture Compare register new value.\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\r
-   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))\r
-\r
-/**\r
-  * @brief  Get the TIM Capture Compare Register value on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CHANNEL__ TIM Channel associated with the capture compare register\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
-  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value\r
-  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value\r
-  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)\r
-  */\r
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\r
-   ((__HANDLE__)->Instance->CCR6))\r
-\r
-/**\r
-  * @brief  Set the TIM Output compare preload.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CHANNEL__ TIM Channels to be configured.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\\r
-   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))\r
-\r
-/**\r
-  * @brief  Reset the TIM Output compare preload.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CHANNEL__ TIM Channels to be configured.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\\r
-   ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))\r
-\r
-/**\r
-  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @note  When the URS bit of the TIMx_CR1 register is set, only counter\r
-  *        overflow/underflow generates an update interrupt or DMA request (if\r
-  *        enabled)\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)\r
-\r
-/**\r
-  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the\r
-  *        following events generate an update interrupt or DMA request (if\r
-  *        enabled):\r
-  *           _ Counter overflow underflow\r
-  *           _ Setting the UG bit\r
-  *           _ Update generation through the slave mode controller\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)\r
-\r
-/**\r
-  * @brief  Set the TIM Capture x input polarity on runtime.\r
-  * @param  __HANDLE__ TIM handle.\r
-  * @param  __CHANNEL__ TIM Channels to be configured.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @param  __POLARITY__ Polarity for TIx source\r
-  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r
-  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r
-  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r
-  * @retval None\r
-  */\r
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \\r
-  do{                                                                     \\r
-    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \\r
-    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\r
-  }while(0)\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported macros ----------------------------------------------------*/\r
-\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup TIM_Private_Constants TIM Private Constants\r
-  * @{\r
-  */\r
-/* The counter of a timer instance is disabled only if all the CCx and CCxN\r
-   channels have been disabled */\r
-#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r
-/**\r
-  * @}\r
-  */\r
-/* End of private constants --------------------------------------------------*/\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup TIM_Private_Macros TIM Private Macros\r
-  * @{\r
-  */\r
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \\r
-                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \\r
-                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))\r
-\r
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_CR2)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_DIER)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_SR)    || \\r
-                                   ((__BASE__) == TIM_DMABASE_EGR)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCER)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_CNT)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_PSC)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_ARR)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_RCR)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_OR1)    || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \\r
-                                   ((__BASE__) == TIM_DMABASE_OR2)   || \\r
-                                   ((__BASE__) == TIM_DMABASE_OR3))\r
-\r
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
-\r
-#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \\r
-                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \\r
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \\r
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \\r
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r
-\r
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\r
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\r
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r
-\r
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\r
-                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\r
-\r
-#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \\r
-                                            ((__STATE__) == TIM_OCFAST_ENABLE))\r
-\r
-#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\r
-                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r
-\r
-#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\r
-                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\r
-\r
-#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \\r
-                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))\r
-\r
-#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\r
-                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))\r
-\r
-#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \\r
-                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \\r
-                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r
-\r
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\r
-                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\r
-                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))\r
-\r
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\r
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\r
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\r
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))\r
-\r
-#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \\r
-                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))\r
-\r
-#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \\r
-                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \\r
-                                            ((__MODE__) == TIM_ENCODERMODE_TI12))\r
-\r
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
-\r
-#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
-                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
-                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
-                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
-                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
-                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \\r
-                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))\r
-\r
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
-                                            ((__CHANNEL__) == TIM_CHANNEL_2))\r
-\r
-#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
-                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
-                                                    ((__CHANNEL__) == TIM_CHANNEL_3))\r
-\r
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \\r
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r
-\r
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \\r
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\r
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \\r
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \\r
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r
-\r
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\r
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\r
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\r
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))\r
-\r
-#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)\r
-\r
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\r
-                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r
-\r
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\r
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\r
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\r
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r
-\r
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
-\r
-#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \\r
-                                            ((__STATE__) == TIM_OSSR_DISABLE))\r
-\r
-#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \\r
-                                            ((__STATE__) == TIM_OSSI_DISABLE))\r
-\r
-#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\r
-                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \\r
-                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \\r
-                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))\r
-\r
-#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)\r
-\r
-\r
-#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \\r
-                                            ((__STATE__) == TIM_BREAK_DISABLE))\r
-\r
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\r
-                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\r
-\r
-#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \\r
-                                            ((__STATE__) == TIM_BREAK2_DISABLE))\r
-\r
-#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\r
-                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r
-\r
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\r
-                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\r
-\r
-#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))\r
-\r
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \\r
-                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \\r
-                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \\r
-                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \\r
-                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \\r
-                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \\r
-                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \\r
-                                        ((__SOURCE__) == TIM_TRGO_OC4REF))\r
-\r
-#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \\r
-                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r
-\r
-#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\r
-                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r
-\r
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \\r
-                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \\r
-                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \\r
-                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \\r
-                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \\r
-                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
-\r
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \\r
-                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \\r
-                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \\r
-                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \\r
-                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \\r
-                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))\r
-\r
-#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \\r
-                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \\r
-                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \\r
-                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \\r
-                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \\r
-                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \\r
-                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\r
-                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r
-\r
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
-                                                 ((__SELECTION__) == TIM_TS_ITR1) || \\r
-                                                 ((__SELECTION__) == TIM_TS_ITR2) || \\r
-                                                 ((__SELECTION__) == TIM_TS_ITR3) || \\r
-                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \\r
-                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \\r
-                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \\r
-                                                 ((__SELECTION__) == TIM_TS_ETRF))\r
-\r
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
-                                                               ((__SELECTION__) == TIM_TS_ITR1) || \\r
-                                                               ((__SELECTION__) == TIM_TS_ITR2) || \\r
-                                                               ((__SELECTION__) == TIM_TS_ITR3) || \\r
-                                                               ((__SELECTION__) == TIM_TS_NONE))\r
-\r
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \\r
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\r
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \\r
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \\r
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))\r
-\r
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\r
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\r
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\r
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))\r
-\r
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
-\r
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\r
-                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r
-\r
-#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\r
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r
-\r
-#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)\r
-\r
-#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)\r
-\r
-#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \\r
-                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \\r
-                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)   || \\r
-                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))\r
-\r
-#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \\r
-                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
-\r
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\r
-   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))\r
-\r
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\r
-   ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r
-\r
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\\r
-   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))\r
-\r
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\r
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\r
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\r
-   ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of private macros -----------------------------------------------------*/\r
-\r
-/* Include TIM HAL Extended module */\r
-#include "stm32l4xx_hal_tim_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
-  *  @brief   Time Base functions\r
-  * @{\r
-  */\r
-/* Time Base functions ********************************************************/\r
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
-  *  @brief   TIM Output Compare functions\r
-  * @{\r
-  */\r
-/* Timer Output Compare functions *********************************************/\r
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions\r
-  *  @brief   TIM PWM functions\r
-  * @{\r
-  */\r
-/* Timer PWM functions ********************************************************/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
-  *  @brief   TIM Input Capture functions\r
-  * @{\r
-  */\r
-/* Timer Input Capture functions **********************************************/\r
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
-  *  @brief   TIM One Pulse functions\r
-  * @{\r
-  */\r
-/* Timer One Pulse functions **************************************************/\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
-  *  @brief   TIM Encoder functions\r
-  * @{\r
-  */\r
-/* Timer Encoder functions ****************************************************/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\r
-                                            uint32_t *pData2, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
-  *  @brief   IRQ handler management\r
-  * @{\r
-  */\r
-/* Interrupt Handler functions  ***********************************************/\r
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
-  *  @brief   Peripheral Control functions\r
-  * @{\r
-  */\r
-/* Control functions  *********************************************************/\r
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,\r
-                                                 uint32_t OutputChannel,  uint32_t InputChannel);\r
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
-                                           uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);\r
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
-                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
-                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
-  *  @brief   TIM Callbacks functions\r
-  * @{\r
-  */\r
-/* Callback in non blocking modes (Interrupt and DMA) *************************/\r
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r
-\r
-/* Callbacks Register/UnRegister functions  ***********************************/\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\r
-                                           pTIM_CallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
-  *  @brief  Peripheral State functions\r
-  * @{\r
-  */\r
-/* Peripheral State functions  ************************************************/\r
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported functions -------------------------------------------------*/\r
-\r
-/* Private functions----------------------------------------------------------*/\r
-/** @defgroup TIM_Private_Functions TIM Private Functions\r
-  * @{\r
-  */\r
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r
-\r
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);\r
-void TIM_DMAError(DMA_HandleTypeDef *hdma);\r
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);\r
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-void TIM_ResetCallback(TIM_HandleTypeDef *htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of private functions --------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_TIM_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
deleted file mode 100644 (file)
index 52d7a46..0000000
+++ /dev/null
@@ -1,440 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_tim_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of TIM HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_TIM_EX_H\r
-#define STM32L4xx_HAL_TIM_EX_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup TIMEx\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  TIM Hall sensor Configuration Structure definition\r
-  */\r
-\r
-typedef struct\r
-{\r
-  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.\r
-                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
-  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.\r
-                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
-  uint32_t IC1Filter;           /*!< Specifies the input capture filter.\r
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-\r
-  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
-                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-} TIM_HallSensor_InitTypeDef;\r
-\r
-/**\r
-  * @brief  TIM Break/Break2 input configuration\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t Source;         /*!< Specifies the source of the timer break input.\r
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source */\r
-  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.\r
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */\r
-  uint32_t Polarity;       /*!< Specifies the break input source polarity.\r
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity\r
-                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */\r
-}\r
-TIMEx_BreakInputConfigTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported types -----------------------------------------------------*/\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup TIMEx_Remap TIM Extended Remapping\r
-  * @{\r
-  */\r
-#define TIM_TIM1_ETR_ADC1_NONE      0x00000000U                                           /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/\r
-#define TIM_TIM1_ETR_ADC1_AWD1      TIM1_OR1_ETR_ADC1_RMP_0                               /* !< TIM1_ETR is connected to ADC1 AWD1 */\r
-#define TIM_TIM1_ETR_ADC1_AWD2      TIM1_OR1_ETR_ADC1_RMP_1                               /* !< TIM1_ETR is connected to ADC1 AWD2 */\r
-#define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */\r
-#if defined (ADC3)\r
-#define TIM_TIM1_ETR_ADC3_NONE      0x00000000U                                           /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/\r
-#define TIM_TIM1_ETR_ADC3_AWD1      TIM1_OR1_ETR_ADC3_RMP_0                               /* !< TIM1_ETR is connected to ADC3 AWD1 */\r
-#define TIM_TIM1_ETR_ADC3_AWD2      TIM1_OR1_ETR_ADC3_RMP_1                               /* !< TIM1_ETR is connected to ADC3 AWD2 */\r
-#define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */\r
-#endif /* ADC3 */\r
-#define TIM_TIM1_TI1_GPIO           0x00000000U                                           /* !< TIM1 TI1 is connected to GPIO */\r
-#define TIM_TIM1_TI1_COMP1          TIM1_OR1_TI1_RMP                                      /* !< TIM1 TI1 is connected to COMP1 */\r
-#define TIM_TIM1_ETR_GPIO           0x00000000U                                           /* !< TIM1_ETR is connected to GPIO */\r
-#define TIM_TIM1_ETR_COMP1          TIM1_OR2_ETRSEL_0                                     /* !< TIM1_ETR is connected to COMP1 output */\r
-#if defined(COMP2)\r
-#define TIM_TIM1_ETR_COMP2          TIM1_OR2_ETRSEL_1                                     /* !< TIM1_ETR is connected to COMP2 output */\r
-#endif /* COMP2 */\r
-\r
-#if defined (USB_OTG_FS)\r
-#define TIM_TIM2_ITR1_TIM8_TRGO     0x00000000U                                           /* !< TIM2_ITR1 is connected to TIM8_TRGO */\r
-#define TIM_TIM2_ITR1_OTG_FS_SOF    TIM2_OR1_ITR1_RMP                                     /* !< TIM2_ITR1 is connected to OTG_FS SOF */\r
-#else\r
-#if defined(STM32L471xx)\r
-#define TIM_TIM2_ITR1_TIM8_TRGO     0x00000000U                                           /* !< TIM2_ITR1 is connected to TIM8_TRGO */\r
-#define TIM_TIM2_ITR1_NONE          TIM2_OR1_ITR1_RMP                                     /* !< No internal trigger on TIM2_ITR1 */\r
-#else\r
-#define TIM_TIM2_ITR1_NONE          0x00000000U                                           /* !< No internal trigger on TIM2_ITR1 */\r
-#define TIM_TIM2_ITR1_USB_SOF       TIM2_OR1_ITR1_RMP                                     /* !< TIM2_ITR1 is connected to USB SOF */\r
-#endif /* STM32L471xx */\r
-#endif /* USB_OTG_FS */\r
-#define TIM_TIM2_ETR_GPIO           0x00000000U                                           /* !< TIM2_ETR is connected to GPIO */\r
-#define TIM_TIM2_ETR_LSE            TIM2_OR1_ETR1_RMP                                     /* !< TIM2_ETR is connected to LSE */\r
-#define TIM_TIM2_ETR_COMP1          TIM2_OR2_ETRSEL_0                                     /* !< TIM2_ETR is connected to COMP1 output */\r
-#if defined(COMP2)\r
-#define TIM_TIM2_ETR_COMP2          TIM2_OR2_ETRSEL_1                                     /* !< TIM2_ETR is connected to COMP2 output */\r
-#endif /* COMP2 */\r
-#define TIM_TIM2_TI4_GPIO           0x00000000U                                           /* !< TIM2 TI4 is connected to GPIO */\r
-#define TIM_TIM2_TI4_COMP1          TIM2_OR1_TI4_RMP_0                                    /* !< TIM2 TI4 is connected to COMP1 output */\r
-#if defined(COMP2)\r
-#define TIM_TIM2_TI4_COMP2          TIM2_OR1_TI4_RMP_1                                    /* !< TIM2 TI4 is connected to COMP2 output */\r
-#define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */\r
-#endif /* COMP2 */\r
-\r
-#if defined (TIM3)\r
-#define TIM_TIM3_TI1_GPIO           0x00000000U                                           /* !< TIM3 TI1 is connected to GPIO */\r
-#define TIM_TIM3_TI1_COMP1          TIM3_OR1_TI1_RMP_0                                    /* !< TIM3 TI1 is connected to COMP1 output */\r
-#define TIM_TIM3_TI1_COMP2          TIM3_OR1_TI1_RMP_1                                    /* !< TIM3 TI1 is connected to COMP2 output */\r
-#define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */\r
-#define TIM_TIM3_ETR_GPIO           0x00000000U                                           /* !< TIM3_ETR is connected to GPIO */\r
-#define TIM_TIM3_ETR_COMP1          TIM3_OR2_ETRSEL_0                                     /* !< TIM3_ETR is connected to COMP1 output */\r
-#endif /* TIM3 */\r
-\r
-#if defined (TIM8)\r
-#if defined(ADC2) && defined(ADC3)\r
-#define TIM_TIM8_ETR_ADC2_NONE      0x00000000U                                           /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/\r
-#define TIM_TIM8_ETR_ADC2_AWD1      TIM8_OR1_ETR_ADC2_RMP_0                               /* !< TIM8_ETR is connected to ADC2 AWD1 */\r
-#define TIM_TIM8_ETR_ADC2_AWD2      TIM8_OR1_ETR_ADC2_RMP_1                               /* !< TIM8_ETR is connected to ADC2 AWD2 */\r
-#define TIM_TIM8_ETR_ADC2_AWD3      (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0)   /* !< TIM8_ETR is connected to ADC2 AWD3 */\r
-#define TIM_TIM8_ETR_ADC3_NONE      0x00000000U                                           /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/\r
-#define TIM_TIM8_ETR_ADC3_AWD1      TIM8_OR1_ETR_ADC3_RMP_0                               /* !< TIM8_ETR is connected to ADC3 AWD1 */\r
-#define TIM_TIM8_ETR_ADC3_AWD2      TIM8_OR1_ETR_ADC3_RMP_1                               /* !< TIM8_ETR is connected to ADC3 AWD2 */\r
-#define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */\r
-#endif /* ADC2 && ADC3 */\r
-\r
-#define TIM_TIM8_TI1_GPIO           0x00000000U                                           /* !< TIM8 TI1 is connected to GPIO */\r
-#define TIM_TIM8_TI1_COMP2          TIM8_OR1_TI1_RMP                                      /* !< TIM8 TI1 is connected to COMP1 */\r
-#define TIM_TIM8_ETR_GPIO           0x00000000U                                           /* !< TIM8_ETR is connected to GPIO */\r
-#define TIM_TIM8_ETR_COMP1          TIM8_OR2_ETRSEL_0                                     /* !< TIM8_ETR is connected to COMP1 output */\r
-#define TIM_TIM8_ETR_COMP2          TIM8_OR2_ETRSEL_1                                     /* !< TIM8_ETR is connected to COMP2 output */\r
-#endif /* TIM8 */\r
-\r
-#define TIM_TIM15_TI1_GPIO          0x00000000U                                           /* !< TIM15 TI1 is connected to GPIO */\r
-#define TIM_TIM15_TI1_LSE           TIM15_OR1_TI1_RMP                                     /* !< TIM15 TI1 is connected to LSE */\r
-#define TIM_TIM15_ENCODERMODE_NONE  0x00000000U                                           /* !< No redirection */\r
-#define TIM_TIM15_ENCODERMODE_TIM2  TIM15_OR1_ENCODER_MODE_0                              /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
-#if defined (TIM3)\r
-#define TIM_TIM15_ENCODERMODE_TIM3  TIM15_OR1_ENCODER_MODE_1                              /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
-#endif /* TIM3 */\r
-#if defined (TIM4)\r
-#define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */\r
-#endif /* TIM4 */\r
-\r
-#define TIM_TIM16_TI1_GPIO          0x00000000U                                           /* !< TIM16 TI1 is connected to GPIO */\r
-#define TIM_TIM16_TI1_LSI           TIM16_OR1_TI1_RMP_0                                   /* !< TIM16 TI1 is connected to LSI */\r
-#define TIM_TIM16_TI1_LSE           TIM16_OR1_TI1_RMP_1                                   /* !< TIM16 TI1 is connected to LSE */\r
-#define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */\r
-#if defined (TIM16_OR1_TI1_RMP_2)\r
-#define TIM_TIM16_TI1_MSI           TIM16_OR1_TI1_RMP_2                                   /* !< TIM16 TI1 is connected to MSI */\r
-#define TIM_TIM16_TI1_HSE_32        (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to HSE div 32 */\r
-#define TIM_TIM16_TI1_MCO           (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1)           /* !< TIM16 TI1 is connected to MCO */\r
-#endif /* TIM16_OR1_TI1_RMP_2 */\r
-\r
-#if defined (TIM17)\r
-#define TIM_TIM17_TI1_GPIO          0x00000000U                                           /* !< TIM17 TI1 is connected to GPIO */\r
-#define TIM_TIM17_TI1_MSI           TIM17_OR1_TI1_RMP_0                                   /* !< TIM17 TI1 is connected to MSI */\r
-#define TIM_TIM17_TI1_HSE_32        TIM17_OR1_TI1_RMP_1                                   /* !< TIM17 TI1 is connected to HSE div 32 */\r
-#define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */\r
-#endif /* TIM17 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Break_Input TIM Extended Break input\r
-  * @{\r
-  */\r
-#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */\r
-#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source\r
-  * @{\r
-  */\r
-#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */\r
-#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */\r
-#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */\r
-#if defined (DFSDM1_Channel0)\r
-#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */\r
-#endif /* DFSDM1_Channel0 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling\r
-  * @{\r
-  */\r
-#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */\r
-#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity\r
-  * @{\r
-  */\r
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */\r
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported constants -------------------------------------------------*/\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported macro -----------------------------------------------------*/\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros\r
-  * @{\r
-  */\r
-#define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))\r
-\r
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \\r
-                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))\r
-\r
-#if defined (DFSDM1_Channel0)\r
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\r
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \\r
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \\r
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))\r
-#else\r
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\r
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \\r
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))\r
-#endif /* DFSDM1_Channel0 */\r
-\r
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \\r
-                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))\r
-\r
-#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \\r
-                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of private macro ------------------------------------------------------*/\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
-  *  @brief    Timer Hall Sensor functions\r
-  * @{\r
-  */\r
-/*  Timer Hall Sensor functions  **********************************************/\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);\r
-\r
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);\r
-\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
-  *  @brief   Timer Complementary Output Compare functions\r
-  * @{\r
-  */\r
-/*  Timer Complementary Output Compare functions  *****************************/\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
-  *  @brief    Timer Complementary PWM functions\r
-  * @{\r
-  */\r
-/*  Timer Complementary PWM functions  ****************************************/\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
-  *  @brief    Timer Complementary One Pulse functions\r
-  * @{\r
-  */\r
-/*  Timer Complementary One Pulse functions  **********************************/\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
-  *  @brief    Peripheral Control functions\r
-  * @{\r
-  */\r
-/* Extended Control functions  ************************************************/\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
-                                              uint32_t  CommutationSource);\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
-                                                 uint32_t  CommutationSource);\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
-                                                  uint32_t  CommutationSource);\r
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
-                                                        TIM_MasterConfigTypeDef *sMasterConfig);\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
-                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,\r
-                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);\r
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);\r
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
-  * @brief    Extended Callbacks functions\r
-  * @{\r
-  */\r
-/* Extended Callback **********************************************************/\r
-void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
-  * @brief    Extended Peripheral State functions\r
-  * @{\r
-  */\r
-/* Extended Peripheral State functions  ***************************************/\r
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported functions -------------------------------------------------*/\r
-\r
-/* Private functions----------------------------------------------------------*/\r
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions\r
-  * @{\r
-  */\r
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);\r
-/**\r
-  * @}\r
-  */\r
-/* End of private functions --------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* STM32L4xx_HAL_TIM_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
deleted file mode 100644 (file)
index 723130c..0000000
+++ /dev/null
@@ -1,1686 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_uart.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of UART HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_UART_H\r
-#define STM32L4xx_HAL_UART_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup UART\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup UART_Exported_Types UART Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief UART Init Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.\r
-                                           The baud rate register is computed using the following formula:\r
-                                           LPUART:\r
-                                           =======\r
-                                              Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))\r
-                                           where lpuart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable)\r
-                                           UART:\r
-                                           =====\r
-                                           - If oversampling is 16 or in LIN mode,\r
-                                              Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))\r
-                                           - If oversampling is 8,\r
-                                              Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]\r
-                                              Baud Rate Register[3] =  0\r
-                                              Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1\r
-                                           where uart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable) */\r
-\r
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r
-                                           This parameter can be a value of @ref UARTEx_Word_Length. */\r
-\r
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\r
-                                           This parameter can be a value of @ref UART_Stop_Bits. */\r
-\r
-  uint32_t Parity;                    /*!< Specifies the parity mode.\r
-                                           This parameter can be a value of @ref UART_Parity\r
-                                           @note When parity is enabled, the computed parity is inserted\r
-                                                 at the MSB position of the transmitted data (9th bit when\r
-                                                 the word length is set to 9 data bits; 8th bit when the\r
-                                                 word length is set to 8 data bits). */\r
-\r
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
-                                           This parameter can be a value of @ref UART_Mode. */\r
-\r
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled\r
-                                           or disabled.\r
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control. */\r
-\r
-  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).\r
-                                           This parameter can be a value of @ref UART_Over_Sampling. */\r
-\r
-  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.\r
-                                           Selecting the single sample method increases the receiver tolerance to clock\r
-                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */\r
-\r
-#if defined(USART_PRESC_PRESCALER)\r
-  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the UART clock source.\r
-                                           This parameter can be a value of @ref UART_ClockPrescaler. */\r
-#endif /* USART_PRESC_PRESCALER */\r
-\r
-} UART_InitTypeDef;\r
-\r
-/**\r
-  * @brief  UART Advanced Features initialization structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several\r
-                                       Advanced Features may be initialized at the same time .\r
-                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */\r
-\r
-  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.\r
-                                       This parameter can be a value of @ref UART_Tx_Inv. */\r
-\r
-  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.\r
-                                       This parameter can be a value of @ref UART_Rx_Inv. */\r
-\r
-  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic\r
-                                       vs negative/inverted logic).\r
-                                       This parameter can be a value of @ref UART_Data_Inv. */\r
-\r
-  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.\r
-                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */\r
-\r
-  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.\r
-                                       This parameter can be a value of @ref UART_Overrun_Disable. */\r
-\r
-  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.\r
-                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */\r
-\r
-  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.\r
-                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */\r
-\r
-  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate\r
-                                       detection is carried out.\r
-                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */\r
-\r
-  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.\r
-                                       This parameter can be a value of @ref UART_MSB_First. */\r
-} UART_AdvFeatureInitTypeDef;\r
-\r
-\r
-\r
-/**\r
-  * @brief HAL UART State definition\r
-  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).\r
-  *        - gState contains UART state information related to global Handle management\r
-  *          and also information related to Tx operations.\r
-  *          gState value coding follow below described bitmap :\r
-  *          b7-b6  Error information\r
-  *             00 : No Error\r
-  *             01 : (Not Used)\r
-  *             10 : Timeout\r
-  *             11 : Error\r
-  *          b5     Peripheral initialization status\r
-  *             0  : Reset (Peripheral not initialized)\r
-  *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)\r
-  *          b4-b3  (not used)\r
-  *             xx : Should be set to 00\r
-  *          b2     Intrinsic process state\r
-  *             0  : Ready\r
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)\r
-  *          b1     (not used)\r
-  *             x  : Should be set to 0\r
-  *          b0     Tx state\r
-  *             0  : Ready (no Tx operation ongoing)\r
-  *             1  : Busy (Tx operation ongoing)\r
-  *        - RxState contains information related to Rx operations.\r
-  *          RxState value coding follow below described bitmap :\r
-  *          b7-b6  (not used)\r
-  *             xx : Should be set to 00\r
-  *          b5     Peripheral initialization status\r
-  *             0  : Reset (Peripheral not initialized)\r
-  *             1  : Init done (Peripheral not initialized)\r
-  *          b4-b2  (not used)\r
-  *            xxx : Should be set to 000\r
-  *          b1     Rx state\r
-  *             0  : Ready (no Rx operation ongoing)\r
-  *             1  : Busy (Rx operation ongoing)\r
-  *          b0     (not used)\r
-  *             x  : Should be set to 0.\r
-  */\r
-typedef uint32_t HAL_UART_StateTypeDef;\r
-\r
-/**\r
-  * @brief UART clock sources definition\r
-  */\r
-typedef enum\r
-{\r
-  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r
-  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r
-  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r
-  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r
-  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */\r
-  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */\r
-} UART_ClockSourceTypeDef;\r
-\r
-/**\r
-  * @brief  UART handle Structure definition\r
-  */\r
-typedef struct __UART_HandleTypeDef\r
-{\r
-  USART_TypeDef            *Instance;                /*!< UART registers base address        */\r
-\r
-  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */\r
-\r
-  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */\r
-\r
-  uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */\r
-\r
-  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */\r
-\r
-  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */\r
-\r
-  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */\r
-\r
-  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */\r
-\r
-  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */\r
-\r
-  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.\r
-                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */\r
-\r
-  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */\r
-\r
-  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */\r
-#endif /*USART_CR1_FIFOEN */\r
-\r
-  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler   */\r
-\r
-  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler   */\r
-\r
-  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */\r
-\r
-  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */\r
-\r
-  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */\r
-\r
-  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management\r
-                                                          and also related to Tx operations.\r
-                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
-\r
-  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations.\r
-                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
-\r
-  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */\r
-  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */\r
-  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */\r
-  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */\r
-  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */\r
-  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */\r
-  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */\r
-  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */\r
-  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */\r
-#if defined(USART_CR1_FIFOEN)\r
-  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */\r
-  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */\r
-  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */\r
-#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-\r
-} UART_HandleTypeDef;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  HAL UART Callback ID enumeration definition\r
-  */\r
-typedef enum\r
-{\r
-  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */\r
-  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */\r
-  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */\r
-  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */\r
-  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */\r
-  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */\r
-  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */\r
-  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */\r
-  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */\r
-#if defined(USART_CR1_FIFOEN)\r
-  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */\r
-  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */\r
-  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */\r
-\r
-} HAL_UART_CallbackIDTypeDef;\r
-\r
-/**\r
-  * @brief  HAL UART Callback pointer definition\r
-  */\r
-typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */\r
-\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup UART_Exported_Constants UART Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup UART_State_Definition UART State Code Definition\r
-  * @{\r
-  */\r
-#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized\r
-                                                          Value is allowed for gState and RxState */\r
-#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use\r
-                                                          Value is allowed for gState and RxState */\r
-#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing\r
-                                                          Value is allowed for gState only */\r
-#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing\r
-                                                          Value is allowed for gState only */\r
-#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing\r
-                                                          Value is allowed for RxState only */\r
-#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing\r
-                                                          Not to be used for neither gState nor RxState.\r
-                                                          Value is result of combination (Or) between gState and RxState values */\r
-#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state\r
-                                                          Value is allowed for gState only */\r
-#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error\r
-                                                          Value is allowed for gState only */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Error_Definition   UART Error Definition\r
-  * @{\r
-  */\r
-#define  HAL_UART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                */\r
-#define  HAL_UART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error            */\r
-#define  HAL_UART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error             */\r
-#define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */\r
-#define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */\r
-#define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-#define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Stop_Bits   UART Number of Stop Bits\r
-  * @{\r
-  */\r
-#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */\r
-#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */\r
-#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */\r
-#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Parity  UART Parity\r
-  * @{\r
-  */\r
-#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */\r
-#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */\r
-#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r
-  * @{\r
-  */\r
-#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */\r
-#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */\r
-#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */\r
-#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Mode UART Transfer Mode\r
-  * @{\r
-  */\r
-#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */\r
-#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */\r
-#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_State  UART State\r
-  * @{\r
-  */\r
-#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */\r
-#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Over_Sampling UART Over Sampling\r
-  * @{\r
-  */\r
-#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */\r
-#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method\r
-  * @{\r
-  */\r
-#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */\r
-#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(USART_PRESC_PRESCALER)\r
-/** @defgroup UART_ClockPrescaler  UART Clock Prescaler\r
-  * @{\r
-  */\r
-#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */\r
-#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */\r
-#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */\r
-#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */\r
-#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */\r
-#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */\r
-#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */\r
-#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */\r
-#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */\r
-#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */\r
-#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */\r
-#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* USART_PRESC_PRESCALER */\r
-/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection on start bit            */\r
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection on falling edge         */\r
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection on 0x7F frame detection */\r
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection on 0x55 frame detection */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut\r
-  * @{\r
-  */\r
-#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                 /*!< UART receiver timeout disable */\r
-#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN             /*!< UART receiver timeout enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_LIN    UART Local Interconnection Network mode\r
-  * @{\r
-  */\r
-#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */\r
-#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection\r
-  * @{\r
-  */\r
-#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */\r
-#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_DMA_Tx    UART DMA Tx\r
-  * @{\r
-  */\r
-#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */\r
-#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_DMA_Rx   UART DMA Rx\r
-  * @{\r
-  */\r
-#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */\r
-#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection\r
-  * @{\r
-  */\r
-#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */\r
-#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods\r
-  * @{\r
-  */\r
-#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */\r
-#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Request_Parameters UART Request Parameters\r
-  * @{\r
-  */\r
-#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */\r
-#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */\r
-#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */\r
-#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */\r
-#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */\r
-#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */\r
-#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */\r
-#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */\r
-#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */\r
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */\r
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */\r
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */\r
-#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */\r
-#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */\r
-#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */\r
-#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */\r
-#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */\r
-#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */\r
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */\r
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_MSB_First   UART Advanced Feature MSB First\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received first disable */\r
-#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received first enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */\r
-#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable\r
-  * @{\r
-  */\r
-#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */\r
-#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register\r
-  * @{\r
-  */\r
-#define UART_CR2_ADDRESS_LSB_POS             24U                                /*!< UART address-matching LSB position in CR2 register */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection\r
-  * @{\r
-  */\r
-#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                         */\r
-#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                       */\r
-#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity\r
-  * @{\r
-  */\r
-#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */\r
-#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register\r
-  * @{\r
-  */\r
-#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB position in CR1 register */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register\r
-  * @{\r
-  */\r
-#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB position in CR1 register */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask\r
-  * @{\r
-  */\r
-#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value\r
-  * @{\r
-  */\r
-#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Flags     UART Status Flags\r
-  *        Elements values convention: 0xXXXX\r
-  *           - 0xXXXX  : Flag mask in the ISR register\r
-  * @{\r
-  */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */\r
-#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */\r
-#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */\r
-#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */\r
-#endif /* USART_CR1_FIFOEN */\r
-#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */\r
-#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */\r
-#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */\r
-#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */\r
-#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */\r
-#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */\r
-#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */\r
-#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */\r
-#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */\r
-#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */\r
-#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */\r
-#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */\r
-#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */\r
-#else\r
-#define UART_FLAG_TXE                       USART_ISR_TXE           /*!< UART transmit data register empty         */\r
-#endif /* USART_CR1_FIFOEN */\r
-#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */\r
-#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */\r
-#else\r
-#define UART_FLAG_RXNE                      USART_ISR_RXNE          /*!< UART read data register not empty         */\r
-#endif /* USART_CR1_FIFOEN */\r
-#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */\r
-#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */\r
-#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */\r
-#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */\r
-#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Interrupt_definition   UART Interrupts Definition\r
-  *        Elements values convention: 000ZZZZZ0XXYYYYYb\r
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r
-  *           - XX  : Interrupt source register (2bits)\r
-  *                 - 01: CR1 register\r
-  *                 - 10: CR2 register\r
-  *                 - 11: CR3 register\r
-  *           - ZZZZZ  : Flag position in the ISR register(5bits)\r
-  *        Elements values convention: 000000000XXYYYYYb\r
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r
-  *           - XX  : Interrupt source register (2bits)\r
-  *                 - 01: CR1 register\r
-  *                 - 10: CR2 register\r
-  *                 - 11: CR3 register\r
-  *        Elements values convention: 0000ZZZZ00000000b\r
-  *           - ZZZZ  : Flag position in the ISR register(4bits)\r
-  * @{\r
-  */\r
-#define UART_IT_PE                          0x0028U                  /*!< UART parity error interruption                 */\r
-#define UART_IT_TXE                         0x0727U                  /*!< UART transmit data register empty interruption */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define UART_IT_TXFNF                       0x0727U                  /*!< UART TX FIFO not full interruption             */\r
-#endif /* USART_CR1_FIFOEN */\r
-#define UART_IT_TC                          0x0626U                  /*!< UART transmission complete interruption        */\r
-#define UART_IT_RXNE                        0x0525U                  /*!< UART read data register not empty interruption */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define UART_IT_RXFNE                       0x0525U                  /*!< UART RXFIFO not empty interruption             */\r
-#endif /* USART_CR1_FIFOEN */\r
-#define UART_IT_IDLE                        0x0424U                  /*!< UART idle interruption                         */\r
-#define UART_IT_LBD                         0x0846U                  /*!< UART LIN break detection interruption          */\r
-#define UART_IT_CTS                         0x096AU                  /*!< UART CTS interruption                          */\r
-#define UART_IT_CM                          0x112EU                  /*!< UART character match interruption              */\r
-#define UART_IT_WUF                         0x1476U                  /*!< UART wake-up from stop mode interruption       */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define UART_IT_RXFF                        0x183FU                  /*!< UART RXFIFO full interruption                  */\r
-#define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */\r
-#define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */\r
-#define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-#define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */\r
-\r
-#define UART_IT_ORE                         0x0300U                  /*!< UART overrun error interruption */\r
-#define UART_IT_NE                          0x0200U                  /*!< UART noise error interruption   */\r
-#define UART_IT_FE                          0x0100U                  /*!< UART frame error interruption   */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags\r
-  * @{\r
-  */\r
-#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */\r
-#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */\r
-#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */\r
-#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */\r
-#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */\r
-#endif /* USART_CR1_FIFOEN */\r
-#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */\r
-#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */\r
-#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */\r
-#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */\r
-#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup UART_Exported_Macros UART Exported Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Reset UART handle states.\r
-  * @param  __HANDLE__ UART handle.\r
-  * @retval None\r
-  */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\r
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\r
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\r
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \\r
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \\r
-                                                     } while(0U)\r
-#else\r
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\r
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\r
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\r
-                                                     } while(0U)\r
-#endif /*USE_HAL_UART_REGISTER_CALLBACKS */\r
-\r
-/** @brief  Flush the UART Data registers.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \\r
-  do{                \\r
-    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \\r
-    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \\r
-  }  while(0U)\r
-\r
-/** @brief  Clear the specified UART pending flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __FLAG__ specifies the flag to check.\r
-  *          This parameter can be any combination of the following values:\r
-  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag\r
-  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag\r
-  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag\r
-  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag\r
-  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag\r
-  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag\r
-  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag\r
-  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag\r
-  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag\r
-  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag\r
-  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r
-\r
-/** @brief  Clear the UART PE pending flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)\r
-\r
-/** @brief  Clear the UART FE pending flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)\r
-\r
-/** @brief  Clear the UART NE pending flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)\r
-\r
-/** @brief  Clear the UART ORE pending flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)\r
-\r
-/** @brief  Clear the UART IDLE pending flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/** @brief  Clear the UART TX FIFO empty clear flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/** @brief  Check whether the specified UART flag is set or not.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __FLAG__ specifies the flag to check.\r
-  *        This parameter can be one of the following values:\r
-  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag\r
-  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag\r
-  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag\r
-  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag\r
-  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag\r
-  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag\r
-  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag\r
-  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)\r
-  *            @arg @ref UART_FLAG_SBKF  Send Break flag\r
-  *            @arg @ref UART_FLAG_CMF   Character match flag\r
-  *            @arg @ref UART_FLAG_BUSY  Busy flag\r
-  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag\r
-  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag\r
-  *            @arg @ref UART_FLAG_CTS   CTS Change flag\r
-  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag\r
-  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag\r
-  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag\r
-  *            @arg @ref UART_FLAG_TC    Transmission Complete flag\r
-  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag\r
-  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag\r
-  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag\r
-  *            @arg @ref UART_FLAG_ORE   Overrun Error flag\r
-  *            @arg @ref UART_FLAG_NE    Noise Error flag\r
-  *            @arg @ref UART_FLAG_FE    Framing Error flag\r
-  *            @arg @ref UART_FLAG_PE    Parity Error flag\r
-  * @retval The new state of __FLAG__ (TRUE or FALSE).\r
-  */\r
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
-\r
-/** @brief  Enable the specified UART interrupt.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
-  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
-  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
-  *            @arg @ref UART_IT_CM    Character match interrupt\r
-  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
-  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
-  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
-  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
-  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
-                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
-\r
-\r
-/** @brief  Disable the specified UART interrupt.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
-  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
-  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
-  *            @arg @ref UART_IT_CM    Character match interrupt\r
-  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
-  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
-  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
-  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
-  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
-\r
-/** @brief  Check whether the specified UART interrupt has occurred or not.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __INTERRUPT__ specifies the UART interrupt to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
-  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
-  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
-  *            @arg @ref UART_IT_CM    Character match interrupt\r
-  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
-  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
-  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
-  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
-  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)\r
-  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
-  */\r
-#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\\r
-                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)\r
-\r
-/** @brief  Check whether the specified UART interrupt source is enabled or not.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __INTERRUPT__ specifies the UART interrupt source to check.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt\r
-  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt\r
-  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt\r
-  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt\r
-  *            @arg @ref UART_IT_CM    Character match interrupt\r
-  *            @arg @ref UART_IT_CTS   CTS change interrupt\r
-  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt\r
-  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt\r
-  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
-  *            @arg @ref UART_IT_TC    Transmission complete interrupt\r
-  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt\r
-  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
-  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt\r
-  *            @arg @ref UART_IT_PE    Parity Error interrupt\r
-  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)\r
-  * @retval The new state of __INTERRUPT__ (SET or RESET).\r
-  */\r
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \\r
-                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \\r
-                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)\r
-\r
-/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r
-  *                       to clear the corresponding interrupt\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag\r
-  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag\r
-  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag\r
-  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag\r
-  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag\r
-  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag\r
-  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag\r
-  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag\r
-  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag\r
-  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag\r
-  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))\r
-\r
-/** @brief  Set a specific UART request flag.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __REQ__ specifies the request flag to set\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request\r
-  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request\r
-  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request\r
-  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request\r
-  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))\r
-\r
-/** @brief  Enable the UART one bit sample method.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r
-\r
-/** @brief  Disable the UART one bit sample method.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)\r
-\r
-/** @brief  Enable UART.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
-\r
-/** @brief  Disable UART.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
-\r
-/** @brief  Enable CTS flow control.\r
-  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,\r
-  *         without need to call HAL_UART_Init() function.\r
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \\r
-  do{                                                      \\r
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \\r
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \\r
-  } while(0U)\r
-\r
-/** @brief  Disable CTS flow control.\r
-  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,\r
-  *         without need to call HAL_UART_Init() function.\r
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \\r
-  do{                                                       \\r
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \\r
-  } while(0U)\r
-\r
-/** @brief  Enable RTS flow control.\r
-  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,\r
-  *         without need to call HAL_UART_Init() function.\r
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \\r
-  do{                                                     \\r
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\r
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \\r
-  } while(0U)\r
-\r
-/** @brief  Disable RTS flow control.\r
-  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,\r
-  *         without need to call HAL_UART_Init() function.\r
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None\r
-  */\r
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \\r
-  do{                                                      \\r
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\r
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \\r
-  } while(0U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros --------------------------------------------------------*/\r
-/** @defgroup UART_Private_Macros   UART Private Macros\r
-  * @{\r
-  */\r
-#if defined(USART_PRESC_PRESCALER)\r
-/** @brief  Get UART clok division factor from clock prescaler value.\r
-  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
-  * @retval UART clock division factor\r
-  */\r
-#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \\r
-  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \\r
-   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)\r
-\r
-/** @brief  BRR division operation to set BRR register with LPUART.\r
-  * @param  __PCLK__ LPUART clock.\r
-  * @param  __BAUD__ Baud rate set by the user.\r
-  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
-  * @retval Division result\r
-  */\r
-#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\\r
-                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))\r
-\r
-/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.\r
-  * @param  __PCLK__ UART clock.\r
-  * @param  __BAUD__ Baud rate set by the user.\r
-  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
-  * @retval Division result\r
-  */\r
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\\r
-                                                                       + ((__BAUD__)/2U)) / (__BAUD__))\r
-\r
-/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.\r
-  * @param  __PCLK__ UART clock.\r
-  * @param  __BAUD__ Baud rate set by the user.\r
-  * @param  __CLOCKPRESCALER__ UART prescaler value.\r
-  * @retval Division result\r
-  */\r
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\\r
-                                                                       + ((__BAUD__)/2U)) / (__BAUD__))\r
-#else\r
-\r
-/** @brief  BRR division operation to set BRR register with LPUART.\r
-  * @param  __PCLK__ LPUART clock.\r
-  * @param  __BAUD__ Baud rate set by the user.\r
-  * @retval Division result\r
-  */\r
-#define UART_DIV_LPUART(__PCLK__, __BAUD__)      (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__))\r
-\r
-/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.\r
-  * @param  __PCLK__ UART clock.\r
-  * @param  __BAUD__ Baud rate set by the user.\r
-  * @retval Division result\r
-  */\r
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))\r
-\r
-/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.\r
-  * @param  __PCLK__ UART clock.\r
-  * @param  __BAUD__ Baud rate set by the user.\r
-  * @retval Division result\r
-  */\r
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))\r
-#endif /* USART_PRESC_PRESCALER */\r
-\r
-/** @brief  Check whether or not UART instance is Low Power UART.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)\r
-  */\r
-#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))\r
-\r
-/** @brief  Check UART Baud rate.\r
-  * @param  __BAUDRATE__ Baudrate specified by the user.\r
-  *         The maximum Baud Rate is derived from the maximum clock on L4\r
-  *         divided by the smallest oversampling used on the USART (i.e. 8)\r
-  *          (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise)\r
-  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)\r
-  */\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U)\r
-#else\r
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U)\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/** @brief  Check UART assertion time.\r
-  * @param  __TIME__ 5-bit value assertion time.\r
-  * @retval Test result (TRUE or FALSE).\r
-  */\r
-#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)\r
-\r
-/** @brief  Check UART deassertion time.\r
-  * @param  __TIME__ 5-bit value deassertion time.\r
-  * @retval Test result (TRUE or FALSE).\r
-  */\r
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)\r
-\r
-/**\r
-  * @brief Ensure that UART frame number of stop bits is valid.\r
-  * @param __STOPBITS__ UART frame number of stop bits.\r
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)\r
-  */\r
-#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \\r
-                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \\r
-                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \\r
-                                        ((__STOPBITS__) == UART_STOPBITS_2))\r
-\r
-/**\r
-  * @brief Ensure that LPUART frame number of stop bits is valid.\r
-  * @param __STOPBITS__ LPUART frame number of stop bits.\r
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)\r
-  */\r
-#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \\r
-                                          ((__STOPBITS__) == UART_STOPBITS_2))\r
-\r
-/**\r
-  * @brief Ensure that UART frame parity is valid.\r
-  * @param __PARITY__ UART frame parity.\r
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)\r
-  */\r
-#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \\r
-                                    ((__PARITY__) == UART_PARITY_EVEN) || \\r
-                                    ((__PARITY__) == UART_PARITY_ODD))\r
-\r
-/**\r
-  * @brief Ensure that UART hardware flow control is valid.\r
-  * @param __CONTROL__ UART hardware flow control.\r
-  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)\r
-  */\r
-#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\\r
-  (((__CONTROL__) == UART_HWCONTROL_NONE) || \\r
-   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \\r
-   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \\r
-   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))\r
-\r
-/**\r
-  * @brief Ensure that UART communication mode is valid.\r
-  * @param __MODE__ UART communication mode.\r
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
-  */\r
-#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))\r
-\r
-/**\r
-  * @brief Ensure that UART state is valid.\r
-  * @param __STATE__ UART state.\r
-  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)\r
-  */\r
-#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \\r
-                                  ((__STATE__) == UART_STATE_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART oversampling is valid.\r
-  * @param __SAMPLING__ UART oversampling.\r
-  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)\r
-  */\r
-#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \\r
-                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))\r
-\r
-/**\r
-  * @brief Ensure that UART frame sampling is valid.\r
-  * @param __ONEBIT__ UART frame sampling.\r
-  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)\r
-  */\r
-#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \\r
-                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART auto Baud rate detection mode is valid.\r
-  * @param __MODE__ UART auto Baud rate detection mode.\r
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \\r
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \\r
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \\r
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))\r
-\r
-/**\r
-  * @brief Ensure that UART receiver timeout setting is valid.\r
-  * @param __TIMEOUT__ UART receiver timeout setting.\r
-  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)\r
-  */\r
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \\r
-                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART LIN state is valid.\r
-  * @param __LIN__ UART LIN state.\r
-  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)\r
-  */\r
-#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \\r
-                                     ((__LIN__) == UART_LIN_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART LIN break detection length is valid.\r
-  * @param __LENGTH__ UART LIN break detection length.\r
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)\r
-  */\r
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \\r
-                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))\r
-\r
-/**\r
-  * @brief Ensure that UART DMA TX state is valid.\r
-  * @param __DMATX__ UART DMA TX state.\r
-  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)\r
-  */\r
-#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \\r
-                                       ((__DMATX__) == UART_DMA_TX_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART DMA RX state is valid.\r
-  * @param __DMARX__ UART DMA RX state.\r
-  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)\r
-  */\r
-#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \\r
-                                       ((__DMARX__) == UART_DMA_RX_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART half-duplex state is valid.\r
-  * @param __HDSEL__ UART half-duplex state.\r
-  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)\r
-  */\r
-#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \\r
-                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART wake-up method is valid.\r
-  * @param __WAKEUP__ UART wake-up method .\r
-  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)\r
-  */\r
-#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \\r
-                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))\r
-\r
-/**\r
-  * @brief Ensure that UART request parameter is valid.\r
-  * @param __PARAM__ UART request parameter.\r
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)\r
-  */\r
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \\r
-                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \\r
-                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \\r
-                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \\r
-                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))\r
-\r
-/**\r
-  * @brief Ensure that UART advanced features initialization is valid.\r
-  * @param __INIT__ UART advanced features initialization.\r
-  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \\r
-                                                            UART_ADVFEATURE_TXINVERT_INIT          | \\r
-                                                            UART_ADVFEATURE_RXINVERT_INIT          | \\r
-                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \\r
-                                                            UART_ADVFEATURE_SWAP_INIT              | \\r
-                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \\r
-                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \\r
-                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \\r
-                                                            UART_ADVFEATURE_MSBFIRST_INIT))\r
-\r
-/**\r
-  * @brief Ensure that UART frame TX inversion setting is valid.\r
-  * @param __TXINV__ UART frame TX inversion setting.\r
-  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \\r
-                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART frame RX inversion setting is valid.\r
-  * @param __RXINV__ UART frame RX inversion setting.\r
-  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \\r
-                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART frame data inversion setting is valid.\r
-  * @param __DATAINV__ UART frame data inversion setting.\r
-  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \\r
-                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART frame RX/TX pins swap setting is valid.\r
-  * @param __SWAP__ UART frame RX/TX pins swap setting.\r
-  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \\r
-                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART frame overrun setting is valid.\r
-  * @param __OVERRUN__ UART frame overrun setting.\r
-  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)\r
-  */\r
-#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \\r
-                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART auto Baud rate state is valid.\r
-  * @param __AUTOBAUDRATE__ UART auto Baud rate state.\r
-  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \\r
-                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.\r
-  * @param __DMA__ UART DMA enabling or disabling on error setting.\r
-  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \\r
-                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))\r
-\r
-/**\r
-  * @brief Ensure that UART frame MSB first setting is valid.\r
-  * @param __MSBFIRST__ UART frame MSB first setting.\r
-  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \\r
-                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART stop mode state is valid.\r
-  * @param __STOPMODE__ UART stop mode state.\r
-  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)\r
-  */\r
-#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \\r
-                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART mute mode state is valid.\r
-  * @param __MUTE__ UART mute mode state.\r
-  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)\r
-  */\r
-#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \\r
-                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))\r
-\r
-/**\r
-  * @brief Ensure that UART wake-up selection is valid.\r
-  * @param __WAKE__ UART wake-up selection.\r
-  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)\r
-  */\r
-#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \\r
-                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \\r
-                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))\r
-\r
-/**\r
-  * @brief Ensure that UART driver enable polarity is valid.\r
-  * @param __POLARITY__ UART driver enable polarity.\r
-  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)\r
-  */\r
-#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \\r
-                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))\r
-\r
-#if defined(USART_PRESC_PRESCALER)\r
-/**\r
-  * @brief Ensure that UART Prescaler is valid.\r
-  * @param __CLOCKPRESCALER__ UART Prescaler value.\r
-  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)\r
-  */\r
-#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \\r
-                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))\r
-#endif /* USART_PRESC_PRESCALER */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Include UART HAL Extended module */\r
-#include "stm32l4xx_hal_uart_ex.h"\r
-\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup UART_Exported_Functions UART Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  * @{\r
-  */\r
-\r
-/* Initialization and de-initialization functions  ****************************/\r
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);\r
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);\r
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r
-\r
-/* Callbacks Register/UnRegister functions  ***********************************/\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,\r
-                                            pUART_CallbackTypeDef pCallback);\r
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r
-  * @{\r
-  */\r
-\r
-/* IO operation functions *****************************************************/\r
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r
-/* Transfer Abort functions */\r
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);\r
-\r
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r
-void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);\r
-void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);\r
-void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions\r
-  * @{\r
-  */\r
-\r
-/* Peripheral Control functions  ************************************************/\r
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);\r
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
-  * @{\r
-  */\r
-\r
-/* Peripheral State and Errors functions  **************************************************/\r
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions -----------------------------------------------------------*/\r
-/** @addtogroup UART_Private_Functions UART Private Functions\r
-  * @{\r
-  */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,\r
-                                              uint32_t Tickstart, uint32_t Timeout);\r
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_UART_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h
deleted file mode 100644 (file)
index b9835b5..0000000
+++ /dev/null
@@ -1,734 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_uart_ex.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of UART HAL Extended module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_UART_EX_H\r
-#define STM32L4xx_HAL_UART_EX_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup UARTEx\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup UARTEx_Exported_Types UARTEx Exported Types\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  UART wake up from stop mode parameters\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).\r
-                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.\r
-                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must\r
-                                    be filled up. */\r
-\r
-  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.\r
-                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */\r
-\r
-  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */\r
-} UART_WakeUpTypeDef;\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants\r
-  * @{\r
-  */\r
-\r
-/** @defgroup UARTEx_Word_Length UARTEx Word Length\r
-  * @{\r
-  */\r
-#define UART_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long UART frame */\r
-#define UART_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long UART frame */\r
-#define UART_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long UART frame */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length\r
-  * @{\r
-  */\r
-#define UART_ADDRESS_DETECT_4B              0x00000000U      /*!< 4-bit long wake-up address */\r
-#define UART_ADDRESS_DETECT_7B              USART_CR2_ADDM7  /*!< 7-bit long wake-up address */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode\r
-  * @brief    UART FIFO mode\r
-  * @{\r
-  */\r
-#define UART_FIFOMODE_DISABLE        0x00000000U       /*!< FIFO mode disable */\r
-#define UART_FIFOMODE_ENABLE         USART_CR1_FIFOEN  /*!< FIFO mode enable  */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level\r
-  * @brief    UART TXFIFO threshold level\r
-  * @{\r
-  */\r
-#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */\r
-#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */\r
-#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */\r
-#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */\r
-#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */\r
-#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level\r
-  * @brief    UART RXFIFO threshold level\r
-  * @{\r
-  */\r
-#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */\r
-#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */\r
-#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */\r
-#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */\r
-#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */\r
-#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */\r
-/**\r
-  * @}\r
-  */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup UARTEx_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup UARTEx_Exported_Functions_Group1\r
-  * @{\r
-  */\r
-\r
-/* Initialization and de-initialization functions  ****************************/\r
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,\r
-                                   uint32_t DeassertionTime);\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup UARTEx_Exported_Functions_Group2\r
-  * @{\r
-  */\r
-\r
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);\r
-void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup UARTEx_Exported_Functions_Group3\r
-  * @{\r
-  */\r
-\r
-/* Peripheral Control functions  **********************************************/\r
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);\r
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);\r
-#if defined(USART_CR3_UCESM)\r
-HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);\r
-#endif /* USART_CR3_UCESM */\r
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r
-#if defined(USART_CR1_FIFOEN)\r
-HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);\r
-HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);\r
-HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup UARTEx_Private_Macros UARTEx Private Macros\r
-  * @{\r
-  */\r
-\r
-/** @brief  Report the UART clock source.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @param  __CLOCKSOURCE__ output variable.\r
-  * @retval UART clocking source, written in __CLOCKSOURCE__.\r
-  */\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \\r
-    || defined (STM32L496xx) || defined (STM32L4A6xx) \\r
-    || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
-  do {                                                        \\r
-    if((__HANDLE__)->Instance == USART1)                      \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == USART2)                 \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == USART3)                 \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART3_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART3CLKSOURCE_PCLK1:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == UART4)                  \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_UART4_SOURCE())                    \\r
-      {                                                       \\r
-        case RCC_UART4CLKSOURCE_PCLK1:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_UART4CLKSOURCE_HSI:                          \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_UART4CLKSOURCE_SYSCLK:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_UART4CLKSOURCE_LSE:                          \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == UART5)                  \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_UART5_SOURCE())                    \\r
-      {                                                       \\r
-        case RCC_UART5CLKSOURCE_PCLK1:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_UART5CLKSOURCE_HSI:                          \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_UART5CLKSOURCE_SYSCLK:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_UART5CLKSOURCE_LSE:                          \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == LPUART1)                \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
-      {                                                       \\r
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else                                                      \\r
-    {                                                         \\r
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
-    }                                                         \\r
-  } while(0U)\r
-#elif defined (STM32L412xx) || defined (STM32L422xx) \\r
-   || defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)\r
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
-  do {                                                        \\r
-    if((__HANDLE__)->Instance == USART1)                      \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == USART2)                 \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == USART3)                 \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART3_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART3CLKSOURCE_PCLK1:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == LPUART1)                \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
-      {                                                       \\r
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else                                                      \\r
-    {                                                         \\r
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
-    }                                                         \\r
-  } while(0U)\r
-#elif defined (STM32L432xx) || defined (STM32L442xx)\r
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
-  do {                                                        \\r
-    if((__HANDLE__)->Instance == USART1)                      \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == USART2)                 \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == LPUART1)                \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
-      {                                                       \\r
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else                                                      \\r
-    {                                                         \\r
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
-    }                                                         \\r
-  } while(0U)\r
-#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\r
-  do {                                                        \\r
-    if((__HANDLE__)->Instance == USART1)                      \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART1_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART1CLKSOURCE_PCLK2:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART1CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == USART2)                 \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART2_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART2CLKSOURCE_PCLK1:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART2CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == USART3)                 \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_USART3_SOURCE())                   \\r
-      {                                                       \\r
-        case RCC_USART3CLKSOURCE_PCLK1:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_HSI:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_SYSCLK:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_USART3CLKSOURCE_LSE:                         \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == UART4)                  \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_UART4_SOURCE())                    \\r
-      {                                                       \\r
-        case RCC_UART4CLKSOURCE_PCLK1:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_UART4CLKSOURCE_HSI:                          \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_UART4CLKSOURCE_SYSCLK:                       \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_UART4CLKSOURCE_LSE:                          \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else if((__HANDLE__)->Instance == LPUART1)                \\r
-    {                                                         \\r
-      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \\r
-      {                                                       \\r
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_HSI:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\r
-          break;                                              \\r
-        case RCC_LPUART1CLKSOURCE_LSE:                        \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\r
-          break;                                              \\r
-        default:                                              \\r
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \\r
-          break;                                              \\r
-      }                                                       \\r
-    }                                                         \\r
-    else                                                      \\r
-    {                                                         \\r
-      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \\r
-    }                                                         \\r
-  } while(0U)\r
-#endif /* STM32L471xx ||  STM32L475xx ||  STM32L476xx ||  STM32L485xx ||  STM32L486xx ||\r
-        * STM32L496xx ||  STM32L4A6xx ||\r
-        * STM32L4R5xx ||  STM32L4R7xx ||  STM32L4R9xx ||  STM32L4S5xx ||  STM32L4S7xx ||  STM32L4S9xx\r
-        */\r
-\r
-/** @brief  Report the UART mask to apply to retrieve the received data\r
-  *         according to the word length and to the parity bits activation.\r
-  * @note   If PCE = 1, the parity bit is not included in the data extracted\r
-  *         by the reception API().\r
-  *         This masking operation is not carried out in the case of\r
-  *         DMA transfers.\r
-  * @param  __HANDLE__ specifies the UART Handle.\r
-  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.\r
-  */\r
-#define UART_MASK_COMPUTATION(__HANDLE__)                             \\r
-  do {                                                                \\r
-    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \\r
-    {                                                                 \\r
-      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \\r
-      {                                                               \\r
-        (__HANDLE__)->Mask = 0x01FFU ;                                \\r
-      }                                                               \\r
-      else                                                            \\r
-      {                                                               \\r
-        (__HANDLE__)->Mask = 0x00FFU ;                                \\r
-      }                                                               \\r
-    }                                                                 \\r
-    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \\r
-    {                                                                 \\r
-      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \\r
-      {                                                               \\r
-        (__HANDLE__)->Mask = 0x00FFU ;                                \\r
-      }                                                               \\r
-      else                                                            \\r
-      {                                                               \\r
-        (__HANDLE__)->Mask = 0x007FU ;                                \\r
-      }                                                               \\r
-    }                                                                 \\r
-    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \\r
-    {                                                                 \\r
-      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \\r
-      {                                                               \\r
-        (__HANDLE__)->Mask = 0x007FU ;                                \\r
-      }                                                               \\r
-      else                                                            \\r
-      {                                                               \\r
-        (__HANDLE__)->Mask = 0x003FU ;                                \\r
-      }                                                               \\r
-    }                                                                 \\r
-    else                                                              \\r
-    {                                                                 \\r
-      (__HANDLE__)->Mask = 0x0000U;                                   \\r
-    }                                                                 \\r
-  } while(0U)\r
-\r
-/**\r
-  * @brief Ensure that UART frame length is valid.\r
-  * @param __LENGTH__ UART frame length.\r
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)\r
-  */\r
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \\r
-                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \\r
-                                         ((__LENGTH__) == UART_WORDLENGTH_9B))\r
-\r
-/**\r
-  * @brief Ensure that UART wake-up address length is valid.\r
-  * @param __ADDRESS__ UART wake-up address length.\r
-  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)\r
-  */\r
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \\r
-                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/**\r
-  * @brief Ensure that UART TXFIFO threshold level is valid.\r
-  * @param __THRESHOLD__ UART TXFIFO threshold level.\r
-  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
-  */\r
-#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \\r
-                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \\r
-                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \\r
-                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \\r
-                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \\r
-                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))\r
-\r
-/**\r
-  * @brief Ensure that UART RXFIFO threshold level is valid.\r
-  * @param __THRESHOLD__ UART RXFIFO threshold level.\r
-  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
-  */\r
-#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \\r
-                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \\r
-                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \\r
-                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \\r
-                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \\r
-                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_UART_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h
deleted file mode 100644 (file)
index ac9c7bd..0000000
+++ /dev/null
@@ -1,652 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_ll_usb.h\r
-  * @author  MCD Application Team\r
-  * @brief   Header file of USB Low Layer HAL module.\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_LL_USB_H\r
-#define STM32L4xx_LL_USB_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-#if defined (USB) || defined (USB_OTG_FS)\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup USB_LL\r
-  * @{\r
-  */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/**\r
-  * @brief  USB Mode definition\r
-  */\r
-#if defined (USB_OTG_FS)\r
-\r
-typedef enum\r
-{\r
-  USB_DEVICE_MODE  = 0,\r
-  USB_HOST_MODE    = 1,\r
-  USB_DRD_MODE     = 2\r
-} USB_ModeTypeDef;\r
-\r
-/**\r
-  * @brief  URB States definition\r
-  */\r
-typedef enum\r
-{\r
-  URB_IDLE = 0,\r
-  URB_DONE,\r
-  URB_NOTREADY,\r
-  URB_NYET,\r
-  URB_ERROR,\r
-  URB_STALL\r
-} USB_OTG_URBStateTypeDef;\r
-\r
-/**\r
-  * @brief  Host channel States  definition\r
-  */\r
-typedef enum\r
-{\r
-  HC_IDLE = 0,\r
-  HC_XFRC,\r
-  HC_HALTED,\r
-  HC_NAK,\r
-  HC_NYET,\r
-  HC_STALL,\r
-  HC_XACTERR,\r
-  HC_BBLERR,\r
-  HC_DATATGLERR\r
-} USB_OTG_HCStateTypeDef;\r
-\r
-/**\r
-  * @brief  USB OTG Initialization Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t dev_endpoints;           /*!< Device Endpoints number.\r
-                                         This parameter depends on the used USB core.\r
-                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r
-\r
-  uint32_t Host_channels;           /*!< Host Channels number.\r
-                                         This parameter Depends on the used USB core.\r
-                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r
-\r
-  uint32_t speed;                   /*!< USB Core speed.\r
-                                         This parameter can be any value of @ref USB_Core_Speed_                */\r
-\r
-  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */\r
-\r
-  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */\r
-\r
-  uint32_t phy_itface;              /*!< Select the used PHY interface.\r
-                                         This parameter can be any value of @ref USB_Core_PHY_                  */\r
-\r
-  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */\r
-\r
-  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */\r
-\r
-  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */\r
-\r
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */\r
-\r
-  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */\r
-\r
-  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */\r
-\r
-  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */\r
-} USB_OTG_CfgTypeDef;\r
-\r
-typedef struct\r
-{\r
-  uint8_t   num;                  /*!< Endpoint number\r
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\r
-\r
-  uint8_t   is_in;                /*!< Endpoint direction\r
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
-\r
-  uint8_t   is_stall;             /*!< Endpoint stall condition\r
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
-\r
-  uint8_t   type;                 /*!< Endpoint type\r
-                                       This parameter can be any value of @ref USB_EP_Type_                     */\r
-\r
-  uint8_t   data_pid_start;       /*!< Initial data PID\r
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
-\r
-  uint8_t   even_odd_frame;       /*!< IFrame parity\r
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r
-\r
-  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number\r
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\r
-\r
-  uint32_t  maxpacket;            /*!< Endpoint Max packet size\r
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */\r
-\r
-  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */\r
-\r
-  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */\r
-\r
-  uint32_t  xfer_len;             /*!< Current transfer length                                                  */\r
-\r
-  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */\r
-} USB_OTG_EPTypeDef;\r
-\r
-typedef struct\r
-{\r
-  uint8_t   dev_addr ;          /*!< USB device address.\r
-                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */\r
-\r
-  uint8_t   ch_num;             /*!< Host channel number.\r
-                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\r
-\r
-  uint8_t   ep_num;             /*!< Endpoint number.\r
-                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\r
-\r
-  uint8_t   ep_is_in;           /*!< Endpoint direction\r
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
-\r
-  uint8_t   speed;              /*!< USB Host speed.\r
-                                     This parameter can be any value of @ref USB_Core_Speed_                    */\r
-\r
-  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */\r
-\r
-  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */\r
-\r
-  uint8_t   ep_type;            /*!< Endpoint Type.\r
-                                     This parameter can be any value of @ref USB_EP_Type_                       */\r
-\r
-  uint16_t  max_packet;         /*!< Endpoint Max packet size.\r
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */\r
-\r
-  uint8_t   data_pid;           /*!< Initial data PID.\r
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
-\r
-  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */\r
-\r
-  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */\r
-\r
-  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */\r
-\r
-  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.\r
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
-\r
-  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag\r
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r
-\r
-  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */\r
-\r
-  uint32_t  ErrCnt;             /*!< Host channel error count.*/\r
-\r
-  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.\r
-                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */\r
-\r
-  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.\r
-                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef   */\r
-} USB_OTG_HCTypeDef;\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-\r
-typedef enum\r
-{\r
-  USB_DEVICE_MODE  = 0\r
-} USB_ModeTypeDef;\r
-\r
-/**\r
-  * @brief  USB Initialization Structure definition\r
-  */\r
-typedef struct\r
-{\r
-  uint32_t dev_endpoints;           /*!< Device Endpoints number.\r
-                                         This parameter depends on the used USB core.\r
-                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r
-\r
-  uint32_t speed;                   /*!< USB Core speed.\r
-                                         This parameter can be any value of @ref USB_Core_Speed                 */\r
-\r
-  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */\r
-\r
-  uint32_t phy_itface;              /*!< Select the used PHY interface.\r
-                                         This parameter can be any value of @ref USB_Core_PHY                   */\r
-\r
-  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */\r
-\r
-  uint32_t low_power_enable;        /*!< Enable or disable Low Power mode                                       */\r
-\r
-  uint32_t lpm_enable;              /*!< Enable or disable Battery charging.                                    */\r
-\r
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */\r
-} USB_CfgTypeDef;\r
-\r
-typedef struct\r
-{\r
-  uint8_t   num;             /*!< Endpoint number\r
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 15    */\r
-\r
-  uint8_t   is_in;           /*!< Endpoint direction\r
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r
-\r
-  uint8_t   is_stall;        /*!< Endpoint stall condition\r
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r
-\r
-  uint8_t   type;            /*!< Endpoint type\r
-                                  This parameter can be any value of @ref USB_EP_Type                       */\r
-\r
-  uint8_t   data_pid_start;  /*!< Initial data PID\r
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r
-\r
-  uint16_t  pmaadress;       /*!< PMA Address\r
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */\r
-\r
-  uint16_t  pmaaddr0;        /*!< PMA Address0\r
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */\r
-\r
-  uint16_t  pmaaddr1;        /*!< PMA Address1\r
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */\r
-\r
-  uint8_t   doublebuffer;    /*!< Double buffer enable\r
-                                  This parameter can be 0 or 1                                              */\r
-\r
-  uint16_t  tx_fifo_num;     /*!< This parameter is not required by USB Device FS peripheral, it is used\r
-                                  only by USB OTG FS peripheral\r
-                                  This parameter is added to ensure compatibility across USB peripherals    */\r
-\r
-  uint32_t  maxpacket;       /*!< Endpoint Max packet size\r
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 64KB  */\r
-\r
-  uint8_t   *xfer_buff;      /*!< Pointer to transfer buffer                                                */\r
-\r
-  uint32_t  xfer_len;        /*!< Current transfer length                                                   */\r
-\r
-  uint32_t  xfer_count;      /*!< Partial transfer length in case of multi packet transfer                  */\r
-\r
-} USB_EPTypeDef;\r
-#endif /* defined (USB) */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup PCD_Exported_Constants PCD Exported Constants\r
-  * @{\r
-  */\r
-\r
-#if defined (USB_OTG_FS)\r
-/** @defgroup USB_OTG_CORE VERSION ID\r
-  * @{\r
-  */\r
-#define USB_OTG_CORE_ID_300A          0x4F54300AU\r
-#define USB_OTG_CORE_ID_310A          0x4F54310AU\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_Core_Mode_ USB Core Mode\r
-  * @{\r
-  */\r
-#define USB_OTG_MODE_DEVICE                    0U\r
-#define USB_OTG_MODE_HOST                      1U\r
-#define USB_OTG_MODE_DRD                       2U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL Device Speed\r
-  * @{\r
-  */\r
-#define USBD_FS_SPEED               2U\r
-#define USBH_FS_SPEED               1U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed\r
-  * @{\r
-  */\r
-#define USB_OTG_SPEED_FULL                     3U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY\r
-  * @{\r
-  */\r
-#define USB_OTG_ULPI_PHY                       1U\r
-#define USB_OTG_EMBEDDED_PHY                   2U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value\r
-  * @{\r
-  */\r
-#ifndef USBD_FS_TRDT_VALUE\r
-#define USBD_FS_TRDT_VALUE           5U\r
-#define USBD_DEFAULT_TRDT_VALUE      9U\r
-#endif /* USBD_HS_TRDT_VALUE */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS\r
-  * @{\r
-  */\r
-#define USB_OTG_FS_MAX_PACKET_SIZE             64U\r
-#define USB_OTG_MAX_EP0_SIZE                   64U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency\r
-  * @{\r
-  */\r
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)\r
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)\r
-#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2U << 1)\r
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval\r
-  * @{\r
-  */\r
-#define DCFG_FRAME_INTERVAL_80                 0U\r
-#define DCFG_FRAME_INTERVAL_85                 1U\r
-#define DCFG_FRAME_INTERVAL_90                 2U\r
-#define DCFG_FRAME_INTERVAL_95                 3U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS\r
-  * @{\r
-  */\r
-#define DEP0CTL_MPS_64                         0U\r
-#define DEP0CTL_MPS_32                         1U\r
-#define DEP0CTL_MPS_16                         2U\r
-#define DEP0CTL_MPS_8                          3U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed\r
-  * @{\r
-  */\r
-#define EP_SPEED_LOW                           0U\r
-#define EP_SPEED_FULL                          1U\r
-#define EP_SPEED_HIGH                          2U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type\r
-  * @{\r
-  */\r
-#define EP_TYPE_CTRL                           0U\r
-#define EP_TYPE_ISOC                           1U\r
-#define EP_TYPE_BULK                           2U\r
-#define EP_TYPE_INTR                           3U\r
-#define EP_TYPE_MSK                            3U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines\r
-  * @{\r
-  */\r
-#define STS_GOUT_NAK                           1U\r
-#define STS_DATA_UPDT                          2U\r
-#define STS_XFER_COMP                          3U\r
-#define STS_SETUP_COMP                         4U\r
-#define STS_SETUP_UPDT                         6U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines\r
-  * @{\r
-  */\r
-#define HCFG_30_60_MHZ                         0U\r
-#define HCFG_48_MHZ                            1U\r
-#define HCFG_6_MHZ                             2U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines\r
-  * @{\r
-  */\r
-#define HPRT0_PRTSPD_HIGH_SPEED                0U\r
-#define HPRT0_PRTSPD_FULL_SPEED                1U\r
-#define HPRT0_PRTSPD_LOW_SPEED                 2U\r
-/**\r
-  * @}\r
-  */\r
-\r
-#define HCCHAR_CTRL                            0U\r
-#define HCCHAR_ISOC                            1U\r
-#define HCCHAR_BULK                            2U\r
-#define HCCHAR_INTR                            3U\r
-\r
-#define HC_PID_DATA0                           0U\r
-#define HC_PID_DATA2                           1U\r
-#define HC_PID_DATA1                           2U\r
-#define HC_PID_SETUP                           3U\r
-\r
-#define GRXSTS_PKTSTS_IN                       2U\r
-#define GRXSTS_PKTSTS_IN_XFER_COMP             3U\r
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U\r
-#define GRXSTS_PKTSTS_CH_HALTED                7U\r
-\r
-#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)\r
-#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)\r
-\r
-#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))\r
-#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\r
-#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\r
-#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))\r
-\r
-#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))\r
-#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS\r
-  * @{\r
-  */\r
-#define DEP0CTL_MPS_64                         0U\r
-#define DEP0CTL_MPS_32                         1U\r
-#define DEP0CTL_MPS_16                         2U\r
-#define DEP0CTL_MPS_8                          3U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type\r
-  * @{\r
-  */\r
-#define EP_TYPE_CTRL                           0U\r
-#define EP_TYPE_ISOC                           1U\r
-#define EP_TYPE_BULK                           2U\r
-#define EP_TYPE_INTR                           3U\r
-#define EP_TYPE_MSK                            3U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup USB_LL Device Speed\r
-  * @{\r
-  */\r
-#define USBD_FS_SPEED                          2U\r
-/**\r
-  * @}\r
-  */\r
-\r
-#define BTABLE_ADDRESS                         0x000U\r
-#define PMA_ACCESS                             1U\r
-#endif /* defined (USB) */\r
-#if defined (USB_OTG_FS)\r
-#define EP_ADDR_MSK                            0xFU\r
-#endif /* defined (USB_OTG_FS) */\r
-#if defined (USB)\r
-#define EP_ADDR_MSK                            0x7U\r
-#endif /* defined (USB) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros\r
-  * @{\r
-  */\r
-#if defined (USB_OTG_FS)\r
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))\r
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))\r
-\r
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))\r
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))\r
-#endif /* defined (USB_OTG_FS) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions\r
-  * @{\r
-  */\r
-#if defined (USB_OTG_FS)\r
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);\r
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode);\r
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);\r
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);\r
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);\r
-void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);\r
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);\r
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);\r
-uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);\r
-uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);\r
-uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);\r
-uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);\r
-uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);\r
-uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);\r
-uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);\r
-void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);\r
-\r
-HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);\r
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);\r
-uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);\r
-uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,\r
-                              uint8_t ch_num,\r
-                              uint8_t epnum,\r
-                              uint8_t dev_address,\r
-                              uint8_t speed,\r
-                              uint8_t ep_type,\r
-                              uint16_t mps);\r
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);\r
-uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);\r
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);\r
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\r
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);\r
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);\r
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);\r
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);\r
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);\r
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);\r
-HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);\r
-HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);\r
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);\r
-void             *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);\r
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);\r
-HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);\r
-HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);\r
-HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);\r
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);\r
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);\r
-uint32_t          USB_ReadInterrupts(USB_TypeDef *USBx);\r
-uint32_t          USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);\r
-uint32_t          USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);\r
-uint32_t          USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);\r
-uint32_t          USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);\r
-void              USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);\r
-\r
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);\r
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);\r
-void USB_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);\r
-void USB_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);\r
-#endif /* defined (USB) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* defined (USB) || defined (USB_OTG_FS) */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* STM32L4xx_LL_USB_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
deleted file mode 100644 (file)
index 1f8e5c5..0000000
+++ /dev/null
@@ -1,758 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal.c\r
-  * @author  MCD Application Team\r
-  * @brief   HAL module driver.\r
-  *          This is the common part of the HAL initialization\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                     ##### How to use this driver #####\r
-  ==============================================================================\r
-    [..]\r
-    The common HAL driver contains a set of generic and common APIs that can be\r
-    used by the PPP peripheral drivers and the user to start using the HAL.\r
-    [..]\r
-    The HAL contains two APIs' categories:\r
-         (+) Common HAL APIs\r
-         (+) Services HAL APIs\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup HAL HAL\r
-  * @brief HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/**\r
- * @brief STM32L4xx HAL Driver version number\r
-   */\r
-#define STM32L4XX_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */\r
-#define STM32L4XX_HAL_VERSION_SUB1   (0x0AU) /*!< [23:16] sub1 version */\r
-#define STM32L4XX_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */\r
-#define STM32L4XX_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\r
-#define STM32L4XX_HAL_VERSION        ((STM32L4XX_HAL_VERSION_MAIN  << 24U)\\r
-                                      |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\\r
-                                      |(STM32L4XX_HAL_VERSION_SUB2 << 8U)\\r
-                                      |(STM32L4XX_HAL_VERSION_RC))\r
-\r
-#if defined(VREFBUF)\r
-#define VREFBUF_TIMEOUT_VALUE     10U   /* 10 ms (to be confirmed) */\r
-#endif /* VREFBUF */\r
-\r
-/* ------------ SYSCFG registers bit address in the alias region ------------ */\r
-#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)\r
-/* ---  MEMRMP Register ---*/\r
-/* Alias word address of FB_MODE bit */\r
-#define MEMRMP_OFFSET             SYSCFG_OFFSET\r
-#define FB_MODE_BitNumber         8U\r
-#define FB_MODE_BB                (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U))\r
-\r
-/* --- SCSR Register ---*/\r
-/* Alias word address of SRAM2ER bit */\r
-#define SCSR_OFFSET               (SYSCFG_OFFSET + 0x18U)\r
-#define BRER_BitNumber            0U\r
-#define SCSR_SRAM2ER_BB           (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U))\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-\r
-/* Exported variables --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Exported_Variables HAL Exported Variables\r
-  * @{\r
-  */\r
-__IO uint32_t uwTick;\r
-uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */\r
-uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Exported_Functions HAL Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions\r
- *  @brief    Initialization and de-initialization functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-              ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Initialize the Flash interface, the NVIC allocation and initial time base\r
-          clock configuration.\r
-      (+) De-initialize common part of the HAL.\r
-      (+) Configure the time base source to have 1ms time base with a dedicated\r
-          Tick interrupt priority.\r
-        (++) SysTick timer is used by default as source of time base, but user\r
-             can eventually implement his proper time base source (a general purpose\r
-             timer for example or other time source), keeping in mind that Time base\r
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and\r
-             handled in milliseconds basis.\r
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically\r
-             at the beginning of the program after reset by HAL_Init() or at any time\r
-             when clock is configured, by HAL_RCC_ClockConfig().\r
-        (++) Source of time base is configured  to generate interrupts at regular\r
-             time intervals. Care must be taken if HAL_Delay() is called from a\r
-             peripheral ISR process, the Tick interrupt line must have higher priority\r
-            (numerically lower) than the peripheral interrupt. Otherwise the caller\r
-            ISR process will be blocked.\r
-       (++) functions affecting time base configurations are declared as __weak\r
-             to make  override possible  in case of other  implementations in user file.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Configure the Flash prefetch, the Instruction and Data caches,\r
-  *         the time base source, NVIC and any required global low level hardware\r
-  *         by calling the HAL_MspInit() callback function to be optionally defined in user file\r
-  *         stm32l4xx_hal_msp.c.\r
-  *\r
-  * @note   HAL_Init() function is called at the beginning of program after reset and before\r
-  *         the clock configuration.\r
-  *\r
-  * @note   In the default implementation the System Timer (Systick) is used as source of time base.\r
-  *         The Systick configuration is based on MSI clock, as MSI is the clock\r
-  *         used after a system Reset and the NVIC configuration is set to Priority group 4.\r
-  *         Once done, time base tick starts incrementing: the tick variable counter is incremented\r
-  *         each 1ms in the SysTick_Handler() interrupt handler.\r
-  *\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_Init(void)\r
-{\r
-  HAL_StatusTypeDef  status = HAL_OK;\r
-\r
-  /* Configure Flash prefetch, Instruction cache, Data cache */\r
-  /* Default configuration at reset is:                      */\r
-  /* - Prefetch disabled                                     */\r
-  /* - Instruction cache enabled                             */\r
-  /* - Data cache enabled                                    */\r
-#if (INSTRUCTION_CACHE_ENABLE == 0)\r
-   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
-#endif /* INSTRUCTION_CACHE_ENABLE */\r
-\r
-#if (DATA_CACHE_ENABLE == 0)\r
-   __HAL_FLASH_DATA_CACHE_DISABLE();\r
-#endif /* DATA_CACHE_ENABLE */\r
-\r
-#if (PREFETCH_ENABLE != 0)\r
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\r
-#endif /* PREFETCH_ENABLE */\r
-\r
-  /* Set Interrupt Group Priority */\r
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
-\r
-  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */\r
-  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Init the low level hardware */\r
-    HAL_MspInit();\r
-  }\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief De-initialize common part of the HAL and stop the source of time base.\r
-  * @note This function is optional.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DeInit(void)\r
-{\r
-  /* Reset of all peripherals */\r
-  __HAL_RCC_APB1_FORCE_RESET();\r
-  __HAL_RCC_APB1_RELEASE_RESET();\r
-\r
-  __HAL_RCC_APB2_FORCE_RESET();\r
-  __HAL_RCC_APB2_RELEASE_RESET();\r
-\r
-  __HAL_RCC_AHB1_FORCE_RESET();\r
-  __HAL_RCC_AHB1_RELEASE_RESET();\r
-\r
-  __HAL_RCC_AHB2_FORCE_RESET();\r
-  __HAL_RCC_AHB2_RELEASE_RESET();\r
-\r
-  __HAL_RCC_AHB3_FORCE_RESET();\r
-  __HAL_RCC_AHB3_RELEASE_RESET();\r
-\r
-  /* De-Init the low level hardware */\r
-  HAL_MspDeInit();\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initialize the MSP.\r
-  * @retval None\r
-  */\r
-__weak void HAL_MspInit(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitialize the MSP.\r
-  * @retval None\r
-  */\r
-__weak void HAL_MspDeInit(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief This function configures the source of the time base:\r
-  *        The time source is configured to have 1ms time base with a dedicated\r
-  *        Tick interrupt priority.\r
-  * @note This function is called  automatically at the beginning of program after\r
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().\r
-  * @note In the default implementation, SysTick timer is the source of time base.\r
-  *       It is used to generate interrupts at regular time intervals.\r
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,\r
-  *       The SysTick interrupt must have higher priority (numerically lower)\r
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
-  *       The function is declared as __weak  to be overwritten  in case of other\r
-  *       implementation  in user file.\r
-  * @param TickPriority  Tick interrupt priority.\r
-  * @retval HAL status\r
-  */\r
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
-{\r
-  HAL_StatusTypeDef  status = HAL_OK;\r
-\r
-  if (uwTickFreq != 0U)\r
-  {\r
-    /*Configure the SysTick to have interrupt in 1ms time basis*/\r
-    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)\r
-    {\r
-      /* Configure the SysTick IRQ priority */\r
-      if (TickPriority < (1UL << __NVIC_PRIO_BITS))\r
-      {\r
-        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\r
-        uwTickPrio = TickPriority;\r
-      }\r
-      else\r
-      {\r
-        status = HAL_ERROR;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions\r
- *  @brief    HAL Control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### HAL Control functions #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Provide a tick value in millisecond\r
-      (+) Provide a blocking delay in millisecond\r
-      (+) Suspend the time base source interrupt\r
-      (+) Resume the time base source interrupt\r
-      (+) Get the HAL API driver version\r
-      (+) Get the device identifier\r
-      (+) Get the device revision identifier\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief This function is called to increment a global variable "uwTick"\r
-  *        used as application time base.\r
-  * @note In the default implementation, this variable is incremented each 1ms\r
-  *       in SysTick ISR.\r
- * @note This function is declared as __weak to be overwritten in case of other\r
-  *      implementations in user file.\r
-  * @retval None\r
-  */\r
-__weak void HAL_IncTick(void)\r
-{\r
-  uwTick += uwTickFreq;\r
-}\r
-\r
-/**\r
-  * @brief Provide a tick value in millisecond.\r
-  * @note This function is declared as __weak to be overwritten in case of other\r
-  *       implementations in user file.\r
-  * @retval tick value\r
-  */\r
-__weak uint32_t HAL_GetTick(void)\r
-{\r
-  return uwTick;\r
-}\r
-\r
-/**\r
-  * @brief This function returns a tick priority.\r
-  * @retval tick priority\r
-  */\r
-uint32_t HAL_GetTickPrio(void)\r
-{\r
-  return uwTickPrio;\r
-}\r
-\r
-/**\r
-  * @brief Set new tick Freq.\r
-  * @param Freq tick frequency\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)\r
-{\r
-  HAL_StatusTypeDef status  = HAL_OK;\r
-  assert_param(IS_TICKFREQ(Freq));\r
-\r
-  if (uwTickFreq != Freq)\r
-  {\r
-    /* Apply the new tick Freq  */\r
-    status = HAL_InitTick(uwTickPrio);\r
-    if (status == HAL_OK)\r
-    {\r
-      uwTickFreq = Freq;\r
-    }\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief Return tick frequency.\r
-  * @retval tick period in Hz\r
-  */\r
-uint32_t HAL_GetTickFreq(void)\r
-{\r
-  return uwTickFreq;\r
-}\r
-\r
-/**\r
-  * @brief This function provides minimum delay (in milliseconds) based\r
-  *        on variable incremented.\r
-  * @note In the default implementation , SysTick timer is the source of time base.\r
-  *       It is used to generate interrupts at regular time intervals where uwTick\r
-  *       is incremented.\r
-  * @note This function is declared as __weak to be overwritten in case of other\r
-  *       implementations in user file.\r
-  * @param Delay  specifies the delay time length, in milliseconds.\r
-  * @retval None\r
-  */\r
-__weak void HAL_Delay(uint32_t Delay)\r
-{\r
-  uint32_t tickstart = HAL_GetTick();\r
-  uint32_t wait = Delay;\r
-\r
-  /* Add a period to guaranty minimum wait */\r
-  if (wait < HAL_MAX_DELAY)\r
-  {\r
-    wait += (uint32_t)(uwTickFreq);\r
-  }\r
-\r
-  while((HAL_GetTick() - tickstart) < wait)\r
-  {\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Suspend Tick increment.\r
-  * @note In the default implementation , SysTick timer is the source of time base. It is\r
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
-  *       is called, the SysTick interrupt will be disabled and so Tick increment\r
-  *       is suspended.\r
-  * @note This function is declared as __weak to be overwritten in case of other\r
-  *       implementations in user file.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SuspendTick(void)\r
-{\r
-  /* Disable SysTick Interrupt */\r
-  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r
-}\r
-\r
-/**\r
-  * @brief Resume Tick increment.\r
-  * @note In the default implementation , SysTick timer is the source of time base. It is\r
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
-  *       is called, the SysTick interrupt will be enabled and so Tick increment\r
-  *       is resumed.\r
-  * @note This function is declared as __weak to be overwritten in case of other\r
-  *       implementations in user file.\r
-  * @retval None\r
-  */\r
-__weak void HAL_ResumeTick(void)\r
-{\r
-  /* Enable SysTick Interrupt */\r
-  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;\r
-}\r
-\r
-/**\r
-  * @brief  Return the HAL revision.\r
-  * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r
-  */\r
-uint32_t HAL_GetHalVersion(void)\r
-{\r
-  return STM32L4XX_HAL_VERSION;\r
-}\r
-\r
-/**\r
-  * @brief  Return the device revision identifier.\r
-  * @retval Device revision identifier\r
-  */\r
-uint32_t HAL_GetREVID(void)\r
-{\r
-  return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);\r
-}\r
-\r
-/**\r
-  * @brief  Return the device identifier.\r
-  * @retval Device identifier\r
-  */\r
-uint32_t HAL_GetDEVID(void)\r
-{\r
-  return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);\r
-}\r
-\r
-/**\r
-  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)\r
-  * @retval Device identifier\r
-  */\r
-uint32_t HAL_GetUIDw0(void)\r
-{\r
-  return(READ_REG(*((uint32_t *)UID_BASE)));\r
-}\r
-\r
-/**\r
-  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)\r
-  * @retval Device identifier\r
-  */\r
-uint32_t HAL_GetUIDw1(void)\r
-{\r
-  return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));\r
-}\r
-\r
-/**\r
-  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)\r
-  * @retval Device identifier\r
-  */\r
-uint32_t HAL_GetUIDw2(void)\r
-{\r
-  return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions\r
- *  @brief    HAL Debug functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### HAL Debug functions #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Enable/Disable Debug module during SLEEP mode\r
-      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes\r
-      (+) Enable/Disable Debug module during STANDBY mode\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Enable the Debug Module during SLEEP mode.\r
-  * @retval None\r
-  */\r
-void HAL_DBGMCU_EnableDBGSleepMode(void)\r
-{\r
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
-}\r
-\r
-/**\r
-  * @brief  Disable the Debug Module during SLEEP mode.\r
-  * @retval None\r
-  */\r
-void HAL_DBGMCU_DisableDBGSleepMode(void)\r
-{\r
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
-}\r
-\r
-/**\r
-  * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.\r
-  * @retval None\r
-  */\r
-void HAL_DBGMCU_EnableDBGStopMode(void)\r
-{\r
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
-}\r
-\r
-/**\r
-  * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.\r
-  * @retval None\r
-  */\r
-void HAL_DBGMCU_DisableDBGStopMode(void)\r
-{\r
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
-}\r
-\r
-/**\r
-  * @brief  Enable the Debug Module during STANDBY mode.\r
-  * @retval None\r
-  */\r
-void HAL_DBGMCU_EnableDBGStandbyMode(void)\r
-{\r
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
-}\r
-\r
-/**\r
-  * @brief  Disable the Debug Module during STANDBY mode.\r
-  * @retval None\r
-  */\r
-void HAL_DBGMCU_DisableDBGStandbyMode(void)\r
-{\r
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions\r
- *  @brief    HAL SYSCFG configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### HAL SYSCFG configuration functions #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Start a hardware SRAM2 erase operation\r
-      (+) Enable/Disable the Internal FLASH Bank Swapping\r
-      (+) Configure the Voltage reference buffer\r
-      (+) Enable/Disable the Voltage reference buffer\r
-      (+) Enable/Disable the I/O analog switch voltage booster\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Start a hardware SRAM2 erase operation.\r
-  * @note   As long as SRAM2 is not erased the SRAM2ER bit will be set.\r
-  *         This bit is automatically reset at the end of the SRAM2 erase operation.\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_SRAM2Erase(void)\r
-{\r
-  /* unlock the write protection of the SRAM2ER bit */\r
-  SYSCFG->SKR = 0xCA;\r
-  SYSCFG->SKR = 0x53;\r
-  /* Starts a hardware SRAM2 erase operation*/\r
-  *(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL;\r
-}\r
-\r
-/**\r
-  * @brief  Enable the Internal FLASH Bank Swapping.\r
-  *\r
-  * @note   This function can be used only for STM32L4xx devices.\r
-  *\r
-  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)\r
-  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)\r
-  *\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_EnableMemorySwappingBank(void)\r
-{\r
-  *(__IO uint32_t *)FB_MODE_BB = 0x00000001UL;\r
-}\r
-\r
-/**\r
-  * @brief  Disable the Internal FLASH Bank Swapping.\r
-  *\r
-  * @note   This function can be used only for STM32L4xx devices.\r
-  *\r
-  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)\r
-  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)\r
-  *\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_DisableMemorySwappingBank(void)\r
-{\r
-\r
-  *(__IO uint32_t *)FB_MODE_BB = 0x00000000UL;\r
-}\r
-\r
-#if defined(VREFBUF)\r
-/**\r
-  * @brief Configure the internal voltage reference buffer voltage scale.\r
-  * @param VoltageScaling  specifies the output voltage to achieve\r
-  *          This parameter can be one of the following values:\r
-  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.\r
-  *                                                This requires VDDA equal to or higher than 2.4 V.\r
-  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.\r
-  *                                                This requires VDDA equal to or higher than 2.8 V.\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));\r
-\r
-  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);\r
-}\r
-\r
-/**\r
-  * @brief Configure the internal voltage reference buffer high impedance mode.\r
-  * @param Mode  specifies the high impedance mode\r
-  *          This parameter can be one of the following values:\r
-  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.\r
-  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));\r
-\r
-  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);\r
-}\r
-\r
-/**\r
-  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));\r
-\r
-  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);\r
-}\r
-\r
-/**\r
-  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).\r
-  * @retval HAL_OK/HAL_TIMEOUT\r
-  */\r
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)\r
-{\r
-  uint32_t  tickstart;\r
-\r
-  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\r
-\r
-  /* Get Start Tick*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait for VRR bit  */\r
-  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)\r
-  {\r
-    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).\r
-  *\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_DisableVREFBUF(void)\r
-{\r
-  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\r
-}\r
-#endif /* VREFBUF */\r
-\r
-/**\r
-  * @brief  Enable the I/O analog switch voltage booster\r
-  *\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)\r
-{\r
-  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);\r
-}\r
-\r
-/**\r
-  * @brief  Disable the I/O analog switch voltage booster\r
-  *\r
-  * @retval None\r
-  */\r
-void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)\r
-{\r
-  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
deleted file mode 100644 (file)
index 8080ad0..0000000
+++ /dev/null
@@ -1,523 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_cortex.c\r
-  * @author  MCD Application Team\r
-  * @brief   CORTEX HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the CORTEX:\r
-  *           + Initialization and Configuration functions\r
-  *           + Peripheral Control functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                        ##### How to use this driver #####\r
-  ==============================================================================\r
-\r
-    [..]\r
-    *** How to configure Interrupts using CORTEX HAL driver ***\r
-    ===========================================================\r
-    [..]\r
-    This section provides functions allowing to configure the NVIC interrupts (IRQ).\r
-    The Cortex-M4 exceptions are managed by CMSIS functions.\r
-\r
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.\r
-    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().\r
-    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r
-\r
-     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.\r
-         The pending IRQ priority will be managed only by the sub priority.\r
-\r
-     -@- IRQ priority order (sorted by highest to lowest priority):\r
-        (+@) Lowest pre-emption priority\r
-        (+@) Lowest sub priority\r
-        (+@) Lowest hardware priority (IRQ number)\r
-\r
-    [..]\r
-    *** How to configure SysTick using CORTEX HAL driver ***\r
-    ========================================================\r
-    [..]\r
-    Setup SysTick Timer for time base.\r
-\r
-   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r
-       is a CMSIS function that:\r
-        (++) Configures the SysTick Reload register with value passed as function parameter.\r
-        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r
-        (++) Resets the SysTick Counter register.\r
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
-        (++) Enables the SysTick Interrupt.\r
-        (++) Starts the SysTick Counter.\r
-\r
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
-       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
-       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r
-       inside the stm32l4xx_hal_cortex.h file.\r
-\r
-   (+) You can change the SysTick IRQ priority by calling the\r
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function\r
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
-\r
-   (+) To adjust the SysTick time base, use the following formula:\r
-\r
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)\r
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
-       (++) Reload Value should not exceed 0xFFFFFF\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-\r
-  The table below gives the allowed values of the pre-emption priority and subpriority according\r
-  to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.\r
-\r
-    ==========================================================================================================================\r
-      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description\r
-    ==========================================================================================================================\r
-     NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority\r
-                           |                                   |                             | 4 bits for subpriority\r
-    --------------------------------------------------------------------------------------------------------------------------\r
-     NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority\r
-                           |                                   |                             | 3 bits for subpriority\r
-    --------------------------------------------------------------------------------------------------------------------------\r
-     NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority\r
-                           |                                   |                             | 2 bits for subpriority\r
-    --------------------------------------------------------------------------------------------------------------------------\r
-     NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority\r
-                           |                                   |                             | 1 bit for subpriority\r
-    --------------------------------------------------------------------------------------------------------------------------\r
-     NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority\r
-                           |                                   |                             | 0 bit for subpriority\r
-    ==========================================================================================================================\r
-\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup CORTEX\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_CORTEX_MODULE_ENABLED\r
-\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private constants ---------------------------------------------------------*/\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup CORTEX_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-\r
-/** @addtogroup CORTEX_Exported_Functions_Group1\r
- *  @brief    Initialization and Configuration functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-              ##### Initialization and Configuration functions #####\r
-  ==============================================================================\r
-    [..]\r
-      This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r
-      SysTick functionalities\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-\r
-/**\r
-  * @brief  Set the priority grouping field (pre-emption priority and subpriority)\r
-  *         using the required unlock sequence.\r
-  * @param  PriorityGroup: The priority grouping bits length.\r
-  *         This parameter can be one of the following values:\r
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,\r
-  *                                    4 bits for subpriority\r
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,\r
-  *                                    3 bits for subpriority\r
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,\r
-  *                                    2 bits for subpriority\r
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,\r
-  *                                    1 bit  for subpriority\r
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,\r
-  *                                    0 bit  for subpriority\r
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.\r
-  *         The pending IRQ priority will be managed only by the subpriority.\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
-\r
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
-  NVIC_SetPriorityGrouping(PriorityGroup);\r
-}\r
-\r
-/**\r
-  * @brief  Set the priority of an interrupt.\r
-  * @param  IRQn: External interrupt number.\r
-  *         This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.\r
-  *         This parameter can be a value between 0 and 15\r
-  *         A lower priority value indicates a higher priority\r
-  * @param  SubPriority: the subpriority level for the IRQ channel.\r
-  *         This parameter can be a value between 0 and 15\r
-  *         A lower priority value indicates a higher priority.\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
-  uint32_t prioritygroup = 0x00;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
-\r
-  prioritygroup = NVIC_GetPriorityGrouping();\r
-\r
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
-}\r
-\r
-/**\r
-  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.\r
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
-  *         function should be called before.\r
-  * @param  IRQn External interrupt number.\r
-  *         This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
-  /* Enable interrupt */\r
-  NVIC_EnableIRQ(IRQn);\r
-}\r
-\r
-/**\r
-  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.\r
-  * @param  IRQn External interrupt number.\r
-  *         This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
-  /* Disable interrupt */\r
-  NVIC_DisableIRQ(IRQn);\r
-}\r
-\r
-/**\r
-  * @brief  Initiate a system reset request to reset the MCU.\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_SystemReset(void)\r
-{\r
-  /* System Reset */\r
-  NVIC_SystemReset();\r
-}\r
-\r
-/**\r
-  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):\r
-  *         Counter is in free running mode to generate periodic interrupts.\r
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.\r
-  * @retval status:  - 0  Function succeeded.\r
-  *                  - 1  Function failed.\r
-  */\r
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
-{\r
-   return SysTick_Config(TicksNumb);\r
-}\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup CORTEX_Exported_Functions_Group2\r
- *  @brief   Cortex control functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-                      ##### Peripheral Control functions #####\r
-  ==============================================================================\r
-    [..]\r
-      This subsection provides a set of functions allowing to control the CORTEX\r
-      (NVIC, SYSTICK, MPU) functionalities.\r
-\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Get the priority grouping field from the NVIC Interrupt Controller.\r
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
-  */\r
-uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
-{\r
-  /* Get the PRIGROUP[10:8] field value */\r
-  return NVIC_GetPriorityGrouping();\r
-}\r
-\r
-/**\r
-  * @brief  Get the priority of an interrupt.\r
-  * @param  IRQn: External interrupt number.\r
-  *         This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @param   PriorityGroup: the priority grouping bits length.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,\r
-  *                                      4 bits for subpriority\r
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,\r
-  *                                      3 bits for subpriority\r
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,\r
-  *                                      2 bits for subpriority\r
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,\r
-  *                                      1 bit for subpriority\r
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,\r
-  *                                      0 bit for subpriority\r
-  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).\r
-  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
- /* Get priority for Cortex-M system or device specific interrupts */\r
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
-}\r
-\r
-/**\r
-  * @brief  Set Pending bit of an external interrupt.\r
-  * @param  IRQn External interrupt number\r
-  *         This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
-  /* Set interrupt pending */\r
-  NVIC_SetPendingIRQ(IRQn);\r
-}\r
-\r
-/**\r
-  * @brief  Get Pending Interrupt (read the pending register in the NVIC\r
-  *         and return the pending bit for the specified interrupt).\r
-  * @param  IRQn External interrupt number.\r
-  *          This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @retval status: - 0  Interrupt status is not pending.\r
-  *                 - 1  Interrupt status is pending.\r
-  */\r
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
-  /* Return 1 if pending else 0 */\r
-  return NVIC_GetPendingIRQ(IRQn);\r
-}\r
-\r
-/**\r
-  * @brief  Clear the pending bit of an external interrupt.\r
-  * @param  IRQn External interrupt number.\r
-  *         This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @retval None\r
-  */\r
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
-  /* Clear pending interrupt */\r
-  NVIC_ClearPendingIRQ(IRQn);\r
-}\r
-\r
-/**\r
-  * @brief Get active interrupt (read the active register in NVIC and return the active bit).\r
-  * @param IRQn External interrupt number\r
-  *         This parameter can be an enumerator of IRQn_Type enumeration\r
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))\r
-  * @retval status: - 0  Interrupt status is not pending.\r
-  *                 - 1  Interrupt status is pending.\r
-  */\r
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
-  /* Return 1 if active else 0 */\r
-  return NVIC_GetActive(IRQn);\r
-}\r
-\r
-/**\r
-  * @brief  Configure the SysTick clock source.\r
-  * @param  CLKSource: specifies the SysTick clock source.\r
-  *          This parameter can be one of the following values:\r
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
-  * @retval None\r
-  */\r
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
-  {\r
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
-  }\r
-  else\r
-  {\r
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Handle SYSTICK interrupt request.\r
-  * @retval None\r
-  */\r
-void HAL_SYSTICK_IRQHandler(void)\r
-{\r
-  HAL_SYSTICK_Callback();\r
-}\r
-\r
-/**\r
-  * @brief  SYSTICK callback.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SYSTICK_Callback(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SYSTICK_Callback could be implemented in the user file\r
-   */\r
-}\r
-\r
-#if (__MPU_PRESENT == 1)\r
-/**\r
-  * @brief  Disable the MPU.\r
-  * @retval None\r
-  */\r
-void HAL_MPU_Disable(void)\r
-{\r
-  /* Make sure outstanding transfers are done */\r
-  __DMB();\r
-\r
-  /* Disable fault exceptions */\r
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
-\r
-  /* Disable the MPU and clear the control register*/\r
-  MPU->CTRL = 0U;\r
-}\r
-\r
-/**\r
-  * @brief  Enable the MPU.\r
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,\r
-  *          NMI, FAULTMASK and privileged accessto the default memory\r
-  *          This parameter can be one of the following values:\r
-  *            @arg MPU_HFNMI_PRIVDEF_NONE\r
-  *            @arg MPU_HARDFAULT_NMI\r
-  *            @arg MPU_PRIVILEGED_DEFAULT\r
-  *            @arg MPU_HFNMI_PRIVDEF\r
-  * @retval None\r
-  */\r
-void HAL_MPU_Enable(uint32_t MPU_Control)\r
-{\r
-  /* Enable the MPU */\r
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
-\r
-  /* Enable fault exceptions */\r
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
-\r
-  /* Ensure MPU settings take effects */\r
-  __DSB();\r
-  __ISB();\r
-}\r
-\r
-/**\r
-  * @brief  Initialize and configure the Region and the memory to be protected.\r
-  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains\r
-  *                the initialization and configuration information.\r
-  * @retval None\r
-  */\r
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
-\r
-  /* Set the Region number */\r
-  MPU->RNR = MPU_Init->Number;\r
-\r
-  if ((MPU_Init->Enable) != RESET)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
-\r
-    MPU->RBAR = MPU_Init->BaseAddress;\r
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |\r
-                ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |\r
-                ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |\r
-                ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |\r
-                ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |\r
-                ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |\r
-                ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |\r
-                ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |\r
-                ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);\r
-  }\r
-  else\r
-  {\r
-    MPU->RBAR = 0x00;\r
-    MPU->RASR = 0x00;\r
-  }\r
-}\r
-#endif /* __MPU_PRESENT */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_CORTEX_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c
deleted file mode 100644 (file)
index 5675a39..0000000
+++ /dev/null
@@ -1,3590 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_dfsdm.c\r
-  * @author  MCD Application Team\r
-  * @brief   This file provides firmware functions to manage the following\r
-  *          functionalities of the Digital Filter for Sigma-Delta Modulators\r
-  *          (DFSDM) peripherals:\r
-  *           + Initialization and configuration of channels and filters\r
-  *           + Regular channels configuration\r
-  *           + Injected channels configuration\r
-  *           + Regular/Injected Channels DMA Configuration\r
-  *           + Interrupts and flags management\r
-  *           + Analog watchdog feature\r
-  *           + Short-circuit detector feature\r
-  *           + Extremes detector feature\r
-  *           + Clock absence detector feature\r
-  *           + Break generation on analog watchdog or short-circuit event\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                     ##### How to use this driver #####\r
-  ==============================================================================\r
-  [..]\r
-    *** Channel initialization ***\r
-    ==============================\r
-    [..]\r
-      (#) User has first to initialize channels (before filters initialization).\r
-      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :\r
-        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().\r
-        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
-        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().\r
-        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global\r
-            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
-      (#) Configure the output clock, input, serial interface, analog watchdog,\r
-          offset and data right bit shift parameters for this channel using the\r
-          HAL_DFSDM_ChannelInit() function.\r
-\r
-    *** Channel clock absence detector ***\r
-    ======================================\r
-    [..]\r
-      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or\r
-          HAL_DFSDM_ChannelCkabStart_IT().\r
-      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock\r
-          absence.\r
-      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if\r
-          clock absence is detected.\r
-      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or\r
-          HAL_DFSDM_ChannelCkabStop_IT().\r
-      (#) Please note that the same mode (polling or interrupt) has to be used\r
-          for all channels because the channels are sharing the same interrupt.\r
-      (#) Please note also that in interrupt mode, if clock absence detector is\r
-          stopped for one channel, interrupt will be disabled for all channels.\r
-\r
-    *** Channel short circuit detector ***\r
-    ======================================\r
-    [..]\r
-      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or\r
-          or HAL_DFSDM_ChannelScdStart_IT().\r
-      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short\r
-          circuit.\r
-      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if\r
-          short circuit is detected.\r
-      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or\r
-          or HAL_DFSDM_ChannelScdStop_IT().\r
-      (#) Please note that the same mode (polling or interrupt) has to be used\r
-          for all channels because the channels are sharing the same interrupt.\r
-      (#) Please note also that in interrupt mode, if short circuit detector is\r
-          stopped for one channel, interrupt will be disabled for all channels.\r
-\r
-    *** Channel analog watchdog value ***\r
-    =====================================\r
-    [..]\r
-      (#) Get analog watchdog filter value of a channel using\r
-          HAL_DFSDM_ChannelGetAwdValue().\r
-\r
-    *** Channel offset value ***\r
-    =====================================\r
-    [..]\r
-      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().\r
-\r
-    *** Filter initialization ***\r
-    =============================\r
-    [..]\r
-      (#) After channel initialization, user has to init filters.\r
-      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :\r
-        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global\r
-            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
-            Please note that DFSDMz_FLT0 global interrupt could be already\r
-            enabled if interrupt is used for channel.\r
-        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it\r
-            with DFSDMz filter handle using __HAL_LINKDMA().\r
-      (#) Configure the regular conversion, injected conversion and filter\r
-          parameters for this filter using the HAL_DFSDM_FilterInit() function.\r
-\r
-    *** Filter regular channel conversion ***\r
-    =========================================\r
-    [..]\r
-      (#) Select regular channel and enable/disable continuous mode using\r
-          HAL_DFSDM_FilterConfigRegChannel().\r
-      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),\r
-          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or\r
-          HAL_DFSDM_FilterRegularMsbStart_DMA().\r
-      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect\r
-          the end of regular conversion.\r
-      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called\r
-          at the end of regular conversion.\r
-      (#) Get value of regular conversion and corresponding channel using\r
-          HAL_DFSDM_FilterGetRegularValue().\r
-      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and\r
-          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the\r
-          half transfer and at the transfer complete. Please note that\r
-          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA\r
-          circular mode.\r
-      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),\r
-          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().\r
-\r
-    *** Filter injected channels conversion ***\r
-    ===========================================\r
-    [..]\r
-      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().\r
-      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),\r
-          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or\r
-          HAL_DFSDM_FilterInjectedMsbStart_DMA().\r
-      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect\r
-          the end of injected conversion.\r
-      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called\r
-          at the end of injected conversion.\r
-      (#) Get value of injected conversion and corresponding channel using\r
-          HAL_DFSDM_FilterGetInjectedValue().\r
-      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and\r
-          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the\r
-          half transfer and at the transfer complete. Please note that\r
-          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA\r
-          circular mode.\r
-      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),\r
-          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().\r
-\r
-    *** Filter analog watchdog ***\r
-    ==============================\r
-    [..]\r
-      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().\r
-      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.\r
-      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().\r
-\r
-    *** Filter extreme detector ***\r
-    ===============================\r
-    [..]\r
-      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().\r
-      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().\r
-      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().\r
-      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().\r
-\r
-    *** Filter conversion time ***\r
-    ==============================\r
-    [..]\r
-      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().\r
-\r
-    *** Callback registration ***\r
-    =============================\r
-    [..]\r
-    The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1\r
-    allows the user to configure dynamically the driver callbacks.\r
-    Use functions HAL_DFSDM_Channel_RegisterCallback(),\r
-    HAL_DFSDM_Filter_RegisterCallback() or\r
-    HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.\r
-\r
-    [..]\r
-    Function HAL_DFSDM_Channel_RegisterCallback() allows to register\r
-    following callbacks:\r
-      (+) CkabCallback      : DFSDM channel clock absence detection callback.\r
-      (+) ScdCallback       : DFSDM channel short circuit detection callback.\r
-      (+) MspInitCallback   : DFSDM channel MSP init callback.\r
-      (+) MspDeInitCallback : DFSDM channel MSP de-init callback.\r
-    [..]\r
-    This function takes as parameters the HAL peripheral handle, the Callback ID\r
-    and a pointer to the user callback function.\r
-\r
-    [..]\r
-    Function HAL_DFSDM_Filter_RegisterCallback() allows to register\r
-    following callbacks:\r
-      (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.\r
-      (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.\r
-      (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.\r
-      (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.\r
-      (+) ErrorCallback           : DFSDM filter error callback.\r
-      (+) MspInitCallback         : DFSDM filter MSP init callback.\r
-      (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.\r
-    [..]\r
-    This function takes as parameters the HAL peripheral handle, the Callback ID\r
-    and a pointer to the user callback function.\r
-\r
-    [..]\r
-    For specific DFSDM filter analog watchdog callback use dedicated register callback:\r
-    HAL_DFSDM_Filter_RegisterAwdCallback().\r
-\r
-    [..]\r
-    Use functions HAL_DFSDM_Channel_UnRegisterCallback() or\r
-    HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default\r
-    weak function.\r
-\r
-    [..]\r
-    HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
-    and the Callback ID.\r
-    [..]\r
-    This function allows to reset following callbacks:\r
-      (+) CkabCallback      : DFSDM channel clock absence detection callback.\r
-      (+) ScdCallback       : DFSDM channel short circuit detection callback.\r
-      (+) MspInitCallback   : DFSDM channel MSP init callback.\r
-      (+) MspDeInitCallback : DFSDM channel MSP de-init callback.\r
-\r
-    [..]\r
-    HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
-    and the Callback ID.\r
-    [..]\r
-    This function allows to reset following callbacks:\r
-      (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.\r
-      (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.\r
-      (+) InjConvCpltCallback     : DFSDM filter injected conversion complete callback.\r
-      (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.\r
-      (+) ErrorCallback           : DFSDM filter error callback.\r
-      (+) MspInitCallback         : DFSDM filter MSP init callback.\r
-      (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.\r
-\r
-    [..]\r
-    For specific DFSDM filter analog watchdog callback use dedicated unregister callback:\r
-    HAL_DFSDM_Filter_UnRegisterAwdCallback().\r
-\r
-    [..]\r
-    By default, after the call of init function and if the state is RESET\r
-    all callbacks are reset to the corresponding legacy weak functions:\r
-    examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().\r
-    Exception done for MspInit and MspDeInit callbacks that are respectively\r
-    reset to the legacy weak functions in the init and de-init only when these\r
-    callbacks are null (not registered beforehand).\r
-    If not, MspInit or MspDeInit are not null, the init and de-init keep and use\r
-    the user MspInit/MspDeInit callbacks (registered beforehand)\r
-\r
-    [..]\r
-    Callbacks can be registered/unregistered in READY state only.\r
-    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered\r
-    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used\r
-    during the init/de-init.\r
-    In that case first register the MspInit/MspDeInit user callbacks using\r
-    HAL_DFSDM_Channel_RegisterCallback() or\r
-    HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.\r
-\r
-    [..]\r
-    When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or\r
-    not defined, the callback registering feature is not available\r
-    and weak callbacks are used.\r
-\r
-    @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-#ifdef HAL_DFSDM_MODULE_ENABLED\r
-\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
-    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
-    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
-    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-\r
-/** @defgroup DFSDM DFSDM\r
-  * @brief DFSDM HAL driver module\r
-  * @{\r
-  */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup DFSDM_Private_Define DFSDM Private Define\r
- * @{\r
- */\r
-#define DFSDM_FLTCR1_MSB_RCH_OFFSET     8\r
-#define DFSDM_MSB_MASK                  0xFFFF0000U\r
-#define DFSDM_LSB_MASK                  0x0000FFFFU\r
-#define DFSDM_CKAB_TIMEOUT              5000U\r
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
-#define DFSDM1_CHANNEL_NUMBER           4U\r
-#else /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-#define DFSDM1_CHANNEL_NUMBER           8U\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/** @defgroup DFSDM_Private_Variables DFSDM Private Variables\r
-  * @{\r
-  */\r
-static __IO uint32_t                v_dfsdm1ChannelCounter = 0;\r
-static DFSDM_Channel_HandleTypeDef *a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup DFSDM_Private_Functions DFSDM Private Functions\r
-  * @{\r
-  */\r
-static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);\r
-static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance);\r
-static void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-static void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-static void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-static void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
-static void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);\r
-static void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);\r
-static void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);\r
-static void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);\r
-static void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r
- *  @brief    Channel initialization and de-initialization functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-        ##### Channel initialization and de-initialization functions #####\r
-  ==============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Initialize the DFSDM channel.\r
-      (+) De-initialize the DFSDM channel.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initialize the DFSDM channel according to the specified parameters\r
-  *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  /* Check DFSDM Channel handle */\r
-  if (hdfsdm_channel == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));\r
-  assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));\r
-  assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));\r
-  assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));\r
-  assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));\r
-  assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));\r
-  assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));\r
-  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));\r
-  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));\r
-  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));\r
-\r
-  /* Check that channel has not been already initialized */\r
-  if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  /* Reset callback pointers to the weak predefined callbacks */\r
-  hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;\r
-  hdfsdm_channel->ScdCallback  = HAL_DFSDM_ChannelScdCallback;\r
-\r
-  /* Call MSP init function */\r
-  if (hdfsdm_channel->MspInitCallback == NULL)\r
-  {\r
-    hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;\r
-  }\r
-  hdfsdm_channel->MspInitCallback(hdfsdm_channel);\r
-#else\r
-  /* Call MSP init function */\r
-  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);\r
-#endif\r
-\r
-  /* Update the channel counter */\r
-  v_dfsdm1ChannelCounter++;\r
-\r
-  /* Configure output serial clock and enable global DFSDM interface only for first channel */\r
-  if (v_dfsdm1ChannelCounter == 1U)\r
-  {\r
-    assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));\r
-    /* Set the output serial clock source */\r
-    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);\r
-    DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;\r
-\r
-    /* Reset clock divider */\r
-    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);\r
-    if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)\r
-    {\r
-      assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));\r
-      /* Set the output clock divider */\r
-      DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<\r
-                                             DFSDM_CHCFGR1_CKOUTDIV_Pos);\r
-    }\r
-\r
-    /* enable the DFSDM global interface */\r
-    DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;\r
-  }\r
-\r
-  /* Set channel input parameters */\r
-  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |\r
-                                         DFSDM_CHCFGR1_CHINSEL);\r
-  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |\r
-                                        hdfsdm_channel->Init.Input.DataPacking |\r
-                                        hdfsdm_channel->Init.Input.Pins);\r
-\r
-  /* Set serial interface parameters */\r
-  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);\r
-  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |\r
-                                        hdfsdm_channel->Init.SerialInterface.SpiClock);\r
-\r
-  /* Set analog watchdog parameters */\r
-  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);\r
-  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |\r
-                                         ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));\r
-\r
-  /* Set channel offset and right bit shift */\r
-  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);\r
-  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |\r
-                                        (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));\r
-\r
-  /* Enable DFSDM channel */\r
-  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;\r
-\r
-  /* Set DFSDM Channel to ready state */\r
-  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;\r
-\r
-  /* Store channel handle in DFSDM channel handle table */\r
-  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  De-initialize the DFSDM channel.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  /* Check DFSDM Channel handle */\r
-  if (hdfsdm_channel == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check that channel has not been already deinitialized */\r
-  if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Disable the DFSDM channel */\r
-  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);\r
-\r
-  /* Update the channel counter */\r
-  v_dfsdm1ChannelCounter--;\r
-\r
-  /* Disable global DFSDM at deinit of last channel */\r
-  if (v_dfsdm1ChannelCounter == 0U)\r
-  {\r
-    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);\r
-  }\r
-\r
-  /* Call MSP deinit function */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  if (hdfsdm_channel->MspDeInitCallback == NULL)\r
-  {\r
-    hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;\r
-  }\r
-  hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);\r
-#else\r
-  HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);\r
-#endif\r
-\r
-  /* Set DFSDM Channel in reset state */\r
-  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;\r
-\r
-  /* Reset channel handle in DFSDM channel handle table */\r
-  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initialize the DFSDM channel MSP.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_channel);\r
-\r
-  /* NOTE : This function should not be modified, when the function is needed,\r
-            the HAL_DFSDM_ChannelMspInit could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  De-initialize the DFSDM channel MSP.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_channel);\r
-\r
-  /* NOTE : This function should not be modified, when the function is needed,\r
-            the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.\r
-   */\r
-}\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  Register a user DFSDM channel callback\r
-  *         to be used instead of the weak predefined callback.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @param  CallbackID ID of the callback to be registered.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.\r
-  * @param  pCallback pointer to the callback function.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
-                                                     HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,\r
-                                                     pDFSDM_Channel_CallbackTypeDef      pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* update return status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)\r
-    {\r
-      switch (CallbackID)\r
-      {\r
-        case HAL_DFSDM_CHANNEL_CKAB_CB_ID :\r
-          hdfsdm_channel->CkabCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_CHANNEL_SCD_CB_ID :\r
-          hdfsdm_channel->ScdCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
-          hdfsdm_channel->MspInitCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
-          hdfsdm_channel->MspDeInitCallback = pCallback;\r
-          break;\r
-        default :\r
-          /* update return status */\r
-          status = HAL_ERROR;\r
-          break;\r
-      }\r
-    }\r
-    else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)\r
-    {\r
-      switch (CallbackID)\r
-      {\r
-        case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
-          hdfsdm_channel->MspInitCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
-          hdfsdm_channel->MspDeInitCallback = pCallback;\r
-          break;\r
-        default :\r
-          /* update return status */\r
-          status = HAL_ERROR;\r
-          break;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* update return status */\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister a user DFSDM channel callback.\r
-  *         DFSDM channel callback is redirected to the weak predefined callback.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @param  CallbackID ID of the callback to be unregistered.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.\r
-  *           @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,\r
-                                                       HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_DFSDM_CHANNEL_CKAB_CB_ID :\r
-        hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;\r
-        break;\r
-      case HAL_DFSDM_CHANNEL_SCD_CB_ID :\r
-        hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;\r
-        break;\r
-      case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
-        hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;\r
-        break;\r
-      case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
-        hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;\r
-        break;\r
-      default :\r
-        /* update return status */\r
-        status = HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :\r
-        hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;\r
-        break;\r
-      case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :\r
-        hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;\r
-        break;\r
-      default :\r
-        /* update return status */\r
-        status = HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* update return status */\r
-    status = HAL_ERROR;\r
-  }\r
-  return status;\r
-}\r
-#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r
- *  @brief    Channel operation functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-                   ##### Channel operation functions #####\r
-  ==============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Manage clock absence detector feature.\r
-      (+) Manage short circuit detector feature.\r
-      (+) Get analog watchdog value.\r
-      (+) Modify offset value.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  This function allows to start clock absence detection in polling mode.\r
-  * @note   Same mode has to be used for all channels.\r
-  * @note   If clock is not available on this channel during 5 seconds,\r
-  *         clock absence detection will not be activated and function\r
-  *         will return HAL_TIMEOUT error.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t channel;\r
-  uint32_t tickstart;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Get channel number from channel instance */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-\r
-    /* Get timeout */\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Clear clock absence flag */\r
-    while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)\r
-    {\r
-      DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
-\r
-      /* Check the Timeout */\r
-      if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT)\r
-      {\r
-        /* Set timeout status */\r
-        status = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      /* Start clock absence detection */\r
-      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r
-    }\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to poll for the clock absence detection.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @param  Timeout Timeout value in milliseconds.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
-                                               uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-  uint32_t channel;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    return HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Get channel number from channel instance */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-\r
-    /* Get timeout */\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait clock absence detection */\r
-    while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)\r
-    {\r
-      /* Check the Timeout */\r
-      if (Timeout != HAL_MAX_DELAY)\r
-      {\r
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
-        {\r
-          /* Return timeout status */\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-\r
-    /* Clear clock absence detection flag */\r
-    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
-\r
-    /* Return function status */\r
-    return HAL_OK;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop clock absence detection in polling mode.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t channel;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop clock absence detection */\r
-    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r
-\r
-    /* Clear clock absence flag */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start clock absence detection in interrupt mode.\r
-  * @note   Same mode has to be used for all channels.\r
-  * @note   If clock is not available on this channel during 5 seconds,\r
-  *         clock absence detection will not be activated and function\r
-  *         will return HAL_TIMEOUT error.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t channel;\r
-  uint32_t tickstart;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Get channel number from channel instance */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-\r
-    /* Get timeout */\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Clear clock absence flag */\r
-    while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)\r
-    {\r
-      DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
-\r
-      /* Check the Timeout */\r
-      if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT)\r
-      {\r
-        /* Set timeout status */\r
-        status = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      /* Activate clock absence detection interrupt */\r
-      DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;\r
-\r
-      /* Start clock absence detection */\r
-      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r
-    }\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Clock absence detection callback.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_channel);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop clock absence detection in interrupt mode.\r
-  * @note   Interrupt will be disabled for all channels\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t channel;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop clock absence detection */\r
-    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r
-\r
-    /* Clear clock absence flag */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
-\r
-    /* Disable clock absence detection interrupt */\r
-    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start short circuit detection in polling mode.\r
-  * @note   Same mode has to be used for all channels\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @param  Threshold Short circuit detector threshold.\r
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r
-  * @param  BreakSignal Break signals assigned to short circuit event.\r
-  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
-                                            uint32_t Threshold,\r
-                                            uint32_t BreakSignal)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r
-  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Configure threshold and break signals */\r
-    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r
-    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \\r
-                                           Threshold);\r
-\r
-    /* Start short circuit detection */\r
-    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to poll for the short circuit detection.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @param  Timeout Timeout value in milliseconds.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
-                                              uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-  uint32_t channel;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    return HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Get channel number from channel instance */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-\r
-    /* Get timeout */\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait short circuit detection */\r
-    while (((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)\r
-    {\r
-      /* Check the Timeout */\r
-      if (Timeout != HAL_MAX_DELAY)\r
-      {\r
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
-        {\r
-          /* Return timeout status */\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-\r
-    /* Clear short circuit detection flag */\r
-    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
-\r
-    /* Return function status */\r
-    return HAL_OK;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop short circuit detection in polling mode.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t channel;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop short circuit detection */\r
-    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r
-\r
-    /* Clear short circuit detection flag */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start short circuit detection in interrupt mode.\r
-  * @note   Same mode has to be used for all channels\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @param  Threshold Short circuit detector threshold.\r
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r
-  * @param  BreakSignal Break signals assigned to short circuit event.\r
-  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
-                                               uint32_t Threshold,\r
-                                               uint32_t BreakSignal)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r
-  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Activate short circuit detection interrupt */\r
-    DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;\r
-\r
-    /* Configure threshold and break signals */\r
-    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r
-    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \\r
-                                           Threshold);\r
-\r
-    /* Start short circuit detection */\r
-    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Short circuit detection callback.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_channel);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_ChannelScdCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop short circuit detection in interrupt mode.\r
-  * @note   Interrupt will be disabled for all channels\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t channel;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop short circuit detection */\r
-    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r
-\r
-    /* Clear short circuit detection flag */\r
-    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r
-    DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
-\r
-    /* Disable short circuit detection interrupt */\r
-    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get channel analog watchdog value.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval Channel analog watchdog value.\r
-  */\r
-int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  return (int16_t) hdfsdm_channel->Instance->CHWDATAR;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to modify channel offset value.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @param  Offset DFSDM channel offset.\r
-  *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
-                                                int32_t Offset)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r
-  assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));\r
-\r
-  /* Check DFSDM channel state */\r
-  if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Modify channel offset */\r
-    hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);\r
-    hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r
- *  @brief    Channel state function\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-                   ##### Channel state function #####\r
-  ==============================================================================\r
-    [..]  This section provides function allowing to:\r
-      (+) Get channel handle state.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  This function allows to get the current DFSDM channel handle state.\r
-  * @param  hdfsdm_channel DFSDM channel handle.\r
-  * @retval DFSDM channel state.\r
-  */\r
-HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r
-{\r
-  /* Return DFSDM channel handle state */\r
-  return hdfsdm_channel->State;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r
- *  @brief    Filter initialization and de-initialization functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-        ##### Filter initialization and de-initialization functions #####\r
-  ==============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Initialize the DFSDM filter.\r
-      (+) De-initialize the DFSDM filter.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initialize the DFSDM filter according to the specified parameters\r
-  *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Check DFSDM Channel handle */\r
-  if (hdfsdm_filter == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));\r
-  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));\r
-  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));\r
-  assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));\r
-  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));\r
-  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));\r
-  assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));\r
-  assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));\r
-  assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));\r
-\r
-  /* Check parameters compatibility */\r
-  if ((hdfsdm_filter->Instance == DFSDM1_Filter0) &&\r
-      ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) ||\r
-       (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Initialize DFSDM filter variables with default values */\r
-  hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;\r
-  hdfsdm_filter->InjectedChannelsNbr = 1;\r
-  hdfsdm_filter->InjConvRemaining    = 1;\r
-  hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  /* Reset callback pointers to the weak predefined callbacks */\r
-  hdfsdm_filter->AwdCallback             = HAL_DFSDM_FilterAwdCallback;\r
-  hdfsdm_filter->RegConvCpltCallback     = HAL_DFSDM_FilterRegConvCpltCallback;\r
-  hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;\r
-  hdfsdm_filter->InjConvCpltCallback     = HAL_DFSDM_FilterInjConvCpltCallback;\r
-  hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;\r
-  hdfsdm_filter->ErrorCallback           = HAL_DFSDM_FilterErrorCallback;\r
-\r
-  /* Call MSP init function */\r
-  if (hdfsdm_filter->MspInitCallback == NULL)\r
-  {\r
-    hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;\r
-  }\r
-  hdfsdm_filter->MspInitCallback(hdfsdm_filter);\r
-#else\r
-  /* Call MSP init function */\r
-  HAL_DFSDM_FilterMspInit(hdfsdm_filter);\r
-#endif\r
-\r
-  /* Set regular parameters */\r
-  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r
-  if (hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;\r
-  }\r
-  else\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);\r
-  }\r
-\r
-  if (hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;\r
-  }\r
-  else\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);\r
-  }\r
-\r
-  /* Set injected parameters */\r
-  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);\r
-  if (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)\r
-  {\r
-    assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));\r
-    assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));\r
-    hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);\r
-  }\r
-\r
-  if (hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;\r
-  }\r
-  else\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);\r
-  }\r
-\r
-  if (hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;\r
-  }\r
-  else\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);\r
-  }\r
-\r
-  /* Set filter parameters */\r
-  hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);\r
-  hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |\r
-                                      ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |\r
-                                      (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));\r
-\r
-  /* Store regular and injected triggers and injected scan mode*/\r
-  hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;\r
-  hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;\r
-  hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;\r
-  hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;\r
-\r
-  /* Enable DFSDM filter */\r
-  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
-\r
-  /* Set DFSDM filter to ready state */\r
-  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  De-initializes the DFSDM filter.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Check DFSDM filter handle */\r
-  if (hdfsdm_filter == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Disable the DFSDM filter */\r
-  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
-\r
-  /* Call MSP deinit function */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  if (hdfsdm_filter->MspDeInitCallback == NULL)\r
-  {\r
-    hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;\r
-  }\r
-  hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);\r
-#else\r
-  HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);\r
-#endif\r
-\r
-  /* Set DFSDM filter in reset state */\r
-  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the DFSDM filter MSP.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-\r
-  /* NOTE : This function should not be modified, when the function is needed,\r
-            the HAL_DFSDM_FilterMspInit could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  De-initializes the DFSDM filter MSP.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-\r
-  /* NOTE : This function should not be modified, when the function is needed,\r
-            the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.\r
-   */\r
-}\r
-\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  Register a user DFSDM filter callback\r
-  *         to be used instead of the weak predefined callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  CallbackID ID of the callback to be registered.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.\r
-  * @param  pCallback pointer to the callback function.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
-                                                    HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,\r
-                                                    pDFSDM_Filter_CallbackTypeDef      pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* update the error code */\r
-    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-    /* update return status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
-    {\r
-      switch (CallbackID)\r
-      {\r
-        case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :\r
-          hdfsdm_filter->RegConvCpltCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :\r
-          hdfsdm_filter->RegConvHalfCpltCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :\r
-          hdfsdm_filter->InjConvCpltCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :\r
-          hdfsdm_filter->InjConvHalfCpltCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_FILTER_ERROR_CB_ID :\r
-          hdfsdm_filter->ErrorCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
-          hdfsdm_filter->MspInitCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
-          hdfsdm_filter->MspDeInitCallback = pCallback;\r
-          break;\r
-        default :\r
-          /* update the error code */\r
-          hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-          /* update return status */\r
-          status = HAL_ERROR;\r
-          break;\r
-      }\r
-    }\r
-    else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)\r
-    {\r
-      switch (CallbackID)\r
-      {\r
-        case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
-          hdfsdm_filter->MspInitCallback = pCallback;\r
-          break;\r
-        case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
-          hdfsdm_filter->MspDeInitCallback = pCallback;\r
-          break;\r
-        default :\r
-          /* update the error code */\r
-          hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-          /* update return status */\r
-          status = HAL_ERROR;\r
-          break;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* update the error code */\r
-      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-      /* update return status */\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister a user DFSDM filter callback.\r
-  *         DFSDM filter callback is redirected to the weak predefined callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  CallbackID ID of the callback to be unregistered.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.\r
-  *           @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,\r
-                                                      HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :\r
-        hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;\r
-        break;\r
-      case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :\r
-        hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;\r
-        break;\r
-      case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :\r
-        hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;\r
-        break;\r
-      case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :\r
-        hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;\r
-        break;\r
-      case HAL_DFSDM_FILTER_ERROR_CB_ID :\r
-        hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;\r
-        break;\r
-      case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
-        hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;\r
-        break;\r
-      case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
-        hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;\r
-        break;\r
-      default :\r
-        /* update the error code */\r
-        hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-        /* update return status */\r
-        status = HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_DFSDM_FILTER_MSPINIT_CB_ID :\r
-        hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;\r
-        break;\r
-      case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :\r
-        hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;\r
-        break;\r
-      default :\r
-        /* update the error code */\r
-        hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-        /* update return status */\r
-        status = HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* update the error code */\r
-    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-    /* update return status */\r
-    status = HAL_ERROR;\r
-  }\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register a user DFSDM filter analog watchdog callback\r
-  *         to be used instead of the weak predefined callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  pCallback pointer to the DFSDM filter analog watchdog callback function.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,\r
-                                                       pDFSDM_Filter_AwdCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* update the error code */\r
-    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-    /* update return status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
-    {\r
-      hdfsdm_filter->AwdCallback = pCallback;\r
-    }\r
-    else\r
-    {\r
-      /* update the error code */\r
-      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-      /* update return status */\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister a user DFSDM filter analog watchdog callback.\r
-  *         DFSDM filter AWD callback is redirected to the weak predefined callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)\r
-  {\r
-    hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;\r
-  }\r
-  else\r
-  {\r
-    /* update the error code */\r
-    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;\r
-    /* update return status */\r
-    status = HAL_ERROR;\r
-  }\r
-  return status;\r
-}\r
-#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r
- *  @brief    Filter control functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-                    ##### Filter control functions #####\r
-  ==============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Select channel and enable/disable continuous mode for regular conversion.\r
-      (+) Select channels for injected conversion.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  This function allows to select channel and to enable/disable\r
-  *         continuous mode for regular conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Channel for regular conversion.\r
-  *         This parameter can be a value of @ref DFSDM_Channel_Selection.\r
-  * @param  ContinuousMode Enable/disable continuous mode for regular conversion.\r
-  *         This parameter can be a value of @ref DFSDM_ContinuousMode.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                   uint32_t                    Channel,\r
-                                                   uint32_t                    ContinuousMode)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));\r
-  assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r
-  {\r
-    /* Configure channel and continuous mode for regular conversion */\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);\r
-    if (ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)\r
-    {\r
-      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)(((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |\r
-                                                    DFSDM_FLTCR1_RCONT);\r
-    }\r
-    else\r
-    {\r
-      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);\r
-    }\r
-    /* Store continuous mode information */\r
-    hdfsdm_filter->RegularContMode = ContinuousMode;\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to select channels for injected conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Channels for injected conversion.\r
-  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                   uint32_t                    Channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r
-  {\r
-    /* Configure channel for injected conversion */\r
-    hdfsdm_filter->Instance->FLTJCHGR = (uint32_t)(Channel & DFSDM_LSB_MASK);\r
-    /* Store number of injected channels */\r
-    hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);\r
-    /* Update number of injected channels remaining */\r
-    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
-                                      hdfsdm_filter->InjectedChannelsNbr : 1U;\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r
- *  @brief    Filter operation functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-                    ##### Filter operation functions #####\r
-  ==============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Start conversion of regular/injected channel.\r
-      (+) Poll for the end of regular/injected conversion.\r
-      (+) Stop conversion of regular/injected channel.\r
-      (+) Start conversion of regular/injected channel and enable interrupt.\r
-      (+) Call the callback functions at the end of regular/injected conversions.\r
-      (+) Stop conversion of regular/injected channel and disable interrupt.\r
-      (+) Start conversion of regular/injected channel and enable DMA transfer.\r
-      (+) Stop conversion of regular/injected channel and disable DMA transfer.\r
-      (+) Start analog watchdog and enable interrupt.\r
-      (+) Call the callback function when analog watchdog occurs.\r
-      (+) Stop analog watchdog and disable interrupt.\r
-      (+) Start extreme detector.\r
-      (+) Stop extreme detector.\r
-      (+) Get result of regular channel conversion.\r
-      (+) Get result of injected channel conversion.\r
-      (+) Get extreme detector maximum and minimum values.\r
-      (+) Get conversion time.\r
-      (+) Handle DFSDM interrupt request.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  This function allows to start regular conversion in polling mode.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if injected conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
-  {\r
-    /* Start regular conversion */\r
-    DFSDM_RegConvStart(hdfsdm_filter);\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to poll for the end of regular conversion.\r
-  * @note   This function should be called only if regular conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Timeout Timeout value in milliseconds.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                       uint32_t                    Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    return HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Get timeout */\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait end of regular conversion */\r
-    while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)\r
-    {\r
-      /* Check the Timeout */\r
-      if (Timeout != HAL_MAX_DELAY)\r
-      {\r
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
-        {\r
-          /* Return timeout status */\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-    /* Check if overrun occurs */\r
-    if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)\r
-    {\r
-      /* Update error code and call error callback */\r
-      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-      hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
-#else\r
-      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
-#endif\r
-\r
-      /* Clear regular overrun flag */\r
-      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r
-    }\r
-    /* Update DFSDM filter state only if not continuous conversion and SW trigger */\r
-    if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
-        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
-    {\r
-      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
-                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
-    }\r
-    /* Return function status */\r
-    return HAL_OK;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop regular conversion in polling mode.\r
-  * @note   This function should be called only if regular conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop regular conversion */\r
-    DFSDM_RegConvStop(hdfsdm_filter);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start regular conversion in interrupt mode.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if injected conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
-  {\r
-    /* Enable interrupts for regular conversions */\r
-    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r
-\r
-    /* Start regular conversion */\r
-    DFSDM_RegConvStart(hdfsdm_filter);\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop regular conversion in interrupt mode.\r
-  * @note   This function should be called only if regular conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Disable interrupts for regular conversions */\r
-    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r
-\r
-    /* Stop regular conversion */\r
-    DFSDM_RegConvStop(hdfsdm_filter);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start regular conversion in DMA mode.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if injected conversion is ongoing.\r
-  *         Please note that data on buffer will contain signed regular conversion\r
-  *         value on 24 most significant bits and corresponding channel on 3 least\r
-  *         significant bits.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  pData The destination buffer address.\r
-  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                   int32_t                    *pData,\r
-                                                   uint32_t                    Length)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check destination address and length */\r
-  if ((pData == NULL) || (Length == 0U))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check that DMA is enabled for regular conversion */\r
-  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check parameters compatibility */\r
-  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
-           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\r
-           (Length != 1U))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
-           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check DFSDM filter state */\r
-  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
-  {\r
-    /* Set callbacks on DMA handler */\r
-    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r
-    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r
-    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \\r
-                                                   DFSDM_DMARegularHalfConvCplt : NULL;\r
-\r
-    /* Start DMA in interrupt mode */\r
-    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \\r
-                         (uint32_t) pData, Length) != HAL_OK)\r
-    {\r
-      /* Set DFSDM filter in error state */\r
-      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
-      status = HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      /* Start regular conversion */\r
-      DFSDM_RegConvStart(hdfsdm_filter);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start regular conversion in DMA mode and to get\r
-  *         only the 16 most significant bits of conversion.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if injected conversion is ongoing.\r
-  *         Please note that data on buffer will contain signed 16 most significant\r
-  *         bits of regular conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  pData The destination buffer address.\r
-  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                      int16_t                    *pData,\r
-                                                      uint32_t                    Length)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check destination address and length */\r
-  if ((pData == NULL) || (Length == 0U))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check that DMA is enabled for regular conversion */\r
-  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check parameters compatibility */\r
-  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
-           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\r
-           (Length != 1U))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
-           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check DFSDM filter state */\r
-  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r
-  {\r
-    /* Set callbacks on DMA handler */\r
-    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r
-    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r
-    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \\r
-                                                   DFSDM_DMARegularHalfConvCplt : NULL;\r
-\r
-    /* Start DMA in interrupt mode */\r
-    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \\r
-                         (uint32_t) pData, Length) != HAL_OK)\r
-    {\r
-      /* Set DFSDM filter in error state */\r
-      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
-      status = HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      /* Start regular conversion */\r
-      DFSDM_RegConvStart(hdfsdm_filter);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop regular conversion in DMA mode.\r
-  * @note   This function should be called only if regular conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop current DMA transfer */\r
-    if (HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)\r
-    {\r
-      /* Set DFSDM filter in error state */\r
-      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
-      status = HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      /* Stop regular conversion */\r
-      DFSDM_RegConvStop(hdfsdm_filter);\r
-    }\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get regular conversion value.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Corresponding channel of regular conversion.\r
-  * @retval Regular conversion value\r
-  */\r
-int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                        uint32_t                   *Channel)\r
-{\r
-  uint32_t reg;\r
-  int32_t  value;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(Channel != (void *)0);\r
-\r
-  /* Get value of data register for regular channel */\r
-  reg = hdfsdm_filter->Instance->FLTRDATAR;\r
-\r
-  /* Extract channel and regular conversion value */\r
-  *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);\r
-  /* Regular conversion value is a signed value located on 24 MSB of register */\r
-  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
-  reg &= DFSDM_FLTRDATAR_RDATA;\r
-  value = ((int32_t)reg) / 256;\r
-\r
-  /* return regular conversion value */\r
-  return value;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start injected conversion in polling mode.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if regular conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
-  {\r
-    /* Start injected conversion */\r
-    DFSDM_InjConvStart(hdfsdm_filter);\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to poll for the end of injected conversion.\r
-  * @note   This function should be called only if injected conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Timeout Timeout value in milliseconds.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                       uint32_t                    Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    return HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Get timeout */\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait end of injected conversions */\r
-    while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)\r
-    {\r
-      /* Check the Timeout */\r
-      if (Timeout != HAL_MAX_DELAY)\r
-      {\r
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
-        {\r
-          /* Return timeout status */\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-    /* Check if overrun occurs */\r
-    if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)\r
-    {\r
-      /* Update error code and call error callback */\r
-      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-      hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
-#else\r
-      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
-#endif\r
-\r
-      /* Clear injected overrun flag */\r
-      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r
-    }\r
-\r
-    /* Update remaining injected conversions */\r
-    hdfsdm_filter->InjConvRemaining--;\r
-    if (hdfsdm_filter->InjConvRemaining == 0U)\r
-    {\r
-      /* Update DFSDM filter state only if trigger is software */\r
-      if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
-      {\r
-        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
-                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
-      }\r
-\r
-      /* end of injected sequence, reset the value */\r
-      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
-                                        hdfsdm_filter->InjectedChannelsNbr : 1U;\r
-    }\r
-\r
-    /* Return function status */\r
-    return HAL_OK;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop injected conversion in polling mode.\r
-  * @note   This function should be called only if injected conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop injected conversion */\r
-    DFSDM_InjConvStop(hdfsdm_filter);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start injected conversion in interrupt mode.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if regular conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
-  {\r
-    /* Enable interrupts for injected conversions */\r
-    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r
-\r
-    /* Start injected conversion */\r
-    DFSDM_InjConvStart(hdfsdm_filter);\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop injected conversion in interrupt mode.\r
-  * @note   This function should be called only if injected conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Disable interrupts for injected conversions */\r
-    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r
-\r
-    /* Stop injected conversion */\r
-    DFSDM_InjConvStop(hdfsdm_filter);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start injected conversion in DMA mode.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if regular conversion is ongoing.\r
-  *         Please note that data on buffer will contain signed injected conversion\r
-  *         value on 24 most significant bits and corresponding channel on 3 least\r
-  *         significant bits.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  pData The destination buffer address.\r
-  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                    int32_t                    *pData,\r
-                                                    uint32_t                    Length)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check destination address and length */\r
-  if ((pData == NULL) || (Length == 0U))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check that DMA is enabled for injected conversion */\r
-  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check parameters compatibility */\r
-  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\r
-           (Length > hdfsdm_filter->InjConvRemaining))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check DFSDM filter state */\r
-  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
-  {\r
-    /* Set callbacks on DMA handler */\r
-    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r
-    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r
-    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \\r
-                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;\r
-\r
-    /* Start DMA in interrupt mode */\r
-    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \\r
-                         (uint32_t) pData, Length) != HAL_OK)\r
-    {\r
-      /* Set DFSDM filter in error state */\r
-      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
-      status = HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      /* Start injected conversion */\r
-      DFSDM_InjConvStart(hdfsdm_filter);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start injected conversion in DMA mode and to get\r
-  *         only the 16 most significant bits of conversion.\r
-  * @note   This function should be called only when DFSDM filter instance is\r
-  *         in idle state or if regular conversion is ongoing.\r
-  *         Please note that data on buffer will contain signed 16 most significant\r
-  *         bits of injected conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  pData The destination buffer address.\r
-  * @param  Length The length of data to be transferred from DFSDM filter to memory.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                                       int16_t                    *pData,\r
-                                                       uint32_t                    Length)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check destination address and length */\r
-  if ((pData == NULL) || (Length == 0U))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check that DMA is enabled for injected conversion */\r
-  else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check parameters compatibility */\r
-  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\r
-           (Length > hdfsdm_filter->InjConvRemaining))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\r
-           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Check DFSDM filter state */\r
-  else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\r
-           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r
-  {\r
-    /* Set callbacks on DMA handler */\r
-    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r
-    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r
-    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \\r
-                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;\r
-\r
-    /* Start DMA in interrupt mode */\r
-    if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \\r
-                         (uint32_t) pData, Length) != HAL_OK)\r
-    {\r
-      /* Set DFSDM filter in error state */\r
-      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
-      status = HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      /* Start injected conversion */\r
-      DFSDM_InjConvStart(hdfsdm_filter);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop injected conversion in DMA mode.\r
-  * @note   This function should be called only if injected conversion is ongoing.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\r
-      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Stop current DMA transfer */\r
-    if (HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)\r
-    {\r
-      /* Set DFSDM filter in error state */\r
-      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r
-      status = HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      /* Stop regular conversion */\r
-      DFSDM_InjConvStop(hdfsdm_filter);\r
-    }\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get injected conversion value.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Corresponding channel of injected conversion.\r
-  * @retval Injected conversion value\r
-  */\r
-int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                         uint32_t                   *Channel)\r
-{\r
-  uint32_t reg;\r
-  int32_t  value;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(Channel != (void *)0);\r
-\r
-  /* Get value of data register for injected channel */\r
-  reg = hdfsdm_filter->Instance->FLTJDATAR;\r
-\r
-  /* Extract channel and injected conversion value */\r
-  *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);\r
-  /* Injected conversion value is a signed value located on 24 MSB of register */\r
-  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
-  reg &= DFSDM_FLTJDATAR_JDATA;\r
-  value = ((int32_t)reg) / 256;\r
-\r
-  /* return regular conversion value */\r
-  return value;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start filter analog watchdog in interrupt mode.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  awdParam DFSDM filter analog watchdog parameters.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,\r
-                                              DFSDM_Filter_AwdParamTypeDef *awdParam)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));\r
-  assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));\r
-  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));\r
-  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));\r
-  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));\r
-  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Set analog watchdog data source */\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r
-    hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;\r
-\r
-    /* Set thresholds and break signals */\r
-    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r
-    hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \\r
-                                          awdParam->HighBreakSignal);\r
-    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r
-    hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \\r
-                                          awdParam->LowBreakSignal);\r
-\r
-    /* Set channels and interrupt for analog watchdog */\r
-    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);\r
-    hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \\r
-                                        DFSDM_FLTCR2_AWDIE);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop filter analog watchdog in interrupt mode.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Reset channels for analog watchdog and deactivate interrupt */\r
-    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);\r
-\r
-    /* Clear all analog watchdog flags */\r
-    hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);\r
-\r
-    /* Reset thresholds and break signals */\r
-    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r
-    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r
-\r
-    /* Reset analog watchdog data source */\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to start extreme detector feature.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Channels where extreme detector is enabled.\r
-  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                           uint32_t                    Channel)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Set channels for extreme detector */\r
-    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r
-    hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to stop extreme detector feature.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  __IO uint32_t     reg1;\r
-  __IO uint32_t     reg2;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Check DFSDM filter state */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\r
-      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r
-  {\r
-    /* Return error status */\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Reset channels for extreme detector */\r
-    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r
-\r
-    /* Clear extreme detector values */\r
-    reg1 = hdfsdm_filter->Instance->FLTEXMAX;\r
-    reg2 = hdfsdm_filter->Instance->FLTEXMIN;\r
-    UNUSED(reg1); /* To avoid GCC warning */\r
-    UNUSED(reg2); /* To avoid GCC warning */\r
-  }\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get extreme detector maximum value.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Corresponding channel.\r
-  * @retval Extreme detector maximum value\r
-  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.\r
-  */\r
-int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                       uint32_t                   *Channel)\r
-{\r
-  uint32_t reg;\r
-  int32_t  value;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(Channel != (void *)0);\r
-\r
-  /* Get value of extreme detector maximum register */\r
-  reg = hdfsdm_filter->Instance->FLTEXMAX;\r
-\r
-  /* Extract channel and extreme detector maximum value */\r
-  *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);\r
-  /* Extreme detector maximum value is a signed value located on 24 MSB of register */\r
-  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
-  reg &= DFSDM_FLTEXMAX_EXMAX;\r
-  value = ((int32_t)reg) / 256;\r
-\r
-  /* return extreme detector maximum value */\r
-  return value;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get extreme detector minimum value.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Corresponding channel.\r
-  * @retval Extreme detector minimum value\r
-  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.\r
-  */\r
-int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                       uint32_t                   *Channel)\r
-{\r
-  uint32_t reg;\r
-  int32_t  value;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-  assert_param(Channel != (void *)0);\r
-\r
-  /* Get value of extreme detector minimum register */\r
-  reg = hdfsdm_filter->Instance->FLTEXMIN;\r
-\r
-  /* Extract channel and extreme detector minimum value */\r
-  *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);\r
-  /* Extreme detector minimum value is a signed value located on 24 MSB of register */\r
-  /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */\r
-  reg &= DFSDM_FLTEXMIN_EXMIN;\r
-  value = ((int32_t)reg) / 256;\r
-\r
-  /* return extreme detector minimum value */\r
-  return value;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get conversion time value.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval Conversion time value\r
-  * @note   To get time in second, this value has to be divided by DFSDM clock frequency.\r
-  */\r
-uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  uint32_t reg;\r
-  uint32_t value;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r
-\r
-  /* Get value of conversion timer register */\r
-  reg = hdfsdm_filter->Instance->FLTCNVTIMR;\r
-\r
-  /* Extract conversion time value */\r
-  value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);\r
-\r
-  /* return extreme detector minimum value */\r
-  return value;\r
-}\r
-\r
-/**\r
-  * @brief  This function handles the DFSDM interrupts.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Get FTLISR and FLTCR2 register values */\r
-  const uint32_t temp_fltisr = hdfsdm_filter->Instance->FLTISR;\r
-  const uint32_t temp_fltcr2 = hdfsdm_filter->Instance->FLTCR2;\r
-\r
-  /* Check if overrun occurs during regular conversion */\r
-  if (((temp_fltisr & DFSDM_FLTISR_ROVRF) != 0U) && \\r
-      ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U))\r
-  {\r
-    /* Clear regular overrun flag */\r
-    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r
-\r
-    /* Update error code */\r
-    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r
-\r
-    /* Call error callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-    hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
-#else\r
-    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
-#endif\r
-  }\r
-  /* Check if overrun occurs during injected conversion */\r
-  else if (((temp_fltisr & DFSDM_FLTISR_JOVRF) != 0U) && \\r
-           ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U))\r
-  {\r
-    /* Clear injected overrun flag */\r
-    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r
-\r
-    /* Update error code */\r
-    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r
-\r
-    /* Call error callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-    hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
-#else\r
-    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
-#endif\r
-  }\r
-  /* Check if end of regular conversion */\r
-  else if (((temp_fltisr & DFSDM_FLTISR_REOCF) != 0U) && \\r
-           ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))\r
-  {\r
-    /* Call regular conversion complete callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-    hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);\r
-#else\r
-    HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r
-#endif\r
-\r
-    /* End of conversion if mode is not continuous and software trigger */\r
-    if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\r
-        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
-    {\r
-      /* Disable interrupts for regular conversions */\r
-      hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);\r
-\r
-      /* Update DFSDM filter state */\r
-      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
-                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
-    }\r
-  }\r
-  /* Check if end of injected conversion */\r
-  else if (((temp_fltisr & DFSDM_FLTISR_JEOCF) != 0U) && \\r
-           ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))\r
-  {\r
-    /* Call injected conversion complete callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-    hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);\r
-#else\r
-    HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r
-#endif\r
-\r
-    /* Update remaining injected conversions */\r
-    hdfsdm_filter->InjConvRemaining--;\r
-    if (hdfsdm_filter->InjConvRemaining == 0U)\r
-    {\r
-      /* End of conversion if trigger is software */\r
-      if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
-      {\r
-        /* Disable interrupts for injected conversions */\r
-        hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);\r
-\r
-        /* Update DFSDM filter state */\r
-        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
-                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
-      }\r
-      /* end of injected sequence, reset the value */\r
-      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
-                                        hdfsdm_filter->InjectedChannelsNbr : 1U;\r
-    }\r
-  }\r
-  /* Check if analog watchdog occurs */\r
-  else if (((temp_fltisr & DFSDM_FLTISR_AWDF) != 0U) && \\r
-           ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U))\r
-  {\r
-    uint32_t reg;\r
-    uint32_t threshold;\r
-    uint32_t channel = 0;\r
-\r
-    /* Get channel and threshold */\r
-    reg = hdfsdm_filter->Instance->FLTAWSR;\r
-    threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;\r
-    if (threshold == DFSDM_AWD_HIGH_THRESHOLD)\r
-    {\r
-      reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;\r
-    }\r
-    while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U)))\r
-    {\r
-      channel++;\r
-      reg = reg >> 1;\r
-    }\r
-    /* Clear analog watchdog flag */\r
-    hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \\r
-                                        (1UL << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \\r
-                                        (1UL << channel);\r
-\r
-    /* Call analog watchdog callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-    hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);\r
-#else\r
-    HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);\r
-#endif\r
-  }\r
-  /* Check if clock absence occurs */\r
-  else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\r
-           ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \\r
-           ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U))\r
-  {\r
-    uint32_t reg;\r
-    uint32_t channel = 0;\r
-\r
-    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);\r
-\r
-    while (channel < DFSDM1_CHANNEL_NUMBER)\r
-    {\r
-      /* Check if flag is set and corresponding channel is enabled */\r
-      if (((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL))\r
-      {\r
-        /* Check clock absence has been enabled for this channel */\r
-        if ((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)\r
-        {\r
-          /* Clear clock absence flag */\r
-          hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));\r
-\r
-          /* Call clock absence callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-          a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);\r
-#else\r
-          HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);\r
-#endif\r
-        }\r
-      }\r
-      channel++;\r
-      reg = reg >> 1;\r
-    }\r
-  }\r
-  /* Check if short circuit detection occurs */\r
-  else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\r
-           ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \\r
-           ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U))\r
-  {\r
-    uint32_t reg;\r
-    uint32_t channel = 0;\r
-\r
-    /* Get channel */\r
-    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);\r
-    while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U)))\r
-    {\r
-      channel++;\r
-      reg = reg >> 1;\r
-    }\r
-\r
-    /* Clear short circuit detection flag */\r
-    hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));\r
-\r
-    /* Call short circuit detection callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-    a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);\r
-#else\r
-    HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);\r
-#endif\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Regular conversion complete callback.\r
-  * @note   In interrupt mode, user has to read conversion value in this function\r
-  *         using HAL_DFSDM_FilterGetRegularValue.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Half regular conversion complete callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Injected conversion complete callback.\r
-  * @note   In interrupt mode, user has to read conversion value in this function\r
-  *         using HAL_DFSDM_FilterGetInjectedValue.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Half injected conversion complete callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Filter analog watchdog callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @param  Channel Corresponding channel.\r
-  * @param  Threshold Low or high threshold has been reached.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
-                                        uint32_t Channel, uint32_t Threshold)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-  UNUSED(Channel);\r
-  UNUSED(Threshold);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Error callback.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hdfsdm_filter);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r
- *  @brief    Filter state functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-                     ##### Filter state functions #####\r
-  ==============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Get the DFSDM filter state.\r
-      (+) Get the DFSDM filter error.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  This function allows to get the current DFSDM filter handle state.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval DFSDM filter state.\r
-  */\r
-HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Return DFSDM filter handle state */\r
-  return hdfsdm_filter->State;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get the current DFSDM filter error.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval DFSDM filter error code.\r
-  */\r
-uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  return hdfsdm_filter->ErrorCode;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of exported functions -------------------------------------------------*/\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  DMA half transfer complete callback for regular conversion.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Get DFSDM filter handle */\r
-  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  /* Call regular half conversion complete callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);\r
-#else\r
-  HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  DMA transfer complete callback for regular conversion.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Get DFSDM filter handle */\r
-  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  /* Call regular conversion complete callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);\r
-#else\r
-  HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  DMA half transfer complete callback for injected conversion.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Get DFSDM filter handle */\r
-  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  /* Call injected half conversion complete callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);\r
-#else\r
-  HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  DMA transfer complete callback for injected conversion.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Get DFSDM filter handle */\r
-  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  /* Call injected conversion complete callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);\r
-#else\r
-  HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  DMA error callback.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Get DFSDM filter handle */\r
-  DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  /* Update error code */\r
-  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;\r
-\r
-  /* Call error callback */\r
-#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
-  hdfsdm_filter->ErrorCallback(hdfsdm_filter);\r
-#else\r
-  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get the number of injected channels.\r
-  * @param  Channels bitfield of injected channels.\r
-  * @retval Number of injected channels.\r
-  */\r
-static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)\r
-{\r
-  uint32_t nbChannels = 0;\r
-  uint32_t tmp;\r
-\r
-  /* Get the number of channels from bitfield */\r
-  tmp = (uint32_t)(Channels & DFSDM_LSB_MASK);\r
-  while (tmp != 0U)\r
-  {\r
-    if ((tmp & 1U) != 0U)\r
-    {\r
-      nbChannels++;\r
-    }\r
-    tmp = (uint32_t)(tmp >> 1);\r
-  }\r
-  return nbChannels;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to get the channel number from channel instance.\r
-  * @param  Instance DFSDM channel instance.\r
-  * @retval Channel number.\r
-  */\r
-static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)\r
-{\r
-  uint32_t channel;\r
-\r
-  /* Get channel from instance */\r
-  if (Instance == DFSDM1_Channel0)\r
-  {\r
-    channel = 0;\r
-  }\r
-  else if (Instance == DFSDM1_Channel1)\r
-  {\r
-    channel = 1;\r
-  }\r
-  else if (Instance == DFSDM1_Channel2)\r
-  {\r
-    channel = 2;\r
-  }\r
-  else if (Instance == DFSDM1_Channel3)\r
-  {\r
-    channel = 3;\r
-  }\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
-    defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
-    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-  else if (Instance == DFSDM1_Channel4)\r
-  {\r
-    channel = 4;\r
-  }\r
-  else if (Instance == DFSDM1_Channel5)\r
-  {\r
-    channel = 5;\r
-  }\r
-  else if (Instance == DFSDM1_Channel6)\r
-  {\r
-    channel = 6;\r
-  }\r
-  else if (Instance == DFSDM1_Channel7)\r
-  {\r
-    channel = 7;\r
-  }\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-  else\r
-  {\r
-    channel = 0;\r
-  }\r
-\r
-  return channel;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to really start regular conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Check regular trigger */\r
-  if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)\r
-  {\r
-    /* Software start of regular conversion */\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
-  }\r
-  else /* synchronous trigger */\r
-  {\r
-    /* Disable DFSDM filter */\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
-\r
-    /* Set RSYNC bit in DFSDM_FLTCR1 register */\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;\r
-\r
-    /* Enable DFSDM  filter */\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
-\r
-    /* If injected conversion was in progress, restart it */\r
-    if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)\r
-    {\r
-      if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
-      {\r
-        hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
-      }\r
-      /* Update remaining injected conversions */\r
-      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
-                                        hdfsdm_filter->InjectedChannelsNbr : 1U;\r
-    }\r
-  }\r
-  /* Update DFSDM filter state */\r
-  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\r
-                         HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to really stop regular conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Disable DFSDM filter */\r
-  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
-\r
-  /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */\r
-  if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r
-  }\r
-\r
-  /* Enable DFSDM filter */\r
-  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
-\r
-  /* If injected conversion was in progress, restart it */\r
-  if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)\r
-  {\r
-    if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
-    {\r
-      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
-    }\r
-    /* Update remaining injected conversions */\r
-    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
-                                      hdfsdm_filter->InjectedChannelsNbr : 1U;\r
-  }\r
-\r
-  /* Update DFSDM filter state */\r
-  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\r
-                         HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to really start injected conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Check injected trigger */\r
-  if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r
-  {\r
-    /* Software start of injected conversion */\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r
-  }\r
-  else /* external or synchronous trigger */\r
-  {\r
-    /* Disable DFSDM filter */\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
-\r
-    if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
-    {\r
-      /* Set JSYNC bit in DFSDM_FLTCR1 register */\r
-      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;\r
-    }\r
-    else /* external trigger */\r
-    {\r
-      /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r
-      hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;\r
-    }\r
-\r
-    /* Enable DFSDM filter */\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
-\r
-    /* If regular conversion was in progress, restart it */\r
-    if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \\r
-        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
-    {\r
-      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
-    }\r
-  }\r
-  /* Update DFSDM filter state */\r
-  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\r
-                         HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;\r
-}\r
-\r
-/**\r
-  * @brief  This function allows to really stop injected conversion.\r
-  * @param  hdfsdm_filter DFSDM filter handle.\r
-  * @retval None\r
-  */\r
-static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r
-{\r
-  /* Disable DFSDM filter */\r
-  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r
-\r
-  /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */\r
-  if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);\r
-  }\r
-  else if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)\r
-  {\r
-    /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r
-    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-\r
-  /* Enable DFSDM filter */\r
-  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r
-\r
-  /* If regular conversion was in progress, restart it */\r
-  if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \\r
-      (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r
-  {\r
-    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r
-  }\r
-\r
-  /* Update remaining injected conversions */\r
-  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\r
-                                    hdfsdm_filter->InjectedChannelsNbr : 1U;\r
-\r
-  /* Update DFSDM filter state */\r
-  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\r
-                         HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-/* End of private functions --------------------------------------------------*/\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* HAL_DFSDM_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
deleted file mode 100644 (file)
index 7746d0e..0000000
+++ /dev/null
@@ -1,1175 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_dma.c\r
-  * @author  MCD Application Team\r
-  * @brief   DMA HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Direct Memory Access (DMA) peripheral:\r
-  *           + Initialization and de-initialization functions\r
-  *           + IO operation functions\r
-  *           + Peripheral State and errors functions\r
-  @verbatim\r
-  ==============================================================================\r
-                        ##### How to use this driver #####\r
-  ==============================================================================\r
-  [..]\r
-   (#) Enable and configure the peripheral to be connected to the DMA Channel\r
-       (except for internal SRAM / FLASH memories: no initialization is\r
-       necessary). Please refer to the Reference manual for connection between peripherals\r
-       and DMA requests.\r
-\r
-   (#) For a given Channel, program the required configuration through the following parameters:\r
-       Channel request, Transfer Direction, Source and Destination data formats,\r
-       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode\r
-       using HAL_DMA_Init() function.\r
-\r
-       Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX\r
-       thanks to:\r
-      (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;\r
-      (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();\r
-\r
-   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error\r
-       detection.\r
-\r
-   (#) Use HAL_DMA_Abort() function to abort the current transfer\r
-\r
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
-\r
-     *** Polling mode IO operation ***\r
-     =================================\r
-     [..]\r
-       (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source\r
-           address and destination address and the Length of data to be transferred\r
-       (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this\r
-           case a fixed Timeout can be configured by User depending from his application.\r
-\r
-     *** Interrupt mode IO operation ***\r
-     ===================================\r
-     [..]\r
-       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
-       (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()\r
-       (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of\r
-           Source address and destination address and the Length of data to be transferred.\r
-           In this case the DMA interrupt is configured\r
-       (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
-       (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can\r
-              add his own function to register callbacks with HAL_DMA_RegisterCallback().\r
-\r
-     *** DMA HAL driver macros list ***\r
-     =============================================\r
-     [..]\r
-       Below the list of macros in DMA HAL driver.\r
-\r
-       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.\r
-       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.\r
-       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.\r
-       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.\r
-       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.\r
-       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.\r
-       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.\r
-\r
-     [..]\r
-      (@) You can refer to the DMA HAL driver header file for more useful macros\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DMA DMA\r
-  * @brief DMA HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_DMA_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup DMA_Private_Functions DMA Private Functions\r
-  * @{\r
-  */\r
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
-#if defined(DMAMUX1)\r
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);\r
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);\r
-#endif /* DMAMUX1 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
- *  @brief   Initialization and de-initialization functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-             ##### Initialization and de-initialization functions  #####\r
- ===============================================================================\r
-    [..]\r
-    This section provides functions allowing to initialize the DMA Channel source\r
-    and destination addresses, incrementation and data sizes, transfer direction,\r
-    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.\r
-    [..]\r
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
-    reference manual.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initialize the DMA according to the specified\r
-  *         parameters in the DMA_InitTypeDef and initialize the associated handle.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified DMA Channel.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
-{\r
-  uint32_t tmp;\r
-\r
-  /* Check the DMA handle allocation */\r
-  if(hdma == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
-\r
-  assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));\r
-\r
-  /* Compute the channel index */\r
-  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
-  {\r
-    /* DMA1 */\r
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
-    hdma->DmaBaseAddress = DMA1;\r
-  }\r
-  else\r
-  {\r
-    /* DMA2 */\r
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;\r
-    hdma->DmaBaseAddress = DMA2;\r
-  }\r
-\r
-  /* Change DMA peripheral state */\r
-  hdma->State = HAL_DMA_STATE_BUSY;\r
-\r
-  /* Get the CR register value */\r
-  tmp = hdma->Instance->CCR;\r
-\r
-  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */\r
-  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |\r
-                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |\r
-                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));\r
-\r
-  /* Prepare the DMA Channel configuration */\r
-  tmp |=  hdma->Init.Direction        |\r
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |\r
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
-          hdma->Init.Mode                | hdma->Init.Priority;\r
-\r
-  /* Write to DMA Channel CR register */\r
-  hdma->Instance->CCR = tmp;\r
-\r
-#if defined(DMAMUX1)\r
-  /* Initialize parameters for DMAMUX channel :\r
-     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask\r
-  */\r
-  DMA_CalcDMAMUXChannelBaseAndMask(hdma);\r
-\r
-  if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
-  {\r
-    /* if memory to memory force the request to 0*/\r
-    hdma->Init.Request = DMA_REQUEST_MEM2MEM;\r
-  }\r
-\r
-  /* Set peripheral request  to DMAMUX channel */\r
-  hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);\r
-\r
-  /* Clear the DMAMUX synchro overrun flag */\r
-  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
-\r
-  if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))\r
-  {\r
-    /* Initialize parameters for DMAMUX request generator :\r
-       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask\r
-    */\r
-    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);\r
-\r
-    /* Reset the DMAMUX request generator register*/\r
-    hdma->DMAmuxRequestGen->RGCR = 0U;\r
-\r
-    /* Clear the DMAMUX request generator overrun flag */\r
-    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
-  }\r
-  else\r
-  {\r
-    hdma->DMAmuxRequestGen = 0U;\r
-    hdma->DMAmuxRequestGenStatus = 0U;\r
-    hdma->DMAmuxRequestGenStatusMask = 0U;\r
-  }\r
-#endif /* DMAMUX1 */\r
-\r
-#if !defined (DMAMUX1)\r
-\r
-  /* Set request selection */\r
-  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)\r
-  {\r
-    /* Write to DMA channel selection register */\r
-    if (DMA1 == hdma->DmaBaseAddress)\r
-    {\r
-      /* Reset request selection for DMA1 Channelx */\r
-      DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
-\r
-      /* Configure request selection for DMA1 Channelx */\r
-      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));\r
-    }\r
-    else /* DMA2 */\r
-    {\r
-      /* Reset request selection for DMA2 Channelx */\r
-      DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
-\r
-      /* Configure request selection for DMA2 Channelx */\r
-      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));\r
-    }\r
-  }\r
-\r
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
-       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */\r
-       /* STM32L496xx || STM32L4A6xx                                              */\r
-\r
-  /* Initialise the error code */\r
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
-\r
-  /* Initialize the DMA state*/\r
-  hdma->State = HAL_DMA_STATE_READY;\r
-\r
-  /* Allocate lock resource and initialize it */\r
-  hdma->Lock = HAL_UNLOCKED;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitialize the DMA peripheral.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA Channel.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
-{\r
-\r
-  /* Check the DMA handle allocation */\r
-  if (NULL == hdma )\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
-\r
-  /* Disable the selected DMA Channelx */\r
-  __HAL_DMA_DISABLE(hdma);\r
-\r
-  /* Compute the channel index */\r
-  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
-  {\r
-    /* DMA1 */\r
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;\r
-    hdma->DmaBaseAddress = DMA1;\r
-  }\r
-  else\r
-  {\r
-    /* DMA2 */\r
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;\r
-    hdma->DmaBaseAddress = DMA2;\r
-  }\r
-\r
-  /* Reset DMA Channel control register */\r
-  hdma->Instance->CCR = 0U;\r
-\r
-  /* Clear all flags */\r
-  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
-\r
-#if !defined (DMAMUX1)\r
-\r
-  /* Reset DMA channel selection register */\r
-  if (DMA1 == hdma->DmaBaseAddress)\r
-  {\r
-    /* DMA1 */\r
-    DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
-  }\r
-  else\r
-  {\r
-    /* DMA2 */\r
-    DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));\r
-  }\r
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */\r
-       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */\r
-       /* STM32L496xx || STM32L4A6xx                                              */\r
-\r
-#if defined(DMAMUX1)\r
-\r
-  /* Initialize parameters for DMAMUX channel :\r
-     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */\r
-\r
-  DMA_CalcDMAMUXChannelBaseAndMask(hdma);\r
-\r
-  /* Reset the DMAMUX channel that corresponds to the DMA channel */\r
-  hdma->DMAmuxChannel->CCR = 0U;\r
-\r
-  /* Clear the DMAMUX synchro overrun flag */\r
-  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
-\r
-  /* Reset Request generator parameters if any */\r
-  if(((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))\r
-  {\r
-    /* Initialize parameters for DMAMUX request generator :\r
-       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask\r
-    */\r
-    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);\r
-\r
-    /* Reset the DMAMUX request generator register*/\r
-    hdma->DMAmuxRequestGen->RGCR = 0U;\r
-\r
-    /* Clear the DMAMUX request generator overrun flag */\r
-    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
-  }\r
-\r
-  hdma->DMAmuxRequestGen = 0U;\r
-  hdma->DMAmuxRequestGenStatus = 0U;\r
-  hdma->DMAmuxRequestGenStatusMask = 0U;\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-  /* Clean callbacks */\r
-  hdma->XferCpltCallback = NULL;\r
-  hdma->XferHalfCpltCallback = NULL;\r
-  hdma->XferErrorCallback = NULL;\r
-  hdma->XferAbortCallback = NULL;\r
-\r
-  /* Initialise the error code */\r
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
-\r
-  /* Initialize the DMA state */\r
-  hdma->State = HAL_DMA_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hdma);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions\r
- *  @brief   Input and Output operation functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      #####  IO operation functions  #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Configure the source, destination address and data length and Start DMA transfer\r
-      (+) Configure the source, destination address and data length and\r
-          Start DMA transfer with interrupt\r
-      (+) Abort DMA transfer\r
-      (+) Poll for transfer complete\r
-      (+) Handle DMA interrupt request\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Start the DMA Transfer.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA Channel.\r
-  * @param  SrcAddress The source memory Buffer address\r
-  * @param  DstAddress The destination memory Buffer address\r
-  * @param  DataLength The length of data to be transferred from source to destination\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hdma);\r
-\r
-  if(HAL_DMA_STATE_READY == hdma->State)\r
-  {\r
-    /* Change DMA peripheral state */\r
-    hdma->State = HAL_DMA_STATE_BUSY;\r
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
-\r
-    /* Disable the peripheral */\r
-    __HAL_DMA_DISABLE(hdma);\r
-\r
-    /* Configure the source, destination address and the data length & clear flags*/\r
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
-\r
-    /* Enable the Peripheral */\r
-    __HAL_DMA_ENABLE(hdma);\r
-  }\r
-  else\r
-  {\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hdma);\r
-    status = HAL_BUSY;\r
-  }\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Start the DMA Transfer with interrupt enabled.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA Channel.\r
-  * @param  SrcAddress The source memory Buffer address\r
-  * @param  DstAddress The destination memory Buffer address\r
-  * @param  DataLength The length of data to be transferred from source to destination\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hdma);\r
-\r
-  if(HAL_DMA_STATE_READY == hdma->State)\r
-  {\r
-    /* Change DMA peripheral state */\r
-    hdma->State = HAL_DMA_STATE_BUSY;\r
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
-\r
-    /* Disable the peripheral */\r
-    __HAL_DMA_DISABLE(hdma);\r
-\r
-    /* Configure the source, destination address and the data length & clear flags*/\r
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
-\r
-    /* Enable the transfer complete interrupt */\r
-    /* Enable the transfer Error interrupt */\r
-    if(NULL != hdma->XferHalfCpltCallback )\r
-    {\r
-      /* Enable the Half transfer complete interrupt as well */\r
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
-    }\r
-    else\r
-    {\r
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));\r
-    }\r
-\r
-#ifdef DMAMUX1\r
-\r
-    /* Check if DMAMUX Synchronization is enabled*/\r
-    if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)\r
-    {\r
-      /* Enable DMAMUX sync overrun IT*/\r
-      hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;\r
-    }\r
-\r
-    if(hdma->DMAmuxRequestGen != 0U)\r
-    {\r
-      /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/\r
-      /* enable the request gen overrun IT*/\r
-      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;\r
-    }\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-    /* Enable the Peripheral */\r
-    __HAL_DMA_ENABLE(hdma);\r
-  }\r
-  else\r
-  {\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hdma);\r
-\r
-    /* Remain BUSY */\r
-    status = HAL_BUSY;\r
-  }\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Abort the DMA Transfer.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA Channel.\r
-    * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check the DMA peripheral state */\r
-  if(hdma->State != HAL_DMA_STATE_BUSY)\r
-  {\r
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hdma);\r
-\r
-    return HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Disable DMA IT */\r
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
-\r
-#if defined(DMAMUX1)\r
-    /* disable the DMAMUX sync overrun IT*/\r
-    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
-#endif /* DMAMUX1 */\r
-\r
-    /* Disable the channel */\r
-    __HAL_DMA_DISABLE(hdma);\r
-\r
-    /* Clear all flags */\r
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
-\r
-#if defined(DMAMUX1)\r
-    /* Clear the DMAMUX synchro overrun flag */\r
-    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
-\r
-    if(hdma->DMAmuxRequestGen != 0U)\r
-    {\r
-      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/\r
-      /* disable the request gen overrun IT*/\r
-      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
-\r
-      /* Clear the DMAMUX request generator overrun flag */\r
-      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
-    }\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-    /* Change the DMA state */\r
-    hdma->State = HAL_DMA_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hdma);\r
-\r
-    return status;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Aborts the DMA Transfer in Interrupt mode.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *                 the configuration information for the specified DMA Channel.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if(HAL_DMA_STATE_BUSY != hdma->State)\r
-  {\r
-    /* no transfer ongoing */\r
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
-\r
-    status = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Disable DMA IT */\r
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
-\r
-    /* Disable the channel */\r
-    __HAL_DMA_DISABLE(hdma);\r
-\r
-#if defined(DMAMUX1)\r
-    /* disable the DMAMUX sync overrun IT*/\r
-    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
-\r
-    /* Clear all flags */\r
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
-\r
-    /* Clear the DMAMUX synchro overrun flag */\r
-    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
-\r
-    if(hdma->DMAmuxRequestGen != 0U)\r
-    {\r
-      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/\r
-      /* disable the request gen overrun IT*/\r
-      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
-\r
-      /* Clear the DMAMUX request generator overrun flag */\r
-      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
-    }\r
-\r
-#else\r
-    /* Clear all flags */\r
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
-#endif /* DMAMUX1 */\r
-\r
-    /* Change the DMA state */\r
-    hdma->State = HAL_DMA_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hdma);\r
-\r
-    /* Call User Abort callback */\r
-    if(hdma->XferAbortCallback != NULL)\r
-    {\r
-      hdma->XferAbortCallback(hdma);\r
-    }\r
-  }\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Polling for transfer complete.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *                  the configuration information for the specified DMA Channel.\r
-  * @param  CompleteLevel Specifies the DMA level complete.\r
-  * @param  Timeout       Timeout duration.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r
-{\r
-  uint32_t temp;\r
-  uint32_t tickstart;\r
-\r
-  if(HAL_DMA_STATE_BUSY != hdma->State)\r
-  {\r
-    /* no transfer ongoing */\r
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
-    __HAL_UNLOCK(hdma);\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Polling mode not supported in circular mode */\r
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)\r
-  {\r
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Get the level transfer complete flag */\r
-  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)\r
-  {\r
-    /* Transfer Complete flag */\r
-    temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);\r
-  }\r
-  else\r
-  {\r
-    /* Half Transfer Complete flag */\r
-    temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);\r
-  }\r
-\r
-  /* Get tick */\r
-  tickstart = HAL_GetTick();\r
-\r
-  while((hdma->DmaBaseAddress->ISR & temp) == 0U)\r
-  {\r
-    if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)\r
-    {\r
-      /* When a DMA transfer error occurs */\r
-      /* A hardware clear of its EN bits is performed */\r
-      /* Clear all flags */\r
-      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
-\r
-      /* Update error code */\r
-      hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
-\r
-      /* Change the DMA state */\r
-      hdma->State= HAL_DMA_STATE_READY;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hdma);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-    /* Check for the Timeout */\r
-    if(Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if(((HAL_GetTick() - tickstart) > Timeout) ||  (Timeout == 0U))\r
-      {\r
-        /* Update error code */\r
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
-\r
-        /* Change the DMA state */\r
-        hdma->State = HAL_DMA_STATE_READY;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hdma);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-  }\r
-\r
-#if defined(DMAMUX1)\r
-  /*Check for DMAMUX Request generator (if used) overrun status */\r
-  if(hdma->DMAmuxRequestGen != 0U)\r
-  {\r
-    /* if using DMAMUX request generator Check for DMAMUX request generator overrun */\r
-    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)\r
-    {\r
-      /* Disable the request gen overrun interrupt */\r
-      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;\r
-\r
-      /* Clear the DMAMUX request generator overrun flag */\r
-      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
-\r
-      /* Update error code */\r
-      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;\r
-    }\r
-  }\r
-\r
-  /* Check for DMAMUX Synchronization overrun */\r
-  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)\r
-  {\r
-    /* Clear the DMAMUX synchro overrun flag */\r
-    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
-\r
-    /* Update error code */\r
-    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;\r
-  }\r
-#endif /* DMAMUX1 */\r
-\r
-  if(HAL_DMA_FULL_TRANSFER == CompleteLevel)\r
-  {\r
-    /* Clear the transfer complete flag */\r
-    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));\r
-\r
-    /* The selected Channelx EN bit is cleared (DMA is disabled and\r
-    all transfers are complete) */\r
-    hdma->State = HAL_DMA_STATE_READY;\r
-  }\r
-  else\r
-  {\r
-    /* Clear the half transfer complete flag */\r
-    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hdma);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handle DMA interrupt request.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA Channel.\r
-  * @retval None\r
-  */\r
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
-{\r
-  uint32_t flag_it = hdma->DmaBaseAddress->ISR;\r
-  uint32_t source_it = hdma->Instance->CCR;\r
-\r
-  /* Half Transfer Complete Interrupt management ******************************/\r
-  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))\r
-  {\r
-      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
-      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
-      {\r
-        /* Disable the half transfer interrupt */\r
-        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
-      }\r
-      /* Clear the half transfer complete flag */\r
-      hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);\r
-\r
-      /* DMA peripheral state is not updated in Half Transfer */\r
-      /* but in Transfer Complete case */\r
-\r
-      if(hdma->XferHalfCpltCallback != NULL)\r
-      {\r
-        /* Half transfer callback */\r
-        hdma->XferHalfCpltCallback(hdma);\r
-      }\r
-  }\r
-\r
-  /* Transfer Complete Interrupt management ***********************************/\r
-  else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))\r
-  {\r
-    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
-    {\r
-      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r
-      /* Disable the transfer complete and error interrupt */\r
-      /* if the DMA mode is not CIRCULAR  */\r
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);\r
-\r
-      /* Change the DMA state */\r
-      hdma->State = HAL_DMA_STATE_READY;\r
-    }\r
-    /* Clear the transfer complete flag */\r
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hdma);\r
-\r
-    if(hdma->XferCpltCallback != NULL)\r
-    {\r
-      /* Transfer complete callback */\r
-      hdma->XferCpltCallback(hdma);\r
-    }\r
-  }\r
-\r
-  /* Transfer Error Interrupt management **************************************/\r
-  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) !=  0U))\r
-  {\r
-    /* When a DMA transfer error occurs */\r
-    /* A hardware clear of its EN bits is performed */\r
-    /* Disable ALL DMA IT */\r
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
-\r
-    /* Clear all flags */\r
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
-\r
-    /* Update error code */\r
-    hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
-\r
-    /* Change the DMA state */\r
-    hdma->State = HAL_DMA_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hdma);\r
-\r
-    if (hdma->XferErrorCallback != NULL)\r
-    {\r
-      /* Transfer error callback */\r
-      hdma->XferErrorCallback(hdma);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Nothing To Do */\r
-  }\r
-  return;\r
-}\r
-\r
-/**\r
-  * @brief  Register callbacks\r
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\r
-  *                               the configuration information for the specified DMA Channel.\r
-  * @param  CallbackID           User Callback identifer\r
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
-  * @param  pCallback            pointer to private callbacsk function which has pointer to\r
-  *                               a DMA_HandleTypeDef structure as parameter.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hdma);\r
-\r
-  if(HAL_DMA_STATE_READY == hdma->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-     case  HAL_DMA_XFER_CPLT_CB_ID:\r
-           hdma->XferCpltCallback = pCallback;\r
-           break;\r
-\r
-     case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r
-           hdma->XferHalfCpltCallback = pCallback;\r
-           break;\r
-\r
-     case  HAL_DMA_XFER_ERROR_CB_ID:\r
-           hdma->XferErrorCallback = pCallback;\r
-           break;\r
-\r
-     case  HAL_DMA_XFER_ABORT_CB_ID:\r
-           hdma->XferAbortCallback = pCallback;\r
-           break;\r
-\r
-     default:\r
-           status = HAL_ERROR;\r
-           break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hdma);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister callbacks\r
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\r
-  *                               the configuration information for the specified DMA Channel.\r
-  * @param  CallbackID           User Callback identifer\r
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-    /* Process locked */\r
-  __HAL_LOCK(hdma);\r
-\r
-  if(HAL_DMA_STATE_READY == hdma->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-     case  HAL_DMA_XFER_CPLT_CB_ID:\r
-           hdma->XferCpltCallback = NULL;\r
-           break;\r
-\r
-     case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r
-           hdma->XferHalfCpltCallback = NULL;\r
-           break;\r
-\r
-     case  HAL_DMA_XFER_ERROR_CB_ID:\r
-           hdma->XferErrorCallback = NULL;\r
-           break;\r
-\r
-     case  HAL_DMA_XFER_ABORT_CB_ID:\r
-           hdma->XferAbortCallback = NULL;\r
-           break;\r
-\r
-    case   HAL_DMA_XFER_ALL_CB_ID:\r
-           hdma->XferCpltCallback = NULL;\r
-           hdma->XferHalfCpltCallback = NULL;\r
-           hdma->XferErrorCallback = NULL;\r
-           hdma->XferAbortCallback = NULL;\r
-           break;\r
-\r
-    default:\r
-           status = HAL_ERROR;\r
-           break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hdma);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-\r
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions\r
- *  @brief    Peripheral State and Errors functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-            ##### Peripheral State and Errors functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides functions allowing to\r
-      (+) Check the DMA state\r
-      (+) Get error code\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Return the DMA handle state.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA Channel.\r
-  * @retval HAL state\r
-  */\r
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Return DMA handle state */\r
-  return hdma->State;\r
-}\r
-\r
-/**\r
-  * @brief  Return the DMA error code.\r
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified DMA Channel.\r
-  * @retval DMA Error Code\r
-  */\r
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
-{\r
-  return hdma->ErrorCode;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup DMA_Private_Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Sets the DMA Transfer parameter.\r
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r
-  *                     the configuration information for the specified DMA Channel.\r
-  * @param  SrcAddress The source memory Buffer address\r
-  * @param  DstAddress The destination memory Buffer address\r
-  * @param  DataLength The length of data to be transferred from source to destination\r
-  * @retval HAL status\r
-  */\r
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
-{\r
-#if defined(DMAMUX1)\r
-  /* Clear the DMAMUX synchro overrun flag */\r
-  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
-\r
-  if(hdma->DMAmuxRequestGen != 0U)\r
-  {\r
-    /* Clear the DMAMUX request generator overrun flag */\r
-    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
-  }\r
-#endif\r
-\r
-  /* Clear all flags */\r
-  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));\r
-\r
-  /* Configure DMA Channel data length */\r
-  hdma->Instance->CNDTR = DataLength;\r
-\r
-  /* Memory to Peripheral */\r
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
-  {\r
-    /* Configure DMA Channel destination address */\r
-    hdma->Instance->CPAR = DstAddress;\r
-\r
-    /* Configure DMA Channel source address */\r
-    hdma->Instance->CMAR = SrcAddress;\r
-  }\r
-  /* Peripheral to Memory */\r
-  else\r
-  {\r
-    /* Configure DMA Channel source address */\r
-    hdma->Instance->CPAR = SrcAddress;\r
-\r
-    /* Configure DMA Channel destination address */\r
-    hdma->Instance->CMAR = DstAddress;\r
-  }\r
-}\r
-\r
-#if defined(DMAMUX1)\r
-\r
-/**\r
-  * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on channel number\r
-  * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains\r
-  *                     the configuration information for the specified DMA Channel.\r
-  * @retval None\r
-  */\r
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)\r
-{\r
-  uint32_t channel_number;\r
-\r
-  /* check if instance is not outside the DMA channel range */\r
-  if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)\r
-  {\r
-    /* DMA1 */\r
-    hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));\r
-  }\r
-  else\r
-  {\r
-    /* DMA2 */\r
-    hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));\r
-  }\r
-\r
-  channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;\r
-  hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;\r
-  hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1CU);\r
-}\r
-\r
-/**\r
-  * @brief  Updates the DMA handle with the DMAMUX  request generator params\r
-  * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains\r
-  *                     the configuration information for the specified DMA Channel.\r
-  * @retval None\r
-  */\r
-\r
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)\r
-{\r
-  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;\r
-\r
-  /* DMA Channels are connected to DMAMUX1 request generator blocks*/\r
-  hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));\r
-\r
-  hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;\r
-\r
-  /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/\r
-  hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);\r
-}\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_DMA_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
deleted file mode 100644 (file)
index fae98f1..0000000
+++ /dev/null
@@ -1,309 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_dma_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   DMA Extension HAL module driver\r
-  *         This file provides firmware functions to manage the following\r
-  *         functionalities of the DMA Extension peripheral:\r
-  *           + Extended features functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                        ##### How to use this driver #####\r
-  ==============================================================================\r
-  [..]\r
-  The DMA Extension HAL driver can be used as follows:\r
-\r
-   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
-   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
-       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
-       to respectively enable/disable the request generator.\r
-\r
-   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from\r
-       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.\r
-       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be\r
-       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project\r
-      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)\r
-\r
-     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r
-     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r
-     -@-  In Multi (Double) buffer mode, it is possible to update the base address for\r
-          the AHB memory port on the fly (DMA_CM0ARx or DMA_CM1ARx) when the channel is enabled.\r
-\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-#if defined(DMAMUX1)\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DMAEx DMAEx\r
-  * @brief DMA Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_DMA_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private Constants ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-\r
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions\r
- *  @brief   Extended features functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                #####  Extended features functions  #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-\r
-    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
-    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
-       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
-       to respectively enable/disable the request generator.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-\r
-/**\r
-  * @brief  Configure the DMAMUX synchronization parameters for a given DMA channel (instance).\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified DMA channel.\r
-  * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
-\r
-  assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));\r
-\r
-  assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));\r
-  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));\r
-  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));\r
-  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));\r
-\r
-  /*Check if the DMA state is ready */\r
-  if(hdma->State == HAL_DMA_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hdma);\r
-\r
-    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/\r
-    MODIFY_REG( hdma->DMAmuxChannel->CCR, \\r
-               (~DMAMUX_CxCR_DMAREQ_ID) , \\r
-               ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \\r
-               pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \\r
-                 ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));\r
-\r
-    /* Process UnLocked */\r
-    __HAL_UNLOCK(hdma);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    /*DMA State not Ready*/\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Configure the DMAMUX request generator block used by the given DMA channel (instance).\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified DMA channel.\r
-  * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :\r
-  *         contains the request generator parameters.\r
-  *\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
-\r
-  assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));\r
-\r
-  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));\r
-  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));\r
-\r
-  /* check if the DMA state is ready\r
-     and DMA is using a DMAMUX request generator block\r
-  */\r
-  if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hdma);\r
-\r
-    /* Set the request generator new parameters */\r
-    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \\r
-                                  ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \\r
-                                  pRequestGeneratorConfig->Polarity;\r
-   /* Process UnLocked */\r
-   __HAL_UNLOCK(hdma);\r
-\r
-   return HAL_OK;\r
- }\r
- else\r
- {\r
-   return HAL_ERROR;\r
- }\r
-}\r
-\r
-/**\r
-  * @brief  Enable the DMAMUX request generator block used by the given DMA channel (instance).\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified DMA channel.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
-\r
-  /* check if the DMA state is ready\r
-     and DMA is using a DMAMUX request generator block\r
-  */\r
-  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))\r
-  {\r
-\r
-    /* Enable the request generator*/\r
-    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;\r
-\r
-   return HAL_OK;\r
- }\r
- else\r
- {\r
-   return HAL_ERROR;\r
- }\r
-}\r
-\r
-/**\r
-  * @brief  Disable the DMAMUX request generator block used by the given DMA channel (instance).\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified DMA channel.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
-\r
-  /* check if the DMA state is ready\r
-     and DMA is using a DMAMUX request generator block\r
-  */\r
-  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))\r
-  {\r
-\r
-    /* Disable the request generator*/\r
-    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Handles DMAMUX interrupt request.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified DMA channel.\r
-  * @retval None\r
-  */\r
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)\r
-{\r
-  /* Check for DMAMUX Synchronization overrun */\r
-  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)\r
-  {\r
-    /* Disable the synchro overrun interrupt */\r
-    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
-\r
-    /* Clear the DMAMUX synchro overrun flag */\r
-    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
-\r
-    /* Update error code */\r
-    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;\r
-\r
-    if(hdma->XferErrorCallback != NULL)\r
-    {\r
-      /* Transfer error callback */\r
-      hdma->XferErrorCallback(hdma);\r
-    }\r
-  }\r
-\r
-  if(hdma->DMAmuxRequestGen != 0)\r
-  {\r
-   /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */\r
-    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)\r
-    {\r
-      /* Disable the request gen overrun interrupt */\r
-      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
-\r
-      /* Clear the DMAMUX request generator overrun flag */\r
-      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
-\r
-      /* Update error code */\r
-      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;\r
-\r
-      if(hdma->XferErrorCallback != NULL)\r
-      {\r
-        /* Transfer error callback */\r
-        hdma->XferErrorCallback(hdma);\r
-      }\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_DMA_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* DMAMUX1 */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
deleted file mode 100644 (file)
index 74405ed..0000000
+++ /dev/null
@@ -1,643 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_exti.c\r
-  * @author  MCD Application Team\r
-  * @brief   EXTI HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:\r
-  *           + Initialization and de-initialization functions\r
-  *           + IO operation functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                    ##### EXTI Peripheral features #####\r
-  ==============================================================================\r
-  [..]\r
-    (+) Each Exti line can be configured within this driver.\r
-\r
-    (+) Exti line can be configured in 3 different modes\r
-        (++) Interrupt\r
-        (++) Event\r
-        (++) Both of them\r
-\r
-    (+) Configurable Exti lines can be configured with 3 different triggers\r
-        (++) Rising\r
-        (++) Falling\r
-        (++) Both of them\r
-\r
-    (+) When set in interrupt mode, configurable Exti lines have two different\r
-        interrupts pending registers which allow to distinguish which transition\r
-        occurs:\r
-        (++) Rising edge pending interrupt\r
-        (++) Falling\r
-\r
-    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can\r
-        be selected through multiplexer.\r
-\r
-                     ##### How to use this driver #####\r
-  ==============================================================================\r
-  [..]\r
-\r
-    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().\r
-        (++) Choose the interrupt line number by setting "Line" member from\r
-             EXTI_ConfigTypeDef structure.\r
-        (++) Configure the interrupt and/or event mode using "Mode" member from\r
-             EXTI_ConfigTypeDef structure.\r
-        (++) For configurable lines, configure rising and/or falling trigger\r
-             "Trigger" member from EXTI_ConfigTypeDef structure.\r
-        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"\r
-             member from GPIO_InitTypeDef structure.\r
-\r
-    (#) Get current Exti configuration of a dedicated line using\r
-        HAL_EXTI_GetConfigLine().\r
-        (++) Provide exiting handle as parameter.\r
-        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.\r
-\r
-    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().\r
-        (++) Provide exiting handle as parameter.\r
-\r
-    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().\r
-        (++) Provide exiting handle as first parameter.\r
-        (++) Provide which callback will be registered using one value from\r
-             EXTI_CallbackIDTypeDef.\r
-        (++) Provide callback function pointer.\r
-\r
-    (#) Get interrupt pending bit using HAL_EXTI_GetPending().\r
-\r
-    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().\r
-\r
-    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup EXTI\r
-  * @{\r
-  */\r
-/** MISRA C:2012 deviation rule has been granted for following rule:\r
-  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out\r
-  * of bounds [0,3] in following API :\r
-  * HAL_EXTI_SetConfigLine\r
-  * HAL_EXTI_GetConfigLine\r
-  * HAL_EXTI_ClearConfigLine\r
-  */\r
-\r
-#ifdef HAL_EXTI_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private defines ------------------------------------------------------------*/\r
-/** @defgroup EXTI_Private_Constants EXTI Private Constants\r
-  * @{\r
-  */\r
-#define EXTI_MODE_OFFSET                    0x08u   /* 0x20: offset between MCU IMR/EMR registers */\r
-#define EXTI_CONFIG_OFFSET                  0x08u   /* 0x20: offset between MCU Rising/Falling configuration registers */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup EXTI_Exported_Functions\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup EXTI_Exported_Functions_Group1\r
- *  @brief    Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-              ##### Configuration functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Set configuration of a dedicated Exti line.\r
-  * @param  hexti Exti handle.\r
-  * @param  pExtiConfig Pointer on EXTI configuration to be set.\r
-  * @retval HAL Status.\r
-  */\r
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\r
-{\r
-  __IO uint32_t *regaddr;\r
-  uint32_t regval;\r
-  uint32_t linepos;\r
-  uint32_t maskline;\r
-  uint32_t offset;\r
-\r
-  /* Check null pointer */\r
-  if ((hexti == NULL) || (pExtiConfig == NULL))\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_EXTI_LINE(pExtiConfig->Line));\r
-  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));\r
-\r
-  /* Assign line number to handle */\r
-  hexti->Line = pExtiConfig->Line;\r
-\r
-  /* Compute line register offset and line mask */\r
-  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);\r
-  maskline = (1uL << linepos);\r
-\r
-  /* Configure triggers for configurable lines */\r
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)\r
-  {\r
-    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));\r
-\r
-    /* Configure rising trigger */\r
-    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
-    regval = *regaddr;\r
-\r
-    /* Mask or set line */\r
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)\r
-    {\r
-      regval |= maskline;\r
-    }\r
-    else\r
-    {\r
-      regval &= ~maskline;\r
-    }\r
-\r
-    /* Store rising trigger mode */\r
-    *regaddr = regval;\r
-\r
-    /* Configure falling trigger */\r
-    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
-    regval = *regaddr;\r
-\r
-    /* Mask or set line */\r
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)\r
-    {\r
-      regval |= maskline;\r
-    }\r
-    else\r
-    {\r
-      regval &= ~maskline;\r
-    }\r
-\r
-    /* Store falling trigger mode */\r
-    *regaddr = regval;\r
-\r
-    /* Configure gpio port selection in case of gpio exti line */\r
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)\r
-    {\r
-      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));\r
-      assert_param(IS_EXTI_GPIO_PIN(linepos));\r
-\r
-      regval = SYSCFG->EXTICR[linepos >> 2u];\r
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\r
-      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\r
-      SYSCFG->EXTICR[linepos >> 2u] = regval;\r
-    }\r
-  }\r
-\r
-  /* Configure interrupt mode : read current mode */\r
-  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));\r
-  regval = *regaddr;\r
-\r
-  /* Mask or set line */\r
-  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)\r
-  {\r
-    regval |= maskline;\r
-  }\r
-  else\r
-  {\r
-    regval &= ~maskline;\r
-  }\r
-\r
-  /* Store interrupt mode */\r
-  *regaddr = regval;\r
-\r
-  /* The event mode cannot be configured if the line does not support it */\r
-  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));\r
-\r
-  /* Configure event mode : read current mode */\r
-  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));\r
-  regval = *regaddr;\r
-\r
-  /* Mask or set line */\r
-  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)\r
-  {\r
-    regval |= maskline;\r
-  }\r
-  else\r
-  {\r
-    regval &= ~maskline;\r
-  }\r
-\r
-  /* Store event mode */\r
-  *regaddr = regval;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Get configuration of a dedicated Exti line.\r
-  * @param  hexti Exti handle.\r
-  * @param  pExtiConfig Pointer on structure to store Exti configuration.\r
-  * @retval HAL Status.\r
-  */\r
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\r
-{\r
-  __IO uint32_t *regaddr;\r
-  uint32_t regval;\r
-  uint32_t linepos;\r
-  uint32_t maskline;\r
-  uint32_t offset;\r
-\r
-  /* Check null pointer */\r
-  if ((hexti == NULL) || (pExtiConfig == NULL))\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameter */\r
-  assert_param(IS_EXTI_LINE(hexti->Line));\r
-\r
-  /* Store handle line number to configuration structure */\r
-  pExtiConfig->Line = hexti->Line;\r
-\r
-  /* Compute line register offset and line mask */\r
-  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);\r
-  maskline = (1uL << linepos);\r
-\r
-  /* 1] Get core mode : interrupt */\r
-  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));\r
-  regval = *regaddr;\r
-\r
-  /* Check if selected line is enable */\r
-  if ((regval & maskline) != 0x00u)\r
-  {\r
-    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;\r
-  }\r
-  else\r
-  {\r
-    pExtiConfig->Mode = EXTI_MODE_NONE;\r
-  }\r
-\r
-  /* Get event mode */\r
-  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));\r
-  regval = *regaddr;\r
-\r
-  /* Check if selected line is enable */\r
-  if ((regval & maskline) != 0x00u)\r
-  {\r
-    pExtiConfig->Mode |= EXTI_MODE_EVENT;\r
-  }\r
-\r
-  /* 2] Get trigger for configurable lines : rising */\r
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)\r
-  {\r
-    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
-    regval = *regaddr;\r
-\r
-    /* Check if configuration of selected line is enable */\r
-    if ((regval & maskline) != 0x00u)\r
-    {\r
-      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;\r
-    }\r
-    else\r
-    {\r
-      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;\r
-    }\r
-\r
-    /* Get falling configuration */\r
-    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
-    regval = *regaddr;\r
-\r
-    /* Check if configuration of selected line is enable */\r
-    if ((regval & maskline) != 0x00u)\r
-    {\r
-      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;\r
-    }\r
-\r
-    /* Get Gpio port selection for gpio lines */\r
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)\r
-    {\r
-      assert_param(IS_EXTI_GPIO_PIN(linepos));\r
-\r
-      regval = SYSCFG->EXTICR[linepos >> 2u];\r
-      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);\r
-    }\r
-    else\r
-    {\r
-      pExtiConfig->GPIOSel = 0x00u;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;\r
-    pExtiConfig->GPIOSel = 0x00u;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Clear whole configuration of a dedicated Exti line.\r
-  * @param  hexti Exti handle.\r
-  * @retval HAL Status.\r
-  */\r
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)\r
-{\r
-  __IO uint32_t *regaddr;\r
-  uint32_t regval;\r
-  uint32_t linepos;\r
-  uint32_t maskline;\r
-  uint32_t offset;\r
-\r
-  /* Check null pointer */\r
-  if (hexti == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameter */\r
-  assert_param(IS_EXTI_LINE(hexti->Line));\r
-\r
-  /* compute line register offset and line mask */\r
-  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
-  linepos = (hexti->Line & EXTI_PIN_MASK);\r
-  maskline = (1uL << linepos);\r
-\r
-  /* 1] Clear interrupt mode */\r
-  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));\r
-  regval = (*regaddr & ~maskline);\r
-  *regaddr = regval;\r
-\r
-  /* 2] Clear event mode */\r
-  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));\r
-  regval = (*regaddr & ~maskline);\r
-  *regaddr = regval;\r
-\r
-  /* 3] Clear triggers in case of configurable lines */\r
-  if ((hexti->Line & EXTI_CONFIG) != 0x00u)\r
-  {\r
-    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
-    regval = (*regaddr & ~maskline);\r
-    *regaddr = regval;\r
-\r
-    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));\r
-    regval = (*regaddr & ~maskline);\r
-    *regaddr = regval;\r
-\r
-    /* Get Gpio port selection for gpio lines */\r
-    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)\r
-    {\r
-      assert_param(IS_EXTI_GPIO_PIN(linepos));\r
-\r
-      regval = SYSCFG->EXTICR[linepos >> 2u];\r
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\r
-      SYSCFG->EXTICR[linepos >> 2u] = regval;\r
-    }\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Register callback for a dedicated Exti line.\r
-  * @param  hexti Exti handle.\r
-  * @param  CallbackID User callback identifier.\r
-  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.\r
-  * @param  pPendingCbfn function pointer to be stored as callback.\r
-  * @retval HAL Status.\r
-  */\r
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  switch (CallbackID)\r
-  {\r
-    case  HAL_EXTI_COMMON_CB_ID:\r
-      hexti->PendingCallback = pPendingCbfn;\r
-      break;\r
-\r
-    default:\r
-      status = HAL_ERROR;\r
-      break;\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Store line number as handle private field.\r
-  * @param  hexti Exti handle.\r
-  * @param  ExtiLine Exti line number.\r
-  *         This parameter can be from 0 to @ref EXTI_LINE_NB.\r
-  * @retval HAL Status.\r
-  */\r
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_EXTI_LINE(ExtiLine));\r
-\r
-  /* Check null pointer */\r
-  if (hexti == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Store line number as handle private field */\r
-    hexti->Line = ExtiLine;\r
-\r
-    return HAL_OK;\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup EXTI_Exported_Functions_Group2\r
- *  @brief EXTI IO functions.\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                       ##### IO operation functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Handle EXTI interrupt request.\r
-  * @param  hexti Exti handle.\r
-  * @retval none.\r
-  */\r
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)\r
-{\r
-  __IO uint32_t *regaddr;\r
-  uint32_t regval;\r
-  uint32_t maskline;\r
-  uint32_t offset;\r
-\r
-  /* Compute line register offset and line mask */\r
-  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\r
-\r
-  /* Get pending bit  */\r
-  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));\r
-  regval = (*regaddr & maskline);\r
-\r
-  if (regval != 0x00u)\r
-  {\r
-    /* Clear pending bit */\r
-    *regaddr = maskline;\r
-\r
-    /* Call callback */\r
-    if (hexti->PendingCallback != NULL)\r
-    {\r
-      hexti->PendingCallback();\r
-    }\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Get interrupt pending bit of a dedicated line.\r
-  * @param  hexti Exti handle.\r
-  * @param  Edge Specify which pending edge as to be checked.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING\r
-  *         This parameter is kept for compatibility with other series.\r
-  * @retval 1 if interrupt is pending else 0.\r
-  */\r
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\r
-{\r
-  __IO uint32_t *regaddr;\r
-  uint32_t regval;\r
-  uint32_t linepos;\r
-  uint32_t maskline;\r
-  uint32_t offset;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_EXTI_LINE(hexti->Line));\r
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\r
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));\r
-\r
-  /* Compute line register offset and line mask */\r
-  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
-  linepos = (hexti->Line & EXTI_PIN_MASK);\r
-  maskline = (1uL << linepos);\r
-\r
-  /* Get pending bit */\r
-  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));\r
-\r
-  /* return 1 if bit is set else 0 */\r
-  regval = ((*regaddr & maskline) >> linepos);\r
-  return regval;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Clear interrupt pending bit of a dedicated line.\r
-  * @param  hexti Exti handle.\r
-  * @param  Edge Specify which pending edge as to be clear.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING\r
-  *         This parameter is kept for compatibility with other series.\r
-  * @retval None.\r
-  */\r
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\r
-{\r
-  __IO uint32_t *regaddr;\r
-  uint32_t maskline;\r
-  uint32_t offset;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_EXTI_LINE(hexti->Line));\r
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\r
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));\r
-\r
-  /* compute line register offset and line mask */\r
-  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\r
-\r
-  /* Get pending register address */\r
-  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));\r
-\r
-  /* Clear Pending bit */\r
-  *regaddr =  maskline;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Generate a software interrupt for a dedicated line.\r
-  * @param  hexti Exti handle.\r
-  * @retval None.\r
-  */\r
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)\r
-{\r
-  __IO uint32_t *regaddr;\r
-  uint32_t maskline;\r
-  uint32_t offset;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_EXTI_LINE(hexti->Line));\r
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\r
-\r
-  /* compute line register offset and line mask */\r
-  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);\r
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\r
-\r
-  regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));\r
-  *regaddr = maskline;\r
-}\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_EXTI_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
deleted file mode 100644 (file)
index a746962..0000000
+++ /dev/null
@@ -1,769 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_flash.c\r
-  * @author  MCD Application Team\r
-  * @brief   FLASH HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the internal FLASH memory:\r
-  *           + Program operations functions\r
-  *           + Memory Control functions\r
-  *           + Peripheral Errors functions\r
-  *\r
- @verbatim\r
-  ==============================================================================\r
-                        ##### FLASH peripheral features #####\r
-  ==============================================================================\r
-\r
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses\r
-       to the Flash memory. It implements the erase and program Flash memory operations\r
-       and the read and write protection mechanisms.\r
-\r
-  [..] The Flash memory interface accelerates code execution with a system of instruction\r
-       prefetch and cache lines.\r
-\r
-  [..] The FLASH main features are:\r
-      (+) Flash memory read operations\r
-      (+) Flash memory program/erase operations\r
-      (+) Read / write protections\r
-      (+) Option bytes programming\r
-      (+) Prefetch on I-Code\r
-      (+) 32 cache lines of 4*64 bits on I-Code\r
-      (+) 8 cache lines of 4*64 bits on D-Code\r
-      (+) Error code correction (ECC) : Data in flash are 72-bits word\r
-          (8 bits added per double word)\r
-\r
-\r
-                        ##### How to use this driver #####\r
- ==============================================================================\r
-    [..]\r
-      This driver provides functions and macros to configure and program the FLASH\r
-      memory of all STM32L4xx devices.\r
-\r
-      (#) Flash Memory IO Programming functions:\r
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and\r
-                HAL_FLASH_Lock() functions\r
-           (++) Program functions: double word and fast program (full row programming)\r
-           (++) There Two modes of programming :\r
-            (+++) Polling mode using HAL_FLASH_Program() function\r
-            (+++) Interrupt mode using HAL_FLASH_Program_IT() function\r
-\r
-      (#) Interrupts and flags management functions :\r
-           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\r
-           (++) Callback functions are called when the flash operations are finished :\r
-                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise\r
-                HAL_FLASH_OperationErrorCallback()\r
-           (++) Get error flag status by calling HAL_GetError()\r
-\r
-      (#) Option bytes management functions :\r
-           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and\r
-                HAL_FLASH_OB_Lock() functions\r
-           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.\r
-                In this case, a reset is generated\r
-\r
-    [..]\r
-      In addition to these functions, this driver includes a set of macros allowing\r
-      to handle the following operations:\r
-       (+) Set the latency\r
-       (+) Enable/Disable the prefetch buffer\r
-       (+) Enable/Disable the Instruction cache and the Data cache\r
-       (+) Reset the Instruction cache and the Data cache\r
-       (+) Enable/Disable the Flash power-down during low-power run and sleep modes\r
-       (+) Enable/Disable the Flash interrupts\r
-       (+) Monitor the Flash flags status\r
-\r
- @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup FLASH FLASH\r
-  * @brief FLASH HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_FLASH_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private defines -----------------------------------------------------------*/\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define FLASH_NB_DOUBLE_WORDS_IN_ROW  64\r
-#else\r
-#define FLASH_NB_DOUBLE_WORDS_IN_ROW  32\r
-#endif\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
- * @{\r
- */\r
-/**\r
-  * @brief  Variable used for Program/Erase sectors under interruption\r
-  */\r
-FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \\r
-                               .ErrorCode = HAL_FLASH_ERROR_NONE, \\r
-                               .ProcedureOnGoing = FLASH_PROC_NONE, \\r
-                               .Address = 0U, \\r
-                               .Bank = FLASH_BANK_1, \\r
-                               .Page = 0U, \\r
-                               .NbPagesToErase = 0U, \\r
-                               .CacheToReactivate = FLASH_CACHE_DISABLED};\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup FLASH_Private_Functions FLASH Private Functions\r
- * @{\r
- */\r
-static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\r
-static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions\r
- *  @brief   Programming operation functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                  ##### Programming operation functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to manage the FLASH\r
-    program operations.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Program double word or fast program of a row at a specified address.\r
-  * @param  TypeProgram:  Indicate the way to program at a specified address.\r
-  *                           This parameter can be a value of @ref FLASH_Type_Program\r
-  * @param  Address:  specifies the address to be programmed.\r
-  * @param  Data: specifies the data to be programmed\r
-  *                This parameter is the data for the double word program and the address where\r
-  *                are stored the data for the row fast program\r
-  *\r
-  * @retval HAL_StatusTypeDef HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t prog_bit = 0;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(&pFlash);\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
-\r
-  /* Wait for last operation to be completed */\r
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
-    /* Deactivate the data cache if they are activated to avoid data misbehavior */\r
-    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
-    {\r
-      /* Disable data cache  */\r
-      __HAL_FLASH_DATA_CACHE_DISABLE();\r
-      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
-    }\r
-    else\r
-    {\r
-      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
-    }\r
-\r
-    if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)\r
-    {\r
-      /* Program double-word (64-bit) at a specified address */\r
-      FLASH_Program_DoubleWord(Address, Data);\r
-      prog_bit = FLASH_CR_PG;\r
-    }\r
-    else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))\r
-    {\r
-      /* Fast program a 32 row double-word (64-bit) at a specified address */\r
-      FLASH_Program_Fast(Address, (uint32_t)Data);\r
-\r
-      /* If it is the last row, the bit will be cleared at the end of the operation */\r
-      if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)\r
-      {\r
-        prog_bit = FLASH_CR_FSTPG;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Nothing to do */\r
-    }\r
-\r
-    /* Wait for last operation to be completed */\r
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-    /* If the program operation is completed, disable the PG or FSTPG Bit */\r
-    if (prog_bit != 0U)\r
-    {\r
-      CLEAR_BIT(FLASH->CR, prog_bit);\r
-    }\r
-\r
-    /* Flush the caches to be sure of the data consistency */\r
-    FLASH_FlushCaches();\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(&pFlash);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.\r
-  * @param  TypeProgram:  Indicate the way to program at a specified address.\r
-  *                           This parameter can be a value of @ref FLASH_Type_Program\r
-  * @param  Address:  specifies the address to be programmed.\r
-  * @param  Data: specifies the data to be programmed\r
-  *                This parameter is the data for the double word program and the address where\r
-  *                are stored the data for the row fast program\r
-  *\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(&pFlash);\r
-\r
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
-  /* Deactivate the data cache if they are activated to avoid data misbehavior */\r
-  if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
-  {\r
-    /* Disable data cache  */\r
-    __HAL_FLASH_DATA_CACHE_DISABLE();\r
-    pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
-  }\r
-  else\r
-  {\r
-    pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
-  }\r
-\r
-  /* Set internal variables used by the IRQ handler */\r
-  if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)\r
-  {\r
-    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;\r
-  }\r
-  else\r
-  {\r
-    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r
-  }\r
-  pFlash.Address = Address;\r
-\r
-  /* Enable End of Operation and Error interrupts */\r
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);\r
-\r
-  if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)\r
-  {\r
-    /* Program double-word (64-bit) at a specified address */\r
-    FLASH_Program_DoubleWord(Address, Data);\r
-  }\r
-  else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))\r
-  {\r
-    /* Fast program a 32 row double-word (64-bit) at a specified address */\r
-    FLASH_Program_Fast(Address, (uint32_t)Data);\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief Handle FLASH interrupt request.\r
-  * @retval None\r
-  */\r
-void HAL_FLASH_IRQHandler(void)\r
-{\r
-  uint32_t tmp_page;\r
-  uint32_t error;\r
-  FLASH_ProcedureTypeDef procedure;\r
-\r
-  /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */\r
-  CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);\r
-#endif\r
-\r
-  /* Disable the FSTPG Bit only if it is the last row programmed */\r
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)\r
-  {\r
-    CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);\r
-  }\r
-\r
-  /* Check FLASH operation error flags */\r
-  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);\r
-  error |= (FLASH->ECCR & FLASH_FLAG_ECCC);\r
-\r
-  if (error !=0U)\r
-  {\r
-    /*Save the error code*/\r
-    pFlash.ErrorCode |= error;\r
-\r
-    /* Clear error programming flags */\r
-    __HAL_FLASH_CLEAR_FLAG(error);\r
-\r
-    /* Flush the caches to be sure of the data consistency */\r
-    FLASH_FlushCaches() ;\r
-\r
-    /* FLASH error interrupt user callback */\r
-    procedure = pFlash.ProcedureOnGoing;\r
-    if(procedure == FLASH_PROC_PAGE_ERASE)\r
-    {\r
-       HAL_FLASH_OperationErrorCallback(pFlash.Page);\r
-    }\r
-    else if(procedure == FLASH_PROC_MASS_ERASE)\r
-    {\r
-        HAL_FLASH_OperationErrorCallback(pFlash.Bank);\r
-    }\r
-    else if((procedure == FLASH_PROC_PROGRAM) ||\r
-            (procedure == FLASH_PROC_PROGRAM_LAST))\r
-    {\r
-       HAL_FLASH_OperationErrorCallback(pFlash.Address);\r
-    }\r
-    else\r
-    {\r
-       HAL_FLASH_OperationErrorCallback(0U);\r
-    }\r
-\r
-    /*Stop the procedure ongoing*/\r
-    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
-  }\r
-\r
-  /* Check FLASH End of Operation flag  */\r
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0U)\r
-  {\r
-    /* Clear FLASH End of Operation pending bit */\r
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
-\r
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)\r
-    {\r
-      /* Nb of pages to erased can be decreased */\r
-      pFlash.NbPagesToErase--;\r
-\r
-      /* Check if there are still pages to erase*/\r
-      if(pFlash.NbPagesToErase != 0U)\r
-      {\r
-        /* Indicate user which page has been erased*/\r
-        HAL_FLASH_EndOfOperationCallback(pFlash.Page);\r
-\r
-        /* Increment page number */\r
-        pFlash.Page++;\r
-        tmp_page = pFlash.Page;\r
-        FLASH_PageErase(tmp_page, pFlash.Bank);\r
-      }\r
-      else\r
-      {\r
-        /* No more pages to Erase */\r
-        /* Reset Address and stop Erase pages procedure */\r
-        pFlash.Page = 0xFFFFFFFFU;\r
-        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
-\r
-        /* Flush the caches to be sure of the data consistency */\r
-        FLASH_FlushCaches() ;\r
-\r
-        /* FLASH EOP interrupt user callback */\r
-        HAL_FLASH_EndOfOperationCallback(pFlash.Page);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Flush the caches to be sure of the data consistency */\r
-      FLASH_FlushCaches() ;\r
-\r
-      procedure = pFlash.ProcedureOnGoing;\r
-      if(procedure == FLASH_PROC_MASS_ERASE)\r
-      {\r
-        /* MassErase ended. Return the selected bank */\r
-        /* FLASH EOP interrupt user callback */\r
-        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);\r
-      }\r
-      else if((procedure == FLASH_PROC_PROGRAM) ||\r
-              (procedure == FLASH_PROC_PROGRAM_LAST))\r
-      {\r
-        /* Program ended. Return the selected address */\r
-        /* FLASH EOP interrupt user callback */\r
-        HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
-      }\r
-      else\r
-      {\r
-        /* Nothing to do */\r
-      }\r
-\r
-      /*Clear the procedure ongoing*/\r
-      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
-    }\r
-  }\r
-\r
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r
-  {\r
-    /* Disable End of Operation and Error interrupts */\r
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(&pFlash);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  FLASH end of operation interrupt callback.\r
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
-  *                  Mass Erase: Bank number which has been requested to erase\r
-  *                  Page Erase: Page which has been erased\r
-  *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)\r
-  *                  Program: Address which was selected for data program\r
-  * @retval None\r
-  */\r
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(ReturnValue);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  FLASH operation error interrupt callback.\r
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
-  *                 Mass Erase: Bank number which has been requested to erase\r
-  *                 Page Erase: Page number which returned an error\r
-  *                 Program: Address which was selected for data program\r
-  * @retval None\r
-  */\r
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(ReturnValue);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions\r
- *  @brief   Management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Peripheral Control functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to control the FLASH\r
-    memory operations.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Unlock the FLASH control register access.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)\r
-  {\r
-    /* Authorize the FLASH Registers access */\r
-    WRITE_REG(FLASH->KEYR, FLASH_KEY1);\r
-    WRITE_REG(FLASH->KEYR, FLASH_KEY2);\r
-\r
-    /* Verify Flash is unlocked */\r
-    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)\r
-    {\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Lock the FLASH control register access.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASH_Lock(void)\r
-{\r
-  /* Set the LOCK Bit to lock the FLASH Registers access */\r
-  SET_BIT(FLASH->CR, FLASH_CR_LOCK);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Unlock the FLASH Option Bytes Registers access.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r
-{\r
-  if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)\r
-  {\r
-    /* Authorizes the Option Byte register programming */\r
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);\r
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Lock the FLASH Option Bytes Registers access.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r
-{\r
-  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r
-  SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Launch the option byte loading.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r
-{\r
-  /* Set the bit to force the option byte reloading */\r
-  SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);\r
-\r
-  /* Wait for last operation to be completed */\r
-  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions\r
- *  @brief   Peripheral Errors functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                ##### Peripheral Errors functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection permits to get in run-time Errors of the FLASH peripheral.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Get the specific FLASH error flag.\r
-  * @retval FLASH_ErrorCode: The returned value can be:\r
-  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)\r
-  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag\r
-  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag\r
-  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag\r
-  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag\r
-  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag\r
-  *            @arg HAL_FLASH_ERROR_NONE: No error set\r
-  *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error\r
-  *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error\r
-  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error\r
-  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error\r
-  *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error\r
-  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error\r
-  *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error\r
-  *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error\r
-  *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error\r
-  *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error\r
-  *            @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)\r
-  *            @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected\r
-  */\r
-uint32_t HAL_FLASH_GetError(void)\r
-{\r
-   return pFlash.ErrorCode;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @addtogroup FLASH_Private_Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Wait for a FLASH operation to complete.\r
-  * @param  Timeout: maximum flash operation timeout\r
-  * @retval HAL_StatusTypeDef HAL Status\r
-  */\r
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r
-{\r
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
-     flag will be set */\r
-\r
-  uint32_t tickstart = HAL_GetTick();\r
-  uint32_t error;\r
-\r
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))\r
-  {\r
-    if(Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if((HAL_GetTick() - tickstart) >= Timeout)\r
-      {\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-  }\r
-\r
-  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);\r
-  error |= (FLASH->ECCR & FLASH_FLAG_ECCD);\r
-\r
-  if(error != 0u)\r
-  {\r
-    /*Save the error code*/\r
-    pFlash.ErrorCode |= error;\r
-\r
-    /* Clear error programming flags */\r
-    __HAL_FLASH_CLEAR_FLAG(error);\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check FLASH End of Operation flag  */\r
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))\r
-  {\r
-    /* Clear FLASH End of Operation pending bit */\r
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
-  }\r
-\r
-  /* If there is an error flag set */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Program double-word (64-bit) at a specified address.\r
-  * @param  Address: specifies the address to be programmed.\r
-  * @param  Data: specifies the data to be programmed.\r
-  * @retval None\r
-  */\r
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
-\r
-  /* Set PG bit */\r
-  SET_BIT(FLASH->CR, FLASH_CR_PG);\r
-\r
-  /* Program first word */\r
-  *(__IO uint32_t*)Address = (uint32_t)Data;\r
-\r
-  /* Barrier to ensure programming is performed in 2 steps, in right order\r
-    (independently of compiler optimization behavior) */\r
-  __ISB();\r
-\r
-  /* Program second word */\r
-  *(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32);\r
-}\r
-\r
-/**\r
-  * @brief  Fast program a row double-word (64-bit) at a specified address.\r
-  * @param  Address: specifies the address to be programmed.\r
-  * @param  DataAddress: specifies the address where the data are stored.\r
-  * @retval None\r
-  */\r
-static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)\r
-{\r
-  uint32_t primask_bit;\r
-  uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);\r
-  __IO uint32_t *dest_addr = (__IO uint32_t*)Address;\r
-  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));\r
-\r
-  /* Set FSTPG bit */\r
-  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);\r
-\r
-  /* Disable interrupts to avoid any interruption during the loop */\r
-  primask_bit = __get_PRIMASK();\r
-  __disable_irq();\r
-\r
-  /* Program the double word of the row */\r
-  do\r
-  {\r
-    *dest_addr = *src_addr;\r
-    dest_addr++;\r
-    src_addr++;\r
-    row_index--;\r
-  } while (row_index != 0U);\r
-\r
-  /* Re-enable the interrupts */\r
-  __set_PRIMASK(primask_bit);\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_FLASH_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
deleted file mode 100644 (file)
index 5a30708..0000000
+++ /dev/null
@@ -1,1308 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_flash_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   Extended FLASH HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the FLASH extended peripheral:\r
-  *           + Extended programming operations functions\r
-  *\r
- @verbatim\r
- ==============================================================================\r
-                   ##### Flash Extended features #####\r
-  ==============================================================================\r
-\r
-  [..] Comparing to other previous devices, the FLASH interface for STM32L4xx\r
-       devices contains the following additional features\r
-\r
-       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\r
-           capability (RWW)\r
-       (+) Dual bank memory organization\r
-       (+) PCROP protection for all banks\r
-\r
-                        ##### How to use this driver #####\r
- ==============================================================================\r
-  [..] This driver provides functions to configure and program the FLASH memory\r
-       of all STM32L4xx devices. It includes\r
-      (#) Flash Memory Erase functions:\r
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and\r
-                HAL_FLASH_Lock() functions\r
-           (++) Erase function: Erase page, erase all sectors\r
-           (++) There are two modes of erase :\r
-             (+++) Polling Mode using HAL_FLASHEx_Erase()\r
-             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\r
-\r
-      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :\r
-        (++) Set/Reset the write protection\r
-        (++) Set the Read protection Level\r
-        (++) Program the user Option Bytes\r
-        (++) Configure the PCROP protection\r
-\r
-      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :\r
-        (++) Get the value of a write protection area\r
-        (++) Know if the read protection is activated\r
-        (++) Get the value of the user Option Bytes\r
-        (++) Get the value of a PCROP area\r
-\r
- @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup FLASHEx FLASHEx\r
-  * @brief FLASH Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_FLASH_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions\r
- * @{\r
- */\r
-static void              FLASH_MassErase(uint32_t Banks);\r
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);\r
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);\r
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);\r
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);\r
-static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);\r
-static uint32_t          FLASH_OB_GetRDP(void);\r
-static uint32_t          FLASH_OB_GetUser(void);\r
-static void              FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions -------------------------------------------------------*/\r
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\r
- *  @brief   Extended IO operation functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                ##### Extended programming operation functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to manage the Extended FLASH\r
-    programming operations Operations.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Perform a mass erase or erase the specified FLASH memory pages.\r
-  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
-  *         contains the configuration information for the erasing.\r
-  *\r
-  * @param[out]  PageError  : pointer to variable that contains the configuration\r
-  *         information on faulty page in case of error (0xFFFFFFFF means that all\r
-  *         the pages have been correctly erased)\r
-  *\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t page_index;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(&pFlash);\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
-\r
-  /* Wait for last operation to be completed */\r
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-  if (status == HAL_OK)\r
-  {\r
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
-    /* Deactivate the cache if they are activated to avoid data misbehavior */\r
-    if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)\r
-    {\r
-      /* Disable instruction cache  */\r
-      __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
-\r
-      if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
-      {\r
-        /* Disable data cache  */\r
-        __HAL_FLASH_DATA_CACHE_DISABLE();\r
-        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;\r
-      }\r
-      else\r
-      {\r
-        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;\r
-      }\r
-    }\r
-    else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
-    {\r
-      /* Disable data cache  */\r
-      __HAL_FLASH_DATA_CACHE_DISABLE();\r
-      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
-    }\r
-    else\r
-    {\r
-      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
-    }\r
-\r
-    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
-    {\r
-      /* Mass erase to be done */\r
-      FLASH_MassErase(pEraseInit->Banks);\r
-\r
-      /* Wait for last operation to be completed */\r
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-      /* If the erase operation is completed, disable the MER1 and MER2 Bits */\r
-      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));\r
-#else\r
-      /* If the erase operation is completed, disable the MER1 Bit */\r
-      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));\r
-#endif\r
-    }\r
-    else\r
-    {\r
-      /*Initialization of PageError variable*/\r
-      *PageError = 0xFFFFFFFFU;\r
-\r
-      for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)\r
-      {\r
-        FLASH_PageErase(page_index, pEraseInit->Banks);\r
-\r
-        /* Wait for last operation to be completed */\r
-        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-        /* If the erase operation is completed, disable the PER Bit */\r
-        CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));\r
-\r
-        if (status != HAL_OK)\r
-        {\r
-          /* In case of error, stop erase procedure and return the faulty address */\r
-          *PageError = page_index;\r
-          break;\r
-        }\r
-      }\r
-    }\r
-\r
-    /* Flush the caches to be sure of the data consistency */\r
-    FLASH_FlushCaches();\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(&pFlash);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.\r
-  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
-  *         contains the configuration information for the erasing.\r
-  *\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(&pFlash);\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
-\r
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
-  /* Deactivate the cache if they are activated to avoid data misbehavior */\r
-  if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)\r
-  {\r
-    /* Disable instruction cache  */\r
-    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
-\r
-    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
-    {\r
-      /* Disable data cache  */\r
-      __HAL_FLASH_DATA_CACHE_DISABLE();\r
-      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;\r
-    }\r
-    else\r
-    {\r
-      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;\r
-    }\r
-  }\r
-  else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
-  {\r
-    /* Disable data cache  */\r
-    __HAL_FLASH_DATA_CACHE_DISABLE();\r
-    pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;\r
-  }\r
-  else\r
-  {\r
-    pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
-  }\r
-\r
-  /* Enable End of Operation and Error interrupts */\r
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);\r
-\r
-  pFlash.Bank = pEraseInit->Banks;\r
-\r
-  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
-  {\r
-    /* Mass erase to be done */\r
-    pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;\r
-    FLASH_MassErase(pEraseInit->Banks);\r
-  }\r
-  else\r
-  {\r
-    /* Erase by page to be done */\r
-    pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;\r
-    pFlash.NbPagesToErase = pEraseInit->NbPages;\r
-    pFlash.Page = pEraseInit->Page;\r
-\r
-    /*Erase 1st page and wait for IT */\r
-    FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Program Option bytes.\r
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that\r
-  *         contains the configuration information for the programming.\r
-  *\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(&pFlash);\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r
-\r
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
-  /* Write protection configuration */\r
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)\r
-  {\r
-    /* Configure of Write protection on the selected area */\r
-    if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)\r
-    {\r
-      status = HAL_ERROR;\r
-    }\r
-\r
-  }\r
-\r
-  /* Read protection configuration */\r
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)\r
-  {\r
-    /* Configure the Read protection level */\r
-    if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)\r
-    {\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-\r
-  /* User Configuration */\r
-  if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)\r
-  {\r
-    /* Configure the user option bytes */\r
-    if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)\r
-    {\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-\r
-  /* PCROP Configuration */\r
-  if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)\r
-  {\r
-    if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)\r
-    {\r
-      /* Configure the Proprietary code readout protection */\r
-      if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)\r
-      {\r
-        status = HAL_ERROR;\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(&pFlash);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Get the Option bytes configuration.\r
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that contains the\r
-  *                  configuration information.\r
-  * @note   The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate\r
-  *         which area is requested for the WRP and PCROP, else no information will be returned\r
-  *\r
-  * @retval None\r
-  */\r
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r
-{\r
-  pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||\r
-     (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))\r
-#else\r
-  if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))\r
-#endif\r
-  {\r
-    pOBInit->OptionType |= OPTIONBYTE_WRP;\r
-    /* Get write protection on the selected area */\r
-    FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));\r
-  }\r
-\r
-  /* Get Read protection level */\r
-  pOBInit->RDPLevel = FLASH_OB_GetRDP();\r
-\r
-  /* Get the user option bytes */\r
-  pOBInit->USERConfig = FLASH_OB_GetUser();\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))\r
-#else\r
-  if(pOBInit->PCROPConfig == FLASH_BANK_1)\r
-#endif\r
-  {\r
-    pOBInit->OptionType |= OPTIONBYTE_PCROP;\r
-    /* Get the Proprietary code readout protection */\r
-    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));\r
-  }\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined (FLASH_CFGR_LVEN)\r
-/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions\r
- *  @brief   Extended specific configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                ##### Extended specific configuration functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to manage the Extended FLASH\r
-    specific configurations.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Configuration of the LVE pin of the Flash (managed by power controller\r
-  *         or forced to low in order to use an external SMPS)\r
-  * @param  ConfigLVE: Configuration of the LVE pin,\r
-  *              This parameter can be one of the following values:\r
-  *                @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller\r
-  *                @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used)\r
-  *\r
-  * @note   Before enforcing the LVE pin to low, the SOC should be in low voltage\r
-  *         range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON.\r
-  *\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE)\r
-{\r
-  HAL_StatusTypeDef status;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(&pFlash);\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_LVE_PIN(ConfigLVE));\r
-\r
-  /* Wait for last operation to be completed */\r
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-  if (status == HAL_OK)\r
-  {\r
-    /* Check that the voltage scaling is range 2 */\r
-    if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2)\r
-    {\r
-      /* Configure the LVEN bit */\r
-      MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE);\r
-\r
-      /* Check that the bit has been correctly configured */\r
-      if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE)\r
-      {\r
-        status = HAL_ERROR;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Not allow to force Flash LVE pin if not in voltage range 2 */\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(&pFlash);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* FLASH_CFGR_LVEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @addtogroup FLASHEx_Private_Functions\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Mass erase of FLASH memory.\r
-  * @param  Banks: Banks to be erased\r
-  *          This parameter can be one of the following values:\r
-  *            @arg FLASH_BANK_1: Bank1 to be erased\r
-  *            @arg FLASH_BANK_2: Bank2 to be erased\r
-  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\r
-  * @retval None\r
-  */\r
-static void FLASH_MassErase(uint32_t Banks)\r
-{\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)\r
-#endif\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_FLASH_BANK(Banks));\r
-\r
-    /* Set the Mass Erase Bit for the bank 1 if requested */\r
-    if((Banks & FLASH_BANK_1) != 0U)\r
-    {\r
-      SET_BIT(FLASH->CR, FLASH_CR_MER1);\r
-    }\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-    /* Set the Mass Erase Bit for the bank 2 if requested */\r
-    if((Banks & FLASH_BANK_2) != 0U)\r
-    {\r
-      SET_BIT(FLASH->CR, FLASH_CR_MER2);\r
-    }\r
-#endif\r
-  }\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  else\r
-  {\r
-    SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));\r
-  }\r
-#endif\r
-\r
-  /* Proceed to erase all sectors */\r
-  SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
-}\r
-\r
-/**\r
-  * @brief  Erase the specified FLASH memory page.\r
-  * @param  Page: FLASH page to erase\r
-  *         This parameter must be a value between 0 and (max number of pages in the bank - 1)\r
-  * @param  Banks: Bank(s) where the page will be erased\r
-  *          This parameter can be one of the following values:\r
-  *            @arg FLASH_BANK_1: Page in bank 1 to be erased\r
-  *            @arg FLASH_BANK_2: Page in bank 2 to be erased\r
-  * @retval None\r
-  */\r
-void FLASH_PageErase(uint32_t Page, uint32_t Banks)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_PAGE(Page));\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)\r
-  {\r
-    CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);\r
-  }\r
-  else\r
-#endif\r
-  {\r
-    assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));\r
-\r
-    if((Banks & FLASH_BANK_1) != 0U)\r
-    {\r
-      CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);\r
-    }\r
-    else\r
-    {\r
-      SET_BIT(FLASH->CR, FLASH_CR_BKER);\r
-    }\r
-  }\r
-#else\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(Banks);\r
-#endif\r
-\r
-  /* Proceed to erase the page */\r
-  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));\r
-  SET_BIT(FLASH->CR, FLASH_CR_PER);\r
-  SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
-}\r
-\r
-/**\r
-  * @brief  Flush the instruction and data caches.\r
-  * @retval None\r
-  */\r
-void FLASH_FlushCaches(void)\r
-{\r
-  FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;\r
-\r
-  /* Flush instruction cache  */\r
-  if((cache == FLASH_CACHE_ICACHE_ENABLED) ||\r
-     (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))\r
-  {\r
-    /* Reset instruction cache */\r
-    __HAL_FLASH_INSTRUCTION_CACHE_RESET();\r
-    /* Enable instruction cache */\r
-    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();\r
-  }\r
-\r
-  /* Flush data cache */\r
-  if((cache == FLASH_CACHE_DCACHE_ENABLED) ||\r
-     (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))\r
-  {\r
-    /* Reset data cache */\r
-    __HAL_FLASH_DATA_CACHE_RESET();\r
-    /* Enable data cache */\r
-    __HAL_FLASH_DATA_CACHE_ENABLE();\r
-  }\r
-\r
-  /* Reset internal variable */\r
-  pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the write protection of the desired pages.\r
-  *\r
-  * @note   When the memory read protection level is selected (RDP level = 1),\r
-  *         it is not possible to program or erase Flash memory if the CPU debug\r
-  *         features are connected (JTAG or single wire) or boot code is being\r
-  *         executed from RAM or System flash, even if WRP is not activated.\r
-  * @note   To configure the WRP options, the option lock bit OPTLOCK must be\r
-  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
-  * @note   To validate the WRP options, the option bytes must be reloaded\r
-  *         through the call of the HAL_FLASH_OB_Launch() function.\r
-  *\r
-  * @param  WRPArea: specifies the area to be configured.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A\r
-  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B\r
-  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A  (don't apply for STM32L43x/STM32L44x devices)\r
-  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B  (don't apply for STM32L43x/STM32L44x devices)\r
-  *\r
-  * @param  WRPStartOffset: specifies the start page of the write protected area\r
-  *          This parameter can be page number between 0 and (max number of pages in the bank - 1)\r
-  *\r
-  * @param  WRDPEndOffset: specifies the end page of the write protected area\r
-  *          This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)\r
-  *\r
-  * @retval HAL Status\r
-  */\r
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)\r
-{\r
-  HAL_StatusTypeDef status;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_OB_WRPAREA(WRPArea));\r
-  assert_param(IS_FLASH_PAGE(WRPStartOffset));\r
-  assert_param(IS_FLASH_PAGE(WRDPEndOffset));\r
-\r
-  /* Wait for last operation to be completed */\r
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-    /* Configure the write protected area */\r
-    if(WRPArea == OB_WRPAREA_BANK1_AREAA)\r
-    {\r
-      MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),\r
-                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
-    }\r
-    else if(WRPArea == OB_WRPAREA_BANK1_AREAB)\r
-    {\r
-      MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),\r
-                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
-    }\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-    else if(WRPArea == OB_WRPAREA_BANK2_AREAA)\r
-    {\r
-      MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),\r
-                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
-    }\r
-    else if(WRPArea == OB_WRPAREA_BANK2_AREAB)\r
-    {\r
-      MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),\r
-                 (WRPStartOffset | (WRDPEndOffset << 16)));\r
-    }\r
-#endif\r
-    else\r
-    {\r
-      /* Nothing to do */\r
-    }\r
-\r
-    /* Set OPTSTRT Bit */\r
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-\r
-    /* Wait for last operation to be completed */\r
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Set the read protection level.\r
-  *\r
-  * @note   To configure the RDP level, the option lock bit OPTLOCK must be\r
-  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
-  * @note   To validate the RDP level, the option bytes must be reloaded\r
-  *         through the call of the HAL_FLASH_OB_Launch() function.\r
-  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible\r
-  *         to go back to level 1 or 0 !!!\r
-  *\r
-  * @param  RDPLevel: specifies the read protection level.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg OB_RDP_LEVEL_0: No protection\r
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r
-  *            @arg OB_RDP_LEVEL_2: Full chip protection\r
-  *\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)\r
-{\r
-  HAL_StatusTypeDef status;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_OB_RDP_LEVEL(RDPLevel));\r
-\r
-  /* Wait for last operation to be completed */\r
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-    /* Configure the RDP level in the option bytes register */\r
-    MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);\r
-\r
-    /* Set OPTSTRT Bit */\r
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-\r
-    /* Wait for last operation to be completed */\r
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Program the FLASH User Option Byte.\r
-  *\r
-  * @note   To configure the user option bytes, the option lock bit OPTLOCK must\r
-  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
-  * @note   To validate the user option bytes, the option bytes must be reloaded\r
-  *         through the call of the HAL_FLASH_OB_Launch() function.\r
-  *\r
-  * @param  UserType: The FLASH User Option Bytes to be modified\r
-  * @param  UserConfig: The FLASH User Option Bytes values:\r
-  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),\r
-  *         IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),\r
-  *         DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).\r
-  *\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)\r
-{\r
-  uint32_t optr_reg_val = 0;\r
-  uint32_t optr_reg_mask = 0;\r
-  HAL_StatusTypeDef status;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_OB_USER_TYPE(UserType));\r
-\r
-  /* Wait for last operation to be completed */\r
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-    if((UserType & OB_USER_BOR_LEV) != 0U)\r
-    {\r
-      /* BOR level option byte should be modified */\r
-      assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));\r
-\r
-      /* Set value and mask for BOR level option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);\r
-      optr_reg_mask |= FLASH_OPTR_BOR_LEV;\r
-    }\r
-\r
-    if((UserType & OB_USER_nRST_STOP) != 0U)\r
-    {\r
-      /* nRST_STOP option byte should be modified */\r
-      assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));\r
-\r
-      /* Set value and mask for nRST_STOP option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);\r
-      optr_reg_mask |= FLASH_OPTR_nRST_STOP;\r
-    }\r
-\r
-    if((UserType & OB_USER_nRST_STDBY) != 0U)\r
-    {\r
-      /* nRST_STDBY option byte should be modified */\r
-      assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));\r
-\r
-      /* Set value and mask for nRST_STDBY option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);\r
-      optr_reg_mask |= FLASH_OPTR_nRST_STDBY;\r
-    }\r
-\r
-    if((UserType & OB_USER_nRST_SHDW) != 0U)\r
-    {\r
-      /* nRST_SHDW option byte should be modified */\r
-      assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));\r
-\r
-      /* Set value and mask for nRST_SHDW option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);\r
-      optr_reg_mask |= FLASH_OPTR_nRST_SHDW;\r
-    }\r
-\r
-    if((UserType & OB_USER_IWDG_SW) != 0U)\r
-    {\r
-      /* IWDG_SW option byte should be modified */\r
-      assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));\r
-\r
-      /* Set value and mask for IWDG_SW option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);\r
-      optr_reg_mask |= FLASH_OPTR_IWDG_SW;\r
-    }\r
-\r
-    if((UserType & OB_USER_IWDG_STOP) != 0U)\r
-    {\r
-      /* IWDG_STOP option byte should be modified */\r
-      assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));\r
-\r
-      /* Set value and mask for IWDG_STOP option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);\r
-      optr_reg_mask |= FLASH_OPTR_IWDG_STOP;\r
-    }\r
-\r
-    if((UserType & OB_USER_IWDG_STDBY) != 0U)\r
-    {\r
-      /* IWDG_STDBY option byte should be modified */\r
-      assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));\r
-\r
-      /* Set value and mask for IWDG_STDBY option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);\r
-      optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;\r
-    }\r
-\r
-    if((UserType & OB_USER_WWDG_SW) != 0U)\r
-    {\r
-      /* WWDG_SW option byte should be modified */\r
-      assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));\r
-\r
-      /* Set value and mask for WWDG_SW option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);\r
-      optr_reg_mask |= FLASH_OPTR_WWDG_SW;\r
-    }\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-    if((UserType & OB_USER_BFB2) != 0U)\r
-    {\r
-      /* BFB2 option byte should be modified */\r
-      assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));\r
-\r
-      /* Set value and mask for BFB2 option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);\r
-      optr_reg_mask |= FLASH_OPTR_BFB2;\r
-    }\r
-\r
-    if((UserType & OB_USER_DUALBANK) != 0U)\r
-    {\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-      /* DUALBANK option byte should be modified */\r
-      assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M));\r
-\r
-      /* Set value and mask for DUALBANK option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M);\r
-      optr_reg_mask |= FLASH_OPTR_DB1M;\r
-#else\r
-      /* DUALBANK option byte should be modified */\r
-      assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));\r
-\r
-      /* Set value and mask for DUALBANK option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);\r
-      optr_reg_mask |= FLASH_OPTR_DUALBANK;\r
-#endif\r
-    }\r
-#endif\r
-\r
-    if((UserType & OB_USER_nBOOT1) != 0U)\r
-    {\r
-      /* nBOOT1 option byte should be modified */\r
-      assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));\r
-\r
-      /* Set value and mask for nBOOT1 option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);\r
-      optr_reg_mask |= FLASH_OPTR_nBOOT1;\r
-    }\r
-\r
-    if((UserType & OB_USER_SRAM2_PE) != 0U)\r
-    {\r
-      /* SRAM2_PE option byte should be modified */\r
-      assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));\r
-\r
-      /* Set value and mask for SRAM2_PE option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);\r
-      optr_reg_mask |= FLASH_OPTR_SRAM2_PE;\r
-    }\r
-\r
-    if((UserType & OB_USER_SRAM2_RST) != 0U)\r
-    {\r
-      /* SRAM2_RST option byte should be modified */\r
-      assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));\r
-\r
-      /* Set value and mask for SRAM2_RST option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);\r
-      optr_reg_mask |= FLASH_OPTR_SRAM2_RST;\r
-    }\r
-\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \\r
-    defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-    if((UserType & OB_USER_nSWBOOT0) != 0U)\r
-    {\r
-      /* nSWBOOT0 option byte should be modified */\r
-      assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));\r
-\r
-      /* Set value and mask for nSWBOOT0 option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);\r
-      optr_reg_mask |= FLASH_OPTR_nSWBOOT0;\r
-    }\r
-\r
-    if((UserType & OB_USER_nBOOT0) != 0U)\r
-    {\r
-      /* nBOOT0 option byte should be modified */\r
-      assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));\r
-\r
-      /* Set value and mask for nBOOT0 option byte */\r
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);\r
-      optr_reg_mask |= FLASH_OPTR_nBOOT0;\r
-    }\r
-#endif\r
-\r
-    /* Configure the option bytes register */\r
-    MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);\r
-\r
-    /* Set OPTSTRT Bit */\r
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-\r
-    /* Wait for last operation to be completed */\r
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the Proprietary code readout protection of the desired addresses.\r
-  *\r
-  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be\r
-  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
-  * @note   To validate the PCROP options, the option bytes must be reloaded\r
-  *         through the call of the HAL_FLASH_OB_Launch() function.\r
-  *\r
-  * @param  PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).\r
-  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2\r
-  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE\r
-  *\r
-  * @param  PCROPStartAddr: specifies the start address of the Proprietary code readout protection\r
-  *          This parameter can be an address between begin and end of the bank\r
-  *\r
-  * @param  PCROPEndAddr: specifies the end address of the Proprietary code readout protection\r
-  *          This parameter can be an address between PCROPStartAddr and end of the bank\r
-  *\r
-  * @retval HAL Status\r
-  */\r
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t reg_value;\r
-  uint32_t bank1_addr;\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  uint32_t bank2_addr;\r
-#endif\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));\r
-  assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));\r
-  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));\r
-  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));\r
-\r
-  /* Wait for last operation to be completed */\r
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-    /* Get the information about the bank swapping */\r
-    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)\r
-    {\r
-      bank1_addr = FLASH_BASE;\r
-      bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
-    }\r
-    else\r
-    {\r
-      bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
-      bank2_addr = FLASH_BASE;\r
-    }\r
-#else\r
-    bank1_addr = FLASH_BASE;\r
-#endif\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-    if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)\r
-    {\r
-      /* Configure the Proprietary code readout protection */\r
-      if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
-      {\r
-        reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);\r
-        MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);\r
-\r
-        reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);\r
-        MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);\r
-      }\r
-      else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
-      {\r
-        reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);\r
-        MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);\r
-\r
-        reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);\r
-        MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);\r
-      }\r
-      else\r
-      {\r
-        /* Nothing to do */\r
-      }\r
-    }\r
-    else\r
-#endif\r
-    {\r
-      /* Configure the Proprietary code readout protection */\r
-      if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
-      {\r
-        reg_value = ((PCROPStartAddr - bank1_addr) >> 3);\r
-        MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);\r
-\r
-        reg_value = ((PCROPEndAddr - bank1_addr) >> 3);\r
-        MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);\r
-      }\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-      else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
-      {\r
-        reg_value = ((PCROPStartAddr - bank2_addr) >> 3);\r
-        MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);\r
-\r
-        reg_value = ((PCROPEndAddr - bank2_addr) >> 3);\r
-        MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);\r
-      }\r
-#endif\r
-      else\r
-      {\r
-        /* Nothing to do */\r
-      }\r
-    }\r
-\r
-    MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));\r
-\r
-    /* Set OPTSTRT Bit */\r
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-\r
-    /* Wait for last operation to be completed */\r
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Return the FLASH Write Protection Option Bytes value.\r
-  *\r
-  * @param[in]  WRPArea: specifies the area to be returned.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A\r
-  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B\r
-  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)\r
-  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)\r
-  *\r
-  * @param[out]  WRPStartOffset: specifies the address where to copied the start page\r
-  *                         of the write protected area\r
-  *\r
-  * @param[out]  WRDPEndOffset: specifies the address where to copied the end page of\r
-  *                        the write protected area\r
-  *\r
-  * @retval None\r
-  */\r
-static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)\r
-{\r
-  /* Get the configuration of the write protected area */\r
-  if(WRPArea == OB_WRPAREA_BANK1_AREAA)\r
-  {\r
-    *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);\r
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);\r
-  }\r
-  else if(WRPArea == OB_WRPAREA_BANK1_AREAB)\r
-  {\r
-    *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);\r
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);\r
-  }\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  else if(WRPArea == OB_WRPAREA_BANK2_AREAA)\r
-  {\r
-    *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);\r
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);\r
-  }\r
-  else if(WRPArea == OB_WRPAREA_BANK2_AREAB)\r
-  {\r
-    *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);\r
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);\r
-  }\r
-#endif\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Return the FLASH Read Protection level.\r
-  * @retval FLASH ReadOut Protection Status:\r
-  *         This return value can be one of the following values:\r
-  *            @arg OB_RDP_LEVEL_0: No protection\r
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r
-  *            @arg OB_RDP_LEVEL_2: Full chip protection\r
-  */\r
-static uint32_t FLASH_OB_GetRDP(void)\r
-{\r
-  uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);\r
-\r
-  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))\r
-  {\r
-    return (OB_RDP_LEVEL_1);\r
-  }\r
-  else\r
-  {\r
-    return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Return the FLASH User Option Byte value.\r
-  * @retval The FLASH User Option Bytes values:\r
-  *      For STM32L47x/STM32L48x devices :\r
-  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),\r
-  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),\r
-  *         BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).\r
-  *      For STM32L43x/STM32L44x devices :\r
-  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),\r
-  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),\r
-  *         nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).\r
-  */\r
-static uint32_t FLASH_OB_GetUser(void)\r
-{\r
-  uint32_t user_config = READ_REG(FLASH->OPTR);\r
-  CLEAR_BIT(user_config, FLASH_OPTR_RDP);\r
-\r
-  return user_config;\r
-}\r
-\r
-/**\r
-  * @brief  Return the FLASH Write Protection Option Bytes value.\r
-  *\r
-  * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).\r
-  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2\r
-  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE\r
-  *\r
-  * @param PCROPStartAddr [out]: specifies the address where to copied the start address\r
-  *                         of the Proprietary code readout protection\r
-  *\r
-  * @param PCROPEndAddr [out]: specifies the address where to copied the end address of\r
-  *                       the Proprietary code readout protection\r
-  *\r
-  * @retval None\r
-  */\r
-static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)\r
-{\r
-  uint32_t reg_value;\r
-  uint32_t bank1_addr;\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  uint32_t bank2_addr;\r
-#endif\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  /* Get the information about the bank swapping */\r
-  if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)\r
-  {\r
-    bank1_addr = FLASH_BASE;\r
-    bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
-  }\r
-  else\r
-  {\r
-    bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;\r
-    bank2_addr = FLASH_BASE;\r
-  }\r
-#else\r
-  bank1_addr = FLASH_BASE;\r
-#endif\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)\r
-  {\r
-    if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
-    {\r
-      reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);\r
-      *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;\r
-\r
-      reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);\r
-      *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;\r
-    }\r
-    else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
-    {\r
-      reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);\r
-      *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;\r
-\r
-      reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);\r
-      *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;;\r
-    }\r
-    else\r
-    {\r
-      /* Nothing to do */\r
-    }\r
-  }\r
-  else\r
-#endif\r
-  {\r
-    if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)\r
-    {\r
-      reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);\r
-      *PCROPStartAddr = (reg_value << 3) + bank1_addr;\r
-\r
-      reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);\r
-      *PCROPEndAddr = (reg_value << 3) + bank1_addr + 0x7U;\r
-    }\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
-    defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-    else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)\r
-    {\r
-      reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);\r
-      *PCROPStartAddr = (reg_value << 3) + bank2_addr;\r
-\r
-      reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);\r
-      *PCROPEndAddr = (reg_value << 3) + bank2_addr + 0x7U;\r
-    }\r
-#endif\r
-    else\r
-    {\r
-      /* Nothing to do */\r
-    }\r
-  }\r
-\r
-  *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);\r
-}\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_FLASH_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
deleted file mode 100644 (file)
index 7d32ef7..0000000
+++ /dev/null
@@ -1,256 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_flash_ramfunc.c\r
-  * @author  MCD Application Team\r
-  * @brief   FLASH RAMFUNC driver.\r
-  *          This file provides a Flash firmware functions which should be\r
-  *          executed from internal SRAM\r
-  *            + FLASH HalfPage Programming\r
-  *            + FLASH Power Down in Run mode\r
-  *\r
-  *  @verbatim\r
-  ==============================================================================\r
-                   ##### Flash RAM functions #####\r
-  ==============================================================================\r
-\r
-    *** ARM Compiler ***\r
-    --------------------\r
-    [..] RAM functions are defined using the toolchain options.\r
-         Functions that are executed in RAM should reside in a separate\r
-         source module. Using the 'Options for File' dialog you can simply change\r
-         the 'Code / Const' area of a module to a memory space in physical RAM.\r
-         Available memory areas are declared in the 'Target' tab of the\r
-         Options for Target' dialog.\r
-\r
-    *** ICCARM Compiler ***\r
-    -----------------------\r
-    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
-\r
-    *** GNU Compiler ***\r
-    --------------------\r
-    [..] RAM functions are defined using a specific toolchain attribute\r
-         "__attribute__((section(".RamFunc")))".\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC\r
-  * @brief FLASH functions executed from RAM\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_FLASH_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-extern FLASH_ProcessTypeDef pFlash;\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Exported functions -------------------------------------------------------*/\r
-\r
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions\r
- *  @brief   Data transfers functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### ramfunc functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions that should be executed from RAM.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief   Enable the Power down in Run Mode\r
-  * @note    This function should be called and executed from SRAM memory\r
-  * @retval None\r
-  */\r
-__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)\r
-{\r
-  /* Enable the Power Down in Run mode*/\r
-  __HAL_FLASH_POWER_DOWN_ENABLE();\r
-\r
-  return HAL_OK;\r
-\r
-}\r
-\r
-/**\r
-  * @brief   Disable the Power down in Run Mode\r
-  * @note    This function should be called and executed from SRAM memory\r
-  * @retval None\r
-  */\r
-__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)\r
-{\r
-  /* Disable the Power Down in Run mode*/\r
-  __HAL_FLASH_POWER_DOWN_DISABLE();\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-/**\r
-  * @brief  Program the FLASH DBANK User Option Byte.\r
-  *\r
-  * @note   To configure the user option bytes, the option lock bit OPTLOCK must\r
-  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
-  * @note   To modify the DBANK option byte, no PCROP region should be defined.\r
-  *         To deactivate PCROP, user should perform RDP changing\r
-  *\r
-  * @param  DBankConfig: The FLASH DBANK User Option Byte value.\r
-  *          This parameter  can be one of the following values:\r
-  *            @arg OB_DBANK_128_BITS: Single-bank with 128-bits data\r
-  *            @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data\r
-  *\r
-  * @retval HAL status\r
-  */\r
-__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)\r
-{\r
-  register uint32_t count, reg;\r
-  HAL_StatusTypeDef status = HAL_ERROR;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(&pFlash);\r
-\r
-  /* Check if the PCROP is disabled */\r
-  reg = FLASH->PCROP1SR;\r
-  if (reg > FLASH->PCROP1ER)\r
-  {\r
-    reg = FLASH->PCROP2SR;\r
-    if (reg > FLASH->PCROP2ER)\r
-    {\r
-      /* Disable Flash prefetch */\r
-      __HAL_FLASH_PREFETCH_BUFFER_DISABLE();\r
-\r
-      if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)\r
-      {\r
-        /* Disable Flash instruction cache */\r
-        __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
-\r
-        /* Flush Flash instruction cache */\r
-        __HAL_FLASH_INSTRUCTION_CACHE_RESET();\r
-      }\r
-\r
-      if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
-      {\r
-        /* Disable Flash data cache */\r
-        __HAL_FLASH_DATA_CACHE_DISABLE();\r
-\r
-        /* Flush Flash data cache */\r
-        __HAL_FLASH_DATA_CACHE_RESET();\r
-      }\r
-\r
-      /* Disable WRP zone 1 of 1st bank if needed */\r
-      reg = FLASH->WRP1AR;\r
-      if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=\r
-          ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))\r
-      {\r
-        MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);\r
-      }\r
-\r
-      /* Disable WRP zone 2 of 1st bank if needed */\r
-      reg = FLASH->WRP1BR;\r
-      if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=\r
-          ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))\r
-      {\r
-        MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);\r
-      }\r
-\r
-      /* Disable WRP zone 1 of 2nd bank if needed */\r
-      reg = FLASH->WRP2AR;\r
-      if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=\r
-          ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))\r
-      {\r
-        MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);\r
-      }\r
-\r
-      /* Disable WRP zone 2 of 2nd bank if needed */\r
-      reg = FLASH->WRP2BR;\r
-      if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=\r
-          ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))\r
-      {\r
-        MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);\r
-      }\r
-\r
-      /* Modify the DBANK user option byte */\r
-      MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);\r
-\r
-      /* Set OPTSTRT Bit */\r
-      SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-\r
-      /* Wait for last operation to be completed */\r
-      /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */\r
-      count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);\r
-      do\r
-      {\r
-        if (count == 0U)\r
-        {\r
-          break;\r
-        }\r
-        count--;\r
-      } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);\r
-\r
-      /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
-      CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
-\r
-      /* Set the bit to force the option byte reloading */\r
-      SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);\r
-    }\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(&pFlash);\r
-\r
-  return status;\r
-}\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* HAL_FLASH_MODULE_ENABLED */\r
-\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
deleted file mode 100644 (file)
index 851121a..0000000
+++ /dev/null
@@ -1,557 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_gpio.c\r
-  * @author  MCD Application Team\r
-  * @brief   GPIO HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
-  *           + Initialization and de-initialization functions\r
-  *           + IO operation functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                    ##### GPIO Peripheral features #####\r
-  ==============================================================================\r
-  [..]\r
-    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually\r
-        configured by software in several modes:\r
-        (++) Input mode\r
-        (++) Analog mode\r
-        (++) Output mode\r
-        (++) Alternate function mode\r
-        (++) External interrupt/event lines\r
-\r
-    (+) During and just after reset, the alternate functions and external interrupt\r
-        lines are not active and the I/O ports are configured in input floating mode.\r
-\r
-    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be\r
-        activated or not.\r
-\r
-    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
-        type and the IO speed can be selected depending on the VDD value.\r
-\r
-    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a\r
-        multiplexer that allows only one peripheral alternate function (AF) connected\r
-       to an IO pin at a time. In this way, there can be no conflict between peripherals\r
-       sharing the same IO pin.\r
-\r
-    (+) All ports have external interrupt/event capability. To use external interrupt\r
-        lines, the port must be configured in input mode. All available GPIO pins are\r
-        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
-\r
-    (+) The external interrupt/event controller consists of up to 39 edge detectors\r
-        (16 lines are connected to GPIO) for generating event/interrupt requests (each\r
-        input line can be independently configured to select the type (interrupt or event)\r
-        and the corresponding trigger event (rising or falling or both). Each line can\r
-        also be masked independently.\r
-\r
-                     ##### How to use this driver #####\r
-  ==============================================================================\r
-  [..]\r
-    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().\r
-\r
-    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
-        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
-        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef\r
-             structure.\r
-        (++) In case of Output or alternate function mode selection: the speed is\r
-             configured through "Speed" member from GPIO_InitTypeDef structure.\r
-        (++) In alternate mode is selection, the alternate function connected to the IO\r
-             is configured through "Alternate" member from GPIO_InitTypeDef structure.\r
-        (++) Analog mode is required when a pin is to be used as ADC channel\r
-             or DAC output.\r
-        (++) In case of external interrupt/event selection the "Mode" member from\r
-             GPIO_InitTypeDef structure select the type (interrupt or event) and\r
-             the corresponding trigger event (rising or falling or both).\r
-\r
-    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority\r
-        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
-        HAL_NVIC_EnableIRQ().\r
-\r
-    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
-\r
-    (#) To set/reset the level of a pin configured in output mode use\r
-        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
-\r
-   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
-\r
-    (#) During and just after reset, the alternate functions are not\r
-        active and the GPIO pins are configured in input floating mode (except JTAG\r
-        pins).\r
-\r
-    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose\r
-        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has\r
-        priority over the GPIO function.\r
-\r
-    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as\r
-        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.\r
-        The HSE has priority over the GPIO function.\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup GPIO GPIO\r
-  * @brief GPIO HAL module driver\r
-  * @{\r
-  */\r
-/** MISRA C:2012 deviation rule has been granted for following rules:\r
-  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of\r
-  * range of the shift operator in following API :\r
-  * HAL_GPIO_Init\r
-  * HAL_GPIO_DeInit\r
-  */\r
-\r
-#ifdef HAL_GPIO_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private defines -----------------------------------------------------------*/\r
-/** @defgroup GPIO_Private_Defines GPIO Private Defines\r
-  * @{\r
-  */\r
-#define GPIO_MODE             (0x00000003u)\r
-#define ANALOG_MODE           (0x00000008u)\r
-#define EXTI_MODE             (0x10000000u)\r
-#define GPIO_MODE_IT          (0x00010000u)\r
-#define GPIO_MODE_EVT         (0x00020000u)\r
-#define RISING_EDGE           (0x00100000u)\r
-#define FALLING_EDGE          (0x00200000u)\r
-#define GPIO_OUTPUT_TYPE      (0x00000010u)\r
-\r
-#define GPIO_NUMBER           (16u)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions\r
- *  @brief    Initialization and Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-              ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains\r
-  *         the configuration information for the specified GPIO peripheral.\r
-  * @retval None\r
-  */\r
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
-{\r
-  uint32_t position = 0x00u;\r
-  uint32_t iocurrent;\r
-  uint32_t temp;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
-  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r
-\r
-  /* Configure the port pins */\r
-  while (((GPIO_Init->Pin) >> position) != 0x00u)\r
-  {\r
-    /* Get current io position */\r
-    iocurrent = (GPIO_Init->Pin) & (1uL << position);\r
-\r
-    if (iocurrent != 0x00u)\r
-    {\r
-      /*--------------------- GPIO Mode Configuration ------------------------*/\r
-      /* In case of Alternate function mode selection */\r
-      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
-      {\r
-        /* Check the Alternate function parameters */\r
-        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));\r
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r
-\r
-        /* Configure Alternate function mapped with the current IO */\r
-        temp = GPIOx->AFR[position >> 3u];\r
-        temp &= ~(0xFu << ((position & 0x07u) * 4u));\r
-        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));\r
-        GPIOx->AFR[position >> 3u] = temp;\r
-      }\r
-\r
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r
-      temp = GPIOx->MODER;\r
-      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));\r
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));\r
-      GPIOx->MODER = temp;\r
-\r
-      /* In case of Output or Alternate function mode selection */\r
-      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r
-         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
-      {\r
-        /* Check the Speed parameter */\r
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
-        /* Configure the IO Speed */\r
-        temp = GPIOx->OSPEEDR;\r
-        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));\r
-        temp |= (GPIO_Init->Speed << (position * 2u));\r
-        GPIOx->OSPEEDR = temp;\r
-\r
-        /* Configure the IO Output Type */\r
-        temp = GPIOx->OTYPER;\r
-        temp &= ~(GPIO_OTYPER_OT0 << position) ;\r
-        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);\r
-        GPIOx->OTYPER = temp;\r
-      }\r
-\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-\r
-      /* In case of Analog mode, check if ADC control mode is selected */\r
-      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)\r
-      {\r
-        /* Configure the IO Output Type */\r
-        temp = GPIOx->ASCR;\r
-        temp &= ~(GPIO_ASCR_ASC0 << position) ;\r
-        temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);\r
-        GPIOx->ASCR = temp;\r
-      }\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
-\r
-      /* Activate the Pull-up or Pull down resistor for the current IO */\r
-      temp = GPIOx->PUPDR;\r
-      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));\r
-      temp |= ((GPIO_Init->Pull) << (position * 2u));\r
-      GPIOx->PUPDR = temp;\r
-\r
-      /*--------------------- EXTI Mode Configuration ------------------------*/\r
-      /* Configure the External Interrupt or event for the current IO */\r
-      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r
-      {\r
-        /* Enable SYSCFG Clock */\r
-        __HAL_RCC_SYSCFG_CLK_ENABLE();\r
-\r
-        temp = SYSCFG->EXTICR[position >> 2u];\r
-        temp &= ~(0x0FuL << (4u * (position & 0x03u)));\r
-        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));\r
-        SYSCFG->EXTICR[position >> 2u] = temp;\r
-\r
-        /* Clear EXTI line configuration */\r
-        temp = EXTI->IMR1;\r
-        temp &= ~(iocurrent);\r
-        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
-        {\r
-          temp |= iocurrent;\r
-        }\r
-        EXTI->IMR1 = temp;\r
-\r
-        temp = EXTI->EMR1;\r
-        temp &= ~(iocurrent);\r
-        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
-        {\r
-          temp |= iocurrent;\r
-        }\r
-        EXTI->EMR1 = temp;\r
-\r
-        /* Clear Rising Falling edge configuration */\r
-        temp = EXTI->RTSR1;\r
-        temp &= ~(iocurrent);\r
-        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
-        {\r
-          temp |= iocurrent;\r
-        }\r
-        EXTI->RTSR1 = temp;\r
-\r
-        temp = EXTI->FTSR1;\r
-        temp &= ~(iocurrent);\r
-        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
-        {\r
-          temp |= iocurrent;\r
-        }\r
-        EXTI->FTSR1 = temp;\r
-      }\r
-    }\r
-\r
-    position++;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.\r
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
-  * @param  GPIO_Pin: specifies the port bit to be written.\r
-  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
-  * @retval None\r
-  */\r
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)\r
-{\r
-  uint32_t position = 0x00u;\r
-  uint32_t iocurrent;\r
-  uint32_t tmp;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
-  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
-  /* Configure the port pins */\r
-  while ((GPIO_Pin >> position) != 0x00u)\r
-  {\r
-    /* Get current io position */\r
-    iocurrent = (GPIO_Pin) & (1uL << position);\r
-\r
-    if (iocurrent != 0x00u)\r
-    {\r
-      /*------------------------- EXTI Mode Configuration --------------------*/\r
-      /* Clear the External Interrupt or Event for the current IO */\r
-\r
-      tmp = SYSCFG->EXTICR[position >> 2u];\r
-      tmp &= (0x0FuL << (4u * (position & 0x03u)));\r
-      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))\r
-      {\r
-        /* Clear EXTI line configuration */\r
-        EXTI->IMR1 &= ~(iocurrent);\r
-        EXTI->EMR1 &= ~(iocurrent);\r
-\r
-        /* Clear Rising Falling edge configuration */\r
-        EXTI->RTSR1 &= ~(iocurrent);\r
-        EXTI->FTSR1 &= ~(iocurrent);\r
-\r
-        tmp = 0x0FuL << (4u * (position & 0x03u));\r
-        SYSCFG->EXTICR[position >> 2u] &= ~tmp;\r
-      }\r
-\r
-      /*------------------------- GPIO Mode Configuration --------------------*/\r
-      /* Configure IO in Analog Mode */\r
-      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));\r
-\r
-      /* Configure the default Alternate Function in current IO */\r
-      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;\r
-\r
-      /* Configure the default value for IO Speed */\r
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));\r
-\r
-      /* Configure the default value IO Output Type */\r
-      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;\r
-\r
-      /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));\r
-\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-      /* Deactivate the Control bit of Analog mode for the current IO */\r
-      GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
-    }\r
-\r
-    position++;\r
-  }\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions\r
- *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                       ##### IO operation functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Read the specified input port pin.\r
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
-  * @param  GPIO_Pin: specifies the port bit to read.\r
-  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
-  * @retval The input port pin value.\r
-  */\r
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
-  GPIO_PinState bitstatus;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
-  if ((GPIOx->IDR & GPIO_Pin) != 0x00u)\r
-  {\r
-    bitstatus = GPIO_PIN_SET;\r
-  }\r
-  else\r
-  {\r
-    bitstatus = GPIO_PIN_RESET;\r
-  }\r
-  return bitstatus;\r
-}\r
-\r
-/**\r
-  * @brief  Set or clear the selected data port bit.\r
-  *\r
-  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify\r
-  *         accesses. In this way, there is no risk of an IRQ occurring between\r
-  *         the read and the modify access.\r
-  *\r
-  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
-  * @param  GPIO_Pin specifies the port bit to be written.\r
-  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
-  * @param  PinState specifies the value to be written to the selected bit.\r
-  *         This parameter can be one of the GPIO_PinState enum values:\r
-  *            @arg GPIO_PIN_RESET: to clear the port pin\r
-  *            @arg GPIO_PIN_SET: to set the port pin\r
-  * @retval None\r
-  */\r
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-  assert_param(IS_GPIO_PIN_ACTION(PinState));\r
-\r
-  if(PinState != GPIO_PIN_RESET)\r
-  {\r
-    GPIOx->BSRR = (uint32_t)GPIO_Pin;\r
-  }\r
-  else\r
-  {\r
-    GPIOx->BRR = (uint32_t)GPIO_Pin;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Toggle the specified GPIO pin.\r
-  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
-  * @param  GPIO_Pin specifies the pin to be toggled.\r
-  * @retval None\r
-  */\r
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
-  if ((GPIOx->ODR & GPIO_Pin) != 0x00u)\r
-  {\r
-    GPIOx->BRR = (uint32_t)GPIO_Pin;\r
-  }\r
-  else\r
-  {\r
-    GPIOx->BSRR = (uint32_t)GPIO_Pin;\r
-  }\r
-}\r
-\r
-/**\r
-* @brief  Lock GPIO Pins configuration registers.\r
-  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
-  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
-  * @note   The configuration of the locked GPIO pins can no longer be modified\r
-  *         until the next reset.\r
-  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family\r
-  * @param  GPIO_Pin specifies the port bits to be locked.\r
-  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
-  * @retval None\r
-  */\r
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
-{\r
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));\r
-  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
-  /* Apply lock key write sequence */\r
-  tmp |= GPIO_Pin;\r
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
-  GPIOx->LCKR = tmp;\r
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
-  GPIOx->LCKR = GPIO_Pin;\r
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
-  GPIOx->LCKR = tmp;\r
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */\r
-  tmp = GPIOx->LCKR;\r
-\r
-  /* Read again in order to confirm lock is active */\r
-  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)\r
-  {\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Handle EXTI interrupt request.\r
-  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.\r
-  * @retval None\r
-  */\r
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
-{\r
-  /* EXTI line interrupt detected */\r
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)\r
-  {\r
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  EXTI line detection callback.\r
-  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.\r
-  * @retval None\r
-  */\r
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(GPIO_Pin);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_GPIO_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
deleted file mode 100644 (file)
index 75be2ea..0000000
+++ /dev/null
@@ -1,6502 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_i2c.c\r
-  * @author  MCD Application Team\r
-  * @brief   I2C HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:\r
-  *           + Initialization and de-initialization functions\r
-  *           + IO operation functions\r
-  *           + Peripheral State and Errors functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                        ##### How to use this driver #####\r
-  ==============================================================================\r
-    [..]\r
-    The I2C HAL driver can be used as follows:\r
-\r
-    (#) Declare a I2C_HandleTypeDef handle structure, for example:\r
-        I2C_HandleTypeDef  hi2c;\r
-\r
-    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:\r
-        (##) Enable the I2Cx interface clock\r
-        (##) I2C pins configuration\r
-            (+++) Enable the clock for the I2C GPIOs\r
-            (+++) Configure I2C pins as alternate function open-drain\r
-        (##) NVIC configuration if you need to use interrupt process\r
-            (+++) Configure the I2Cx interrupt priority\r
-            (+++) Enable the NVIC I2C IRQ Channel\r
-        (##) DMA Configuration if you need to use DMA process\r
-            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel\r
-            (+++) Enable the DMAx interface clock using\r
-            (+++) Configure the DMA handle parameters\r
-            (+++) Configure the DMA Tx or Rx channel\r
-            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\r
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on\r
-                  the DMA Tx or Rx channel\r
-\r
-    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,\r
-        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.\r
-\r
-    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware\r
-        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.\r
-\r
-    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()\r
-\r
-    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\r
-\r
-    *** Polling mode IO operation ***\r
-    =================================\r
-    [..]\r
-      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()\r
-      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()\r
-      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()\r
-      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()\r
-\r
-    *** Polling mode IO MEM operation ***\r
-    =====================================\r
-    [..]\r
-      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()\r
-      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()\r
-\r
-\r
-    *** Interrupt mode IO operation ***\r
-    ===================================\r
-    [..]\r
-      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()\r
-      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
-      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()\r
-      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
-      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()\r
-      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
-      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()\r
-      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
-      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
-      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
-      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
-           This action will inform Master to generate a Stop condition to discard the communication.\r
-\r
-\r
-    *** Interrupt mode or DMA mode IO sequential operation ***\r
-    ==========================================================\r
-    [..]\r
-      (@) These interfaces allow to manage a sequential transfer with a repeated start condition\r
-          when a direction change during transfer\r
-    [..]\r
-      (+) A specific option field manage the different steps of a sequential transfer\r
-      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:\r
-      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode\r
-      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address\r
-                            and data to transfer without a final stop condition\r
-      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address\r
-                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface\r
-                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()\r
-                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())\r
-      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address\r
-                            and with new data to transfer if the direction change or manage only the new data to transfer\r
-                            if no direction change and without a final stop condition in both cases\r
-      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address\r
-                            and with new data to transfer if the direction change or manage only the new data to transfer\r
-                            if no direction change and with a final stop condition in both cases\r
-      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential\r
-                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).\r
-                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
-                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
-                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
-                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).\r
-                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit\r
-                              without stopping the communication and so generate a restart condition.\r
-      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential\r
-                            interface.\r
-                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
-                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
-                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
-                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).\r
-                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.\r
-\r
-      (+) Differents sequential I2C interfaces are listed below:\r
-      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()\r
-            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()\r
-      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
-      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()\r
-            or using @ref HAL_I2C_Master_Seq_Receive_DMA()\r
-      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
-      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
-      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
-      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()\r
-      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can\r
-           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).\r
-      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()\r
-      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()\r
-            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()\r
-      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
-      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()\r
-            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()\r
-      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
-      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
-      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
-           This action will inform Master to generate a Stop condition to discard the communication.\r
-\r
-    *** Interrupt mode IO MEM operation ***\r
-    =======================================\r
-    [..]\r
-      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using\r
-          @ref HAL_I2C_Mem_Write_IT()\r
-      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\r
-      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using\r
-          @ref HAL_I2C_Mem_Read_IT()\r
-      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\r
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
-\r
-    *** DMA mode IO operation ***\r
-    ==============================\r
-    [..]\r
-      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using\r
-          @ref HAL_I2C_Master_Transmit_DMA()\r
-      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
-      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using\r
-          @ref HAL_I2C_Master_Receive_DMA()\r
-      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
-      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using\r
-          @ref HAL_I2C_Slave_Transmit_DMA()\r
-      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
-      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using\r
-          @ref HAL_I2C_Slave_Receive_DMA()\r
-      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
-      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
-      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
-      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
-           This action will inform Master to generate a Stop condition to discard the communication.\r
-\r
-    *** DMA mode IO MEM operation ***\r
-    =================================\r
-    [..]\r
-      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using\r
-          @ref HAL_I2C_Mem_Write_DMA()\r
-      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\r
-      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using\r
-          @ref HAL_I2C_Mem_Read_DMA()\r
-      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\r
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
-\r
-\r
-     *** I2C HAL driver macros list ***\r
-     ==================================\r
-     [..]\r
-       Below the list of most used macros in I2C HAL driver.\r
-\r
-      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral\r
-      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral\r
-      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode\r
-      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not\r
-      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag\r
-      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt\r
-      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\r
-\r
-     *** Callback registration ***\r
-     =============================================\r
-    [..]\r
-     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1\r
-     allows the user to configure dynamically the driver callbacks.\r
-     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()\r
-     to register an interrupt callback.\r
-    [..]\r
-     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:\r
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\r
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.\r
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.\r
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.\r
-       (+) ListenCpltCallback   : callback for end of listen mode.\r
-       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.\r
-       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.\r
-       (+) ErrorCallback        : callback for error detection.\r
-       (+) AbortCpltCallback    : callback for abort completion process.\r
-       (+) MspInitCallback      : callback for Msp Init.\r
-       (+) MspDeInitCallback    : callback for Msp DeInit.\r
-     This function takes as parameters the HAL peripheral handle, the Callback ID\r
-     and a pointer to the user callback function.\r
-    [..]\r
-     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().\r
-    [..]\r
-     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default\r
-     weak function.\r
-     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
-     and the Callback ID.\r
-     This function allows to reset following callbacks:\r
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\r
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.\r
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.\r
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.\r
-       (+) ListenCpltCallback   : callback for end of listen mode.\r
-       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.\r
-       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.\r
-       (+) ErrorCallback        : callback for error detection.\r
-       (+) AbortCpltCallback    : callback for abort completion process.\r
-       (+) MspInitCallback      : callback for Msp Init.\r
-       (+) MspDeInitCallback    : callback for Msp DeInit.\r
-    [..]\r
-     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().\r
-    [..]\r
-     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET\r
-     all callbacks are set to the corresponding weak functions:\r
-     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().\r
-     Exception done for MspInit and MspDeInit functions that are\r
-     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when\r
-     these callbacks are null (not registered beforehand).\r
-     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()\r
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\r
-    [..]\r
-     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.\r
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered\r
-     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,\r
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\r
-     Then, the user first registers the MspInit/MspDeInit user callbacks\r
-     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()\r
-     or @ref HAL_I2C_Init() function.\r
-    [..]\r
-     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or\r
-     not defined, the callback registration feature is not available and all callbacks\r
-     are set to the corresponding weak functions.\r
-\r
-     [..]\r
-       (@) You can refer to the I2C HAL driver header file for more useful macros\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup I2C I2C\r
-  * @brief I2C HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_I2C_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/** @defgroup I2C_Private_Define I2C Private Define\r
-  * @{\r
-  */\r
-#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */\r
-#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */\r
-#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */\r
-#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */\r
-#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */\r
-#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */\r
-#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */\r
-#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */\r
-#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */\r
-#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */\r
-\r
-#define MAX_NBYTE_SIZE      255U\r
-#define SlaveAddr_SHIFT     7U\r
-#define SlaveAddr_MSK       0x06U\r
-\r
-/* Private define for @ref PreviousState usage */\r
-#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */\r
-#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */\r
-#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */\r
-#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */\r
-#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */\r
-#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */\r
-#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */\r
-#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */\r
-\r
-\r
-/* Private define to centralize the enable/disable of Interrupts */\r
-#define I2C_XFER_TX_IT          (0x00000001U)\r
-#define I2C_XFER_RX_IT          (0x00000002U)\r
-#define I2C_XFER_LISTEN_IT      (0x00000004U)\r
-\r
-#define I2C_XFER_ERROR_IT       (0x00000011U)\r
-#define I2C_XFER_CPLT_IT        (0x00000012U)\r
-#define I2C_XFER_RELOAD_IT      (0x00000012U)\r
-\r
-/* Private define Sequential Transfer Options default/reset value */\r
-#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-\r
-/** @defgroup I2C_Private_Functions I2C Private Functions\r
-  * @{\r
-  */\r
-/* Private functions to handle DMA transfer */\r
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);\r
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);\r
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);\r
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);\r
-\r
-/* Private functions to handle IT transfer */\r
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
-static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);\r
-static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);\r
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);\r
-\r
-/* Private functions to handle IT transfer */\r
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
-\r
-/* Private functions for I2C transfer IRQ handler */\r
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
-\r
-/* Private functions to handle flags during polling transfer */\r
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
-\r
-/* Private functions to centralize the enable/disable of Interrupts */\r
-static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
-static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
-\r
-/* Private function to flush TXDR register */\r
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);\r
-\r
-/* Private function to handle  start, restart or stop a transfer */\r
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\r
-\r
-/* Private function to Convert Specific options */\r
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup I2C_Exported_Functions I2C Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
- *  @brief    Initialization and Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-              ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
-    [..]  This subsection provides a set of functions allowing to initialize and\r
-          deinitialize the I2Cx peripheral:\r
-\r
-      (+) User must Implement HAL_I2C_MspInit() function in which he configures\r
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
-\r
-      (+) Call the function HAL_I2C_Init() to configure the selected device with\r
-          the selected configuration:\r
-        (++) Clock Timing\r
-        (++) Own Address 1\r
-        (++) Addressing mode (Master, Slave)\r
-        (++) Dual Addressing mode\r
-        (++) Own Address 2\r
-        (++) Own Address 2 Mask\r
-        (++) General call mode\r
-        (++) Nostretch mode\r
-\r
-      (+) Call the function HAL_I2C_DeInit() to restore the default configuration\r
-          of the selected I2Cx peripheral.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initializes the I2C according to the specified parameters\r
-  *         in the I2C_InitTypeDef and initialize the associated handle.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Check the I2C handle allocation */\r
-  if (hi2c == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
-  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\r
-  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\r
-  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\r
-  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\r
-  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));\r
-  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\r
-  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    hi2c->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    /* Init the I2C Callback settings */\r
-    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\r
-    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\r
-    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */\r
-    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */\r
-    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */\r
-    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */\r
-    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */\r
-    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */\r
-    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */\r
-    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */\r
-\r
-    if (hi2c->MspInitCallback == NULL)\r
-    {\r
-      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */\r
-    }\r
-\r
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
-    hi2c->MspInitCallback(hi2c);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
-    HAL_I2C_MspInit(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  hi2c->State = HAL_I2C_STATE_BUSY;\r
-\r
-  /* Disable the selected I2C peripheral */\r
-  __HAL_I2C_DISABLE(hi2c);\r
-\r
-  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/\r
-  /* Configure I2Cx: Frequency range */\r
-  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;\r
-\r
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r
-  /* Disable Own Address1 before set the Own Address1 configuration */\r
-  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;\r
-\r
-  /* Configure I2Cx: Own Address1 and ack own address1 mode */\r
-  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\r
-  {\r
-    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);\r
-  }\r
-  else /* I2C_ADDRESSINGMODE_10BIT */\r
-  {\r
-    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);\r
-  }\r
-\r
-  /*---------------------------- I2Cx CR2 Configuration ----------------------*/\r
-  /* Configure I2Cx: Addressing Master mode */\r
-  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
-  {\r
-    hi2c->Instance->CR2 = (I2C_CR2_ADD10);\r
-  }\r
-  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */\r
-  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);\r
-\r
-  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\r
-  /* Disable Own Address2 before set the Own Address2 configuration */\r
-  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;\r
-\r
-  /* Configure I2Cx: Dual mode and Own Address2 */\r
-  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));\r
-\r
-  /*---------------------------- I2Cx CR1 Configuration ----------------------*/\r
-  /* Configure I2Cx: Generalcall and NoStretch mode */\r
-  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);\r
-\r
-  /* Enable the selected I2C peripheral */\r
-  __HAL_I2C_ENABLE(hi2c);\r
-\r
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-  hi2c->State = HAL_I2C_STATE_READY;\r
-  hi2c->PreviousState = I2C_STATE_NONE;\r
-  hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitialize the I2C peripheral.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Check the I2C handle allocation */\r
-  if (hi2c == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
-\r
-  hi2c->State = HAL_I2C_STATE_BUSY;\r
-\r
-  /* Disable the I2C Peripheral Clock */\r
-  __HAL_I2C_DISABLE(hi2c);\r
-\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-  if (hi2c->MspDeInitCallback == NULL)\r
-  {\r
-    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */\r
-  }\r
-\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
-  hi2c->MspDeInitCallback(hi2c);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
-  HAL_I2C_MspDeInit(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-\r
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-  hi2c->State = HAL_I2C_STATE_RESET;\r
-  hi2c->PreviousState = I2C_STATE_NONE;\r
-  hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hi2c);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Initialize the I2C MSP.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief DeInitialize the I2C MSP.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  Register a User I2C Callback\r
-  *         To be used instead of the weak predefined callback\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  CallbackID ID of the callback to be registered\r
-  *         This parameter can be one of the following values:\r
-  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\r
-  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\r
-  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\r
-  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\r
-  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\r
-  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\r
-  * @param  pCallback pointer to the Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-  /* Process locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if (HAL_I2C_STATE_READY == hi2c->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\r
-        hi2c->MasterTxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\r
-        hi2c->MasterRxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\r
-        hi2c->SlaveTxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\r
-        hi2c->SlaveRxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_LISTEN_COMPLETE_CB_ID :\r
-        hi2c->ListenCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\r
-        hi2c->MemTxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\r
-        hi2c->MemRxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_ERROR_CB_ID :\r
-        hi2c->ErrorCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_ABORT_CB_ID :\r
-        hi2c->AbortCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_MSPINIT_CB_ID :\r
-        hi2c->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_MSPDEINIT_CB_ID :\r
-        hi2c->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (HAL_I2C_STATE_RESET == hi2c->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_I2C_MSPINIT_CB_ID :\r
-        hi2c->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_I2C_MSPDEINIT_CB_ID :\r
-        hi2c->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hi2c);\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister an I2C Callback\r
-  *         I2C callback is redirected to the weak predefined callback\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  CallbackID ID of the callback to be unregistered\r
-  *         This parameter can be one of the following values:\r
-  *         This parameter can be one of the following values:\r
-  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\r
-  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\r
-  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\r
-  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\r
-  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\r
-  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\r
-  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if (HAL_I2C_STATE_READY == hi2c->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\r
-        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\r
-        break;\r
-\r
-      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\r
-        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\r
-        break;\r
-\r
-      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\r
-        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */\r
-        break;\r
-\r
-      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\r
-        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */\r
-        break;\r
-\r
-      case HAL_I2C_LISTEN_COMPLETE_CB_ID :\r
-        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */\r
-        break;\r
-\r
-      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\r
-        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */\r
-        break;\r
-\r
-      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\r
-        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */\r
-        break;\r
-\r
-      case HAL_I2C_ERROR_CB_ID :\r
-        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */\r
-        break;\r
-\r
-      case HAL_I2C_ABORT_CB_ID :\r
-        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */\r
-        break;\r
-\r
-      case HAL_I2C_MSPINIT_CB_ID :\r
-        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */\r
-        break;\r
-\r
-      case HAL_I2C_MSPDEINIT_CB_ID :\r
-        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (HAL_I2C_STATE_RESET == hi2c->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_I2C_MSPINIT_CB_ID :\r
-        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */\r
-        break;\r
-\r
-      case HAL_I2C_MSPDEINIT_CB_ID :\r
-        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hi2c);\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register the Slave Address Match I2C Callback\r
-  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pCallback pointer to the Address Match Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-  /* Process locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if (HAL_I2C_STATE_READY == hi2c->State)\r
-  {\r
-    hi2c->AddrCallback = pCallback;\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hi2c);\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister the Slave Address Match I2C Callback\r
-  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if (HAL_I2C_STATE_READY == hi2c->State)\r
-  {\r
-    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hi2c);\r
-  return status;\r
-}\r
-\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
- *  @brief   Data transfers functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### IO operation functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to manage the I2C data\r
-    transfers.\r
-\r
-    (#) There are two modes of transfer:\r
-       (++) Blocking mode : The communication is performed in the polling mode.\r
-            The status of all data processing is returned by the same function\r
-            after finishing transfer.\r
-       (++) No-Blocking mode : The communication is performed using Interrupts\r
-            or DMA. These functions return the status of the transfer startup.\r
-            The end of the data processing will be indicated through the\r
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when\r
-            using DMA mode.\r
-\r
-    (#) Blocking mode functions are :\r
-        (++) HAL_I2C_Master_Transmit()\r
-        (++) HAL_I2C_Master_Receive()\r
-        (++) HAL_I2C_Slave_Transmit()\r
-        (++) HAL_I2C_Slave_Receive()\r
-        (++) HAL_I2C_Mem_Write()\r
-        (++) HAL_I2C_Mem_Read()\r
-        (++) HAL_I2C_IsDeviceReady()\r
-\r
-    (#) No-Blocking mode functions with Interrupt are :\r
-        (++) HAL_I2C_Master_Transmit_IT()\r
-        (++) HAL_I2C_Master_Receive_IT()\r
-        (++) HAL_I2C_Slave_Transmit_IT()\r
-        (++) HAL_I2C_Slave_Receive_IT()\r
-        (++) HAL_I2C_Mem_Write_IT()\r
-        (++) HAL_I2C_Mem_Read_IT()\r
-        (++) HAL_I2C_Master_Seq_Transmit_IT()\r
-        (++) HAL_I2C_Master_Seq_Receive_IT()\r
-        (++) HAL_I2C_Slave_Seq_Transmit_IT()\r
-        (++) HAL_I2C_Slave_Seq_Receive_IT()\r
-        (++) HAL_I2C_EnableListen_IT()\r
-        (++) HAL_I2C_DisableListen_IT()\r
-        (++) HAL_I2C_Master_Abort_IT()\r
-\r
-    (#) No-Blocking mode functions with DMA are :\r
-        (++) HAL_I2C_Master_Transmit_DMA()\r
-        (++) HAL_I2C_Master_Receive_DMA()\r
-        (++) HAL_I2C_Slave_Transmit_DMA()\r
-        (++) HAL_I2C_Slave_Receive_DMA()\r
-        (++) HAL_I2C_Mem_Write_DMA()\r
-        (++) HAL_I2C_Mem_Read_DMA()\r
-        (++) HAL_I2C_Master_Seq_Transmit_DMA()\r
-        (++) HAL_I2C_Master_Seq_Receive_DMA()\r
-        (++) HAL_I2C_Slave_Seq_Transmit_DMA()\r
-        (++) HAL_I2C_Slave_Seq_Receive_DMA()\r
-\r
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
-        (++) HAL_I2C_MasterTxCpltCallback()\r
-        (++) HAL_I2C_MasterRxCpltCallback()\r
-        (++) HAL_I2C_SlaveTxCpltCallback()\r
-        (++) HAL_I2C_SlaveRxCpltCallback()\r
-        (++) HAL_I2C_MemTxCpltCallback()\r
-        (++) HAL_I2C_MemRxCpltCallback()\r
-        (++) HAL_I2C_AddrCallback()\r
-        (++) HAL_I2C_ListenCpltCallback()\r
-        (++) HAL_I2C_ErrorCallback()\r
-        (++) HAL_I2C_AbortCpltCallback()\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Transmits in master mode an amount of data in blocking mode.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr  = pData;\r
-    hi2c->XferCount = Size;\r
-    hi2c->XferISR   = NULL;\r
-\r
-    /* Send Slave Address */\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
-    }\r
-\r
-    while (hi2c->XferCount > 0U)\r
-    {\r
-      /* Wait until TXIS flag is set */\r
-      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Write data to TXDR */\r
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferCount--;\r
-      hi2c->XferSize--;\r
-\r
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
-      {\r
-        /* Wait until TCR flag is set */\r
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-        {\r
-          hi2c->XferSize = MAX_NBYTE_SIZE;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-        else\r
-        {\r
-          hi2c->XferSize = hi2c->XferCount;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-      }\r
-    }\r
-\r
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
-    /* Wait until STOPF flag is set */\r
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Clear STOP Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-    /* Clear Configuration Register 2 */\r
-    I2C_RESET_CR2(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Receives in master mode an amount of data in blocking mode.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr  = pData;\r
-    hi2c->XferCount = Size;\r
-    hi2c->XferISR   = NULL;\r
-\r
-    /* Send Slave Address */\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
-    }\r
-\r
-    while (hi2c->XferCount > 0U)\r
-    {\r
-      /* Wait until RXNE flag is set */\r
-      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Read data from RXDR */\r
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferSize--;\r
-      hi2c->XferCount--;\r
-\r
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
-      {\r
-        /* Wait until TCR flag is set */\r
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-        {\r
-          hi2c->XferSize = MAX_NBYTE_SIZE;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-        else\r
-        {\r
-          hi2c->XferSize = hi2c->XferCount;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-      }\r
-    }\r
-\r
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
-    /* Wait until STOPF flag is set */\r
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Clear STOP Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-    /* Clear Configuration Register 2 */\r
-    I2C_RESET_CR2(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Transmits in slave mode an amount of data in blocking mode.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr  = pData;\r
-    hi2c->XferCount = Size;\r
-    hi2c->XferISR   = NULL;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Wait until ADDR flag is set */\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Clear ADDR flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-\r
-    /* If 10bit addressing mode is selected */\r
-    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
-    {\r
-      /* Wait until ADDR flag is set */\r
-      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
-      {\r
-        /* Disable Address Acknowledge */\r
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Clear ADDR flag */\r
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-    }\r
-\r
-    /* Wait until DIR flag is set Transmitter mode */\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    while (hi2c->XferCount > 0U)\r
-    {\r
-      /* Wait until TXIS flag is set */\r
-      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-      {\r
-        /* Disable Address Acknowledge */\r
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Write data to TXDR */\r
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferCount--;\r
-    }\r
-\r
-    /* Wait until STOP flag is set */\r
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-\r
-      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
-      {\r
-        /* Normal use case for Transmitter mode */\r
-        /* A NACK is generated to confirm the end of transfer */\r
-        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-      }\r
-      else\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-\r
-    /* Clear STOP flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-    /* Wait until BUSY flag is reset */\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Disable Address Acknowledge */\r
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Receive in slave mode an amount of data in blocking mode\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr  = pData;\r
-    hi2c->XferCount = Size;\r
-    hi2c->XferISR   = NULL;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Wait until ADDR flag is set */\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Clear ADDR flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-\r
-    /* Wait until DIR flag is reset Receiver mode */\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    while (hi2c->XferCount > 0U)\r
-    {\r
-      /* Wait until RXNE flag is set */\r
-      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-      {\r
-        /* Disable Address Acknowledge */\r
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-\r
-        /* Store Last receive data if any */\r
-        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r
-        {\r
-          /* Read data from RXDR */\r
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-          /* Increment Buffer pointer */\r
-          hi2c->pBuffPtr++;\r
-\r
-          hi2c->XferCount--;\r
-        }\r
-\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Read data from RXDR */\r
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferCount--;\r
-    }\r
-\r
-    /* Wait until STOP flag is set */\r
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Clear STOP flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-    /* Wait until BUSY flag is reset */\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Disable Address Acknowledge */\r
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Disable Address Acknowledge */\r
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t xfermode;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_IT;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    /* Send Slave Address */\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-\r
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
-    /* possible to enable all of these */\r
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t xfermode;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_IT;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    /* Send Slave Address */\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-\r
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
-    /* possible to enable all of these */\r
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
-{\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-\r
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
-    /* possible to enable all of these */\r
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
-{\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-\r
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
-    /* possible to enable all of these */\r
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t xfermode;\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    if (hi2c->XferSize > 0U)\r
-    {\r
-      if (hi2c->hdmatx != NULL)\r
-      {\r
-        /* Set the I2C DMA transfer complete callback */\r
-        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
-\r
-        /* Set the DMA error callback */\r
-        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
-\r
-        /* Set the unused DMA callbacks to NULL */\r
-        hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
-        hi2c->hdmatx->XferAbortCallback = NULL;\r
-\r
-        /* Enable the DMA channel */\r
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      if (dmaxferstatus == HAL_OK)\r
-      {\r
-        /* Send Slave Address */\r
-        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
-\r
-        /* Update XferCount value */\r
-        hi2c->XferCount -= hi2c->XferSize;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                  to avoid the risk of I2C interrupt handle execution before current\r
-                  process unlock */\r
-        /* Enable ERR and NACK interrupts */\r
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
-\r
-        /* Enable DMA Request */\r
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Update Transfer ISR function pointer */\r
-      hi2c->XferISR = I2C_Master_ISR_IT;\r
-\r
-      /* Send Slave Address */\r
-      /* Set NBYTES to write and generate START condition */\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
-      /* possible to enable all of these */\r
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t xfermode;\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    if (hi2c->XferSize > 0U)\r
-    {\r
-      if (hi2c->hdmarx != NULL)\r
-      {\r
-        /* Set the I2C DMA transfer complete callback */\r
-        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
-\r
-        /* Set the DMA error callback */\r
-        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
-\r
-        /* Set the unused DMA callbacks to NULL */\r
-        hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
-        hi2c->hdmarx->XferAbortCallback = NULL;\r
-\r
-        /* Enable the DMA channel */\r
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      if (dmaxferstatus == HAL_OK)\r
-      {\r
-        /* Send Slave Address */\r
-        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
-\r
-        /* Update XferCount value */\r
-        hi2c->XferCount -= hi2c->XferSize;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                  to avoid the risk of I2C interrupt handle execution before current\r
-                  process unlock */\r
-        /* Enable ERR and NACK interrupts */\r
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
-\r
-        /* Enable DMA Request */\r
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Update Transfer ISR function pointer */\r
-      hi2c->XferISR = I2C_Master_ISR_IT;\r
-\r
-      /* Send Slave Address */\r
-      /* Set NBYTES to read and generate START condition */\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
-      /* possible to enable all of these */\r
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
-{\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
-\r
-    if (hi2c->hdmatx != NULL)\r
-    {\r
-      /* Set the I2C DMA transfer complete callback */\r
-      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
-\r
-      /* Set the unused DMA callbacks to NULL */\r
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
-      hi2c->hdmatx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the DMA channel */\r
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (dmaxferstatus == HAL_OK)\r
-    {\r
-      /* Enable Address Acknowledge */\r
-      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR, STOP, NACK, ADDR interrupts */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
-\r
-      /* Enable DMA Request */\r
-      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
-{\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
-\r
-    if (hi2c->hdmarx != NULL)\r
-    {\r
-      /* Set the I2C DMA transfer complete callback */\r
-      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
-\r
-      /* Set the unused DMA callbacks to NULL */\r
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
-      hi2c->hdmarx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the DMA channel */\r
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (dmaxferstatus == HAL_OK)\r
-    {\r
-      /* Enable Address Acknowledge */\r
-      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR, STOP, NACK, ADDR interrupts */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
-\r
-      /* Enable DMA Request */\r
-      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-/**\r
-  * @brief  Write an amount of data in blocking mode to a specific memory address\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MEM;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr  = pData;\r
-    hi2c->XferCount = Size;\r
-    hi2c->XferISR   = NULL;\r
-\r
-    /* Send Slave Address and Memory Address */\r
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
-    }\r
-\r
-    do\r
-    {\r
-      /* Wait until TXIS flag is set */\r
-      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Write data to TXDR */\r
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferCount--;\r
-      hi2c->XferSize--;\r
-\r
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
-      {\r
-        /* Wait until TCR flag is set */\r
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-        {\r
-          hi2c->XferSize = MAX_NBYTE_SIZE;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-        else\r
-        {\r
-          hi2c->XferSize = hi2c->XferCount;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-      }\r
-\r
-    }\r
-    while (hi2c->XferCount > 0U);\r
-\r
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
-    /* Wait until STOPF flag is reset */\r
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Clear STOP Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-    /* Clear Configuration Register 2 */\r
-    I2C_RESET_CR2(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Read an amount of data in blocking mode from a specific memory address\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MEM;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr  = pData;\r
-    hi2c->XferCount = Size;\r
-    hi2c->XferISR   = NULL;\r
-\r
-    /* Send Slave Address and Memory Address */\r
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Send Slave Address */\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
-    }\r
-\r
-    do\r
-    {\r
-      /* Wait until RXNE flag is set */\r
-      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Read data from RXDR */\r
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferSize--;\r
-      hi2c->XferCount--;\r
-\r
-      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
-      {\r
-        /* Wait until TCR flag is set */\r
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-        {\r
-          hi2c->XferSize = MAX_NBYTE_SIZE;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-        else\r
-        {\r
-          hi2c->XferSize = hi2c->XferCount;\r
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-      }\r
-    }\r
-    while (hi2c->XferCount > 0U);\r
-\r
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
-    /* Wait until STOPF flag is reset */\r
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Clear STOP Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-    /* Clear Configuration Register 2 */\r
-    I2C_RESET_CR2(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode  = HAL_I2C_MODE_NONE;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-/**\r
-  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t tickstart;\r
-  uint32_t xfermode;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_IT;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    /* Send Slave Address and Memory Address */\r
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
-    {\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-\r
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
-    /* possible to enable all of these */\r
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t tickstart;\r
-  uint32_t xfermode;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_IT;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    /* Send Slave Address and Memory Address */\r
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
-    {\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-\r
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
-    /* possible to enable all of these */\r
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-/**\r
-  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t tickstart;\r
-  uint32_t xfermode;\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    /* Send Slave Address and Memory Address */\r
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
-    {\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-      return HAL_ERROR;\r
-    }\r
-\r
-\r
-    if (hi2c->hdmatx != NULL)\r
-    {\r
-      /* Set the I2C DMA transfer complete callback */\r
-      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
-\r
-      /* Set the unused DMA callbacks to NULL */\r
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
-      hi2c->hdmatx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the DMA channel */\r
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_READY;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (dmaxferstatus == HAL_OK)\r
-    {\r
-      /* Send Slave Address */\r
-      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
-\r
-      /* Update XferCount value */\r
-      hi2c->XferCount -= hi2c->XferSize;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR and NACK interrupts */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
-\r
-      /* Enable DMA Request */\r
-      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_READY;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be read\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
-{\r
-  uint32_t tickstart;\r
-  uint32_t xfermode;\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Init tickstart for timeout management*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode        = HAL_I2C_MODE_MEM;\r
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
-\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = I2C_AUTOEND_MODE;\r
-    }\r
-\r
-    /* Send Slave Address and Memory Address */\r
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
-    {\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (hi2c->hdmarx != NULL)\r
-    {\r
-      /* Set the I2C DMA transfer complete callback */\r
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
-\r
-      /* Set the unused DMA callbacks to NULL */\r
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
-      hi2c->hdmarx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the DMA channel */\r
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_READY;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (dmaxferstatus == HAL_OK)\r
-    {\r
-      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
-\r
-      /* Update XferCount value */\r
-      hi2c->XferCount -= hi2c->XferSize;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR and NACK interrupts */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
-\r
-      /* Enable DMA Request */\r
-      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_READY;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Checks if target device is ready for communication.\r
-  * @note   This function is used with Memory devices\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  Trials Number of trials\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  __IO uint32_t I2C_Trials = 0UL;\r
-\r
-  FlagStatus tmp1;\r
-  FlagStatus tmp2;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
-    {\r
-      return HAL_BUSY;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_BUSY;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    do\r
-    {\r
-      /* Generate Start */\r
-      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);\r
-\r
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
-      /* Wait until STOPF flag is set or a NACK flag is set*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);\r
-      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-      while ((tmp1 == RESET) && (tmp2 == RESET))\r
-      {\r
-        if (Timeout != HAL_MAX_DELAY)\r
-        {\r
-          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
-          {\r
-            /* Update I2C state */\r
-            hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-            /* Update I2C error code */\r
-            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
-\r
-            /* Process Unlocked */\r
-            __HAL_UNLOCK(hi2c);\r
-\r
-            return HAL_ERROR;\r
-          }\r
-        }\r
-\r
-        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);\r
-        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\r
-      }\r
-\r
-      /* Check if the NACKF flag has not been set */\r
-      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)\r
-      {\r
-        /* Wait until STOPF flag is reset */\r
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        /* Clear STOP Flag */\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-        /* Device is ready */\r
-        hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_OK;\r
-      }\r
-      else\r
-      {\r
-        /* Wait until STOPF flag is reset */\r
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        /* Clear NACK Flag */\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-        /* Clear STOP Flag, auto generated with autoend*/\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-      }\r
-\r
-      /* Check if the maximum allowed number of trials has been reached */\r
-      if (I2C_Trials == Trials)\r
-      {\r
-        /* Generate Stop */\r
-        hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
-\r
-        /* Wait until STOPF flag is reset */\r
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        /* Clear STOP Flag */\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-      }\r
-\r
-      /* Increment Trials */\r
-      I2C_Trials++;\r
-    }\r
-    while (I2C_Trials < Trials);\r
-\r
-    /* Update I2C state */\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Update I2C error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  uint32_t xfermode;\r
-  uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Master_ISR_IT;\r
-\r
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = hi2c->XferOptions;\r
-    }\r
-\r
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
-    /* Mean Previous state is same as current state */\r
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
-    {\r
-      xferrequest = I2C_NO_STARTSTOP;\r
-    }\r
-    else\r
-    {\r
-      /* Convert OTHER_xxx XferOptions if any */\r
-      I2C_ConvertOtherXferOptions(hi2c);\r
-\r
-      /* Update xfermode accordingly if no reload is necessary */\r
-      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
-      {\r
-        xfermode = hi2c->XferOptions;\r
-      }\r
-    }\r
-\r
-    /* Send Slave Address and set NBYTES to write */\r
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  uint32_t xfermode;\r
-  uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
-\r
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = hi2c->XferOptions;\r
-    }\r
-\r
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
-    /* Mean Previous state is same as current state */\r
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
-    {\r
-      xferrequest = I2C_NO_STARTSTOP;\r
-    }\r
-    else\r
-    {\r
-      /* Convert OTHER_xxx XferOptions if any */\r
-      I2C_ConvertOtherXferOptions(hi2c);\r
-\r
-      /* Update xfermode accordingly if no reload is necessary */\r
-      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
-      {\r
-        xfermode = hi2c->XferOptions;\r
-      }\r
-    }\r
-\r
-    if (hi2c->XferSize > 0U)\r
-    {\r
-      if (hi2c->hdmatx != NULL)\r
-      {\r
-        /* Set the I2C DMA transfer complete callback */\r
-        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
-\r
-        /* Set the DMA error callback */\r
-        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
-\r
-        /* Set the unused DMA callbacks to NULL */\r
-        hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
-        hi2c->hdmatx->XferAbortCallback = NULL;\r
-\r
-        /* Enable the DMA channel */\r
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      if (dmaxferstatus == HAL_OK)\r
-      {\r
-        /* Send Slave Address and set NBYTES to write */\r
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
-\r
-        /* Update XferCount value */\r
-        hi2c->XferCount -= hi2c->XferSize;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                  to avoid the risk of I2C interrupt handle execution before current\r
-                  process unlock */\r
-        /* Enable ERR and NACK interrupts */\r
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
-\r
-        /* Enable DMA Request */\r
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Update Transfer ISR function pointer */\r
-      hi2c->XferISR = I2C_Master_ISR_IT;\r
-\r
-      /* Send Slave Address */\r
-      /* Set NBYTES to write and generate START condition */\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
-      /* possible to enable all of these */\r
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  uint32_t xfermode;\r
-  uint32_t xferrequest = I2C_GENERATE_START_READ;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Master_ISR_IT;\r
-\r
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = hi2c->XferOptions;\r
-    }\r
-\r
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
-    /* Mean Previous state is same as current state */\r
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
-    {\r
-      xferrequest = I2C_NO_STARTSTOP;\r
-    }\r
-    else\r
-    {\r
-      /* Convert OTHER_xxx XferOptions if any */\r
-      I2C_ConvertOtherXferOptions(hi2c);\r
-\r
-      /* Update xfermode accordingly if no reload is necessary */\r
-      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
-      {\r
-        xfermode = hi2c->XferOptions;\r
-      }\r
-    }\r
-\r
-    /* Send Slave Address and set NBYTES to read */\r
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  uint32_t xfermode;\r
-  uint32_t xferrequest = I2C_GENERATE_START_READ;\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Master_ISR_DMA;\r
-\r
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-      xfermode = I2C_RELOAD_MODE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-      xfermode = hi2c->XferOptions;\r
-    }\r
-\r
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
-    /* Mean Previous state is same as current state */\r
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
-    {\r
-      xferrequest = I2C_NO_STARTSTOP;\r
-    }\r
-    else\r
-    {\r
-      /* Convert OTHER_xxx XferOptions if any */\r
-      I2C_ConvertOtherXferOptions(hi2c);\r
-\r
-      /* Update xfermode accordingly if no reload is necessary */\r
-      if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
-      {\r
-        xfermode = hi2c->XferOptions;\r
-      }\r
-    }\r
-\r
-    if (hi2c->XferSize > 0U)\r
-    {\r
-      if (hi2c->hdmarx != NULL)\r
-      {\r
-        /* Set the I2C DMA transfer complete callback */\r
-        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
-\r
-        /* Set the DMA error callback */\r
-        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
-\r
-        /* Set the unused DMA callbacks to NULL */\r
-        hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
-        hi2c->hdmarx->XferAbortCallback = NULL;\r
-\r
-        /* Enable the DMA channel */\r
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      if (dmaxferstatus == HAL_OK)\r
-      {\r
-        /* Send Slave Address and set NBYTES to read */\r
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
-\r
-        /* Update XferCount value */\r
-        hi2c->XferCount -= hi2c->XferSize;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                  to avoid the risk of I2C interrupt handle execution before current\r
-                  process unlock */\r
-        /* Enable ERR and NACK interrupts */\r
-        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
-\r
-        /* Enable DMA Request */\r
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
-      }\r
-      else\r
-      {\r
-        /* Update I2C state */\r
-        hi2c->State     = HAL_I2C_STATE_READY;\r
-        hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-        /* Update I2C error code */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Update Transfer ISR function pointer */\r
-      hi2c->XferISR = I2C_Master_ISR_IT;\r
-\r
-      /* Send Slave Address */\r
-      /* Set NBYTES to read and generate START condition */\r
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Note : The I2C interrupts must be enabled after unlocking current process\r
-                to avoid the risk of I2C interrupt handle execution before current\r
-                process unlock */\r
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
-      /* possible to enable all of these */\r
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-    }\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
-    /* and then toggle the HAL slave RX state to TX state */\r
-    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
-    {\r
-      /* Disable associated Interrupts */\r
-      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-\r
-      /* Abort DMA Xfer if any */\r
-      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
-      {\r
-        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
-\r
-        if (hi2c->hdmarx != NULL)\r
-        {\r
-          /* Set the I2C DMA Abort callback :\r
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-          /* Abort DMA RX */\r
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
-          {\r
-            /* Call Directly XferAbortCallback function in case of error */\r
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
-          }\r
-        }\r
-      }\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\r
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
-\r
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r
-    {\r
-      /* Clear ADDR flag after prepare the transfer parameters */\r
-      /* This action will generate an acknowledge to the Master */\r
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-    }\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-    to avoid the risk of I2C interrupt handle execution before current\r
-    process unlock */\r
-    /* REnable ADDR interrupt */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r
-\r
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
-    /* and then toggle the HAL slave RX state to TX state */\r
-    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
-    {\r
-      /* Disable associated Interrupts */\r
-      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-\r
-      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
-      {\r
-        /* Abort DMA Xfer if any */\r
-        if (hi2c->hdmarx != NULL)\r
-        {\r
-          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
-\r
-          /* Set the I2C DMA Abort callback :\r
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-          /* Abort DMA RX */\r
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
-          {\r
-            /* Call Directly XferAbortCallback function in case of error */\r
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
-          }\r
-        }\r
-      }\r
-    }\r
-    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
-    {\r
-      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
-      {\r
-        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
-\r
-        /* Abort DMA Xfer if any */\r
-        if (hi2c->hdmatx != NULL)\r
-        {\r
-          /* Set the I2C DMA Abort callback :\r
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-          /* Abort DMA TX */\r
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
-          {\r
-            /* Call Directly XferAbortCallback function in case of error */\r
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
-          }\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Nothing to do */\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\r
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
-\r
-    if (hi2c->hdmatx != NULL)\r
-    {\r
-      /* Set the I2C DMA transfer complete callback */\r
-      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
-\r
-      /* Set the unused DMA callbacks to NULL */\r
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
-      hi2c->hdmatx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the DMA channel */\r
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (dmaxferstatus == HAL_OK)\r
-    {\r
-      /* Update XferCount value */\r
-      hi2c->XferCount -= hi2c->XferSize;\r
-\r
-      /* Reset XferSize */\r
-      hi2c->XferSize = 0;\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r
-    {\r
-      /* Clear ADDR flag after prepare the transfer parameters */\r
-      /* This action will generate an acknowledge to the Master */\r
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-    }\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-    to avoid the risk of I2C interrupt handle execution before current\r
-    process unlock */\r
-    /* Enable ERR, STOP, NACK, ADDR interrupts */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
-\r
-    /* Enable DMA Request */\r
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
-    /* and then toggle the HAL slave TX state to RX state */\r
-    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
-    {\r
-      /* Disable associated Interrupts */\r
-      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
-      {\r
-        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
-\r
-        /* Abort DMA Xfer if any */\r
-        if (hi2c->hdmatx != NULL)\r
-        {\r
-          /* Set the I2C DMA Abort callback :\r
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-          /* Abort DMA TX */\r
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
-          {\r
-            /* Call Directly XferAbortCallback function in case of error */\r
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
-          }\r
-        }\r
-      }\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\r
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Slave_ISR_IT;\r
-\r
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r
-    {\r
-      /* Clear ADDR flag after prepare the transfer parameters */\r
-      /* This action will generate an acknowledge to the Master */\r
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-    }\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-    to avoid the risk of I2C interrupt handle execution before current\r
-    process unlock */\r
-    /* REnable ADDR interrupt */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA\r
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  pData Pointer to data buffer\r
-  * @param  Size Amount of data to be sent\r
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
-{\r
-  HAL_StatusTypeDef dmaxferstatus;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
-\r
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r
-\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
-    /* and then toggle the HAL slave TX state to RX state */\r
-    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
-    {\r
-      /* Disable associated Interrupts */\r
-      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
-      {\r
-        /* Abort DMA Xfer if any */\r
-        if (hi2c->hdmatx != NULL)\r
-        {\r
-          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
-\r
-          /* Set the I2C DMA Abort callback :\r
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-          /* Abort DMA TX */\r
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
-          {\r
-            /* Call Directly XferAbortCallback function in case of error */\r
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
-          }\r
-        }\r
-      }\r
-    }\r
-    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
-    {\r
-      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
-      {\r
-        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
-\r
-        /* Abort DMA Xfer if any */\r
-        if (hi2c->hdmarx != NULL)\r
-        {\r
-          /* Set the I2C DMA Abort callback :\r
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-          /* Abort DMA RX */\r
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
-          {\r
-            /* Call Directly XferAbortCallback function in case of error */\r
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
-          }\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Nothing to do */\r
-    }\r
-\r
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\r
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-\r
-    /* Enable Address Acknowledge */\r
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
-\r
-    /* Prepare transfer parameters */\r
-    hi2c->pBuffPtr    = pData;\r
-    hi2c->XferCount   = Size;\r
-    hi2c->XferSize    = hi2c->XferCount;\r
-    hi2c->XferOptions = XferOptions;\r
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r
-\r
-    if (hi2c->hdmarx != NULL)\r
-    {\r
-      /* Set the I2C DMA transfer complete callback */\r
-      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
-\r
-      /* Set the unused DMA callbacks to NULL */\r
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
-      hi2c->hdmarx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the DMA channel */\r
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (dmaxferstatus == HAL_OK)\r
-    {\r
-      /* Update XferCount value */\r
-      hi2c->XferCount -= hi2c->XferSize;\r
-\r
-      /* Reset XferSize */\r
-      hi2c->XferSize = 0;\r
-    }\r
-    else\r
-    {\r
-      /* Update I2C state */\r
-      hi2c->State     = HAL_I2C_STATE_LISTEN;\r
-      hi2c->Mode      = HAL_I2C_MODE_NONE;\r
-\r
-      /* Update I2C error code */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r
-    {\r
-      /* Clear ADDR flag after prepare the transfer parameters */\r
-      /* This action will generate an acknowledge to the Master */\r
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-    }\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-    to avoid the risk of I2C interrupt handle execution before current\r
-    process unlock */\r
-    /* REnable ADDR interrupt */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
-\r
-    /* Enable DMA Request */\r
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Enable the Address listen mode with Interrupt.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)\r
-{\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    hi2c->State = HAL_I2C_STATE_LISTEN;\r
-    hi2c->XferISR = I2C_Slave_ISR_IT;\r
-\r
-    /* Enable the Address Match interrupt */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Disable the Address listen mode with Interrupt.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */\r
-  uint32_t tmp;\r
-\r
-  /* Disable Address listen mode only if a transfer is not ongoing */\r
-  if (hi2c->State == HAL_I2C_STATE_LISTEN)\r
-  {\r
-    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;\r
-    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode = HAL_I2C_MODE_NONE;\r
-    hi2c->XferISR = NULL;\r
-\r
-    /* Disable the Address Match interrupt */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)\r
-{\r
-  if (hi2c->Mode == HAL_I2C_MODE_MASTER)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    /* Disable Interrupts */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-    /* Set State at HAL_I2C_STATE_ABORT */\r
-    hi2c->State = HAL_I2C_STATE_ABORT;\r
-\r
-    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */\r
-    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */\r
-    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Note : The I2C interrupts must be enabled after unlocking current process\r
-              to avoid the risk of I2C interrupt handle execution before current\r
-              process unlock */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    /* Wrong usage of abort function */\r
-    /* This function should be used only in case of abort monitored by master device */\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
- * @{\r
- */\r
-\r
-/**\r
-  * @brief  This function handles I2C event interrupt request.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Get current IT Flags and IT sources value */\r
-  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r
-  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
-\r
-  /* I2C events treatment -------------------------------------*/\r
-  if (hi2c->XferISR != NULL)\r
-  {\r
-    hi2c->XferISR(hi2c, itflags, itsources);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  This function handles I2C error interrupt request.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\r
-{\r
-  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r
-  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
-  uint32_t tmperror;\r
-\r
-  /* I2C Bus error interrupt occurred ------------------------------------*/\r
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
-  {\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;\r
-\r
-    /* Clear BERR flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\r
-  }\r
-\r
-  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/\r
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
-  {\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;\r
-\r
-    /* Clear OVR flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\r
-  }\r
-\r
-  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/\r
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
-  {\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;\r
-\r
-    /* Clear ARLO flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\r
-  }\r
-\r
-  /* Store current volatile hi2c->ErrorCode, misra rule */\r
-  tmperror = hi2c->ErrorCode;\r
-\r
-  /* Call the Error Callback in case of Error detected */\r
-  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)\r
-  {\r
-    I2C_ITError(hi2c, tmperror);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Master Tx Transfer completed callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Master Rx Transfer completed callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/** @brief  Slave Tx Transfer completed callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Slave Rx Transfer completed callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Slave Address Match callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION\r
-  * @param  AddrMatchCode Address Match Code\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-  UNUSED(TransferDirection);\r
-  UNUSED(AddrMatchCode);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_AddrCallback() could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Listen Complete callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_ListenCpltCallback() could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Memory Tx Transfer completed callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_MemTxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Memory Rx Transfer completed callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_MemRxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  I2C error callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_ErrorCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  I2C abort callback.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval None\r
-  */\r
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hi2c);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_I2C_AbortCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
- *  @brief   Peripheral State, Mode and Error functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-            ##### Peripheral State, Mode and Error functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection permit to get in run-time the status of the peripheral\r
-    and the data flow.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Return the I2C handle state.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @retval HAL state\r
-  */\r
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Return I2C handle state */\r
-  return hi2c->State;\r
-}\r
-\r
-/**\r
-  * @brief  Returns the I2C Master, Slave, Memory or no mode.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *         the configuration information for I2C module\r
-  * @retval HAL mode\r
-  */\r
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)\r
-{\r
-  return hi2c->Mode;\r
-}\r
-\r
-/**\r
-* @brief  Return the I2C error code.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *              the configuration information for the specified I2C.\r
-* @retval I2C Error Code\r
-*/\r
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\r
-{\r
-  return hi2c->ErrorCode;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup I2C_Private_Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @param  ITSources Interrupt sources enabled.\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
-{\r
-  uint16_t devaddress;\r
-  uint32_t tmpITFlags = ITFlags;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
-  {\r
-    /* Clear NACK Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-    /* Set corresponding Error Code */\r
-    /* No need to generate STOP, it is automatically done */\r
-    /* Error callback will be send during stop flag treatment */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-\r
-    /* Flush TX register */\r
-    I2C_Flush_TXDR(hi2c);\r
-  }\r
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))\r
-  {\r
-    /* Remove RXNE flag on temporary variable as read done */\r
-    tmpITFlags &= ~I2C_FLAG_RXNE;\r
-\r
-    /* Read data from RXDR */\r
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-    /* Increment Buffer pointer */\r
-    hi2c->pBuffPtr++;\r
-\r
-    hi2c->XferSize--;\r
-    hi2c->XferCount--;\r
-  }\r
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))\r
-  {\r
-    /* Write data to TXDR */\r
-    hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
-\r
-    /* Increment Buffer pointer */\r
-    hi2c->pBuffPtr++;\r
-\r
-    hi2c->XferSize--;\r
-    hi2c->XferCount--;\r
-  }\r
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
-  {\r
-    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
-    {\r
-      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);\r
-\r
-      if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-      {\r
-        hi2c->XferSize = MAX_NBYTE_SIZE;\r
-        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
-      }\r
-      else\r
-      {\r
-        hi2c->XferSize = hi2c->XferCount;\r
-        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
-        {\r
-          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);\r
-        }\r
-        else\r
-        {\r
-          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Call TxCpltCallback() if no stop mode is set */\r
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
-      {\r
-        /* Call I2C Master Sequential complete process */\r
-        I2C_ITMasterSeqCplt(hi2c);\r
-      }\r
-      else\r
-      {\r
-        /* Wrong size Status regarding TCR flag event */\r
-        /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
-      }\r
-    }\r
-  }\r
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
-  {\r
-    if (hi2c->XferCount == 0U)\r
-    {\r
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
-      {\r
-        /* Generate a stop condition in case of no transfer option */\r
-        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)\r
-        {\r
-          /* Generate Stop */\r
-          hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
-        }\r
-        else\r
-        {\r
-          /* Call I2C Master Sequential complete process */\r
-          I2C_ITMasterSeqCplt(hi2c);\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Wrong size Status regarding TC flag event */\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-\r
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
-  {\r
-    /* Call I2C Master complete process */\r
-    I2C_ITMasterCplt(hi2c, tmpITFlags);\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hi2c);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @param  ITSources Interrupt sources enabled.\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
-{\r
-  uint32_t tmpoptions = hi2c->XferOptions;\r
-  uint32_t tmpITFlags = ITFlags;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
-  {\r
-    /* Check that I2C transfer finished */\r
-    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
-    /* Mean XferCount == 0*/\r
-    /* So clear Flag NACKF only */\r
-    if (hi2c->XferCount == 0U)\r
-    {\r
-      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */\r
-      {\r
-        /* Call I2C Listen complete process */\r
-        I2C_ITListenCplt(hi2c, tmpITFlags);\r
-      }\r
-      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))\r
-      {\r
-        /* Clear NACK Flag */\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-        /* Flush TX register */\r
-        I2C_Flush_TXDR(hi2c);\r
-\r
-        /* Last Byte is Transmitted */\r
-        /* Call I2C Slave Sequential complete process */\r
-        I2C_ITSlaveSeqCplt(hi2c);\r
-      }\r
-      else\r
-      {\r
-        /* Clear NACK Flag */\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
-      /* Clear NACK Flag */\r
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-      /* Set ErrorCode corresponding to a Non-Acknowledge */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-\r
-      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))\r
-      {\r
-        /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-        I2C_ITError(hi2c, hi2c->ErrorCode);\r
-      }\r
-    }\r
-  }\r
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))\r
-  {\r
-    if (hi2c->XferCount > 0U)\r
-    {\r
-      /* Remove RXNE flag on temporary variable as read done */\r
-      tmpITFlags &= ~I2C_FLAG_RXNE;\r
-\r
-      /* Read data from RXDR */\r
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferSize--;\r
-      hi2c->XferCount--;\r
-    }\r
-\r
-    if ((hi2c->XferCount == 0U) && \\r
-        (tmpoptions != I2C_NO_OPTION_FRAME))\r
-    {\r
-      /* Call I2C Slave Sequential complete process */\r
-      I2C_ITSlaveSeqCplt(hi2c);\r
-    }\r
-  }\r
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))\r
-  {\r
-    I2C_ITAddrCplt(hi2c, tmpITFlags);\r
-  }\r
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))\r
-  {\r
-    /* Write data to TXDR only if XferCount not reach "0" */\r
-    /* A TXIS flag can be set, during STOP treatment      */\r
-    /* Check if all Datas have already been sent */\r
-    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */\r
-    if (hi2c->XferCount > 0U)\r
-    {\r
-      /* Write data to TXDR */\r
-      hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
-\r
-      /* Increment Buffer pointer */\r
-      hi2c->pBuffPtr++;\r
-\r
-      hi2c->XferCount--;\r
-      hi2c->XferSize--;\r
-    }\r
-    else\r
-    {\r
-      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))\r
-      {\r
-        /* Last Byte is Transmitted */\r
-        /* Call I2C Slave Sequential complete process */\r
-        I2C_ITSlaveSeqCplt(hi2c);\r
-      }\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-\r
-  /* Check if STOPF is set */\r
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
-  {\r
-    /* Call I2C Slave complete process */\r
-    I2C_ITSlaveCplt(hi2c, tmpITFlags);\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hi2c);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @param  ITSources Interrupt sources enabled.\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
-{\r
-  uint16_t devaddress;\r
-  uint32_t xfermode;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
-  {\r
-    /* Clear NACK Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-    /* Set corresponding Error Code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-\r
-    /* No need to generate STOP, it is automatically done */\r
-    /* But enable STOP interrupt, to treat it */\r
-    /* Error callback will be send during stop flag treatment */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
-\r
-    /* Flush TX register */\r
-    I2C_Flush_TXDR(hi2c);\r
-  }\r
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
-  {\r
-    /* Disable TC interrupt */\r
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);\r
-\r
-    if (hi2c->XferCount != 0U)\r
-    {\r
-      /* Recover Slave address */\r
-      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);\r
-\r
-      /* Prepare the new XferSize to transfer */\r
-      if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-      {\r
-        hi2c->XferSize = MAX_NBYTE_SIZE;\r
-        xfermode = I2C_RELOAD_MODE;\r
-      }\r
-      else\r
-      {\r
-        hi2c->XferSize = hi2c->XferCount;\r
-        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
-        {\r
-          xfermode = hi2c->XferOptions;\r
-        }\r
-        else\r
-        {\r
-          xfermode = I2C_AUTOEND_MODE;\r
-        }\r
-      }\r
-\r
-      /* Set the new XferSize in Nbytes register */\r
-      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
-\r
-      /* Update XferCount value */\r
-      hi2c->XferCount -= hi2c->XferSize;\r
-\r
-      /* Enable DMA Request */\r
-      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
-      {\r
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
-      }\r
-      else\r
-      {\r
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Call TxCpltCallback() if no stop mode is set */\r
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
-      {\r
-        /* Call I2C Master Sequential complete process */\r
-        I2C_ITMasterSeqCplt(hi2c);\r
-      }\r
-      else\r
-      {\r
-        /* Wrong size Status regarding TCR flag event */\r
-        /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
-      }\r
-    }\r
-  }\r
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
-  {\r
-    if (hi2c->XferCount == 0U)\r
-    {\r
-      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
-      {\r
-        /* Generate a stop condition in case of no transfer option */\r
-        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)\r
-        {\r
-          /* Generate Stop */\r
-          hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
-        }\r
-        else\r
-        {\r
-          /* Call I2C Master Sequential complete process */\r
-          I2C_ITMasterSeqCplt(hi2c);\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Wrong size Status regarding TC flag event */\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
-    }\r
-  }\r
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
-  {\r
-    /* Call I2C Master complete process */\r
-    I2C_ITMasterCplt(hi2c, ITFlags);\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hi2c);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @param  ITSources Interrupt sources enabled.\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
-{\r
-  uint32_t tmpoptions = hi2c->XferOptions;\r
-  uint32_t treatdmanack = 0U;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hi2c);\r
-\r
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
-  {\r
-    /* Check that I2C transfer finished */\r
-    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
-    /* Mean XferCount == 0 */\r
-    /* So clear Flag NACKF only */\r
-    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||\r
-        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))\r
-    {\r
-      /* Split check of hdmarx, for MISRA compliance */\r
-      if (hi2c->hdmarx != NULL)\r
-      {\r
-        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)\r
-        {\r
-          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)\r
-          {\r
-            treatdmanack = 1U;\r
-          }\r
-        }\r
-      }\r
-\r
-      /* Split check of hdmatx, for MISRA compliance  */\r
-      if (hi2c->hdmatx != NULL)\r
-      {\r
-        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)\r
-        {\r
-          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)\r
-          {\r
-            treatdmanack = 1U;\r
-          }\r
-        }\r
-      }\r
-\r
-      if (treatdmanack == 1U)\r
-      {\r
-        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */\r
-        {\r
-          /* Call I2C Listen complete process */\r
-          I2C_ITListenCplt(hi2c, ITFlags);\r
-        }\r
-        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))\r
-        {\r
-          /* Clear NACK Flag */\r
-          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-          /* Flush TX register */\r
-          I2C_Flush_TXDR(hi2c);\r
-\r
-          /* Last Byte is Transmitted */\r
-          /* Call I2C Slave Sequential complete process */\r
-          I2C_ITSlaveSeqCplt(hi2c);\r
-        }\r
-        else\r
-        {\r
-          /* Clear NACK Flag */\r
-          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
-        /* Clear NACK Flag */\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-        /* Set ErrorCode corresponding to a Non-Acknowledge */\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-\r
-        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))\r
-        {\r
-          /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-          I2C_ITError(hi2c, hi2c->ErrorCode);\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Only Clear NACK Flag, no DMA treatment is pending */\r
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-    }\r
-  }\r
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))\r
-  {\r
-    I2C_ITAddrCplt(hi2c, ITFlags);\r
-  }\r
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
-  {\r
-    /* Call I2C Slave complete process */\r
-    I2C_ITSlaveCplt(hi2c, ITFlags);\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hi2c);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Master sends target device address followed by internal memory address for write request.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart Tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
-\r
-  /* Wait until TXIS flag is set */\r
-  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* If Memory address size is 8Bit */\r
-  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
-  {\r
-    /* Send Memory Address */\r
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
-  }\r
-  /* If Memory address size is 16Bit */\r
-  else\r
-  {\r
-    /* Send MSB of Memory Address */\r
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
-\r
-    /* Wait until TXIS flag is set */\r
-    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Send LSB of Memory Address */\r
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
-  }\r
-\r
-  /* Wait until TCR flag is set */\r
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Master sends target device address followed by internal memory address for read request.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  DevAddress Target device address: The device 7 bits address value\r
-  *         in datasheet must be shifted to the left before calling the interface\r
-  * @param  MemAddress Internal memory address\r
-  * @param  MemAddSize Size of internal memory address\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart Tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);\r
-\r
-  /* Wait until TXIS flag is set */\r
-  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* If Memory address size is 8Bit */\r
-  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
-  {\r
-    /* Send Memory Address */\r
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
-  }\r
-  /* If Memory address size is 16Bit */\r
-  else\r
-  {\r
-    /* Send MSB of Memory Address */\r
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
-\r
-    /* Wait until TXIS flag is set */\r
-    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Send LSB of Memory Address */\r
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
-  }\r
-\r
-  /* Wait until TC flag is set */\r
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  I2C Address complete process callback.\r
-  * @param  hi2c I2C handle.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
-{\r
-  uint8_t transferdirection;\r
-  uint16_t slaveaddrcode;\r
-  uint16_t ownadd1code;\r
-  uint16_t ownadd2code;\r
-\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(ITFlags);\r
-\r
-  /* In case of Listen state, need to inform upper layer of address match code event */\r
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
-  {\r
-    transferdirection = I2C_GET_DIR(hi2c);\r
-    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);\r
-    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);\r
-    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);\r
-\r
-    /* If 10bits addressing mode is selected */\r
-    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
-    {\r
-      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))\r
-      {\r
-        slaveaddrcode = ownadd1code;\r
-        hi2c->AddrEventCount++;\r
-        if (hi2c->AddrEventCount == 2U)\r
-        {\r
-          /* Reset Address Event counter */\r
-          hi2c->AddrEventCount = 0U;\r
-\r
-          /* Clear ADDR flag */\r
-          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-\r
-          /* Process Unlocked */\r
-          __HAL_UNLOCK(hi2c);\r
-\r
-          /* Call Slave Addr callback */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
-#else\r
-          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-        }\r
-      }\r
-      else\r
-      {\r
-        slaveaddrcode = ownadd2code;\r
-\r
-        /* Disable ADDR Interrupts */\r
-        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        /* Call Slave Addr callback */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
-#else\r
-        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-      }\r
-    }\r
-    /* else 7 bits addressing mode is selected */\r
-    else\r
-    {\r
-      /* Disable ADDR Interrupts */\r
-      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Call Slave Addr callback */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
-#else\r
-      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  /* Else clear address flag only */\r
-  else\r
-  {\r
-    /* Clear ADDR flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  I2C Master sequential complete process.\r
-  * @param  hi2c I2C handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Reset I2C handle mode */\r
-  hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-  /* No Generate Stop, to permit restart mode */\r
-  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */\r
-  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
-  {\r
-    hi2c->State         = HAL_I2C_STATE_READY;\r
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\r
-    hi2c->XferISR       = NULL;\r
-\r
-    /* Disable Interrupts */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->MasterTxCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_MasterTxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
-  else\r
-  {\r
-    hi2c->State         = HAL_I2C_STATE_READY;\r
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\r
-    hi2c->XferISR       = NULL;\r
-\r
-    /* Disable Interrupts */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->MasterRxCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_MasterRxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  I2C Slave sequential complete process.\r
-  * @param  hi2c I2C handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Reset I2C handle mode */\r
-  hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
-  {\r
-    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */\r
-    hi2c->State         = HAL_I2C_STATE_LISTEN;\r
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\r
-\r
-    /* Disable Interrupts */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->SlaveTxCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_SlaveTxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
-  {\r
-    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */\r
-    hi2c->State         = HAL_I2C_STATE_LISTEN;\r
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\r
-\r
-    /* Disable Interrupts */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->SlaveRxCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_SlaveRxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  I2C Master complete process.\r
-  * @param  hi2c I2C handle.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
-{\r
-  uint32_t tmperror;\r
-\r
-  /* Clear STOP Flag */\r
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-  /* Clear Configuration Register 2 */\r
-  I2C_RESET_CR2(hi2c);\r
-\r
-  /* Reset handle parameters */\r
-  hi2c->PreviousState = I2C_STATE_NONE;\r
-  hi2c->XferISR       = NULL;\r
-  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r
-\r
-  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)\r
-  {\r
-    /* Clear NACK Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-    /* Set acknowledge error code */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-  }\r
-\r
-  /* Flush TX register */\r
-  I2C_Flush_TXDR(hi2c);\r
-\r
-  /* Disable Interrupts */\r
-  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r
-\r
-  /* Store current volatile hi2c->ErrorCode, misra rule */\r
-  tmperror = hi2c->ErrorCode;\r
-\r
-  /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))\r
-  {\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-    I2C_ITError(hi2c, hi2c->ErrorCode);\r
-  }\r
-  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */\r
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
-  {\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
-    {\r
-      hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-      hi2c->MemTxCpltCallback(hi2c);\r
-#else\r
-      HAL_I2C_MemTxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-    }\r
-    else\r
-    {\r
-      hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-      hi2c->MasterTxCpltCallback(hi2c);\r
-#else\r
-      HAL_I2C_MasterTxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
-  {\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
-    {\r
-      hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-      hi2c->MemRxCpltCallback(hi2c);\r
-#else\r
-      HAL_I2C_MemRxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-    }\r
-    else\r
-    {\r
-      hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-      hi2c->MasterRxCpltCallback(hi2c);\r
-#else\r
-      HAL_I2C_MasterRxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  I2C Slave complete process.\r
-  * @param  hi2c I2C handle.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
-{\r
-  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);\r
-  uint32_t tmpITFlags = ITFlags;\r
-\r
-  /* Clear STOP Flag */\r
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-  /* Disable all interrupts */\r
-  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r
-\r
-  /* Disable Address Acknowledge */\r
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-\r
-  /* Clear Configuration Register 2 */\r
-  I2C_RESET_CR2(hi2c);\r
-\r
-  /* Flush TX register */\r
-  I2C_Flush_TXDR(hi2c);\r
-\r
-  /* If a DMA is ongoing, Update handle size context */\r
-  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)\r
-  {\r
-    if (hi2c->hdmatx != NULL)\r
-    {\r
-      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);\r
-    }\r
-  }\r
-  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)\r
-  {\r
-    if (hi2c->hdmarx != NULL)\r
-    {\r
-      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Do nothing */\r
-  }\r
-\r
-  /* Store Last receive data if any */\r
-  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)\r
-  {\r
-    /* Remove RXNE flag on temporary variable as read done */\r
-    tmpITFlags &= ~I2C_FLAG_RXNE;\r
-\r
-    /* Read data from RXDR */\r
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-    /* Increment Buffer pointer */\r
-    hi2c->pBuffPtr++;\r
-\r
-    if ((hi2c->XferSize > 0U))\r
-    {\r
-      hi2c->XferSize--;\r
-      hi2c->XferCount--;\r
-    }\r
-  }\r
-\r
-  /* All data are not transferred, so set error code accordingly */\r
-  if (hi2c->XferCount != 0U)\r
-  {\r
-    /* Set ErrorCode corresponding to a Non-Acknowledge */\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-  }\r
-\r
-  hi2c->PreviousState = I2C_STATE_NONE;\r
-  hi2c->Mode = HAL_I2C_MODE_NONE;\r
-  hi2c->XferISR = NULL;\r
-\r
-  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
-  {\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-    I2C_ITError(hi2c, hi2c->ErrorCode);\r
-\r
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
-    if (hi2c->State == HAL_I2C_STATE_LISTEN)\r
-    {\r
-      /* Call I2C Listen complete process */\r
-      I2C_ITListenCplt(hi2c, tmpITFlags);\r
-    }\r
-  }\r
-  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
-  {\r
-    /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */\r
-    I2C_ITSlaveSeqCplt(hi2c);\r
-\r
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->ListenCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_ListenCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-  /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
-  {\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->SlaveRxCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_SlaveRxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->SlaveTxCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_SlaveTxCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  I2C Listen complete process.\r
-  * @param  hi2c I2C handle.\r
-  * @param  ITFlags Interrupt flags to handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
-{\r
-  /* Reset handle parameters */\r
-  hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
-  hi2c->PreviousState = I2C_STATE_NONE;\r
-  hi2c->State = HAL_I2C_STATE_READY;\r
-  hi2c->Mode = HAL_I2C_MODE_NONE;\r
-  hi2c->XferISR = NULL;\r
-\r
-  /* Store Last receive data if any */\r
-  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)\r
-  {\r
-    /* Read data from RXDR */\r
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
-\r
-    /* Increment Buffer pointer */\r
-    hi2c->pBuffPtr++;\r
-\r
-    if ((hi2c->XferSize > 0U))\r
-    {\r
-      hi2c->XferSize--;\r
-      hi2c->XferCount--;\r
-\r
-      /* Set ErrorCode corresponding to a Non-Acknowledge */\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-    }\r
-  }\r
-\r
-  /* Disable all Interrupts*/\r
-  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
-\r
-  /* Clear NACK Flag */\r
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hi2c);\r
-\r
-  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-  hi2c->ListenCpltCallback(hi2c);\r
-#else\r
-  HAL_I2C_ListenCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  I2C interrupts error process.\r
-  * @param  hi2c I2C handle.\r
-  * @param  ErrorCode Error code to handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)\r
-{\r
-  HAL_I2C_StateTypeDef tmpstate = hi2c->State;\r
-\r
-  /* Reset handle parameters */\r
-  hi2c->Mode          = HAL_I2C_MODE_NONE;\r
-  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r
-  hi2c->XferCount     = 0U;\r
-\r
-  /* Set new error code */\r
-  hi2c->ErrorCode |= ErrorCode;\r
-\r
-  /* Disable Interrupts */\r
-  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||\r
-      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||\r
-      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))\r
-  {\r
-    /* Disable all interrupts, except interrupts related to LISTEN state */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
-\r
-    /* keep HAL_I2C_STATE_LISTEN if set */\r
-    hi2c->State         = HAL_I2C_STATE_LISTEN;\r
-    hi2c->PreviousState = I2C_STATE_NONE;\r
-    hi2c->XferISR       = I2C_Slave_ISR_IT;\r
-  }\r
-  else\r
-  {\r
-    /* Disable all interrupts */\r
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
-\r
-    /* If state is an abort treatment on goind, don't change state */\r
-    /* This change will be do later */\r
-    if (hi2c->State != HAL_I2C_STATE_ABORT)\r
-    {\r
-      /* Set HAL_I2C_STATE_READY */\r
-      hi2c->State         = HAL_I2C_STATE_READY;\r
-    }\r
-    hi2c->PreviousState = I2C_STATE_NONE;\r
-    hi2c->XferISR       = NULL;\r
-  }\r
-\r
-  /* Abort DMA TX transfer if any */\r
-  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
-  {\r
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
-\r
-    if (hi2c->hdmatx != NULL)\r
-    {\r
-      /* Set the I2C DMA Abort callback :\r
-       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Abort DMA TX */\r
-      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
-      {\r
-        /* Call Directly XferAbortCallback function in case of error */\r
-        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
-      }\r
-    }\r
-  }\r
-  /* Abort DMA RX transfer if any */\r
-  else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
-  {\r
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
-\r
-    if (hi2c->hdmarx != NULL)\r
-    {\r
-      /* Set the I2C DMA Abort callback :\r
-        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
-      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      /* Abort DMA RX */\r
-      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
-      {\r
-        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */\r
-        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
-      }\r
-    }\r
-  }\r
-  else if (hi2c->State == HAL_I2C_STATE_ABORT)\r
-  {\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->AbortCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_AbortCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->ErrorCallback(hi2c);\r
-#else\r
-    HAL_I2C_ErrorCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  I2C Tx data register flush process.\r
-  * @param  hi2c I2C handle.\r
-  * @retval None\r
-  */\r
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* If a pending TXIS flag is set */\r
-  /* Write a dummy data in TXDR to clear it */\r
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)\r
-  {\r
-    hi2c->Instance->TXDR = 0x00U;\r
-  }\r
-\r
-  /* Flush TX register if not empty */\r
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)\r
-  {\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  DMA I2C master transmit process complete callback.\r
-  * @param  hdma DMA handle\r
-  * @retval None\r
-  */\r
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Disable DMA Request */\r
-  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
-\r
-  /* If last transfer, enable STOP interrupt */\r
-  if (hi2c->XferCount == 0U)\r
-  {\r
-    /* Enable STOP interrupt */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
-  }\r
-  /* else prepare a new DMA transfer and enable TCReload interrupt */\r
-  else\r
-  {\r
-    /* Update Buffer pointer */\r
-    hi2c->pBuffPtr += hi2c->XferSize;\r
-\r
-    /* Set the XferSize to transfer */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-    }\r
-\r
-    /* Enable the DMA channel */\r
-    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)\r
-    {\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
-    }\r
-    else\r
-    {\r
-      /* Enable TC interrupts */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  DMA I2C slave transmit process complete callback.\r
-  * @param  hdma DMA handle\r
-  * @retval None\r
-  */\r
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-  uint32_t tmpoptions = hi2c->XferOptions;\r
-\r
-  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))\r
-  {\r
-    /* Disable DMA Request */\r
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
-\r
-    /* Last Byte is Transmitted */\r
-    /* Call I2C Slave Sequential complete process */\r
-    I2C_ITSlaveSeqCplt(hi2c);\r
-  }\r
-  else\r
-  {\r
-    /* No specific action, Master fully manage the generation of STOP condition */\r
-    /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
-    /* So STOP condition should be manage through Interrupt treatment */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief DMA I2C master receive process complete callback.\r
-  * @param  hdma DMA handle\r
-  * @retval None\r
-  */\r
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Disable DMA Request */\r
-  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
-\r
-  /* If last transfer, enable STOP interrupt */\r
-  if (hi2c->XferCount == 0U)\r
-  {\r
-    /* Enable STOP interrupt */\r
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
-  }\r
-  /* else prepare a new DMA transfer and enable TCReload interrupt */\r
-  else\r
-  {\r
-    /* Update Buffer pointer */\r
-    hi2c->pBuffPtr += hi2c->XferSize;\r
-\r
-    /* Set the XferSize to transfer */\r
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
-    {\r
-      hi2c->XferSize = MAX_NBYTE_SIZE;\r
-    }\r
-    else\r
-    {\r
-      hi2c->XferSize = hi2c->XferCount;\r
-    }\r
-\r
-    /* Enable the DMA channel */\r
-    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)\r
-    {\r
-      /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
-    }\r
-    else\r
-    {\r
-      /* Enable TC interrupts */\r
-      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  DMA I2C slave receive process complete callback.\r
-  * @param  hdma DMA handle\r
-  * @retval None\r
-  */\r
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-  uint32_t tmpoptions = hi2c->XferOptions;\r
-\r
-  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \\r
-      (tmpoptions != I2C_NO_OPTION_FRAME))\r
-  {\r
-    /* Disable DMA Request */\r
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
-\r
-    /* Call I2C Slave Sequential complete process */\r
-    I2C_ITSlaveSeqCplt(hi2c);\r
-  }\r
-  else\r
-  {\r
-    /* No specific action, Master fully manage the generation of STOP condition */\r
-    /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
-    /* So STOP condition should be manage through Interrupt treatment */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  DMA I2C communication error callback.\r
-  * @param hdma DMA handle\r
-  * @retval None\r
-  */\r
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Disable Acknowledge */\r
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
-\r
-  /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
-}\r
-\r
-/**\r
-  * @brief DMA I2C communication abort callback\r
-  *        (To be called at end of DMA Abort procedure).\r
-  * @param hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)\r
-{\r
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Reset AbortCpltCallback */\r
-  hi2c->hdmatx->XferAbortCallback = NULL;\r
-  hi2c->hdmarx->XferAbortCallback = NULL;\r
-\r
-  /* Check if come from abort from user */\r
-  if (hi2c->State == HAL_I2C_STATE_ABORT)\r
-  {\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->AbortCpltCallback(hi2c);\r
-#else\r
-    HAL_I2C_AbortCpltCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-    /* Call the corresponding callback to inform upper layer of End of Transfer */\r
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
-    hi2c->ErrorCallback(hi2c);\r
-#else\r
-    HAL_I2C_ErrorCallback(hi2c);\r
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  This function handles I2C Communication Timeout.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  Flag Specifies the I2C flag to check.\r
-  * @param  Status The new Flag status (SET or RESET).\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart Tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)\r
-  {\r
-    /* Check for the Timeout */\r
-    if (Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
-      {\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
-        hi2c->State = HAL_I2C_STATE_READY;\r
-        hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart Tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)\r
-  {\r
-    /* Check if a NACK is detected */\r
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Check for the Timeout */\r
-    if (Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
-      {\r
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
-        hi2c->State = HAL_I2C_STATE_READY;\r
-        hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart Tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
-  {\r
-    /* Check if a NACK is detected */\r
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Check for the Timeout */\r
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
-    {\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
-      hi2c->State = HAL_I2C_STATE_READY;\r
-      hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart Tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\r
-  {\r
-    /* Check if a NACK is detected */\r
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    /* Check if a STOPF is detected */\r
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
-    {\r
-      /* Check if an RXNE is pending */\r
-      /* Store Last receive data if any */\r
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))\r
-      {\r
-        /* Return HAL_OK */\r
-        /* The Reading of data from RXDR will be done in caller function */\r
-        return HAL_OK;\r
-      }\r
-      else\r
-      {\r
-        /* Clear STOP Flag */\r
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-        /* Clear Configuration Register 2 */\r
-        I2C_RESET_CR2(hi2c);\r
-\r
-        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
-        hi2c->State = HAL_I2C_STATE_READY;\r
-        hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hi2c);\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-\r
-    /* Check for the Timeout */\r
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
-    {\r
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
-      hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-      /* Process Unlocked */\r
-      __HAL_UNLOCK(hi2c);\r
-\r
-      return HAL_ERROR;\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart Tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r
-  {\r
-    /* Wait until STOP Flag is reset */\r
-    /* AutoEnd should be initiate after AF */\r
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
-    {\r
-      /* Check for the Timeout */\r
-      if (Timeout != HAL_MAX_DELAY)\r
-      {\r
-        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
-        {\r
-          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
-          hi2c->State = HAL_I2C_STATE_READY;\r
-          hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-          /* Process Unlocked */\r
-          __HAL_UNLOCK(hi2c);\r
-\r
-          return HAL_ERROR;\r
-        }\r
-      }\r
-    }\r
-\r
-    /* Clear NACKF Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
-\r
-    /* Clear STOP Flag */\r
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
-\r
-    /* Flush TX register */\r
-    I2C_Flush_TXDR(hi2c);\r
-\r
-    /* Clear Configuration Register 2 */\r
-    I2C_RESET_CR2(hi2c);\r
-\r
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-    hi2c->Mode = HAL_I2C_MODE_NONE;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_ERROR;\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).\r
-  * @param  hi2c I2C handle.\r
-  * @param  DevAddress Specifies the slave address to be programmed.\r
-  * @param  Size Specifies the number of bytes to be programmed.\r
-  *   This parameter must be a value between 0 and 255.\r
-  * @param  Mode New state of the I2C START condition generation.\r
-  *   This parameter can be one of the following values:\r
-  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .\r
-  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.\r
-  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.\r
-  * @param  Request New state of the I2C START condition generation.\r
-  *   This parameter can be one of the following values:\r
-  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.\r
-  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).\r
-  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.\r
-  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.\r
-  * @retval None\r
-  */\r
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
-  assert_param(IS_TRANSFER_MODE(Mode));\r
-  assert_param(IS_TRANSFER_REQUEST(Request));\r
-\r
-  /* update CR2 register */\r
-  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \\r
-             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));\r
-}\r
-\r
-/**\r
-  * @brief  Manage the enabling of Interrupts.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r
-  * @retval None\r
-  */\r
-static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
-{\r
-  uint32_t tmpisr = 0U;\r
-\r
-  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \\r
-      (hi2c->XferISR == I2C_Slave_ISR_DMA))\r
-  {\r
-    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
-    {\r
-      /* Enable ERR, STOP, NACK and ADDR interrupts */\r
-      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
-    }\r
-\r
-    if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
-    {\r
-      /* Enable ERR and NACK interrupts */\r
-      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
-    }\r
-\r
-    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
-    {\r
-      /* Enable STOP interrupts */\r
-      tmpisr |= I2C_IT_STOPI;\r
-    }\r
-\r
-    if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
-    {\r
-      /* Enable TC interrupts */\r
-      tmpisr |= I2C_IT_TCI;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
-    {\r
-      /* Enable ERR, STOP, NACK, and ADDR interrupts */\r
-      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
-    }\r
-\r
-    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
-    {\r
-      /* Enable ERR, TC, STOP, NACK and RXI interrupts */\r
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;\r
-    }\r
-\r
-    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
-    {\r
-      /* Enable ERR, TC, STOP, NACK and TXI interrupts */\r
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;\r
-    }\r
-\r
-    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
-    {\r
-      /* Enable STOP interrupts */\r
-      tmpisr |= I2C_IT_STOPI;\r
-    }\r
-  }\r
-\r
-  /* Enable interrupts only at the end */\r
-  /* to avoid the risk of I2C interrupt handle execution before */\r
-  /* all interrupts requested done */\r
-  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);\r
-}\r
-\r
-/**\r
-  * @brief  Manage the disabling of Interrupts.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2C.\r
-  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r
-  * @retval None\r
-  */\r
-static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
-{\r
-  uint32_t tmpisr = 0U;\r
-\r
-  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
-  {\r
-    /* Disable TC and TXI interrupts */\r
-    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;\r
-\r
-    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)\r
-    {\r
-      /* Disable NACK and STOP interrupts */\r
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
-    }\r
-  }\r
-\r
-  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
-  {\r
-    /* Disable TC and RXI interrupts */\r
-    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;\r
-\r
-    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)\r
-    {\r
-      /* Disable NACK and STOP interrupts */\r
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
-    }\r
-  }\r
-\r
-  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
-  {\r
-    /* Disable ADDR, NACK and STOP interrupts */\r
-    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
-  }\r
-\r
-  if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
-  {\r
-    /* Enable ERR and NACK interrupts */\r
-    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
-  }\r
-\r
-  if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
-  {\r
-    /* Enable STOP interrupts */\r
-    tmpisr |= I2C_IT_STOPI;\r
-  }\r
-\r
-  if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
-  {\r
-    /* Enable TC interrupts */\r
-    tmpisr |= I2C_IT_TCI;\r
-  }\r
-\r
-  /* Disable interrupts only at the end */\r
-  /* to avoid a breaking situation like at "t" time */\r
-  /* all disable interrupts request are not done */\r
-  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);\r
-}\r
-\r
-/**\r
-  * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.\r
-  * @param  hi2c I2C handle.\r
-  * @retval None\r
-  */\r
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* if user set XferOptions to I2C_OTHER_FRAME            */\r
-  /* it request implicitly to generate a restart condition */\r
-  /* set XferOptions to I2C_FIRST_FRAME                    */\r
-  if (hi2c->XferOptions == I2C_OTHER_FRAME)\r
-  {\r
-    hi2c->XferOptions = I2C_FIRST_FRAME;\r
-  }\r
-  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */\r
-  /* it request implicitly to generate a restart condition    */\r
-  /* then generate a stop condition at the end of transfer    */\r
-  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */\r
-  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)\r
-  {\r
-    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;\r
-  }\r
-  else\r
-  {\r
-    /* Nothing to do */\r
-  }\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_I2C_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
deleted file mode 100644 (file)
index 54d74c7..0000000
+++ /dev/null
@@ -1,339 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_i2c_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   I2C Extended HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of I2C Extended peripheral:\r
-  *           + Extended features functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-               ##### I2C peripheral Extended features  #####\r
-  ==============================================================================\r
-\r
-  [..] Comparing to other previous devices, the I2C interface for STM32L4xx\r
-       devices contains the following additional features\r
-\r
-       (+) Possibility to disable or enable Analog Noise Filter\r
-       (+) Use of a configured Digital Noise Filter\r
-       (+) Disable or enable wakeup from Stop mode(s)\r
-       (+) Disable or enable Fast Mode Plus\r
-\r
-                     ##### How to use this driver #####\r
-  ==============================================================================\r
-  [..] This driver provides functions to configure Noise Filter and Wake Up Feature\r
-    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()\r
-    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()\r
-    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :\r
-          (++) HAL_I2CEx_EnableWakeUp()\r
-          (++) HAL_I2CEx_DisableWakeUp()\r
-    (#) Configure the enable or disable of fast mode plus driving capability using the functions :\r
-          (++) HAL_I2CEx_EnableFastModePlus()\r
-          (++) HAL_I2CEx_DisableFastModePlus()\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup I2CEx I2CEx\r
-  * @brief I2C Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_I2C_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions\r
-  * @brief    Extended features functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Extended features functions #####\r
- ===============================================================================\r
-    [..] This section provides functions allowing to:\r
-      (+) Configure Noise Filters\r
-      (+) Configure Wake Up Feature\r
-      (+) Configure Fast Mode Plus\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Configure I2C Analog noise filter.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2Cx peripheral.\r
-  * @param  AnalogFilter New state of the Analog filter.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
-  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_BUSY;\r
-\r
-    /* Disable the selected I2C peripheral */\r
-    __HAL_I2C_DISABLE(hi2c);\r
-\r
-    /* Reset I2Cx ANOFF bit */\r
-    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);\r
-\r
-    /* Set analog filter bit*/\r
-    hi2c->Instance->CR1 |= AnalogFilter;\r
-\r
-    __HAL_I2C_ENABLE(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Configure I2C Digital noise filter.\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2Cx peripheral.\r
-  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\r
-{\r
-  uint32_t tmpreg;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
-  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_BUSY;\r
-\r
-    /* Disable the selected I2C peripheral */\r
-    __HAL_I2C_DISABLE(hi2c);\r
-\r
-    /* Get the old register value */\r
-    tmpreg = hi2c->Instance->CR1;\r
-\r
-    /* Reset I2Cx DNF bits [11:8] */\r
-    tmpreg &= ~(I2C_CR1_DNF);\r
-\r
-    /* Set I2Cx DNF coefficient */\r
-    tmpreg |= DigitalFilter << 8U;\r
-\r
-    /* Store the new register value */\r
-    hi2c->Instance->CR1 = tmpreg;\r
-\r
-    __HAL_I2C_ENABLE(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Enable I2C wakeup from Stop mode(s).\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2Cx peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_BUSY;\r
-\r
-    /* Disable the selected I2C peripheral */\r
-    __HAL_I2C_DISABLE(hi2c);\r
-\r
-    /* Enable wakeup from stop mode */\r
-    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;\r
-\r
-    __HAL_I2C_ENABLE(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Disable I2C wakeup from Stop mode(s).\r
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified I2Cx peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));\r
-\r
-  if (hi2c->State == HAL_I2C_STATE_READY)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_BUSY;\r
-\r
-    /* Disable the selected I2C peripheral */\r
-    __HAL_I2C_DISABLE(hi2c);\r
-\r
-    /* Enable wakeup from stop mode */\r
-    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);\r
-\r
-    __HAL_I2C_ENABLE(hi2c);\r
-\r
-    hi2c->State = HAL_I2C_STATE_READY;\r
-\r
-    /* Process Unlocked */\r
-    __HAL_UNLOCK(hi2c);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Enable the I2C fast mode plus driving capability.\r
-  * @param ConfigFastModePlus Selects the pin.\r
-  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r
-  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected\r
-  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.\r
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r
-  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r
-  * @note  For all I2C2 pins fast mode plus driving capability can be enabled\r
-  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.\r
-  * @note  For all I2C3 pins fast mode plus driving capability can be enabled\r
-  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.\r
-  * @note  For all I2C4 pins fast mode plus driving capability can be enabled\r
-  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.\r
-  * @retval None\r
-  */\r
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)\r
-{\r
-  /* Check the parameter */\r
-  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
-\r
-  /* Enable SYSCFG clock */\r
-  __HAL_RCC_SYSCFG_CLK_ENABLE();\r
-\r
-  /* Enable fast mode plus driving capability for selected pin */\r
-  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);\r
-}\r
-\r
-/**\r
-  * @brief Disable the I2C fast mode plus driving capability.\r
-  * @param ConfigFastModePlus Selects the pin.\r
-  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r
-  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected\r
-  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.\r
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r
-  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r
-  * @note  For all I2C2 pins fast mode plus driving capability can be disabled\r
-  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.\r
-  * @note  For all I2C3 pins fast mode plus driving capability can be disabled\r
-  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.\r
-  * @note  For all I2C4 pins fast mode plus driving capability can be disabled\r
-  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.\r
-  * @retval None\r
-  */\r
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)\r
-{\r
-  /* Check the parameter */\r
-  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
-\r
-  /* Enable SYSCFG clock */\r
-  __HAL_RCC_SYSCFG_CLK_ENABLE();\r
-\r
-  /* Disable fast mode plus driving capability for selected pin */\r
-  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_I2C_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
deleted file mode 100644 (file)
index 756b6d4..0000000
+++ /dev/null
@@ -1,2452 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pcd.c\r
-  * @author  MCD Application Team\r
-  * @brief   PCD HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the USB Peripheral Controller:\r
-  *           + Initialization and de-initialization functions\r
-  *           + IO operation functions\r
-  *           + Peripheral Control functions\r
-  *           + Peripheral State functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                    ##### How to use this driver #####\r
-  ==============================================================================\r
-    [..]\r
-      The PCD HAL driver can be used as follows:\r
-\r
-     (#) Declare a PCD_HandleTypeDef handle structure, for example:\r
-         PCD_HandleTypeDef  hpcd;\r
-\r
-     (#) Fill parameters of Init structure in HCD handle\r
-\r
-     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)\r
-\r
-     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:\r
-         (##) Enable the PCD/USB Low Level interface clock using\r
-              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral\r
-\r
-         (##) Initialize the related GPIO clocks\r
-         (##) Configure PCD pin-out\r
-         (##) Configure PCD NVIC interrupt\r
-\r
-     (#)Associate the Upper USB device stack to the HAL PCD Driver:\r
-         (##) hpcd.pData = pdev;\r
-\r
-     (#)Enable PCD transmission and reception:\r
-         (##) HAL_PCD_Start();\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PCD PCD\r
-  * @brief PCD HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_PCD_MODULE_ENABLED\r
-\r
-#if defined (USB) || defined (USB_OTG_FS)\r
-\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private constants ---------------------------------------------------------*/\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup PCD_Private_Macros PCD Private Macros\r
-  * @{\r
-  */\r
-#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))\r
-#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions prototypes ----------------------------------------------*/\r
-/** @defgroup PCD_Private_Functions PCD Private Functions\r
-  * @{\r
-  */\r
-#if defined (USB_OTG_FS)\r
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
-static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
-static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);\r
-#endif /* defined (USB) */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup PCD_Exported_Functions PCD Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r
- *  @brief    Initialization and Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-            ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initializes the PCD according to the specified\r
-  *         parameters in the PCD_InitTypeDef and initialize the associated handle.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)\r
-{\r
-#if defined (USB_OTG_FS)\r
-  USB_OTG_GlobalTypeDef *USBx;\r
-#endif /* defined (USB_OTG_FS) */\r
-  uint8_t i;\r
-\r
-  /* Check the PCD handle allocation */\r
-  if (hpcd == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));\r
-\r
-#if defined (USB_OTG_FS)\r
-  USBx = hpcd->Instance;\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    hpcd->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->SOFCallback = HAL_PCD_SOFCallback;\r
-    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;\r
-    hpcd->ResetCallback = HAL_PCD_ResetCallback;\r
-    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;\r
-    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;\r
-    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;\r
-    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;\r
-    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;\r
-    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;\r
-    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;\r
-    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;\r
-    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;\r
-    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;\r
-\r
-    if (hpcd->MspInitCallback == NULL)\r
-    {\r
-      hpcd->MspInitCallback = HAL_PCD_MspInit;\r
-    }\r
-\r
-    /* Init the low level hardware */\r
-    hpcd->MspInitCallback(hpcd);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
-    HAL_PCD_MspInit(hpcd);\r
-#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */\r
-  }\r
-\r
-  hpcd->State = HAL_PCD_STATE_BUSY;\r
-\r
-#if defined (USB_OTG_FS)\r
-  /* Disable DMA mode for FS instance */\r
-  if ((USBx->CID & (0x1U << 8)) == 0U)\r
-  {\r
-    hpcd->Init.dma_enable = 0U;\r
-  }\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-  /* Disable the Interrupts */\r
-  __HAL_PCD_DISABLE(hpcd);\r
-\r
-  /*Init the Core (common init.) */\r
-  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)\r
-  {\r
-    hpcd->State = HAL_PCD_STATE_ERROR;\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Force Device Mode*/\r
-  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);\r
-\r
-  /* Init endpoints structures */\r
-  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\r
-  {\r
-    /* Init ep structure */\r
-    hpcd->IN_ep[i].is_in = 1U;\r
-    hpcd->IN_ep[i].num = i;\r
-    hpcd->IN_ep[i].tx_fifo_num = i;\r
-    /* Control until ep is activated */\r
-    hpcd->IN_ep[i].type = EP_TYPE_CTRL;\r
-    hpcd->IN_ep[i].maxpacket = 0U;\r
-    hpcd->IN_ep[i].xfer_buff = 0U;\r
-    hpcd->IN_ep[i].xfer_len = 0U;\r
-  }\r
-\r
-  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\r
-  {\r
-    hpcd->OUT_ep[i].is_in = 0U;\r
-    hpcd->OUT_ep[i].num = i;\r
-    /* Control until ep is activated */\r
-    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;\r
-    hpcd->OUT_ep[i].maxpacket = 0U;\r
-    hpcd->OUT_ep[i].xfer_buff = 0U;\r
-    hpcd->OUT_ep[i].xfer_len = 0U;\r
-  }\r
-\r
-  /* Init Device */\r
-  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)\r
-  {\r
-    hpcd->State = HAL_PCD_STATE_ERROR;\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  hpcd->USB_Address = 0U;\r
-  hpcd->State = HAL_PCD_STATE_READY;\r
-  \r
-  /* Activate LPM */\r
-  if (hpcd->Init.lpm_enable == 1U)\r
-  {\r
-    (void)HAL_PCDEx_ActivateLPM(hpcd);\r
-  }\r
-  \r
-  (void)USB_DevDisconnect(hpcd->Instance);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes the PCD peripheral.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Check the PCD handle allocation */\r
-  if (hpcd == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  hpcd->State = HAL_PCD_STATE_BUSY;\r
-\r
-  /* Stop Device */\r
-  (void)HAL_PCD_Stop(hpcd);\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-  if (hpcd->MspDeInitCallback == NULL)\r
-  {\r
-    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */\r
-  }\r
-\r
-  /* DeInit the low level hardware */\r
-  hpcd->MspDeInitCallback(hpcd);\r
-#else\r
-  /* DeInit the low level hardware: CLOCK, NVIC.*/\r
-  HAL_PCD_MspDeInit(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-  hpcd->State = HAL_PCD_STATE_RESET;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the PCD MSP.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes PCD MSP.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-/**\r
-  * @brief  Register a User USB PCD Callback\r
-  *         To be used instead of the weak predefined callback\r
-  * @param  hpcd USB PCD handle\r
-  * @param  CallbackID ID of the callback to be registered\r
-  *         This parameter can be one of the following values:\r
-  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID\r
-  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID\r
-  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID\r
-  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID\r
-  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID\r
-  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID\r
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID\r
-  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID\r
-  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID\r
-  * @param  pCallback pointer to the Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-    return HAL_ERROR;\r
-  }\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_PCD_SOF_CB_ID :\r
-        hpcd->SOFCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_SETUPSTAGE_CB_ID :\r
-        hpcd->SetupStageCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_RESET_CB_ID :\r
-        hpcd->ResetCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_SUSPEND_CB_ID :\r
-        hpcd->SuspendCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_RESUME_CB_ID :\r
-        hpcd->ResumeCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_CONNECT_CB_ID :\r
-        hpcd->ConnectCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_DISCONNECT_CB_ID :\r
-        hpcd->DisconnectCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_MSPINIT_CB_ID :\r
-        hpcd->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_MSPDEINIT_CB_ID :\r
-        hpcd->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (hpcd->State == HAL_PCD_STATE_RESET)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_PCD_MSPINIT_CB_ID :\r
-        hpcd->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_PCD_MSPDEINIT_CB_ID :\r
-        hpcd->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister an USB PCD Callback\r
-  *         USB PCD callabck is redirected to the weak predefined callback\r
-  * @param  hpcd USB PCD handle\r
-  * @param  CallbackID ID of the callback to be unregistered\r
-  *         This parameter can be one of the following values:\r
-  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID\r
-  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID\r
-  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID\r
-  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID\r
-  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID\r
-  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID\r
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID\r
-  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID\r
-  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  /* Setup Legacy weak Callbacks  */\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_PCD_SOF_CB_ID :\r
-        hpcd->SOFCallback = HAL_PCD_SOFCallback;\r
-        break;\r
-\r
-      case HAL_PCD_SETUPSTAGE_CB_ID :\r
-        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;\r
-        break;\r
-\r
-      case HAL_PCD_RESET_CB_ID :\r
-        hpcd->ResetCallback = HAL_PCD_ResetCallback;\r
-        break;\r
-\r
-      case HAL_PCD_SUSPEND_CB_ID :\r
-        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;\r
-        break;\r
-\r
-      case HAL_PCD_RESUME_CB_ID :\r
-        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;\r
-        break;\r
-\r
-      case HAL_PCD_CONNECT_CB_ID :\r
-        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;\r
-        break;\r
-\r
-      case HAL_PCD_DISCONNECT_CB_ID :\r
-        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;\r
-        break;\r
-\r
-      case HAL_PCD_MSPINIT_CB_ID :\r
-        hpcd->MspInitCallback = HAL_PCD_MspInit;\r
-        break;\r
-\r
-      case HAL_PCD_MSPDEINIT_CB_ID :\r
-        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (hpcd->State == HAL_PCD_STATE_RESET)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_PCD_MSPINIT_CB_ID :\r
-        hpcd->MspInitCallback = HAL_PCD_MspInit;\r
-        break;\r
-\r
-      case HAL_PCD_MSPDEINIT_CB_ID :\r
-        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register USB PCD Data OUT Stage Callback\r
-  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->DataOutStageCallback = pCallback;\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister the USB PCD Data OUT Stage Callback\r
-  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register USB PCD Data IN Stage Callback\r
-  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->DataInStageCallback = pCallback;\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister the USB PCD Data IN Stage Callback\r
-  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register USB PCD Iso OUT incomplete Callback\r
-  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->ISOOUTIncompleteCallback = pCallback;\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister the USB PCD Iso OUT incomplete Callback\r
-  *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register USB PCD Iso IN incomplete Callback\r
-  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->ISOINIncompleteCallback = pCallback;\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister the USB PCD Iso IN incomplete Callback\r
-  *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register USB PCD BCD Callback\r
-  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @param  pCallback pointer to the USB PCD BCD Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->BCDCallback = pCallback;\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister the USB PCD BCD Callback\r
-  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Register USB PCD LPM Callback\r
-  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @param  pCallback pointer to the USB PCD LPM Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->LPMCallback = pCallback;\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  UnRegister the USB PCD LPM Callback\r
-  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if (hpcd->State == HAL_PCD_STATE_READY)\r
-  {\r
-    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return status;\r
-}\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions\r
- *  @brief   Data transfers functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### IO operation functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to manage the PCD data\r
-    transfers.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Start the USB device\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)\r
-{\r
-#if defined (USB_OTG_FS)\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-  __HAL_LOCK(hpcd);\r
-#if defined (USB_OTG_FS)\r
-  if (hpcd->Init.battery_charging_enable == 1U)\r
-  {\r
-    /* Enable USB Transceiver */\r
-    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\r
-  }\r
-#endif /* defined (USB_OTG_FS) */\r
-  (void)USB_DevConnect(hpcd->Instance);\r
-  __HAL_PCD_ENABLE(hpcd);\r
-  __HAL_UNLOCK(hpcd);\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stop the USB device.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)\r
-{\r
-  __HAL_LOCK(hpcd);\r
-  __HAL_PCD_DISABLE(hpcd);\r
-\r
-  if (USB_StopDevice(hpcd->Instance) != HAL_OK)\r
-  {\r
-    __HAL_UNLOCK(hpcd);\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  (void)USB_DevDisconnect(hpcd->Instance);\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return HAL_OK;\r
-}\r
-#if defined (USB_OTG_FS)\r
-/**\r
-  * @brief  Handles PCD interrupt request.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t i, ep_intr, epint, epnum = 0U;\r
-  uint32_t fifoemptymsk, temp;\r
-  USB_OTG_EPTypeDef *ep;\r
-\r
-  /* ensure that we are in device mode */\r
-  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)\r
-  {\r
-    /* avoid spurious interrupt */\r
-    if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))\r
-    {\r
-      return;\r
-    }\r
-\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))\r
-    {\r
-      /* incorrect mode, acknowledge the interrupt */\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);\r
-    }\r
-\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))\r
-    {\r
-      epnum = 0U;\r
-\r
-      /* Read in the device interrupt bits */\r
-      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);\r
-\r
-      while (ep_intr != 0U)\r
-      {\r
-        if ((ep_intr & 0x1U) != 0U)\r
-        {\r
-          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);\r
-\r
-          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)\r
-          {\r
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);\r
-            (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);\r
-          }\r
-\r
-          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)\r
-          {\r
-            /* Class B setup phase done for previous decoded setup */\r
-            (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);\r
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);\r
-          }\r
-\r
-          if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)\r
-          {\r
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);\r
-          }\r
-\r
-          /* Clear Status Phase Received interrupt */\r
-          if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\r
-          {\r
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\r
-          }\r
-\r
-          /* Clear OUT NAK interrupt */\r
-          if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)\r
-          {\r
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);\r
-          }\r
-        }\r
-        epnum++;\r
-        ep_intr >>= 1U;\r
-      }\r
-    }\r
-\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))\r
-    {\r
-      /* Read in the device interrupt bits */\r
-      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);\r
-\r
-      epnum = 0U;\r
-\r
-      while (ep_intr != 0U)\r
-      {\r
-        if ((ep_intr & 0x1U) != 0U) /* In ITR */\r
-        {\r
-          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);\r
-\r
-          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)\r
-          {\r
-            fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));\r
-            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
-\r
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-            hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);\r
-#else\r
-            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-          }\r
-          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)\r
-          {\r
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);\r
-          }\r
-          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)\r
-          {\r
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);\r
-          }\r
-          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)\r
-          {\r
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);\r
-          }\r
-          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)\r
-          {\r
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);\r
-          }\r
-          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)\r
-          {\r
-            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);\r
-          }\r
-        }\r
-        epnum++;\r
-        ep_intr >>= 1U;\r
-      }\r
-    }\r
-\r
-    /* Handle Resume Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))\r
-    {\r
-      /* Clear the Remote Wake-up Signaling */\r
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r
-\r
-      if (hpcd->LPM_State == LPM_L1)\r
-      {\r
-        hpcd->LPM_State = LPM_L0;\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-        hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);\r
-#else\r
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-      }\r
-      else\r
-      {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-        hpcd->ResumeCallback(hpcd);\r
-#else\r
-        HAL_PCD_ResumeCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-      }\r
-\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);\r
-    }\r
-\r
-    /* Handle Suspend Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))\r
-    {\r
-      if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
-      {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-        hpcd->SuspendCallback(hpcd);\r
-#else\r
-        HAL_PCD_SuspendCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-      }\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);\r
-    }\r
-    \r
-    /* Handle LPM Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))\r
-    {\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);\r
-\r
-      if (hpcd->LPM_State == LPM_L0)\r
-      {\r
-        hpcd->LPM_State = LPM_L1;\r
-        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-        hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);\r
-#else\r
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-      }\r
-      else\r
-      {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-        hpcd->SuspendCallback(hpcd);\r
-#else\r
-        HAL_PCD_SuspendCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-      }\r
-    }\r
-    \r
-    /* Handle Reset Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))\r
-    {\r
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r
-      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);\r
-\r
-      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\r
-      {\r
-        USBx_INEP(i)->DIEPINT = 0xFB7FU;\r
-        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
-        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r
-        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
-      }\r
-      USBx_DEVICE->DAINTMSK |= 0x10001U;\r
-\r
-      if (hpcd->Init.use_dedicated_ep1 != 0U)\r
-      {\r
-        USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |\r
-                                   USB_OTG_DOEPMSK_XFRCM |\r
-                                   USB_OTG_DOEPMSK_EPDM;\r
-\r
-        USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |\r
-                                  USB_OTG_DIEPMSK_XFRCM |\r
-                                  USB_OTG_DIEPMSK_EPDM;\r
-      }\r
-      else\r
-      {\r
-        USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |\r
-                                USB_OTG_DOEPMSK_XFRCM |\r
-                                USB_OTG_DOEPMSK_EPDM |\r
-                                USB_OTG_DOEPMSK_OTEPSPRM |\r
-                                USB_OTG_DOEPMSK_NAKM;\r
-\r
-        USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |\r
-                                USB_OTG_DIEPMSK_XFRCM |\r
-                                USB_OTG_DIEPMSK_EPDM;\r
-      }\r
-\r
-      /* Set Default Address to 0 */\r
-      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\r
-\r
-      /* setup EP0 to receive SETUP packets */\r
-      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);\r
-\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);\r
-    }\r
-\r
-    /* Handle Enumeration done Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))\r
-    {\r
-      (void)USB_ActivateSetup(hpcd->Instance);\r
-      hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);\r
-\r
-      /* Set USB Turnaround time */\r
-      (void)USB_SetTurnaroundTime(hpcd->Instance,\r
-                                  HAL_RCC_GetHCLKFreq(),\r
-                                  (uint8_t)hpcd->Init.speed);\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->ResetCallback(hpcd);\r
-#else\r
-      HAL_PCD_ResetCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);\r
-    }\r
-\r
-    /* Handle RxQLevel Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))\r
-    {\r
-      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
-\r
-      temp = USBx->GRXSTSP;\r
-\r
-      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];\r
-\r
-      if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)\r
-      {\r
-        if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)\r
-        {\r
-          (void)USB_ReadPacket(USBx, ep->xfer_buff,\r
-                               (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));\r
-\r
-          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
-          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
-        }\r
-      }\r
-      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)\r
-      {\r
-        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);\r
-        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
-      }\r
-      else\r
-      {\r
-        /* ... */\r
-      }\r
-      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
-    }\r
-\r
-    /* Handle SOF Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->SOFCallback(hpcd);\r
-#else\r
-      HAL_PCD_SOFCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);\r
-    }\r
-\r
-    /* Handle Incomplete ISO IN Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);\r
-#else\r
-      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);\r
-    }\r
-\r
-    /* Handle Incomplete ISO OUT Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);\r
-#else\r
-      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r
-    }\r
-\r
-    /* Handle Connection event Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->ConnectCallback(hpcd);\r
-#else\r
-      HAL_PCD_ConnectCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);\r
-    }\r
-\r
-    /* Handle Disconnection event Interrupt */\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))\r
-    {\r
-      temp = hpcd->Instance->GOTGINT;\r
-\r
-      if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)\r
-      {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-        hpcd->DisconnectCallback(hpcd);\r
-#else\r
-        HAL_PCD_DisconnectCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-      }\r
-      hpcd->Instance->GOTGINT |= temp;\r
-    }\r
-  }\r
-}\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-/**\r
-  * @brief  This function handles PCD interrupt request.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r
-{\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))\r
-  {\r
-    /* servicing of the endpoint correct transfer interrupt */\r
-    /* clear of the CTR flag into the sub */\r
-    (void)PCD_EP_ISR_Handler(hpcd);\r
-  }\r
-\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))\r
-  {\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->ResetCallback(hpcd);\r
-#else\r
-    HAL_PCD_ResetCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-    (void)HAL_PCD_SetAddress(hpcd, 0U);\r
-  }\r
-\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))\r
-  {\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);\r
-  }\r
-\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))\r
-  {\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);\r
-  }\r
-\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))\r
-  {\r
-    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);\r
-    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);\r
-\r
-    if (hpcd->LPM_State == LPM_L1)\r
-    {\r
-      hpcd->LPM_State = LPM_L0;\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);\r
-#else\r
-      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->ResumeCallback(hpcd);\r
-#else\r
-    HAL_PCD_ResumeCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);\r
-  }\r
-\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))\r
-  {\r
-    /* Force low-power mode in the macrocell */\r
-    hpcd->Instance->CNTR |= USB_CNTR_FSUSP;\r
-\r
-    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);\r
-\r
-    hpcd->Instance->CNTR |= USB_CNTR_LPMODE;\r
-\r
-    if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U)\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->SuspendCallback(hpcd);\r
-#else\r
-      HAL_PCD_SuspendCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-\r
-  /* Handle LPM Interrupt */\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))\r
-  {\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);\r
-    if (hpcd->LPM_State == LPM_L0)\r
-    {\r
-      /* Force suspend and low-power mode before going to L1 state*/\r
-      hpcd->Instance->CNTR |= USB_CNTR_LPMODE;\r
-      hpcd->Instance->CNTR |= USB_CNTR_FSUSP;\r
-\r
-      hpcd->LPM_State = LPM_L1;\r
-      hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);\r
-#else\r
-      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-    else\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->SuspendCallback(hpcd);\r
-#else\r
-      HAL_PCD_SuspendCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))\r
-  {\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->SOFCallback(hpcd);\r
-#else\r
-    HAL_PCD_SOFCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))\r
-  {\r
-    /* clear ESOF flag in ISTR */\r
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);\r
-  }\r
-}\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @brief  Data OUT stage callback.\r
-  * @param  hpcd PCD handle\r
-  * @param  epnum endpoint number\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-  UNUSED(epnum);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_DataOutStageCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Data IN stage callback\r
-  * @param  hpcd PCD handle\r
-  * @param  epnum endpoint number\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-  UNUSED(epnum);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_DataInStageCallback could be implemented in the user file\r
-   */\r
-}\r
-/**\r
-  * @brief  Setup stage callback\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_SetupStageCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  USB Start Of Frame callback.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_SOFCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  USB Reset callback.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_ResetCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Suspend event callback.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_SuspendCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Resume event callback.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_ResumeCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Incomplete ISO OUT callback.\r
-  * @param  hpcd PCD handle\r
-  * @param  epnum endpoint number\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-  UNUSED(epnum);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Incomplete ISO IN callback.\r
-  * @param  hpcd PCD handle\r
-  * @param  epnum endpoint number\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-  UNUSED(epnum);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Connection event callback.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_ConnectCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Disconnection event callback.\r
-  * @param  hpcd PCD handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCD_DisconnectCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions\r
- *  @brief   management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Peripheral Control functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to control the PCD data\r
-    transfers.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Connect the USB device\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)\r
-{\r
-#if defined (USB_OTG_FS)\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-  __HAL_LOCK(hpcd);\r
-#if defined (USB_OTG_FS)\r
-  if (hpcd->Init.battery_charging_enable == 1U)\r
-  {\r
-    /* Enable USB Transceiver */\r
-    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\r
-  }\r
-#endif /* defined (USB_OTG_FS) */\r
-  (void)USB_DevConnect(hpcd->Instance);\r
-  __HAL_UNLOCK(hpcd);\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Disconnect the USB device.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)\r
-{\r
-#if defined (USB_OTG_FS)\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-\r
-#endif /* defined (USB_OTG_FS) */\r
-  __HAL_LOCK(hpcd);\r
-  (void)USB_DevDisconnect(hpcd->Instance);\r
-#if defined (USB_OTG_FS)\r
-  if (hpcd->Init.battery_charging_enable == 1U)\r
-  {\r
-    /* Disable USB Transceiver */\r
-    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
-  }\r
-#endif /* defined (USB_OTG_FS) */\r
-  __HAL_UNLOCK(hpcd);\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Set the USB Device address.\r
-  * @param  hpcd PCD handle\r
-  * @param  address new device address\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)\r
-{\r
-  __HAL_LOCK(hpcd);\r
-  hpcd->USB_Address = address;\r
-  (void)USB_SetDevAddress(hpcd->Instance, address);\r
-  __HAL_UNLOCK(hpcd);\r
-  return HAL_OK;\r
-}\r
-/**\r
-  * @brief  Open and configure an endpoint.\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @param  ep_mps endpoint max packet size\r
-  * @param  ep_type endpoint type\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)\r
-{\r
-  HAL_StatusTypeDef  ret = HAL_OK;\r
-  PCD_EPTypeDef *ep;\r
-\r
-  if ((ep_addr & 0x80U) == 0x80U)\r
-  {\r
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
-    ep->is_in = 1U;\r
-  }\r
-  else\r
-  {\r
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
-    ep->is_in = 0U;\r
-  }\r
-\r
-  ep->num = ep_addr & EP_ADDR_MSK;\r
-  ep->maxpacket = ep_mps;\r
-  ep->type = ep_type;\r
-\r
-  if (ep->is_in != 0U)\r
-  {\r
-    /* Assign a Tx FIFO */\r
-    ep->tx_fifo_num = ep->num;\r
-  }\r
-  /* Set initial data PID. */\r
-  if (ep_type == EP_TYPE_BULK)\r
-  {\r
-    ep->data_pid_start = 0U;\r
-  }\r
-\r
-  __HAL_LOCK(hpcd);\r
-  (void)USB_ActivateEndpoint(hpcd->Instance, ep);\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return ret;\r
-}\r
-\r
-/**\r
-  * @brief  Deactivate an endpoint.\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
-{\r
-  PCD_EPTypeDef *ep;\r
-\r
-  if ((ep_addr & 0x80U) == 0x80U)\r
-  {\r
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
-    ep->is_in = 1U;\r
-  }\r
-  else\r
-  {\r
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
-    ep->is_in = 0U;\r
-  }\r
-  ep->num   = ep_addr & EP_ADDR_MSK;\r
-\r
-  __HAL_LOCK(hpcd);\r
-  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);\r
-  __HAL_UNLOCK(hpcd);\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Receive an amount of data.\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @param  pBuf pointer to the reception buffer\r
-  * @param  len amount of data to be received\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
-{\r
-  PCD_EPTypeDef *ep;\r
-\r
-  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
-\r
-  /*setup and start the Xfer */\r
-  ep->xfer_buff = pBuf;\r
-  ep->xfer_len = len;\r
-  ep->xfer_count = 0U;\r
-  ep->is_in = 0U;\r
-  ep->num = ep_addr & EP_ADDR_MSK;\r
-\r
-  if ((ep_addr & EP_ADDR_MSK) == 0U)\r
-  {\r
-    (void)USB_EP0StartXfer(hpcd->Instance, ep);\r
-  }\r
-  else\r
-  {\r
-    (void)USB_EPStartXfer(hpcd->Instance, ep);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Get Received Data Size\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @retval Data Size\r
-  */\r
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
-{\r
-  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;\r
-}\r
-/**\r
-  * @brief  Send an amount of data\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @param  pBuf pointer to the transmission buffer\r
-  * @param  len amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
-{\r
-  PCD_EPTypeDef *ep;\r
-\r
-  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
-\r
-  /*setup and start the Xfer */\r
-  ep->xfer_buff = pBuf;\r
-  ep->xfer_len = len;\r
-  ep->xfer_count = 0U;\r
-  ep->is_in = 1U;\r
-  ep->num = ep_addr & EP_ADDR_MSK;\r
-\r
-  if ((ep_addr & EP_ADDR_MSK) == 0U)\r
-  {\r
-    (void)USB_EP0StartXfer(hpcd->Instance, ep);\r
-  }\r
-  else\r
-  {\r
-    (void)USB_EPStartXfer(hpcd->Instance, ep);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Set a STALL condition over an endpoint\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
-{\r
-  PCD_EPTypeDef *ep;\r
-\r
-  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if ((0x80U & ep_addr) == 0x80U)\r
-  {\r
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
-    ep->is_in = 1U;\r
-  }\r
-  else\r
-  {\r
-    ep = &hpcd->OUT_ep[ep_addr];\r
-    ep->is_in = 0U;\r
-  }\r
-\r
-  ep->is_stall = 1U;\r
-  ep->num = ep_addr & EP_ADDR_MSK;\r
-\r
-  __HAL_LOCK(hpcd);\r
-\r
-  (void)USB_EPSetStall(hpcd->Instance, ep);\r
-  if ((ep_addr & EP_ADDR_MSK) == 0U)\r
-  {\r
-    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);\r
-  }\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Clear a STALL condition over in an endpoint\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
-{\r
-  PCD_EPTypeDef *ep;\r
-\r
-  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if ((0x80U & ep_addr) == 0x80U)\r
-  {\r
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
-    ep->is_in = 1U;\r
-  }\r
-  else\r
-  {\r
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\r
-    ep->is_in = 0U;\r
-  }\r
-\r
-  ep->is_stall = 0U;\r
-  ep->num = ep_addr & EP_ADDR_MSK;\r
-\r
-  __HAL_LOCK(hpcd);\r
-  (void)USB_EPClearStall(hpcd->Instance, ep);\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Flush an endpoint\r
-  * @param  hpcd PCD handle\r
-  * @param  ep_addr endpoint address\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
-{\r
-  __HAL_LOCK(hpcd);\r
-\r
-  if ((ep_addr & 0x80U) == 0x80U)\r
-  {\r
-    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);\r
-  }\r
-  else\r
-  {\r
-    (void)USB_FlushRxFifo(hpcd->Instance);\r
-  }\r
-\r
-  __HAL_UNLOCK(hpcd);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Activate remote wakeup signalling\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
-{\r
-  return (USB_ActivateRemoteWakeup(hpcd->Instance));\r
-}\r
-\r
-/**\r
-  * @brief  De-activate remote wakeup signalling.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
-{\r
-  return (USB_DeActivateRemoteWakeup(hpcd->Instance));\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions\r
- *  @brief   Peripheral State functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Peripheral State functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection permits to get in run-time the status of the peripheral\r
-    and the data flow.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Return the PCD handle state.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL state\r
-  */\r
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)\r
-{\r
-  return hpcd->State;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-/** @addtogroup PCD_Private_Functions\r
-  * @{\r
-  */\r
-#if defined (USB_OTG_FS)\r
-/**\r
-  * @brief  Check FIFO for the next packet to be loaded.\r
-  * @param  hpcd PCD handle\r
-  * @param  epnum endpoint number\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  USB_OTG_EPTypeDef *ep;\r
-  uint32_t len;\r
-  uint32_t len32b;\r
-  uint32_t fifoemptymsk;\r
-\r
-  ep = &hpcd->IN_ep[epnum];\r
-\r
-  if (ep->xfer_count > ep->xfer_len)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  len = ep->xfer_len - ep->xfer_count;\r
-\r
-  if (len > ep->maxpacket)\r
-  {\r
-    len = ep->maxpacket;\r
-  }\r
-\r
-  len32b = (len + 3U) / 4U;\r
-\r
-  while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&\r
-         (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))\r
-  {\r
-    /* Write the FIFO */\r
-    len = ep->xfer_len - ep->xfer_count;\r
-\r
-    if (len > ep->maxpacket)\r
-    {\r
-      len = ep->maxpacket;\r
-    }\r
-    len32b = (len + 3U) / 4U;\r
-\r
-    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len);\r
-\r
-    ep->xfer_buff  += len;\r
-    ep->xfer_count += len;\r
-  }\r
-\r
-  if (ep->xfer_len <= ep->xfer_count)\r
-  {\r
-    fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));\r
-    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  process EP OUT transfer complete interrupt.\r
-  * @param  hpcd PCD handle\r
-  * @param  epnum endpoint number\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\r
-  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;\r
-\r
-  if (gSNPSiD == USB_OTG_CORE_ID_310A)\r
-  {\r
-    /* StupPktRcvd = 1 this is a setup packet */\r
-    if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)\r
-    {\r
-      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\r
-    }\r
-    else\r
-    {\r
-      if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\r
-      {\r
-        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\r
-      }\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);\r
-#else\r
-      HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  else\r
-  {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);\r
-#else\r
-    HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  process EP OUT setup packet received interrupt.\r
-  * @param  hpcd PCD handle\r
-  * @param  epnum endpoint number\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\r
-  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;\r
-\r
-\r
-  if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&\r
-      ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))\r
-  {\r
-    CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\r
-  }\r
-\r
-  /* Inform the upper layer that a setup packet is available */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-  hpcd->SetupStageCallback(hpcd);\r
-#else\r
-  HAL_PCD_SetupStageCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-  return HAL_OK;\r
-}\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-/**\r
-  * @brief  This function handles PCD Endpoint interrupt request.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)\r
-{\r
-  PCD_EPTypeDef *ep;\r
-  uint16_t count;\r
-  uint16_t wIstr;\r
-  uint16_t wEPVal;\r
-  uint8_t epindex;\r
-\r
-  /* stay in loop while pending interrupts */\r
-  while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)\r
-  {\r
-    wIstr = hpcd->Instance->ISTR;\r
-    /* extract highest priority endpoint number */\r
-    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);\r
-\r
-    if (epindex == 0U)\r
-    {\r
-      /* Decode and service control endpoint interrupt */\r
-\r
-      /* DIR bit = origin of the interrupt */\r
-      if ((wIstr & USB_ISTR_DIR) == 0U)\r
-      {\r
-        /* DIR = 0 */\r
-\r
-        /* DIR = 0      => IN  int */\r
-        /* DIR = 0 implies that (EP_CTR_TX = 1) always  */\r
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);\r
-        ep = &hpcd->IN_ep[0];\r
-\r
-        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);\r
-        ep->xfer_buff += ep->xfer_count;\r
-\r
-        /* TX COMPLETE */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-        hpcd->DataInStageCallback(hpcd, 0U);\r
-#else\r
-        HAL_PCD_DataInStageCallback(hpcd, 0U);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-        if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))\r
-        {\r
-          hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);\r
-          hpcd->USB_Address = 0U;\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* DIR = 1 */\r
-\r
-        /* DIR = 1 & CTR_RX       => SETUP or OUT int */\r
-        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */\r
-        ep = &hpcd->OUT_ep[0];\r
-        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);\r
-\r
-        if ((wEPVal & USB_EP_SETUP) != 0U)\r
-        {\r
-          /* Get SETUP Packet*/\r
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);\r
-\r
-          USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,\r
-                      ep->pmaadress, (uint16_t)ep->xfer_count);\r
-\r
-          /* SETUP bit kept frozen while CTR_RX = 1*/\r
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);\r
-\r
-          /* Process SETUP Packet*/\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-          hpcd->SetupStageCallback(hpcd);\r
-#else\r
-          HAL_PCD_SetupStageCallback(hpcd);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-        }\r
-\r
-        else if ((wEPVal & USB_EP_CTR_RX) != 0U)\r
-        {\r
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);\r
-\r
-          /* Get Control Data OUT Packet*/\r
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);\r
-\r
-          if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))\r
-          {\r
-            USB_ReadPMA(hpcd->Instance, ep->xfer_buff,\r
-                        ep->pmaadress, (uint16_t)ep->xfer_count);\r
-\r
-            ep->xfer_buff += ep->xfer_count;\r
-\r
-            /* Process Control Data OUT Packet*/\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-            hpcd->DataOutStageCallback(hpcd, 0U);\r
-#else\r
-            HAL_PCD_DataOutStageCallback(hpcd, 0U);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-          }\r
-\r
-          PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);\r
-          PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Decode and service non control endpoints interrupt  */\r
-\r
-      /* process related endpoint register */\r
-      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);\r
-      if ((wEPVal & USB_EP_CTR_RX) != 0U)\r
-      {\r
-        /* clear int flag */\r
-        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);\r
-        ep = &hpcd->OUT_ep[epindex];\r
-\r
-        /* OUT double Buffering*/\r
-        if (ep->doublebuffer == 0U)\r
-        {\r
-          count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);\r
-          if (count != 0U)\r
-          {\r
-            USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);\r
-          }\r
-        }\r
-        else\r
-        {\r
-          if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)\r
-          {\r
-            /*read from endpoint BUF0Addr buffer*/\r
-            count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);\r
-            if (count != 0U)\r
-            {\r
-              USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);\r
-            }\r
-          }\r
-          else\r
-          {\r
-            /*read from endpoint BUF1Addr buffer*/\r
-            count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);\r
-            if (count != 0U)\r
-            {\r
-              USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);\r
-            }\r
-          }\r
-          /* free EP OUT Buffer */\r
-          PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);\r
-        }\r
-        /*multi-packet on the NON control OUT endpoint*/\r
-        ep->xfer_count += count;\r
-        ep->xfer_buff += count;\r
-\r
-        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))\r
-        {\r
-          /* RX COMPLETE */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-          hpcd->DataOutStageCallback(hpcd, ep->num);\r
-#else\r
-          HAL_PCD_DataOutStageCallback(hpcd, ep->num);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-        }\r
-        else\r
-        {\r
-          (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);\r
-        }\r
-\r
-      } /* if((wEPVal & EP_CTR_RX) */\r
-\r
-      if ((wEPVal & USB_EP_CTR_TX) != 0U)\r
-      {\r
-        ep = &hpcd->IN_ep[epindex];\r
-\r
-        /* clear int flag */\r
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);\r
-\r
-        /*multi-packet on the NON control IN endpoint*/\r
-        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);\r
-        ep->xfer_buff += ep->xfer_count;\r
-\r
-        /* Zero Length Packet? */\r
-        if (ep->xfer_len == 0U)\r
-        {\r
-          /* TX COMPLETE */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-          hpcd->DataInStageCallback(hpcd, ep->num);\r
-#else\r
-          HAL_PCD_DataInStageCallback(hpcd, ep->num);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-        }\r
-        else\r
-        {\r
-          (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);\r
-        }\r
-      }\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* defined (USB) || defined (USB_OTG_FS) */\r
-#endif /* HAL_PCD_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
deleted file mode 100644 (file)
index b4a4842..0000000
+++ /dev/null
@@ -1,566 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pcd_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   PCD Extended HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the USB Peripheral Controller:\r
-  *           + Extended features functions\r
-  *\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PCDEx PCDEx\r
-  * @brief PCD Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_PCD_MODULE_ENABLED\r
-\r
-#if defined (USB) || defined (USB_OTG_FS)\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private constants ---------------------------------------------------------*/\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r
-  * @brief    PCDEx control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                 ##### Extended features functions #####\r
- ===============================================================================\r
-    [..]  This section provides functions allowing to:\r
-      (+) Update FIFO configuration\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-#if defined (USB_OTG_FS)\r
-/**\r
-  * @brief  Set Tx FIFO\r
-  * @param  hpcd PCD handle\r
-  * @param  fifo The number of Tx fifo\r
-  * @param  size Fifo size\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)\r
-{\r
-  uint8_t i;\r
-  uint32_t Tx_Offset;\r
-\r
-  /*  TXn min size = 16 words. (n  : Transmit FIFO index)\r
-      When a TxFIFO is not used, the Configuration should be as follows:\r
-          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r
-         --> Txm can use the space allocated for Txn.\r
-         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r
-         --> Txn should be configured with the minimum space of 16 words\r
-     The FIFO is used optimally when used TxFIFOs are allocated in the top\r
-         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.\r
-     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */\r
-\r
-  Tx_Offset = hpcd->Instance->GRXFSIZ;\r
-\r
-  if (fifo == 0U)\r
-  {\r
-    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;\r
-  }\r
-  else\r
-  {\r
-    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;\r
-    for (i = 0U; i < (fifo - 1U); i++)\r
-    {\r
-      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);\r
-    }\r
-\r
-    /* Multiply Tx_Size by 2 to get higher performance */\r
-    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Set Rx FIFO\r
-  * @param  hpcd PCD handle\r
-  * @param  size Size of Rx fifo\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)\r
-{\r
-  hpcd->Instance->GRXFSIZ = size;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Activate LPM feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-\r
-  hpcd->lpm_active = 1U;\r
-  hpcd->LPM_State = LPM_L0;\r
-  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;\r
-  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Deactivate LPM feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-\r
-  hpcd->lpm_active = 0U;\r
-  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;\r
-  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Handle BatteryCharging Process.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Enable DCD : Data Contact Detect */\r
-  USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;\r
-\r
-  /* Wait Detect flag or a timeout is happen*/\r
-  while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)\r
-  {\r
-    /* Check for the Timeout */\r
-    if ((HAL_GetTick() - tickstart) > 1000U)\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);\r
-#else\r
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-      return;\r
-    }\r
-  }\r
-\r
-  /* Right response got */\r
-  HAL_Delay(200U);\r
-\r
-  /* Check Detect flag*/\r
-  if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)\r
-  {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
-#else\r
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /*Primary detection: checks if connected to Standard Downstream Port\r
-  (without charging capability) */\r
-  USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;\r
-  HAL_Delay(50U);\r
-  USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;\r
-  HAL_Delay(50U);\r
-\r
-  if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)\r
-  {\r
-    /* Case of Standard Downstream Port */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
-#else\r
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-    /* start secondary detection to check connection to Charging Downstream\r
-    Port or Dedicated Charging Port */\r
-    USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;\r
-    HAL_Delay(50U);\r
-    USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;\r
-    HAL_Delay(50U);\r
-\r
-    if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)\r
-    {\r
-      /* case Dedicated Charging Port  */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
-#else\r
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-    else\r
-    {\r
-      /* case Charging Downstream Port  */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
-#else\r
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-\r
-  /* Battery Charging capability discovery finished */\r
-  (void)HAL_PCDEx_DeActivateBCD(hpcd);\r
-\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
-#else\r
-  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  Activate BatteryCharging feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);\r
-\r
-  /* Power Down USB tranceiver  */\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
-\r
-  /* Enable Battery charging */\r
-  USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;\r
-\r
-  hpcd->battery_charging_active = 1U;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Deactivate BatteryCharging feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
-\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);\r
-\r
-  /* Disable Battery charging */\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);\r
-\r
-  hpcd->battery_charging_active = 0U;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-#endif /* defined (USB_OTG_FS) */\r
-#if defined (USB)\r
-/**\r
-  * @brief  Configure PMA for EP\r
-  * @param  hpcd  Device instance\r
-  * @param  ep_addr endpoint address\r
-  * @param  ep_kind endpoint Kind\r
-  *                  USB_SNG_BUF: Single Buffer used\r
-  *                  USB_DBL_BUF: Double Buffer used\r
-  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint\r
-  *                   this parameter is 16-bit value providing the address\r
-  *                   in PMA allocated to endpoint.\r
-  *                   In case of double buffer endpoint this parameter\r
-  *                   is a 32-bit value providing the endpoint buffer 0 address\r
-  *                   in the LSB part of 32-bit value and endpoint buffer 1 address\r
-  *                   in the MSB part of 32-bit value.\r
-  * @retval HAL status\r
-  */\r
-\r
-HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,\r
-                                       uint16_t ep_addr,\r
-                                       uint16_t ep_kind,\r
-                                       uint32_t pmaadress)\r
-{\r
-  PCD_EPTypeDef *ep;\r
-\r
-  /* initialize ep structure*/\r
-  if ((0x80U & ep_addr) == 0x80U)\r
-  {\r
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\r
-  }\r
-  else\r
-  {\r
-    ep = &hpcd->OUT_ep[ep_addr];\r
-  }\r
-\r
-  /* Here we check if the endpoint is single or double Buffer*/\r
-  if (ep_kind == PCD_SNG_BUF)\r
-  {\r
-    /* Single Buffer */\r
-    ep->doublebuffer = 0U;\r
-    /* Configure the PMA */\r
-    ep->pmaadress = (uint16_t)pmaadress;\r
-  }\r
-  else /* USB_DBL_BUF */\r
-  {\r
-    /* Double Buffer Endpoint */\r
-    ep->doublebuffer = 1U;\r
-    /* Configure the PMA */\r
-    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);\r
-    ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Activate BatteryCharging feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_TypeDef *USBx = hpcd->Instance;\r
-  hpcd->battery_charging_active = 1U;\r
-\r
-  /* Enable DCD : Data Contact Detect */\r
-  USBx->BCDR &= ~(USB_BCDR_PDEN);\r
-  USBx->BCDR &= ~(USB_BCDR_SDEN);\r
-  USBx->BCDR |= USB_BCDR_DCDEN;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Deactivate BatteryCharging feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_TypeDef *USBx = hpcd->Instance;\r
-  hpcd->battery_charging_active = 0U;\r
-\r
-  USBx->BCDR &= ~(USB_BCDR_BCDEN);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handle BatteryCharging Process.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_TypeDef *USBx = hpcd->Instance;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Wait Detect flag or a timeout is happen*/\r
-  while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)\r
-  {\r
-    /* Check for the Timeout */\r
-    if ((HAL_GetTick() - tickstart) > 1000U)\r
-    {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);\r
-#else\r
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-\r
-      return;\r
-    }\r
-  }\r
-\r
-  HAL_Delay(200U);\r
-\r
-  /* Data Pin Contact ? Check Detect flag */\r
-  if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)\r
-  {\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
-#else\r
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-  }\r
-  /* Primary detection: checks if connected to Standard Downstream Port\r
-  (without charging capability) */\r
-  USBx->BCDR &= ~(USB_BCDR_DCDEN);\r
-  HAL_Delay(50U);\r
-  USBx->BCDR |= (USB_BCDR_PDEN);\r
-  HAL_Delay(50U);\r
-\r
-  /* If Charger detect ? */\r
-  if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)\r
-  {\r
-    /* Start secondary detection to check connection to Charging Downstream\r
-    Port or Dedicated Charging Port */\r
-    USBx->BCDR &= ~(USB_BCDR_PDEN);\r
-    HAL_Delay(50U);\r
-    USBx->BCDR |= (USB_BCDR_SDEN);\r
-    HAL_Delay(50U);\r
-\r
-    /* If CDP ? */\r
-    if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)\r
-    {\r
-      /* Dedicated Downstream Port DCP */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
-#else\r
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-    else\r
-    {\r
-      /* Charging Downstream Port CDP */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
-#else\r
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  else /* NO */\r
-  {\r
-    /* Standard Downstream Port */\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
-#else\r
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Battery Charging capability discovery finished Start Enumeration */\r
-  (void)HAL_PCDEx_DeActivateBCD(hpcd);\r
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\r
-  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
-#else\r
-  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\r
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Activate LPM feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r
-{\r
-\r
-  USB_TypeDef *USBx = hpcd->Instance;\r
-  hpcd->lpm_active = 1U;\r
-  hpcd->LPM_State = LPM_L0;\r
-\r
-  USBx->LPMCSR |= USB_LPMCSR_LMPEN;\r
-  USBx->LPMCSR |= USB_LPMCSR_LPMACK;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Deactivate LPM feature.\r
-  * @param  hpcd PCD handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r
-{\r
-  USB_TypeDef *USBx = hpcd->Instance;\r
-\r
-  hpcd->lpm_active = 0U;\r
-\r
-  USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);\r
-  USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @brief  Send LPM message to user layer callback.\r
-  * @param  hpcd PCD handle\r
-  * @param  msg LPM message\r
-  * @retval HAL status\r
-  */\r
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-  UNUSED(msg);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCDEx_LPM_Callback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Send BatteryCharging message to user layer callback.\r
-  * @param  hpcd PCD handle\r
-  * @param  msg LPM message\r
-  * @retval HAL status\r
-  */\r
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hpcd);\r
-  UNUSED(msg);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_PCDEx_BCD_Callback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* defined (USB) || defined (USB_OTG_FS) */\r
-#endif /* HAL_PCD_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
deleted file mode 100644 (file)
index ba44650..0000000
+++ /dev/null
@@ -1,661 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pwr.c\r
-  * @author  MCD Application Team\r
-  * @brief   PWR HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Power Controller (PWR) peripheral:\r
-  *           + Initialization/de-initialization functions\r
-  *           + Peripheral Control functions\r
-  *\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PWR PWR\r
-  * @brief PWR HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_PWR_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Private_Defines PWR Private Defines\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
-  * @{\r
-  */\r
-#define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */\r
-#define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */\r
-#define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */\r
-#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  *  @brief    Initialization and de-initialization functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-              ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
-    [..]\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_DeInit(void)\r
-{\r
-  __HAL_RCC_PWR_FORCE_RESET();\r
-  __HAL_RCC_PWR_RELEASE_RESET();\r
-}\r
-\r
-/**\r
-  * @brief Enable access to the backup domain\r
-  *        (RTC registers, RTC backup data registers).\r
-  * @note  After reset, the backup domain is protected against\r
-  *        possible unwanted write accesses.\r
-  * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.\r
-  *        In order to set or modify the RTC clock, the backup domain access must be\r
-  *        disabled.\r
-  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the\r
-  *        back-up domain.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnableBkUpAccess(void)\r
-{\r
-  SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
-}\r
-\r
-/**\r
-  * @brief Disable access to the backup domain\r
-  *        (RTC registers, RTC backup data registers).\r
-  * @retval None\r
-  */\r
-void HAL_PWR_DisableBkUpAccess(void)\r
-{\r
-  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
-}\r
-\r
-\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-\r
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
-  *  @brief Low Power modes configuration functions\r
-  *\r
-@verbatim\r
-\r
- ===============================================================================\r
-                 ##### Peripheral Control functions #####\r
- ===============================================================================\r
-\r
-     [..]\r
-     *** PVD configuration ***\r
-    =========================\r
-    [..]\r
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a\r
-          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).\r
-\r
-      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower\r
-          than the PVD threshold. This event is internally connected to the EXTI\r
-          line16 and can generate an interrupt if enabled. This is done through\r
-          __HAL_PVD_EXTI_ENABLE_IT() macro.\r
-      (+) The PVD is stopped in Standby mode.\r
-\r
-\r
-    *** WakeUp pin configuration ***\r
-    ================================\r
-    [..]\r
-      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.\r
-          The polarity of these pins can be set to configure event detection on high\r
-          level (rising edge) or low level (falling edge).\r
-\r
-\r
-\r
-    *** Low Power modes configuration ***\r
-    =====================================\r
-    [..]\r
-      The devices feature 8 low-power modes:\r
-      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.\r
-      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.\r
-      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.\r
-      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.\r
-      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.\r
-      (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.\r
-      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.\r
-      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.\r
-      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.\r
-\r
-\r
-   *** Low-power run mode ***\r
-   ==========================\r
-    [..]\r
-      (+) Entry: (from main run mode)\r
-        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.\r
-\r
-      (+) Exit:\r
-        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only\r
-             then can the system clock frequency be increased above 2 MHz.\r
-\r
-\r
-   *** Sleep mode / Low-power sleep mode ***\r
-   =========================================\r
-    [..]\r
-      (+) Entry:\r
-          The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API\r
-          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.\r
-          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).\r
-          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).\r
-          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.\r
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
-\r
-      (+) WFI Exit:\r
-        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt\r
-             controller (NVIC) or any wake-up event.\r
-\r
-      (+) WFE Exit:\r
-        (++) Any wake-up event such as an EXTI line configured in event mode.\r
-\r
-         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,\r
-             the MCU is in Low-power Run mode.\r
-\r
-   *** Stop 0, Stop 1 and Stop 2 modes ***\r
-   ===============================\r
-    [..]\r
-      (+) Entry:\r
-          The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:\r
-          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().\r
-          (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.\r
-      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):\r
-          (++) PWR_MAINREGULATOR_ON\r
-          (++) PWR_LOWPOWERREGULATOR_ON\r
-      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):\r
-          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction\r
-          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction\r
-\r
-      (+) WFI Exit:\r
-          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.\r
-          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts\r
-               when programmed in wakeup mode.\r
-      (+) WFE Exit:\r
-          (++) Any EXTI Line (Internal or External) configured in Event mode.\r
-\r
-       [..]\r
-          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode\r
-          depending on the LPR bit setting.\r
-          When exiting Stop 2 mode, the MCU is in Run mode.\r
-\r
-   *** Standby mode ***\r
-   ====================\r
-     [..]\r
-      The Standby mode offers two options:\r
-      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).\r
-        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers\r
-        and Standby circuitry.\r
-      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).\r
-        SRAM and register contents are lost except for the RTC registers, RTC backup registers\r
-        and Standby circuitry.\r
-\r
-      (++) Entry:\r
-          (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.\r
-                SRAM1 and register contents are lost except for registers in the Backup domain and\r
-                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.\r
-                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API\r
-                to set RRS bit.\r
-\r
-      (++) Exit:\r
-          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,\r
-                external reset in NRST pin, IWDG reset.\r
-\r
-      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.\r
-\r
-\r
-    *** Shutdown mode ***\r
-   ======================\r
-     [..]\r
-      In Shutdown mode,\r
-        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.\r
-        SRAM and registers contents are lost except for backup domain registers.\r
-\r
-      (+) Entry:\r
-          The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.\r
-\r
-      (+) Exit:\r
-          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,\r
-               external reset in NRST pin.\r
-\r
-         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.\r
-\r
-\r
-   *** Auto-wakeup (AWU) from low-power mode ***\r
-   =============================================\r
-    [..]\r
-      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC\r
-      Wakeup event, a tamper event or a time-stamp event, without depending on\r
-      an external interrupt (Auto-wakeup mode).\r
-\r
-      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes\r
-\r
-\r
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to\r
-             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
-\r
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it\r
-             is necessary to configure the RTC to detect the tamper or time stamp event using the\r
-             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
-\r
-        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
-              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-\r
-\r
-/**\r
-  * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).\r
-  * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD\r
-  *        configuration information.\r
-  * @note Refer to the electrical characteristics of your device datasheet for\r
-  *         more details about the voltage thresholds corresponding to each\r
-  *         detection level.\r
-  * @retval None\r
-  */\r
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
-\r
-  /* Set PLS bits according to PVDLevel value */\r
-  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);\r
-\r
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
-  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
-  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
-\r
-  /* Configure interrupt mode */\r
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
-  {\r
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
-  }\r
-\r
-  /* Configure event mode */\r
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
-  {\r
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
-  }\r
-\r
-  /* Configure the edge */\r
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
-  {\r
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
-  }\r
-\r
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
-  {\r
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enable the Power Voltage Detector (PVD).\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnablePVD(void)\r
-{\r
-  SET_BIT(PWR->CR2, PWR_CR2_PVDE);\r
-}\r
-\r
-/**\r
-  * @brief Disable the Power Voltage Detector (PVD).\r
-  * @retval None\r
-  */\r
-void HAL_PWR_DisablePVD(void)\r
-{\r
-  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);\r
-}\r
-\r
-\r
-\r
-\r
-/**\r
-  * @brief Enable the WakeUp PINx functionality.\r
-  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r
-  *         This parameter can be one of the following legacy values which set the default polarity\r
-  *         i.e. detection on high level (rising edge):\r
-  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5\r
-  *\r
-  *         or one of the following value where the user can explicitly specify the enabled pin and\r
-  *         the chosen polarity:\r
-  *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW\r
-  *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW\r
-  *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW\r
-  *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
-  *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW\r
-  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
-{\r
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
-\r
-  /* Specifies the Wake-Up pin polarity for the event detection\r
-    (rising or falling edge) */\r
-  MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));\r
-\r
-  /* Enable wake-up pin */\r
-  SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));\r
-\r
-\r
-}\r
-\r
-/**\r
-  * @brief Disable the WakeUp PINx functionality.\r
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5\r
-  * @retval None\r
-  */\r
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
-{\r
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
-\r
-  CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enter Sleep or Low-power Sleep mode.\r
-  * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.\r
-  * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)\r
-  *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)\r
-  * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet\r
-  *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set\r
-  *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the\r
-  *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.\r
-  *        Additionally, the clock frequency must be reduced below 2 MHz.\r
-  *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must\r
-  *        be done before calling HAL_PWR_EnterSLEEPMode() API.\r
-  * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in\r
-  *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.\r
-  * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.\r
-  *           This parameter can be one of the following values:\r
-  *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction\r
-  *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction\r
-  * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as\r
-  *        the interrupt wake up source.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_PWR_REGULATOR(Regulator));\r
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
-\r
-  /* Set Regulator parameter */\r
-  if (Regulator == PWR_MAINREGULATOR_ON)\r
-  {\r
-    /* If in low-power run mode at this point, exit it */\r
-    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))\r
-    {\r
-      if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)\r
-      {\r
-        return ;\r
-      }\r
-    }\r
-    /* Regulator now in main mode. */\r
-  }\r
-  else\r
-  {\r
-    /* If in run mode, first move to low-power run mode.\r
-       The system clock frequency must be below 2 MHz at this point. */\r
-    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)\r
-    {\r
-      HAL_PWREx_EnableLowPowerRunMode();\r
-    }\r
-  }\r
-\r
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
-  /* Select SLEEP mode entry -------------------------------------------------*/\r
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
-  {\r
-    /* Request Wait For Interrupt */\r
-    __WFI();\r
-  }\r
-  else\r
-  {\r
-    /* Request Wait For Event */\r
-    __SEV();\r
-    __WFE();\r
-    __WFE();\r
-  }\r
-\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enter Stop mode\r
-  * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running\r
-  *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.\r
-  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.\r
-  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
-  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
-  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
-  *        only to the peripheral requesting it.\r
-  *        SRAM1, SRAM2 and register contents are preserved.\r
-  *        The BOR is available.\r
-  *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).\r
-  * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,\r
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
-  * @note  When the voltage regulator operates in low power mode (Stop 1), an additional\r
-  *         startup delay is incurred when waking up.\r
-  *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption\r
-  *         is higher although the startup time is reduced.\r
-  * @param Regulator: Specifies the regulator state in Stop mode.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)\r
-  *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)\r
-  * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.\r
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_PWR_REGULATOR(Regulator));\r
-\r
-  if(Regulator == PWR_LOWPOWERREGULATOR_ON)\r
-  {\r
-    HAL_PWREx_EnterSTOP1Mode(STOPEntry);\r
-  }\r
-  else\r
-  {\r
-    HAL_PWREx_EnterSTOP0Mode(STOPEntry);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Enter Standby mode.\r
-  * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched\r
-  *        off. The voltage regulator is disabled, except when SRAM2 content is preserved\r
-  *        in which case the regulator is in low-power mode.\r
-  *        SRAM1 and register contents are lost except for registers in the Backup domain and\r
-  *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.\r
-  *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API\r
-  *        to set RRS bit.\r
-  *        The BOR is available.\r
-  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.\r
-  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and\r
-  *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the\r
-  *        same.\r
-  *        These states are effective in Standby mode only if APC bit is set through\r
-  *        HAL_PWREx_EnablePullUpPullDownConfig() API.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnterSTANDBYMode(void)\r
-{\r
-  /* Set Stand-by mode */\r
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);\r
-\r
-  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
-/* This option is used to ensure that store operations are completed */\r
-#if defined ( __CC_ARM)\r
-  __force_stores();\r
-#endif\r
-  /* Request Wait For Interrupt */\r
-  __WFI();\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.\r
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
-  *       re-enters SLEEP mode when an interruption handling is over.\r
-  *       Setting this bit is useful when the processor is expected to run only on\r
-  *       interruptions handling.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnableSleepOnExit(void)\r
-{\r
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.\r
-  * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
-  *       re-enters SLEEP mode when an interruption handling is over.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_DisableSleepOnExit(void)\r
-{\r
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Enable CORTEX M4 SEVONPEND bit.\r
-  * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes\r
-  *       WFE to wake up when an interrupt moves from inactive to pended.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_EnableSEVOnPend(void)\r
-{\r
-  /* Set SEVONPEND bit of Cortex System Control Register */\r
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable CORTEX M4 SEVONPEND bit.\r
-  * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes\r
-  *       WFE to wake up when an interrupt moves from inactive to pended.\r
-  * @retval None\r
-  */\r
-void HAL_PWR_DisableSEVOnPend(void)\r
-{\r
-  /* Clear SEVONPEND bit of Cortex System Control Register */\r
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
-}\r
-\r
-\r
-\r
-\r
-\r
-/**\r
-  * @brief PWR PVD interrupt callback\r
-  * @retval None\r
-  */\r
-__weak void HAL_PWR_PVDCallback(void)\r
-{\r
-  /* NOTE : This function should not be modified; when the callback is needed,\r
-            the HAL_PWR_PVDCallback can be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_PWR_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
deleted file mode 100644 (file)
index 9adf448..0000000
+++ /dev/null
@@ -1,1446 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_pwr_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   Extended PWR HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Power Controller (PWR) peripheral:\r
-  *           + Extended Initialization and de-initialization functions\r
-  *           + Extended Peripheral Control functions\r
-  *\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PWREx PWREx\r
-  * @brief PWR Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_PWR_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)\r
-#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */\r
-#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
-#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */\r
-#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)\r
-#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x00000003) /* PH0/PH1 */\r
-#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000FFFF) /* PH0..PH15 */\r
-#endif\r
-\r
-#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define PWR_PORTI_AVAILABLE_PINS   ((uint32_t)0x00000FFF) /* PI0..PI11 */\r
-#endif\r
-\r
-/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask\r
-  * @{\r
-  */\r
-#define PVM_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVM threshold crossing */\r
-#define PVM_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVM threshold crossing        */\r
-#define PVM_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVM trigger                 */\r
-#define PVM_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVM trigger                */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value\r
-  * @{\r
-  */\r
-#define PWR_FLAG_SETTING_DELAY_US                      50UL   /*!< Time out value for REGLPF and VOSF flags setting */\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions\r
-  *  @brief   Extended Peripheral Control functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-              ##### Extended Peripheral Initialization and de-initialization functions #####\r
- ===============================================================================\r
-    [..]\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-\r
-/**\r
-  * @brief Return Voltage Scaling Range.\r
-  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2\r
-  *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)\r
-  */\r
-uint32_t HAL_PWREx_GetVoltageRange(void)\r
-{\r
-#if defined(PWR_CR5_R1MODE)\r
-    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
-    {\r
-      return PWR_REGULATOR_VOLTAGE_SCALE2;\r
-    }\r
-    else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)\r
-    {\r
-      /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */\r
-      return PWR_REGULATOR_VOLTAGE_SCALE1;\r
-    }\r
-    else\r
-    {\r
-      return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;\r
-    }\r
-#else\r
-  return  (PWR->CR1 & PWR_CR1_VOS);\r
-#endif\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Configure the main internal regulator output voltage.\r
-  * @param  VoltageScaling: specifies the regulator output voltage to achieve\r
-  *         a tradeoff between performance and power consumption.\r
-  *          This parameter can be one of the following values:\r
-  @if STM32L4S9xx\r
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,\r
-  *                                                typical output voltage at 1.2 V,\r
-  *                                                system frequency up to 120 MHz.\r
-  @endif\r
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,\r
-  *                                                typical output voltage at 1.2 V,\r
-  *                                                system frequency up to 80 MHz.\r
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,\r
-  *                                                typical output voltage at 1.0 V,\r
-  *                                                system frequency up to 26 MHz.\r
-  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to\r
-  *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.\r
-  *        When moving from Range 2 to Range 1, the system frequency can be increased to\r
-  *        a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For\r
-  *        some devices, the system frequency can be increased up to 120 MHz.\r
-  * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be\r
-  *        cleared before returning the status. If the flag is not cleared within\r
-  *        50 microseconds, HAL_TIMEOUT status is reported.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r
-{\r
-  uint32_t wait_loop_index;\r
-\r
-  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));\r
-\r
-#if defined(PWR_CR5_R1MODE)\r
-  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)\r
-  {\r
-    /* If current range is range 2 */\r
-    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
-    {\r
-      /* Make sure Range 1 Boost is enabled */\r
-      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
-\r
-      /* Set Range 1 */\r
-      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
-\r
-      /* Wait until VOSF is cleared */\r
-      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;\r
-      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
-      {\r
-        wait_loop_index--;\r
-      }\r
-      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
-      {\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-    /* If current range is range 1 normal or boost mode */\r
-    else\r
-    {\r
-      /* Enable Range 1 Boost (no issue if bit already reset) */\r
-      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
-    }\r
-  }\r
-  else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)\r
-  {\r
-    /* If current range is range 2 */\r
-    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
-    {\r
-      /* Make sure Range 1 Boost is disabled */\r
-      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
-\r
-      /* Set Range 1 */\r
-      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
-\r
-      /* Wait until VOSF is cleared */\r
-      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;\r
-      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
-      {\r
-        wait_loop_index--;\r
-      }\r
-      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
-      {\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-     /* If current range is range 1 normal or boost mode */\r
-    else\r
-    {\r
-      /* Disable Range 1 Boost (no issue if bit already set) */\r
-      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Set Range 2 */\r
-    MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);\r
-    /* No need to wait for VOSF to be cleared for this transition */\r
-    /* PWR_CR5_R1MODE bit setting has no effect in Range 2        */\r
-  }\r
-\r
-#else\r
-\r
-  /* If Set Range 1 */\r
-  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)\r
-  {\r
-    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)\r
-    {\r
-      /* Set Range 1 */\r
-      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
-\r
-      /* Wait until VOSF is cleared */\r
-      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;\r
-      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
-      {\r
-        wait_loop_index--;\r
-      }\r
-      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
-      {\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-  }\r
-  else\r
-  {\r
-    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)\r
-    {\r
-      /* Set Range 2 */\r
-      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);\r
-      /* No need to wait for VOSF to be cleared for this transition */\r
-    }\r
-  }\r
-#endif\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enable battery charging.\r
-  *        When VDD is present, charge the external battery on VBAT thru an internal resistor.\r
-  * @param  ResistorSelection: specifies the resistor impedance.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor\r
-  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)\r
-{\r
-  assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));\r
-\r
-  /* Specify resistor selection */\r
-  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);\r
-\r
-  /* Enable battery charging */\r
-  SET_BIT(PWR->CR4, PWR_CR4_VBE);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable battery charging.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableBatteryCharging(void)\r
-{\r
-  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);\r
-}\r
-\r
-\r
-#if defined(PWR_CR2_USV)\r
-/**\r
-  * @brief Enable VDDUSB supply.\r
-  * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableVddUSB(void)\r
-{\r
-  SET_BIT(PWR->CR2, PWR_CR2_USV);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable VDDUSB supply.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableVddUSB(void)\r
-{\r
-  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);\r
-}\r
-#endif /* PWR_CR2_USV */\r
-\r
-#if defined(PWR_CR2_IOSV)\r
-/**\r
-  * @brief Enable VDDIO2 supply.\r
-  * @note  Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableVddIO2(void)\r
-{\r
-  SET_BIT(PWR->CR2, PWR_CR2_IOSV);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable VDDIO2 supply.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableVddIO2(void)\r
-{\r
-  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);\r
-}\r
-#endif /* PWR_CR2_IOSV */\r
-\r
-\r
-/**\r
-  * @brief Enable Internal Wake-up Line.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableInternalWakeUpLine(void)\r
-{\r
-  SET_BIT(PWR->CR3, PWR_CR3_EIWF);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable Internal Wake-up Line.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableInternalWakeUpLine(void)\r
-{\r
-  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Enable GPIO pull-up state in Standby and Shutdown modes.\r
-  * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in\r
-  *        pull-up state in Standby and Shutdown modes.\r
-  * @note  This state is effective in Standby and Shutdown modes only if APC bit\r
-  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.\r
-  * @note  The configuration is lost when exiting the Shutdown mode due to the\r
-  *        power-on reset, maintained when exiting the Standby mode.\r
-  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding\r
-  *        PDy bit of PWR_PDCRx register is cleared unless it is reserved.\r
-  * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input\r
-  *        parameter at the same time are set.\r
-  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H\r
-  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
-  * @param  GPIONumber: Specify the I/O pins numbers.\r
-  *         This parameter can be one of the following values:\r
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
-  *         I/O pins are available) or the logical OR of several of them to set\r
-  *         several bits for a given port in a single API call.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  assert_param(IS_PWR_GPIO(GPIO));\r
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
-\r
-  switch (GPIO)\r
-  {\r
-    case PWR_GPIO_A:\r
-       SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
-       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
-       break;\r
-    case PWR_GPIO_B:\r
-       SET_BIT(PWR->PUCRB, GPIONumber);\r
-       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
-       break;\r
-    case PWR_GPIO_C:\r
-       SET_BIT(PWR->PUCRC, GPIONumber);\r
-       CLEAR_BIT(PWR->PDCRC, GPIONumber);\r
-       break;\r
-#if defined(GPIOD)\r
-    case PWR_GPIO_D:\r
-       SET_BIT(PWR->PUCRD, GPIONumber);\r
-       CLEAR_BIT(PWR->PDCRD, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOE)\r
-    case PWR_GPIO_E:\r
-       SET_BIT(PWR->PUCRE, GPIONumber);\r
-       CLEAR_BIT(PWR->PDCRE, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOF)\r
-    case PWR_GPIO_F:\r
-       SET_BIT(PWR->PUCRF, GPIONumber);\r
-       CLEAR_BIT(PWR->PDCRF, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOG)\r
-    case PWR_GPIO_G:\r
-       SET_BIT(PWR->PUCRG, GPIONumber);\r
-       CLEAR_BIT(PWR->PDCRG, GPIONumber);\r
-       break;\r
-#endif\r
-    case PWR_GPIO_H:\r
-       SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
-#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
-       CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
-#else\r
-       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
-#endif\r
-       break;\r
-#if defined(GPIOI)\r
-    case PWR_GPIO_I:\r
-       SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
-       CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
-       break;\r
-#endif\r
-    default:\r
-      status = HAL_ERROR;\r
-      break;\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.\r
-  * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O\r
-  *        in pull-up state in Standby and Shutdown modes.\r
-  * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input\r
-  *        parameter at the same time are reset.\r
-  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H\r
-  *          (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
-  * @param  GPIONumber: Specify the I/O pins numbers.\r
-  *         This parameter can be one of the following values:\r
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
-  *         I/O pins are available) or the logical OR of several of them to reset\r
-  *         several bits for a given port in a single API call.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  assert_param(IS_PWR_GPIO(GPIO));\r
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
-\r
-  switch (GPIO)\r
-  {\r
-    case PWR_GPIO_A:\r
-       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
-       break;\r
-    case PWR_GPIO_B:\r
-       CLEAR_BIT(PWR->PUCRB, GPIONumber);\r
-       break;\r
-    case PWR_GPIO_C:\r
-       CLEAR_BIT(PWR->PUCRC, GPIONumber);\r
-       break;\r
-#if defined(GPIOD)\r
-    case PWR_GPIO_D:\r
-       CLEAR_BIT(PWR->PUCRD, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOE)\r
-    case PWR_GPIO_E:\r
-       CLEAR_BIT(PWR->PUCRE, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOF)\r
-    case PWR_GPIO_F:\r
-       CLEAR_BIT(PWR->PUCRF, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOG)\r
-    case PWR_GPIO_G:\r
-       CLEAR_BIT(PWR->PUCRG, GPIONumber);\r
-       break;\r
-#endif\r
-    case PWR_GPIO_H:\r
-       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
-       break;\r
-#if defined(GPIOI)\r
-    case PWR_GPIO_I:\r
-       CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
-       break;\r
-#endif\r
-    default:\r
-       status = HAL_ERROR;\r
-       break;\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Enable GPIO pull-down state in Standby and Shutdown modes.\r
-  * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in\r
-  *        pull-down state in Standby and Shutdown modes.\r
-  * @note  This state is effective in Standby and Shutdown modes only if APC bit\r
-  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.\r
-  * @note  The configuration is lost when exiting the Shutdown mode due to the\r
-  *        power-on reset, maintained when exiting the Standby mode.\r
-  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding\r
-  *        PUy bit of PWR_PUCRx register is cleared unless it is reserved.\r
-  * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input\r
-  *        parameter at the same time are set.\r
-  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H\r
-  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
-  * @param  GPIONumber: Specify the I/O pins numbers.\r
-  *         This parameter can be one of the following values:\r
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
-  *         I/O pins are available) or the logical OR of several of them to set\r
-  *         several bits for a given port in a single API call.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  assert_param(IS_PWR_GPIO(GPIO));\r
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
-\r
-  switch (GPIO)\r
-  {\r
-    case PWR_GPIO_A:\r
-       SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
-       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
-       break;\r
-    case PWR_GPIO_B:\r
-       SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
-       CLEAR_BIT(PWR->PUCRB, GPIONumber);\r
-       break;\r
-    case PWR_GPIO_C:\r
-       SET_BIT(PWR->PDCRC, GPIONumber);\r
-       CLEAR_BIT(PWR->PUCRC, GPIONumber);\r
-       break;\r
-#if defined(GPIOD)\r
-    case PWR_GPIO_D:\r
-       SET_BIT(PWR->PDCRD, GPIONumber);\r
-       CLEAR_BIT(PWR->PUCRD, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOE)\r
-    case PWR_GPIO_E:\r
-       SET_BIT(PWR->PDCRE, GPIONumber);\r
-       CLEAR_BIT(PWR->PUCRE, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOF)\r
-    case PWR_GPIO_F:\r
-       SET_BIT(PWR->PDCRF, GPIONumber);\r
-       CLEAR_BIT(PWR->PUCRF, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOG)\r
-    case PWR_GPIO_G:\r
-       SET_BIT(PWR->PDCRG, GPIONumber);\r
-       CLEAR_BIT(PWR->PUCRG, GPIONumber);\r
-       break;\r
-#endif\r
-    case PWR_GPIO_H:\r
-#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
-       SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
-#else\r
-       SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
-#endif\r
-       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
-       break;\r
-#if defined(GPIOI)\r
-    case PWR_GPIO_I:\r
-       SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
-       CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
-       break;\r
-#endif\r
-    default:\r
-      status = HAL_ERROR;\r
-      break;\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable GPIO pull-down state in Standby and Shutdown modes.\r
-  * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O\r
-  *        in pull-down state in Standby and Shutdown modes.\r
-  * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input\r
-  *        parameter at the same time are reset.\r
-  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H\r
-  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
-  * @param  GPIONumber: Specify the I/O pins numbers.\r
-  *         This parameter can be one of the following values:\r
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
-  *         I/O pins are available) or the logical OR of several of them to reset\r
-  *         several bits for a given port in a single API call.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  assert_param(IS_PWR_GPIO(GPIO));\r
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
-\r
-  switch (GPIO)\r
-  {\r
-    case PWR_GPIO_A:\r
-       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
-       break;\r
-    case PWR_GPIO_B:\r
-       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
-       break;\r
-    case PWR_GPIO_C:\r
-       CLEAR_BIT(PWR->PDCRC, GPIONumber);\r
-       break;\r
-#if defined(GPIOD)\r
-    case PWR_GPIO_D:\r
-       CLEAR_BIT(PWR->PDCRD, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOE)\r
-    case PWR_GPIO_E:\r
-       CLEAR_BIT(PWR->PDCRE, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOF)\r
-    case PWR_GPIO_F:\r
-       CLEAR_BIT(PWR->PDCRF, GPIONumber);\r
-       break;\r
-#endif\r
-#if defined(GPIOG)\r
-    case PWR_GPIO_G:\r
-       CLEAR_BIT(PWR->PDCRG, GPIONumber);\r
-       break;\r
-#endif\r
-    case PWR_GPIO_H:\r
-#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
-       CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
-#else\r
-       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
-#endif\r
-       break;\r
-#if defined(GPIOI)\r
-    case PWR_GPIO_I:\r
-       CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
-       break;\r
-#endif\r
-    default:\r
-      status = HAL_ERROR;\r
-      break;\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Enable pull-up and pull-down configuration.\r
-  * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in\r
-  *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.\r
-  * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding\r
-  *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).\r
-  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there\r
-  *        is no conflict when setting PUy or PDy bit.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnablePullUpPullDownConfig(void)\r
-{\r
-  SET_BIT(PWR->CR3, PWR_CR3_APC);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable pull-up and pull-down configuration.\r
-  * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in\r
-  *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisablePullUpPullDownConfig(void)\r
-{\r
-  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Enable SRAM2 content retention in Standby mode.\r
-  * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in\r
-  *         Standby mode and its content is kept.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableSRAM2ContentRetention(void)\r
-{\r
-  SET_BIT(PWR->CR3, PWR_CR3_RRS);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable SRAM2 content retention in Standby mode.\r
-  * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode\r
-  *        and its content is lost.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableSRAM2ContentRetention(void)\r
-{\r
-  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);\r
-}\r
-\r
-\r
-#if defined(PWR_CR3_ENULP)\r
-/**\r
-  * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.\r
-  * @note  All the other modes are not affected by this bit.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableBORPVD_ULP(void)\r
-{\r
-  SET_BIT(PWR->CR3, PWR_CR3_ENULP);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.\r
-  * @note  All the other modes are not affected by this bit\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableBORPVD_ULP(void)\r
-{\r
-  CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);\r
-}\r
-#endif /* PWR_CR3_ENULP */\r
-\r
-\r
-#if defined(PWR_CR4_EXT_SMPS_ON)\r
-/**\r
-  * @brief Enable the CFLDO working @ 0.95V.\r
-  * @note  When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the\r
-  *        internal CFLDO can be reduced to 0.95V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableExtSMPS_0V95(void)\r
-{\r
-  SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\r
-}\r
-\r
-/**\r
-  * @brief Disable the CFLDO working @ 0.95V\r
-  * @note  Before SMPS is switched off, the regulated voltage of the\r
-  *        internal CFLDO shall be set to 1.00V.\r
-  *        1.00V. is also default operating Range 2 voltage.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableExtSMPS_0V95(void)\r
-{\r
-  CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\r
-}\r
-#endif /* PWR_CR4_EXT_SMPS_ON */\r
-\r
-\r
-#if defined(PWR_CR1_RRSTP)\r
-/**\r
-  * @brief Enable SRAM3 content retention in Stop 2 mode.\r
-  * @note  When RRSTP bit is set, SRAM3 is powered by the low-power regulator in\r
-  *        Stop 2 mode and its content is kept.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableSRAM3ContentRetention(void)\r
-{\r
-  SET_BIT(PWR->CR1, PWR_CR1_RRSTP);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable SRAM3 content retention in Stop 2 mode.\r
-  * @note  When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode\r
-  *        and its content is lost.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableSRAM3ContentRetention(void)\r
-{\r
-  CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);\r
-}\r
-#endif /* PWR_CR1_RRSTP */\r
-\r
-#if defined(PWR_CR3_DSIPDEN)\r
-/**\r
-  * @brief Enable pull-down activation on DSI pins.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableDSIPinsPDActivation(void)\r
-{\r
-  SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Disable pull-down activation on DSI pins.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisableDSIPinsPDActivation(void)\r
-{\r
-  CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\r
-}\r
-#endif /* PWR_CR3_DSIPDEN */\r
-\r
-#if defined(PWR_CR2_PVME1)\r
-/**\r
-  * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnablePVM1(void)\r
-{\r
-  SET_BIT(PWR->CR2, PWR_PVM_1);\r
-}\r
-\r
-/**\r
-  * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisablePVM1(void)\r
-{\r
-  CLEAR_BIT(PWR->CR2, PWR_PVM_1);\r
-}\r
-#endif /* PWR_CR2_PVME1 */\r
-\r
-\r
-#if defined(PWR_CR2_PVME2)\r
-/**\r
-  * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnablePVM2(void)\r
-{\r
-  SET_BIT(PWR->CR2, PWR_PVM_2);\r
-}\r
-\r
-/**\r
-  * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisablePVM2(void)\r
-{\r
-  CLEAR_BIT(PWR->CR2, PWR_PVM_2);\r
-}\r
-#endif /* PWR_CR2_PVME2 */\r
-\r
-\r
-/**\r
-  * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnablePVM3(void)\r
-{\r
-  SET_BIT(PWR->CR2, PWR_PVM_3);\r
-}\r
-\r
-/**\r
-  * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisablePVM3(void)\r
-{\r
-  CLEAR_BIT(PWR->CR2, PWR_PVM_3);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enable the Power Voltage Monitoring 4:  VDDA versus 2.2V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnablePVM4(void)\r
-{\r
-  SET_BIT(PWR->CR2, PWR_PVM_4);\r
-}\r
-\r
-/**\r
-  * @brief Disable the Power Voltage Monitoring 4:  VDDA versus 2.2V.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_DisablePVM4(void)\r
-{\r
-  CLEAR_BIT(PWR->CR2, PWR_PVM_4);\r
-}\r
-\r
-\r
-\r
-\r
-/**\r
-  * @brief Configure the Peripheral Voltage Monitoring (PVM).\r
-  * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the\r
-  *        PVM configuration information.\r
-  * @note The API configures a single PVM according to the information contained\r
-  *       in the input structure. To configure several PVMs, the API must be singly\r
-  *       called for each PVM used.\r
-  * @note Refer to the electrical characteristics of your device datasheet for\r
-  *         more details about the voltage thresholds corresponding to each\r
-  *         detection level and to each monitored supply.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));\r
-  assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));\r
-\r
-\r
-  /* Configure EXTI 35 to 38 interrupts if so required:\r
-     scan thru PVMType to detect which PVMx is set and\r
-     configure the corresponding EXTI line accordingly. */\r
-  switch (sConfigPVM->PVMType)\r
-  {\r
-#if defined(PWR_CR2_PVME1)\r
-    case PWR_PVM_1:\r
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
-      __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();\r
-      __HAL_PWR_PVM1_EXTI_DISABLE_IT();\r
-      __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();\r
-      __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();\r
-\r
-      /* Configure interrupt mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
-      {\r
-        __HAL_PWR_PVM1_EXTI_ENABLE_IT();\r
-      }\r
-\r
-      /* Configure event mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
-      {\r
-        __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();\r
-      }\r
-\r
-      /* Configure the edge */\r
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();\r
-      }\r
-\r
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();\r
-      }\r
-      break;\r
-#endif /* PWR_CR2_PVME1 */\r
-\r
-#if defined(PWR_CR2_PVME2)\r
-    case PWR_PVM_2:\r
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
-      __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();\r
-      __HAL_PWR_PVM2_EXTI_DISABLE_IT();\r
-      __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();\r
-      __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();\r
-\r
-      /* Configure interrupt mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
-      {\r
-        __HAL_PWR_PVM2_EXTI_ENABLE_IT();\r
-      }\r
-\r
-      /* Configure event mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
-      {\r
-        __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();\r
-      }\r
-\r
-      /* Configure the edge */\r
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();\r
-      }\r
-\r
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();\r
-      }\r
-      break;\r
-#endif /* PWR_CR2_PVME2 */\r
-\r
-    case PWR_PVM_3:\r
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
-      __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();\r
-      __HAL_PWR_PVM3_EXTI_DISABLE_IT();\r
-      __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();\r
-      __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();\r
-\r
-      /* Configure interrupt mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
-      {\r
-        __HAL_PWR_PVM3_EXTI_ENABLE_IT();\r
-      }\r
-\r
-      /* Configure event mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
-      {\r
-        __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();\r
-      }\r
-\r
-      /* Configure the edge */\r
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();\r
-      }\r
-\r
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();\r
-      }\r
-      break;\r
-\r
-    case PWR_PVM_4:\r
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
-      __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();\r
-      __HAL_PWR_PVM4_EXTI_DISABLE_IT();\r
-      __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();\r
-      __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();\r
-\r
-      /* Configure interrupt mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
-      {\r
-        __HAL_PWR_PVM4_EXTI_ENABLE_IT();\r
-      }\r
-\r
-      /* Configure event mode */\r
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
-      {\r
-        __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();\r
-      }\r
-\r
-      /* Configure the edge */\r
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();\r
-      }\r
-\r
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
-      {\r
-        __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();\r
-      }\r
-      break;\r
-\r
-    default:\r
-      status = HAL_ERROR;\r
-      break;\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-\r
-\r
-/**\r
-  * @brief Enter Low-power Run mode\r
-  * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.\r
-  * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the\r
-  *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.\r
-  *        Additionally, the clock frequency must be reduced below 2 MHz.\r
-  *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must\r
-  *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnableLowPowerRunMode(void)\r
-{\r
-  /* Set Regulator parameter */\r
-  SET_BIT(PWR->CR1, PWR_CR1_LPR);\r
-}\r
-\r
-\r
-/**\r
-  * @brief Exit Low-power Run mode.\r
-  * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that\r
-  *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode\r
-  *        returns HAL_TIMEOUT status). The system clock frequency can then be\r
-  *        increased above 2 MHz.\r
-  * @retval HAL Status\r
-  */\r
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)\r
-{\r
-  uint32_t wait_loop_index;\r
-\r
-  /* Clear LPR bit */\r
-  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);\r
-\r
-  /* Wait until REGLPF is reset */\r
-  wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;\r
-  while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))\r
-  {\r
-    wait_loop_index--;\r
-  }\r
-  if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))\r
-  {\r
-    return HAL_TIMEOUT;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enter Stop 0 mode.\r
-  * @note  In Stop 0 mode, main and low voltage regulators are ON.\r
-  * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.\r
-  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
-  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
-  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
-  *        only to the peripheral requesting it.\r
-  *        SRAM1, SRAM2 and register contents are preserved.\r
-  *        The BOR is available.\r
-  * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,\r
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
-  * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption\r
-  *         is higher although the startup time is reduced.\r
-  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction\r
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
-\r
-  /* Stop 0 mode with Main Regulator */\r
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);\r
-\r
-  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
-  /* Select Stop mode entry --------------------------------------------------*/\r
-  if(STOPEntry == PWR_STOPENTRY_WFI)\r
-  {\r
-    /* Request Wait For Interrupt */\r
-    __WFI();\r
-  }\r
-  else\r
-  {\r
-    /* Request Wait For Event */\r
-    __SEV();\r
-    __WFE();\r
-    __WFE();\r
-  }\r
-\r
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enter Stop 1 mode.\r
-  * @note  In Stop 1 mode, only low power voltage regulator is ON.\r
-  * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.\r
-  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
-  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
-  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
-  *        only to the peripheral requesting it.\r
-  *        SRAM1, SRAM2 and register contents are preserved.\r
-  *        The BOR is available.\r
-  * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,\r
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
-  * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.\r
-  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction\r
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
-\r
-  /* Stop 1 mode with Low-Power Regulator */\r
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);\r
-\r
-  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
-  /* Select Stop mode entry --------------------------------------------------*/\r
-  if(STOPEntry == PWR_STOPENTRY_WFI)\r
-  {\r
-    /* Request Wait For Interrupt */\r
-    __WFI();\r
-  }\r
-  else\r
-  {\r
-    /* Request Wait For Event */\r
-    __SEV();\r
-    __WFE();\r
-    __WFE();\r
-  }\r
-\r
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-}\r
-\r
-\r
-/**\r
-  * @brief Enter Stop 2 mode.\r
-  * @note  In Stop 2 mode, only low power voltage regulator is ON.\r
-  * @note  In Stop 2 mode, all I/O pins keep the same state as in Run mode.\r
-  * @note  All clocks in the VCORE domain are stopped, the PLL, the MSI,\r
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability\r
-  *        (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after\r
-  *        receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only\r
-  *        to the peripheral requesting it.\r
-  *        SRAM1, SRAM2 and register contents are preserved.\r
-  *        The BOR is available.\r
-  *        The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.\r
-  *        Otherwise, Stop 1 mode is entered.\r
-  * @note  When exiting Stop 2 mode by issuing an interrupt or a wakeup event,\r
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
-  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction\r
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)\r
-{\r
-  /* Check the parameter */\r
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
-\r
-  /* Set Stop mode 2 */\r
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);\r
-\r
-  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
-  /* Select Stop mode entry --------------------------------------------------*/\r
-  if(STOPEntry == PWR_STOPENTRY_WFI)\r
-  {\r
-    /* Request Wait For Interrupt */\r
-    __WFI();\r
-  }\r
-  else\r
-  {\r
-    /* Request Wait For Event */\r
-    __SEV();\r
-    __WFE();\r
-    __WFE();\r
-  }\r
-\r
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-}\r
-\r
-\r
-\r
-\r
-\r
-/**\r
-  * @brief Enter Shutdown mode.\r
-  * @note  In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched\r
-  *        off. The voltage regulator is disabled and Vcore domain is powered off.\r
-  *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.\r
-  *        The BOR is not available.\r
-  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_EnterSHUTDOWNMode(void)\r
-{\r
-\r
-  /* Set Shutdown mode */\r
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);\r
-\r
-  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
-/* This option is used to ensure that store operations are completed */\r
-#if defined ( __CC_ARM)\r
-  __force_stores();\r
-#endif\r
-  /* Request Wait For Interrupt */\r
-  __WFI();\r
-}\r
-\r
-\r
-\r
-\r
-/**\r
-  * @brief This function handles the PWR PVD/PVMx interrupt request.\r
-  * @note This API should be called under the PVD_PVM_IRQHandler().\r
-  * @retval None\r
-  */\r
-void HAL_PWREx_PVD_PVM_IRQHandler(void)\r
-{\r
-  /* Check PWR exti flag */\r
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U)\r
-  {\r
-    /* PWR PVD interrupt user callback */\r
-    HAL_PWR_PVDCallback();\r
-\r
-    /* Clear PVD exti pending bit */\r
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
-  }\r
-  /* Next, successively check PVMx exti flags */\r
-#if defined(PWR_CR2_PVME1)\r
-  if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U)\r
-  {\r
-    /* PWR PVM1 interrupt user callback */\r
-    HAL_PWREx_PVM1Callback();\r
-\r
-    /* Clear PVM1 exti pending bit */\r
-    __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();\r
-  }\r
-#endif /* PWR_CR2_PVME1 */\r
-#if defined(PWR_CR2_PVME2)\r
-  if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U)\r
-  {\r
-    /* PWR PVM2 interrupt user callback */\r
-    HAL_PWREx_PVM2Callback();\r
-\r
-    /* Clear PVM2 exti pending bit */\r
-    __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();\r
-  }\r
-#endif /* PWR_CR2_PVME2 */\r
-  if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U)\r
-  {\r
-    /* PWR PVM3 interrupt user callback */\r
-    HAL_PWREx_PVM3Callback();\r
-\r
-    /* Clear PVM3 exti pending bit */\r
-    __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();\r
-  }\r
-  if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U)\r
-  {\r
-    /* PWR PVM4 interrupt user callback */\r
-    HAL_PWREx_PVM4Callback();\r
-\r
-    /* Clear PVM4 exti pending bit */\r
-    __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();\r
-  }\r
-}\r
-\r
-\r
-#if defined(PWR_CR2_PVME1)\r
-/**\r
-  * @brief PWR PVM1 interrupt callback\r
-  * @retval None\r
-  */\r
-__weak void HAL_PWREx_PVM1Callback(void)\r
-{\r
-  /* NOTE : This function should not be modified; when the callback is needed,\r
-            HAL_PWREx_PVM1Callback() API can be implemented in the user file\r
-   */\r
-}\r
-#endif /* PWR_CR2_PVME1 */\r
-\r
-#if defined(PWR_CR2_PVME2)\r
-/**\r
-  * @brief PWR PVM2 interrupt callback\r
-  * @retval None\r
-  */\r
-__weak void HAL_PWREx_PVM2Callback(void)\r
-{\r
-  /* NOTE : This function should not be modified; when the callback is needed,\r
-            HAL_PWREx_PVM2Callback() API can be implemented in the user file\r
-   */\r
-}\r
-#endif /* PWR_CR2_PVME2 */\r
-\r
-/**\r
-  * @brief PWR PVM3 interrupt callback\r
-  * @retval None\r
-  */\r
-__weak void HAL_PWREx_PVM3Callback(void)\r
-{\r
-  /* NOTE : This function should not be modified; when the callback is needed,\r
-            HAL_PWREx_PVM3Callback() API can be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief PWR PVM4 interrupt callback\r
-  * @retval None\r
-  */\r
-__weak void HAL_PWREx_PVM4Callback(void)\r
-{\r
-  /* NOTE : This function should not be modified; when the callback is needed,\r
-            HAL_PWREx_PVM4Callback() API can be implemented in the user file\r
-   */\r
-}\r
-\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_PWR_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
deleted file mode 100644 (file)
index 536d163..0000000
+++ /dev/null
@@ -1,2814 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_qspi.c\r
-  * @author  MCD Application Team\r
-  * @brief   QSPI HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the QuadSPI interface (QSPI).\r
-  *           + Initialization and de-initialization functions\r
-  *           + Indirect functional mode management\r
-  *           + Memory-mapped functional mode management\r
-  *           + Auto-polling functional mode management\r
-  *           + Interrupts and flags management\r
-  *           + DMA channel configuration for indirect functional mode\r
-  *           + Errors management and abort functionality\r
-  *\r
-  *\r
-  @verbatim\r
- ===============================================================================\r
-                        ##### How to use this driver #####\r
- ===============================================================================\r
-  [..]\r
-    *** Initialization ***\r
-    ======================\r
-    [..]\r
-      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :\r
-        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().\r
-        (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().\r
-        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
-        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().\r
-        (++) If interrupt mode is used, enable and configure QuadSPI global\r
-            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
-        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel\r
-            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),\r
-            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure\r
-            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
-      (#) Configure the flash size, the clock prescaler, the fifo threshold, the\r
-          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.\r
-\r
-    *** Indirect functional mode ***\r
-    ================================\r
-    [..]\r
-      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()\r
-          functions :\r
-         (++) Instruction phase : the mode used and if present the instruction opcode.\r
-         (++) Address phase : the mode used and if present the size and the address value.\r
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate\r
-             bytes values.\r
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
-         (++) Data phase : the mode used and if present the number of bytes.\r
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay\r
-             if activated.\r
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
-      (#) If no data is required for the command, it is sent directly to the memory :\r
-         (++) In polling mode, the output of the function is done when the transfer is complete.\r
-         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.\r
-      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or\r
-          HAL_QSPI_Transmit_IT() after the command configuration :\r
-         (++) In polling mode, the output of the function is done when the transfer is complete.\r
-         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold\r
-             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
-         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and\r
-             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
-      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or\r
-          HAL_QSPI_Receive_IT() after the command configuration :\r
-         (++) In polling mode, the output of the function is done when the transfer is complete.\r
-         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold\r
-             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
-         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and\r
-             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
-\r
-    *** Auto-polling functional mode ***\r
-    ====================================\r
-    [..]\r
-      (#) Configure the command sequence and the auto-polling functional mode using the\r
-          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :\r
-         (++) Instruction phase : the mode used and if present the instruction opcode.\r
-         (++) Address phase : the mode used and if present the size and the address value.\r
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate\r
-             bytes values.\r
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
-         (++) Data phase : the mode used.\r
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay\r
-             if activated.\r
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
-         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),\r
-             the polling interval and the automatic stop activation.\r
-      (#) After the configuration :\r
-         (++) In polling mode, the output of the function is done when the status match is reached. The\r
-             automatic stop is activated to avoid an infinite loop.\r
-         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.\r
-\r
-    *** Memory-mapped functional mode ***\r
-    =====================================\r
-    [..]\r
-      (#) Configure the command sequence and the memory-mapped functional mode using the\r
-          HAL_QSPI_MemoryMapped() functions :\r
-         (++) Instruction phase : the mode used and if present the instruction opcode.\r
-         (++) Address phase : the mode used and the size.\r
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate\r
-             bytes values.\r
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
-         (++) Data phase : the mode used.\r
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay\r
-             if activated.\r
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
-         (++) The timeout activation and the timeout period.\r
-      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on\r
-          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.\r
-\r
-    *** Errors management and abort functionality ***\r
-    =================================================\r
-    [..]\r
-      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.\r
-      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and\r
-          flushes the fifo :\r
-         (++) In polling mode, the output of the function is done when the transfer\r
-              complete bit is set and the busy bit cleared.\r
-         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when\r
-              the transfer complete bit is set.\r
-\r
-    *** Control functions ***\r
-    =========================\r
-    [..]\r
-      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.\r
-      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.\r
-      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.\r
-      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold\r
-      (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.\r
-\r
-    *** Callback registration ***\r
-    =============================================\r
-    [..]\r
-      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1\r
-      allows the user to configure dynamically the driver callbacks.\r
-\r
-      Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,\r
-      it allows to register following callbacks:\r
-        (+) ErrorCallback : callback when error occurs.\r
-        (+) AbortCpltCallback : callback when abort is completed.\r
-        (+) FifoThresholdCallback : callback when the fifo threshold is reached.\r
-        (+) CmdCpltCallback : callback when a command without data is completed.\r
-        (+) RxCpltCallback : callback when a reception transfer is completed.\r
-        (+) TxCpltCallback : callback when a transmission transfer is completed.\r
-        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.\r
-        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.\r
-        (+) StatusMatchCallback : callback when a status match occurs.\r
-        (+) TimeOutCallback : callback when the timeout perioed expires.\r
-        (+) MspInitCallback    : QSPI MspInit.\r
-        (+) MspDeInitCallback  : QSPI MspDeInit.\r
-      This function takes as parameters the HAL peripheral handle, the Callback ID\r
-      and a pointer to the user callback function.\r
-\r
-      Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default\r
-      weak (surcharged) function. It allows to reset following callbacks:\r
-        (+) ErrorCallback : callback when error occurs.\r
-        (+) AbortCpltCallback : callback when abort is completed.\r
-        (+) FifoThresholdCallback : callback when the fifo threshold is reached.\r
-        (+) CmdCpltCallback : callback when a command without data is completed.\r
-        (+) RxCpltCallback : callback when a reception transfer is completed.\r
-        (+) TxCpltCallback : callback when a transmission transfer is completed.\r
-        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.\r
-        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.\r
-        (+) StatusMatchCallback : callback when a status match occurs.\r
-        (+) TimeOutCallback : callback when the timeout perioed expires.\r
-        (+) MspInitCallback    : QSPI MspInit.\r
-        (+) MspDeInitCallback  : QSPI MspDeInit.\r
-      This function) takes as parameters the HAL peripheral handle and the Callback ID.\r
-\r
-      By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET\r
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.\r
-      Exception done for MspInit and MspDeInit callbacks that are respectively\r
-      reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init\r
-      and @ref  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).\r
-      If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit\r
-      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)\r
-\r
-      Callbacks can be registered/unregistered in READY state only.\r
-      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered\r
-      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used\r
-      during the Init/DeInit.\r
-      In that case first register the MspInit/MspDeInit user callbacks\r
-      using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit\r
-      or @ref HAL_QSPI_Init function.\r
-\r
-      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or\r
-      not defined, the callback registering feature is not available\r
-      and weak (surcharged) callbacks are used.\r
-\r
-    *** Workarounds linked to Silicon Limitation ***\r
-    ====================================================\r
-    [..]\r
-      (#) Workarounds Implemented inside HAL Driver\r
-         (++) Extra data written in the FIFO at the end of a read transfer\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                       opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-#if defined(QUADSPI)\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup QSPI QSPI\r
-  * @brief QSPI HAL module driver\r
-  * @{\r
-  */\r
-#ifdef HAL_QSPI_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup QSPI_Private_Constants QSPI Private Constants\r
-  * @{\r
-  */\r
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U                     /*!<Indirect write mode*/\r
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/\r
-#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/\r
-#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup QSPI_Private_Macros QSPI Private Macros\r
-  * @{\r
-  */\r
-#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \\r
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \\r
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \\r
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);\r
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);\r
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup QSPI_Exported_Functions QSPI Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions\r
-  *  @brief    Initialization and Configuration functions\r
-  *\r
-@verbatim\r
-===============================================================================\r
-            ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to :\r
-      (+) Initialize the QuadSPI.\r
-      (+) De-initialize the QuadSPI.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Initialize the QSPI mode according to the specified parameters\r
-  *        in the QSPI_InitTypeDef and initialize the associated handle.\r
-  * @param hqspi : QSPI handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Check the QSPI handle allocation */\r
-  if(hqspi == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));\r
-  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));\r
-  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));\r
-  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));\r
-  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));\r
-  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));\r
-  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));\r
-#if defined(QUADSPI_CR_DFM)\r
-  assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));\r
-\r
-  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )\r
-  {\r
-    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r
-  }\r
-#endif\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    hqspi->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-    /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */\r
-    hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;\r
-    hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;\r
-    hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;\r
-    hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;\r
-    hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;\r
-    hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;\r
-    hqspi->RxHalfCpltCallback    = HAL_QSPI_RxHalfCpltCallback;\r
-    hqspi->TxHalfCpltCallback    = HAL_QSPI_TxHalfCpltCallback;\r
-    hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;\r
-    hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;\r
-\r
-    if(hqspi->MspInitCallback == NULL)\r
-    {\r
-      hqspi->MspInitCallback = HAL_QSPI_MspInit;\r
-    }\r
-\r
-    /* Init the low level hardware */\r
-    hqspi->MspInitCallback(hqspi);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK */\r
-    HAL_QSPI_MspInit(hqspi);\r
-#endif\r
-\r
-    /* Configure the default timeout for the QSPI memory access */\r
-    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);\r
-  }\r
-\r
-  /* Configure QSPI FIFO Threshold */\r
-  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,\r
-             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));\r
-\r
-  /* Wait till BUSY flag reset */\r
-  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-    /* Configure QSPI Clock Prescaler and Sample Shift */\r
-#if defined(QUADSPI_CR_DFM)\r
-    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),\r
-               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |\r
-                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));\r
-#else\r
-    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),\r
-               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |\r
-                hqspi->Init.SampleShifting));\r
-#endif\r
-\r
-    /* Configure QSPI Flash Size, CS High Time and Clock Mode */\r
-    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),\r
-               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |\r
-                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));\r
-\r
-    /* Enable the QSPI peripheral */\r
-    __HAL_QSPI_ENABLE(hqspi);\r
-\r
-    /* Set QSPI error code to none */\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    /* Initialize the QSPI state */\r
-    hqspi->State = HAL_QSPI_STATE_READY;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief De-Initialize the QSPI peripheral.\r
-  * @param hqspi : QSPI handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Check the QSPI handle allocation */\r
-  if(hqspi == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  /* Disable the QSPI Peripheral Clock */\r
-  __HAL_QSPI_DISABLE(hqspi);\r
-\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-  if(hqspi->MspDeInitCallback == NULL)\r
-  {\r
-    hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;\r
-  }\r
-\r
-  /* DeInit the low level hardware */\r
-  hqspi->MspDeInitCallback(hqspi);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
-  HAL_QSPI_MspDeInit(hqspi);\r
-#endif\r
-\r
-  /* Set QSPI error code to none */\r
-  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-  /* Initialize the QSPI state */\r
-  hqspi->State = HAL_QSPI_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Initialize the QSPI MSP.\r
-  * @param hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_QSPI_MspInit can be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief DeInitialize the QSPI MSP.\r
-  * @param hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_QSPI_MspDeInit can be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions\r
-  *  @brief QSPI Transmit/Receive functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### IO operation functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to :\r
-      (+) Handle the interrupts.\r
-      (+) Handle the command sequence.\r
-      (+) Transmit data in blocking, interrupt or DMA mode.\r
-      (+) Receive data in blocking, interrupt or DMA mode.\r
-      (+) Manage the auto-polling functional mode.\r
-      (+) Manage the memory-mapped functional mode.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Handle QSPI interrupt request.\r
-  * @param hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  __IO uint32_t *data_reg;\r
-  uint32_t flag = READ_REG(hqspi->Instance->SR);\r
-  uint32_t itsource = READ_REG(hqspi->Instance->CR);\r
-\r
-  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/\r
-  if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))\r
-  {\r
-    data_reg = &hqspi->Instance->DR;\r
-\r
-    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
-    {\r
-      /* Transmission process */\r
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)\r
-      {\r
-        if (hqspi->TxXferCount > 0U)\r
-        {\r
-          /* Fill the FIFO until the threshold is reached */\r
-          *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;\r
-          hqspi->pTxBuffPtr++;\r
-          hqspi->TxXferCount--;\r
-        }\r
-        else\r
-        {\r
-          /* No more data available for the transfer */\r
-          /* Disable the QSPI FIFO Threshold Interrupt */\r
-          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r
-          break;\r
-        }\r
-      }\r
-    }\r
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
-    {\r
-      /* Receiving Process */\r
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)\r
-      {\r
-        if (hqspi->RxXferCount > 0U)\r
-        {\r
-          /* Read the FIFO until the threshold is reached */\r
-          *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);\r
-          hqspi->pRxBuffPtr++;\r
-          hqspi->RxXferCount--;\r
-        }\r
-        else\r
-        {\r
-          /* All data have been received for the transfer */\r
-          /* Disable the QSPI FIFO Threshold Interrupt */\r
-          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r
-          break;\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Nothing to do */\r
-    }\r
-\r
-    /* FIFO Threshold callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-    hqspi->FifoThresholdCallback(hqspi);\r
-#else\r
-    HAL_QSPI_FifoThresholdCallback(hqspi);\r
-#endif\r
-  }\r
-\r
-  /* QSPI Transfer Complete interrupt occurred -------------------------------*/\r
-  else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))\r
-  {\r
-    /* Clear interrupt */\r
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);\r
-\r
-    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */\r
-    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
-\r
-    /* Transfer complete callback */\r
-    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
-    {\r
-      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
-      {\r
-        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
-        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-\r
-        /* Disable the DMA channel */\r
-        __HAL_DMA_DISABLE(hqspi->hdma);\r
-      }\r
-\r
-#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
-      /* Clear Busy bit */\r
-      HAL_QSPI_Abort_IT(hqspi);\r
-#endif\r
-\r
-      /* Change state of QSPI */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-      /* TX Complete callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-      hqspi->TxCpltCallback(hqspi);\r
-#else\r
-      HAL_QSPI_TxCpltCallback(hqspi);\r
-#endif\r
-    }\r
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
-    {\r
-      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
-      {\r
-        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
-        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-\r
-        /* Disable the DMA channel */\r
-        __HAL_DMA_DISABLE(hqspi->hdma);\r
-      }\r
-      else\r
-      {\r
-        data_reg = &hqspi->Instance->DR;\r
-        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)\r
-        {\r
-          if (hqspi->RxXferCount > 0U)\r
-          {\r
-            /* Read the last data received in the FIFO until it is empty */\r
-            *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);\r
-            hqspi->pRxBuffPtr++;\r
-            hqspi->RxXferCount--;\r
-          }\r
-          else\r
-          {\r
-            /* All data have been received for the transfer */\r
-            break;\r
-          }\r
-        }\r
-      }\r
-\r
-#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
-      /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
-      HAL_QSPI_Abort_IT(hqspi);\r
-#endif\r
-\r
-      /* Change state of QSPI */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-      /* RX Complete callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-      hqspi->RxCpltCallback(hqspi);\r
-#else\r
-      HAL_QSPI_RxCpltCallback(hqspi);\r
-#endif\r
-    }\r
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY)\r
-    {\r
-      /* Change state of QSPI */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-      /* Command Complete callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-      hqspi->CmdCpltCallback(hqspi);\r
-#else\r
-      HAL_QSPI_CmdCpltCallback(hqspi);\r
-#endif\r
-    }\r
-    else if(hqspi->State == HAL_QSPI_STATE_ABORT)\r
-    {\r
-      /* Reset functional mode configuration to indirect write mode by default */\r
-      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);\r
-\r
-      /* Change state of QSPI */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)\r
-      {\r
-        /* Abort called by the user */\r
-\r
-        /* Abort Complete callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-        hqspi->AbortCpltCallback(hqspi);\r
-#else\r
-        HAL_QSPI_AbortCpltCallback(hqspi);\r
-#endif\r
-      }\r
-      else\r
-      {\r
-        /* Abort due to an error (eg :  DMA error) */\r
-\r
-        /* Error callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-        hqspi->ErrorCallback(hqspi);\r
-#else\r
-        HAL_QSPI_ErrorCallback(hqspi);\r
-#endif\r
-      }\r
-    }\r
-    else\r
-    {\r
-     /* Nothing to do */\r
-    }\r
-  }\r
-\r
-  /* QSPI Status Match interrupt occurred ------------------------------------*/\r
-  else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))\r
-  {\r
-    /* Clear interrupt */\r
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);\r
-\r
-    /* Check if the automatic poll mode stop is activated */\r
-    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)\r
-    {\r
-      /* Disable the QSPI Transfer Error and Status Match Interrupts */\r
-      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r
-\r
-      /* Change state of QSPI */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-    }\r
-\r
-    /* Status match callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-    hqspi->StatusMatchCallback(hqspi);\r
-#else\r
-    HAL_QSPI_StatusMatchCallback(hqspi);\r
-#endif\r
-  }\r
-\r
-  /* QSPI Transfer Error interrupt occurred ----------------------------------*/\r
-  else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))\r
-  {\r
-    /* Clear interrupt */\r
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);\r
-\r
-    /* Disable all the QSPI Interrupts */\r
-    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
-\r
-    /* Set error code */\r
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;\r
-\r
-    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
-    {\r
-      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
-      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-\r
-      /* Disable the DMA channel */\r
-      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r
-      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)\r
-      {\r
-        /* Set error code to DMA */\r
-        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
-\r
-        /* Change state of QSPI */\r
-        hqspi->State = HAL_QSPI_STATE_READY;\r
-        \r
-        /* Error callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-        hqspi->ErrorCallback(hqspi);\r
-#else\r
-        HAL_QSPI_ErrorCallback(hqspi);\r
-#endif\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Change state of QSPI */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-      /* Error callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-      hqspi->ErrorCallback(hqspi);\r
-#else\r
-      HAL_QSPI_ErrorCallback(hqspi);\r
-#endif\r
-    }\r
-  }\r
-\r
-  /* QSPI Timeout interrupt occurred -----------------------------------------*/\r
-  else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))\r
-  {\r
-    /* Clear interrupt */\r
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);\r
-\r
-    /* Timeout callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-    hqspi->TimeOutCallback(hqspi);\r
-#else\r
-    HAL_QSPI_TimeOutCallback(hqspi);\r
-#endif\r
-  }\r
-\r
-   else\r
-  {\r
-   /* Nothing to do */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Set the command configuration.\r
-  * @param hqspi : QSPI handle\r
-  * @param cmd : structure that contains the command configuration information\r
-  * @param Timeout : Timeout duration\r
-  * @note   This function is used only in Indirect Read or Write Modes\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
-  {\r
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    /* Update QSPI state */\r
-    hqspi->State = HAL_QSPI_STATE_BUSY;\r
-\r
-    /* Wait till BUSY flag reset */\r
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      /* Call the configuration function */\r
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
-\r
-      if (cmd->DataMode == QSPI_DATA_NONE)\r
-      {\r
-        /* When there is no data phase, the transfer start as soon as the configuration is done\r
-        so wait until TC flag is set to go back in idle state */\r
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
-\r
-        if (status == HAL_OK)\r
-        {\r
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
-          /* Update QSPI state */\r
-          hqspi->State = HAL_QSPI_STATE_READY;\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Update QSPI state */\r
-        hqspi->State = HAL_QSPI_STATE_READY;\r
-      }\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief Set the command configuration in interrupt mode.\r
-  * @param hqspi : QSPI handle\r
-  * @param cmd : structure that contains the command configuration information\r
-  * @note   This function is used only in Indirect Read or Write Modes\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
-  {\r
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    /* Update QSPI state */\r
-    hqspi->State = HAL_QSPI_STATE_BUSY;\r
-\r
-    /* Wait till BUSY flag reset */\r
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      if (cmd->DataMode == QSPI_DATA_NONE)\r
-      {\r
-        /* Clear interrupt */\r
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
-      }\r
-\r
-      /* Call the configuration function */\r
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
-\r
-      if (cmd->DataMode == QSPI_DATA_NONE)\r
-      {\r
-        /* When there is no data phase, the transfer start as soon as the configuration is done\r
-        so activate TC and TE interrupts */\r
-        /* Process unlocked */\r
-        __HAL_UNLOCK(hqspi);\r
-\r
-        /* Enable the QSPI Transfer Error Interrupt */\r
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);\r
-      }\r
-      else\r
-      {\r
-        /* Update QSPI state */\r
-        hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-        /* Process unlocked */\r
-        __HAL_UNLOCK(hqspi);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-  }\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief Transmit an amount of data in blocking mode.\r
-  * @param hqspi : QSPI handle\r
-  * @param pData : pointer to data buffer\r
-  * @param Timeout : Timeout duration\r
-  * @note   This function is used only in Indirect Write Mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t tickstart = HAL_GetTick();\r
-  __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    if(pData != NULL )\r
-    {\r
-      /* Update state */\r
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
-\r
-      /* Configure counters and size of the handle */\r
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->pTxBuffPtr = pData;\r
-\r
-      /* Configure QSPI: CCR register with functional as indirect write */\r
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
-\r
-      while(hqspi->TxXferCount > 0U)\r
-      {\r
-        /* Wait until FT flag is set to send data */\r
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);\r
-\r
-        if (status != HAL_OK)\r
-        {\r
-          break;\r
-        }\r
-\r
-        *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;\r
-        hqspi->pTxBuffPtr++;\r
-        hqspi->TxXferCount--;\r
-      }\r
-\r
-      if (status == HAL_OK)\r
-      {\r
-        /* Wait until TC flag is set to go back in idle state */\r
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
-\r
-        if (status == HAL_OK)\r
-        {\r
-          /* Clear Transfer Complete bit */\r
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
-#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
-          /* Clear Busy bit */\r
-          status = HAL_QSPI_Abort(hqspi);\r
-#endif\r
-        }\r
-      }\r
-\r
-      /* Update QSPI state */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-    }\r
-    else\r
-    {\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  return status;\r
-}\r
-\r
-\r
-/**\r
-  * @brief Receive an amount of data in blocking mode.\r
-  * @param hqspi : QSPI handle\r
-  * @param pData : pointer to data buffer\r
-  * @param Timeout : Timeout duration\r
-  * @note   This function is used only in Indirect Read Mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t tickstart = HAL_GetTick();\r
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
-  __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    if(pData != NULL )\r
-    {\r
-      /* Update state */\r
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
-\r
-      /* Configure counters and size of the handle */\r
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->pRxBuffPtr = pData;\r
-\r
-      /* Configure QSPI: CCR register with functional as indirect read */\r
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
-\r
-      /* Start the transfer by re-writing the address in AR register */\r
-      WRITE_REG(hqspi->Instance->AR, addr_reg);\r
-\r
-      while(hqspi->RxXferCount > 0U)\r
-      {\r
-        /* Wait until FT or TC flag is set to read received data */\r
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);\r
-\r
-        if  (status != HAL_OK)\r
-        {\r
-          break;\r
-        }\r
-\r
-        *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);\r
-        hqspi->pRxBuffPtr++;\r
-        hqspi->RxXferCount--;\r
-      }\r
-\r
-      if (status == HAL_OK)\r
-      {\r
-        /* Wait until TC flag is set to go back in idle state */\r
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r
-\r
-        if  (status == HAL_OK)\r
-        {\r
-          /* Clear Transfer Complete bit */\r
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
-#if  (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))\r
-          /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
-          status = HAL_QSPI_Abort(hqspi);\r
-#endif\r
-        }\r
-      }\r
-\r
-      /* Update QSPI state */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-    }\r
-    else\r
-    {\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Send an amount of data in non-blocking mode with interrupt.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  pData : pointer to data buffer\r
-  * @note   This function is used only in Indirect Write Mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    if(pData != NULL )\r
-    {\r
-      /* Update state */\r
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
-\r
-      /* Configure counters and size of the handle */\r
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->pTxBuffPtr = pData;\r
-\r
-      /* Clear interrupt */\r
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
-\r
-      /* Configure QSPI: CCR register with functional as indirect write */\r
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
-\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-\r
-      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
-    }\r
-    else\r
-    {\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-      status = HAL_ERROR;\r
-\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Receive an amount of data in non-blocking mode with interrupt.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  pData : pointer to data buffer\r
-  * @note   This function is used only in Indirect Read Mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    if(pData != NULL )\r
-    {\r
-      /* Update state */\r
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
-\r
-      /* Configure counters and size of the handle */\r
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;\r
-      hqspi->pRxBuffPtr = pData;\r
-\r
-      /* Clear interrupt */\r
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r
-\r
-      /* Configure QSPI: CCR register with functional as indirect read */\r
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
-\r
-      /* Start the transfer by re-writing the address in AR register */\r
-      WRITE_REG(hqspi->Instance->AR, addr_reg);\r
-\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-\r
-      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
-    }\r
-    else\r
-    {\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-      status = HAL_ERROR;\r
-\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Send an amount of data in non-blocking mode with DMA.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  pData : pointer to data buffer\r
-  * @note   This function is used only in Indirect Write Mode\r
-  * @note   If DMA peripheral access is configured as halfword, the number\r
-  *         of data and the fifo threshold should be aligned on halfword\r
-  * @note   If DMA peripheral access is configured as word, the number\r
-  *         of data and the fifo threshold should be aligned on word\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    /* Clear the error code */\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    if(pData != NULL )\r
-    {\r
-      /* Configure counters of the handle */\r
-      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r
-      {\r
-        hqspi->TxXferCount = data_size;\r
-      }\r
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r
-      {\r
-        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))\r
-        {\r
-          /* The number of data or the fifo threshold is not aligned on halfword\r
-          => no transfer possible with DMA peripheral access configured as halfword */\r
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-          status = HAL_ERROR;\r
-\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-        }\r
-        else\r
-        {\r
-          hqspi->TxXferCount = (data_size >> 1U);\r
-        }\r
-      }\r
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r
-      {\r
-        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))\r
-        {\r
-          /* The number of data or the fifo threshold is not aligned on word\r
-          => no transfer possible with DMA peripheral access configured as word */\r
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-          status = HAL_ERROR;\r
-\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-        }\r
-        else\r
-        {\r
-          hqspi->TxXferCount = (data_size >> 2U);\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Nothing to do */\r
-      }\r
-\r
-      if (status == HAL_OK)\r
-      {\r
-        /* Update state */\r
-        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
-\r
-        /* Clear interrupt */\r
-        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r
-\r
-        /* Configure size and pointer of the handle */\r
-        hqspi->TxXferSize = hqspi->TxXferCount;\r
-        hqspi->pTxBuffPtr = pData;\r
-\r
-        /* Configure QSPI: CCR register with functional mode as indirect write */\r
-        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
-\r
-        /* Set the QSPI DMA transfer complete callback */\r
-        hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;\r
-\r
-        /* Set the QSPI DMA Half transfer complete callback */\r
-        hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;\r
-\r
-        /* Set the DMA error callback */\r
-        hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
-\r
-        /* Clear the DMA abort callback */\r
-        hqspi->hdma->XferAbortCallback = NULL;\r
-\r
-        /* Configure the direction of the DMA */\r
-        hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;\r
-        MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);\r
-\r
-        /* Enable the QSPI transmit DMA Channel */\r
-        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)\r
-        {\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-          \r
-          /* Enable the QSPI transfer error Interrupt */\r
-          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r
-          \r
-          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
-          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-        }\r
-        else\r
-        {\r
-          status = HAL_ERROR;\r
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
-          hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-        }\r
-     }\r
-    }\r
-    else\r
-    {\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-      status = HAL_ERROR;\r
-\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Receive an amount of data in non-blocking mode with DMA.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  pData : pointer to data buffer.\r
-  * @note   This function is used only in Indirect Read Mode\r
-  * @note   If DMA peripheral access is configured as halfword, the number\r
-  *         of data and the fifo threshold should be aligned on halfword\r
-  * @note   If DMA peripheral access is configured as word, the number\r
-  *         of data and the fifo threshold should be aligned on word\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
-  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    /* Clear the error code */\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    if(pData != NULL )\r
-    {\r
-      /* Configure counters of the handle */\r
-      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r
-      {\r
-        hqspi->RxXferCount = data_size;\r
-      }\r
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r
-      {\r
-        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))\r
-        {\r
-          /* The number of data or the fifo threshold is not aligned on halfword\r
-             => no transfer possible with DMA peripheral access configured as halfword */\r
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-          status = HAL_ERROR;\r
-\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-        }\r
-        else\r
-        {\r
-          hqspi->RxXferCount = (data_size >> 1U);\r
-        }\r
-      }\r
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r
-      {\r
-        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))\r
-        {\r
-          /* The number of data or the fifo threshold is not aligned on word\r
-             => no transfer possible with DMA peripheral access configured as word */\r
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-          status = HAL_ERROR;\r
-\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-        }\r
-        else\r
-        {\r
-          hqspi->RxXferCount = (data_size >> 2U);\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Nothing to do */\r
-      }\r
-\r
-      if (status == HAL_OK)\r
-      {\r
-        /* Update state */\r
-        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
-\r
-        /* Clear interrupt */\r
-        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r
-\r
-        /* Configure size and pointer of the handle */\r
-        hqspi->RxXferSize = hqspi->RxXferCount;\r
-        hqspi->pRxBuffPtr = pData;\r
-\r
-        /* Set the QSPI DMA transfer complete callback */\r
-        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;\r
-\r
-        /* Set the QSPI DMA Half transfer complete callback */\r
-        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;\r
-\r
-        /* Set the DMA error callback */\r
-        hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
-\r
-        /* Clear the DMA abort callback */\r
-        hqspi->hdma->XferAbortCallback = NULL;\r
-\r
-        /* Configure the direction of the DMA */\r
-        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;\r
-        MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);\r
-\r
-        /* Enable the DMA Channel */\r
-        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)\r
-        {\r
-          /* Configure QSPI: CCR register with functional as indirect read */\r
-          MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
-\r
-          /* Start the transfer by re-writing the address in AR register */\r
-          WRITE_REG(hqspi->Instance->AR, addr_reg);\r
-\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-          \r
-          /* Enable the QSPI transfer error Interrupt */\r
-          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r
-          \r
-          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
-          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-        }\r
-        else\r
-        {\r
-          status = HAL_ERROR;\r
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
-          hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-          /* Process unlocked */\r
-          __HAL_UNLOCK(hqspi);\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r
-      status = HAL_ERROR;\r
-\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  cmd : structure that contains the command configuration information.\r
-  * @param  cfg : structure that contains the polling configuration information.\r
-  * @param  Timeout : Timeout duration\r
-  * @note   This function is used only in Automatic Polling Mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
-  {\r
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
-  assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
-  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
-  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    /* Update state */\r
-    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
-\r
-    /* Wait till BUSY flag reset */\r
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      /* Configure QSPI: PSMAR register with the status match value */\r
-      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
-\r
-      /* Configure QSPI: PSMKR register with the status mask value */\r
-      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
-\r
-      /* Configure QSPI: PIR register with the interval value */\r
-      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
-\r
-      /* Configure QSPI: CR register with Match mode and Automatic stop enabled\r
-      (otherwise there will be an infinite loop in blocking mode) */\r
-      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),\r
-               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));\r
-\r
-      /* Call the configuration function */\r
-      cmd->NbData = cfg->StatusBytesSize;\r
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
-\r
-      /* Wait until SM flag is set to go back in idle state */\r
-      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);\r
-\r
-      if (status == HAL_OK)\r
-      {\r
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r
-\r
-        /* Update state */\r
-        hqspi->State = HAL_QSPI_STATE_READY;\r
-      }\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  cmd : structure that contains the command configuration information.\r
-  * @param  cfg : structure that contains the polling configuration information.\r
-  * @note   This function is used only in Automatic Polling Mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
-  {\r
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
-  assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
-  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
-  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
-  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    /* Update state */\r
-    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
-\r
-    /* Wait till BUSY flag reset */\r
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      /* Configure QSPI: PSMAR register with the status match value */\r
-      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
-\r
-      /* Configure QSPI: PSMKR register with the status mask value */\r
-      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
-\r
-      /* Configure QSPI: PIR register with the interval value */\r
-      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
-\r
-      /* Configure QSPI: CR register with Match mode and Automatic stop mode */\r
-      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),\r
-               (cfg->MatchMode | cfg->AutomaticStop));\r
-\r
-      /* Clear interrupt */\r
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);\r
-\r
-      /* Call the configuration function */\r
-      cmd->NbData = cfg->StatusBytesSize;\r
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
-\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-\r
-      /* Enable the QSPI Transfer Error and status match Interrupt */\r
-      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r
-\r
-    }\r
-    else\r
-    {\r
-      /* Process unlocked */\r
-      __HAL_UNLOCK(hqspi);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-  }\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the Memory Mapped mode.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  cmd : structure that contains the command configuration information.\r
-  * @param  cfg : structure that contains the memory mapped configuration information.\r
-  * @note   This function is used only in Memory mapped Mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)\r
-{\r
-  HAL_StatusTypeDef status;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
-  {\r
-  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
-  {\r
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
-  }\r
-\r
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
-  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
-    /* Update state */\r
-    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;\r
-\r
-    /* Wait till BUSY flag reset */\r
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      /* Configure QSPI: CR register with timeout counter enable */\r
-    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);\r
-\r
-    if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)\r
-      {\r
-        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));\r
-\r
-        /* Configure QSPI: LPTR register with the low-power timeout value */\r
-        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);\r
-\r
-        /* Clear interrupt */\r
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);\r
-\r
-        /* Enable the QSPI TimeOut Interrupt */\r
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);\r
-      }\r
-\r
-      /* Call the configuration function */\r
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Transfer Error callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_QSPI_ErrorCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Abort completed callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_QSPI_AbortCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Command completed callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_QSPI_CmdCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Rx Transfer completed callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_QSPI_RxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Tx Transfer completed callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_QSPI_TxCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Rx Half Transfer completed callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Tx Half Transfer completed callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  FIFO Threshold callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Status Match callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_QSPI_StatusMatchCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Timeout callback.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hqspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_QSPI_TimeOutCallback could be implemented in the user file\r
-   */\r
-}\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  Register a User QSPI Callback\r
-  *         To be used instead of the weak (surcharged) predefined callback\r
-  * @param hqspi : QSPI handle\r
-  * @param CallbackId : ID of the callback to be registered\r
-  *        This parameter can be one of the following values:\r
-  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID\r
-  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID\r
-  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID\r
-  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID\r
-  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID\r
-  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID\r
-  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID\r
-  * @param pCallback : pointer to the Callback function\r
-  * @retval status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if(pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    switch (CallbackId)\r
-    {\r
-    case  HAL_QSPI_ERROR_CB_ID :\r
-      hqspi->ErrorCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_ABORT_CB_ID :\r
-      hqspi->AbortCpltCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :\r
-      hqspi->FifoThresholdCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_CMD_CPLT_CB_ID :\r
-      hqspi->CmdCpltCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_RX_CPLT_CB_ID :\r
-      hqspi->RxCpltCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_TX_CPLT_CB_ID :\r
-      hqspi->TxCpltCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_RX_HALF_CPLT_CB_ID :\r
-      hqspi->RxHalfCpltCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_TX_HALF_CPLT_CB_ID :\r
-      hqspi->TxHalfCpltCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_STATUS_MATCH_CB_ID :\r
-      hqspi->StatusMatchCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_TIMEOUT_CB_ID :\r
-      hqspi->TimeOutCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_MSP_INIT_CB_ID :\r
-      hqspi->MspInitCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
-      hqspi->MspDeInitCallback = pCallback;\r
-      break;\r
-    default :\r
-      /* Update the error code */\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
-      /* update return status */\r
-      status =  HAL_ERROR;\r
-      break;\r
-    }\r
-  }\r
-  else if (hqspi->State == HAL_QSPI_STATE_RESET)\r
-  {\r
-    switch (CallbackId)\r
-    {\r
-    case HAL_QSPI_MSP_INIT_CB_ID :\r
-      hqspi->MspInitCallback = pCallback;\r
-      break;\r
-    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
-      hqspi->MspDeInitCallback = pCallback;\r
-      break;\r
-    default :\r
-      /* Update the error code */\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
-      /* update return status */\r
-      status =  HAL_ERROR;\r
-      break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
-    /* update return status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hqspi);\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister a User QSPI Callback\r
-  *         QSPI Callback is redirected to the weak (surcharged) predefined callback\r
-  * @param hqspi : QSPI handle\r
-  * @param CallbackId : ID of the callback to be unregistered\r
-  *        This parameter can be one of the following values:\r
-  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID\r
-  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID\r
-  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID\r
-  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID\r
-  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID\r
-  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID\r
-  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID\r
-  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID\r
-  * @retval status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    switch (CallbackId)\r
-    {\r
-    case  HAL_QSPI_ERROR_CB_ID :\r
-      hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;\r
-      break;\r
-    case HAL_QSPI_ABORT_CB_ID :\r
-      hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;\r
-      break;\r
-    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :\r
-      hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;\r
-      break;\r
-    case HAL_QSPI_CMD_CPLT_CB_ID :\r
-      hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;\r
-      break;\r
-    case HAL_QSPI_RX_CPLT_CB_ID :\r
-      hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;\r
-      break;\r
-    case HAL_QSPI_TX_CPLT_CB_ID :\r
-      hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;\r
-      break;\r
-    case HAL_QSPI_RX_HALF_CPLT_CB_ID :\r
-      hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;\r
-      break;\r
-    case HAL_QSPI_TX_HALF_CPLT_CB_ID :\r
-      hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;\r
-      break;\r
-    case HAL_QSPI_STATUS_MATCH_CB_ID :\r
-      hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;\r
-      break;\r
-    case HAL_QSPI_TIMEOUT_CB_ID :\r
-      hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;\r
-      break;\r
-    case HAL_QSPI_MSP_INIT_CB_ID :\r
-      hqspi->MspInitCallback = HAL_QSPI_MspInit;\r
-      break;\r
-    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
-      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;\r
-      break;\r
-    default :\r
-      /* Update the error code */\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
-      /* update return status */\r
-      status =  HAL_ERROR;\r
-      break;\r
-    }\r
-  }\r
-  else if (hqspi->State == HAL_QSPI_STATE_RESET)\r
-  {\r
-    switch (CallbackId)\r
-    {\r
-    case HAL_QSPI_MSP_INIT_CB_ID :\r
-      hqspi->MspInitCallback = HAL_QSPI_MspInit;\r
-      break;\r
-    case HAL_QSPI_MSP_DEINIT_CB_ID :\r
-      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;\r
-      break;\r
-    default :\r
-      /* Update the error code */\r
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
-      /* update return status */\r
-      status =  HAL_ERROR;\r
-      break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;\r
-    /* update return status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hqspi);\r
-  return status;\r
-}\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions\r
-  *  @brief   QSPI control and State functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-                  ##### Peripheral Control and State functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to :\r
-      (+) Check in run-time the state of the driver.\r
-      (+) Check the error code set during last operation.\r
-      (+) Abort any operation.\r
-\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Return the QSPI handle state.\r
-  * @param  hqspi : QSPI handle\r
-  * @retval HAL state\r
-  */\r
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  /* Return QSPI handle state */\r
-  return hqspi->State;\r
-}\r
-\r
-/**\r
-* @brief  Return the QSPI error code.\r
-* @param  hqspi : QSPI handle\r
-* @retval QSPI Error Code\r
-*/\r
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  return hqspi->ErrorCode;\r
-}\r
-\r
-/**\r
-* @brief  Abort the current transmission.\r
-* @param  hqspi : QSPI handle\r
-* @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t tickstart = HAL_GetTick();\r
-\r
-  /* Check if the state is in one of the busy states */\r
-  if (((uint32_t)hqspi->State & 0x2U) != 0U)\r
-  {\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-\r
-    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
-    {\r
-      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
-      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-\r
-      /* Abort DMA channel */\r
-      status = HAL_DMA_Abort(hqspi->hdma);\r
-      if(status != HAL_OK)\r
-      {\r
-        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
-      }\r
-    }\r
-\r
-    /* Configure QSPI: CR register with Abort request */\r
-    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
-\r
-    /* Wait until TC flag is set to go back in idle state */\r
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
-      /* Wait until BUSY flag is reset */\r
-      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r
-    }\r
-\r
-    if (status == HAL_OK)\r
-    {\r
-      /* Reset functional mode configuration to indirect write mode by default */\r
-      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);\r
-\r
-      /* Update state */\r
-      hqspi->State = HAL_QSPI_STATE_READY;\r
-    }\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-* @brief  Abort the current transmission (non-blocking function)\r
-* @param  hqspi : QSPI handle\r
-* @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check if the state is in one of the busy states */\r
-  if (((uint32_t)hqspi->State & 0x2U) != 0U)\r
-  {\r
-    /* Process unlocked */\r
-    __HAL_UNLOCK(hqspi);\r
-\r
-    /* Update QSPI state */\r
-    hqspi->State = HAL_QSPI_STATE_ABORT;\r
-\r
-    /* Disable all interrupts */\r
-    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));\r
-\r
-    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)\r
-    {\r
-      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
-      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-\r
-      /* Abort DMA channel */\r
-      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r
-      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)\r
-      {\r
-        /* Change state of QSPI */\r
-        hqspi->State = HAL_QSPI_STATE_READY;\r
-        \r
-        /* Abort Complete callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-        hqspi->AbortCpltCallback(hqspi);\r
-#else\r
-        HAL_QSPI_AbortCpltCallback(hqspi);\r
-#endif\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Clear interrupt */\r
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
-      /* Enable the QSPI Transfer Complete Interrupt */\r
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
-\r
-      /* Configure QSPI: CR register with Abort request */\r
-      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
-    }\r
-  }\r
-  return status;\r
-}\r
-\r
-/** @brief Set QSPI timeout.\r
-  * @param  hqspi : QSPI handle.\r
-  * @param  Timeout : Timeout for the QSPI memory access.\r
-  * @retval None\r
-  */\r
-void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)\r
-{\r
-  hqspi->Timeout = Timeout;\r
-}\r
-\r
-/** @brief Set QSPI Fifo threshold.\r
-  * @param  hqspi : QSPI handle.\r
-  * @param  Threshold : Threshold of the Fifo (value between 1 and 16).\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    /* Synchronize init structure with new FIFO threshold value */\r
-    hqspi->Init.FifoThreshold = Threshold;\r
-\r
-    /* Configure QSPI FIFO Threshold */\r
-    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,\r
-               ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/** @brief Get QSPI Fifo threshold.\r
-  * @param  hqspi : QSPI handle.\r
-  * @retval Fifo threshold (value between 1 and 16)\r
-  */\r
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)\r
-{\r
-  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);\r
-}\r
-\r
-#if defined(QUADSPI_CR_DFM)\r
-/** @brief  Set FlashID.\r
-  * @param  hqspi : QSPI handle.\r
-  * @param  FlashID : Index of the flash memory to be accessed.\r
-  *                   This parameter can be a value of @ref QSPI_Flash_Select.\r
-  * @note   The FlashID is ignored when dual flash mode is enabled.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Check the parameter */\r
-  assert_param(IS_QSPI_FLASH_ID(FlashID));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hqspi);\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_READY)\r
-  {\r
-    /* Synchronize init structure with new FlashID value */\r
-    hqspi->Init.FlashID = FlashID;\r
-\r
-    /* Configure QSPI FlashID */\r
-    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);\r
-  }\r
-  else\r
-  {\r
-    status = HAL_BUSY;\r
-  }\r
-\r
-  /* Process unlocked */\r
-  __HAL_UNLOCK(hqspi);\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup QSPI_Private_Functions QSPI Private Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  DMA QSPI receive process complete callback.\r
-  * @param  hdma : DMA handle\r
-  * @retval None\r
-  */\r
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
-  hqspi->RxXferCount = 0U;\r
-\r
-  /* Enable the QSPI transfer complete Interrupt */\r
-  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
-}\r
-\r
-/**\r
-  * @brief  DMA QSPI transmit process complete callback.\r
-  * @param  hdma : DMA handle\r
-  * @retval None\r
-  */\r
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
-  hqspi->TxXferCount = 0U;\r
-\r
-  /* Enable the QSPI transfer complete Interrupt */\r
-  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
-}\r
-\r
-/**\r
-  * @brief  DMA QSPI receive process half complete callback.\r
-  * @param  hdma : DMA handle\r
-  * @retval None\r
-  */\r
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
-\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-  hqspi->RxHalfCpltCallback(hqspi);\r
-#else\r
-  HAL_QSPI_RxHalfCpltCallback(hqspi);\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  DMA QSPI transmit process half complete callback.\r
-  * @param  hdma : DMA handle\r
-  * @retval None\r
-  */\r
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);\r
-\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-  hqspi->TxHalfCpltCallback(hqspi);\r
-#else\r
-  HAL_QSPI_TxHalfCpltCallback(hqspi);\r
-#endif\r
-}\r
-\r
-/**\r
-  * @brief  DMA QSPI communication error callback.\r
-  * @param  hdma : DMA handle\r
-  * @retval None\r
-  */\r
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
-  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);\r
-\r
-  hqspi->RxXferCount = 0U;\r
-  hqspi->TxXferCount = 0U;\r
-  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;\r
-\r
-  /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
-  CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-\r
-  /* Abort the QSPI */\r
-  (void)HAL_QSPI_Abort_IT(hqspi);\r
-\r
-}\r
-\r
-/**\r
-  * @brief  DMA QSPI abort complete callback.\r
-  * @param  hdma : DMA handle\r
-  * @retval None\r
-  */\r
-static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);\r
-\r
-  hqspi->RxXferCount = 0U;\r
-  hqspi->TxXferCount = 0U;\r
-\r
-  if(hqspi->State == HAL_QSPI_STATE_ABORT)\r
-  {\r
-    /* DMA Abort called by QSPI abort */\r
-    /* Clear interrupt */\r
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
-    /* Enable the QSPI Transfer Complete Interrupt */\r
-    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r
-\r
-    /* Configure QSPI: CR register with Abort request */\r
-    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
-  }\r
-  else\r
-  {\r
-    /* DMA Abort called due to a transfer error interrupt */\r
-    /* Change state of QSPI */\r
-    hqspi->State = HAL_QSPI_STATE_READY;\r
-\r
-    /* Error callback */\r
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
-    hqspi->ErrorCallback(hqspi);\r
-#else\r
-    HAL_QSPI_ErrorCallback(hqspi);\r
-#endif\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Wait for a flag state until timeout.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  Flag : Flag checked\r
-  * @param  State : Value of the flag expected\r
-  * @param  Tickstart : Tick start value\r
-  * @param  Timeout : Duration of the timeout\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,\r
-                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)\r
-{\r
-  /* Wait until flag is in expected state */\r
-  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)\r
-  {\r
-    /* Check for the Timeout */\r
-    if (Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
-      {\r
-        hqspi->State     = HAL_QSPI_STATE_ERROR;\r
-        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the communication registers.\r
-  * @param  hqspi : QSPI handle\r
-  * @param  cmd : structure that contains the command configuration information\r
-  * @param  FunctionalMode : functional mode to configured\r
-  *           This parameter can be one of the following values:\r
-  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode\r
-  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode\r
-  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode\r
-  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode\r
-  * @retval None\r
-  */\r
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)\r
-{\r
-  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));\r
-\r
-  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
-  {\r
-    /* Configure QSPI: DLR register with the number of data to read or write */\r
-    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));\r
-  }\r
-\r
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
-  {\r
-    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
-    {\r
-      /* Configure QSPI: ABR register with alternate bytes value */\r
-      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
-\r
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-      {\r
-        /*---- Command with instruction, address and alternate bytes ----*/\r
-        /* Configure QSPI: CCR register with all communications parameters */\r
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
-                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |\r
-                                         cmd->Instruction | FunctionalMode));\r
-\r
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
-        {\r
-          /* Configure QSPI: AR register with address value */\r
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /*---- Command with instruction and alternate bytes ----*/\r
-        /* Configure QSPI: CCR register with all communications parameters */\r
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
-                                         cmd->AddressMode | cmd->InstructionMode |\r
-                                         cmd->Instruction | FunctionalMode));\r
-      }\r
-    }\r
-    else\r
-    {\r
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-      {\r
-        /*---- Command with instruction and address ----*/\r
-        /* Configure QSPI: CCR register with all communications parameters */\r
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
-                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r
-\r
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
-        {\r
-          /* Configure QSPI: AR register with address value */\r
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /*---- Command with only instruction ----*/\r
-        /* Configure QSPI: CCR register with all communications parameters */\r
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                         cmd->AlternateByteMode | cmd->AddressMode |\r
-                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r
-      }\r
-    }\r
-  }\r
-  else\r
-  {\r
-    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
-    {\r
-      /* Configure QSPI: ABR register with alternate bytes value */\r
-      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
-\r
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-      {\r
-        /*---- Command with address and alternate bytes ----*/\r
-        /* Configure QSPI: CCR register with all communications parameters */\r
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
-                                         cmd->AddressSize | cmd->AddressMode |\r
-                                         cmd->InstructionMode | FunctionalMode));\r
-\r
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
-        {\r
-          /* Configure QSPI: AR register with address value */\r
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /*---- Command with only alternate bytes ----*/\r
-        /* Configure QSPI: CCR register with all communications parameters */\r
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |\r
-                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r
-      }\r
-    }\r
-    else\r
-    {\r
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
-      {\r
-        /*---- Command with only address ----*/\r
-        /* Configure QSPI: CCR register with all communications parameters */\r
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                         cmd->AlternateByteMode | cmd->AddressSize |\r
-                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r
-\r
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
-        {\r
-          /* Configure QSPI: AR register with address value */\r
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /*---- Command with only data phase ----*/\r
-        if (cmd->DataMode != QSPI_DATA_NONE)\r
-        {\r
-          /* Configure QSPI: CCR register with all communications parameters */\r
-          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
-                                           cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |\r
-                                           cmd->AlternateByteMode | cmd->AddressMode |\r
-                                           cmd->InstructionMode | FunctionalMode));\r
-        }\r
-      }\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_QSPI_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
deleted file mode 100644 (file)
index 9709d06..0000000
+++ /dev/null
@@ -1,1869 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_rcc.c\r
-  * @author  MCD Application Team\r
-  * @brief   RCC HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:\r
-  *           + Initialization and de-initialization functions\r
-  *           + Peripheral Control functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                      ##### RCC specific features #####\r
-  ==============================================================================\r
-    [..]\r
-      After reset the device is running from Multiple Speed Internal oscillator\r
-      (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache\r
-      and I-Cache are disabled, and all peripherals are off except internal\r
-      SRAM, Flash and JTAG.\r
-\r
-      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:\r
-          all peripherals mapped on these busses are running at MSI speed.\r
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
-      (+) All GPIOs are in analog mode, except the JTAG pins which\r
-          are assigned to be used for debug purpose.\r
-\r
-    [..]\r
-      Once the device started from reset, the user application has to:\r
-      (+) Configure the clock source to be used to drive the System clock\r
-          (if the application needs higher frequency/performance)\r
-      (+) Configure the System clock frequency and Flash settings\r
-      (+) Configure the AHB and APB busses prescalers\r
-      (+) Enable the clock for the peripheral(s) to be used\r
-      (+) Configure the clock source(s) for peripherals which clocks are not\r
-          derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup RCC RCC\r
-  * @brief RCC HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_RCC_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Constants RCC Private Constants\r
- * @{\r
- */\r
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT\r
-#define HSI_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
-#define MSI_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-#define LSI_TIMEOUT_VALUE          17U   /* 17 ms (16 ms starting time + 1) */\r
-#else\r
-#define LSI_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-#define HSI48_TIMEOUT_VALUE        2U    /* 2 ms (minimum Tick + 1) */\r
-#define PLL_TIMEOUT_VALUE          2U    /* 2 ms (minimum Tick + 1) */\r
-#define CLOCKSWITCH_TIMEOUT_VALUE  5000U /* 5 s    */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Macros RCC Private Macros\r
-  * @{\r
-  */\r
-#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()\r
-#define MCO1_GPIO_PORT        GPIOA\r
-#define MCO1_PIN              GPIO_PIN_8\r
-\r
-#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \\r
-            (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup RCC_Private_Functions RCC Private Functions\r
-  * @{\r
-  */\r
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-static uint32_t          RCC_GetSysClockFreqFromPLLSource(void);\r
-#endif\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  *  @brief    Initialization and Configuration functions\r
-  *\r
-  @verbatim\r
- ===============================================================================\r
-           ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
-    [..]\r
-      This section provides functions allowing to configure the internal and external oscillators\r
-      (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1\r
-       and APB2).\r
-\r
-    [..] Internal/external clock and PLL configuration\r
-         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through\r
-             the PLL as System clock source.\r
-\r
-         (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.\r
-             It can be used to generate the clock for the USB OTG FS (48 MHz).\r
-             The number of flash wait states is automatically adjusted when MSI range is updated with\r
-             HAL_RCC_OscConfig() and the MSI is used as System clock source.\r
-\r
-         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC\r
-             clock source.\r
-\r
-         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or\r
-             through the PLL as System clock source. Can be used also optionally as RTC clock source.\r
-\r
-         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.\r
-\r
-         (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:\r
-           (++) The first output is used to generate the high speed system clock (up to 80MHz).\r
-           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
-                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
-           (++) The third output is used to generate an accurate clock to achieve\r
-                high-quality audio performance on SAI interface.\r
-\r
-         (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:\r
-           (++) The first output is used to generate SAR ADC1 clock.\r
-           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
-                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
-           (++) The Third output is used to generate an accurate clock to achieve\r
-                high-quality audio performance on SAI interface.\r
-\r
-         (+) PLLSAI2 (clocked by HSI, HSE or MSI) providing up to two independent output clocks:\r
-           (++) The first output is used to generate SAR ADC2 clock.\r
-           (++) The second  output is used to generate an accurate clock to achieve\r
-                high-quality audio performance on SAI interface.\r
-\r
-         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs\r
-            (HSE used directly or through PLL as System clock source), the System clock\r
-             is automatically switched to HSI and an interrupt is generated if enabled.\r
-             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)\r
-             exception vector.\r
-\r
-         (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or\r
-             main PLL clock (through a configurable prescaler) on PA8 pin.\r
-\r
-    [..] System, AHB and APB busses clocks configuration\r
-         (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
-             HSE and main PLL.\r
-             The AHB clock (HCLK) is derived from System clock through configurable\r
-             prescaler and used to clock the CPU, memory and peripherals mapped\r
-             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\r
-             from AHB clock through configurable prescalers and used to clock\r
-             the peripherals mapped on these busses. You can use\r
-             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.\r
-\r
-         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
-\r
-           (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or\r
-                from an external clock mapped on the SAI_CKIN pin.\r
-                You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.\r
-           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r
-                divided by 2 to 31.\r
-                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function\r
-                to configure this clock.\r
-           (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz\r
-                to work correctly, while the SDMMC1 and RNG peripherals require a frequency\r
-                equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1\r
-                through PLLQ divider. You have to enable the peripheral clock and use\r
-                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.\r
-           (+@) IWDG clock which is always the LSI clock.\r
-\r
-\r
-         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.\r
-             The clock source frequency should be adapted depending on the device voltage range\r
-             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.\r
-\r
-  @endverbatim\r
-\r
-           Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices\r
-           +--------------------------------------------------------+\r
-           | Latency         |     HCLK clock frequency (MHz)       |\r
-           |                 |--------------------------------------|\r
-           |                 |  voltage range 1  | voltage range 2  |\r
-           |                 |       1.2 V       |     1.0 V        |\r
-           |-----------------|-------------------|------------------|\r
-           |0WS(1 CPU cycles)|   0 < HCLK <= 20  |  0 < HCLK <= 8   |\r
-           |-----------------|-------------------|------------------|\r
-           |1WS(2 CPU cycles)|  20 < HCLK <= 40  |  8 < HCLK <= 16  |\r
-           |-----------------|-------------------|------------------|\r
-           |2WS(3 CPU cycles)|  40 < HCLK <= 60  | 16 < HCLK <= 26  |\r
-           |-----------------|-------------------|------------------|\r
-           |3WS(4 CPU cycles)|  60 < HCLK <= 80  | 16 < HCLK <= 26  |\r
-           |-----------------|-------------------|------------------|\r
-           |4WS(5 CPU cycles)|  80 < HCLK <= 100 | 16 < HCLK <= 26  |\r
-           |-----------------|-------------------|------------------|\r
-           |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26  |\r
-           +--------------------------------------------------------+\r
-\r
-           Table 2. HCLK clock frequency for other STM32L4 devices\r
-           +-------------------------------------------------------+\r
-           | Latency         |    HCLK clock frequency (MHz)       |\r
-           |                 |-------------------------------------|\r
-           |                 | voltage range 1  | voltage range 2  |\r
-           |                 |      1.2 V       |     1.0 V        |\r
-           |-----------------|------------------|------------------|\r
-           |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |\r
-           |-----------------|------------------|------------------|\r
-           |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |\r
-           |-----------------|------------------|------------------|\r
-           |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |\r
-           |-----------------|------------------|------------------|\r
-           |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |\r
-           |-----------------|------------------|------------------|\r
-           |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |\r
-           +-------------------------------------------------------+\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Reset the RCC clock configuration to the default reset state.\r
-  * @note   The default reset state of the clock configuration is given below:\r
-  *            - MSI ON and used as system clock source\r
-  *            - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF\r
-  *            - AHB, APB1 and APB2 prescalers set to 1.\r
-  *            - CSS, MCO1 OFF\r
-  *            - All interrupts disabled\r
-  *            - All interrupt and reset flags cleared\r
-  * @note   This function does not modify the configuration of the\r
-  *            - Peripheral clock sources\r
-  *            - LSI, LSE and RTC clocks (Backup domain)\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RCC_DeInit(void)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Reset to default System clock */\r
-  /* Set MSION bit */\r
-  SET_BIT(RCC->CR, RCC_CR_MSION);\r
-\r
-  /* Insure MSIRDY bit is set before writing default MSIRANGE value */\r
-  /* Get start tick */\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait till MSI is ready */\r
-  while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
-  {\r
-    if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-\r
-  /* Set MSIRANGE default value */\r
-  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);\r
-\r
-  /* Reset CFGR register (MSI is selected as system clock source) */\r
-  CLEAR_REG(RCC->CFGR);\r
-\r
-  /* Update the SystemCoreClock global variable for MSI as system clock source */\r
-  SystemCoreClock = MSI_VALUE;\r
-\r
-  /* Configure the source of time base considering new system clock settings  */\r
-  if(HAL_InitTick(uwTickPrio) != HAL_OK)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Insure MSI selected as system clock source */\r
-  /* Get start tick */\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait till system clock source is ready */\r
-  while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)\r
-  {\r
-    if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-\r
-  /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);\r
-\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);\r
-\r
-#else\r
-\r
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON);\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-  /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */\r
-  /* Get start tick */\r
-  tickstart = HAL_GetTick();\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)\r
-\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)\r
-\r
-#else\r
-\r
-  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
-\r
-#endif\r
-  {\r
-    if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-\r
-  /* Reset PLLCFGR register */\r
-  CLEAR_REG(RCC->PLLCFGR);\r
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-  /* Reset PLLSAI1CFGR register */\r
-  CLEAR_REG(RCC->PLLSAI1CFGR);\r
-  SET_BIT(RCC->PLLSAI1CFGR,  RCC_PLLSAI1CFGR_PLLSAI1N_4 );\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-  /* Reset PLLSAI2CFGR register */\r
-  CLEAR_REG(RCC->PLLSAI2CFGR);\r
-  SET_BIT(RCC->PLLSAI2CFGR,  RCC_PLLSAI2CFGR_PLLSAI2N_4 );\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-  /* Reset HSEBYP bit */\r
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
-\r
-  /* Disable all interrupts */\r
-  CLEAR_REG(RCC->CIER);\r
-\r
-  /* Clear all interrupt flags */\r
-  WRITE_REG(RCC->CICR, 0xFFFFFFFFU);\r
-\r
-  /* Clear all reset flags */\r
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initialize the RCC Oscillators according to the specified parameters in the\r
-  *         RCC_OscInitTypeDef.\r
-  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that\r
-  *         contains the configuration information for the RCC Oscillators.\r
-  * @note   The PLL is not disabled when used as system clock.\r
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
-  *         supported by this macro. User should request a transition to LSE Off\r
-  *         first and then LSE On or LSE Bypass.\r
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
-  *         supported by this macro. User should request a transition to HSE Off\r
-  *         first and then HSE On or HSE Bypass.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef status;\r
-  uint32_t sysclk_source, pll_config;\r
-\r
-  /* Check Null pointer */\r
-  if(RCC_OscInitStruct == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
-\r
-  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();\r
-  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();\r
-\r
-  /*----------------------------- MSI Configuration --------------------------*/\r
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));\r
-    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));\r
-    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));\r
-\r
-    /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */\r
-    if((sysclk_source == RCC_CFGR_SWS_MSI) ||\r
-       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))\r
-    {\r
-      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-       /* Otherwise, just the calibration and MSI range change are allowed */\r
-      else\r
-      {\r
-        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
-           must be correctly programmed according to the frequency of the CPU clock\r
-           (HCLK) and the supply voltage of the device. */\r
-        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())\r
-        {\r
-          /* First increase number of wait states update if necessary */\r
-          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
-          {\r
-            return HAL_ERROR;\r
-          }\r
-\r
-          /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
-          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
-          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
-          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
-        }\r
-        else\r
-        {\r
-          /* Else, keep current flash latency while decreasing applies */\r
-          /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
-          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
-          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
-          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
-\r
-          /* Decrease number of wait states update if necessary */\r
-          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
-          {\r
-            return HAL_ERROR;\r
-          }\r
-        }\r
-\r
-        /* Update the SystemCoreClock global variable */\r
-        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);\r
-\r
-        /* Configure the source of time base considering new system clocks settings*/\r
-        status = HAL_InitTick(uwTickPrio);\r
-        if(status != HAL_OK)\r
-        {\r
-          return status;\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Check the MSI State */\r
-      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)\r
-      {\r
-        /* Enable the Internal High Speed oscillator (MSI). */\r
-        __HAL_RCC_MSI_ENABLE();\r
-\r
-        /* Get timeout */\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till MSI is ready */\r
-        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-         /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
-        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
-         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
-        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
-\r
-      }\r
-      else\r
-      {\r
-        /* Disable the Internal High Speed oscillator (MSI). */\r
-        __HAL_RCC_MSI_DISABLE();\r
-\r
-        /* Get timeout */\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till MSI is ready */\r
-        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-      }\r
-    }\r
-  }\r
-  /*------------------------------- HSE Configuration ------------------------*/\r
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
-\r
-    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */\r
-    if((sysclk_source == RCC_CFGR_SWS_HSE) ||\r
-       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))\r
-    {\r
-      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Set the new HSE configuration ---------------------------------------*/\r
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
-\r
-      /* Check the HSE State */\r
-      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
-      {\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till HSE is ready */\r
-        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till HSE is disabled */\r
-        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-      }\r
-    }\r
-  }\r
-  /*----------------------------- HSI Configuration --------------------------*/\r
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
-    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
-\r
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\r
-    if((sysclk_source == RCC_CFGR_SWS_HSI) ||\r
-       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))\r
-    {\r
-      /* When HSI is used as system clock it will not be disabled */\r
-      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Otherwise, just the calibration is allowed */\r
-      else\r
-      {\r
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Check the HSI State */\r
-      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)\r
-      {\r
-        /* Enable the Internal High Speed oscillator (HSI). */\r
-        __HAL_RCC_HSI_ENABLE();\r
-\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till HSI is ready */\r
-        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-\r
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
-      }\r
-      else\r
-      {\r
-        /* Disable the Internal High Speed oscillator (HSI). */\r
-        __HAL_RCC_HSI_DISABLE();\r
-\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till HSI is disabled */\r
-        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-      }\r
-    }\r
-  }\r
-  /*------------------------------ LSI Configuration -------------------------*/\r
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
-\r
-    /* Check the LSI State */\r
-    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)\r
-    {\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-      uint32_t csr_temp = RCC->CSR;\r
-\r
-      /* Check LSI division factor */\r
-      assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv));\r
-\r
-      if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPREDIV))\r
-      {\r
-        if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \\r
-            ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION))\r
-        {\r
-           /* If LSIRDY is set while LSION is not enabled,\r
-              LSIPREDIV can't be updated  */\r
-          return HAL_ERROR;\r
-        }\r
-\r
-        /* Turn off LSI before changing RCC_CSR_LSIPREDIV */\r
-        if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION)\r
-        {\r
-          __HAL_RCC_LSI_DISABLE();\r
-\r
-          /* Get Start Tick*/\r
-          tickstart = HAL_GetTick();\r
-\r
-          /* Wait till LSI is disabled */\r
-          while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)\r
-          {\r
-            if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
-            {\r
-              return HAL_TIMEOUT;\r
-            }\r
-          }\r
-        }\r
-\r
-        /* Set LSI division factor */\r
-        MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);\r
-      }\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-      /* Enable the Internal Low Speed oscillator (LSI). */\r
-      __HAL_RCC_LSI_ENABLE();\r
-\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till LSI is ready */\r
-      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
-        {\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Disable the Internal Low Speed oscillator (LSI). */\r
-      __HAL_RCC_LSI_DISABLE();\r
-\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till LSI is disabled */\r
-      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
-        {\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-  }\r
-  /*------------------------------ LSE Configuration -------------------------*/\r
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
-  {\r
-    FlagStatus       pwrclkchanged = RESET;\r
-\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
-\r
-    /* Update LSE configuration in Backup Domain control register    */\r
-    /* Requires to enable write access to Backup Domain of necessary */\r
-    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))\r
-    {\r
-      __HAL_RCC_PWR_CLK_ENABLE();\r
-      pwrclkchanged = SET;\r
-    }\r
-\r
-    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
-    {\r
-      /* Enable write access to Backup domain */\r
-      SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
-\r
-      /* Wait for Backup domain Write protection disable */\r
-      tickstart = HAL_GetTick();\r
-\r
-      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
-      {\r
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
-        {\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-\r
-    /* Set the new LSE configuration -----------------------------------------*/\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-    if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)\r
-    {\r
-      /* Set LSESYSDIS bit according to LSE propagation option (enabled or disabled) */\r
-      MODIFY_REG(RCC->BDCR, RCC_BDCR_LSESYSDIS, (RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSDIS));\r
-\r
-      if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)\r
-      {\r
-        /* LSE oscillator bypass enable */\r
-        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\r
-        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
-      }\r
-      else\r
-      {\r
-        /* LSE oscillator enable */\r
-        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
-      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\r
-    }\r
-#else\r
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-\r
-    /* Check the LSE State */\r
-    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)\r
-    {\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till LSE is ready */\r
-      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
-        {\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till LSE is disabled */\r
-      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
-        {\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-      /* By default, stop disabling LSE propagation */\r
-      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-    }\r
-\r
-    /* Restore clock configuration if changed */\r
-    if(pwrclkchanged == SET)\r
-    {\r
-      __HAL_RCC_PWR_CLK_DISABLE();\r
-    }\r
-  }\r
-#if defined(RCC_HSI48_SUPPORT)\r
-  /*------------------------------ HSI48 Configuration -----------------------*/\r
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));\r
-\r
-    /* Check the LSI State */\r
-    if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)\r
-    {\r
-      /* Enable the Internal Low Speed oscillator (HSI48). */\r
-      __HAL_RCC_HSI48_ENABLE();\r
-\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till HSI48 is ready */\r
-      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)\r
-        {\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Disable the Internal Low Speed oscillator (HSI48). */\r
-      __HAL_RCC_HSI48_DISABLE();\r
-\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till HSI48 is disabled */\r
-      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)\r
-        {\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-  }\r
-#endif /* RCC_HSI48_SUPPORT */\r
-  /*-------------------------------- PLL Configuration -----------------------*/\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
-\r
-  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)\r
-  {\r
-    /* Check if the PLL is used as system clock or not */\r
-    if(sysclk_source != RCC_CFGR_SWS_PLL)\r
-    {\r
-      if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)\r
-      {\r
-        /* Check the parameters */\r
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
-        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
-#if defined(RCC_PLLP_SUPPORT)\r
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
-#endif /* RCC_PLLP_SUPPORT */\r
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
-        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r
-\r
-        /* Disable the main PLL. */\r
-        __HAL_RCC_PLL_DISABLE();\r
-\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till PLL is ready */\r
-        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-\r
-        /* Configure the main PLL clock source, multiplication and division factors. */\r
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
-                             RCC_OscInitStruct->PLL.PLLM,\r
-                             RCC_OscInitStruct->PLL.PLLN,\r
-#if defined(RCC_PLLP_SUPPORT)\r
-                             RCC_OscInitStruct->PLL.PLLP,\r
-#endif\r
-                             RCC_OscInitStruct->PLL.PLLQ,\r
-                             RCC_OscInitStruct->PLL.PLLR);\r
-\r
-        /* Enable the main PLL. */\r
-        __HAL_RCC_PLL_ENABLE();\r
-\r
-        /* Enable PLL System Clock output. */\r
-        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);\r
-\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till PLL is ready */\r
-        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Disable the main PLL. */\r
-        __HAL_RCC_PLL_DISABLE();\r
-\r
-        /* Disable all PLL outputs to save power if no PLLs on */\r
-#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY)\r
-        if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U)\r
-        {\r
-          MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
-        }\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-        if(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)\r
-        {\r
-          MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
-        }\r
-#else\r
-        MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
-#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);\r
-#else\r
-        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK);\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till PLL is disabled */\r
-        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
-          {\r
-            return HAL_TIMEOUT;\r
-          }\r
-        }\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Check if there is a request to disable the PLL used as System clock source */\r
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      else\r
-      {\r
-        pll_config = RCC->PLLCFGR;\r
-        /* Do not return HAL_ERROR if request repeats the current configuration */\r
-        if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||\r
-           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||\r
-           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||\r
-#if defined(RCC_PLLP_SUPPORT)\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-           (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||\r
-#else\r
-           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||\r
-#endif\r
-#endif\r
-           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||\r
-           (READ_BIT(pll_config, RCC_PLLCFGR_PLLR)    != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-      }\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initialize the CPU, AHB and APB busses clocks according to the specified\r
-  *         parameters in the RCC_ClkInitStruct.\r
-  * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that\r
-  *         contains the configuration information for the RCC peripheral.\r
-  * @param  FLatency  FLASH Latency\r
-  *          This parameter can be one of the following values:\r
-  *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle\r
-  *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle\r
-  *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycles\r
-  *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycles\r
-  *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycles\r
-  @if STM32L4S9xx\r
-  *            @arg FLASH_LATENCY_5   FLASH 5 Latency cycles\r
-  *            @arg FLASH_LATENCY_6   FLASH 6 Latency cycles\r
-  *            @arg FLASH_LATENCY_7   FLASH 7 Latency cycles\r
-  *            @arg FLASH_LATENCY_8   FLASH 8 Latency cycles\r
-  *            @arg FLASH_LATENCY_9   FLASH 9 Latency cycles\r
-  *            @arg FLASH_LATENCY_10  FLASH 10 Latency cycles\r
-  *            @arg FLASH_LATENCY_11  FLASH 11 Latency cycles\r
-  *            @arg FLASH_LATENCY_12  FLASH 12 Latency cycles\r
-  *            @arg FLASH_LATENCY_13  FLASH 13 Latency cycles\r
-  *            @arg FLASH_LATENCY_14  FLASH 14 Latency cycles\r
-  *            @arg FLASH_LATENCY_15  FLASH 15 Latency cycles\r
-  @endif\r
-  *\r
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
-  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function\r
-  *\r
-  * @note   The MSI is used by default as system clock source after\r
-  *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,\r
-  *         the MSI frequency is set to its default value 4 MHz.\r
-  *\r
-  * @note   The HSI can be selected as system clock source after\r
-  *         from STOP modes or in case of failure of the HSE used directly or indirectly\r
-  *         as system clock (if the Clock Security System CSS is enabled).\r
-  *\r
-  * @note   A switch from one clock source to another occurs only if the target\r
-  *         clock source is ready (clock stable after startup delay or PLL locked).\r
-  *         If a clock source which is not yet ready is selected, the switch will\r
-  *         occur when the clock source is ready.\r
-  *\r
-  * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is\r
-  *         currently used as system clock source.\r
-  *\r
-  * @note   Depending on the device voltage range, the software has to set correctly\r
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r
-  *         (for more details refer to section above "Initialization/de-initialization functions")\r
-  * @retval None\r
-  */\r
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)\r
-{\r
-  uint32_t tickstart;\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-  uint32_t hpre = RCC_SYSCLK_DIV1;\r
-#endif\r
-  HAL_StatusTypeDef status;\r
-\r
-  /* Check Null pointer */\r
-  if(RCC_ClkInitStruct == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
-  assert_param(IS_FLASH_LATENCY(FLatency));\r
-\r
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
-    must be correctly programmed according to the frequency of the CPU clock\r
-    (HCLK) and the supply voltage of the device. */\r
-\r
-  /* Increasing the number of wait states because of higher CPU frequency */\r
-  if(FLatency > __HAL_FLASH_GET_LATENCY())\r
-  {\r
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
-    __HAL_FLASH_SET_LATENCY(FLatency);\r
-\r
-    /* Check that the new number of wait states is taken into account to access the Flash\r
-    memory by reading the FLASH_ACR register */\r
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-  }\r
-\r
-  /*------------------------- SYSCLK Configuration ---------------------------*/\r
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
-  {\r
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
-\r
-    /* PLL is selected as System Clock Source */\r
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
-    {\r
-      /* Check the PLL ready flag */\r
-      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-      /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */\r
-      /* Compute target PLL output frequency */\r
-      if(RCC_GetSysClockFreqFromPLLSource() > 80000000U)\r
-      {\r
-        if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)\r
-        {\r
-          /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */\r
-          MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
-          hpre = RCC_SYSCLK_DIV2;\r
-        }\r
-        else if((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))\r
-        {\r
-          /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */\r
-          MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
-          hpre = RCC_SYSCLK_DIV2;\r
-        }\r
-        else\r
-        {\r
-          /* nothing to do */\r
-        }\r
-      }\r
-#endif\r
-    }\r
-    else\r
-    {\r
-      /* HSE is selected as System Clock Source */\r
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
-      {\r
-        /* Check the HSE ready flag */\r
-        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-      }\r
-      /* MSI is selected as System Clock Source */\r
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)\r
-      {\r
-        /* Check the MSI ready flag */\r
-        if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-      }\r
-      /* HSI is selected as System Clock Source */\r
-      else\r
-      {\r
-        /* Check the HSI ready flag */\r
-        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)\r
-        {\r
-          return HAL_ERROR;\r
-        }\r
-      }\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-      /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */\r
-      if(HAL_RCC_GetSysClockFreq() > 80000000U)\r
-      {\r
-        /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */\r
-        MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
-        hpre = RCC_SYSCLK_DIV2;\r
-      }\r
-#endif\r
-\r
-    }\r
-\r
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);\r
-\r
-    /* Get Start Tick*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))\r
-    {\r
-      if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
-      {\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-  }\r
-\r
-  /*-------------------------- HCLK Configuration --------------------------*/\r
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
-  {\r
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
-  }\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-  else\r
-  {\r
-    /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */\r
-    if(hpre == RCC_SYSCLK_DIV2)\r
-    {\r
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);\r
-    }\r
-  }\r
-#endif\r
-\r
-  /* Decreasing the number of wait states because of lower CPU frequency */\r
-  if(FLatency < __HAL_FLASH_GET_LATENCY())\r
-  {\r
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
-    __HAL_FLASH_SET_LATENCY(FLatency);\r
-\r
-    /* Check that the new number of wait states is taken into account to access the Flash\r
-    memory by reading the FLASH_ACR register */\r
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-  }\r
-\r
-  /*-------------------------- PCLK1 Configuration ---------------------------*/\r
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
-  {\r
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
-  }\r
-\r
-  /*-------------------------- PCLK2 Configuration ---------------------------*/\r
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
-  {\r
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));\r
-  }\r
-\r
-  /* Update the SystemCoreClock global variable */\r
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);\r
-\r
-  /* Configure the source of time base considering new system clocks settings*/\r
-  status = HAL_InitTick(uwTickPrio);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\r
- *  @brief   RCC clocks control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Peripheral Control functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to:\r
-\r
-    (+) Ouput clock to MCO pin.\r
-    (+) Retrieve current clock frequencies.\r
-    (+) Enable the Clock Security System.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Select the clock source to output on MCO pin(PA8).\r
-  * @note   PA8 should be configured in alternate function mode.\r
-  * @param  RCC_MCOx  specifies the output direction for the clock source.\r
-  *          For STM32L4xx family this parameter can have only one value:\r
-  *            @arg @ref RCC_MCO1  Clock source to output on MCO1 pin(PA8).\r
-  * @param  RCC_MCOSource  specifies the clock source to output.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO\r
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee\r
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source\r
-  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48\r
-  @endif\r
-  * @param  RCC_MCODiv  specifies the MCO prescaler.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock\r
-  *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock\r
-  *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock\r
-  *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock\r
-  *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock\r
-  * @retval None\r
-  */\r
-void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_MCO(RCC_MCOx));\r
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
-  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
-\r
-  /* Prevent unused argument(s) compilation warning if no assert_param check */\r
-  UNUSED(RCC_MCOx);\r
-\r
-  /* MCO Clock Enable */\r
-  __MCO1_CLK_ENABLE();\r
-\r
-  /* Configue the MCO1 pin in alternate function mode */\r
-  GPIO_InitStruct.Pin = MCO1_PIN;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
-  HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r
-\r
-  /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */\r
-  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv ));\r
-}\r
-\r
-/**\r
-  * @brief  Return the SYSCLK frequency.\r
-  *\r
-  * @note   The system frequency computed by this function is not the real\r
-  *         frequency in the chip. It is calculated based on the predefined\r
-  *         constant and the selected clock source:\r
-  * @note     If SYSCLK source is MSI, function returns values based on MSI\r
-  *             Value as defined by the MSI range.\r
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
-  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),\r
-  *           HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.\r
-  * @note     (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value\r
-  *               16 MHz) but the real value may vary depending on the variations\r
-  *               in voltage and temperature.\r
-  * @note     (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value\r
-  *                8 MHz), user has to ensure that HSE_VALUE is same as the real\r
-  *                frequency of the crystal used. Otherwise, this function may\r
-  *                have wrong result.\r
-  *\r
-  * @note   The result of this function could be not correct when using fractional\r
-  *         value for HSE crystal.\r
-  *\r
-  * @note   This function can be used by the user application to compute the\r
-  *         baudrate for the communication peripherals or configure other parameters.\r
-  *\r
-  * @note   Each time SYSCLK changes, this function must be called to update the\r
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
-  *\r
-  *\r
-  * @retval SYSCLK frequency\r
-  */\r
-uint32_t HAL_RCC_GetSysClockFreq(void)\r
-{\r
-  uint32_t msirange = 0U, sysclockfreq = 0U;\r
-  uint32_t pllvco, pllsource, pllr, pllm;    /* no init needed */\r
-  uint32_t sysclk_source, pll_oscsource;\r
-\r
-  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();\r
-  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();\r
-\r
-  if((sysclk_source == RCC_CFGR_SWS_MSI) ||\r
-     ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))\r
-  {\r
-    /* MSI or PLL with MSI source used as system clock source */\r
-\r
-    /* Get SYSCLK source */\r
-    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)\r
-    { /* MSISRANGE from RCC_CSR applies */\r
-      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;\r
-    }\r
-    else\r
-    { /* MSIRANGE from RCC_CR applies */\r
-      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;\r
-    }\r
-    /*MSI frequency range in HZ*/\r
-    msirange = MSIRangeTable[msirange];\r
-\r
-    if(sysclk_source == RCC_CFGR_SWS_MSI)\r
-    {\r
-      /* MSI used as system clock source */\r
-      sysclockfreq = msirange;\r
-    }\r
-  }\r
-  else if(sysclk_source == RCC_CFGR_SWS_HSI)\r
-  {\r
-    /* HSI used as system clock source */\r
-    sysclockfreq = HSI_VALUE;\r
-  }\r
-  else if(sysclk_source == RCC_CFGR_SWS_HSE)\r
-  {\r
-    /* HSE used as system clock source */\r
-    sysclockfreq = HSE_VALUE;\r
-  }\r
-  else\r
-  {\r
-    /* unexpected case: sysclockfreq at 0 */\r
-  }\r
-\r
-  if(sysclk_source == RCC_CFGR_SWS_PLL)\r
-  {\r
-    /* PLL used as system clock  source */\r
-\r
-    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM\r
-    SYSCLK = PLL_VCO / PLLR\r
-    */\r
-    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
-\r
-    switch (pllsource)\r
-    {\r
-    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\r
-      pllvco = HSI_VALUE;\r
-      break;\r
-\r
-    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\r
-      pllvco = HSE_VALUE;\r
-      break;\r
-\r
-    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */\r
-    default:\r
-      pllvco = msirange;\r
-      break;\r
-    }\r
-    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;\r
-    pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;\r
-    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;\r
-    sysclockfreq = pllvco / pllr;\r
-  }\r
-\r
-  return sysclockfreq;\r
-}\r
-\r
-/**\r
-  * @brief  Return the HCLK frequency.\r
-  * @note   Each time HCLK changes, this function must be called to update the\r
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
-  *\r
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.\r
-  * @retval HCLK frequency in Hz\r
-  */\r
-uint32_t HAL_RCC_GetHCLKFreq(void)\r
-{\r
-  return SystemCoreClock;\r
-}\r
-\r
-/**\r
-  * @brief  Return the PCLK1 frequency.\r
-  * @note   Each time PCLK1 changes, this function must be called to update the\r
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
-  * @retval PCLK1 frequency in Hz\r
-  */\r
-uint32_t HAL_RCC_GetPCLK1Freq(void)\r
-{\r
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
-  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));\r
-}\r
-\r
-/**\r
-  * @brief  Return the PCLK2 frequency.\r
-  * @note   Each time PCLK2 changes, this function must be called to update the\r
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
-  * @retval PCLK2 frequency in Hz\r
-  */\r
-uint32_t HAL_RCC_GetPCLK2Freq(void)\r
-{\r
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
-  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));\r
-}\r
-\r
-/**\r
-  * @brief  Configure the RCC_OscInitStruct according to the internal\r
-  *         RCC configuration registers.\r
-  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that\r
-  *         will be configured.\r
-  * @retval None\r
-  */\r
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(RCC_OscInitStruct != (void *)NULL);\r
-\r
-  /* Set all possible values for the Oscillator type parameter ---------------*/\r
-#if defined(RCC_HSI48_SUPPORT)\r
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \\r
-                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;\r
-#else\r
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \\r
-                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-  /* Get the HSE configuration -----------------------------------------------*/\r
-  if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
-  {\r
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
-  }\r
-  else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON)\r
-  {\r
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
-  }\r
-\r
-   /* Get the MSI configuration -----------------------------------------------*/\r
-  if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION)\r
-  {\r
-    RCC_OscInitStruct->MSIState = RCC_MSI_ON;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->MSIState = RCC_MSI_OFF;\r
-  }\r
-\r
-  RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos;\r
-  RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);\r
-\r
-  /* Get the HSI configuration -----------------------------------------------*/\r
-  if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION)\r
-  {\r
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
-  }\r
-\r
-  RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;\r
-\r
-  /* Get the LSE configuration -----------------------------------------------*/\r
-  if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
-  {\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-    if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)\r
-    {\r
-      RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;\r
-    }\r
-    else\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-    {\r
-      RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
-    }\r
-  }\r
-  else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
-  {\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-    if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)\r
-    {\r
-      RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;\r
-    }\r
-    else\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-    {\r
-      RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
-  }\r
-\r
-  /* Get the LSI configuration -----------------------------------------------*/\r
-  if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)\r
-  {\r
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
-  }\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-\r
-  /* Get the LSI configuration -----------------------------------------------*/\r
-  if((RCC->CSR & RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)\r
-  {\r
-    RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1;\r
-  }\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-  /* Get the HSI48 configuration ---------------------------------------------*/\r
-  if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)\r
-  {\r
-    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;\r
-  }\r
-#else\r
-  RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-  /* Get the PLL configuration -----------------------------------------------*/\r
-  if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)\r
-  {\r
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
-  }\r
-  RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
-  RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;\r
-  RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
-  RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);\r
-  RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U);\r
-#if defined(RCC_PLLP_SUPPORT)\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-  RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
-#else\r
-  if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
-  {\r
-    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;\r
-  }\r
-  else\r
-  {\r
-    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;\r
-  }\r
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
-#endif /* RCC_PLLP_SUPPORT */\r
-}\r
-\r
-/**\r
-  * @brief  Configure the RCC_ClkInitStruct according to the internal\r
-  *         RCC configuration registers.\r
-  * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that\r
-  *         will be configured.\r
-  * @param  pFLatency  Pointer on the Flash Latency.\r
-  * @retval None\r
-  */\r
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(RCC_ClkInitStruct != (void  *)NULL);\r
-  assert_param(pFLatency != (void *)NULL);\r
-\r
-  /* Set all possible values for the Clock type parameter --------------------*/\r
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
-\r
-  /* Get the SYSCLK configuration --------------------------------------------*/\r
-  RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);\r
-\r
-  /* Get the HCLK configuration ----------------------------------------------*/\r
-  RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);\r
-\r
-  /* Get the APB1 configuration ----------------------------------------------*/\r
-  RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);\r
-\r
-  /* Get the APB2 configuration ----------------------------------------------*/\r
-  RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);\r
-\r
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/\r
-  *pFLatency = __HAL_FLASH_GET_LATENCY();\r
-}\r
-\r
-/**\r
-  * @brief  Enable the Clock Security System.\r
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator\r
-  *         is automatically disabled and an interrupt is generated to inform the\r
-  *         software about the failure (Clock Security System Interrupt, CSSI),\r
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to\r
-  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.\r
-  * @note   The Clock Security System can only be cleared by reset.\r
-  * @retval None\r
-  */\r
-void HAL_RCC_EnableCSS(void)\r
-{\r
-  SET_BIT(RCC->CR, RCC_CR_CSSON) ;\r
-}\r
-\r
-/**\r
-  * @brief Handle the RCC Clock Security System interrupt request.\r
-  * @note This API should be called under the NMI_Handler().\r
-  * @retval None\r
-  */\r
-void HAL_RCC_NMI_IRQHandler(void)\r
-{\r
-  /* Check RCC CSSF interrupt flag  */\r
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
-  {\r
-    /* RCC Clock Security System interrupt user callback */\r
-    HAL_RCC_CSSCallback();\r
-\r
-    /* Clear RCC CSS pending bit */\r
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  RCC Clock Security System interrupt callback.\r
-  * @retval none\r
-  */\r
-__weak void HAL_RCC_CSSCallback(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_RCC_CSSCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @addtogroup RCC_Private_Functions\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Update number of Flash wait states in line with MSI range and current\r
-            voltage range.\r
-  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)\r
-{\r
-  uint32_t vos;\r
-  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */\r
-\r
-  if(__HAL_RCC_PWR_IS_CLK_ENABLED())\r
-  {\r
-    vos = HAL_PWREx_GetVoltageRange();\r
-  }\r
-  else\r
-  {\r
-    __HAL_RCC_PWR_CLK_ENABLE();\r
-    vos = HAL_PWREx_GetVoltageRange();\r
-    __HAL_RCC_PWR_CLK_DISABLE();\r
-  }\r
-\r
-  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)\r
-  {\r
-    if(msirange > RCC_MSIRANGE_8)\r
-    {\r
-      /* MSI > 16Mhz */\r
-      if(msirange > RCC_MSIRANGE_10)\r
-      {\r
-        /* MSI 48Mhz */\r
-        latency = FLASH_LATENCY_2; /* 2WS */\r
-      }\r
-      else\r
-      {\r
-        /* MSI 24Mhz or 32Mhz */\r
-        latency = FLASH_LATENCY_1; /* 1WS */\r
-      }\r
-    }\r
-    /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */\r
-  }\r
-  else\r
-  {\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-    if(msirange >= RCC_MSIRANGE_8)\r
-    {\r
-      /* MSI >= 16Mhz */\r
-      latency = FLASH_LATENCY_2; /* 2WS */\r
-    }\r
-    else\r
-    {\r
-      if(msirange == RCC_MSIRANGE_7)\r
-      {\r
-        /* MSI 8Mhz */\r
-        latency = FLASH_LATENCY_1; /* 1WS */\r
-      }\r
-      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */\r
-    }\r
-#else\r
-    if(msirange > RCC_MSIRANGE_8)\r
-    {\r
-      /* MSI > 16Mhz */\r
-      latency = FLASH_LATENCY_3; /* 3WS */\r
-    }\r
-    else\r
-    {\r
-      if(msirange == RCC_MSIRANGE_8)\r
-      {\r
-        /* MSI 16Mhz */\r
-        latency = FLASH_LATENCY_2; /* 2WS */\r
-      }\r
-      else if(msirange == RCC_MSIRANGE_7)\r
-      {\r
-        /* MSI 8Mhz */\r
-        latency = FLASH_LATENCY_1; /* 1WS */\r
-      }\r
-      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */\r
-    }\r
-#endif\r
-  }\r
-\r
-  __HAL_FLASH_SET_LATENCY(latency);\r
-\r
-  /* Check that the new number of wait states is taken into account to access the Flash\r
-     memory by reading the FLASH_ACR register */\r
-  if(__HAL_FLASH_GET_LATENCY() != latency)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-/**\r
-  * @brief  Compute SYSCLK frequency based on PLL SYSCLK source.\r
-  * @retval SYSCLK frequency\r
-  */\r
-static uint32_t RCC_GetSysClockFreqFromPLLSource(void)\r
-{\r
-  uint32_t msirange = 0U;\r
-  uint32_t pllvco, pllsource, pllr, pllm, sysclockfreq;  /* no init needed */\r
-\r
-  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)\r
-  {\r
-    /* Get MSI range source */\r
-    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)\r
-    { /* MSISRANGE from RCC_CSR applies */\r
-      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;\r
-    }\r
-    else\r
-    { /* MSIRANGE from RCC_CR applies */\r
-      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;\r
-    }\r
-    /*MSI frequency range in HZ*/\r
-    msirange = MSIRangeTable[msirange];\r
-  }\r
-\r
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM\r
-     SYSCLK = PLL_VCO / PLLR\r
-   */\r
-  pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
-\r
-  switch (pllsource)\r
-  {\r
-  case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\r
-    pllvco = HSI_VALUE;\r
-    break;\r
-\r
-  case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\r
-    pllvco = HSE_VALUE;\r
-    break;\r
-\r
-  case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */\r
-  default:\r
-    pllvco = msirange;\r
-    break;\r
-  }\r
-  pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;\r
-  pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;\r
-  pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;\r
-  sysclockfreq = pllvco / pllr;\r
-\r
-  return sysclockfreq;\r
-}\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_RCC_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
deleted file mode 100644 (file)
index 2dc8462..0000000
+++ /dev/null
@@ -1,3538 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_rcc_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   Extended RCC HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities RCC extended peripheral:\r
-  *           + Extended Peripheral Control functions\r
-  *           + Extended Clock management functions\r
-  *           + Extended Clock Recovery System Control functions\r
-  *\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup RCCEx RCCEx\r
-  * @brief RCC Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_RCC_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private defines -----------------------------------------------------------*/\r
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants\r
- * @{\r
- */\r
-#define PLLSAI1_TIMEOUT_VALUE     2U    /* 2 ms (minimum Tick + 1) */\r
-#define PLLSAI2_TIMEOUT_VALUE     2U    /* 2 ms (minimum Tick + 1) */\r
-#define PLL_TIMEOUT_VALUE         2U    /* 2 ms (minimum Tick + 1) */\r
-\r
-#define DIVIDER_P_UPDATE          0U\r
-#define DIVIDER_Q_UPDATE          1U\r
-#define DIVIDER_R_UPDATE          2U\r
-\r
-#define __LSCO_CLK_ENABLE()       __HAL_RCC_GPIOA_CLK_ENABLE()\r
-#define LSCO_GPIO_PORT            GPIOA\r
-#define LSCO_PIN                  GPIO_PIN_2\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup RCCEx_Private_Functions RCCEx Private Functions\r
- * @{\r
- */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider);\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider);\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#if defined(SAI1)\r
-\r
-static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency);\r
-\r
-#endif /* SAI1 */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions\r
- *  @brief  Extended Peripheral Control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                ##### Extended Peripheral Control functions  #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to control the RCC Clocks\r
-    frequencies.\r
-    [..]\r
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
-        select the RTC clock source; in this case the Backup domain will be reset in\r
-        order to modify the RTC Clock source, as consequence RTC registers (including\r
-        the backup registers) are set to their reset values.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initialize the RCC extended peripherals clocks according to the specified\r
-  *         parameters in the RCC_PeriphCLKInitTypeDef.\r
-  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that\r
-  *         contains a field PeriphClockSelection which can be a combination of the following values:\r
-  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock\r
-  @if STM32L462xx\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)\r
-  @endif\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock\r
-  @if STM32L462xx\r
-  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock (only for devices with SAI1)\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
-  @endif\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock\r
-  @if STM32L462xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
-  @endif\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
-  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
-  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
-  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral kernel clock (only for devices with DFSDM1)\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO  DFSDM1 peripheral audio clock (only for devices with DFSDM1)\r
-  *            @arg @ref RCC_PERIPHCLK_LTDC  LTDC peripheral clock (only for devices with LTDC)\r
-  *            @arg @ref RCC_PERIPHCLK_DSI  DSI peripheral clock (only for devices with DSI)\r
-  *            @arg @ref RCC_PERIPHCLK_OSPI  OctoSPI peripheral clock (only for devices with OctoSPI)\r
-  @endif\r
-  *\r
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\r
-  *         the RTC clock source: in this case the access to Backup domain is enabled.\r
-  *\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r
-{\r
-  uint32_t tmpregister, tickstart;     /* no init needed */\r
-  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */\r
-  HAL_StatusTypeDef status = HAL_OK;   /* Final status */\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
-\r
-#if defined(SAI1)\r
-\r
-  /*-------------------------- SAI1 clock source configuration ---------------------*/\r
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));\r
-\r
-    switch(PeriphClkInit->Sai1ClockSelection)\r
-    {\r
-    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/\r
-      /* Enable SAI Clock output generated form System PLL . */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);\r
-#else\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-      /* SAI1 clock source config set later after clock selection check */\r
-      break;\r
-\r
-    case RCC_SAI1CLKSOURCE_PLLSAI1:  /* PLLSAI1 is used as clock source for SAI1*/\r
-      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */\r
-      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);\r
-      /* SAI1 clock source config set later after clock selection check */\r
-      break;\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-    case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/\r
-      /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */\r
-      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);\r
-      /* SAI1 clock source config set later after clock selection check */\r
-      break;\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-    case RCC_SAI1CLKSOURCE_PIN:      /* External clock is used as source of SAI1 clock*/\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-    case RCC_SAI1CLKSOURCE_HSI:      /* HSI is used as source of SAI1 clock*/\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-      /* SAI1 clock source config set later after clock selection check */\r
-      break;\r
-\r
-    default:\r
-      ret = HAL_ERROR;\r
-      break;\r
-    }\r
-\r
-    if(ret == HAL_OK)\r
-    {\r
-      /* Set the source of SAI1 clock*/\r
-      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r
-    }\r
-    else\r
-    {\r
-      /* set overall return value */\r
-      status = ret;\r
-    }\r
-  }\r
-\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-\r
-  /*-------------------------- SAI2 clock source configuration ---------------------*/\r
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));\r
-\r
-    switch(PeriphClkInit->Sai2ClockSelection)\r
-    {\r
-    case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/\r
-      /* Enable SAI Clock output generated form System PLL . */\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);\r
-      /* SAI2 clock source config set later after clock selection check */\r
-      break;\r
-\r
-    case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/\r
-      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */\r
-      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);\r
-      /* SAI2 clock source config set later after clock selection check */\r
-      break;\r
-\r
-    case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/\r
-      /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */\r
-      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);\r
-      /* SAI2 clock source config set later after clock selection check */\r
-      break;\r
-\r
-    case RCC_SAI2CLKSOURCE_PIN:      /* External clock is used as source of SAI2 clock*/\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-    case RCC_SAI2CLKSOURCE_HSI:      /* HSI is used as source of SAI2 clock*/\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-      /* SAI2 clock source config set later after clock selection check */\r
-      break;\r
-\r
-    default:\r
-      ret = HAL_ERROR;\r
-      break;\r
-    }\r
-\r
-    if(ret == HAL_OK)\r
-    {\r
-      /* Set the source of SAI2 clock*/\r
-      __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r
-    }\r
-    else\r
-    {\r
-      /* set overall return value */\r
-      status = ret;\r
-    }\r
-  }\r
-#endif /* SAI2 */\r
-\r
-  /*-------------------------- RTC clock source configuration ----------------------*/\r
-  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)\r
-  {\r
-    FlagStatus       pwrclkchanged = RESET;\r
-\r
-    /* Check for RTC Parameters used to output RTCCLK */\r
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
-\r
-    /* Enable Power Clock */\r
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)\r
-    {\r
-      __HAL_RCC_PWR_CLK_ENABLE();\r
-      pwrclkchanged = SET;\r
-    }\r
-\r
-    /* Enable write access to Backup domain */\r
-    SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
-\r
-    /* Wait for Backup domain Write protection disable */\r
-    tickstart = HAL_GetTick();\r
-\r
-    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)\r
-    {\r
-      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
-      {\r
-        ret = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-\r
-    if(ret == HAL_OK)\r
-    {\r
-      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */\r
-      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);\r
-\r
-      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))\r
-      {\r
-        /* Store the content of BDCR register before the reset of Backup Domain */\r
-        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));\r
-        /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
-        __HAL_RCC_BACKUPRESET_FORCE();\r
-        __HAL_RCC_BACKUPRESET_RELEASE();\r
-        /* Restore the Content of BDCR register */\r
-        RCC->BDCR = tmpregister;\r
-      }\r
-\r
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r
-      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))\r
-      {\r
-        /* Get Start Tick*/\r
-        tickstart = HAL_GetTick();\r
-\r
-        /* Wait till LSE is ready */\r
-        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)\r
-        {\r
-          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
-          {\r
-            ret = HAL_TIMEOUT;\r
-            break;\r
-          }\r
-        }\r
-      }\r
-\r
-      if(ret == HAL_OK)\r
-      {\r
-        /* Apply new RTC clock source selection */\r
-        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r
-      }\r
-      else\r
-      {\r
-        /* set overall return value */\r
-        status = ret;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* set overall return value */\r
-      status = ret;\r
-    }\r
-\r
-    /* Restore clock configuration if changed */\r
-    if(pwrclkchanged == SET)\r
-    {\r
-      __HAL_RCC_PWR_CLK_DISABLE();\r
-    }\r
-  }\r
-\r
-  /*-------------------------- USART1 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r
-\r
-    /* Configure the USART1 clock source */\r
-    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r
-  }\r
-\r
-  /*-------------------------- USART2 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r
-\r
-    /* Configure the USART2 clock source */\r
-    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r
-  }\r
-\r
-#if defined(USART3)\r
-\r
-  /*-------------------------- USART3 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r
-\r
-    /* Configure the USART3 clock source */\r
-    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r
-  }\r
-\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-\r
-  /*-------------------------- UART4 clock source configuration --------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r
-\r
-    /* Configure the UART4 clock source */\r
-    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r
-  }\r
-\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-\r
-  /*-------------------------- UART5 clock source configuration --------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r
-\r
-    /* Configure the UART5 clock source */\r
-    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r
-  }\r
-\r
-#endif /* UART5 */\r
-\r
-  /*-------------------------- LPUART1 clock source configuration ------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));\r
-\r
-    /* Configure the LPUAR1 clock source */\r
-    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);\r
-  }\r
-\r
-  /*-------------------------- LPTIM1 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))\r
-  {\r
-    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r
-    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r
-  }\r
-\r
-  /*-------------------------- LPTIM2 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))\r
-  {\r
-    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));\r
-    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);\r
-  }\r
-\r
-  /*-------------------------- I2C1 clock source configuration ---------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r
-\r
-    /* Configure the I2C1 clock source */\r
-    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r
-  }\r
-\r
-#if defined(I2C2)\r
-\r
-  /*-------------------------- I2C2 clock source configuration ---------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r
-\r
-    /* Configure the I2C2 clock source */\r
-    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r
-  }\r
-\r
-#endif /* I2C2 */\r
-\r
-  /*-------------------------- I2C3 clock source configuration ---------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r
-\r
-    /* Configure the I2C3 clock source */\r
-    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r
-  }\r
-\r
-#if defined(I2C4)\r
-\r
-  /*-------------------------- I2C4 clock source configuration ---------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r
-\r
-    /* Configure the I2C4 clock source */\r
-    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r
-  }\r
-\r
-#endif /* I2C4 */\r
-\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-\r
-  /*-------------------------- USB clock source configuration ----------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))\r
-  {\r
-    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));\r
-    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);\r
-\r
-    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)\r
-    {\r
-      /* Enable PLL48M1CLK output */\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
-    }\r
-    else\r
-    {\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-      if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)\r
-      {\r
-        /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */\r
-        ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);\r
-\r
-        if(ret != HAL_OK)\r
-        {\r
-          /* set overall return value */\r
-          status = ret;\r
-        }\r
-      }\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-    }\r
-  }\r
-\r
-#endif /* USB_OTG_FS || USB */\r
-\r
-#if defined(SDMMC1)\r
-\r
-  /*-------------------------- SDMMC1 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))\r
-  {\r
-    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r
-    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r
-\r
-    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)   /* PLL "Q" ? */\r
-    {\r
-      /* Enable PLL48M1CLK output */\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
-    }\r
-#if defined(RCC_CCIPR2_SDMMCSEL)\r
-    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */\r
-    {\r
-      /* Enable PLLSAI3CLK output */\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);\r
-    }\r
-#endif\r
-    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)\r
-    {\r
-      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */\r
-      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);\r
-\r
-      if(ret != HAL_OK)\r
-      {\r
-        /* set overall return value */\r
-        status = ret;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* nothing to do */\r
-    }\r
-  }\r
-\r
-#endif /* SDMMC1 */\r
-\r
-  /*-------------------------- RNG clock source configuration ----------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))\r
-  {\r
-    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));\r
-    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);\r
-\r
-    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)\r
-    {\r
-      /* Enable PLL48M1CLK output */\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
-    }\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)\r
-    {\r
-      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */\r
-      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);\r
-\r
-      if(ret != HAL_OK)\r
-      {\r
-        /* set overall return value */\r
-        status = ret;\r
-      }\r
-    }\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-    else\r
-    {\r
-      /* nothing to do */\r
-    }\r
-  }\r
-\r
-  /*-------------------------- ADC clock source configuration ----------------------*/\r
-#if !defined(STM32L412xx) && !defined(STM32L422xx)\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));\r
-\r
-    /* Configure the ADC interface clock source */\r
-    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)\r
-    {\r
-      /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */\r
-      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);\r
-\r
-      if(ret != HAL_OK)\r
-      {\r
-        /* set overall return value */\r
-        status = ret;\r
-      }\r
-    }\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-\r
-    else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)\r
-    {\r
-      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */\r
-      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);\r
-\r
-      if(ret != HAL_OK)\r
-      {\r
-        /* set overall return value */\r
-        status = ret;\r
-      }\r
-    }\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-\r
-  }\r
-#endif /* !STM32L412xx && !STM32L422xx */\r
-\r
-#if defined(SWPMI1)\r
-\r
-  /*-------------------------- SWPMI1 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));\r
-\r
-    /* Configure the SWPMI1 clock source */\r
-    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);\r
-  }\r
-\r
-#endif /* SWPMI1 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-\r
-  /*-------------------------- DFSDM1 clock source configuration -------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\r
-\r
-    /* Configure the DFSDM1 interface clock source */\r
-    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\r
-  }\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-  /*-------------------------- DFSDM1 audio clock source configuration -------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));\r
-\r
-    /* Configure the DFSDM1 interface audio clock source */\r
-    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);\r
-  }\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-\r
-  /*-------------------------- LTDC clock source configuration --------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection));\r
-\r
-    /* Disable the PLLSAI2 */\r
-    __HAL_RCC_PLLSAI2_DISABLE();\r
-\r
-    /* Get Start Tick*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait till PLLSAI2 is ready */\r
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
-    {\r
-      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
-      {\r
-        ret = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-\r
-    if(ret == HAL_OK)\r
-    {\r
-      /* Configure the LTDC clock source */\r
-      __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection);\r
-\r
-      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */\r
-      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);\r
-    }\r
-\r
-    if(ret != HAL_OK)\r
-    {\r
-      /* set overall return value */\r
-      status = ret;\r
-    }\r
-  }\r
-\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-\r
-  /*-------------------------- DSI clock source configuration ---------------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));\r
-\r
-    /* Configure the DSI clock source */\r
-    __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);\r
-\r
-    if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2)\r
-    {\r
-      /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */\r
-      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE);\r
-\r
-      if(ret != HAL_OK)\r
-      {\r
-        /* set overall return value */\r
-        status = ret;\r
-      }\r
-    }\r
-  }\r
-\r
-#endif /* DSI */\r
-\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-\r
-  /*-------------------------- OctoSPIx clock source configuration ----------------*/\r
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection));\r
-\r
-    /* Configure the OctoSPI clock source */\r
-    __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);\r
-\r
-    if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL)\r
-    {\r
-      /* Enable PLL48M1CLK output */\r
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);\r
-    }\r
-  }\r
-\r
-#endif /* OCTOSPI1 || OCTOSPI2 */\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.\r
-  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that\r
-  *         returns the configuration information for the Extended Peripherals\r
-  *         clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART,\r
-  *         USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r
-{\r
-  /* Set all possible values for the extended clock type parameter------------*/\r
-\r
-#if defined(STM32L412xx) || defined(STM32L422xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 |                                               RCC_PERIPHCLK_USB    | \\r
-                                                                RCC_PERIPHCLK_RNG    |                                                                      \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L431xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                                               \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L432xx) || defined(STM32L442xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 |                                                                      \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   |                        RCC_PERIPHCLK_I2C3   |                        \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \\r
-                                                                RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L433xx) || defined(STM32L443xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L451xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  |                        \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                                               \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    |                        RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L452xx) || defined(STM32L462xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  |                        \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    |                        RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L471xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3                          | \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2                          | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L496xx) || defined(STM32L4A6xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_RTC ;\r
-\r
-#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC                           | RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI;\r
-\r
-#elif defined(STM32L4R7xx) || defined(STM32L4S7xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC                           | RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI  | RCC_PERIPHCLK_LTDC;\r
-\r
-#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)\r
-\r
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \\r
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \\r
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \\r
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC                           | RCC_PERIPHCLK_DFSDM1 | \\r
-                                        RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI  | RCC_PERIPHCLK_LTDC   | RCC_PERIPHCLK_DSI;\r
-\r
-#endif /* STM32L431xx */\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-  /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/\r
-\r
-  PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos;\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U;\r
-#else\r
-  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-  PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
-  PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U;\r
-  PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U;\r
-  PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U;\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-  /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/\r
-\r
-  PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-  PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U;\r
-#else\r
-  PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
-  PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;\r
-  PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U;\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-  PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U;\r
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
-  PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U;\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-  /* Get the USART1 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();\r
-  /* Get the USART2 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();\r
-\r
-#if defined(USART3)\r
-  /* Get the USART3 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-  /* Get the UART4 clock source ----------------------------------------------*/\r
-  PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-  /* Get the UART5 clock source ----------------------------------------------*/\r
-  PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();\r
-#endif /* UART5 */\r
-\r
-  /* Get the LPUART1 clock source --------------------------------------------*/\r
-  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();\r
-\r
-  /* Get the I2C1 clock source -----------------------------------------------*/\r
-  PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();\r
-\r
-#if defined(I2C2)\r
-   /* Get the I2C2 clock source ----------------------------------------------*/\r
-  PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();\r
-#endif /* I2C2 */\r
-\r
-  /* Get the I2C3 clock source -----------------------------------------------*/\r
-  PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();\r
-\r
-#if defined(I2C4)\r
-  /* Get the I2C4 clock source -----------------------------------------------*/\r
-  PeriphClkInit->I2c4ClockSelection    = __HAL_RCC_GET_I2C4_SOURCE();\r
-#endif /* I2C4 */\r
-\r
-  /* Get the LPTIM1 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();\r
-\r
-  /* Get the LPTIM2 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Lptim2ClockSelection  = __HAL_RCC_GET_LPTIM2_SOURCE();\r
-\r
-#if defined(SAI1)\r
-  /* Get the SAI1 clock source -----------------------------------------------*/\r
-  PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-  /* Get the SAI2 clock source -----------------------------------------------*/\r
-  PeriphClkInit->Sai2ClockSelection    = __HAL_RCC_GET_SAI2_SOURCE();\r
-#endif /* SAI2 */\r
-\r
-  /* Get the RTC clock source ------------------------------------------------*/\r
-  PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();\r
-\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-  /* Get the USB clock source ------------------------------------------------*/\r
-  PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();\r
-#endif /* USB_OTG_FS || USB */\r
-\r
-#if defined(SDMMC1)\r
-  /* Get the SDMMC1 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Sdmmc1ClockSelection   = __HAL_RCC_GET_SDMMC1_SOURCE();\r
-#endif /* SDMMC1 */\r
-\r
-  /* Get the RNG clock source ------------------------------------------------*/\r
-  PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();\r
-\r
-#if !defined(STM32L412xx) && !defined(STM32L422xx)\r
-  /* Get the ADC clock source ------------------------------------------------*/\r
-  PeriphClkInit->AdcClockSelection     = __HAL_RCC_GET_ADC_SOURCE();\r
-#endif /* !STM32L412xx && !STM32L422xx */\r
-\r
-#if defined(SWPMI1)\r
-  /* Get the SWPMI1 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Swpmi1ClockSelection  = __HAL_RCC_GET_SWPMI1_SOURCE();\r
-#endif /* SWPMI1 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-  /* Get the DFSDM1 clock source ---------------------------------------------*/\r
-  PeriphClkInit->Dfsdm1ClockSelection  = __HAL_RCC_GET_DFSDM1_SOURCE();\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-  /* Get the DFSDM1 audio clock source ---------------------------------------*/\r
-  PeriphClkInit->Dfsdm1AudioClockSelection  = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-  /* Get the LTDC clock source -----------------------------------------------*/\r
-  PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-  /* Get the DSI clock source ------------------------------------------------*/\r
-  PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();\r
-#endif /* DSI */\r
-\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-  /* Get the OctoSPIclock source --------------------------------------------*/\r
-  PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();\r
-#endif /* OCTOSPI1 || OCTOSPI2 */\r
-}\r
-\r
-/**\r
-  * @brief  Return the peripheral clock frequency for peripherals with clock source from PLLSAIs\r
-  * @note   Return 0 if peripheral clock identifier not managed by this API\r
-  * @param  PeriphClk  Peripheral clock identifier\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock\r
-  @if STM32L462xx\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)\r
-  @endif\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock\r
-  @if STM32L462xx\r
-  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock (only for devices with SAI1)\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock\r
-  @if STM32L443xx\r
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
-  @endif\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)\r
-  @endif\r
-  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock\r
-  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock\r
-  @if STM32L462xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)\r
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
-  @endif\r
-  @if STM32L486xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)\r
-  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)\r
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
-  @endif\r
-  @if STM32L4A6xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)\r
-  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)\r
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
-  @endif\r
-  @if STM32L4S9xx\r
-  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)\r
-  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)\r
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral kernel clock (only for devices with DFSDM1)\r
-  *            @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO  DFSDM1 peripheral audio clock (only for devices with DFSDM1)\r
-  *            @arg @ref RCC_PERIPHCLK_LTDC  LTDC peripheral clock (only for devices with LTDC)\r
-  *            @arg @ref RCC_PERIPHCLK_DSI  DSI peripheral clock (only for devices with DSI)\r
-  *            @arg @ref RCC_PERIPHCLK_OSPI  OctoSPI peripheral clock (only for devices with OctoSPI)\r
-  @endif\r
-  * @retval Frequency in Hz\r
-  */\r
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
-{\r
-  uint32_t frequency = 0U;\r
-  uint32_t srcclk, pll_oscsource, pllvco, plln;    /* no init needed */\r
-#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)\r
-  uint32_t pllp;  /* no init needed */\r
-#endif\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));\r
-\r
-  if(PeriphClk == RCC_PERIPHCLK_RTC)\r
-  {\r
-    /* Get the current RTC source */\r
-    srcclk = __HAL_RCC_GET_RTC_SOURCE();\r
-\r
-    switch(srcclk)\r
-    {\r
-    case RCC_RTCCLKSOURCE_LSE:\r
-      /* Check if LSE is ready */\r
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-      {\r
-        frequency = LSE_VALUE;\r
-      }\r
-      break;\r
-    case RCC_RTCCLKSOURCE_LSI:\r
-      /* Check if LSI is ready */\r
-      if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))\r
-      {\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-        if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))\r
-        {\r
-          frequency = LSI_VALUE/128U;\r
-        }\r
-        else\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-        {\r
-          frequency = LSI_VALUE;\r
-        }\r
-      }\r
-      break;\r
-    case RCC_RTCCLKSOURCE_HSE_DIV32:\r
-      /* Check if HSE is ready */\r
-      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))\r
-      {\r
-        frequency = HSE_VALUE / 32U;\r
-      }\r
-      break;\r
-    default:\r
-      /* No clock source, frequency default init at 0 */\r
-      break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Other external peripheral clock source than RTC */\r
-    pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();\r
-\r
-    /* Compute PLL clock input */\r
-    switch(pll_oscsource)\r
-    {\r
-    case RCC_PLLSOURCE_MSI:   /* MSI ? */\r
-      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
-      {\r
-        /*MSI frequency range in HZ*/\r
-        pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
-      }\r
-      else\r
-      {\r
-        pllvco = 0U;\r
-      }\r
-      break;\r
-    case RCC_PLLSOURCE_HSI:   /* HSI ? */\r
-      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-      {\r
-        pllvco = HSI_VALUE;\r
-      }\r
-      else\r
-      {\r
-        pllvco = 0U;\r
-      }\r
-      break;\r
-    case RCC_PLLSOURCE_HSE:   /* HSE ? */\r
-      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))\r
-      {\r
-        pllvco = HSE_VALUE;\r
-      }\r
-      else\r
-      {\r
-        pllvco = 0U;\r
-      }\r
-      break;\r
-    default:\r
-      /* No source */\r
-      pllvco = 0U;\r
-      break;\r
-    }\r
-\r
-    switch(PeriphClk)\r
-    {\r
-#if defined(SAI1)\r
-\r
-    case RCC_PERIPHCLK_SAI1:\r
-      frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);\r
-      break;\r
-\r
-#endif\r
-\r
-#if defined(SAI2)\r
-\r
-    case RCC_PERIPHCLK_SAI2:\r
-      frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco);\r
-      break;\r
-\r
-#endif\r
-\r
-#if defined(USB_OTG_FS) || defined(USB)\r
-\r
-    case RCC_PERIPHCLK_USB:\r
-\r
-#endif /* USB_OTG_FS || USB */\r
-\r
-    case RCC_PERIPHCLK_RNG:\r
-\r
-#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL)\r
-\r
-    case RCC_PERIPHCLK_SDMMC1:\r
-\r
-#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */\r
-      {\r
-        srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_CCIPR_CLK48SEL:   /* MSI ? */\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
-          {\r
-            /*MSI frequency range in HZ*/\r
-            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
-          }\r
-          break;\r
-        case RCC_CCIPR_CLK48SEL_1:  /* PLL ? */\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
-          {\r
-            if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))\r
-            {\r
-              /* f(PLL Source) * PLLN / PLLM */\r
-              plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
-              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-              /* f(PLL48M1CLK) = f(VCO input) / PLLQ */\r
-              frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));\r
-            }\r
-          }\r
-          break;\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-        case RCC_CCIPR_CLK48SEL_0:  /* PLLSAI1 ? */\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))\r
-          {\r
-            if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))\r
-            {\r
-              plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-              /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
-              /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */\r
-              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
-#else\r
-              /* f(PLL Source) * PLLSAI1N / PLLM */\r
-              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-#endif\r
-              /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */\r
-              frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));\r
-            }\r
-          }\r
-          break;\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-        case 0U:\r
-          if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */\r
-          {\r
-            frequency = HSI48_VALUE;\r
-          }\r
-          break;\r
-#endif /* RCC_HSI48_SUPPORT */\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        } /* switch(srcclk) */\r
-        break;\r
-      }\r
-\r
-#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)\r
-\r
-    case RCC_PERIPHCLK_SDMMC1:\r
-\r
-      if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL))  /* PLL "P" ? */\r
-      {\r
-        if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
-        {\r
-          if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN))\r
-          {\r
-            /* f(PLL Source) * PLLN / PLLM */\r
-            plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
-            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-            /* f(PLLSAI3CLK) = f(VCO input) / PLLP */\r
-            pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
-            if(pllp == 0U)\r
-            {\r
-              if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
-              {\r
-                pllp = 17U;\r
-              }\r
-              else\r
-              {\r
-                pllp = 7U;\r
-              }\r
-            }\r
-            frequency = (pllvco / pllp);\r
-          }\r
-        }\r
-      }\r
-      else  /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */\r
-      {\r
-        srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_CCIPR_CLK48SEL:   /* MSI ? */\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
-          {\r
-            /*MSI frequency range in HZ*/\r
-            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
-          }\r
-          break;\r
-        case RCC_CCIPR_CLK48SEL_1:  /* PLL "Q" ? */\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
-          {\r
-            if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))\r
-            {\r
-              /* f(PLL Source) * PLLN / PLLM */\r
-              plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
-              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-              /* f(PLL48M1CLK) = f(VCO input) / PLLQ */\r
-              frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));\r
-            }\r
-          }\r
-          break;\r
-        case RCC_CCIPR_CLK48SEL_0:  /* PLLSAI1 ? */\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))\r
-          {\r
-            if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))\r
-            {\r
-              /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */\r
-              plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
-              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
-              /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */\r
-              frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));\r
-            }\r
-          }\r
-          break;\r
-        case 0U:\r
-          if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */\r
-          {\r
-            frequency = HSI48_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        } /* switch(srcclk) */\r
-      }\r
-      break;\r
-\r
-#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */\r
-\r
-    case RCC_PERIPHCLK_USART1:\r
-      {\r
-        /* Get the current USART1 source */\r
-        srcclk = __HAL_RCC_GET_USART1_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_USART1CLKSOURCE_PCLK2:\r
-          frequency = HAL_RCC_GetPCLK2Freq();\r
-          break;\r
-        case RCC_USART1CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_USART1CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_USART1CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-    case RCC_PERIPHCLK_USART2:\r
-      {\r
-        /* Get the current USART2 source */\r
-        srcclk = __HAL_RCC_GET_USART2_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_USART2CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_USART2CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_USART2CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_USART2CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#if defined(USART3)\r
-\r
-    case RCC_PERIPHCLK_USART3:\r
-      {\r
-        /* Get the current USART3 source */\r
-        srcclk = __HAL_RCC_GET_USART3_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_USART3CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_USART3CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_USART3CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_USART3CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-\r
-    case RCC_PERIPHCLK_UART4:\r
-      {\r
-        /* Get the current UART4 source */\r
-        srcclk = __HAL_RCC_GET_UART4_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_UART4CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_UART4CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_UART4CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_UART4CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-\r
-    case RCC_PERIPHCLK_UART5:\r
-      {\r
-        /* Get the current UART5 source */\r
-        srcclk = __HAL_RCC_GET_UART5_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_UART5CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_UART5CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_UART5CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_UART5CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* UART5 */\r
-\r
-    case RCC_PERIPHCLK_LPUART1:\r
-      {\r
-        /* Get the current LPUART1 source */\r
-        srcclk = __HAL_RCC_GET_LPUART1_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_LPUART1CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_LPUART1CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_LPUART1CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_LPUART1CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-    case RCC_PERIPHCLK_ADC:\r
-      {\r
-        srcclk = __HAL_RCC_GET_ADC_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_ADCCLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-        case RCC_ADCCLKSOURCE_PLLSAI1:\r
-          if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U)\r
-          {\r
-            plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-            /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
-            /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */\r
-            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
-#else\r
-            /* f(PLL Source) * PLLSAI1N / PLLM */\r
-            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-#endif\r
-            /* f(PLLADC1CLK) = f(VCOSAI1 input) / PLLSAI1R */\r
-            frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U));\r
-          }\r
-          break;\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-        case RCC_ADCCLKSOURCE_PLLSAI2:\r
-          if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U)\r
-          {\r
-            plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-            /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */\r
-            /* f(PLLSAI2 Source) * PLLSAI2N / PLLSAI2M */\r
-            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));\r
-#else\r
-            /* f(PLL Source) * PLLSAI2N / PLLM */\r
-            pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-#endif\r
-            /* f(PLLADC2CLK) = f(VCOSAI2 input) / PLLSAI2R */\r
-            frequency = (pllvco / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U));\r
-          }\r
-          break;\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#if defined(DFSDM1_Filter0)\r
-\r
-    case RCC_PERIPHCLK_DFSDM1:\r
-      {\r
-        /* Get the current DFSDM1 source */\r
-        srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();\r
-\r
-        if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2)\r
-        {\r
-          frequency = HAL_RCC_GetPCLK2Freq();\r
-        }\r
-        else\r
-        {\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-\r
-    case RCC_PERIPHCLK_DFSDM1AUDIO:\r
-      {\r
-        /* Get the current DFSDM1 audio source */\r
-        srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_DFSDM1AUDIOCLKSOURCE_SAI1:\r
-          frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);\r
-          break;\r
-        case RCC_DFSDM1AUDIOCLKSOURCE_MSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
-          {\r
-            /*MSI frequency range in HZ*/\r
-            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
-          }\r
-          break;\r
-        case RCC_DFSDM1AUDIOCLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-    case RCC_PERIPHCLK_I2C1:\r
-      {\r
-        /* Get the current I2C1 source */\r
-        srcclk = __HAL_RCC_GET_I2C1_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_I2C1CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_I2C1CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_I2C1CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#if defined(I2C2)\r
-\r
-    case RCC_PERIPHCLK_I2C2:\r
-      {\r
-        /* Get the current I2C2 source */\r
-        srcclk = __HAL_RCC_GET_I2C2_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_I2C2CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_I2C2CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_I2C2CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* I2C2 */\r
-\r
-    case RCC_PERIPHCLK_I2C3:\r
-      {\r
-        /* Get the current I2C3 source */\r
-        srcclk = __HAL_RCC_GET_I2C3_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_I2C3CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_I2C3CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_I2C3CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#if defined(I2C4)\r
-\r
-    case RCC_PERIPHCLK_I2C4:\r
-      {\r
-        /* Get the current I2C4 source */\r
-        srcclk = __HAL_RCC_GET_I2C4_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_I2C4CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_I2C4CLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_I2C4CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* I2C4 */\r
-\r
-    case RCC_PERIPHCLK_LPTIM1:\r
-      {\r
-        /* Get the current LPTIM1 source */\r
-        srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_LPTIM1CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_LPTIM1CLKSOURCE_LSI:\r
-          if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))\r
-          {\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-            if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))\r
-            {\r
-              frequency = LSI_VALUE/128U;\r
-            }\r
-            else\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-            {\r
-              frequency = LSI_VALUE;\r
-            }\r
-          }\r
-          break;\r
-        case RCC_LPTIM1CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_LPTIM1CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-    case RCC_PERIPHCLK_LPTIM2:\r
-      {\r
-        /* Get the current LPTIM2 source */\r
-       srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_LPTIM2CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_LPTIM2CLKSOURCE_LSI:\r
-          if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))\r
-          {\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-            if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))\r
-            {\r
-              frequency = LSI_VALUE/128U;\r
-            }\r
-            else\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-            {\r
-              frequency = LSI_VALUE;\r
-            }\r
-          }\r
-          break;\r
-        case RCC_LPTIM2CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        case RCC_LPTIM2CLKSOURCE_LSE:\r
-          if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))\r
-          {\r
-            frequency = LSE_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#if defined(SWPMI1)\r
-\r
-    case RCC_PERIPHCLK_SWPMI1:\r
-      {\r
-        /* Get the current SWPMI1 source */\r
-        srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_SWPMI1CLKSOURCE_PCLK1:\r
-          frequency = HAL_RCC_GetPCLK1Freq();\r
-          break;\r
-        case RCC_SWPMI1CLKSOURCE_HSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-          {\r
-            frequency = HSI_VALUE;\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* SWPMI1 */\r
-\r
-#if defined(OCTOSPI1) || defined(OCTOSPI2)\r
-\r
-    case RCC_PERIPHCLK_OSPI:\r
-      {\r
-        /* Get the current OctoSPI clock source */\r
-        srcclk = __HAL_RCC_GET_OSPI_SOURCE();\r
-\r
-        switch(srcclk)\r
-        {\r
-        case RCC_OSPICLKSOURCE_SYSCLK:\r
-          frequency = HAL_RCC_GetSysClockFreq();\r
-          break;\r
-        case RCC_OSPICLKSOURCE_MSI:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))\r
-          {\r
-            /*MSI frequency range in HZ*/\r
-            frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];\r
-          }\r
-          break;\r
-        case RCC_OSPICLKSOURCE_PLL:\r
-          if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))\r
-          {\r
-            if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))\r
-            {\r
-              /* f(PLL Source) * PLLN / PLLM */\r
-              plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
-              pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-              /* f(PLL48M1CLK) = f(VCO input) / PLLQ */\r
-              frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));\r
-            }\r
-          }\r
-          break;\r
-        default:\r
-          /* No clock source, frequency default init at 0 */\r
-          break;\r
-        }\r
-\r
-        break;\r
-      }\r
-\r
-#endif /* OCTOSPI1 || OCTOSPI2 */\r
-\r
-    default:\r
-      break;\r
-    }\r
-  }\r
-\r
-  return(frequency);\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions\r
- *  @brief  Extended Clock management functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                ##### Extended clock management functions  #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to control the\r
-    activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,\r
-    Low speed clock output and clock after wake-up from STOP mode.\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-/**\r
-  * @brief  Enable PLLSAI1.\r
-  * @param  PLLSAI1Init  pointer to an RCC_PLLSAI1InitTypeDef structure that\r
-  *         contains the configuration information for the PLLSAI1\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */\r
-  assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source));\r
-  assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M));\r
-  assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));\r
-  assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));\r
-  assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));\r
-  assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));\r
-  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));\r
-\r
-  /* Disable the PLLSAI1 */\r
-  __HAL_RCC_PLLSAI1_DISABLE();\r
-\r
-  /* Get Start Tick*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait till PLLSAI1 is ready to be updated */\r
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)\r
-  {\r
-    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
-    {\r
-      status = HAL_TIMEOUT;\r
-      break;\r
-    }\r
-  }\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-    /* Configure the PLLSAI1 Multiplication factor N */\r
-    /* Configure the PLLSAI1 Division factors M, P, Q and R */\r
-    __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);\r
-#else\r
-    /* Configure the PLLSAI1 Multiplication factor N */\r
-    /* Configure the PLLSAI1 Division factors P, Q and R */\r
-    __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-    /* Configure the PLLSAI1 Clock output(s) */\r
-    __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);\r
-\r
-    /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/\r
-    __HAL_RCC_PLLSAI1_ENABLE();\r
-\r
-    /* Get Start Tick*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait till PLLSAI1 is ready */\r
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)\r
-    {\r
-      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
-      {\r
-        status = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Disable PLLSAI1.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Disable the PLLSAI1 */\r
-  __HAL_RCC_PLLSAI1_DISABLE();\r
-\r
-  /* Get Start Tick*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait till PLLSAI1 is ready */\r
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)\r
-  {\r
-    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
-    {\r
-      status = HAL_TIMEOUT;\r
-      break;\r
-    }\r
-  }\r
-\r
-  /* Disable the PLLSAI1 Clock outputs */\r
-  __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN);\r
-\r
-  /* Reset PLL source to save power if no PLLs on */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-  if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI2RDY)) == 0U)\r
-  {\r
-    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
-  }\r
-#else\r
-  if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
-  {\r
-    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
-  }\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-  return status;\r
-}\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-/**\r
-  * @brief  Enable PLLSAI2.\r
-  * @param  PLLSAI2Init  pointer to an RCC_PLLSAI2InitTypeDef structure that\r
-  *         contains the configuration information for the PLLSAI2\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */\r
-  assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source));\r
-  assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M));\r
-  assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));\r
-  assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-  assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q));\r
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
-  assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));\r
-  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));\r
-\r
-  /* Disable the PLLSAI2 */\r
-  __HAL_RCC_PLLSAI2_DISABLE();\r
-\r
-  /* Get Start Tick*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait till PLLSAI2 is ready to be updated */\r
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
-  {\r
-    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
-    {\r
-      status = HAL_TIMEOUT;\r
-      break;\r
-    }\r
-  }\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-    /* Configure the PLLSAI2 Multiplication factor N */\r
-    /* Configure the PLLSAI2 Division factors M, P, Q and R */\r
-    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);\r
-#elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-    /* Configure the PLLSAI2 Multiplication factor N */\r
-    /* Configure the PLLSAI2 Division factors M, P and R */\r
-    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);\r
-#elif defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-    /* Configure the PLLSAI2 Multiplication factor N */\r
-    /* Configure the PLLSAI2 Division factors P, Q and R */\r
-    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);\r
-#else\r
-    /* Configure the PLLSAI2 Multiplication factor N */\r
-    /* Configure the PLLSAI2 Division factors P and R */\r
-    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
-    /* Configure the PLLSAI2 Clock output(s) */\r
-    __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);\r
-\r
-    /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/\r
-    __HAL_RCC_PLLSAI2_ENABLE();\r
-\r
-    /* Get Start Tick*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait till PLLSAI2 is ready */\r
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)\r
-    {\r
-      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
-      {\r
-        status = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Disable PLLISAI2.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Disable the PLLSAI2 */\r
-  __HAL_RCC_PLLSAI2_DISABLE();\r
-\r
-  /* Get Start Tick*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait till PLLSAI2 is ready */\r
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
-  {\r
-    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
-    {\r
-      status = HAL_TIMEOUT;\r
-      break;\r
-    }\r
-  }\r
-\r
-  /* Disable the PLLSAI2 Clock outputs */\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN);\r
-#else\r
-  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN);\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */\r
-\r
-  /* Reset PLL source to save power if no PLLs on */\r
-  if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY)) == 0U)\r
-  {\r
-    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-/**\r
-  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock.\r
-  * @param  WakeUpClk  Wakeup clock\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI oscillator selection\r
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI oscillator selection\r
-  * @note   This function shall not be called after the Clock Security System on HSE has been\r
-  *         enabled.\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)\r
-{\r
-  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));\r
-\r
-  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);\r
-}\r
-\r
-/**\r
-  * @brief  Configure the MSI range after standby mode.\r
-  * @note   After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).\r
-  * @param  MSIRange  MSI range\r
-  *         This parameter can be one of the following values:\r
-  *            @arg @ref RCC_MSIRANGE_4  Range 4 around 1 MHz\r
-  *            @arg @ref RCC_MSIRANGE_5  Range 5 around 2 MHz\r
-  *            @arg @ref RCC_MSIRANGE_6  Range 6 around 4 MHz (reset value)\r
-  *            @arg @ref RCC_MSIRANGE_7  Range 7 around 8 MHz\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)\r
-{\r
-  assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));\r
-\r
-  __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);\r
-}\r
-\r
-/**\r
-  * @brief  Enable the LSE Clock Security System.\r
-  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled\r
-  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC\r
-  *         clock with HAL_RCCEx_PeriphCLKConfig().\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_EnableLSECSS(void)\r
-{\r
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
-}\r
-\r
-/**\r
-  * @brief  Disable the LSE Clock Security System.\r
-  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_DisableLSECSS(void)\r
-{\r
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
-\r
-  /* Disable LSE CSS IT if any */\r
-  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);\r
-}\r
-\r
-/**\r
-  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.\r
-  * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_EnableLSECSS_IT(void)\r
-{\r
-  /* Enable LSE CSS */\r
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
-\r
-  /* Enable LSE CSS IT */\r
-  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);\r
-\r
-  /* Enable IT on EXTI Line 19 */\r
-  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();\r
-  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();\r
-}\r
-\r
-/**\r
-  * @brief Handle the RCC LSE Clock Security System interrupt request.\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_LSECSS_IRQHandler(void)\r
-{\r
-  /* Check RCC LSE CSSF flag  */\r
-  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))\r
-  {\r
-    /* RCC LSE Clock Security System interrupt user callback */\r
-    HAL_RCCEx_LSECSS_Callback();\r
-\r
-    /* Clear RCC LSE CSS pending bit */\r
-    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  RCCEx LSE Clock Security System interrupt callback.\r
-  * @retval none\r
-  */\r
-__weak void HAL_RCCEx_LSECSS_Callback(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).\r
-  * @param  LSCOSource  specifies the Low Speed clock source to output.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source\r
-  *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)\r
-{\r
-  GPIO_InitTypeDef GPIO_InitStruct;\r
-  FlagStatus       pwrclkchanged = RESET;\r
-  FlagStatus       backupchanged = RESET;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_LSCOSOURCE(LSCOSource));\r
-\r
-  /* LSCO Pin Clock Enable */\r
-  __LSCO_CLK_ENABLE();\r
-\r
-  /* Configue the LSCO pin in analog mode */\r
-  GPIO_InitStruct.Pin = LSCO_PIN;\r
-  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;\r
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\r
-  GPIO_InitStruct.Pull = GPIO_NOPULL;\r
-  HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);\r
-\r
-  /* Update LSCOSEL clock source in Backup Domain control register */\r
-  if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
-  {\r
-    __HAL_RCC_PWR_CLK_ENABLE();\r
-    pwrclkchanged = SET;\r
-  }\r
-  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
-  {\r
-    HAL_PWR_EnableBkUpAccess();\r
-    backupchanged = SET;\r
-  }\r
-\r
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);\r
-\r
-  if(backupchanged == SET)\r
-  {\r
-    HAL_PWR_DisableBkUpAccess();\r
-  }\r
-  if(pwrclkchanged == SET)\r
-  {\r
-    __HAL_RCC_PWR_CLK_DISABLE();\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Disable the Low Speed clock output.\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_DisableLSCO(void)\r
-{\r
-  FlagStatus       pwrclkchanged = RESET;\r
-  FlagStatus       backupchanged = RESET;\r
-\r
-  /* Update LSCOEN bit in Backup Domain control register */\r
-  if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
-  {\r
-    __HAL_RCC_PWR_CLK_ENABLE();\r
-    pwrclkchanged = SET;\r
-  }\r
-  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
-  {\r
-    /* Enable access to the backup domain */\r
-    HAL_PWR_EnableBkUpAccess();\r
-    backupchanged = SET;\r
-  }\r
-\r
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);\r
-\r
-  /* Restore previous configuration */\r
-  if(backupchanged == SET)\r
-  {\r
-    /* Disable access to the backup domain */\r
-    HAL_PWR_DisableBkUpAccess();\r
-  }\r
-  if(pwrclkchanged == SET)\r
-  {\r
-    __HAL_RCC_PWR_CLK_DISABLE();\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Enable the PLL-mode of the MSI.\r
-  * @note   Prior to enable the PLL-mode of the MSI for automatic hardware\r
-  *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_EnableMSIPLLMode(void)\r
-{\r
-  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;\r
-}\r
-\r
-/**\r
-  * @brief  Disable the PLL-mode of the MSI.\r
-  * @note   PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_DisableMSIPLLMode(void)\r
-{\r
-  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#if defined(CRS)\r
-\r
-/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions\r
- *  @brief  Extended Clock Recovery System Control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                ##### Extended Clock Recovery System Control functions  #####\r
- ===============================================================================\r
-    [..]\r
-      For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:\r
-\r
-      (#) In System clock config, HSI48 needs to be enabled\r
-\r
-      (#) Enable CRS clock in IP MSP init which will use CRS functions\r
-\r
-      (#) Call CRS functions as follows:\r
-          (##) Prepare synchronization configuration necessary for HSI48 calibration\r
-              (+++) Default values can be set for frequency Error Measurement (reload and error limit)\r
-                        and also HSI48 oscillator smooth trimming.\r
-              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate\r
-                        directly reload value with target and sychronization frequencies values\r
-          (##) Call function HAL_RCCEx_CRSConfig which\r
-              (+++) Resets CRS registers to their default values.\r
-              (+++) Configures CRS registers with synchronization configuration\r
-              (+++) Enables automatic calibration and frequency error counter feature\r
-           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the\r
-           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be\r
-           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock\r
-           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs\r
-           should be used as SYNC signal.\r
-\r
-          (##) A polling function is provided to wait for complete synchronization\r
-              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()\r
-              (+++) According to CRS status, user can decide to adjust again the calibration or continue\r
-                        application if synchronization is OK\r
-\r
-      (#) User can retrieve information related to synchronization in calling function\r
-            HAL_RCCEx_CRSGetSynchronizationInfo()\r
-\r
-      (#) Regarding synchronization status and synchronization information, user can try a new calibration\r
-           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.\r
-           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),\r
-           it means that the actual frequency is lower than the target (and so, that the TRIM value should be\r
-           incremented), while when it is detected during the upcounting phase it means that the actual frequency\r
-           is higher (and that the TRIM value should be decremented).\r
-\r
-      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go\r
-          through CRS Handler (CRS_IRQn/CRS_IRQHandler)\r
-              (++) Call function HAL_RCCEx_CRSConfig()\r
-              (++) Enable CRS_IRQn (thanks to NVIC functions)\r
-              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)\r
-              (++) Implement CRS status management in the following user callbacks called from\r
-                   HAL_RCCEx_CRS_IRQHandler():\r
-                   (+++) HAL_RCCEx_CRS_SyncOkCallback()\r
-                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()\r
-                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()\r
-                   (+++) HAL_RCCEx_CRS_ErrorCallback()\r
-\r
-      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().\r
-          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
-  * @brief  Start automatic synchronization for polling mode\r
-  * @param  pInit Pointer on RCC_CRSInitTypeDef structure\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)\r
-{\r
-  uint32_t value;  /* no init needed */\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));\r
-  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));\r
-  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));\r
-  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));\r
-  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));\r
-  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));\r
-\r
-  /* CONFIGURATION */\r
-\r
-  /* Before configuration, reset CRS registers to their default values*/\r
-  __HAL_RCC_CRS_FORCE_RESET();\r
-  __HAL_RCC_CRS_RELEASE_RESET();\r
-\r
-  /* Set the SYNCDIV[2:0] bits according to Prescaler value */\r
-  /* Set the SYNCSRC[1:0] bits according to Source value */\r
-  /* Set the SYNCSPOL bit according to Polarity value */\r
-  value = (pInit->Prescaler | pInit->Source | pInit->Polarity);\r
-  /* Set the RELOAD[15:0] bits according to ReloadValue value */\r
-  value |= pInit->ReloadValue;\r
-  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */\r
-  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);\r
-  WRITE_REG(CRS->CFGR, value);\r
-\r
-  /* Adjust HSI48 oscillator smooth trimming */\r
-  /* Set the TRIM[6:0] bits for STM32L412xx/L422xx or TRIM[5:0] bits otherwise\r
-     according to RCC_CRS_HSI48CalibrationValue value */\r
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));\r
-\r
-  /* START AUTOMATIC SYNCHRONIZATION*/\r
-\r
-  /* Enable Automatic trimming & Frequency error counter */\r
-  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);\r
-}\r
-\r
-/**\r
-  * @brief  Generate the software synchronization event\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)\r
-{\r
-  SET_BIT(CRS->CR, CRS_CR_SWSYNC);\r
-}\r
-\r
-/**\r
-  * @brief  Return synchronization info\r
-  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)\r
-{\r
-  /* Check the parameter */\r
-  assert_param(pSynchroInfo != (void *)NULL);\r
-\r
-  /* Get the reload value */\r
-  pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));\r
-\r
-  /* Get HSI48 oscillator smooth trimming */\r
-  pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);\r
-\r
-  /* Get Frequency error capture */\r
-  pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);\r
-\r
-  /* Get Frequency error direction */\r
-  pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));\r
-}\r
-\r
-/**\r
-* @brief Wait for CRS Synchronization status.\r
-* @param Timeout  Duration of the timeout\r
-* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization\r
-*        frequency.\r
-* @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.\r
-* @retval Combination of Synchronization status\r
-*          This parameter can be a combination of the following values:\r
-*            @arg @ref RCC_CRS_TIMEOUT\r
-*            @arg @ref RCC_CRS_SYNCOK\r
-*            @arg @ref RCC_CRS_SYNCWARN\r
-*            @arg @ref RCC_CRS_SYNCERR\r
-*            @arg @ref RCC_CRS_SYNCMISS\r
-*            @arg @ref RCC_CRS_TRIMOVF\r
-*/\r
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)\r
-{\r
-  uint32_t crsstatus = RCC_CRS_NONE;\r
-  uint32_t tickstart;\r
-\r
-  /* Get timeout */\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait for CRS flag or timeout detection */\r
-  do\r
-  {\r
-    if(Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
-      {\r
-        crsstatus = RCC_CRS_TIMEOUT;\r
-      }\r
-    }\r
-    /* Check CRS SYNCOK flag  */\r
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))\r
-    {\r
-      /* CRS SYNC event OK */\r
-      crsstatus |= RCC_CRS_SYNCOK;\r
-\r
-      /* Clear CRS SYNC event OK bit */\r
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);\r
-    }\r
-\r
-    /* Check CRS SYNCWARN flag  */\r
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))\r
-    {\r
-      /* CRS SYNC warning */\r
-      crsstatus |= RCC_CRS_SYNCWARN;\r
-\r
-      /* Clear CRS SYNCWARN bit */\r
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);\r
-    }\r
-\r
-    /* Check CRS TRIM overflow flag  */\r
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))\r
-    {\r
-      /* CRS SYNC Error */\r
-      crsstatus |= RCC_CRS_TRIMOVF;\r
-\r
-      /* Clear CRS Error bit */\r
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);\r
-    }\r
-\r
-    /* Check CRS Error flag  */\r
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))\r
-    {\r
-      /* CRS SYNC Error */\r
-      crsstatus |= RCC_CRS_SYNCERR;\r
-\r
-      /* Clear CRS Error bit */\r
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);\r
-    }\r
-\r
-    /* Check CRS SYNC Missed flag  */\r
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))\r
-    {\r
-      /* CRS SYNC Missed */\r
-      crsstatus |= RCC_CRS_SYNCMISS;\r
-\r
-      /* Clear CRS SYNC Missed bit */\r
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);\r
-    }\r
-\r
-    /* Check CRS Expected SYNC flag  */\r
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))\r
-    {\r
-      /* frequency error counter reached a zero value */\r
-      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);\r
-    }\r
-  } while(RCC_CRS_NONE == crsstatus);\r
-\r
-  return crsstatus;\r
-}\r
-\r
-/**\r
-  * @brief Handle the Clock Recovery System interrupt request.\r
-  * @retval None\r
-  */\r
-void HAL_RCCEx_CRS_IRQHandler(void)\r
-{\r
-  uint32_t crserror = RCC_CRS_NONE;\r
-  /* Get current IT flags and IT sources values */\r
-  uint32_t itflags = READ_REG(CRS->ISR);\r
-  uint32_t itsources = READ_REG(CRS->CR);\r
-\r
-  /* Check CRS SYNCOK flag  */\r
-  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))\r
-  {\r
-    /* Clear CRS SYNC event OK flag */\r
-    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);\r
-\r
-    /* user callback */\r
-    HAL_RCCEx_CRS_SyncOkCallback();\r
-  }\r
-  /* Check CRS SYNCWARN flag  */\r
-  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))\r
-  {\r
-    /* Clear CRS SYNCWARN flag */\r
-    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);\r
-\r
-    /* user callback */\r
-    HAL_RCCEx_CRS_SyncWarnCallback();\r
-  }\r
-  /* Check CRS Expected SYNC flag  */\r
-  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))\r
-  {\r
-    /* frequency error counter reached a zero value */\r
-    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);\r
-\r
-    /* user callback */\r
-    HAL_RCCEx_CRS_ExpectedSyncCallback();\r
-  }\r
-  /* Check CRS Error flags  */\r
-  else\r
-  {\r
-    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))\r
-    {\r
-      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)\r
-      {\r
-        crserror |= RCC_CRS_SYNCERR;\r
-      }\r
-      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)\r
-      {\r
-        crserror |= RCC_CRS_SYNCMISS;\r
-      }\r
-      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)\r
-      {\r
-        crserror |= RCC_CRS_TRIMOVF;\r
-      }\r
-\r
-      /* Clear CRS Error flags */\r
-      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);\r
-\r
-      /* user error callback */\r
-      HAL_RCCEx_CRS_ErrorCallback(crserror);\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.\r
-  * @retval none\r
-  */\r
-__weak void HAL_RCCEx_CRS_SyncOkCallback(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.\r
-  * @retval none\r
-  */\r
-__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.\r
-  * @retval none\r
-  */\r
-__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)\r
-{\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  RCCEx Clock Recovery System Error interrupt callback.\r
-  * @param  Error Combination of Error status.\r
-  *         This parameter can be a combination of the following values:\r
-  *           @arg @ref RCC_CRS_SYNCERR\r
-  *           @arg @ref RCC_CRS_SYNCMISS\r
-  *           @arg @ref RCC_CRS_TRIMOVF\r
-  * @retval none\r
-  */\r
-__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(Error);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* CRS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup RCCEx_Private_Functions\r
- * @{\r
- */\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-/**\r
-  * @brief  Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).\r
-  * @param  PllSai1  pointer to an RCC_PLLSAI1InitTypeDef structure that\r
-  *         contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s)\r
-  * @param  Divider  divider parameter to be updated\r
-  *\r
-  * @note   PLLSAI1 is temporary disable to apply new parameters\r
-  *\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */\r
-  /* P, Q and R dividers are verified in each specific divider case below */\r
-  assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source));\r
-  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));\r
-  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));\r
-  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));\r
-\r
-  /* Check that PLLSAI1 clock source and divider M can be applied */\r
-  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)\r
-  {\r
-    /* PLL clock source and divider M already set, check that no request for change  */\r
-    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)\r
-       ||\r
-       (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)\r
-#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-       ||\r
-       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)\r
-#endif\r
-      )\r
-    {\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Check PLLSAI1 clock source availability */\r
-    switch(PllSai1->PLLSAI1Source)\r
-    {\r
-    case RCC_PLLSOURCE_MSI:\r
-      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))\r
-      {\r
-        status = HAL_ERROR;\r
-      }\r
-      break;\r
-    case RCC_PLLSOURCE_HSI:\r
-      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))\r
-      {\r
-        status = HAL_ERROR;\r
-      }\r
-      break;\r
-    case RCC_PLLSOURCE_HSE:\r
-      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))\r
-      {\r
-        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))\r
-        {\r
-          status = HAL_ERROR;\r
-        }\r
-      }\r
-      break;\r
-    default:\r
-      status = HAL_ERROR;\r
-      break;\r
-    }\r
-\r
-    if(status == HAL_OK)\r
-    {\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-      /* Set PLLSAI1 clock source */\r
-      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);\r
-#else\r
-      /* Set PLLSAI1 clock source and divider M */\r
-      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);\r
-#endif\r
-    }\r
-  }\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-    /* Disable the PLLSAI1 */\r
-    __HAL_RCC_PLLSAI1_DISABLE();\r
-\r
-    /* Get Start Tick*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait till PLLSAI1 is ready to be updated */\r
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)\r
-    {\r
-      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
-      {\r
-        status = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-\r
-    if(status == HAL_OK)\r
-    {\r
-      if(Divider == DIVIDER_P_UPDATE)\r
-      {\r
-        assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-\r
-        /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) |\r
-                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
-#else\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) |\r
-                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
-\r
-#else\r
-        /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));\r
-#else\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));\r
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\r
-\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-      }\r
-      else if(Divider == DIVIDER_Q_UPDATE)\r
-      {\r
-        assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-        /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |\r
-                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
-#else\r
-        /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos));\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-      }\r
-      else\r
-      {\r
-        assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-        /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |\r
-                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));\r
-#else\r
-        /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI1CFGR,\r
-                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,\r
-                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |\r
-                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));\r
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\r
-      }\r
-\r
-      /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/\r
-      __HAL_RCC_PLLSAI1_ENABLE();\r
-\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till PLLSAI1 is ready */\r
-      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)\r
-        {\r
-          status = HAL_TIMEOUT;\r
-          break;\r
-        }\r
-      }\r
-\r
-      if(status == HAL_OK)\r
-      {\r
-        /* Configure the PLLSAI1 Clock output(s) */\r
-        __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);\r
-      }\r
-    }\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-/**\r
-  * @brief  Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).\r
-  * @param  PllSai2  pointer to an RCC_PLLSAI2InitTypeDef structure that\r
-  *         contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s)\r
-  * @param  Divider  divider parameter to be updated\r
-  *\r
-  * @note   PLLSAI2 is temporary disable to apply new parameters\r
-  *\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */\r
-  /* P, Q and R dividers are verified in each specific divider case below */\r
-  assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source));\r
-  assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));\r
-  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));\r
-  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));\r
-\r
-  /* Check that PLLSAI2 clock source and divider M can be applied */\r
-  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)\r
-  {\r
-    /* PLL clock source and divider M already set, check that no request for change  */\r
-    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)\r
-       ||\r
-       (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)\r
-#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-       ||\r
-       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)\r
-#endif\r
-      )\r
-    {\r
-      status = HAL_ERROR;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Check PLLSAI2 clock source availability */\r
-    switch(PllSai2->PLLSAI2Source)\r
-    {\r
-    case RCC_PLLSOURCE_MSI:\r
-      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))\r
-      {\r
-        status = HAL_ERROR;\r
-      }\r
-      break;\r
-    case RCC_PLLSOURCE_HSI:\r
-      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))\r
-      {\r
-        status = HAL_ERROR;\r
-      }\r
-      break;\r
-    case RCC_PLLSOURCE_HSE:\r
-      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))\r
-      {\r
-        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))\r
-        {\r
-          status = HAL_ERROR;\r
-        }\r
-      }\r
-      break;\r
-    default:\r
-      status = HAL_ERROR;\r
-      break;\r
-    }\r
-\r
-    if(status == HAL_OK)\r
-    {\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-      /* Set PLLSAI2 clock source */\r
-      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);\r
-#else\r
-      /* Set PLLSAI2 clock source and divider M */\r
-      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);\r
-#endif\r
-    }\r
-  }\r
-\r
-  if(status == HAL_OK)\r
-  {\r
-    /* Disable the PLLSAI2 */\r
-    __HAL_RCC_PLLSAI2_DISABLE();\r
-\r
-    /* Get Start Tick*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    /* Wait till PLLSAI2 is ready to be updated */\r
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)\r
-    {\r
-      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
-      {\r
-        status = HAL_TIMEOUT;\r
-        break;\r
-      }\r
-    }\r
-\r
-    if(status == HAL_OK)\r
-    {\r
-      if(Divider == DIVIDER_P_UPDATE)\r
-      {\r
-        assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-\r
-        /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/\r
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) |\r
-                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
-#else\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) |\r
-                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
-#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\r
-\r
-#else\r
-        /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/\r
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));\r
-#else\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos));\r
-#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\r
-\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
-      }\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-      else if(Divider == DIVIDER_Q_UPDATE)\r
-      {\r
-        assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q));\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-        /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) |\r
-                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
-#else\r
-        /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos));\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
-      }\r
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
-      else\r
-      {\r
-        assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-        /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |\r
-                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));\r
-#else\r
-        /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/\r
-        MODIFY_REG(RCC->PLLSAI2CFGR,\r
-                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,\r
-                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |\r
-                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));\r
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\r
-      }\r
-\r
-      /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/\r
-      __HAL_RCC_PLLSAI2_ENABLE();\r
-\r
-      /* Get Start Tick*/\r
-      tickstart = HAL_GetTick();\r
-\r
-      /* Wait till PLLSAI2 is ready */\r
-      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)\r
-      {\r
-        if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)\r
-        {\r
-          status = HAL_TIMEOUT;\r
-          break;\r
-        }\r
-      }\r
-\r
-      if(status == HAL_OK)\r
-      {\r
-        /* Configure the PLLSAI2 Clock output(s) */\r
-        __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);\r
-      }\r
-    }\r
-  }\r
-\r
-  return status;\r
-}\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#if defined(SAI1)\r
-\r
-static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency)\r
-{\r
-  uint32_t frequency = 0U;\r
-  uint32_t srcclk = 0U;\r
-  uint32_t pllvco, plln;    /* no init needed */\r
-#if defined(RCC_PLLP_SUPPORT)\r
-  uint32_t pllp = 0U;\r
-#endif /* RCC_PLLP_SUPPORT */\r
-\r
-  /* Handle SAIs */\r
-  if(PeriphClk == RCC_PERIPHCLK_SAI1)\r
-  {\r
-    srcclk = __HAL_RCC_GET_SAI1_SOURCE();\r
-    if(srcclk == RCC_SAI1CLKSOURCE_PIN)\r
-    {\r
-      frequency = EXTERNAL_SAI1_CLOCK_VALUE;\r
-    }\r
-    /* Else, PLL clock output to check below */\r
-  }\r
-#if defined(SAI2)\r
-  else\r
-  {\r
-    if(PeriphClk == RCC_PERIPHCLK_SAI2)\r
-    {\r
-      srcclk = __HAL_RCC_GET_SAI2_SOURCE();\r
-      if(srcclk == RCC_SAI2CLKSOURCE_PIN)\r
-      {\r
-        frequency = EXTERNAL_SAI2_CLOCK_VALUE;\r
-      }\r
-      /* Else, PLL clock output to check below */\r
-    }\r
-  }\r
-#endif /* SAI2 */\r
-\r
-  if(frequency == 0U)\r
-  {\r
-    pllvco = InputFrequency;\r
-\r
-#if defined(SAI2)\r
-    if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))\r
-    {\r
-      if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U)\r
-      {\r
-        /* f(PLL Source) / PLLM */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-        /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */\r
-        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-        pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
-#endif\r
-        if(pllp == 0U)\r
-        {\r
-          if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
-          {\r
-            pllp = 17U;\r
-          }\r
-          else\r
-          {\r
-            pllp = 7U;\r
-          }\r
-        }\r
-        frequency = (pllvco * plln) / pllp;\r
-      }\r
-    }\r
-    else if(srcclk == 0U)  /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */\r
-    {\r
-      if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)\r
-      {\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-        /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
-        /* f(PLLSAI1 Source) / PLLSAI1M */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
-#else\r
-        /* f(PLL Source) / PLLM */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-#endif\r
-        /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */\r
-        plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-        pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;\r
-#endif\r
-        if(pllp == 0U)\r
-        {\r
-          if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)\r
-          {\r
-            pllp = 17U;\r
-          }\r
-          else\r
-          {\r
-            pllp = 7U;\r
-          }\r
-        }\r
-        frequency = (pllvco * plln) / pllp;\r
-      }\r
-    }\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-    else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI))\r
-    {\r
-      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-      {\r
-        frequency = HSI_VALUE;\r
-      }\r
-    }\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#else\r
-    if(srcclk == RCC_SAI1CLKSOURCE_PLL)\r
-    {\r
-      if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U)\r
-      {\r
-        /* f(PLL Source) / PLLM */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-        /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */\r
-        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-        pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
-#endif\r
-        if(pllp == 0U)\r
-        {\r
-          if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
-          {\r
-            pllp = 17U;\r
-          }\r
-          else\r
-          {\r
-            pllp = 7U;\r
-          }\r
-        }\r
-        frequency = (pllvco * plln) / pllp;\r
-      }\r
-      else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-      {\r
-        /* HSI automatically selected as clock source if PLLs not enabled */\r
-        frequency = HSI_VALUE;\r
-      }\r
-      else\r
-      {\r
-        /* No clock source, frequency default init at 0 */\r
-      }\r
-    }\r
-    else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)\r
-    {\r
-      if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)\r
-      {\r
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\r
-        /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */\r
-        /* f(PLLSAI1 Source) / PLLSAI1M */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));\r
-#else\r
-        /* f(PLL Source) / PLLM */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-#endif\r
-        /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */\r
-        plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;\r
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\r
-        pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;\r
-#endif\r
-        if(pllp == 0U)\r
-        {\r
-          if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)\r
-          {\r
-            pllp = 17U;\r
-          }\r
-          else\r
-          {\r
-            pllp = 7U;\r
-          }\r
-        }\r
-        frequency = (pllvco * plln) / pllp;\r
-      }\r
-      else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))\r
-      {\r
-        /* HSI automatically selected as clock source if PLLs not enabled */\r
-        frequency = HSI_VALUE;\r
-      }\r
-      else\r
-      {\r
-        /* No clock source, frequency default init at 0 */\r
-      }\r
-    }\r
-#endif /* SAI2 */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-    else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))\r
-    {\r
-      if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U)\r
-      {\r
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\r
-        /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */\r
-        /* f(PLLSAI2 Source) / PLLSAI2M */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));\r
-#else\r
-        /* f(PLL Source) / PLLM */\r
-        pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));\r
-#endif\r
-        /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */\r
-        plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;\r
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\r
-        pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos;\r
-#endif\r
-        if(pllp == 0U)\r
-        {\r
-          if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U)\r
-          {\r
-            pllp = 17U;\r
-          }\r
-          else\r
-          {\r
-            pllp = 7U;\r
-          }\r
-        }\r
-        frequency = (pllvco * plln) / pllp;\r
-      }\r
-    }\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-    else\r
-    {\r
-      /* No clock source, frequency default init at 0 */\r
-    }\r
-  }\r
-\r
-\r
-  return frequency;\r
-}\r
-\r
-#endif /* SAI1 */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_RCC_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
deleted file mode 100644 (file)
index 3be342c..0000000
+++ /dev/null
@@ -1,4273 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_spi.c\r
-  * @author  MCD Application Team\r
-  * @brief   SPI HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:\r
-  *           + Initialization and de-initialization functions\r
-  *           + IO operation functions\r
-  *           + Peripheral Control functions\r
-  *           + Peripheral State functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                        ##### How to use this driver #####\r
-  ==============================================================================\r
-    [..]\r
-      The SPI HAL driver can be used as follows:\r
-\r
-      (#) Declare a SPI_HandleTypeDef handle structure, for example:\r
-          SPI_HandleTypeDef  hspi;\r
-\r
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\r
-          (##) Enable the SPIx interface clock\r
-          (##) SPI pins configuration\r
-              (+++) Enable the clock for the SPI GPIOs\r
-              (+++) Configure these SPI pins as alternate function push-pull\r
-          (##) NVIC configuration if you need to use interrupt process\r
-              (+++) Configure the SPIx interrupt priority\r
-              (+++) Enable the NVIC SPI IRQ handle\r
-          (##) DMA Configuration if you need to use DMA process\r
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel\r
-              (+++) Enable the DMAx clock\r
-              (+++) Configure the DMA handle parameters\r
-              (+++) Configure the DMA Tx or Rx Stream/Channel\r
-              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle\r
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel\r
-\r
-      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\r
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\r
-\r
-      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
-              by calling the customized HAL_SPI_MspInit() API.\r
-     [..]\r
-       Circular mode restriction:\r
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r
-          (##) Master 2Lines RxOnly\r
-          (##) Master 1Line Rx\r
-      (#) The CRC feature is not managed when the DMA circular mode is enabled\r
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\r
-          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\r
-     [..]\r
-       Master Receive mode restriction:\r
-      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or\r
-          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI\r
-          does not initiate a new transfer the following procedure has to be respected:\r
-          (##) HAL_SPI_DeInit()\r
-          (##) HAL_SPI_Init()\r
-     [..]\r
-       Callback registration:\r
-\r
-      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U\r
-          allows the user to configure dynamically the driver callbacks.\r
-          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.\r
-\r
-          Function HAL_SPI_RegisterCallback() allows to register following callbacks:\r
-            (+) TxCpltCallback        : SPI Tx Completed callback\r
-            (+) RxCpltCallback        : SPI Rx Completed callback\r
-            (+) TxRxCpltCallback      : SPI TxRx Completed callback\r
-            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback\r
-            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback\r
-            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback\r
-            (+) ErrorCallback         : SPI Error callback\r
-            (+) AbortCpltCallback     : SPI Abort callback\r
-            (+) MspInitCallback       : SPI Msp Init callback\r
-            (+) MspDeInitCallback     : SPI Msp DeInit callback\r
-          This function takes as parameters the HAL peripheral handle, the Callback ID\r
-          and a pointer to the user callback function.\r
-\r
-\r
-      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default\r
-          weak function.\r
-          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
-          and the Callback ID.\r
-          This function allows to reset following callbacks:\r
-            (+) TxCpltCallback        : SPI Tx Completed callback\r
-            (+) RxCpltCallback        : SPI Rx Completed callback\r
-            (+) TxRxCpltCallback      : SPI TxRx Completed callback\r
-            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback\r
-            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback\r
-            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback\r
-            (+) ErrorCallback         : SPI Error callback\r
-            (+) AbortCpltCallback     : SPI Abort callback\r
-            (+) MspInitCallback       : SPI Msp Init callback\r
-            (+) MspDeInitCallback     : SPI Msp DeInit callback\r
-\r
-       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET\r
-       all callbacks are set to the corresponding weak functions:\r
-       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().\r
-       Exception done for MspInit and MspDeInit functions that are\r
-       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when\r
-       these callbacks are null (not registered beforehand).\r
-       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()\r
-       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\r
-\r
-       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.\r
-       Exception done MspInit/MspDeInit functions that can be registered/unregistered\r
-       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,\r
-       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\r
-       Then, the user first registers the MspInit/MspDeInit user callbacks\r
-       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()\r
-       or HAL_SPI_Init() function.\r
-\r
-       When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or\r
-       not defined, the callback registering feature is not available\r
-       and weak (surcharged) callbacks are used.\r
-\r
-     [..]\r
-       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,\r
-       the following table resume the max SPI frequency reached with data size 8bits/16bits,\r
-         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.\r
-\r
-  @endverbatim\r
-\r
-  Additional table :\r
-\r
-       DataSize = SPI_DATASIZE_8BIT:\r
-       +----------------------------------------------------------------------------------------------+\r
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\r
-       | Process | Tranfert mode  |---------------------|----------------------|----------------------|\r
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\r
-       |==============================================================================================|\r
-       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\r
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |\r
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\r
-       |=========|================|==========|==========|===========|==========|===========|==========|\r
-       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |\r
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |\r
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |\r
-       |=========|================|==========|==========|===========|==========|===========|==========|\r
-       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |\r
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |\r
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |\r
-       +----------------------------------------------------------------------------------------------+\r
-\r
-       DataSize = SPI_DATASIZE_16BIT:\r
-       +----------------------------------------------------------------------------------------------+\r
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\r
-       | Process | Tranfert mode  |---------------------|----------------------|----------------------|\r
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\r
-       |==============================================================================================|\r
-       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\r
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |\r
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\r
-       |=========|================|==========|==========|===========|==========|===========|==========|\r
-       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |\r
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |\r
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |\r
-       |=========|================|==========|==========|===========|==========|===========|==========|\r
-       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |\r
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |\r
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |\r
-       +----------------------------------------------------------------------------------------------+\r
-       @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),\r
-             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).\r
-       @note\r
-            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()\r
-            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()\r
-            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()\r
-\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup SPI SPI\r
-  * @brief SPI HAL module driver\r
-  * @{\r
-  */\r
-#ifdef HAL_SPI_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private defines -----------------------------------------------------------*/\r
-/** @defgroup SPI_Private_Constants SPI Private Constants\r
-  * @{\r
-  */\r
-#define SPI_DEFAULT_TIMEOUT 100U\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup SPI_Private_Functions SPI Private Functions\r
-  * @{\r
-  */\r
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\r
-                                                       uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r
-                                                       uint32_t Timeout, uint32_t Tickstart);\r
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-#if (USE_SPI_CRC != 0U)\r
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-#endif /* USE_SPI_CRC */\r
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\r
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup SPI_Exported_Functions SPI Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r
- *  @brief    Initialization and Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-              ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
-    [..]  This subsection provides a set of functions allowing to initialize and\r
-          de-initialize the SPIx peripheral:\r
-\r
-      (+) User must implement HAL_SPI_MspInit() function in which he configures\r
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
-\r
-      (+) Call the function HAL_SPI_Init() to configure the selected device with\r
-          the selected configuration:\r
-        (++) Mode\r
-        (++) Direction\r
-        (++) Data Size\r
-        (++) Clock Polarity and Phase\r
-        (++) NSS Management\r
-        (++) BaudRate Prescaler\r
-        (++) FirstBit\r
-        (++) TIMode\r
-        (++) CRC Calculation\r
-        (++) CRC Polynomial if CRC enabled\r
-        (++) CRC Length, used only with Data8 and Data16\r
-        (++) FIFO reception threshold\r
-\r
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration\r
-          of the selected SPIx peripheral.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initialize the SPI according to the specified parameters\r
-  *         in the SPI_InitTypeDef and initialize the associated handle.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\r
-{\r
-  uint32_t frxth;\r
-\r
-  /* Check the SPI handle allocation */\r
-  if (hspi == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
-  assert_param(IS_SPI_MODE(hspi->Init.Mode));\r
-  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\r
-  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\r
-  assert_param(IS_SPI_NSS(hspi->Init.NSS));\r
-  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));\r
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\r
-  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\r
-  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\r
-  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)\r
-  {\r
-    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\r
-    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\r
-  }\r
-#if (USE_SPI_CRC != 0U)\r
-  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\r
-    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));\r
-  }\r
-#else\r
-  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
-#endif /* USE_SPI_CRC */\r
-\r
-  if (hspi->State == HAL_SPI_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    hspi->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-    /* Init the SPI Callback settings */\r
-    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */\r
-    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */\r
-    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */\r
-    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */\r
-    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */\r
-    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\r
-    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */\r
-    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */\r
-\r
-    if (hspi->MspInitCallback == NULL)\r
-    {\r
-      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */\r
-    }\r
-\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
-    hspi->MspInitCallback(hspi);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
-    HAL_SPI_MspInit(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  hspi->State = HAL_SPI_STATE_BUSY;\r
-\r
-  /* Disable the selected SPI peripheral */\r
-  __HAL_SPI_DISABLE(hspi);\r
-\r
-  /* Align by default the rs fifo threshold on the data size */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    frxth = SPI_RXFIFO_THRESHOLD_HF;\r
-  }\r
-  else\r
-  {\r
-    frxth = SPI_RXFIFO_THRESHOLD_QF;\r
-  }\r
-\r
-  /* CRC calculation is valid only for 16Bit and 8 Bit */\r
-  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))\r
-  {\r
-    /* CRC must be disabled */\r
-    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
-  }\r
-\r
-  /* Align the CRC Length on the data size */\r
-  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)\r
-  {\r
-    /* CRC Length aligned on the data size : value set by default */\r
-    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-    {\r
-      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;\r
-    }\r
-    else\r
-    {\r
-      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;\r
-    }\r
-  }\r
-\r
-  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/\r
-  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,\r
-  Communication speed, First bit and CRC calculation state */\r
-  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |\r
-                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\r
-                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Configure : CRC Length */\r
-  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
-  {\r
-    hspi->Instance->CR1 |= SPI_CR1_CRCL;\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */\r
-  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |\r
-                                  hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/\r
-  /* Configure : CRC Polynomial */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-#if defined(SPI_I2SCFGR_I2SMOD)\r
-  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */\r
-  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);\r
-#endif /* SPI_I2SCFGR_I2SMOD */\r
-\r
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
-  hspi->State     = HAL_SPI_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  De-Initialize the SPI peripheral.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Check the SPI handle allocation */\r
-  if (hspi == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check SPI Instance parameter */\r
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
-\r
-  hspi->State = HAL_SPI_STATE_BUSY;\r
-\r
-  /* Disable the SPI Peripheral Clock */\r
-  __HAL_SPI_DISABLE(hspi);\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  if (hspi->MspDeInitCallback == NULL)\r
-  {\r
-    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */\r
-  }\r
-\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
-  hspi->MspDeInitCallback(hspi);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
-  HAL_SPI_MspDeInit(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-\r
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
-  hspi->State = HAL_SPI_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hspi);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initialize the SPI MSP.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_MspInit should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  De-Initialize the SPI MSP.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_MspDeInit should be implemented in the user file\r
-   */\r
-}\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-/**\r
-  * @brief  Register a User SPI Callback\r
-  *         To be used instead of the weak predefined callback\r
-  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified SPI.\r
-  * @param  CallbackID ID of the callback to be registered\r
-  * @param  pCallback pointer to the Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    /* Update the error code */\r
-    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-  /* Process locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  if (HAL_SPI_STATE_READY == hspi->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_SPI_TX_COMPLETE_CB_ID :\r
-        hspi->TxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_RX_COMPLETE_CB_ID :\r
-        hspi->RxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_TX_RX_COMPLETE_CB_ID :\r
-        hspi->TxRxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\r
-        hspi->TxHalfCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\r
-        hspi->RxHalfCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\r
-        hspi->TxRxHalfCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_ERROR_CB_ID :\r
-        hspi->ErrorCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_ABORT_CB_ID :\r
-        hspi->AbortCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_MSPINIT_CB_ID :\r
-        hspi->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_MSPDEINIT_CB_ID :\r
-        hspi->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (HAL_SPI_STATE_RESET == hspi->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_SPI_MSPINIT_CB_ID :\r
-        hspi->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_SPI_MSPDEINIT_CB_ID :\r
-        hspi->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hspi);\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister an SPI Callback\r
-  *         SPI callback is redirected to the weak predefined callback\r
-  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified SPI.\r
-  * @param  CallbackID ID of the callback to be unregistered\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  if (HAL_SPI_STATE_READY == hspi->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_SPI_TX_COMPLETE_CB_ID :\r
-        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */\r
-        break;\r
-\r
-      case HAL_SPI_RX_COMPLETE_CB_ID :\r
-        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */\r
-        break;\r
-\r
-      case HAL_SPI_TX_RX_COMPLETE_CB_ID :\r
-        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */\r
-        break;\r
-\r
-      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\r
-        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */\r
-        break;\r
-\r
-      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\r
-        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */\r
-        break;\r
-\r
-      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\r
-        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\r
-        break;\r
-\r
-      case HAL_SPI_ERROR_CB_ID :\r
-        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */\r
-        break;\r
-\r
-      case HAL_SPI_ABORT_CB_ID :\r
-        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */\r
-        break;\r
-\r
-      case HAL_SPI_MSPINIT_CB_ID :\r
-        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */\r
-        break;\r
-\r
-      case HAL_SPI_MSPDEINIT_CB_ID :\r
-        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (HAL_SPI_STATE_RESET == hspi->State)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_SPI_MSPINIT_CB_ID :\r
-        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */\r
-        break;\r
-\r
-      case HAL_SPI_MSPDEINIT_CB_ID :\r
-        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */\r
-        break;\r
-\r
-      default :\r
-        /* Update the error code */\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Update the error code */\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(hspi);\r
-  return status;\r
-}\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\r
- *  @brief   Data transfers functions\r
- *\r
-@verbatim\r
-  ==============================================================================\r
-                      ##### IO operation functions #####\r
- ===============================================================================\r
- [..]\r
-    This subsection provides a set of functions allowing to manage the SPI\r
-    data transfers.\r
-\r
-    [..] The SPI supports master and slave mode :\r
-\r
-    (#) There are two modes of transfer:\r
-       (++) Blocking mode: The communication is performed in polling mode.\r
-            The HAL status of all data processing is returned by the same function\r
-            after finishing transfer.\r
-       (++) No-Blocking mode: The communication is performed using Interrupts\r
-            or DMA, These APIs return the HAL status.\r
-            The end of the data processing will be indicated through the\r
-            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\r
-            using DMA mode.\r
-            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\r
-            will be executed respectively at the end of the transmit or Receive process\r
-            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\r
-\r
-    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\r
-        exist for 1Line (simplex) and 2Lines (full duplex) modes.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Transmit an amount of data in blocking mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pData pointer to data buffer\r
-  * @param  Size amount of data to be sent\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-  uint16_t initial_TxXferCount;\r
-\r
-  /* Check Direction parameter */\r
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  /* Init tickstart for timeout management*/\r
-  tickstart = HAL_GetTick();\r
-  initial_TxXferCount = Size;\r
-\r
-  if (hspi->State != HAL_SPI_STATE_READY)\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pTxBuffPtr  = (uint8_t *)pData;\r
-  hspi->TxXferSize  = Size;\r
-  hspi->TxXferCount = Size;\r
-\r
-  /*Init field not used in handle to zero */\r
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r
-  hspi->RxXferSize  = 0U;\r
-  hspi->RxXferCount = 0U;\r
-  hspi->TxISR       = NULL;\r
-  hspi->RxISR       = NULL;\r
-\r
-  /* Configure communication direction : 1Line */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-  {\r
-    SPI_1LINE_TX(hspi);\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-  /* Transmit data in 16 Bit mode */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
-    {\r
-      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-      hspi->pTxBuffPtr += sizeof(uint16_t);\r
-      hspi->TxXferCount--;\r
-    }\r
-    /* Transmit data in 16 Bit mode */\r
-    while (hspi->TxXferCount > 0U)\r
-    {\r
-      /* Wait until TXE flag is set to send data */\r
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r
-      {\r
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-        hspi->pTxBuffPtr += sizeof(uint16_t);\r
-        hspi->TxXferCount--;\r
-      }\r
-      else\r
-      {\r
-        /* Timeout management */\r
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
-        {\r
-          errorcode = HAL_TIMEOUT;\r
-          goto error;\r
-        }\r
-      }\r
-    }\r
-  }\r
-  /* Transmit data in 8 Bit mode */\r
-  else\r
-  {\r
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
-    {\r
-      if (hspi->TxXferCount > 1U)\r
-      {\r
-        /* write on the data register in packing mode */\r
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-        hspi->pTxBuffPtr += sizeof(uint16_t);\r
-        hspi->TxXferCount -= 2U;\r
-      }\r
-      else\r
-      {\r
-        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\r
-        hspi->pTxBuffPtr ++;\r
-        hspi->TxXferCount--;\r
-      }\r
-    }\r
-    while (hspi->TxXferCount > 0U)\r
-    {\r
-      /* Wait until TXE flag is set to send data */\r
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r
-      {\r
-        if (hspi->TxXferCount > 1U)\r
-        {\r
-          /* write on the data register in packing mode */\r
-          hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-          hspi->pTxBuffPtr += sizeof(uint16_t);\r
-          hspi->TxXferCount -= 2U;\r
-        }\r
-        else\r
-        {\r
-          *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\r
-          hspi->pTxBuffPtr++;\r
-          hspi->TxXferCount--;\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Timeout management */\r
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
-        {\r
-          errorcode = HAL_TIMEOUT;\r
-          goto error;\r
-        }\r
-      }\r
-    }\r
-  }\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Enable CRC Transmission */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Check the end of the transaction */\r
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
-  }\r
-\r
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
-  {\r
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-  }\r
-\r
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
-  {\r
-    errorcode = HAL_ERROR;\r
-  }\r
-\r
-error:\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Receive an amount of data in blocking mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pData pointer to data buffer\r
-  * @param  Size amount of data to be received\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint32_t tickstart;\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
-  {\r
-    hspi->State = HAL_SPI_STATE_BUSY_RX;\r
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
-    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);\r
-  }\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  /* Init tickstart for timeout management*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  if (hspi->State != HAL_SPI_STATE_READY)\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pRxBuffPtr  = (uint8_t *)pData;\r
-  hspi->RxXferSize  = Size;\r
-  hspi->RxXferCount = Size;\r
-\r
-  /*Init field not used in handle to zero */\r
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r
-  hspi->TxXferSize  = 0U;\r
-  hspi->TxXferCount = 0U;\r
-  hspi->RxISR       = NULL;\r
-  hspi->TxISR       = NULL;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SPI_RESET_CRC(hspi);\r
-    /* this is done to handle the CRCNEXT before the latest data */\r
-    hspi->RxXferCount--;\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Set the Rx Fifo threshold */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 16bit */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-  else\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 8bit */\r
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-\r
-  /* Configure communication direction: 1Line */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-  {\r
-    SPI_1LINE_RX(hspi);\r
-  }\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-  /* Receive data in 8 Bit mode */\r
-  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)\r
-  {\r
-    /* Transfer loop */\r
-    while (hspi->RxXferCount > 0U)\r
-    {\r
-      /* Check the RXNE flag */\r
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r
-      {\r
-        /* read the received data */\r
-        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
-        hspi->pRxBuffPtr += sizeof(uint8_t);\r
-        hspi->RxXferCount--;\r
-      }\r
-      else\r
-      {\r
-        /* Timeout management */\r
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
-        {\r
-          errorcode = HAL_TIMEOUT;\r
-          goto error;\r
-        }\r
-      }\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Transfer loop */\r
-    while (hspi->RxXferCount > 0U)\r
-    {\r
-      /* Check the RXNE flag */\r
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r
-      {\r
-        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
-        hspi->pRxBuffPtr += sizeof(uint16_t);\r
-        hspi->RxXferCount--;\r
-      }\r
-      else\r
-      {\r
-        /* Timeout management */\r
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
-        {\r
-          errorcode = HAL_TIMEOUT;\r
-          goto error;\r
-        }\r
-      }\r
-    }\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Handle the CRC Transmission */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    /* freeze the CRC before the latest data */\r
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-\r
-    /* Read the latest data */\r
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* the latest data has not been received */\r
-      errorcode = HAL_TIMEOUT;\r
-      goto error;\r
-    }\r
-\r
-    /* Receive last data in 16 Bit mode */\r
-    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-    {\r
-      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
-    }\r
-    /* Receive last data in 8 Bit mode */\r
-    else\r
-    {\r
-      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
-    }\r
-\r
-    /* Wait the CRC data */\r
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-      errorcode = HAL_TIMEOUT;\r
-      goto error;\r
-    }\r
-\r
-    /* Read CRC to Flush DR and RXNE flag */\r
-    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
-    {\r
-      /* Read 16bit CRC */\r
-      READ_REG(hspi->Instance->DR);\r
-    }\r
-    else\r
-    {\r
-      /* Read 8bit CRC */\r
-      READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
-      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
-      {\r
-        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          /* Error on the CRC reception */\r
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-          errorcode = HAL_TIMEOUT;\r
-          goto error;\r
-        }\r
-        /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
-        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-      }\r
-    }\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Check the end of the transaction */\r
-  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Check if CRC error occurred */\r
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
-  {\r
-    errorcode = HAL_ERROR;\r
-  }\r
-\r
-error :\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Transmit and Receive an amount of data in blocking mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pTxData pointer to transmission data buffer\r
-  * @param  pRxData pointer to reception data buffer\r
-  * @param  Size amount of data to be sent and received\r
-  * @param  Timeout Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\r
-                                          uint32_t Timeout)\r
-{\r
-  uint16_t             initial_TxXferCount;\r
-  uint16_t             initial_RxXferCount;\r
-  uint32_t             tmp_mode;\r
-  HAL_SPI_StateTypeDef tmp_state;\r
-  uint32_t             tickstart;\r
-#if (USE_SPI_CRC != 0U)\r
-  uint32_t             spi_cr1;\r
-  uint32_t             spi_cr2;\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Variable used to alternate Rx and Tx during transfer */\r
-  uint32_t             txallowed = 1U;\r
-  HAL_StatusTypeDef    errorcode = HAL_OK;\r
-\r
-  /* Check Direction parameter */\r
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  /* Init tickstart for timeout management*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Init temporary variables */\r
-  tmp_state           = hspi->State;\r
-  tmp_mode            = hspi->Init.Mode;\r
-  initial_TxXferCount = Size;\r
-  initial_RxXferCount = Size;\r
-#if (USE_SPI_CRC != 0U)\r
-  spi_cr1             = READ_REG(hspi->Instance->CR1);\r
-  spi_cr2             = READ_REG(hspi->Instance->CR2);\r
-#endif /* USE_SPI_CRC */\r
-\r
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \\r
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
-  {\r
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r
-  hspi->RxXferCount = Size;\r
-  hspi->RxXferSize  = Size;\r
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r
-  hspi->TxXferCount = Size;\r
-  hspi->TxXferSize  = Size;\r
-\r
-  /*Init field not used in handle to zero */\r
-  hspi->RxISR       = NULL;\r
-  hspi->TxISR       = NULL;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Set the Rx Fifo threshold */\r
-  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))\r
-  {\r
-    /* Set fiforxthreshold according the reception data length: 16bit */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-  else\r
-  {\r
-    /* Set fiforxthreshold according the reception data length: 8bit */\r
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-  /* Transmit and Receive data in 16 Bit mode */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
-    {\r
-      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-      hspi->pTxBuffPtr += sizeof(uint16_t);\r
-      hspi->TxXferCount--;\r
-    }\r
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r
-    {\r
-      /* Check TXE flag */\r
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\r
-      {\r
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-        hspi->pTxBuffPtr += sizeof(uint16_t);\r
-        hspi->TxXferCount--;\r
-        /* Next Data is a reception (Rx). Tx not allowed */\r
-        txallowed = 0U;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-        /* Enable CRC Transmission */\r
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
-        {\r
-          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
-          if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
-          {\r
-            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
-          }\r
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-        }\r
-#endif /* USE_SPI_CRC */\r
-      }\r
-\r
-      /* Check RXNE flag */\r
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\r
-      {\r
-        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
-        hspi->pRxBuffPtr += sizeof(uint16_t);\r
-        hspi->RxXferCount--;\r
-        /* Next Data is a Transmission (Tx). Tx is allowed */\r
-        txallowed = 1U;\r
-      }\r
-      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))\r
-      {\r
-        errorcode = HAL_TIMEOUT;\r
-        goto error;\r
-      }\r
-    }\r
-  }\r
-  /* Transmit and Receive data in 8 Bit mode */\r
-  else\r
-  {\r
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
-    {\r
-      if (hspi->TxXferCount > 1U)\r
-      {\r
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-        hspi->pTxBuffPtr += sizeof(uint16_t);\r
-        hspi->TxXferCount -= 2U;\r
-      }\r
-      else\r
-      {\r
-        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
-        hspi->pTxBuffPtr++;\r
-        hspi->TxXferCount--;\r
-      }\r
-    }\r
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r
-    {\r
-      /* Check TXE flag */\r
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\r
-      {\r
-        if (hspi->TxXferCount > 1U)\r
-        {\r
-          hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-          hspi->pTxBuffPtr += sizeof(uint16_t);\r
-          hspi->TxXferCount -= 2U;\r
-        }\r
-        else\r
-        {\r
-          *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
-          hspi->pTxBuffPtr++;\r
-          hspi->TxXferCount--;\r
-        }\r
-        /* Next Data is a reception (Rx). Tx not allowed */\r
-        txallowed = 0U;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-        /* Enable CRC Transmission */\r
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
-        {\r
-          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
-          if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
-          {\r
-            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
-          }\r
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-        }\r
-#endif /* USE_SPI_CRC */\r
-      }\r
-\r
-      /* Wait until RXNE flag is reset */\r
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\r
-      {\r
-        if (hspi->RxXferCount > 1U)\r
-        {\r
-          *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
-          hspi->pRxBuffPtr += sizeof(uint16_t);\r
-          hspi->RxXferCount -= 2U;\r
-          if (hspi->RxXferCount <= 1U)\r
-          {\r
-            /* Set RX Fifo threshold before to switch on 8 bit data size */\r
-            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-          }\r
-        }\r
-        else\r
-        {\r
-          (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
-          hspi->pRxBuffPtr++;\r
-          hspi->RxXferCount--;\r
-        }\r
-        /* Next Data is a Transmission (Tx). Tx is allowed */\r
-        txallowed = 1U;\r
-      }\r
-      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))\r
-      {\r
-        errorcode = HAL_TIMEOUT;\r
-        goto error;\r
-      }\r
-    }\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Read CRC from DR to close CRC calculation process */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    /* Wait until TXE flag */\r
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
-    {\r
-      /* Error on the CRC reception */\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-      errorcode = HAL_TIMEOUT;\r
-      goto error;\r
-    }\r
-    /* Read CRC */\r
-    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
-    {\r
-      /* Read 16bit CRC */\r
-      READ_REG(hspi->Instance->DR);\r
-    }\r
-    else\r
-    {\r
-      /* Read 8bit CRC */\r
-      READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
-      if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
-      {\r
-        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
-        {\r
-          /* Error on the CRC reception */\r
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-          errorcode = HAL_TIMEOUT;\r
-          goto error;\r
-        }\r
-        /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
-        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Check if CRC error occurred */\r
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-    /* Clear CRC Flag */\r
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
-\r
-    errorcode = HAL_ERROR;\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Check the end of the transaction */\r
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
-  }\r
-\r
-error :\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pData pointer to data buffer\r
-  * @param  Size amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
-  /* Check Direction parameter */\r
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  if ((pData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  if (hspi->State != HAL_SPI_STATE_READY)\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pTxBuffPtr  = (uint8_t *)pData;\r
-  hspi->TxXferSize  = Size;\r
-  hspi->TxXferCount = Size;\r
-\r
-  /* Init field not used in handle to zero */\r
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r
-  hspi->RxXferSize  = 0U;\r
-  hspi->RxXferCount = 0U;\r
-  hspi->RxISR       = NULL;\r
-\r
-  /* Set the function for IT treatment */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    hspi->TxISR = SPI_TxISR_16BIT;\r
-  }\r
-  else\r
-  {\r
-    hspi->TxISR = SPI_TxISR_8BIT;\r
-  }\r
-\r
-  /* Configure communication direction : 1Line */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-  {\r
-    SPI_1LINE_TX(hspi);\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Enable TXE and ERR interrupt */\r
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
-\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-error :\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pData pointer to data buffer\r
-  * @param  Size amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r
-  {\r
-    hspi->State = HAL_SPI_STATE_BUSY_RX;\r
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
-    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);\r
-  }\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  if (hspi->State != HAL_SPI_STATE_READY)\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pRxBuffPtr  = (uint8_t *)pData;\r
-  hspi->RxXferSize  = Size;\r
-  hspi->RxXferCount = Size;\r
-\r
-  /* Init field not used in handle to zero */\r
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r
-  hspi->TxXferSize  = 0U;\r
-  hspi->TxXferCount = 0U;\r
-  hspi->TxISR       = NULL;\r
-\r
-  /* Check the data size to adapt Rx threshold and the set the function for IT treatment */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 16 bit */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-    hspi->RxISR = SPI_RxISR_16BIT;\r
-  }\r
-  else\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 8 bit */\r
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-    hspi->RxISR = SPI_RxISR_8BIT;\r
-  }\r
-\r
-  /* Configure communication direction : 1Line */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-  {\r
-    SPI_1LINE_RX(hspi);\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    hspi->CRCSize = 1U;\r
-    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
-    {\r
-      hspi->CRCSize = 2U;\r
-    }\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-  else\r
-  {\r
-    hspi->CRCSize = 0U;\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Enable TXE and ERR interrupt */\r
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-  /* Note : The SPI must be enabled after unlocking current process\r
-            to avoid the risk of SPI interrupt handle execution before current\r
-            process unlock */\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-error :\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pTxData pointer to transmission data buffer\r
-  * @param  pRxData pointer to reception data buffer\r
-  * @param  Size amount of data to be sent and received\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
-{\r
-  uint32_t             tmp_mode;\r
-  HAL_SPI_StateTypeDef tmp_state;\r
-  HAL_StatusTypeDef    errorcode = HAL_OK;\r
-\r
-  /* Check Direction parameter */\r
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  /* Init temporary variables */\r
-  tmp_state           = hspi->State;\r
-  tmp_mode            = hspi->Init.Mode;\r
-\r
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \\r
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
-  {\r
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r
-  hspi->TxXferSize  = Size;\r
-  hspi->TxXferCount = Size;\r
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r
-  hspi->RxXferSize  = Size;\r
-  hspi->RxXferCount = Size;\r
-\r
-  /* Set the function for IT treatment */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    hspi->RxISR     = SPI_2linesRxISR_16BIT;\r
-    hspi->TxISR     = SPI_2linesTxISR_16BIT;\r
-  }\r
-  else\r
-  {\r
-    hspi->RxISR     = SPI_2linesRxISR_8BIT;\r
-    hspi->TxISR     = SPI_2linesTxISR_8BIT;\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    hspi->CRCSize = 1U;\r
-    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
-    {\r
-      hspi->CRCSize = 2U;\r
-    }\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-  else\r
-  {\r
-    hspi->CRCSize = 0U;\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Check if packing mode is enabled and if there is more than 2 data to receive */\r
-  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 16 bit */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-  else\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 8 bit */\r
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-\r
-  /* Enable TXE, RXNE and ERR interrupt */\r
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-error :\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Transmit an amount of data in non-blocking mode with DMA.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pData pointer to data buffer\r
-  * @param  Size amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
-  /* Check tx dma handle */\r
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
-\r
-  /* Check Direction parameter */\r
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  if (hspi->State != HAL_SPI_STATE_READY)\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pTxBuffPtr  = (uint8_t *)pData;\r
-  hspi->TxXferSize  = Size;\r
-  hspi->TxXferCount = Size;\r
-\r
-  /* Init field not used in handle to zero */\r
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r
-  hspi->TxISR       = NULL;\r
-  hspi->RxISR       = NULL;\r
-  hspi->RxXferSize  = 0U;\r
-  hspi->RxXferCount = 0U;\r
-\r
-  /* Configure communication direction : 1Line */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-  {\r
-    SPI_1LINE_TX(hspi);\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Set the SPI TxDMA Half transfer complete callback */\r
-  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\r
-\r
-  /* Set the SPI TxDMA transfer complete callback */\r
-  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\r
-\r
-  /* Set the DMA error callback */\r
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
-\r
-  /* Set the DMA AbortCpltCallback */\r
-  hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
-  /* Packing mode is enabled only if the DMA setting is HALWORD */\r
-  if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r
-  {\r
-    /* Check the even/odd of the data size + crc if enabled */\r
-    if ((hspi->TxXferCount & 0x1U) == 0U)\r
-    {\r
-      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
-      hspi->TxXferCount = (hspi->TxXferCount >> 1U);\r
-    }\r
-    else\r
-    {\r
-      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
-      hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r
-    }\r
-  }\r
-\r
-  /* Enable the Tx DMA Stream/Channel */\r
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))\r
-  {\r
-    /* Update SPI error code */\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
-    errorcode = HAL_ERROR;\r
-\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-    goto error;\r
-  }\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-  /* Enable the SPI Error Interrupt Bit */\r
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
-\r
-  /* Enable Tx DMA Request */\r
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
-error :\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Receive an amount of data in non-blocking mode with DMA.\r
-  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pData pointer to data buffer\r
-  * @note   When the CRC feature is enabled the pData Length must be Size + 1.\r
-  * @param  Size amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
-  /* Check rx dma handle */\r
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\r
-\r
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r
-  {\r
-    hspi->State = HAL_SPI_STATE_BUSY_RX;\r
-\r
-    /* Check tx dma handle */\r
-    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
-\r
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
-    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);\r
-  }\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  if (hspi->State != HAL_SPI_STATE_READY)\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pRxBuffPtr  = (uint8_t *)pData;\r
-  hspi->RxXferSize  = Size;\r
-  hspi->RxXferCount = Size;\r
-\r
-  /*Init field not used in handle to zero */\r
-  hspi->RxISR       = NULL;\r
-  hspi->TxISR       = NULL;\r
-  hspi->TxXferSize  = 0U;\r
-  hspi->TxXferCount = 0U;\r
-\r
-  /* Configure communication direction : 1Line */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-  {\r
-    SPI_1LINE_RX(hspi);\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 16bit */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-  else\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 8bit */\r
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
-    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
-    {\r
-      /* Set RX Fifo threshold according the reception data length: 16bit */\r
-      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
-      if ((hspi->RxXferCount & 0x1U) == 0x0U)\r
-      {\r
-        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
-        hspi->RxXferCount = hspi->RxXferCount >> 1U;\r
-      }\r
-      else\r
-      {\r
-        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
-        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Set the SPI RxDMA Half transfer complete callback */\r
-  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
-\r
-  /* Set the SPI Rx DMA transfer complete callback */\r
-  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
-\r
-  /* Set the DMA error callback */\r
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
-\r
-  /* Set the DMA AbortCpltCallback */\r
-  hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
-  /* Enable the Rx DMA Stream/Channel  */\r
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))\r
-  {\r
-    /* Update SPI error code */\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
-    errorcode = HAL_ERROR;\r
-\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-    goto error;\r
-  }\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-\r
-  /* Enable the SPI Error Interrupt Bit */\r
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
-\r
-  /* Enable Rx DMA Request */\r
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
-\r
-error:\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  pTxData pointer to transmission data buffer\r
-  * @param  pRxData pointer to reception data buffer\r
-  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1\r
-  * @param  Size amount of data to be sent\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r
-                                              uint16_t Size)\r
-{\r
-  uint32_t             tmp_mode;\r
-  HAL_SPI_StateTypeDef tmp_state;\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
-  /* Check rx & tx dma handles */\r
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\r
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
-\r
-  /* Check Direction parameter */\r
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  /* Init temporary variables */\r
-  tmp_state           = hspi->State;\r
-  tmp_mode            = hspi->Init.Mode;\r
-\r
-  if (!((tmp_state == HAL_SPI_STATE_READY) ||\r
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
-  {\r
-    errorcode = HAL_BUSY;\r
-    goto error;\r
-  }\r
-\r
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
-  {\r
-    errorcode = HAL_ERROR;\r
-    goto error;\r
-  }\r
-\r
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
-  {\r
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
-  }\r
-\r
-  /* Set the transaction information */\r
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r
-  hspi->TxXferSize  = Size;\r
-  hspi->TxXferCount = Size;\r
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r
-  hspi->RxXferSize  = Size;\r
-  hspi->RxXferCount = Size;\r
-\r
-  /* Init field not used in handle to zero */\r
-  hspi->RxISR       = NULL;\r
-  hspi->TxISR       = NULL;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Reset CRC Calculation */\r
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-  {\r
-    SPI_RESET_CRC(hspi);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  /* Reset the threshold bit */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);\r
-\r
-  /* The packing mode management is enabled by the DMA settings according the spi data size */\r
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-  {\r
-    /* Set fiforxthreshold according the reception data length: 16bit */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-  }\r
-  else\r
-  {\r
-    /* Set RX Fifo threshold according the reception data length: 8bit */\r
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
-    if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
-    {\r
-      if ((hspi->TxXferSize & 0x1U) == 0x0U)\r
-      {\r
-        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
-        hspi->TxXferCount = hspi->TxXferCount >> 1U;\r
-      }\r
-      else\r
-      {\r
-        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
-        hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r
-      }\r
-    }\r
-\r
-    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
-    {\r
-      /* Set RX Fifo threshold according the reception data length: 16bit */\r
-      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
-      if ((hspi->RxXferCount & 0x1U) == 0x0U)\r
-      {\r
-        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
-        hspi->RxXferCount = hspi->RxXferCount >> 1U;\r
-      }\r
-      else\r
-      {\r
-        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
-        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */\r
-  if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r
-  {\r
-    /* Set the SPI Rx DMA Half transfer complete callback */\r
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
-    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;\r
-  }\r
-  else\r
-  {\r
-    /* Set the SPI Tx/Rx DMA Half transfer complete callback */\r
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r
-    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;\r
-  }\r
-\r
-  /* Set the DMA error callback */\r
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
-\r
-  /* Set the DMA AbortCpltCallback */\r
-  hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
-  /* Enable the Rx DMA Stream/Channel  */\r
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))\r
-  {\r
-    /* Update SPI error code */\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
-    errorcode = HAL_ERROR;\r
-\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-    goto error;\r
-  }\r
-\r
-  /* Enable Rx DMA Request */\r
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
-\r
-  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r
-  is performed in DMA reception complete callback  */\r
-  hspi->hdmatx->XferHalfCpltCallback = NULL;\r
-  hspi->hdmatx->XferCpltCallback     = NULL;\r
-  hspi->hdmatx->XferErrorCallback    = NULL;\r
-  hspi->hdmatx->XferAbortCallback    = NULL;\r
-\r
-  /* Enable the Tx DMA Stream/Channel  */\r
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))\r
-  {\r
-    /* Update SPI error code */\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
-    errorcode = HAL_ERROR;\r
-\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-    goto error;\r
-  }\r
-\r
-  /* Check if the SPI is already enabled */\r
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
-  {\r
-    /* Enable SPI peripheral */\r
-    __HAL_SPI_ENABLE(hspi);\r
-  }\r
-  /* Enable the SPI Error Interrupt Bit */\r
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
-\r
-  /* Enable Tx DMA Request */\r
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
-error :\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing transfer (blocking mode).\r
-  * @param  hspi SPI handle.\r
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r
-  *         started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable SPI Interrupts (depending of transfer direction)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
-  * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)\r
-{\r
-  HAL_StatusTypeDef errorcode;\r
-  __IO uint32_t count, resetcount;\r
-\r
-  /* Initialized local variable  */\r
-  errorcode = HAL_OK;\r
-  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
-  count = resetcount;\r
-\r
-  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r
-\r
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r
-  {\r
-    hspi->TxISR = SPI_AbortTx_ISR;\r
-    /* Wait HAL_SPI_STATE_ABORT state */\r
-    do\r
-    {\r
-      if (count == 0U)\r
-      {\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-        break;\r
-      }\r
-      count--;\r
-    }\r
-    while (hspi->State != HAL_SPI_STATE_ABORT);\r
-    /* Reset Timeout Counter */\r
-    count = resetcount;\r
-  }\r
-\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
-  {\r
-    hspi->RxISR = SPI_AbortRx_ISR;\r
-    /* Wait HAL_SPI_STATE_ABORT state */\r
-    do\r
-    {\r
-      if (count == 0U)\r
-      {\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-        break;\r
-      }\r
-      count--;\r
-    }\r
-    while (hspi->State != HAL_SPI_STATE_ABORT);\r
-    /* Reset Timeout Counter */\r
-    count = resetcount;\r
-  }\r
-\r
-  /* Disable the SPI DMA Tx request if enabled */\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
-  {\r
-    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */\r
-    if (hspi->hdmatx != NULL)\r
-    {\r
-      /* Set the SPI DMA Abort callback :\r
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r
-      hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
-      /* Abort DMA Tx Handle linked to SPI Peripheral */\r
-      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)\r
-      {\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-\r
-      /* Disable Tx DMA Request */\r
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));\r
-\r
-      if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-      {\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-\r
-      /* Disable SPI Peripheral */\r
-      __HAL_SPI_DISABLE(hspi);\r
-\r
-      /* Empty the FRLVL fifo */\r
-      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-      {\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Disable the SPI DMA Rx request if enabled */\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
-  {\r
-    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */\r
-    if (hspi->hdmarx != NULL)\r
-    {\r
-      /* Set the SPI DMA Abort callback :\r
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r
-      hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
-      /* Abort DMA Rx Handle linked to SPI Peripheral */\r
-      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)\r
-      {\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-\r
-      /* Disable peripheral */\r
-      __HAL_SPI_DISABLE(hspi);\r
-\r
-      /* Control the BSY flag */\r
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-      {\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-\r
-      /* Empty the FRLVL fifo */\r
-      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-      {\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-\r
-      /* Disable Rx DMA Request */\r
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));\r
-    }\r
-  }\r
-  /* Reset Tx and Rx transfer counters */\r
-  hspi->RxXferCount = 0U;\r
-  hspi->TxXferCount = 0U;\r
-\r
-  /* Check error during Abort procedure */\r
-  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r
-  {\r
-    /* return HAL_Error in case of error during Abort procedure */\r
-    errorcode = HAL_ERROR;\r
-  }\r
-  else\r
-  {\r
-    /* Reset errorCode */\r
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
-  }\r
-\r
-  /* Clear the Error flags in the SR register */\r
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-  __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
-  /* Restore hspi->state to ready */\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing transfer (Interrupt mode).\r
-  * @param  hspi SPI handle.\r
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r
-  *         started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable SPI Interrupts (depending of transfer direction)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  *           - At abort completion, call user abort complete callback\r
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
-  * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)\r
-{\r
-  HAL_StatusTypeDef errorcode;\r
-  uint32_t abortcplt ;\r
-  __IO uint32_t count, resetcount;\r
-\r
-  /* Initialized local variable  */\r
-  errorcode = HAL_OK;\r
-  abortcplt = 1U;\r
-  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
-  count = resetcount;\r
-\r
-  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r
-\r
-  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r
-  {\r
-    hspi->TxISR = SPI_AbortTx_ISR;\r
-    /* Wait HAL_SPI_STATE_ABORT state */\r
-    do\r
-    {\r
-      if (count == 0U)\r
-      {\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-        break;\r
-      }\r
-      count--;\r
-    }\r
-    while (hspi->State != HAL_SPI_STATE_ABORT);\r
-    /* Reset Timeout Counter */\r
-    count = resetcount;\r
-  }\r
-\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
-  {\r
-    hspi->RxISR = SPI_AbortRx_ISR;\r
-    /* Wait HAL_SPI_STATE_ABORT state */\r
-    do\r
-    {\r
-      if (count == 0U)\r
-      {\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-        break;\r
-      }\r
-      count--;\r
-    }\r
-    while (hspi->State != HAL_SPI_STATE_ABORT);\r
-    /* Reset Timeout Counter */\r
-    count = resetcount;\r
-  }\r
-\r
-  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised\r
-     before any call to DMA Abort functions */\r
-  /* DMA Tx Handle is valid */\r
-  if (hspi->hdmatx != NULL)\r
-  {\r
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r
-       Otherwise, set it to NULL */\r
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
-    {\r
-      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;\r
-    }\r
-    else\r
-    {\r
-      hspi->hdmatx->XferAbortCallback = NULL;\r
-    }\r
-  }\r
-  /* DMA Rx Handle is valid */\r
-  if (hspi->hdmarx != NULL)\r
-  {\r
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r
-       Otherwise, set it to NULL */\r
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
-    {\r
-      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;\r
-    }\r
-    else\r
-    {\r
-      hspi->hdmarx->XferAbortCallback = NULL;\r
-    }\r
-  }\r
-\r
-  /* Disable the SPI DMA Tx request if enabled */\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
-  {\r
-    /* Abort the SPI DMA Tx Stream/Channel */\r
-    if (hspi->hdmatx != NULL)\r
-    {\r
-      /* Abort DMA Tx Handle linked to SPI Peripheral */\r
-      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\r
-      {\r
-        hspi->hdmatx->XferAbortCallback = NULL;\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-      else\r
-      {\r
-        abortcplt = 0U;\r
-      }\r
-    }\r
-  }\r
-  /* Disable the SPI DMA Rx request if enabled */\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
-  {\r
-    /* Abort the SPI DMA Rx Stream/Channel */\r
-    if (hspi->hdmarx != NULL)\r
-    {\r
-      /* Abort DMA Rx Handle linked to SPI Peripheral */\r
-      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)\r
-      {\r
-        hspi->hdmarx->XferAbortCallback = NULL;\r
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-      }\r
-      else\r
-      {\r
-        abortcplt = 0U;\r
-      }\r
-    }\r
-  }\r
-\r
-  if (abortcplt == 1U)\r
-  {\r
-    /* Reset Tx and Rx transfer counters */\r
-    hspi->RxXferCount = 0U;\r
-    hspi->TxXferCount = 0U;\r
-\r
-    /* Check error during Abort procedure */\r
-    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r
-    {\r
-      /* return HAL_Error in case of error during Abort procedure */\r
-      errorcode = HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      /* Reset errorCode */\r
-      hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
-    }\r
-\r
-    /* Clear the Error flags in the SR register */\r
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-    __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
-    /* Restore hspi->State to Ready */\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-\r
-    /* As no DMA to be aborted, call directly user Abort complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-    hspi->AbortCpltCallback(hspi);\r
-#else\r
-    HAL_SPI_AbortCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Pause the DMA Transfer.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified SPI module.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  /* Disable the SPI DMA Tx & Rx requests */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Resume the DMA Transfer.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified SPI module.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Process Locked */\r
-  __HAL_LOCK(hspi);\r
-\r
-  /* Enable the SPI DMA Tx & Rx requests */\r
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(hspi);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stop the DMA Transfer.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified SPI module.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\r
-{\r
-  HAL_StatusTypeDef errorcode = HAL_OK;\r
-  /* The Lock is not implemented on this API to allow the user application\r
-     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\r
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r
-     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\r
-     */\r
-\r
-  /* Abort the SPI DMA tx Stream/Channel  */\r
-  if (hspi->hdmatx != NULL)\r
-  {\r
-    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
-      errorcode = HAL_ERROR;\r
-    }\r
-  }\r
-  /* Abort the SPI DMA rx Stream/Channel  */\r
-  if (hspi->hdmarx != NULL)\r
-  {\r
-    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
-      errorcode = HAL_ERROR;\r
-    }\r
-  }\r
-\r
-  /* Disable the SPI DMA Tx & Rx requests */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-  return errorcode;\r
-}\r
-\r
-/**\r
-  * @brief  Handle SPI interrupt request.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified SPI module.\r
-  * @retval None\r
-  */\r
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\r
-{\r
-  uint32_t itsource = hspi->Instance->CR2;\r
-  uint32_t itflag   = hspi->Instance->SR;\r
-\r
-  /* SPI in mode Receiver ----------------------------------------------------*/\r
-  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&\r
-      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))\r
-  {\r
-    hspi->RxISR(hspi);\r
-    return;\r
-  }\r
-\r
-  /* SPI in mode Transmitter -------------------------------------------------*/\r
-  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))\r
-  {\r
-    hspi->TxISR(hspi);\r
-    return;\r
-  }\r
-\r
-  /* SPI in Error Treatment --------------------------------------------------*/\r
-  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))\r
-  {\r
-    /* SPI Overrun error interrupt occurred ----------------------------------*/\r
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)\r
-    {\r
-      if (hspi->State != HAL_SPI_STATE_BUSY_TX)\r
-      {\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);\r
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-      }\r
-      else\r
-      {\r
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-        return;\r
-      }\r
-    }\r
-\r
-    /* SPI Mode Fault error interrupt occurred -------------------------------*/\r
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);\r
-      __HAL_SPI_CLEAR_MODFFLAG(hspi);\r
-    }\r
-\r
-    /* SPI Frame error interrupt occurred ------------------------------------*/\r
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);\r
-      __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-    }\r
-\r
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
-    {\r
-      /* Disable all interrupts */\r
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);\r
-\r
-      hspi->State = HAL_SPI_STATE_READY;\r
-      /* Disable the SPI DMA requests if enabled */\r
-      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))\r
-      {\r
-        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\r
-\r
-        /* Abort the SPI DMA Rx channel */\r
-        if (hspi->hdmarx != NULL)\r
-        {\r
-          /* Set the SPI DMA Abort callback :\r
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
-          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r
-          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))\r
-          {\r
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-          }\r
-        }\r
-        /* Abort the SPI DMA Tx channel */\r
-        if (hspi->hdmatx != NULL)\r
-        {\r
-          /* Set the SPI DMA Abort callback :\r
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
-          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r
-          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))\r
-          {\r
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-          }\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-        hspi->ErrorCallback(hspi);\r
-#else\r
-        HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-      }\r
-    }\r
-    return;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Tx Transfer completed callback.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_TxCpltCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Rx Transfer completed callback.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_RxCpltCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Tx and Rx Transfer completed callback.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_TxRxCpltCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Tx Half Transfer completed callback.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Rx Half Transfer completed callback.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Tx and Rx Half Transfer callback.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  SPI error callback.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_ErrorCallback should be implemented in the user file\r
-   */\r
-  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\r
-            and user can use HAL_SPI_GetError() API to check the latest error occurred\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  SPI Abort Complete callback.\r
-  * @param  hspi SPI handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(hspi);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_SPI_AbortCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r
-  * @brief   SPI control functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Peripheral State and Errors functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to control the SPI.\r
-     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\r
-     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Return the SPI handle state.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval SPI state\r
-  */\r
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Return SPI handle state */\r
-  return hspi->State;\r
-}\r
-\r
-/**\r
-  * @brief  Return the SPI error code.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval SPI error code in bitmap format\r
-  */\r
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Return SPI ErrorCode */\r
-  return hspi->ErrorCode;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup SPI_Private_Functions\r
-  * @brief   Private functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  DMA SPI transmit process complete callback.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA module.\r
-  * @retval None\r
-  */\r
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-  uint32_t tickstart;\r
-\r
-  /* Init tickstart for timeout management*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* DMA Normal Mode */\r
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
-  {\r
-    /* Disable ERR interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
-    /* Disable Tx DMA Request */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
-    /* Check the end of the transaction */\r
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-    }\r
-\r
-    /* Clear overrun flag in 2 Lines communication mode because received data is not read */\r
-    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
-    {\r
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-    }\r
-\r
-    hspi->TxXferCount = 0U;\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-\r
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
-    {\r
-      /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-      hspi->ErrorCallback(hspi);\r
-#else\r
-      HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-      return;\r
-    }\r
-  }\r
-  /* Call user Tx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->TxCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_TxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI receive process complete callback.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA module.\r
-  * @retval None\r
-  */\r
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-  uint32_t tickstart;\r
-\r
-  /* Init tickstart for timeout management*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* DMA Normal Mode */\r
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
-  {\r
-    /* Disable ERR interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-    /* CRC handling */\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      /* Wait until RXNE flag */\r
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-      {\r
-        /* Error on the CRC reception */\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-      }\r
-      /* Read CRC */\r
-      if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
-      {\r
-        /* Read 16bit CRC */\r
-        READ_REG(hspi->Instance->DR);\r
-      }\r
-      else\r
-      {\r
-        /* Read 8bit CRC */\r
-        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
-        if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
-        {\r
-          if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-          {\r
-            /* Error on the CRC reception */\r
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-          }\r
-          /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
-          READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-        }\r
-      }\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
-    /* Check the end of the transaction */\r
-    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-    {\r
-      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
-    }\r
-\r
-    hspi->RxXferCount = 0U;\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-    /* Check if CRC error occurred */\r
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
-    {\r
-      /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-      hspi->ErrorCallback(hspi);\r
-#else\r
-      HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-      return;\r
-    }\r
-  }\r
-  /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->RxCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_RxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI transmit receive process complete callback.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA module.\r
-  * @retval None\r
-  */\r
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-  uint32_t tickstart;\r
-\r
-  /* Init tickstart for timeout management*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* DMA Normal Mode */\r
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
-  {\r
-    /* Disable ERR interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-    /* CRC handling */\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))\r
-      {\r
-        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,\r
-                                          tickstart) != HAL_OK)\r
-        {\r
-          /* Error on the CRC reception */\r
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-        }\r
-        /* Read CRC to Flush DR and RXNE flag */\r
-        READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-      }\r
-      else\r
-      {\r
-        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-        {\r
-          /* Error on the CRC reception */\r
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-        }\r
-        /* Read CRC to Flush DR and RXNE flag */\r
-        READ_REG(hspi->Instance->DR);\r
-      }\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    /* Check the end of the transaction */\r
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-    }\r
-\r
-    /* Disable Rx/Tx DMA Request */\r
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
-    hspi->TxXferCount = 0U;\r
-    hspi->RxXferCount = 0U;\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-    /* Check if CRC error occurred */\r
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
-    {\r
-      /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-      hspi->ErrorCallback(hspi);\r
-#else\r
-      HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-      return;\r
-    }\r
-  }\r
-  /* Call user TxRx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->TxRxCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_TxRxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI half transmit process complete callback.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA module.\r
-  * @retval None\r
-  */\r
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Call user Tx half complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->TxHalfCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_TxHalfCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI half receive process complete callback\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA module.\r
-  * @retval None\r
-  */\r
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Call user Rx half complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->RxHalfCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_RxHalfCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI half transmit receive process complete callback.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA module.\r
-  * @retval None\r
-  */\r
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Call user TxRx half complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->TxRxHalfCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_TxRxHalfCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI communication error callback.\r
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified DMA module.\r
-  * @retval None\r
-  */\r
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Stop the disable DMA transfer on SPI side */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
-  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-  /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->ErrorCallback(hspi);\r
-#else\r
-  HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error\r
-  *         (To be called at end of DMA Abort procedure following error occurrence).\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-  hspi->RxXferCount = 0U;\r
-  hspi->TxXferCount = 0U;\r
-\r
-  /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->ErrorCallback(hspi);\r
-#else\r
-  HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI Tx communication abort callback, when initiated by user\r
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).\r
-  * @note   When this callback is executed, User Abort complete call back is called only if no\r
-  *         Abort still ongoing for Rx DMA Handle.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
-  /* Disable Tx DMA Request */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  /* Disable SPI Peripheral */\r
-  __HAL_SPI_DISABLE(hspi);\r
-\r
-  /* Empty the FRLVL fifo */\r
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  /* Check if an Abort process is still ongoing */\r
-  if (hspi->hdmarx != NULL)\r
-  {\r
-    if (hspi->hdmarx->XferAbortCallback != NULL)\r
-    {\r
-      return;\r
-    }\r
-  }\r
-\r
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r
-  hspi->RxXferCount = 0U;\r
-  hspi->TxXferCount = 0U;\r
-\r
-  /* Check no error during Abort procedure */\r
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r
-  {\r
-    /* Reset errorCode */\r
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
-  }\r
-\r
-  /* Clear the Error flags in the SR register */\r
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-  __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
-  /* Restore hspi->State to Ready */\r
-  hspi->State  = HAL_SPI_STATE_READY;\r
-\r
-  /* Call user Abort complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->AbortCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_AbortCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA SPI Rx communication abort callback, when initiated by user\r
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).\r
-  * @note   When this callback is executed, User Abort complete call back is called only if no\r
-  *         Abort still ongoing for Tx DMA Handle.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
-  /* Disable SPI Peripheral */\r
-  __HAL_SPI_DISABLE(hspi);\r
-\r
-  hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
-  /* Disable Rx DMA Request */\r
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
-\r
-  /* Control the BSY flag */\r
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  /* Empty the FRLVL fifo */\r
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  /* Check if an Abort process is still ongoing */\r
-  if (hspi->hdmatx != NULL)\r
-  {\r
-    if (hspi->hdmatx->XferAbortCallback != NULL)\r
-    {\r
-      return;\r
-    }\r
-  }\r
-\r
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r
-  hspi->RxXferCount = 0U;\r
-  hspi->TxXferCount = 0U;\r
-\r
-  /* Check no error during Abort procedure */\r
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r
-  {\r
-    /* Reset errorCode */\r
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
-  }\r
-\r
-  /* Clear the Error flags in the SR register */\r
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-  __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
-  /* Restore hspi->State to Ready */\r
-  hspi->State  = HAL_SPI_STATE_READY;\r
-\r
-  /* Call user Abort complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-  hspi->AbortCpltCallback(hspi);\r
-#else\r
-  HAL_SPI_AbortCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Receive data in packing mode */\r
-  if (hspi->RxXferCount > 1U)\r
-  {\r
-    *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
-    hspi->pRxBuffPtr += sizeof(uint16_t);\r
-    hspi->RxXferCount -= 2U;\r
-    if (hspi->RxXferCount == 1U)\r
-    {\r
-      /* Set RX Fifo threshold according the reception data length: 8bit */\r
-      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-    }\r
-  }\r
-  /* Receive data in 8 Bit mode */\r
-  else\r
-  {\r
-    *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);\r
-    hspi->pRxBuffPtr++;\r
-    hspi->RxXferCount--;\r
-  }\r
-\r
-  /* Check end of the reception */\r
-  if (hspi->RxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;\r
-      return;\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    /* Disable RXNE  and ERR interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-    if (hspi->TxXferCount == 0U)\r
-    {\r
-      SPI_CloseRxTx_ISR(hspi);\r
-    }\r
-  }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Read 8bit CRC to flush Data Regsiter */\r
-  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
-  hspi->CRCSize--;\r
-\r
-  /* Check end of the reception */\r
-  if (hspi->CRCSize == 0U)\r
-  {\r
-    /* Disable RXNE and ERR interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-    if (hspi->TxXferCount == 0U)\r
-    {\r
-      SPI_CloseRxTx_ISR(hspi);\r
-    }\r
-  }\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
-  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Transmit data in packing Bit mode */\r
-  if (hspi->TxXferCount >= 2U)\r
-  {\r
-    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-    hspi->pTxBuffPtr += sizeof(uint16_t);\r
-    hspi->TxXferCount -= 2U;\r
-  }\r
-  /* Transmit data in 8 Bit mode */\r
-  else\r
-  {\r
-    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
-    hspi->pTxBuffPtr++;\r
-    hspi->TxXferCount--;\r
-  }\r
-\r
-  /* Check the end of the transmission */\r
-  if (hspi->TxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      /* Set CRC Next Bit to send CRC */\r
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-      /* Disable TXE interrupt */\r
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
-      return;\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    /* Disable TXE interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
-\r
-    if (hspi->RxXferCount == 0U)\r
-    {\r
-      SPI_CloseRxTx_ISR(hspi);\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Receive data in 16 Bit mode */\r
-  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
-  hspi->pRxBuffPtr += sizeof(uint16_t);\r
-  hspi->RxXferCount--;\r
-\r
-  if (hspi->RxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;\r
-      return;\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    /* Disable RXNE interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
-\r
-    if (hspi->TxXferCount == 0U)\r
-    {\r
-      SPI_CloseRxTx_ISR(hspi);\r
-    }\r
-  }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
-  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Read 16bit CRC to flush Data Regsiter */\r
-  READ_REG(hspi->Instance->DR);\r
-\r
-  /* Disable RXNE interrupt */\r
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
-\r
-  SPI_CloseRxTx_ISR(hspi);\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
-  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Transmit data in 16 Bit mode */\r
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-  hspi->pTxBuffPtr += sizeof(uint16_t);\r
-  hspi->TxXferCount--;\r
-\r
-  /* Enable CRC Transmission */\r
-  if (hspi->TxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      /* Set CRC Next Bit to send CRC */\r
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-      /* Disable TXE interrupt */\r
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
-      return;\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-\r
-    /* Disable TXE interrupt */\r
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
-\r
-    if (hspi->RxXferCount == 0U)\r
-    {\r
-      SPI_CloseRxTx_ISR(hspi);\r
-    }\r
-  }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
-  * @brief  Manage the CRC 8-bit receive in Interrupt context.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Read 8bit CRC to flush Data Register */\r
-  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
-  hspi->CRCSize--;\r
-\r
-  if (hspi->CRCSize == 0U)\r
-  {\r
-    SPI_CloseRx_ISR(hspi);\r
-  }\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
-  * @brief  Manage the receive 8-bit in Interrupt context.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);\r
-  hspi->pRxBuffPtr++;\r
-  hspi->RxXferCount--;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Enable CRC Transmission */\r
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
-  {\r
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  if (hspi->RxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      hspi->RxISR =  SPI_RxISR_8BITCRC;\r
-      return;\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-    SPI_CloseRx_ISR(hspi);\r
-  }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
-  * @brief  Manage the CRC 16-bit receive in Interrupt context.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Read 16bit CRC to flush Data Register */\r
-  READ_REG(hspi->Instance->DR);\r
-\r
-  /* Disable RXNE and ERR interrupt */\r
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-  SPI_CloseRx_ISR(hspi);\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
-  * @brief  Manage the 16-bit receive in Interrupt context.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
-  hspi->pRxBuffPtr += sizeof(uint16_t);\r
-  hspi->RxXferCount--;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Enable CRC Transmission */\r
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
-  {\r
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-\r
-  if (hspi->RxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      hspi->RxISR = SPI_RxISR_16BITCRC;\r
-      return;\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-    SPI_CloseRx_ISR(hspi);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Handle the data 8-bit transmit in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
-  hspi->pTxBuffPtr++;\r
-  hspi->TxXferCount--;\r
-\r
-  if (hspi->TxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      /* Enable CRC Transmission */\r
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-    SPI_CloseTx_ISR(hspi);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Handle the data 16-bit transmit in Interrupt mode.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Transmit data in 16 Bit mode */\r
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
-  hspi->pTxBuffPtr += sizeof(uint16_t);\r
-  hspi->TxXferCount--;\r
-\r
-  if (hspi->TxXferCount == 0U)\r
-  {\r
-#if (USE_SPI_CRC != 0U)\r
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-    {\r
-      /* Enable CRC Transmission */\r
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-    }\r
-#endif /* USE_SPI_CRC */\r
-    SPI_CloseTx_ISR(hspi);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Handle SPI Communication Timeout.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *              the configuration information for SPI module.\r
-  * @param  Flag SPI flag to check\r
-  * @param  State flag state to check\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\r
-                                                       uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)\r
-  {\r
-    if (Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))\r
-      {\r
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
-        on both master and slave sides in order to resynchronize the master\r
-        and slave for their respective CRC calculation */\r
-\r
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
-        {\r
-          /* Disable SPI peripheral */\r
-          __HAL_SPI_DISABLE(hspi);\r
-        }\r
-\r
-        /* Reset CRC Calculation */\r
-        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-        {\r
-          SPI_RESET_CRC(hspi);\r
-        }\r
-\r
-        hspi->State = HAL_SPI_STATE_READY;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hspi);\r
-\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handle SPI FIFO Communication Timeout.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *              the configuration information for SPI module.\r
-  * @param  Fifo Fifo to check\r
-  * @param  State Fifo state to check\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r
-                                                       uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  while ((hspi->Instance->SR & Fifo) != State)\r
-  {\r
-    if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))\r
-    {\r
-      /* Read 8bit CRC to flush Data Register */\r
-      READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));\r
-    }\r
-\r
-    if (Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))\r
-      {\r
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
-           on both master and slave sides in order to resynchronize the master\r
-           and slave for their respective CRC calculation */\r
-\r
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
-        {\r
-          /* Disable SPI peripheral */\r
-          __HAL_SPI_DISABLE(hspi);\r
-        }\r
-\r
-        /* Reset CRC Calculation */\r
-        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
-        {\r
-          SPI_RESET_CRC(hspi);\r
-        }\r
-\r
-        hspi->State = HAL_SPI_STATE_READY;\r
-\r
-        /* Process Unlocked */\r
-        __HAL_UNLOCK(hspi);\r
-\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handle the check of the RX transaction complete.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
-  {\r
-    /* Disable SPI peripheral */\r
-    __HAL_SPI_DISABLE(hspi);\r
-  }\r
-\r
-  /* Control the BSY flag */\r
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-    return HAL_TIMEOUT;\r
-  }\r
-\r
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
-                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
-  {\r
-    /* Empty the FRLVL fifo */\r
-    if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handle the check of the RXTX or TX transaction complete.\r
-  * @param  hspi SPI handle\r
-  * @param  Timeout Timeout duration\r
-  * @param  Tickstart tick start value\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
-  /* Control if the TX fifo is empty */\r
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-    return HAL_TIMEOUT;\r
-  }\r
-\r
-  /* Control the BSY flag */\r
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-    return HAL_TIMEOUT;\r
-  }\r
-\r
-  /* Control if the RX fifo is empty */\r
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-    return HAL_TIMEOUT;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handle the end of the RXTX transaction.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Init tickstart for timeout managment*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Disable ERR interrupt */\r
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
-  /* Check the end of the transaction */\r
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-  }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Check if CRC error occurred */\r
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
-  {\r
-    hspi->State = HAL_SPI_STATE_READY;\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
-    /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-    hspi->ErrorCallback(hspi);\r
-#else\r
-    HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-#endif /* USE_SPI_CRC */\r
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
-    {\r
-      if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r
-      {\r
-        hspi->State = HAL_SPI_STATE_READY;\r
-        /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-        hspi->RxCpltCallback(hspi);\r
-#else\r
-        HAL_SPI_RxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-      }\r
-      else\r
-      {\r
-        hspi->State = HAL_SPI_STATE_READY;\r
-        /* Call user TxRx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-        hspi->TxRxCpltCallback(hspi);\r
-#else\r
-        HAL_SPI_TxRxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-      }\r
-    }\r
-    else\r
-    {\r
-      hspi->State = HAL_SPI_STATE_READY;\r
-      /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-      hspi->ErrorCallback(hspi);\r
-#else\r
-      HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-    }\r
-#if (USE_SPI_CRC != 0U)\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-}\r
-\r
-/**\r
-  * @brief  Handle the end of the RX transaction.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
-  /* Disable RXNE and ERR interrupt */\r
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
-  /* Check the end of the transaction */\r
-  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-  }\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-  /* Check if CRC error occurred */\r
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
-    /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-    hspi->ErrorCallback(hspi);\r
-#else\r
-    HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-#endif /* USE_SPI_CRC */\r
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
-    {\r
-      /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-      hspi->RxCpltCallback(hspi);\r
-#else\r
-      HAL_SPI_RxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-    }\r
-    else\r
-    {\r
-      /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-      hspi->ErrorCallback(hspi);\r
-#else\r
-      HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-    }\r
-#if (USE_SPI_CRC != 0U)\r
-  }\r
-#endif /* USE_SPI_CRC */\r
-}\r
-\r
-/**\r
-  * @brief  Handle the end of the TX transaction.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Init tickstart for timeout management*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Disable TXE and ERR interrupt */\r
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
-\r
-  /* Check the end of the transaction */\r
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
-  {\r
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
-  }\r
-\r
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
-  {\r
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
-  }\r
-\r
-  hspi->State = HAL_SPI_STATE_READY;\r
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
-  {\r
-    /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-    hspi->ErrorCallback(hspi);\r
-#else\r
-    HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-  }\r
-  else\r
-  {\r
-    /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-    hspi->TxCpltCallback(hspi);\r
-#else\r
-    HAL_SPI_TxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Handle abort a Rx transaction.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
-  __IO uint32_t count;\r
-\r
-  /* Disable SPI Peripheral */\r
-  __HAL_SPI_DISABLE(hspi);\r
-\r
-  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
-\r
-  /* Disable RXNEIE interrupt */\r
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));\r
-\r
-  /* Check RXNEIE is disabled */\r
-  do\r
-  {\r
-    if (count == 0U)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-      break;\r
-    }\r
-    count--;\r
-  }\r
-  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));\r
-\r
-  /* Control the BSY flag */\r
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  /* Empty the FRLVL fifo */\r
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  hspi->State = HAL_SPI_STATE_ABORT;\r
-}\r
-\r
-/**\r
-  * @brief  Handle abort a Tx or Rx/Tx transaction.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for SPI module.\r
-  * @retval None\r
-  */\r
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
-  __IO uint32_t count;\r
-\r
-  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
-\r
-  /* Disable TXEIE interrupt */\r
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));\r
-\r
-  /* Check TXEIE is disabled */\r
-  do\r
-  {\r
-    if (count == 0U)\r
-    {\r
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-      break;\r
-    }\r
-    count--;\r
-  }\r
-  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));\r
-\r
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  /* Disable SPI Peripheral */\r
-  __HAL_SPI_DISABLE(hspi);\r
-\r
-  /* Empty the FRLVL fifo */\r
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-  {\r
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-  }\r
-\r
-  /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */\r
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
-  {\r
-    /* Disable RXNEIE interrupt */\r
-    CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));\r
-\r
-    /* Check RXNEIE is disabled */\r
-    do\r
-    {\r
-      if (count == 0U)\r
-      {\r
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
-        break;\r
-      }\r
-      count--;\r
-    }\r
-    while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));\r
-\r
-    /* Control the BSY flag */\r
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-    {\r
-      hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-    }\r
-\r
-    /* Empty the FRLVL fifo */\r
-    if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
-    {\r
-      hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
-    }\r
-  }\r
-  hspi->State = HAL_SPI_STATE_ABORT;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_SPI_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
deleted file mode 100644 (file)
index 6aae121..0000000
+++ /dev/null
@@ -1,115 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_spi_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   Extended SPI HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          SPI peripheral extended functionalities :\r
-  *           + IO operation functions\r
-  *\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup SPIEx SPIEx\r
-  * @brief SPI Extended HAL module driver\r
-  * @{\r
-  */\r
-#ifdef HAL_SPI_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private defines -----------------------------------------------------------*/\r
-/** @defgroup SPIEx_Private_Constants SPIEx Private Constants\r
-  * @{\r
-  */\r
-#define SPI_FIFO_SIZE       4UL\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions\r
-  *  @brief   Data transfers functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                      ##### IO operation functions #####\r
- ===============================================================================\r
- [..]\r
-    This subsection provides a set of extended functions to manage the SPI\r
-    data transfers.\r
-\r
-    (#) Rx data flush function:\r
-        (++) HAL_SPIEx_FlushRxFifo()\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Flush the RX fifo.\r
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified SPI module.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)\r
-{\r
-  __IO uint32_t tmpreg;\r
-  uint8_t  count = 0U;\r
-  while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)\r
-  {\r
-    count++;\r
-    tmpreg = hspi->Instance->DR;\r
-    UNUSED(tmpreg); /* To avoid GCC warning */\r
-    if (count == SPI_FIFO_SIZE)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_SPI_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
deleted file mode 100644 (file)
index ef36e7c..0000000
+++ /dev/null
@@ -1,6904 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_tim.c\r
-  * @author  MCD Application Team\r
-  * @brief   TIM HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Timer (TIM) peripheral:\r
-  *           + TIM Time Base Initialization\r
-  *           + TIM Time Base Start\r
-  *           + TIM Time Base Start Interruption\r
-  *           + TIM Time Base Start DMA\r
-  *           + TIM Output Compare/PWM Initialization\r
-  *           + TIM Output Compare/PWM Channel Configuration\r
-  *           + TIM Output Compare/PWM  Start\r
-  *           + TIM Output Compare/PWM  Start Interruption\r
-  *           + TIM Output Compare/PWM Start DMA\r
-  *           + TIM Input Capture Initialization\r
-  *           + TIM Input Capture Channel Configuration\r
-  *           + TIM Input Capture Start\r
-  *           + TIM Input Capture Start Interruption\r
-  *           + TIM Input Capture Start DMA\r
-  *           + TIM One Pulse Initialization\r
-  *           + TIM One Pulse Channel Configuration\r
-  *           + TIM One Pulse Start\r
-  *           + TIM Encoder Interface Initialization\r
-  *           + TIM Encoder Interface Start\r
-  *           + TIM Encoder Interface Start Interruption\r
-  *           + TIM Encoder Interface Start DMA\r
-  *           + Commutation Event configuration with Interruption and DMA\r
-  *           + TIM OCRef clear configuration\r
-  *           + TIM External Clock configuration\r
-  @verbatim\r
-  ==============================================================================\r
-                      ##### TIMER Generic features #####\r
-  ==============================================================================\r
-  [..] The Timer features include:\r
-       (#) 16-bit up, down, up/down auto-reload counter.\r
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the\r
-           counter clock frequency either by any factor between 1 and 65536.\r
-       (#) Up to 4 independent channels for:\r
-           (++) Input Capture\r
-           (++) Output Compare\r
-           (++) PWM generation (Edge and Center-aligned Mode)\r
-           (++) One-pulse mode output\r
-       (#) Synchronization circuit to control the timer with external signals and to interconnect\r
-            several timers together.\r
-       (#) Supports incremental encoder for positioning purposes\r
-\r
-            ##### How to use this driver #####\r
-  ==============================================================================\r
-    [..]\r
-     (#) Initialize the TIM low level resources by implementing the following functions\r
-         depending on the selected feature:\r
-           (++) Time Base : HAL_TIM_Base_MspInit()\r
-           (++) Input Capture : HAL_TIM_IC_MspInit()\r
-           (++) Output Compare : HAL_TIM_OC_MspInit()\r
-           (++) PWM generation : HAL_TIM_PWM_MspInit()\r
-           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
-           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
-\r
-     (#) Initialize the TIM low level resources :\r
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
-        (##) TIM pins configuration\r
-            (+++) Enable the clock for the TIM GPIOs using the following function:\r
-             __HAL_RCC_GPIOx_CLK_ENABLE();\r
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
-\r
-     (#) The external Clock can be configured, if needed (the default clock is the\r
-         internal clock from the APBx), using the following function:\r
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
-         any start function.\r
-\r
-     (#) Configure the TIM in the desired functioning mode using one of the\r
-       Initialization function of this driver:\r
-       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
-       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an\r
-            Output Compare signal.\r
-       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a\r
-            PWM signal.\r
-       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an\r
-            external signal.\r
-       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer\r
-            in One Pulse Mode.\r
-       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
-\r
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:\r
-           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
-           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
-           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
-           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
-           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
-           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
-\r
-     (#) The DMA Burst is managed with the two following functions:\r
-         HAL_TIM_DMABurst_WriteStart()\r
-         HAL_TIM_DMABurst_ReadStart()\r
-\r
-    *** Callback registration ***\r
-  =============================================\r
-\r
-  [..]\r
-  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1\r
-  allows the user to configure dynamically the driver callbacks.\r
-\r
-  [..]\r
-  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.\r
-  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,\r
-  the Callback ID and a pointer to the user callback function.\r
-\r
-  [..]\r
-  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default\r
-  weak function.\r
-  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
-  and the Callback ID.\r
-\r
-  [..]\r
-  These functions allow to register/unregister following callbacks:\r
-    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.\r
-    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.\r
-    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.\r
-    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.\r
-    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.\r
-    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.\r
-    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.\r
-    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.\r
-    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.\r
-    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.\r
-    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.\r
-    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.\r
-    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.\r
-    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.\r
-    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.\r
-    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.\r
-    (+) TriggerCallback                   : TIM Trigger Callback.\r
-    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.\r
-    (+) IC_CaptureCallback                : TIM Input Capture Callback.\r
-    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.\r
-    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.\r
-    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.\r
-    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.\r
-    (+) ErrorCallback                     : TIM Error Callback.\r
-    (+) CommutationCallback               : TIM Commutation Callback.\r
-    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.\r
-    (+) BreakCallback                     : TIM Break Callback.\r
-    (+) Break2Callback                    : TIM Break2 Callback.\r
-\r
-  [..]\r
-By default, after the Init and when the state is HAL_TIM_STATE_RESET\r
-all interrupt callbacks are set to the corresponding weak functions:\r
-  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().\r
-\r
-  [..]\r
-  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\r
-  functionalities in the Init / DeInit only when these callbacks are null\r
-  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit\r
-    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)\r
-\r
-  [..]\r
-    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.\r
-    Exception done MspInit / MspDeInit that can be registered / unregistered\r
-    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,\r
-    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.\r
-  In that case first register the MspInit/MspDeInit user callbacks\r
-      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.\r
-\r
-  [..]\r
-      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or\r
-      not defined, the callback registration feature is not available and all callbacks\r
-      are set to the corresponding weak functions.\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup TIM TIM\r
-  * @brief TIM HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_TIM_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @addtogroup TIM_Private_Functions\r
-  * @{\r
-  */\r
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
-                              uint32_t TIM_ICFilter);\r
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
-                              uint32_t TIM_ICFilter);\r
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
-                              uint32_t TIM_ICFilter);\r
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);\r
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);\r
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);\r
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);\r
-/**\r
-  * @}\r
-  */\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
-  *  @brief    Time Base functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-              ##### Time Base functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Initialize and configure the TIM base.\r
-    (+) De-initialize the TIM base.\r
-    (+) Start the Time Base.\r
-    (+) Stop the Time Base.\r
-    (+) Start the Time Base and enable interrupt.\r
-    (+) Stop the Time Base and disable interrupt.\r
-    (+) Start the Time Base and enable DMA transfer.\r
-    (+) Stop the Time Base and disable DMA transfer.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initializes the TIM Time base Unit according to the specified\r
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.\r
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
-  *         requires a timer reset to avoid unexpected direction\r
-  *         due to DIR bit readonly in center aligned mode.\r
-  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the TIM handle allocation */\r
-  if (htim == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
-  if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    htim->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-    /* Reset interrupt callbacks to legacy weak callbacks */\r
-    TIM_ResetCallback(htim);\r
-\r
-    if (htim->Base_MspInitCallback == NULL)\r
-    {\r
-      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;\r
-    }\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    htim->Base_MspInitCallback(htim);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    HAL_TIM_Base_MspInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Set the Time Base configuration */\r
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
-  /* Initialize the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes the TIM Base peripheral\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the TIM Peripheral Clock */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  if (htim->Base_MspDeInitCallback == NULL)\r
-  {\r
-    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  htim->Base_MspDeInitCallback(htim);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
-  HAL_TIM_Base_MspDeInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  /* Change TIM state */\r
-  htim->State = HAL_TIM_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM Base MSP.\r
-  * @param  htim TIM Base handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_Base_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes TIM Base MSP.\r
-  * @param  htim TIM Base handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Starts the TIM Base generation.\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Change the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Base generation.\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Base generation in interrupt mode.\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  /* Enable the TIM Update interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Base generation in interrupt mode.\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-  /* Disable the TIM Update interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Base generation in DMA mode.\r
-  * @param  htim TIM Base handle\r
-  * @param  pData The source Buffer address.\r
-  * @param  Length The length of data to be transferred from memory to peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if ((pData == NULL) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-  /* Set the DMA Period elapsed callbacks */\r
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
-\r
-  /* Set the DMA error callback */\r
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
-\r
-  /* Enable the DMA channel */\r
-  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Enable the TIM Update DMA request */\r
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Base generation in DMA mode.\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
-\r
-  /* Disable the TIM Update DMA request */\r
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
-\r
-  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
-  *  @brief    TIM Output Compare functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                  ##### TIM Output Compare functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Initialize and configure the TIM Output Compare.\r
-    (+) De-initialize the TIM Output Compare.\r
-    (+) Start the TIM Output Compare.\r
-    (+) Stop the TIM Output Compare.\r
-    (+) Start the TIM Output Compare and enable interrupt.\r
-    (+) Stop the TIM Output Compare and disable interrupt.\r
-    (+) Start the TIM Output Compare and enable DMA transfer.\r
-    (+) Stop the TIM Output Compare and disable DMA transfer.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initializes the TIM Output Compare according to the specified\r
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
-  *         requires a timer reset to avoid unexpected direction\r
-  *         due to DIR bit readonly in center aligned mode.\r
-  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()\r
-  * @param  htim TIM Output Compare handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the TIM handle allocation */\r
-  if (htim == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
-  if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    htim->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-    /* Reset interrupt callbacks to legacy weak callbacks */\r
-    TIM_ResetCallback(htim);\r
-\r
-    if (htim->OC_MspInitCallback == NULL)\r
-    {\r
-      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;\r
-    }\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    htim->OC_MspInitCallback(htim);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
-    HAL_TIM_OC_MspInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Init the base time for the Output Compare */\r
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init);\r
-\r
-  /* Initialize the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes the TIM peripheral\r
-  * @param  htim TIM Output Compare handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the TIM Peripheral Clock */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  if (htim->OC_MspDeInitCallback == NULL)\r
-  {\r
-    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  htim->OC_MspDeInitCallback(htim);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
-  HAL_TIM_OC_MspDeInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  /* Change TIM state */\r
-  htim->State = HAL_TIM_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM Output Compare MSP.\r
-  * @param  htim TIM Output Compare handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_OC_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes TIM Output Compare MSP.\r
-  * @param  htim TIM Output Compare handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Output Compare signal generation.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Enable the Output compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Output Compare signal generation.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Disable the Output compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Enable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Enable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Enable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Enable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the Output compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Disable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Output compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @param  pData The source Buffer address.\r
-  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if ((pData == NULL) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Enable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Enable the TIM Capture/Compare 2 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 3 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 4 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the Output compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Disable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Output compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions\r
-  *  @brief    TIM PWM functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                          ##### TIM PWM functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Initialize and configure the TIM PWM.\r
-    (+) De-initialize the TIM PWM.\r
-    (+) Start the TIM PWM.\r
-    (+) Stop the TIM PWM.\r
-    (+) Start the TIM PWM and enable interrupt.\r
-    (+) Stop the TIM PWM and disable interrupt.\r
-    (+) Start the TIM PWM and enable DMA transfer.\r
-    (+) Stop the TIM PWM and disable DMA transfer.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initializes the TIM PWM Time Base according to the specified\r
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
-  *         requires a timer reset to avoid unexpected direction\r
-  *         due to DIR bit readonly in center aligned mode.\r
-  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()\r
-  * @param  htim TIM PWM handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the TIM handle allocation */\r
-  if (htim == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
-  if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    htim->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-    /* Reset interrupt callbacks to legacy weak callbacks */\r
-    TIM_ResetCallback(htim);\r
-\r
-    if (htim->PWM_MspInitCallback == NULL)\r
-    {\r
-      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;\r
-    }\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    htim->PWM_MspInitCallback(htim);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
-    HAL_TIM_PWM_MspInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Init the base time for the PWM */\r
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
-  /* Initialize the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes the TIM peripheral\r
-  * @param  htim TIM PWM handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the TIM Peripheral Clock */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  if (htim->PWM_MspDeInitCallback == NULL)\r
-  {\r
-    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  htim->PWM_MspDeInitCallback(htim);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
-  HAL_TIM_PWM_MspDeInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  /* Change TIM state */\r
-  htim->State = HAL_TIM_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM PWM MSP.\r
-  * @param  htim TIM PWM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_PWM_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes TIM PWM MSP.\r
-  * @param  htim TIM PWM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Starts the PWM signal generation.\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Enable the Capture compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the PWM signal generation.\r
-  * @param  htim TIM PWM handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Disable the Capture compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the PWM signal generation in interrupt mode.\r
-  * @param  htim TIM PWM handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Enable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Enable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Enable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Enable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the Capture compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the PWM signal generation in interrupt mode.\r
-  * @param  htim TIM PWM handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Disable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Capture compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM PWM signal generation in DMA mode.\r
-  * @param  htim TIM PWM handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @param  pData The source Buffer address.\r
-  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if ((pData == NULL) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Enable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 2 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Output Capture/Compare 3 request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 4 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the Capture compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM PWM signal generation in DMA mode.\r
-  * @param  htim TIM PWM handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Disable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Capture compare channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
-  *  @brief    TIM Input Capture functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-              ##### TIM Input Capture functions #####\r
-  ==============================================================================\r
- [..]\r
-   This section provides functions allowing to:\r
-   (+) Initialize and configure the TIM Input Capture.\r
-   (+) De-initialize the TIM Input Capture.\r
-   (+) Start the TIM Input Capture.\r
-   (+) Stop the TIM Input Capture.\r
-   (+) Start the TIM Input Capture and enable interrupt.\r
-   (+) Stop the TIM Input Capture and disable interrupt.\r
-   (+) Start the TIM Input Capture and enable DMA transfer.\r
-   (+) Stop the TIM Input Capture and disable DMA transfer.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initializes the TIM Input Capture Time base according to the specified\r
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
-  *         requires a timer reset to avoid unexpected direction\r
-  *         due to DIR bit readonly in center aligned mode.\r
-  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()\r
-  * @param  htim TIM Input Capture handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the TIM handle allocation */\r
-  if (htim == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
-  if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    htim->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-    /* Reset interrupt callbacks to legacy weak callbacks */\r
-    TIM_ResetCallback(htim);\r
-\r
-    if (htim->IC_MspInitCallback == NULL)\r
-    {\r
-      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;\r
-    }\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    htim->IC_MspInitCallback(htim);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
-    HAL_TIM_IC_MspInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Init the base time for the input capture */\r
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
-  /* Initialize the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes the TIM peripheral\r
-  * @param  htim TIM Input Capture handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the TIM Peripheral Clock */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  if (htim->IC_MspDeInitCallback == NULL)\r
-  {\r
-    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  htim->IC_MspDeInitCallback(htim);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
-  HAL_TIM_IC_MspDeInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  /* Change TIM state */\r
-  htim->State = HAL_TIM_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM Input Capture MSP.\r
-  * @param  htim TIM Input Capture handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_IC_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes TIM Input Capture MSP.\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Input Capture measurement.\r
-  * @param  htim TIM Input Capture handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Enable the Input Capture channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Input Capture measurement.\r
-  * @param  htim TIM Input Capture handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Disable the Input Capture channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Input Capture measurement in interrupt mode.\r
-  * @param  htim TIM Input Capture handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Enable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Enable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Enable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Enable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-  /* Enable the Input Capture channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Input Capture measurement in interrupt mode.\r
-  * @param  htim TIM Input Capture handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Disable the TIM Capture/Compare 4 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Input Capture channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Input Capture measurement in DMA mode.\r
-  * @param  htim TIM Input Capture handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @param  pData The destination Buffer address.\r
-  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if ((pData == NULL) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 2  DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 3  DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 4  DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the Input Capture channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Input Capture measurement in DMA mode.\r
-  * @param  htim TIM Input Capture handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3  DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Disable the TIM Capture/Compare 4  DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Input Capture channel */\r
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
-  *  @brief    TIM One Pulse functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                        ##### TIM One Pulse functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Initialize and configure the TIM One Pulse.\r
-    (+) De-initialize the TIM One Pulse.\r
-    (+) Start the TIM One Pulse.\r
-    (+) Stop the TIM One Pulse.\r
-    (+) Start the TIM One Pulse and enable interrupt.\r
-    (+) Stop the TIM One Pulse and disable interrupt.\r
-    (+) Start the TIM One Pulse and enable DMA transfer.\r
-    (+) Stop the TIM One Pulse and disable DMA transfer.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initializes the TIM One Pulse Time Base according to the specified\r
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
-  *         requires a timer reset to avoid unexpected direction\r
-  *         due to DIR bit readonly in center aligned mode.\r
-  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OnePulseMode Select the One pulse mode.\r
-  *         This parameter can be one of the following values:\r
-  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
-  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
-{\r
-  /* Check the TIM handle allocation */\r
-  if (htim == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
-  assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
-  if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    htim->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-    /* Reset interrupt callbacks to legacy weak callbacks */\r
-    TIM_ResetCallback(htim);\r
-\r
-    if (htim->OnePulse_MspInitCallback == NULL)\r
-    {\r
-      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;\r
-    }\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    htim->OnePulse_MspInitCallback(htim);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
-    HAL_TIM_OnePulse_MspInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Configure the Time base in the One Pulse Mode */\r
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
-  /* Reset the OPM Bit */\r
-  htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
-\r
-  /* Configure the OPM Mode */\r
-  htim->Instance->CR1 |= OnePulseMode;\r
-\r
-  /* Initialize the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes the TIM One Pulse\r
-  * @param  htim TIM One Pulse handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the TIM Peripheral Clock */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  if (htim->OnePulse_MspDeInitCallback == NULL)\r
-  {\r
-    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  htim->OnePulse_MspDeInitCallback(htim);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
-  HAL_TIM_OnePulse_MspDeInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  /* Change TIM state */\r
-  htim->State = HAL_TIM_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM One Pulse MSP.\r
-  * @param  htim TIM One Pulse handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes TIM One Pulse MSP.\r
-  * @param  htim TIM One Pulse handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM One Pulse signal generation.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(OutputChannel);\r
-\r
-  /* Enable the Capture compare and the Input Capture channels\r
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
-\r
-    No need to enable the counter, it's enabled automatically by hardware\r
-    (the counter starts in response to a stimulus and generate a pulse */\r
-\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM One Pulse signal generation.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channels to be disable\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(OutputChannel);\r
-\r
-  /* Disable the Capture compare and the Input Capture channels\r
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
-\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(OutputChannel);\r
-\r
-  /* Enable the Capture compare and the Input Capture channels\r
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
-\r
-    No need to enable the counter, it's enabled automatically by hardware\r
-    (the counter starts in response to a stimulus and generate a pulse */\r
-\r
-  /* Enable the TIM Capture/Compare 1 interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-\r
-  /* Enable the TIM Capture/Compare 2 interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Enable the main output */\r
-    __HAL_TIM_MOE_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(OutputChannel);\r
-\r
-  /* Disable the TIM Capture/Compare 1 interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-\r
-  /* Disable the TIM Capture/Compare 2 interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-\r
-  /* Disable the Capture compare and the Input Capture channels\r
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
-  {\r
-    /* Disable the Main Output */\r
-    __HAL_TIM_MOE_DISABLE(htim);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
-  *  @brief    TIM Encoder functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                          ##### TIM Encoder functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Initialize and configure the TIM Encoder.\r
-    (+) De-initialize the TIM Encoder.\r
-    (+) Start the TIM Encoder.\r
-    (+) Stop the TIM Encoder.\r
-    (+) Start the TIM Encoder and enable interrupt.\r
-    (+) Stop the TIM Encoder and disable interrupt.\r
-    (+) Start the TIM Encoder and enable DMA transfer.\r
-    (+) Stop the TIM Encoder and disable DMA transfer.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.\r
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
-  *         requires a timer reset to avoid unexpected direction\r
-  *         due to DIR bit readonly in center aligned mode.\r
-  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()\r
-  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together\r
-  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource\r
-  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @param  sConfig TIM Encoder Interface configuration structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)\r
-{\r
-  uint32_t tmpsmcr;\r
-  uint32_t tmpccmr1;\r
-  uint32_t tmpccer;\r
-\r
-  /* Check the TIM handle allocation */\r
-  if (htim == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
-\r
-  if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    htim->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-    /* Reset interrupt callbacks to legacy weak callbacks */\r
-    TIM_ResetCallback(htim);\r
-\r
-    if (htim->Encoder_MspInitCallback == NULL)\r
-    {\r
-      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;\r
-    }\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    htim->Encoder_MspInitCallback(htim);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
-    HAL_TIM_Encoder_MspInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Reset the SMS and ECE bits */\r
-  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);\r
-\r
-  /* Configure the Time base in the Encoder Mode */\r
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
-  /* Get the TIMx SMCR register value */\r
-  tmpsmcr = htim->Instance->SMCR;\r
-\r
-  /* Get the TIMx CCMR1 register value */\r
-  tmpccmr1 = htim->Instance->CCMR1;\r
-\r
-  /* Get the TIMx CCER register value */\r
-  tmpccer = htim->Instance->CCER;\r
-\r
-  /* Set the encoder Mode */\r
-  tmpsmcr |= sConfig->EncoderMode;\r
-\r
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));\r
-\r
-  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
-  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);\r
-  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);\r
-\r
-  /* Set the TI1 and the TI2 Polarities */\r
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);\r
-\r
-  /* Write to TIMx SMCR */\r
-  htim->Instance->SMCR = tmpsmcr;\r
-\r
-  /* Write to TIMx CCMR1 */\r
-  htim->Instance->CCMR1 = tmpccmr1;\r
-\r
-  /* Write to TIMx CCER */\r
-  htim->Instance->CCER = tmpccer;\r
-\r
-  /* Initialize the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  DeInitializes the TIM Encoder interface\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the TIM Peripheral Clock */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  if (htim->Encoder_MspDeInitCallback == NULL)\r
-  {\r
-    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  htim->Encoder_MspDeInitCallback(htim);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
-  HAL_TIM_Encoder_MspDeInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  /* Change TIM state */\r
-  htim->State = HAL_TIM_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM Encoder Interface MSP.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes TIM Encoder Interface MSP.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Encoder Interface.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-  /* Enable the encoder interface channels */\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-      break;\r
-    }\r
-\r
-    default :\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-      break;\r
-    }\r
-  }\r
-  /* Enable the Peripheral */\r
-  __HAL_TIM_ENABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Encoder Interface.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-  /* Disable the Input Capture channels 1 and 2\r
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-      break;\r
-    }\r
-\r
-    default :\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-      break;\r
-    }\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Encoder Interface in interrupt mode.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-  /* Enable the encoder interface channels */\r
-  /* Enable the capture compare Interrupts 1 and/or 2 */\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    default :\r
-    {\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-  }\r
-\r
-  /* Enable the Peripheral */\r
-  __HAL_TIM_ENABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Encoder Interface in interrupt mode.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @param  Channel TIM Channels to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-  /* Disable the Input Capture channels 1 and 2\r
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
-  if (Channel == TIM_CHANNEL_1)\r
-  {\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
-    /* Disable the capture compare Interrupts 1 */\r
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-  }\r
-  else if (Channel == TIM_CHANNEL_2)\r
-  {\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
-    /* Disable the capture compare Interrupts 2 */\r
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-  }\r
-  else\r
-  {\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
-    /* Disable the capture compare Interrupts 1 and 2 */\r
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Encoder Interface in DMA mode.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
-  * @param  pData1 The destination Buffer address for IC1.\r
-  * @param  pData2 The destination Buffer address for IC2.\r
-  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\r
-                                            uint32_t *pData2, uint16_t Length)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Input Capture DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-\r
-      /* Enable the Peripheral */\r
-      __HAL_TIM_ENABLE(htim);\r
-\r
-      /* Enable the Capture compare channel */\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Input Capture  DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-\r
-      /* Enable the Peripheral */\r
-      __HAL_TIM_ENABLE(htim);\r
-\r
-      /* Enable the Capture compare channel */\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_ALL:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the Peripheral */\r
-      __HAL_TIM_ENABLE(htim);\r
-\r
-      /* Enable the Capture compare channel */\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-\r
-      /* Enable the TIM Input Capture  DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-      /* Enable the TIM Input Capture  DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Encoder Interface in DMA mode.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
-  /* Disable the Input Capture channels 1 and 2\r
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
-  if (Channel == TIM_CHANNEL_1)\r
-  {\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
-    /* Disable the capture compare DMA Request 1 */\r
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-  }\r
-  else if (Channel == TIM_CHANNEL_2)\r
-  {\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
-    /* Disable the capture compare DMA Request 2 */\r
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-  }\r
-  else\r
-  {\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
-    /* Disable the capture compare DMA Request 1 and 2 */\r
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-  }\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
-  *  @brief    TIM IRQ handler management\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                        ##### IRQ handler management #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides Timer IRQ handler function.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  This function handles TIM interrupts requests.\r
-  * @param  htim TIM  handle\r
-  * @retval None\r
-  */\r
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Capture compare 1 event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)\r
-    {\r
-      {\r
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
-\r
-        /* Input capture event */\r
-        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)\r
-        {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-          htim->IC_CaptureCallback(htim);\r
-#else\r
-          HAL_TIM_IC_CaptureCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-        }\r
-        /* Output compare event */\r
-        else\r
-        {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-          htim->OC_DelayElapsedCallback(htim);\r
-          htim->PWM_PulseFinishedCallback(htim);\r
-#else\r
-          HAL_TIM_OC_DelayElapsedCallback(htim);\r
-          HAL_TIM_PWM_PulseFinishedCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-        }\r
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-      }\r
-    }\r
-  }\r
-  /* Capture compare 2 event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
-      /* Input capture event */\r
-      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)\r
-      {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-        htim->IC_CaptureCallback(htim);\r
-#else\r
-        HAL_TIM_IC_CaptureCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-      }\r
-      /* Output compare event */\r
-      else\r
-      {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-        htim->OC_DelayElapsedCallback(htim);\r
-        htim->PWM_PulseFinishedCallback(htim);\r
-#else\r
-        HAL_TIM_OC_DelayElapsedCallback(htim);\r
-        HAL_TIM_PWM_PulseFinishedCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-      }\r
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-    }\r
-  }\r
-  /* Capture compare 3 event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
-      /* Input capture event */\r
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)\r
-      {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-        htim->IC_CaptureCallback(htim);\r
-#else\r
-        HAL_TIM_IC_CaptureCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-      }\r
-      /* Output compare event */\r
-      else\r
-      {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-        htim->OC_DelayElapsedCallback(htim);\r
-        htim->PWM_PulseFinishedCallback(htim);\r
-#else\r
-        HAL_TIM_OC_DelayElapsedCallback(htim);\r
-        HAL_TIM_PWM_PulseFinishedCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-      }\r
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-    }\r
-  }\r
-  /* Capture compare 4 event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
-      /* Input capture event */\r
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)\r
-      {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-        htim->IC_CaptureCallback(htim);\r
-#else\r
-        HAL_TIM_IC_CaptureCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-      }\r
-      /* Output compare event */\r
-      else\r
-      {\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-        htim->OC_DelayElapsedCallback(htim);\r
-        htim->PWM_PulseFinishedCallback(htim);\r
-#else\r
-        HAL_TIM_OC_DelayElapsedCallback(htim);\r
-        HAL_TIM_PWM_PulseFinishedCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-      }\r
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-    }\r
-  }\r
-  /* TIM Update event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-      htim->PeriodElapsedCallback(htim);\r
-#else\r
-      HAL_TIM_PeriodElapsedCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  /* TIM Break input event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-      htim->BreakCallback(htim);\r
-#else\r
-      HAL_TIMEx_BreakCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  /* TIM Break2 input event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-      htim->Break2Callback(htim);\r
-#else\r
-      HAL_TIMEx_Break2Callback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  /* TIM Trigger detection event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-      htim->TriggerCallback(htim);\r
-#else\r
-      HAL_TIM_TriggerCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  /* TIM commutation event */\r
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r
-  {\r
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)\r
-    {\r
-      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-      htim->CommutationCallback(htim);\r
-#else\r
-      HAL_TIMEx_CommutCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
-  *  @brief    TIM Peripheral Control functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                   ##### Peripheral Control functions #####\r
-  ==============================================================================\r
- [..]\r
-   This section provides functions allowing to:\r
-      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.\r
-      (+) Configure External Clock source.\r
-      (+) Configure Complementary channels, break features and dead time.\r
-      (+) Configure Master and the Slave synchronization.\r
-      (+) Configure the DMA Burst Mode.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initializes the TIM Output Compare Channels according to the specified\r
-  *         parameters in the TIM_OC_InitTypeDef.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  sConfig TIM Output Compare configuration structure\r
-  * @param  Channel TIM Channels to configure\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,\r
-                                           TIM_OC_InitTypeDef *sConfig,\r
-                                           uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CHANNELS(Channel));\r
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the TIM Channel 1 in Output Compare */\r
-      TIM_OC1_SetConfig(htim->Instance, sConfig);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the TIM Channel 2 in Output Compare */\r
-      TIM_OC2_SetConfig(htim->Instance, sConfig);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the TIM Channel 3 in Output Compare */\r
-      TIM_OC3_SetConfig(htim->Instance, sConfig);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the TIM Channel 4 in Output Compare */\r
-      TIM_OC4_SetConfig(htim->Instance, sConfig);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_5:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the TIM Channel 5 in Output Compare */\r
-      TIM_OC5_SetConfig(htim->Instance, sConfig);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_6:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the TIM Channel 6 in Output Compare */\r
-      TIM_OC6_SetConfig(htim->Instance, sConfig);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM Input Capture Channels according to the specified\r
-  *         parameters in the TIM_IC_InitTypeDef.\r
-  * @param  htim TIM IC handle\r
-  * @param  sConfig TIM Input Capture configuration structure\r
-  * @param  Channel TIM Channel to configure\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
-  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
-  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  if (Channel == TIM_CHANNEL_1)\r
-  {\r
-    /* TI1 Configuration */\r
-    TIM_TI1_SetConfig(htim->Instance,\r
-                      sConfig->ICPolarity,\r
-                      sConfig->ICSelection,\r
-                      sConfig->ICFilter);\r
-\r
-    /* Reset the IC1PSC Bits */\r
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
-\r
-    /* Set the IC1PSC value */\r
-    htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
-  }\r
-  else if (Channel == TIM_CHANNEL_2)\r
-  {\r
-    /* TI2 Configuration */\r
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-    TIM_TI2_SetConfig(htim->Instance,\r
-                      sConfig->ICPolarity,\r
-                      sConfig->ICSelection,\r
-                      sConfig->ICFilter);\r
-\r
-    /* Reset the IC2PSC Bits */\r
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
-\r
-    /* Set the IC2PSC value */\r
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);\r
-  }\r
-  else if (Channel == TIM_CHANNEL_3)\r
-  {\r
-    /* TI3 Configuration */\r
-    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
-\r
-    TIM_TI3_SetConfig(htim->Instance,\r
-                      sConfig->ICPolarity,\r
-                      sConfig->ICSelection,\r
-                      sConfig->ICFilter);\r
-\r
-    /* Reset the IC3PSC Bits */\r
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
-\r
-    /* Set the IC3PSC value */\r
-    htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
-  }\r
-  else\r
-  {\r
-    /* TI4 Configuration */\r
-    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
-\r
-    TIM_TI4_SetConfig(htim->Instance,\r
-                      sConfig->ICPolarity,\r
-                      sConfig->ICSelection,\r
-                      sConfig->ICFilter);\r
-\r
-    /* Reset the IC4PSC Bits */\r
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
-\r
-    /* Set the IC4PSC value */\r
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);\r
-  }\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM PWM  channels according to the specified\r
-  *         parameters in the TIM_OC_InitTypeDef.\r
-  * @param  htim TIM PWM handle\r
-  * @param  sConfig TIM PWM configuration structure\r
-  * @param  Channel TIM Channels to be configured\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,\r
-                                            TIM_OC_InitTypeDef *sConfig,\r
-                                            uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CHANNELS(Channel));\r
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the Channel 1 in PWM mode */\r
-      TIM_OC1_SetConfig(htim->Instance, sConfig);\r
-\r
-      /* Set the Preload enable bit for channel1 */\r
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
-\r
-      /* Configure the Output Fast mode */\r
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the Channel 2 in PWM mode */\r
-      TIM_OC2_SetConfig(htim->Instance, sConfig);\r
-\r
-      /* Set the Preload enable bit for channel2 */\r
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
-\r
-      /* Configure the Output Fast mode */\r
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the Channel 3 in PWM mode */\r
-      TIM_OC3_SetConfig(htim->Instance, sConfig);\r
-\r
-      /* Set the Preload enable bit for channel3 */\r
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
-\r
-      /* Configure the Output Fast mode */\r
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the Channel 4 in PWM mode */\r
-      TIM_OC4_SetConfig(htim->Instance, sConfig);\r
-\r
-      /* Set the Preload enable bit for channel4 */\r
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
-\r
-      /* Configure the Output Fast mode */\r
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_5:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the Channel 5 in PWM mode */\r
-      TIM_OC5_SetConfig(htim->Instance, sConfig);\r
-\r
-      /* Set the Preload enable bit for channel5*/\r
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;\r
-\r
-      /* Configure the Output Fast mode */\r
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;\r
-      htim->Instance->CCMR3 |= sConfig->OCFastMode;\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_6:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
-\r
-      /* Configure the Channel 6 in PWM mode */\r
-      TIM_OC6_SetConfig(htim->Instance, sConfig);\r
-\r
-      /* Set the Preload enable bit for channel6 */\r
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;\r
-\r
-      /* Configure the Output Fast mode */\r
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;\r
-      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM One Pulse Channels according to the specified\r
-  *         parameters in the TIM_OnePulse_InitTypeDef.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  sConfig TIM One Pulse configuration structure\r
-  * @param  OutputChannel TIM output channel to configure\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @param  InputChannel TIM input Channel to configure\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,\r
-                                                 uint32_t OutputChannel,  uint32_t InputChannel)\r
-{\r
-  TIM_OC_InitTypeDef temp1;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
-  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
-\r
-  if (OutputChannel != InputChannel)\r
-  {\r
-    /* Process Locked */\r
-    __HAL_LOCK(htim);\r
-\r
-    htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-    /* Extract the Output compare configuration from sConfig structure */\r
-    temp1.OCMode = sConfig->OCMode;\r
-    temp1.Pulse = sConfig->Pulse;\r
-    temp1.OCPolarity = sConfig->OCPolarity;\r
-    temp1.OCNPolarity = sConfig->OCNPolarity;\r
-    temp1.OCIdleState = sConfig->OCIdleState;\r
-    temp1.OCNIdleState = sConfig->OCNIdleState;\r
-\r
-    switch (OutputChannel)\r
-    {\r
-      case TIM_CHANNEL_1:\r
-      {\r
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
-        TIM_OC1_SetConfig(htim->Instance, &temp1);\r
-        break;\r
-      }\r
-      case TIM_CHANNEL_2:\r
-      {\r
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-        TIM_OC2_SetConfig(htim->Instance, &temp1);\r
-        break;\r
-      }\r
-      default:\r
-        break;\r
-    }\r
-\r
-    switch (InputChannel)\r
-    {\r
-      case TIM_CHANNEL_1:\r
-      {\r
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
-        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
-                          sConfig->ICSelection, sConfig->ICFilter);\r
-\r
-        /* Reset the IC1PSC Bits */\r
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
-\r
-        /* Select the Trigger source */\r
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
-        htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
-\r
-        /* Select the Slave Mode */\r
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
-        break;\r
-      }\r
-      case TIM_CHANNEL_2:\r
-      {\r
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
-                          sConfig->ICSelection, sConfig->ICFilter);\r
-\r
-        /* Reset the IC2PSC Bits */\r
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
-\r
-        /* Select the Trigger source */\r
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
-        htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
-\r
-        /* Select the Slave Mode */\r
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
-        break;\r
-      }\r
-\r
-      default:\r
-        break;\r
-    }\r
-\r
-    htim->State = HAL_TIM_STATE_READY;\r
-\r
-    __HAL_UNLOCK(htim);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral\r
-  * @param  htim TIM handle\r
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write\r
-  *         This parameter can be one of the following values:\r
-  *            @arg TIM_DMABASE_CR1\r
-  *            @arg TIM_DMABASE_CR2\r
-  *            @arg TIM_DMABASE_SMCR\r
-  *            @arg TIM_DMABASE_DIER\r
-  *            @arg TIM_DMABASE_SR\r
-  *            @arg TIM_DMABASE_EGR\r
-  *            @arg TIM_DMABASE_CCMR1\r
-  *            @arg TIM_DMABASE_CCMR2\r
-  *            @arg TIM_DMABASE_CCER\r
-  *            @arg TIM_DMABASE_CNT\r
-  *            @arg TIM_DMABASE_PSC\r
-  *            @arg TIM_DMABASE_ARR\r
-  *            @arg TIM_DMABASE_RCR\r
-  *            @arg TIM_DMABASE_CCR1\r
-  *            @arg TIM_DMABASE_CCR2\r
-  *            @arg TIM_DMABASE_CCR3\r
-  *            @arg TIM_DMABASE_CCR4\r
-  *            @arg TIM_DMABASE_BDTR\r
-  *            @arg TIM_DMABASE_OR1\r
-  *            @arg TIM_DMABASE_CCMR3 \r
-  *            @arg TIM_DMABASE_CCR5 \r
-  *            @arg TIM_DMABASE_CCR6 \r
-  *            @arg TIM_DMABASE_OR2  \r
-  *            @arg TIM_DMABASE_OR3  \r
-  * @param  BurstRequestSrc TIM DMA Request sources\r
-  *         This parameter can be one of the following values:\r
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
-  * @param  BurstBuffer The Buffer address.\r
-  * @param  BurstLength DMA Burst length. This parameter can be one value\r
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
-  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
-                                              uint32_t *BurstBuffer, uint32_t  BurstLength)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-  switch (BurstRequestSrc)\r
-  {\r
-    case TIM_DMA_UPDATE:\r
-    {\r
-      /* Set the DMA Period elapsed callbacks */\r
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC1:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,\r
-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC2:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,\r
-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC3:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,\r
-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC4:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,\r
-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_COM:\r
-    {\r
-      /* Set the DMA commutation callbacks */\r
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;\r
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,\r
-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_TRIGGER:\r
-    {\r
-      /* Set the DMA trigger callbacks */\r
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,\r
-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    default:\r
-      break;\r
-  }\r
-  /* configure the DMA Burst Mode */\r
-  htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
-\r
-  /* Enable the TIM DMA Request */\r
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM DMA Burst mode\r
-  * @param  htim TIM handle\r
-  * @param  BurstRequestSrc TIM DMA Request sources to disable\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
-\r
-  /* Abort the DMA transfer (at least disable the DMA channel) */\r
-  switch (BurstRequestSrc)\r
-  {\r
-    case TIM_DMA_UPDATE:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC1:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC2:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC3:\r
-    {\r
-      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC4:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
-      break;\r
-    }\r
-    case TIM_DMA_COM:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
-      break;\r
-    }\r
-    case TIM_DMA_TRIGGER:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
-      break;\r
-    }\r
-    default:\r
-      break;\r
-  }\r
-\r
-  if (HAL_OK == status)\r
-  {\r
-    /* Disable the TIM Update DMA request */\r
-    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
-  }\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\r
-  * @param  htim TIM handle\r
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read\r
-  *         This parameter can be one of the following values:\r
-  *            @arg TIM_DMABASE_CR1\r
-  *            @arg TIM_DMABASE_CR2\r
-  *            @arg TIM_DMABASE_SMCR\r
-  *            @arg TIM_DMABASE_DIER\r
-  *            @arg TIM_DMABASE_SR\r
-  *            @arg TIM_DMABASE_EGR\r
-  *            @arg TIM_DMABASE_CCMR1\r
-  *            @arg TIM_DMABASE_CCMR2\r
-  *            @arg TIM_DMABASE_CCER\r
-  *            @arg TIM_DMABASE_CNT\r
-  *            @arg TIM_DMABASE_PSC\r
-  *            @arg TIM_DMABASE_ARR\r
-  *            @arg TIM_DMABASE_RCR\r
-  *            @arg TIM_DMABASE_CCR1\r
-  *            @arg TIM_DMABASE_CCR2\r
-  *            @arg TIM_DMABASE_CCR3\r
-  *            @arg TIM_DMABASE_CCR4\r
-  *            @arg TIM_DMABASE_BDTR\r
-  *            @arg TIM_DMABASE_OR1\r
-  *            @arg TIM_DMABASE_CCMR3 \r
-  *            @arg TIM_DMABASE_CCR5 \r
-  *            @arg TIM_DMABASE_CCR6 \r
-  *            @arg TIM_DMABASE_OR2  \r
-  *            @arg TIM_DMABASE_OR3  \r
-  * @param  BurstRequestSrc TIM DMA Request sources\r
-  *         This parameter can be one of the following values:\r
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
-  * @param  BurstBuffer The Buffer address.\r
-  * @param  BurstLength DMA Burst length. This parameter can be one value\r
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
-  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
-                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-  switch (BurstRequestSrc)\r
-  {\r
-    case TIM_DMA_UPDATE:\r
-    {\r
-      /* Set the DMA Period elapsed callbacks */\r
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC1:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC2:\r
-    {\r
-      /* Set the DMA capture/compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC3:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_CC4:\r
-    {\r
-      /* Set the DMA capture callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_COM:\r
-    {\r
-      /* Set the DMA commutation callbacks */\r
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;\r
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    case TIM_DMA_TRIGGER:\r
-    {\r
-      /* Set the DMA trigger callbacks */\r
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      break;\r
-    }\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* configure the DMA Burst Mode */\r
-  htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
-\r
-  /* Enable the TIM DMA Request */\r
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stop the DMA burst reading\r
-  * @param  htim TIM handle\r
-  * @param  BurstRequestSrc TIM DMA Request sources to disable.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
-\r
-  /* Abort the DMA transfer (at least disable the DMA channel) */\r
-  switch (BurstRequestSrc)\r
-  {\r
-    case TIM_DMA_UPDATE:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC1:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC2:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC3:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
-      break;\r
-    }\r
-    case TIM_DMA_CC4:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
-      break;\r
-    }\r
-    case TIM_DMA_COM:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
-      break;\r
-    }\r
-    case TIM_DMA_TRIGGER:\r
-    {\r
-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
-      break;\r
-    }\r
-    default:\r
-      break;\r
-  }\r
-\r
-  if (HAL_OK == status)\r
-  {\r
-    /* Disable the TIM Update DMA request */\r
-    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
-  }\r
-\r
-  /* Return function status */\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Generate a software event\r
-  * @param  htim TIM handle\r
-  * @param  EventSource specifies the event source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
-  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
-  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
-  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
-  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
-  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source\r
-  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
-  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r
-  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source\r
-  * @note   Basic timers can only generate an update event.\r
-  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.\r
-  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant\r
-  *         only for timer instances supporting break input(s).\r
-  * @retval HAL status\r
-  */\r
-\r
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  /* Change the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Set the event sources */\r
-  htim->Instance->EGR = EventSource;\r
-\r
-  /* Change the TIM state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configures the OCRef clear feature\r
-  * @param  htim TIM handle\r
-  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that\r
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.\r
-  * @param  Channel specifies the TIM Channel\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r
-                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
-                                           uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  switch (sClearInputConfig->ClearInputSource)\r
-  {\r
-    case TIM_CLEARINPUTSOURCE_NONE:\r
-    {\r
-      /* Clear the OCREF clear selection bit and the the ETR Bits */\r
-      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));\r
-      break;\r
-    }\r
-    case TIM_CLEARINPUTSOURCE_OCREFCLR:\r
-    {\r
-      /* Clear the OCREF clear selection bit */\r
-      CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);\r
-    }\r
-    break;\r
-\r
-    case TIM_CLEARINPUTSOURCE_ETR:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
-      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
-      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
-\r
-      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
-      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)\r
-      {\r
-        htim->State = HAL_TIM_STATE_READY;\r
-        __HAL_UNLOCK(htim);\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      TIM_ETR_SetConfig(htim->Instance,\r
-                        sClearInputConfig->ClearInputPrescaler,\r
-                        sClearInputConfig->ClearInputPolarity,\r
-                        sClearInputConfig->ClearInputFilter);\r
-\r
-      /* Set the OCREF clear selection bit */\r
-      SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
-      {\r
-        /* Enable the OCREF clear feature for Channel 1 */\r
-        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
-      }\r
-      else\r
-      {\r
-        /* Disable the OCREF clear feature for Channel 1 */\r
-        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
-      }\r
-      break;\r
-    }\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
-      {\r
-        /* Enable the OCREF clear feature for Channel 2 */\r
-        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
-      }\r
-      else\r
-      {\r
-        /* Disable the OCREF clear feature for Channel 2 */\r
-        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
-      }\r
-      break;\r
-    }\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
-      {\r
-        /* Enable the OCREF clear feature for Channel 3 */\r
-        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
-      }\r
-      else\r
-      {\r
-        /* Disable the OCREF clear feature for Channel 3 */\r
-        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
-      }\r
-      break;\r
-    }\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
-      {\r
-        /* Enable the OCREF clear feature for Channel 4 */\r
-        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
-      }\r
-      else\r
-      {\r
-        /* Disable the OCREF clear feature for Channel 4 */\r
-        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
-      }\r
-      break;\r
-    }\r
-    case TIM_CHANNEL_5:\r
-    {\r
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
-      {\r
-        /* Enable the OCREF clear feature for Channel 5 */\r
-        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
-      }\r
-      else\r
-      {\r
-        /* Disable the OCREF clear feature for Channel 5 */\r
-        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
-      }\r
-      break;\r
-    }\r
-    case TIM_CHANNEL_6:\r
-    {\r
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
-      {\r
-        /* Enable the OCREF clear feature for Channel 6 */\r
-        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
-      }\r
-      else\r
-      {\r
-        /* Disable the OCREF clear feature for Channel 6 */\r
-        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
-      }\r
-      break;\r
-    }\r
-    default:\r
-      break;\r
-  }\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief   Configures the clock source to be used\r
-  * @param  htim TIM handle\r
-  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that\r
-  *         contains the clock source information for the TIM peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
-\r
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
-  tmpsmcr = htim->Instance->SMCR;\r
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
-  htim->Instance->SMCR = tmpsmcr;\r
-\r
-  switch (sClockSourceConfig->ClockSource)\r
-  {\r
-    case TIM_CLOCKSOURCE_INTERNAL:\r
-    {\r
-      assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-      break;\r
-    }\r
-\r
-    case TIM_CLOCKSOURCE_ETRMODE1:\r
-    {\r
-      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/\r
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
-\r
-      /* Check ETR input conditioning related parameters */\r
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
-\r
-      /* Configure the ETR Clock source */\r
-      TIM_ETR_SetConfig(htim->Instance,\r
-                        sClockSourceConfig->ClockPrescaler,\r
-                        sClockSourceConfig->ClockPolarity,\r
-                        sClockSourceConfig->ClockFilter);\r
-\r
-      /* Select the External clock mode1 and the ETRF trigger */\r
-      tmpsmcr = htim->Instance->SMCR;\r
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
-      /* Write to TIMx SMCR */\r
-      htim->Instance->SMCR = tmpsmcr;\r
-      break;\r
-    }\r
-\r
-    case TIM_CLOCKSOURCE_ETRMODE2:\r
-    {\r
-      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/\r
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));\r
-\r
-      /* Check ETR input conditioning related parameters */\r
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
-\r
-      /* Configure the ETR Clock source */\r
-      TIM_ETR_SetConfig(htim->Instance,\r
-                        sClockSourceConfig->ClockPrescaler,\r
-                        sClockSourceConfig->ClockPolarity,\r
-                        sClockSourceConfig->ClockFilter);\r
-      /* Enable the External clock mode2 */\r
-      htim->Instance->SMCR |= TIM_SMCR_ECE;\r
-      break;\r
-    }\r
-\r
-    case TIM_CLOCKSOURCE_TI1:\r
-    {\r
-      /* Check whether or not the timer instance supports external clock mode 1 */\r
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
-\r
-      /* Check TI1 input conditioning related parameters */\r
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
-\r
-      TIM_TI1_ConfigInputStage(htim->Instance,\r
-                               sClockSourceConfig->ClockPolarity,\r
-                               sClockSourceConfig->ClockFilter);\r
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CLOCKSOURCE_TI2:\r
-    {\r
-      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/\r
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
-\r
-      /* Check TI2 input conditioning related parameters */\r
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
-\r
-      TIM_TI2_ConfigInputStage(htim->Instance,\r
-                               sClockSourceConfig->ClockPolarity,\r
-                               sClockSourceConfig->ClockFilter);\r
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CLOCKSOURCE_TI1ED:\r
-    {\r
-      /* Check whether or not the timer instance supports external clock mode 1 */\r
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
-\r
-      /* Check TI1 input conditioning related parameters */\r
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
-\r
-      TIM_TI1_ConfigInputStage(htim->Instance,\r
-                               sClockSourceConfig->ClockPolarity,\r
-                               sClockSourceConfig->ClockFilter);\r
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
-      break;\r
-    }\r
-\r
-    case TIM_CLOCKSOURCE_ITR0:\r
-    case TIM_CLOCKSOURCE_ITR1:\r
-    case TIM_CLOCKSOURCE_ITR2:\r
-    case TIM_CLOCKSOURCE_ITR3:\r
-    {\r
-      /* Check whether or not the timer instance supports internal trigger input */\r
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
-\r
-      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input\r
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input\r
-  * @param  htim TIM handle.\r
-  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the\r
-  *         output of a XOR gate.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
-  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
-  *            pins are connected to the TI1 input (XOR combination)\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
-{\r
-  uint32_t tmpcr2;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
-\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 = htim->Instance->CR2;\r
-\r
-  /* Reset the TI1 selection */\r
-  tmpcr2 &= ~TIM_CR2_TI1S;\r
-\r
-  /* Set the TI1 selection */\r
-  tmpcr2 |= TI1_Selection;\r
-\r
-  /* Write to TIMxCR2 */\r
-  htim->Instance->CR2 = tmpcr2;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configures the TIM in Slave mode\r
-  * @param  htim TIM handle.\r
-  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
-  *         contains the selected trigger (internal trigger input, filtered\r
-  *         timer input or external trigger input) and the Slave mode\r
-  *         (Disable, Reset, Gated, Trigger, External clock mode 1).\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
-\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
-  {\r
-    htim->State = HAL_TIM_STATE_READY;\r
-    __HAL_UNLOCK(htim);\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Disable Trigger Interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);\r
-\r
-  /* Disable Trigger DMA request */\r
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configures the TIM in Slave mode in interrupt mode\r
-  * @param  htim TIM handle.\r
-  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
-  *         contains the selected trigger (internal trigger input, filtered\r
-  *         timer input or external trigger input) and the Slave mode\r
-  *         (Disable, Reset, Gated, Trigger, External clock mode 1).\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,\r
-                                                TIM_SlaveConfigTypeDef *sSlaveConfig)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
-\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
-  {\r
-    htim->State = HAL_TIM_STATE_READY;\r
-    __HAL_UNLOCK(htim);\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Enable Trigger Interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
-\r
-  /* Disable Trigger DMA request */\r
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Read the captured value from Capture Compare unit\r
-  * @param  htim TIM handle.\r
-  * @param  Channel TIM Channels to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
-  * @retval Captured value\r
-  */\r
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpreg = 0U;\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
-      /* Return the capture 1 value */\r
-      tmpreg =  htim->Instance->CCR1;\r
-\r
-      break;\r
-    }\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
-      /* Return the capture 2 value */\r
-      tmpreg =   htim->Instance->CCR2;\r
-\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
-\r
-      /* Return the capture 3 value */\r
-      tmpreg =   htim->Instance->CCR3;\r
-\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_4:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
-\r
-      /* Return the capture 4 value */\r
-      tmpreg =   htim->Instance->CCR4;\r
-\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  return tmpreg;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
-  *  @brief    TIM Callbacks functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                        ##### TIM Callbacks functions #####\r
-  ==============================================================================\r
- [..]\r
-   This section provides TIM callback functions:\r
-   (+) TIM Period elapsed callback\r
-   (+) TIM Output Compare callback\r
-   (+) TIM Input capture callback\r
-   (+) TIM Trigger callback\r
-   (+) TIM Error callback\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Period elapsed callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Period elapsed half complete callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Output Compare callback in non-blocking mode\r
-  * @param  htim TIM OC handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Input Capture callback in non-blocking mode\r
-  * @param  htim TIM IC handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Input Capture half complete callback in non-blocking mode\r
-  * @param  htim TIM IC handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  PWM Pulse finished callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  PWM Pulse finished half complete callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Hall Trigger detection callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_TriggerCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Hall Trigger detection half complete callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Timer error callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIM_ErrorCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  Register a User TIM callback to be used instead of the weak predefined callback\r
-  * @param htim tim handle\r
-  * @param CallbackID ID of the callback to be registered\r
-  *        This parameter can be one of the following values:\r
-  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
-  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
-  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
-  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
-  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
-  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
-  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
-  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
-  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
-  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
-  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
-  *          @param pCallback pointer to the callback function\r
-  *          @retval status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\r
-                                           pTIM_CallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-  /* Process locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  if (htim->State == HAL_TIM_STATE_READY)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
-        htim->Base_MspInitCallback                 = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
-        htim->Base_MspDeInitCallback               = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPINIT_CB_ID :\r
-        htim->IC_MspInitCallback                   = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
-        htim->IC_MspDeInitCallback                 = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPINIT_CB_ID :\r
-        htim->OC_MspInitCallback                   = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
-        htim->OC_MspDeInitCallback                 = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
-        htim->PWM_MspInitCallback                  = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
-        htim->PWM_MspDeInitCallback                = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
-        htim->OnePulse_MspInitCallback             = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
-        htim->OnePulse_MspDeInitCallback           = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
-        htim->Encoder_MspInitCallback              = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
-        htim->Encoder_MspDeInitCallback            = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
-        htim->HallSensor_MspInitCallback           = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
-        htim->HallSensor_MspDeInitCallback         = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
-        htim->PeriodElapsedCallback                = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
-        htim->PeriodElapsedHalfCpltCallback        = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_TRIGGER_CB_ID :\r
-        htim->TriggerCallback                      = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_TRIGGER_HALF_CB_ID :\r
-        htim->TriggerHalfCpltCallback              = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_IC_CAPTURE_CB_ID :\r
-        htim->IC_CaptureCallback                   = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
-        htim->IC_CaptureHalfCpltCallback           = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
-        htim->OC_DelayElapsedCallback              = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
-        htim->PWM_PulseFinishedCallback            = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
-        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ERROR_CB_ID :\r
-        htim->ErrorCallback                        = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_COMMUTATION_CB_ID :\r
-        htim->CommutationCallback                  = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
-        htim->CommutationHalfCpltCallback          = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_BREAK_CB_ID :\r
-        htim->BreakCallback                        = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_BREAK2_CB_ID :\r
-        htim->Break2Callback                       = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
-        htim->Base_MspInitCallback         = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
-        htim->Base_MspDeInitCallback       = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPINIT_CB_ID :\r
-        htim->IC_MspInitCallback           = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
-        htim->IC_MspDeInitCallback         = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPINIT_CB_ID :\r
-        htim->OC_MspInitCallback           = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
-        htim->OC_MspDeInitCallback         = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
-        htim->PWM_MspInitCallback          = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
-        htim->PWM_MspDeInitCallback        = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
-        htim->OnePulse_MspInitCallback     = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
-        htim->OnePulse_MspDeInitCallback   = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
-        htim->Encoder_MspInitCallback      = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
-        htim->Encoder_MspDeInitCallback    = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
-        htim->HallSensor_MspInitCallback   = pCallback;\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
-        htim->HallSensor_MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister a TIM callback\r
-  *         TIM callback is redirected to the weak predefined callback\r
-  * @param htim tim handle\r
-  * @param CallbackID ID of the callback to be unregistered\r
-  *        This parameter can be one of the following values:\r
-  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
-  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
-  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
-  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
-  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
-  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
-  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
-  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
-  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
-  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
-  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
-  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
-  *          @retval status\r
-  */\r
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  /* Process locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  if (htim->State == HAL_TIM_STATE_READY)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
-        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
-        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPINIT_CB_ID :\r
-        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
-        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPINIT_CB_ID :\r
-        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
-        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
-        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
-        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
-        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
-        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
-        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
-        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
-        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
-        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
-        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
-        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */\r
-        break;\r
-\r
-      case HAL_TIM_TRIGGER_CB_ID :\r
-        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */\r
-        break;\r
-\r
-      case HAL_TIM_TRIGGER_HALF_CB_ID :\r
-        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */\r
-        break;\r
-\r
-      case HAL_TIM_IC_CAPTURE_CB_ID :\r
-        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */\r
-        break;\r
-\r
-      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
-        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */\r
-        break;\r
-\r
-      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
-        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
-        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
-        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ERROR_CB_ID :\r
-        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */\r
-        break;\r
-\r
-      case HAL_TIM_COMMUTATION_CB_ID :\r
-        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */\r
-        break;\r
-\r
-      case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
-        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */\r
-        break;\r
-\r
-      case HAL_TIM_BREAK_CB_ID :\r
-        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */\r
-        break;\r
-\r
-      case HAL_TIM_BREAK2_CB_ID :\r
-        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */\r
-        break;\r
-\r
-      default :\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_TIM_BASE_MSPINIT_CB_ID :\r
-        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
-        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPINIT_CB_ID :\r
-        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
-        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPINIT_CB_ID :\r
-        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
-        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPINIT_CB_ID :\r
-        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
-        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
-        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
-        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
-        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
-        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
-        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */\r
-        break;\r
-\r
-      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
-        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */\r
-        break;\r
-\r
-      default :\r
-        /* Return error status */\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Return error status */\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return status;\r
-}\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
-  *  @brief   TIM Peripheral State functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                        ##### Peripheral State functions #####\r
-  ==============================================================================\r
-    [..]\r
-    This subsection permits to get in run-time the status of the peripheral\r
-    and the data flow.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Return the TIM Base handle state.\r
-  * @param  htim TIM Base handle\r
-  * @retval HAL state\r
-  */\r
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
-{\r
-  return htim->State;\r
-}\r
-\r
-/**\r
-  * @brief  Return the TIM OC handle state.\r
-  * @param  htim TIM Output Compare handle\r
-  * @retval HAL state\r
-  */\r
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
-{\r
-  return htim->State;\r
-}\r
-\r
-/**\r
-  * @brief  Return the TIM PWM handle state.\r
-  * @param  htim TIM handle\r
-  * @retval HAL state\r
-  */\r
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
-{\r
-  return htim->State;\r
-}\r
-\r
-/**\r
-  * @brief  Return the TIM Input Capture handle state.\r
-  * @param  htim TIM IC handle\r
-  * @retval HAL state\r
-  */\r
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
-{\r
-  return htim->State;\r
-}\r
-\r
-/**\r
-  * @brief  Return the TIM One Pulse Mode handle state.\r
-  * @param  htim TIM OPM handle\r
-  * @retval HAL state\r
-  */\r
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
-{\r
-  return htim->State;\r
-}\r
-\r
-/**\r
-  * @brief  Return the TIM Encoder Mode handle state.\r
-  * @param  htim TIM Encoder Interface handle\r
-  * @retval HAL state\r
-  */\r
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
-{\r
-  return htim->State;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIM_Private_Functions TIM Private Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  TIM DMA error callback\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-void TIM_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->ErrorCallback(htim);\r
-#else\r
-  HAL_TIM_ErrorCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Delay Pulse complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->PWM_PulseFinishedCallback(htim);\r
-#else\r
-  HAL_TIM_PWM_PulseFinishedCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Delay Pulse half complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->PWM_PulseFinishedHalfCpltCallback(htim);\r
-#else\r
-  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Capture complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->IC_CaptureCallback(htim);\r
-#else\r
-  HAL_TIM_IC_CaptureCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Capture half complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
-  }\r
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
-  {\r
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->IC_CaptureHalfCpltCallback(htim);\r
-#else\r
-  HAL_TIM_IC_CaptureHalfCpltCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Period Elapse complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->PeriodElapsedCallback(htim);\r
-#else\r
-  HAL_TIM_PeriodElapsedCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Period Elapse half complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->PeriodElapsedHalfCpltCallback(htim);\r
-#else\r
-  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Trigger callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->TriggerCallback(htim);\r
-#else\r
-  HAL_TIM_TriggerCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Trigger half complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->TriggerHalfCpltCallback(htim);\r
-#else\r
-  HAL_TIM_TriggerHalfCpltCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  Time Base configuration\r
-  * @param  TIMx TIM peripheral\r
-  * @param  Structure TIM Base configuration structure\r
-  * @retval None\r
-  */\r
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
-{\r
-  uint32_t tmpcr1;\r
-  tmpcr1 = TIMx->CR1;\r
-\r
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))\r
-  {\r
-    /* Select the Counter Mode */\r
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
-    tmpcr1 |= Structure->CounterMode;\r
-  }\r
-\r
-  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))\r
-  {\r
-    /* Set the clock division */\r
-    tmpcr1 &= ~TIM_CR1_CKD;\r
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
-  }\r
-\r
-  /* Set the auto-reload preload */\r
-  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);\r
-\r
-  TIMx->CR1 = tmpcr1;\r
-\r
-  /* Set the Autoreload value */\r
-  TIMx->ARR = (uint32_t)Structure->Period ;\r
-\r
-  /* Set the Prescaler value */\r
-  TIMx->PSC = Structure->Prescaler;\r
-\r
-  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))\r
-  {\r
-    /* Set the Repetition Counter value */\r
-    TIMx->RCR = Structure->RepetitionCounter;\r
-  }\r
-\r
-  /* Generate an update event to reload the Prescaler\r
-     and the repetition counter (only for advanced timer) value immediately */\r
-  TIMx->EGR = TIM_EGR_UG;\r
-}\r
-\r
-/**\r
-  * @brief  Timer Output Compare 1 configuration\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  OC_Config The ouput configuration structure\r
-  * @retval None\r
-  */\r
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
-  uint32_t tmpccmrx;\r
-  uint32_t tmpccer;\r
-  uint32_t tmpcr2;\r
-\r
-  /* Disable the Channel 1: Reset the CC1E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC1E;\r
-\r
-  /* Get the TIMx CCER register value */\r
-  tmpccer = TIMx->CCER;\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 =  TIMx->CR2;\r
-\r
-  /* Get the TIMx CCMR1 register value */\r
-  tmpccmrx = TIMx->CCMR1;\r
-\r
-  /* Reset the Output Compare Mode Bits */\r
-  tmpccmrx &= ~TIM_CCMR1_OC1M;\r
-  tmpccmrx &= ~TIM_CCMR1_CC1S;\r
-  /* Select the Output Compare Mode */\r
-  tmpccmrx |= OC_Config->OCMode;\r
-\r
-  /* Reset the Output Polarity level */\r
-  tmpccer &= ~TIM_CCER_CC1P;\r
-  /* Set the Output Compare Polarity */\r
-  tmpccer |= OC_Config->OCPolarity;\r
-\r
-  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))\r
-  {\r
-    /* Check parameters */\r
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
-\r
-    /* Reset the Output N Polarity level */\r
-    tmpccer &= ~TIM_CCER_CC1NP;\r
-    /* Set the Output N Polarity */\r
-    tmpccer |= OC_Config->OCNPolarity;\r
-    /* Reset the Output N State */\r
-    tmpccer &= ~TIM_CCER_CC1NE;\r
-  }\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
-  {\r
-    /* Check parameters */\r
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
-    /* Reset the Output Compare and Output Compare N IDLE State */\r
-    tmpcr2 &= ~TIM_CR2_OIS1;\r
-    tmpcr2 &= ~TIM_CR2_OIS1N;\r
-    /* Set the Output Idle state */\r
-    tmpcr2 |= OC_Config->OCIdleState;\r
-    /* Set the Output N Idle state */\r
-    tmpcr2 |= OC_Config->OCNIdleState;\r
-  }\r
-\r
-  /* Write to TIMx CR2 */\r
-  TIMx->CR2 = tmpcr2;\r
-\r
-  /* Write to TIMx CCMR1 */\r
-  TIMx->CCMR1 = tmpccmrx;\r
-\r
-  /* Set the Capture Compare Register value */\r
-  TIMx->CCR1 = OC_Config->Pulse;\r
-\r
-  /* Write to TIMx CCER */\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Timer Output Compare 2 configuration\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  OC_Config The ouput configuration structure\r
-  * @retval None\r
-  */\r
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
-  uint32_t tmpccmrx;\r
-  uint32_t tmpccer;\r
-  uint32_t tmpcr2;\r
-\r
-  /* Disable the Channel 2: Reset the CC2E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC2E;\r
-\r
-  /* Get the TIMx CCER register value */\r
-  tmpccer = TIMx->CCER;\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 =  TIMx->CR2;\r
-\r
-  /* Get the TIMx CCMR1 register value */\r
-  tmpccmrx = TIMx->CCMR1;\r
-\r
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
-  tmpccmrx &= ~TIM_CCMR1_OC2M;\r
-  tmpccmrx &= ~TIM_CCMR1_CC2S;\r
-\r
-  /* Select the Output Compare Mode */\r
-  tmpccmrx |= (OC_Config->OCMode << 8U);\r
-\r
-  /* Reset the Output Polarity level */\r
-  tmpccer &= ~TIM_CCER_CC2P;\r
-  /* Set the Output Compare Polarity */\r
-  tmpccer |= (OC_Config->OCPolarity << 4U);\r
-\r
-  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))\r
-  {\r
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
-\r
-    /* Reset the Output N Polarity level */\r
-    tmpccer &= ~TIM_CCER_CC2NP;\r
-    /* Set the Output N Polarity */\r
-    tmpccer |= (OC_Config->OCNPolarity << 4U);\r
-    /* Reset the Output N State */\r
-    tmpccer &= ~TIM_CCER_CC2NE;\r
-\r
-  }\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
-  {\r
-    /* Check parameters */\r
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
-    /* Reset the Output Compare and Output Compare N IDLE State */\r
-    tmpcr2 &= ~TIM_CR2_OIS2;\r
-    tmpcr2 &= ~TIM_CR2_OIS2N;\r
-    /* Set the Output Idle state */\r
-    tmpcr2 |= (OC_Config->OCIdleState << 2U);\r
-    /* Set the Output N Idle state */\r
-    tmpcr2 |= (OC_Config->OCNIdleState << 2U);\r
-  }\r
-\r
-  /* Write to TIMx CR2 */\r
-  TIMx->CR2 = tmpcr2;\r
-\r
-  /* Write to TIMx CCMR1 */\r
-  TIMx->CCMR1 = tmpccmrx;\r
-\r
-  /* Set the Capture Compare Register value */\r
-  TIMx->CCR2 = OC_Config->Pulse;\r
-\r
-  /* Write to TIMx CCER */\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Timer Output Compare 3 configuration\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  OC_Config The ouput configuration structure\r
-  * @retval None\r
-  */\r
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
-  uint32_t tmpccmrx;\r
-  uint32_t tmpccer;\r
-  uint32_t tmpcr2;\r
-\r
-  /* Disable the Channel 3: Reset the CC2E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC3E;\r
-\r
-  /* Get the TIMx CCER register value */\r
-  tmpccer = TIMx->CCER;\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 =  TIMx->CR2;\r
-\r
-  /* Get the TIMx CCMR2 register value */\r
-  tmpccmrx = TIMx->CCMR2;\r
-\r
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
-  tmpccmrx &= ~TIM_CCMR2_OC3M;\r
-  tmpccmrx &= ~TIM_CCMR2_CC3S;\r
-  /* Select the Output Compare Mode */\r
-  tmpccmrx |= OC_Config->OCMode;\r
-\r
-  /* Reset the Output Polarity level */\r
-  tmpccer &= ~TIM_CCER_CC3P;\r
-  /* Set the Output Compare Polarity */\r
-  tmpccer |= (OC_Config->OCPolarity << 8U);\r
-\r
-  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))\r
-  {\r
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
-\r
-    /* Reset the Output N Polarity level */\r
-    tmpccer &= ~TIM_CCER_CC3NP;\r
-    /* Set the Output N Polarity */\r
-    tmpccer |= (OC_Config->OCNPolarity << 8U);\r
-    /* Reset the Output N State */\r
-    tmpccer &= ~TIM_CCER_CC3NE;\r
-  }\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
-  {\r
-    /* Check parameters */\r
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
-    /* Reset the Output Compare and Output Compare N IDLE State */\r
-    tmpcr2 &= ~TIM_CR2_OIS3;\r
-    tmpcr2 &= ~TIM_CR2_OIS3N;\r
-    /* Set the Output Idle state */\r
-    tmpcr2 |= (OC_Config->OCIdleState << 4U);\r
-    /* Set the Output N Idle state */\r
-    tmpcr2 |= (OC_Config->OCNIdleState << 4U);\r
-  }\r
-\r
-  /* Write to TIMx CR2 */\r
-  TIMx->CR2 = tmpcr2;\r
-\r
-  /* Write to TIMx CCMR2 */\r
-  TIMx->CCMR2 = tmpccmrx;\r
-\r
-  /* Set the Capture Compare Register value */\r
-  TIMx->CCR3 = OC_Config->Pulse;\r
-\r
-  /* Write to TIMx CCER */\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Timer Output Compare 4 configuration\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  OC_Config The ouput configuration structure\r
-  * @retval None\r
-  */\r
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
-  uint32_t tmpccmrx;\r
-  uint32_t tmpccer;\r
-  uint32_t tmpcr2;\r
-\r
-  /* Disable the Channel 4: Reset the CC4E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC4E;\r
-\r
-  /* Get the TIMx CCER register value */\r
-  tmpccer = TIMx->CCER;\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 =  TIMx->CR2;\r
-\r
-  /* Get the TIMx CCMR2 register value */\r
-  tmpccmrx = TIMx->CCMR2;\r
-\r
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
-  tmpccmrx &= ~TIM_CCMR2_OC4M;\r
-  tmpccmrx &= ~TIM_CCMR2_CC4S;\r
-\r
-  /* Select the Output Compare Mode */\r
-  tmpccmrx |= (OC_Config->OCMode << 8U);\r
-\r
-  /* Reset the Output Polarity level */\r
-  tmpccer &= ~TIM_CCER_CC4P;\r
-  /* Set the Output Compare Polarity */\r
-  tmpccer |= (OC_Config->OCPolarity << 12U);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
-  {\r
-    /* Check parameters */\r
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
-    /* Reset the Output Compare IDLE State */\r
-    tmpcr2 &= ~TIM_CR2_OIS4;\r
-\r
-    /* Set the Output Idle state */\r
-    tmpcr2 |= (OC_Config->OCIdleState << 6U);\r
-  }\r
-\r
-  /* Write to TIMx CR2 */\r
-  TIMx->CR2 = tmpcr2;\r
-\r
-  /* Write to TIMx CCMR2 */\r
-  TIMx->CCMR2 = tmpccmrx;\r
-\r
-  /* Set the Capture Compare Register value */\r
-  TIMx->CCR4 = OC_Config->Pulse;\r
-\r
-  /* Write to TIMx CCER */\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Timer Output Compare 5 configuration\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  OC_Config The ouput configuration structure\r
-  * @retval None\r
-  */\r
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,\r
-                              TIM_OC_InitTypeDef *OC_Config)\r
-{\r
-  uint32_t tmpccmrx;\r
-  uint32_t tmpccer;\r
-  uint32_t tmpcr2;\r
-\r
-  /* Disable the output: Reset the CCxE Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC5E;\r
-\r
-  /* Get the TIMx CCER register value */\r
-  tmpccer = TIMx->CCER;\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 =  TIMx->CR2;\r
-  /* Get the TIMx CCMR1 register value */\r
-  tmpccmrx = TIMx->CCMR3;\r
-\r
-  /* Reset the Output Compare Mode Bits */\r
-  tmpccmrx &= ~(TIM_CCMR3_OC5M);\r
-  /* Select the Output Compare Mode */\r
-  tmpccmrx |= OC_Config->OCMode;\r
-\r
-  /* Reset the Output Polarity level */\r
-  tmpccer &= ~TIM_CCER_CC5P;\r
-  /* Set the Output Compare Polarity */\r
-  tmpccer |= (OC_Config->OCPolarity << 16U);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
-  {\r
-    /* Reset the Output Compare IDLE State */\r
-    tmpcr2 &= ~TIM_CR2_OIS5;\r
-    /* Set the Output Idle state */\r
-    tmpcr2 |= (OC_Config->OCIdleState << 8U);\r
-  }\r
-  /* Write to TIMx CR2 */\r
-  TIMx->CR2 = tmpcr2;\r
-\r
-  /* Write to TIMx CCMR3 */\r
-  TIMx->CCMR3 = tmpccmrx;\r
-\r
-  /* Set the Capture Compare Register value */\r
-  TIMx->CCR5 = OC_Config->Pulse;\r
-\r
-  /* Write to TIMx CCER */\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Timer Output Compare 6 configuration\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  OC_Config The ouput configuration structure\r
-  * @retval None\r
-  */\r
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,\r
-                              TIM_OC_InitTypeDef *OC_Config)\r
-{\r
-  uint32_t tmpccmrx;\r
-  uint32_t tmpccer;\r
-  uint32_t tmpcr2;\r
-\r
-  /* Disable the output: Reset the CCxE Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC6E;\r
-\r
-  /* Get the TIMx CCER register value */\r
-  tmpccer = TIMx->CCER;\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 =  TIMx->CR2;\r
-  /* Get the TIMx CCMR1 register value */\r
-  tmpccmrx = TIMx->CCMR3;\r
-\r
-  /* Reset the Output Compare Mode Bits */\r
-  tmpccmrx &= ~(TIM_CCMR3_OC6M);\r
-  /* Select the Output Compare Mode */\r
-  tmpccmrx |= (OC_Config->OCMode << 8U);\r
-\r
-  /* Reset the Output Polarity level */\r
-  tmpccer &= (uint32_t)~TIM_CCER_CC6P;\r
-  /* Set the Output Compare Polarity */\r
-  tmpccer |= (OC_Config->OCPolarity << 20U);\r
-\r
-  if (IS_TIM_BREAK_INSTANCE(TIMx))\r
-  {\r
-    /* Reset the Output Compare IDLE State */\r
-    tmpcr2 &= ~TIM_CR2_OIS6;\r
-    /* Set the Output Idle state */\r
-    tmpcr2 |= (OC_Config->OCIdleState << 10U);\r
-  }\r
-\r
-  /* Write to TIMx CR2 */\r
-  TIMx->CR2 = tmpcr2;\r
-\r
-  /* Write to TIMx CCMR3 */\r
-  TIMx->CCMR3 = tmpccmrx;\r
-\r
-  /* Set the Capture Compare Register value */\r
-  TIMx->CCR6 = OC_Config->Pulse;\r
-\r
-  /* Write to TIMx CCER */\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Slave Timer configuration function\r
-  * @param  htim TIM handle\r
-  * @param  sSlaveConfig Slave timer configuration\r
-  * @retval None\r
-  */\r
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)\r
-{\r
-  uint32_t tmpsmcr;\r
-  uint32_t tmpccmr1;\r
-  uint32_t tmpccer;\r
-\r
-  /* Get the TIMx SMCR register value */\r
-  tmpsmcr = htim->Instance->SMCR;\r
-\r
-  /* Reset the Trigger Selection Bits */\r
-  tmpsmcr &= ~TIM_SMCR_TS;\r
-  /* Set the Input Trigger source */\r
-  tmpsmcr |= sSlaveConfig->InputTrigger;\r
-\r
-  /* Reset the slave mode Bits */\r
-  tmpsmcr &= ~TIM_SMCR_SMS;\r
-  /* Set the slave mode */\r
-  tmpsmcr |= sSlaveConfig->SlaveMode;\r
-\r
-  /* Write to TIMx SMCR */\r
-  htim->Instance->SMCR = tmpsmcr;\r
-\r
-  /* Configure the trigger prescaler, filter, and polarity */\r
-  switch (sSlaveConfig->InputTrigger)\r
-  {\r
-    case TIM_TS_ETRF:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
-      /* Configure the ETR Trigger source */\r
-      TIM_ETR_SetConfig(htim->Instance,\r
-                        sSlaveConfig->TriggerPrescaler,\r
-                        sSlaveConfig->TriggerPolarity,\r
-                        sSlaveConfig->TriggerFilter);\r
-      break;\r
-    }\r
-\r
-    case TIM_TS_TI1F_ED:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
-\r
-      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-\r
-      /* Disable the Channel 1: Reset the CC1E Bit */\r
-      tmpccer = htim->Instance->CCER;\r
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
-      tmpccmr1 = htim->Instance->CCMR1;\r
-\r
-      /* Set the filter */\r
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);\r
-\r
-      /* Write to TIMx CCMR1 and CCER registers */\r
-      htim->Instance->CCMR1 = tmpccmr1;\r
-      htim->Instance->CCER = tmpccer;\r
-      break;\r
-    }\r
-\r
-    case TIM_TS_TI1FP1:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
-\r
-      /* Configure TI1 Filter and Polarity */\r
-      TIM_TI1_ConfigInputStage(htim->Instance,\r
-                               sSlaveConfig->TriggerPolarity,\r
-                               sSlaveConfig->TriggerFilter);\r
-      break;\r
-    }\r
-\r
-    case TIM_TS_TI2FP2:\r
-    {\r
-      /* Check the parameters */\r
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
-\r
-      /* Configure TI2 Filter and Polarity */\r
-      TIM_TI2_ConfigInputStage(htim->Instance,\r
-                               sSlaveConfig->TriggerPolarity,\r
-                               sSlaveConfig->TriggerFilter);\r
-      break;\r
-    }\r
-\r
-    case TIM_TS_ITR0:\r
-    case TIM_TS_ITR1:\r
-    case TIM_TS_ITR2:\r
-    case TIM_TS_ITR3:\r
-    {\r
-      /* Check the parameter */\r
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the TI1 as Input.\r
-  * @param  TIMx to select the TIM peripheral.\r
-  * @param  TIM_ICPolarity The Input Polarity.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICPOLARITY_RISING\r
-  *            @arg TIM_ICPOLARITY_FALLING\r
-  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
-  * @param  TIM_ICSelection specifies the input to be used.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.\r
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.\r
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.\r
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
-  *          This parameter must be a value between 0x00 and 0x0F.\r
-  * @retval None\r
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1\r
-  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be\r
-  *        protected against un-initialized filter and polarity values.\r
-  */\r
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
-                       uint32_t TIM_ICFilter)\r
-{\r
-  uint32_t tmpccmr1;\r
-  uint32_t tmpccer;\r
-\r
-  /* Disable the Channel 1: Reset the CC1E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC1E;\r
-  tmpccmr1 = TIMx->CCMR1;\r
-  tmpccer = TIMx->CCER;\r
-\r
-  /* Select the Input */\r
-  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
-  {\r
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
-    tmpccmr1 |= TIM_ICSelection;\r
-  }\r
-  else\r
-  {\r
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
-  }\r
-\r
-  /* Set the filter */\r
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
-  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);\r
-\r
-  /* Select the Polarity and set the CC1E Bit */\r
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
-  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
-\r
-  /* Write to TIMx CCMR1 and CCER registers */\r
-  TIMx->CCMR1 = tmpccmr1;\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the Polarity and Filter for TI1.\r
-  * @param  TIMx to select the TIM peripheral.\r
-  * @param  TIM_ICPolarity The Input Polarity.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICPOLARITY_RISING\r
-  *            @arg TIM_ICPOLARITY_FALLING\r
-  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
-  *          This parameter must be a value between 0x00 and 0x0F.\r
-  * @retval None\r
-  */\r
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
-{\r
-  uint32_t tmpccmr1;\r
-  uint32_t tmpccer;\r
-\r
-  /* Disable the Channel 1: Reset the CC1E Bit */\r
-  tmpccer = TIMx->CCER;\r
-  TIMx->CCER &= ~TIM_CCER_CC1E;\r
-  tmpccmr1 = TIMx->CCMR1;\r
-\r
-  /* Set the filter */\r
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
-  tmpccmr1 |= (TIM_ICFilter << 4U);\r
-\r
-  /* Select the Polarity and set the CC1E Bit */\r
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
-  tmpccer |= TIM_ICPolarity;\r
-\r
-  /* Write to TIMx CCMR1 and CCER registers */\r
-  TIMx->CCMR1 = tmpccmr1;\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the TI2 as Input.\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  TIM_ICPolarity The Input Polarity.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICPOLARITY_RISING\r
-  *            @arg TIM_ICPOLARITY_FALLING\r
-  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
-  * @param  TIM_ICSelection specifies the input to be used.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.\r
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.\r
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.\r
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
-  *          This parameter must be a value between 0x00 and 0x0F.\r
-  * @retval None\r
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2\r
-  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be\r
-  *        protected against un-initialized filter and polarity values.\r
-  */\r
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
-                              uint32_t TIM_ICFilter)\r
-{\r
-  uint32_t tmpccmr1;\r
-  uint32_t tmpccer;\r
-\r
-  /* Disable the Channel 2: Reset the CC2E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC2E;\r
-  tmpccmr1 = TIMx->CCMR1;\r
-  tmpccer = TIMx->CCER;\r
-\r
-  /* Select the Input */\r
-  tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
-  tmpccmr1 |= (TIM_ICSelection << 8U);\r
-\r
-  /* Set the filter */\r
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
-  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);\r
-\r
-  /* Select the Polarity and set the CC2E Bit */\r
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
-  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
-\r
-  /* Write to TIMx CCMR1 and CCER registers */\r
-  TIMx->CCMR1 = tmpccmr1 ;\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the Polarity and Filter for TI2.\r
-  * @param  TIMx to select the TIM peripheral.\r
-  * @param  TIM_ICPolarity The Input Polarity.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICPOLARITY_RISING\r
-  *            @arg TIM_ICPOLARITY_FALLING\r
-  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
-  *          This parameter must be a value between 0x00 and 0x0F.\r
-  * @retval None\r
-  */\r
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
-{\r
-  uint32_t tmpccmr1;\r
-  uint32_t tmpccer;\r
-\r
-  /* Disable the Channel 2: Reset the CC2E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC2E;\r
-  tmpccmr1 = TIMx->CCMR1;\r
-  tmpccer = TIMx->CCER;\r
-\r
-  /* Set the filter */\r
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
-  tmpccmr1 |= (TIM_ICFilter << 12U);\r
-\r
-  /* Select the Polarity and set the CC2E Bit */\r
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
-  tmpccer |= (TIM_ICPolarity << 4U);\r
-\r
-  /* Write to TIMx CCMR1 and CCER registers */\r
-  TIMx->CCMR1 = tmpccmr1 ;\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the TI3 as Input.\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  TIM_ICPolarity The Input Polarity.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICPOLARITY_RISING\r
-  *            @arg TIM_ICPOLARITY_FALLING\r
-  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
-  * @param  TIM_ICSelection specifies the input to be used.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.\r
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.\r
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.\r
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
-  *          This parameter must be a value between 0x00 and 0x0F.\r
-  * @retval None\r
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4\r
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
-  *        protected against un-initialized filter and polarity values.\r
-  */\r
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
-                              uint32_t TIM_ICFilter)\r
-{\r
-  uint32_t tmpccmr2;\r
-  uint32_t tmpccer;\r
-\r
-  /* Disable the Channel 3: Reset the CC3E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC3E;\r
-  tmpccmr2 = TIMx->CCMR2;\r
-  tmpccer = TIMx->CCER;\r
-\r
-  /* Select the Input */\r
-  tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
-  tmpccmr2 |= TIM_ICSelection;\r
-\r
-  /* Set the filter */\r
-  tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
-  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);\r
-\r
-  /* Select the Polarity and set the CC3E Bit */\r
-  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r
-  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
-\r
-  /* Write to TIMx CCMR2 and CCER registers */\r
-  TIMx->CCMR2 = tmpccmr2;\r
-  TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the TI4 as Input.\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  TIM_ICPolarity The Input Polarity.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICPOLARITY_RISING\r
-  *            @arg TIM_ICPOLARITY_FALLING\r
-  *            @arg TIM_ICPOLARITY_BOTHEDGE\r
-  * @param  TIM_ICSelection specifies the input to be used.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.\r
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.\r
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.\r
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r
-  *          This parameter must be a value between 0x00 and 0x0F.\r
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3\r
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
-  *        protected against un-initialized filter and polarity values.\r
-  * @retval None\r
-  */\r
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
-                              uint32_t TIM_ICFilter)\r
-{\r
-  uint32_t tmpccmr2;\r
-  uint32_t tmpccer;\r
-\r
-  /* Disable the Channel 4: Reset the CC4E Bit */\r
-  TIMx->CCER &= ~TIM_CCER_CC4E;\r
-  tmpccmr2 = TIMx->CCMR2;\r
-  tmpccer = TIMx->CCER;\r
-\r
-  /* Select the Input */\r
-  tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
-  tmpccmr2 |= (TIM_ICSelection << 8U);\r
-\r
-  /* Set the filter */\r
-  tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
-  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);\r
-\r
-  /* Select the Polarity and set the CC4E Bit */\r
-  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r
-  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
-\r
-  /* Write to TIMx CCMR2 and CCER registers */\r
-  TIMx->CCMR2 = tmpccmr2;\r
-  TIMx->CCER = tmpccer ;\r
-}\r
-\r
-/**\r
-  * @brief  Selects the Input Trigger source\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  InputTriggerSource The Input Trigger source.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_TS_ITR0: Internal Trigger 0\r
-  *            @arg TIM_TS_ITR1: Internal Trigger 1\r
-  *            @arg TIM_TS_ITR2: Internal Trigger 2\r
-  *            @arg TIM_TS_ITR3: Internal Trigger 3\r
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
-  *            @arg TIM_TS_ETRF: External Trigger input\r
-  * @retval None\r
-  */\r
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Get the TIMx SMCR register value */\r
-  tmpsmcr = TIMx->SMCR;\r
-  /* Reset the TS Bits */\r
-  tmpsmcr &= ~TIM_SMCR_TS;\r
-  /* Set the Input Trigger source and the slave mode*/\r
-  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);\r
-  /* Write to TIMx SMCR */\r
-  TIMx->SMCR = tmpsmcr;\r
-}\r
-/**\r
-  * @brief  Configures the TIMx External Trigger (ETR).\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.\r
-  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.\r
-  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.\r
-  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.\r
-  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.\r
-  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.\r
-  * @param  ExtTRGFilter External Trigger Filter.\r
-  *          This parameter must be a value between 0x00 and 0x0F\r
-  * @retval None\r
-  */\r
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  tmpsmcr = TIMx->SMCR;\r
-\r
-  /* Reset the ETR Bits */\r
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
-\r
-  /* Set the Prescaler, the Filter value and the Polarity */\r
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));\r
-\r
-  /* Write to TIMx SMCR */\r
-  TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
-  * @brief  Enables or disables the TIM Capture Compare Channel x.\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  Channel specifies the TIM Channel\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3\r
-  *            @arg TIM_CHANNEL_4: TIM Channel 4\r
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
-  * @param  ChannelState specifies the TIM Channel CCxE bit new state.\r
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.\r
-  * @retval None\r
-  */\r
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)\r
-{\r
-  uint32_t tmp;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));\r
-  assert_param(IS_TIM_CHANNELS(Channel));\r
-\r
-  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
-\r
-  /* Reset the CCxE Bit */\r
-  TIMx->CCER &= ~tmp;\r
-\r
-  /* Set or reset the CCxE Bit */\r
-  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
-}\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  Reset interrupt callbacks to the legacy weak callbacks.\r
-  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r
-  *                the configuration information for TIM module.\r
-  * @retval None\r
-  */\r
-void TIM_ResetCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Reset the TIM callback to the legacy weak callbacks */\r
-  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */\r
-  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */\r
-  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */\r
-  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */\r
-  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */\r
-  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */\r
-  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */\r
-  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */\r
-  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */\r
-  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */\r
-  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */\r
-  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */\r
-  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */\r
-  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */\r
-}\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_TIM_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
deleted file mode 100644 (file)
index 559abea..0000000
+++ /dev/null
@@ -1,2373 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_tim_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   TIM HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Timer Extended peripheral:\r
-  *           + Time Hall Sensor Interface Initialization\r
-  *           + Time Hall Sensor Interface Start\r
-  *           + Time Complementary signal break and dead time configuration\r
-  *           + Time Master and Slave synchronization configuration\r
-  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)\r
-  *           + Time OCRef clear configuration\r
-  *           + Timer remapping capabilities configuration\r
-  @verbatim\r
-  ==============================================================================\r
-                      ##### TIMER Extended features #####\r
-  ==============================================================================\r
-  [..]\r
-    The Timer Extended features include:\r
-    (#) Complementary outputs with programmable dead-time for :\r
-        (++) Output Compare\r
-        (++) PWM generation (Edge and Center-aligned Mode)\r
-        (++) One-pulse mode output\r
-    (#) Synchronization circuit to control the timer with external signals and to\r
-        interconnect several timers together.\r
-    (#) Break input to put the timer output signals in reset state or in a known state.\r
-    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for\r
-        positioning purposes\r
-\r
-            ##### How to use this driver #####\r
-  ==============================================================================\r
-    [..]\r
-     (#) Initialize the TIM low level resources by implementing the following functions\r
-         depending on the selected feature:\r
-           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()\r
-\r
-     (#) Initialize the TIM low level resources :\r
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
-        (##) TIM pins configuration\r
-            (+++) Enable the clock for the TIM GPIOs using the following function:\r
-              __HAL_RCC_GPIOx_CLK_ENABLE();\r
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
-\r
-     (#) The external Clock can be configured, if needed (the default clock is the\r
-         internal clock from the APBx), using the following function:\r
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
-         any start function.\r
-\r
-     (#) Configure the TIM in the desired functioning mode using one of the\r
-         initialization function of this driver:\r
-          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the\r
-               Timer Hall Sensor Interface and the commutation event with the corresponding\r
-               Interrupt and DMA request if needed (Note that One Timer is used to interface\r
-               with the Hall sensor Interface and another Timer should be used to use\r
-               the commutation event).\r
-\r
-     (#) Activate the TIM peripheral using one of the start functions:\r
-           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()\r
-           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r
-           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r
-           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup TIMEx TIMEx\r
-  * @brief TIM Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_TIM_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
-  * @brief    Timer Hall Sensor functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                      ##### Timer Hall Sensor functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Initialize and configure TIM HAL Sensor.\r
-    (+) De-initialize TIM HAL Sensor.\r
-    (+) Start the Hall Sensor Interface.\r
-    (+) Stop the Hall Sensor Interface.\r
-    (+) Start the Hall Sensor Interface and enable interrupts.\r
-    (+) Stop the Hall Sensor Interface and disable interrupts.\r
-    (+) Start the Hall Sensor Interface and enable DMA transfers.\r
-    (+) Stop the Hall Sensor Interface and disable DMA transfers.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-/**\r
-  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @param  sConfig TIM Hall Sensor configuration structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)\r
-{\r
-  TIM_OC_InitTypeDef OC_Config;\r
-\r
-  /* Check the TIM handle allocation */\r
-  if (htim == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
-\r
-  if (htim->State == HAL_TIM_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    htim->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-    /* Reset interrupt callbacks to legacy week callbacks */\r
-    TIM_ResetCallback(htim);\r
-\r
-    if (htim->HallSensor_MspInitCallback == NULL)\r
-    {\r
-      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;\r
-    }\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
-    htim->HallSensor_MspInitCallback(htim);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
-    HAL_TIMEx_HallSensor_MspInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  /* Set the TIM state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Configure the Time base in the Encoder Mode */\r
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
-  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */\r
-  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r
-\r
-  /* Reset the IC1PSC Bits */\r
-  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
-  /* Set the IC1PSC value */\r
-  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r
-\r
-  /* Enable the Hall sensor interface (XOR function of the three inputs) */\r
-  htim->Instance->CR2 |= TIM_CR2_TI1S;\r
-\r
-  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r
-  htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
-  htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r
-\r
-  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */\r
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
-  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r
-\r
-  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r
-  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
-  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
-  OC_Config.OCMode = TIM_OCMODE_PWM2;\r
-  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
-  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
-  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
-  OC_Config.Pulse = sConfig->Commutation_Delay;\r
-\r
-  TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r
-\r
-  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r
-    register to 101 */\r
-  htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
-  htim->Instance->CR2 |= TIM_TRGO_OC2REF;\r
-\r
-  /* Initialize the TIM state*/\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes the TIM Hall Sensor interface\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Disable the TIM Peripheral Clock */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  if (htim->HallSensor_MspDeInitCallback == NULL)\r
-  {\r
-    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  htim->HallSensor_MspDeInitCallback(htim);\r
-#else\r
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
-  HAL_TIMEx_HallSensor_MspDeInit(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-\r
-  /* Change TIM state */\r
-  htim->State = HAL_TIM_STATE_RESET;\r
-\r
-  /* Release Lock */\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initializes the TIM Hall Sensor MSP.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  DeInitializes TIM Hall Sensor MSP.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Hall Sensor Interface.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
-\r
-  /* Enable the Input Capture channel 1\r
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Hall sensor Interface.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
-\r
-  /* Disable the Input Capture channels 1, 2 and 3\r
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
-\r
-  /* Enable the capture compare Interrupts 1 event */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-\r
-  /* Enable the Input Capture channel 1\r
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
-\r
-  /* Disable the Input Capture channel 1\r
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
-  /* Disable the capture compare Interrupts event */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @param  pData The destination Buffer address.\r
-  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if (((uint32_t)pData == 0U) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-  /* Enable the Input Capture channel 1\r
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-\r
-  /* Set the DMA Input Capture 1 Callbacks */\r
-  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
-  /* Set the DMA error callback */\r
-  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-  /* Enable the DMA channel for Capture 1*/\r
-  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-  /* Enable the capture compare 1 Interrupt */\r
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.\r
-  * @param  htim TIM Hall Sensor Interface handle\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
-\r
-  /* Disable the Input Capture channel 1\r
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
-\r
-  /* Disable the capture compare Interrupts 1 event */\r
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-\r
-  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
-  *  @brief   Timer Complementary Output Compare functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-              ##### Timer Complementary Output Compare functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Start the Complementary Output Compare/PWM.\r
-    (+) Stop the Complementary Output Compare/PWM.\r
-    (+) Start the Complementary Output Compare/PWM and enable interrupts.\r
-    (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r
-    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r
-    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Starts the TIM Output Compare signal generation on the complementary\r
-  *         output.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Enable the Capture compare channel N */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Output Compare signal generation on the complementary\r
-  *         output.\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Disable the Capture compare channel N */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode\r
-  *         on the complementary output.\r
-  * @param  htim TIM OC handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Enable the TIM Output Compare interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Enable the TIM Output Compare interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Enable the TIM Output Compare interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the TIM Break interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
-\r
-  /* Enable the Capture compare channel N */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode\r
-  *         on the complementary output.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpccer;\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Output Compare interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Output Compare interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Output Compare interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Capture compare channel N */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the TIM Break interrupt (only if no more channel is active) */\r
-  tmpccer = htim->Instance->CCER;\r
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
-  {\r
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
-  }\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode\r
-  *         on the complementary output.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @param  pData The source Buffer address.\r
-  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if (((uint32_t)pData == 0U) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do  */\r
-  }\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Output Compare DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Output Compare DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Output Compare DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the Capture compare channel N */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode\r
-  *         on the complementary output.\r
-  * @param  htim TIM Output Compare handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Output Compare DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Output Compare DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Output Compare DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the Capture compare channel N */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
-  * @brief    Timer Complementary PWM functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                 ##### Timer Complementary PWM functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Start the Complementary PWM.\r
-    (+) Stop the Complementary PWM.\r
-    (+) Start the Complementary PWM and enable interrupts.\r
-    (+) Stop the Complementary PWM and disable interrupts.\r
-    (+) Start the Complementary PWM and enable DMA transfers.\r
-    (+) Stop the Complementary PWM and disable DMA transfers.\r
-    (+) Start the Complementary Input Capture measurement.\r
-    (+) Stop the Complementary Input Capture.\r
-    (+) Start the Complementary Input Capture and enable interrupts.\r
-    (+) Stop the Complementary Input Capture and disable interrupts.\r
-    (+) Start the Complementary Input Capture and enable DMA transfers.\r
-    (+) Stop the Complementary Input Capture and disable DMA transfers.\r
-    (+) Start the Complementary One Pulse generation.\r
-    (+) Stop the Complementary One Pulse.\r
-    (+) Start the Complementary One Pulse and enable interrupts.\r
-    (+) Stop the Complementary One Pulse and disable interrupts.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Starts the PWM signal generation on the complementary output.\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Enable the complementary PWM output  */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the PWM signal generation on the complementary output.\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  /* Disable the complementary PWM output  */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the PWM signal generation in interrupt mode on the\r
-  *         complementary output.\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Enable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Enable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Enable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the TIM Break interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
-\r
-  /* Enable the complementary PWM output  */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the PWM signal generation in interrupt mode on the\r
-  *         complementary output.\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  uint32_t tmpccer;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3 interrupt */\r
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the complementary PWM output  */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the TIM Break interrupt (only if no more channel is active) */\r
-  tmpccer = htim->Instance->CCER;\r
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
-  {\r
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
-  }\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM PWM signal generation in DMA mode on the\r
-  *         complementary output\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @param  pData The source Buffer address.\r
-  * @param  Length The length of data to be transferred from memory to TIM peripheral\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  if ((htim->State == HAL_TIM_STATE_BUSY))\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-  else if ((htim->State == HAL_TIM_STATE_READY))\r
-  {\r
-    if (((uint32_t)pData == 0U) && (Length > 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-    else\r
-    {\r
-      htim->State = HAL_TIM_STATE_BUSY;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* nothing to do */\r
-  }\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 2 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Set the DMA compare callbacks */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
-      {\r
-        return HAL_ERROR;\r
-      }\r
-      /* Enable the TIM Capture/Compare 3 DMA request */\r
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Enable the complementary PWM output  */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
-  {\r
-    __HAL_TIM_ENABLE(htim);\r
-  }\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary\r
-  *         output\r
-  * @param  htim TIM handle\r
-  * @param  Channel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
-  switch (Channel)\r
-  {\r
-    case TIM_CHANNEL_1:\r
-    {\r
-      /* Disable the TIM Capture/Compare 1 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_2:\r
-    {\r
-      /* Disable the TIM Capture/Compare 2 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
-      break;\r
-    }\r
-\r
-    case TIM_CHANNEL_3:\r
-    {\r
-      /* Disable the TIM Capture/Compare 3 DMA request */\r
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
-      break;\r
-    }\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  /* Disable the complementary PWM output */\r
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
-  * @brief    Timer Complementary One Pulse functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                ##### Timer Complementary One Pulse functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-    (+) Start the Complementary One Pulse generation.\r
-    (+) Stop the Complementary One Pulse.\r
-    (+) Start the Complementary One Pulse and enable interrupts.\r
-    (+) Stop the Complementary One Pulse and disable interrupts.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Starts the TIM One Pulse signal generation on the complementary\r
-  *         output.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
-  /* Enable the complementary One Pulse output */\r
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM One Pulse signal generation on the complementary\r
-  *         output.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
-  /* Disable the complementary One Pulse output */\r
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the\r
-  *         complementary channel.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channel to be enabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
-  /* Enable the TIM Capture/Compare 1 interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-\r
-  /* Enable the TIM Capture/Compare 2 interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-\r
-  /* Enable the complementary One Pulse output */\r
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
-\r
-  /* Enable the Main Output */\r
-  __HAL_TIM_MOE_ENABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the\r
-  *         complementary channel.\r
-  * @param  htim TIM One Pulse handle\r
-  * @param  OutputChannel TIM Channel to be disabled\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
-  /* Disable the TIM Capture/Compare 1 interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-\r
-  /* Disable the TIM Capture/Compare 2 interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-\r
-  /* Disable the complementary One Pulse output */\r
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
-\r
-  /* Disable the Main Output */\r
-  __HAL_TIM_MOE_DISABLE(htim);\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_TIM_DISABLE(htim);\r
-\r
-  /* Return function status */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
-  * @brief    Peripheral Control functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                    ##### Peripheral Control functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides functions allowing to:\r
-      (+) Configure the commutation event in case of use of the Hall sensor interface.\r
-      (+) Configure Output channels for OC and PWM mode.\r
-\r
-      (+) Configure Complementary channels, break features and dead time.\r
-      (+) Configure Master synchronization.\r
-      (+) Configure timer remapping capabilities.\r
-      (+) Enable or disable channel grouping.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Configure the TIM commutation event sequence.\r
-  * @note  This function is mandatory to use the commutation event in order to\r
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r
-  *        the typical use of this feature is with the use of another Timer(interface Timer)\r
-  *        configured in Hall sensor interface, this interface Timer will generate the\r
-  *        commutation at its TRGO output (connected to Timer used in this function) each time\r
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r
-  * @param  htim TIM handle\r
-  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r
-  *            @arg TIM_TS_NONE: No trigger is needed\r
-  * @param  CommutationSource the Commutation Event source\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
-                                              uint32_t  CommutationSource)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
-\r
-  __HAL_LOCK(htim);\r
-\r
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
-  {\r
-    /* Select the Input trigger */\r
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
-    htim->Instance->SMCR |= InputTrigger;\r
-  }\r
-\r
-  /* Select the Capture Compare preload feature */\r
-  htim->Instance->CR2 |= TIM_CR2_CCPC;\r
-  /* Select the Commutation event source */\r
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
-  htim->Instance->CR2 |= CommutationSource;\r
-\r
-  /* Disable Commutation Interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
-\r
-  /* Disable Commutation DMA request */\r
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the TIM commutation event sequence with interrupt.\r
-  * @note  This function is mandatory to use the commutation event in order to\r
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r
-  *        the typical use of this feature is with the use of another Timer(interface Timer)\r
-  *        configured in Hall sensor interface, this interface Timer will generate the\r
-  *        commutation at its TRGO output (connected to Timer used in this function) each time\r
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r
-  * @param  htim TIM handle\r
-  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r
-  *            @arg TIM_TS_NONE: No trigger is needed\r
-  * @param  CommutationSource the Commutation Event source\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
-                                                 uint32_t  CommutationSource)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
-\r
-  __HAL_LOCK(htim);\r
-\r
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
-  {\r
-    /* Select the Input trigger */\r
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
-    htim->Instance->SMCR |= InputTrigger;\r
-  }\r
-\r
-  /* Select the Capture Compare preload feature */\r
-  htim->Instance->CR2 |= TIM_CR2_CCPC;\r
-  /* Select the Commutation event source */\r
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
-  htim->Instance->CR2 |= CommutationSource;\r
-\r
-  /* Disable Commutation DMA request */\r
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
-\r
-  /* Enable the Commutation Interrupt */\r
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configure the TIM commutation event sequence with DMA.\r
-  * @note  This function is mandatory to use the commutation event in order to\r
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r
-  *        the typical use of this feature is with the use of another Timer(interface Timer)\r
-  *        configured in Hall sensor interface, this interface Timer will generate the\r
-  *        commutation at its TRGO output (connected to Timer used in this function) each time\r
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r
-  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set\r
-  * @param  htim TIM handle\r
-  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r
-  *            @arg TIM_TS_NONE: No trigger is needed\r
-  * @param  CommutationSource the Commutation Event source\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\r
-                                                  uint32_t  CommutationSource)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
-\r
-  __HAL_LOCK(htim);\r
-\r
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
-  {\r
-    /* Select the Input trigger */\r
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
-    htim->Instance->SMCR |= InputTrigger;\r
-  }\r
-\r
-  /* Select the Capture Compare preload feature */\r
-  htim->Instance->CR2 |= TIM_CR2_CCPC;\r
-  /* Select the Commutation event source */\r
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
-  htim->Instance->CR2 |= CommutationSource;\r
-\r
-  /* Enable the Commutation DMA Request */\r
-  /* Set the DMA Commutation Callback */\r
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
-  /* Set the DMA error callback */\r
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;\r
-\r
-  /* Disable Commutation Interrupt */\r
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
-\r
-  /* Enable the Commutation DMA Request */\r
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configures the TIM in master mode.\r
-  * @param  htim TIM handle.\r
-  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that\r
-  *         contains the selected trigger output (TRGO) and the Master/Slave\r
-  *         mode.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
-                                                        TIM_MasterConfigTypeDef *sMasterConfig)\r
-{\r
-  uint32_t tmpcr2;\r
-  uint32_t tmpsmcr;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
-  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
-\r
-  /* Check input state */\r
-  __HAL_LOCK(htim);\r
-\r
-  /* Change the handler state */\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Get the TIMx CR2 register value */\r
-  tmpcr2 = htim->Instance->CR2;\r
-\r
-  /* Get the TIMx SMCR register value */\r
-  tmpsmcr = htim->Instance->SMCR;\r
-\r
-  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */\r
-  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));\r
-\r
-    /* Clear the MMS2 bits */\r
-    tmpcr2 &= ~TIM_CR2_MMS2;\r
-    /* Select the TRGO2 source*/\r
-    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;\r
-  }\r
-\r
-  /* Reset the MMS Bits */\r
-  tmpcr2 &= ~TIM_CR2_MMS;\r
-  /* Select the TRGO source */\r
-  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;\r
-\r
-  /* Reset the MSM Bit */\r
-  tmpsmcr &= ~TIM_SMCR_MSM;\r
-  /* Set master mode */\r
-  tmpsmcr |= sMasterConfig->MasterSlaveMode;\r
-\r
-  /* Update TIMx CR2 */\r
-  htim->Instance->CR2 = tmpcr2;\r
-\r
-  /* Update TIMx SMCR */\r
-  htim->Instance->SMCR = tmpsmcr;\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r
-  *         and the AOE(automatic output enable).\r
-  * @param  htim TIM handle\r
-  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that\r
-  *         contains the BDTR Register configuration  information for the TIM peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
-                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)\r
-{\r
-  /* Keep this variable initialized to 0 as it is used to configure BDTR register */\r
-  uint32_t tmpbdtr = 0U;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r
-  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r
-  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r
-  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r
-  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r
-  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r
-  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));\r
-  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r
-\r
-  /* Check input state */\r
-  __HAL_LOCK(htim);\r
-\r
-  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
-\r
-  /* Set the BDTR bits */\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);\r
-  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));\r
-\r
-  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));\r
-    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));\r
-    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));\r
-\r
-    /* Set the BREAK2 input related BDTR bits */\r
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));\r
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);\r
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);\r
-  }\r
-\r
-  /* Set TIMx_BDTR */\r
-  htim->Instance->BDTR = tmpbdtr;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configures the break input source.\r
-  * @param  htim TIM handle.\r
-  * @param  BreakInput Break input to configure\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_BREAKINPUT_BRK: Timer break input\r
-  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input\r
-  * @param  sBreakInputConfig Break input source configuration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,\r
-                                             uint32_t BreakInput,\r
-                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)\r
-\r
-{\r
-  uint32_t tmporx;\r
-  uint32_t bkin_enable_mask = 0U;\r
-  uint32_t bkin_polarity_mask = 0U;\r
-  uint32_t bkin_enable_bitpos = 0U;\r
-  uint32_t bkin_polarity_bitpos = 0U;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_BREAKINPUT(BreakInput));\r
-  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));\r
-  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));\r
-#if defined(DFSDM1_Channel0)\r
-  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
-  {\r
-    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));\r
-  }\r
-#else\r
-  assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));\r
-#endif /* DFSDM1_Channel0 */\r
-\r
-  /* Check input state */\r
-  __HAL_LOCK(htim);\r
-\r
-  switch (sBreakInputConfig->Source)\r
-  {\r
-    case TIM_BREAKINPUTSOURCE_BKIN:\r
-    {\r
-      bkin_enable_mask = TIM1_OR2_BKINE;\r
-      bkin_enable_bitpos = TIM1_OR2_BKINE_Pos;\r
-      bkin_polarity_mask = TIM1_OR2_BKINP;\r
-      bkin_polarity_bitpos = TIM1_OR2_BKINP_Pos;\r
-      break;\r
-    }\r
-    case TIM_BREAKINPUTSOURCE_COMP1:\r
-    {\r
-      bkin_enable_mask = TIM1_OR2_BKCMP1E;\r
-      bkin_enable_bitpos = TIM1_OR2_BKCMP1E_Pos;\r
-      bkin_polarity_mask = TIM1_OR2_BKCMP1P;\r
-      bkin_polarity_bitpos = TIM1_OR2_BKCMP1P_Pos;\r
-      break;\r
-    }\r
-    case TIM_BREAKINPUTSOURCE_COMP2:\r
-    {\r
-      bkin_enable_mask = TIM1_OR2_BKCMP2E;\r
-      bkin_enable_bitpos = TIM1_OR2_BKCMP2E_Pos;\r
-      bkin_polarity_mask = TIM1_OR2_BKCMP2P;\r
-      bkin_polarity_bitpos = TIM1_OR2_BKCMP2P_Pos;\r
-      break;\r
-    }\r
-#if defined(DFSDM1_Channel0)\r
-    case TIM_BREAKINPUTSOURCE_DFSDM1:\r
-    {\r
-      bkin_enable_mask = TIM1_OR2_BKDF1BK0E;\r
-      bkin_enable_bitpos = 8U;\r
-      break;\r
-    }\r
-#endif /* DFSDM1_Channel0 */\r
-\r
-    default:\r
-      break;\r
-  }\r
-\r
-  switch (BreakInput)\r
-  {\r
-    case TIM_BREAKINPUT_BRK:\r
-    {\r
-      /* Get the TIMx_OR2 register value */\r
-      tmporx = htim->Instance->OR2;\r
-\r
-      /* Enable the break input */\r
-      tmporx &= ~bkin_enable_mask;\r
-      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
-\r
-      /* Set the break input polarity */\r
-#if defined(DFSDM1_Channel0)\r
-      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
-#endif /* DFSDM1_Channel0 */\r
-      {\r
-        tmporx &= ~bkin_polarity_mask;\r
-        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
-      }\r
-\r
-      /* Set TIMx_OR2 */\r
-      htim->Instance->OR2 = tmporx;\r
-      break;\r
-    }\r
-    case TIM_BREAKINPUT_BRK2:\r
-    {\r
-      /* Get the TIMx_OR3 register value */\r
-      tmporx = htim->Instance->OR3;\r
-\r
-      /* Enable the break input */\r
-      tmporx &= ~bkin_enable_mask;\r
-      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
-\r
-      /* Set the break input polarity */\r
-#if defined(DFSDM1_Channel0)\r
-      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
-#endif /* DFSDM1_Channel0 */\r
-      {\r
-        tmporx &= ~bkin_polarity_mask;\r
-        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
-      }\r
-\r
-      /* Set TIMx_OR3 */\r
-      htim->Instance->OR3 = tmporx;\r
-      break;\r
-    }\r
-    default:\r
-      break;\r
-  }\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Configures the TIMx Remapping input capabilities.\r
-  * @param  htim TIM handle.\r
-  * @param  Remap specifies the TIM remapping source.\r
-    @if STM32L422xx\r
-  *         For TIM1, the parameter is a combination of 2 fields (field1 | field2):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output\r
-  *\r
-  @endif\r
-@if STM32L486xx\r
-  *         For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM1_ETR_ADC3_NONE:           TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)\r
-  *            @arg TIM_TIM1_ETR_ADC3_AWD1:           TIM1_ETR is connected to ADC3 AWD1\r
-  *            @arg TIM_TIM1_ETR_ADC3_AWD2:           TIM1_ETR is connected to ADC3 AWD2\r
-  *            @arg TIM_TIM1_ETR_ADC3_AWD3:           TIM1_ETR is connected to ADC3 AWD3\r
-  *\r
-  *                   field3 can have the following values:\r
-  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output\r
-  *\r
-  *                   field4 can have the following values:\r
-  *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output\r
-  *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output\r
-  *            @note  When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant\r
-  @endif\r
-  @if STM32L443xx\r
-  *         For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2\r
-  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output\r
-  *\r
-  *                   field3 can have the following values:\r
-  *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output\r
-  *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output\r
-  *\r
-  *            @note  When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant\r
-  *\r
-  @endif\r
-  @if STM32L486xx\r
-  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM2_ITR1_TIM8_TRGO:          TIM2_ITR1 is connected to TIM8_TRGO\r
-  *            @arg TIM_TIM2_ITR1_OTG_FS_SOF:         TIM2_ITR1 is connected to OTG_FS SOF\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO\r
-  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE\r
-  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output\r
-  *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output\r
-  *\r
-  *                   field3 can have the following values:\r
-  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO\r
-  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output\r
-  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output\r
-  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output\r
-  @endif\r
-  @if STM32L422xx\r
-  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1\r
-  *            @arg TIM_TIM2_ITR1_USB_SOF:            TIM2_ITR1 is connected to USB SOF\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO\r
-  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE\r
-  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output\r
-  *\r
-  *                   field3 can have the following values:\r
-  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO\r
-  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output\r
-  *\r
-  @endif\r
-  @if STM32L443xx\r
-  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1\r
-  *            @arg TIM_TIM2_ITR1_USB_SOF:            TIM2_ITR1 is connected to USB SOF\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO\r
-  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE\r
-  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output\r
-  *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output\r
-  *\r
-  *                   field3 can have the following values:\r
-  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO\r
-  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output\r
-  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output\r
-  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output\r
-  *\r
-  @endif\r
-  @if STM32L486xx\r
-  *         For TIM3, the parameter is a combination 2 fields(field1 | field2):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output\r
-  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output\r
-  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM3_ETR_GPIO:                TIM3_ETR is connected to GPIO\r
-  *            @arg TIM_TIM3_ETR_COMP1:               TIM3_ETR is connected to COMP1 output\r
-  *\r
-  @endif\r
-  @if STM32L486xx\r
-  *         For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM8_ETR_ADC2_NONE:          TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)\r
-  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1\r
-  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2\r
-  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM8_ETR_ADC3_NONE:          TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)\r
-  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1\r
-  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2\r
-  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3\r
-  *\r
-  *                   field3 can have the following values:\r
-  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output\r
-  *\r
-  *                   field4 can have the following values:\r
-  *            @arg TIM_TIM8_ETR_COMP1:               TIM8_ETR is connected to COMP1 output\r
-  *            @arg TIM_TIM8_ETR_COMP2:               TIM8_ETR is connected to COMP2 output\r
-  *            @note  When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant\r
-  *\r
-  @endif\r
-  @if STM32L422xx\r
-  *         For TIM15, the parameter is a combination of 2 fields (field1 | field2):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection\r
-  *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
-  *\r
-  @endif\r
-  @if STM32L443xx\r
-  *         For TIM15, the parameter is a combination of 2 fields (field1 | field2):\r
-  *\r
-  *                   field1 can have the following values:\r
-  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE\r
-  *\r
-  *                   field2 can have the following values:\r
-  *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection\r
-  *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
-  *            @arg TIM_TIM15_ENCODERMODE_TIM3:      TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
-  *            @arg TIM_TIM15_ENCODERMODE_TIM4:      TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively\r
-  *\r
-  @endif\r
-  @if STM32L486xx\r
-  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI\r
-  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE\r
-  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt\r
-  *\r
-  @endif\r
-  @if STM32L422xx\r
-  *         For TIM16, the parameter can have the following values:\r
-  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI\r
-  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE\r
-  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt\r
-  *            @arg TIM_TIM16_TI1_MSI:               TIM16 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)\r
-  *            @arg TIM_TIM16_TI1_HSE_32:            TIM16 TI1 is connected to HSE div 32  (note that HSE div 32 must be selected as RTC clock source)\r
-  *            @arg TIM_TIM16_TI1_MCO:               TIM16 TI1 is connected to MCO\r
-  *\r
-  @endif\r
-  @if STM32L443xx\r
-  *         For TIM16, the parameter can have the following values:\r
-  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI\r
-  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE\r
-  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt\r
-  *            @arg TIM_TIM16_TI1_MSI:               TIM16 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)\r
-  *            @arg TIM_TIM16_TI1_HSE_32:            TIM16 TI1 is connected to HSE div 32  (note that HSE div 32 must be selected as RTC clock source)\r
-  *            @arg TIM_TIM16_TI1_MCO:               TIM16 TI1 is connected to MCO\r
-  *\r
-  @endif\r
-  @if STM32L486xx\r
-  *         For TIM17, the parameter can have the following values:\r
-  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO\r
-  *            @arg TIM_TIM17_TI1_MSI:               TIM17 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)\r
-  *            @arg TIM_TIM17_TI1_HSE_32:            TIM17 TI1 is connected to HSE div 32\r
-  *            @arg TIM_TIM17_TI1_MCO:               TIM17 TI1 is connected to MCO\r
-  @endif\r
-  *\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r
-{\r
-  uint32_t tmpor1 = 0U;\r
-  uint32_t tmpor2 = 0U;\r
-\r
-  __HAL_LOCK(htim);\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_REMAP(Remap));\r
-\r
-  /* Set ETR_SEL bit field (if required) */\r
-  if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))\r
-  {\r
-    tmpor2 = htim->Instance->OR2;\r
-    tmpor2 &= ~TIM1_OR2_ETRSEL_Msk;\r
-    tmpor2 |= (Remap & TIM1_OR2_ETRSEL_Msk);\r
-\r
-    /* Set TIMx_OR2 */\r
-    htim->Instance->OR2 = tmpor2;\r
-  }\r
-\r
-  /* Set other remapping capabilities */\r
-  tmpor1 = Remap;\r
-  tmpor1 &= ~TIM1_OR2_ETRSEL_Msk;\r
-\r
-  /* Set TIMx_OR1 */\r
-  htim->Instance->OR1 = tmpor1;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Group channel 5 and channel 1, 2 or 3\r
-  * @param  htim TIM handle.\r
-  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.\r
-  *         This parameter can be any combination of the following values:\r
-  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC\r
-  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF\r
-  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF\r
-  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)\r
-{\r
-  /* Check parameters */\r
-  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));\r
-  assert_param(IS_TIM_GROUPCH5(Channels));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(htim);\r
-\r
-  htim->State = HAL_TIM_STATE_BUSY;\r
-\r
-  /* Clear GC5Cx bit fields */\r
-  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);\r
-\r
-  /* Set GC5Cx bit fields */\r
-  htim->Instance->CCR5 |= Channels;\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-  __HAL_UNLOCK(htim);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
-  * @brief    Extended Callbacks functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                    ##### Extended Callbacks functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This section provides Extended TIM callback functions:\r
-    (+) Timer Commutation callback\r
-    (+) Timer Break callback\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Hall commutation changed callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIMEx_CommutCallback could be implemented in the user file\r
-   */\r
-}\r
-/**\r
-  * @brief  Hall commutation changed half complete callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Hall Break detection callback in non-blocking mode\r
-  * @param  htim TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_TIMEx_BreakCallback could be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Hall Break2 detection callback in non blocking mode\r
-  * @param  htim: TIM handle\r
-  * @retval None\r
-  */\r
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(htim);\r
-\r
-  /* NOTE : This function Should not be modified, when the callback is needed,\r
-            the HAL_TIMEx_Break2Callback could be implemented in the user file\r
-   */\r
-}\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
-  * @brief    Extended Peripheral State functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-                ##### Extended Peripheral State functions #####\r
-  ==============================================================================\r
-  [..]\r
-    This subsection permits to get in run-time the status of the peripheral\r
-    and the data flow.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Return the TIM Hall Sensor interface handle state.\r
-  * @param  htim TIM Hall Sensor handle\r
-  * @retval HAL state\r
-  */\r
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r
-{\r
-  return htim->State;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  TIM DMA Commutation callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->CommutationCallback(htim);\r
-#else\r
-  HAL_TIMEx_CommutCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  TIM DMA Commutation half complete callback.\r
-  * @param  hdma pointer to DMA handle.\r
-  * @retval None\r
-  */\r
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  /* Change the htim state */\r
-  htim->State = HAL_TIM_STATE_READY;\r
-\r
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
-  htim->CommutationHalfCpltCallback(htim);\r
-#else\r
-  HAL_TIMEx_CommutHalfCpltCallback(htim);\r
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Enables or disables the TIM Capture Compare Channel xN.\r
-  * @param  TIMx to select the TIM peripheral\r
-  * @param  Channel specifies the TIM Channel\r
-  *          This parameter can be one of the following values:\r
-  *            @arg TIM_CHANNEL_1: TIM Channel 1\r
-  *            @arg TIM_CHANNEL_2: TIM Channel 2\r
-  *            @arg TIM_CHANNEL_3: TIM Channel 3\r
-  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.\r
-  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.\r
-  * @retval None\r
-  */\r
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)\r
-{\r
-  uint32_t tmp;\r
-\r
-  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
-\r
-  /* Reset the CCxNE Bit */\r
-  TIMx->CCER &=  ~tmp;\r
-\r
-  /* Set or reset the CCxNE Bit */\r
-  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
-}\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_TIM_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
deleted file mode 100644 (file)
index 696c3f0..0000000
+++ /dev/null
@@ -1,4143 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_uart.c\r
-  * @author  MCD Application Team\r
-  * @brief   UART HAL module driver.\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\r
-  *           + Initialization and de-initialization functions\r
-  *           + IO operation functions\r
-  *           + Peripheral Control functions\r
-  *\r
-  *\r
-  @verbatim\r
- ===============================================================================\r
-                        ##### How to use this driver #####\r
- ===============================================================================\r
-  [..]\r
-    The UART HAL driver can be used as follows:\r
-\r
-    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).\r
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r
-        (++) Enable the USARTx interface clock.\r
-        (++) UART pins configuration:\r
-            (+++) Enable the clock for the UART GPIOs.\r
-            (+++) Configure these UART pins as alternate function pull-up.\r
-        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r
-             and HAL_UART_Receive_IT() APIs):\r
-            (+++) Configure the USARTx interrupt priority.\r
-            (+++) Enable the NVIC USART IRQ handle.\r
-        (++) UART interrupts handling:\r
-              -@@-  The specific UART interrupts (Transmission complete interrupt,\r
-                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)\r
-                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()\r
-                inside the transmit and receive processes.\r
-        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r
-             and HAL_UART_Receive_DMA() APIs):\r
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.\r
-            (+++) Enable the DMAx interface clock.\r
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r
-            (+++) Configure the DMA Tx/Rx channel.\r
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.\r
-\r
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware\r
-        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.\r
-\r
-    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)\r
-        in the huart handle AdvancedInit structure.\r
-\r
-    (#) For the UART asynchronous mode, initialize the UART registers by calling\r
-        the HAL_UART_Init() API.\r
-\r
-    (#) For the UART Half duplex mode, initialize the UART registers by calling\r
-        the HAL_HalfDuplex_Init() API.\r
-\r
-    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers\r
-        by calling the HAL_LIN_Init() API.\r
-\r
-    (#) For the UART Multiprocessor mode, initialize the UART registers\r
-        by calling the HAL_MultiProcessor_Init() API.\r
-\r
-    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers\r
-        by calling the HAL_RS485Ex_Init() API.\r
-\r
-    [..]\r
-    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),\r
-        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by\r
-        calling the customized HAL_UART_MspInit() API.\r
-\r
-    ##### Callback registration #####\r
-    ==================================\r
-\r
-    [..]\r
-    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1\r
-    allows the user to configure dynamically the driver callbacks.\r
-\r
-    [..]\r
-    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.\r
-    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:\r
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.\r
-    (+) TxCpltCallback            : Tx Complete Callback.\r
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.\r
-    (+) RxCpltCallback            : Rx Complete Callback.\r
-    (+) ErrorCallback             : Error Callback.\r
-    (+) AbortCpltCallback         : Abort Complete Callback.\r
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.\r
-    (+) WakeupCallback            : Wakeup Callback.\r
-    (+) RxFifoFullCallback        : Rx Fifo Full Callback.\r
-    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.\r
-    (+) MspInitCallback           : UART MspInit.\r
-    (+) MspDeInitCallback         : UART MspDeInit.\r
-    This function takes as parameters the HAL peripheral handle, the Callback ID\r
-    and a pointer to the user callback function.\r
-\r
-    [..]\r
-    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default\r
-    weak (surcharged) function.\r
-    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
-    and the Callback ID.\r
-    This function allows to reset following callbacks:\r
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.\r
-    (+) TxCpltCallback            : Tx Complete Callback.\r
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.\r
-    (+) RxCpltCallback            : Rx Complete Callback.\r
-    (+) ErrorCallback             : Error Callback.\r
-    (+) AbortCpltCallback         : Abort Complete Callback.\r
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.\r
-    (+) WakeupCallback            : Wakeup Callback.\r
-    (+) RxFifoFullCallback        : Rx Fifo Full Callback.\r
-    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.\r
-    (+) MspInitCallback           : UART MspInit.\r
-    (+) MspDeInitCallback         : UART MspDeInit.\r
-\r
-    [..]\r
-    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET\r
-    all callbacks are set to the corresponding weak (surcharged) functions:\r
-    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().\r
-    Exception done for MspInit and MspDeInit functions that are respectively\r
-    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()\r
-    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).\r
-    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()\r
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).\r
-\r
-    [..]\r
-    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.\r
-    Exception done MspInit/MspDeInit that can be registered/unregistered\r
-    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)\r
-    MspInit/DeInit callbacks can be used during the Init/DeInit.\r
-    In that case first register the MspInit/MspDeInit user callbacks\r
-    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()\r
-    or @ref HAL_UART_Init() function.\r
-\r
-    [..]\r
-    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or\r
-    not defined, the callback registration feature is not available\r
-    and weak (surcharged) callbacks are used.\r
-\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup UART UART\r
-  * @brief HAL UART module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_UART_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup UART_Private_Constants UART Private Constants\r
-  * @{\r
-  */\r
-#if defined(USART_CR1_FIFOEN)\r
-#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
-                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \\r
-                                      USART_CR1_FIFOEN ))                      /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */\r
-#else\r
-#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
-                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \\r
-                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */\r
-#else\r
-#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */\r
-#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */\r
-\r
-#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */\r
-#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @addtogroup UART_Private_Functions\r
-  * @{\r
-  */\r
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);\r
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);\r
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
-static void UART_DMAError(DMA_HandleTypeDef *hdma);\r
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
-static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);\r
-static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);\r
-#if defined(USART_CR1_FIFOEN)\r
-static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);\r
-static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);\r
-#endif /* USART_CR1_FIFOEN */\r
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);\r
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);\r
-#if defined(USART_CR1_FIFOEN)\r
-static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);\r
-static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);\r
-#endif /* USART_CR1_FIFOEN */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup UART_Exported_Functions UART Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  *  @brief    Initialization and Configuration functions\r
-  *\r
-@verbatim\r
-===============================================================================\r
-            ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
-    in asynchronous mode.\r
-      (+) For the asynchronous mode the parameters below can be configured:\r
-        (++) Baud Rate\r
-        (++) Word Length\r
-        (++) Stop Bit\r
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
-             in the data register is transmitted but is changed by the parity bit.\r
-        (++) Hardware flow control\r
-        (++) Receiver/transmitter modes\r
-        (++) Over Sampling Method\r
-        (++) One-Bit Sampling Method\r
-      (+) For the asynchronous mode, the following advanced features can be configured as well:\r
-        (++) TX and/or RX pin level inversion\r
-        (++) data logical level inversion\r
-        (++) RX and TX pins swap\r
-        (++) RX overrun detection disabling\r
-        (++) DMA disabling on RX error\r
-        (++) MSB first on communication line\r
-        (++) auto Baud rate detection\r
-    [..]\r
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API\r
-    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode\r
-    and UART multiprocessor mode configuration procedures (details for the procedures\r
-    are available in reference manual).\r
-\r
-@endverbatim\r
-\r
-  Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
-  8-bit or 9-bit), the possible UART formats are listed in the\r
-  following table.\r
-\r
-  Table 1. UART frame format.\r
-    +-----------------------------------------------------------------------+\r
-    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |\r
-    +-----------------------------------------------------------------------+\r
-\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Initialize the UART mode according to the specified\r
-  *        parameters in the UART_InitTypeDef and initialize the associated handle.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r
-{\r
-  /* Check the UART handle allocation */\r
-  if (huart == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r
-  {\r
-    /* Check the parameters */\r
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r
-  }\r
-  else\r
-  {\r
-    /* Check the parameters */\r
-    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));\r
-  }\r
-\r
-  if (huart->gState == HAL_UART_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    huart->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    UART_InitCallbacksToDefault(huart);\r
-\r
-    if (huart->MspInitCallback == NULL)\r
-    {\r
-      huart->MspInitCallback = HAL_UART_MspInit;\r
-    }\r
-\r
-    /* Init the low level hardware */\r
-    huart->MspInitCallback(huart);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK */\r
-    HAL_UART_MspInit(huart);\r
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
-  }\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Set the UART Communication parameters */\r
-  if (UART_SetConfig(huart) == HAL_ERROR)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
-  {\r
-    UART_AdvFeatureConfig(huart);\r
-  }\r
-\r
-  /* In asynchronous mode, the following bits must be kept cleared:\r
-  - LINEN and CLKEN bits in the USART_CR2 register,\r
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/\r
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
-\r
-  __HAL_UART_ENABLE(huart);\r
-\r
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-/**\r
-  * @brief Initialize the half-duplex mode according to the specified\r
-  *        parameters in the UART_InitTypeDef and creates the associated handle.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r
-{\r
-  /* Check the UART handle allocation */\r
-  if (huart == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check UART instance */\r
-  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));\r
-\r
-  if (huart->gState == HAL_UART_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    huart->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    UART_InitCallbacksToDefault(huart);\r
-\r
-    if (huart->MspInitCallback == NULL)\r
-    {\r
-      huart->MspInitCallback = HAL_UART_MspInit;\r
-    }\r
-\r
-    /* Init the low level hardware */\r
-    huart->MspInitCallback(huart);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK */\r
-    HAL_UART_MspInit(huart);\r
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
-  }\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Set the UART Communication parameters */\r
-  if (UART_SetConfig(huart) == HAL_ERROR)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
-  {\r
-    UART_AdvFeatureConfig(huart);\r
-  }\r
-\r
-  /* In half-duplex mode, the following bits must be kept cleared:\r
-  - LINEN and CLKEN bits in the USART_CR2 register,\r
-  - SCEN and IREN bits in the USART_CR3 register.*/\r
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\r
-\r
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
-  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\r
-\r
-  __HAL_UART_ENABLE(huart);\r
-\r
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-\r
-/**\r
-  * @brief Initialize the LIN mode according to the specified\r
-  *        parameters in the UART_InitTypeDef and creates the associated handle.\r
-  * @param huart             UART handle.\r
-  * @param BreakDetectLength Specifies the LIN break detection length.\r
-  *        This parameter can be one of the following values:\r
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection\r
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r
-{\r
-  /* Check the UART handle allocation */\r
-  if (huart == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the LIN UART instance */\r
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\r
-  /* Check the Break detection length parameter */\r
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r
-\r
-  /* LIN mode limited to 16-bit oversampling only */\r
-  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-  /* LIN mode limited to 8-bit data length */\r
-  if (huart->Init.WordLength != UART_WORDLENGTH_8B)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if (huart->gState == HAL_UART_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    huart->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    UART_InitCallbacksToDefault(huart);\r
-\r
-    if (huart->MspInitCallback == NULL)\r
-    {\r
-      huart->MspInitCallback = HAL_UART_MspInit;\r
-    }\r
-\r
-    /* Init the low level hardware */\r
-    huart->MspInitCallback(huart);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK */\r
-    HAL_UART_MspInit(huart);\r
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
-  }\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Set the UART Communication parameters */\r
-  if (UART_SetConfig(huart) == HAL_ERROR)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
-  {\r
-    UART_AdvFeatureConfig(huart);\r
-  }\r
-\r
-  /* In LIN mode, the following bits must be kept cleared:\r
-  - LINEN and CLKEN bits in the USART_CR2 register,\r
-  - SCEN and IREN bits in the USART_CR3 register.*/\r
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\r
-\r
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
-  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\r
-\r
-  /* Set the USART LIN Break detection length. */\r
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);\r
-\r
-  __HAL_UART_ENABLE(huart);\r
-\r
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-\r
-/**\r
-  * @brief Initialize the multiprocessor mode according to the specified\r
-  *        parameters in the UART_InitTypeDef and initialize the associated handle.\r
-  * @param huart        UART handle.\r
-  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).\r
-  * @param WakeUpMethod Specifies the UART wakeup method.\r
-  *        This parameter can be one of the following values:\r
-  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection\r
-  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark\r
-  * @note  If the user resorts to idle line detection wake up, the Address parameter\r
-  *        is useless and ignored by the initialization function.\r
-  * @note  If the user resorts to address mark wake up, the address length detection\r
-  *        is configured by default to 4 bits only. For the UART to be able to\r
-  *        manage 6-, 7- or 8-bit long addresses detection, the API\r
-  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after\r
-  *        HAL_MultiProcessor_Init().\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r
-{\r
-  /* Check the UART handle allocation */\r
-  if (huart == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the wake up method parameter */\r
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r
-\r
-  if (huart->gState == HAL_UART_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    huart->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    UART_InitCallbacksToDefault(huart);\r
-\r
-    if (huart->MspInitCallback == NULL)\r
-    {\r
-      huart->MspInitCallback = HAL_UART_MspInit;\r
-    }\r
-\r
-    /* Init the low level hardware */\r
-    huart->MspInitCallback(huart);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK */\r
-    HAL_UART_MspInit(huart);\r
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
-  }\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Set the UART Communication parameters */\r
-  if (UART_SetConfig(huart) == HAL_ERROR)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
-  {\r
-    UART_AdvFeatureConfig(huart);\r
-  }\r
-\r
-  /* In multiprocessor mode, the following bits must be kept cleared:\r
-  - LINEN and CLKEN bits in the USART_CR2 register,\r
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */\r
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
-\r
-  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)\r
-  {\r
-    /* If address mark wake up method is chosen, set the USART address node */\r
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));\r
-  }\r
-\r
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */\r
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);\r
-\r
-  __HAL_UART_ENABLE(huart);\r
-\r
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-\r
-/**\r
-  * @brief DeInitialize the UART peripheral.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r
-{\r
-  /* Check the UART handle allocation */\r
-  if (huart == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the parameters */\r
-  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  huart->Instance->CR1 = 0x0U;\r
-  huart->Instance->CR2 = 0x0U;\r
-  huart->Instance->CR3 = 0x0U;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  if (huart->MspDeInitCallback == NULL)\r
-  {\r
-    huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
-  }\r
-  /* DeInit the low level hardware */\r
-  huart->MspDeInitCallback(huart);\r
-#else\r
-  /* DeInit the low level hardware */\r
-  HAL_UART_MspDeInit(huart);\r
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
-\r
-  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-  huart->gState = HAL_UART_STATE_RESET;\r
-  huart->RxState = HAL_UART_STATE_RESET;\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Initialize the UART MSP.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_MspInit can be implemented in the user file\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief DeInitialize the UART MSP.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_MspDeInit can be implemented in the user file\r
-   */\r
-}\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-/**\r
-  * @brief  Register a User UART Callback\r
-  *         To be used instead of the weak predefined callback\r
-  * @param  huart uart handle\r
-  * @param  CallbackID ID of the callback to be registered\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
-  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID\r
-  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
-  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
-  * @param  pCallback pointer to the Callback function\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,\r
-                                            pUART_CallbackTypeDef pCallback)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  if (pCallback == NULL)\r
-  {\r
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
-\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  __HAL_LOCK(huart);\r
-\r
-  if (huart->gState == HAL_UART_STATE_READY)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
-        huart->TxHalfCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_TX_COMPLETE_CB_ID :\r
-        huart->TxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
-        huart->RxHalfCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_RX_COMPLETE_CB_ID :\r
-        huart->RxCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_ERROR_CB_ID :\r
-        huart->ErrorCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_ABORT_COMPLETE_CB_ID :\r
-        huart->AbortCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
-        huart->AbortTransmitCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
-        huart->AbortReceiveCpltCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_WAKEUP_CB_ID :\r
-        huart->WakeupCallback = pCallback;\r
-        break;\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-      case HAL_UART_RX_FIFO_FULL_CB_ID :\r
-        huart->RxFifoFullCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_TX_FIFO_EMPTY_CB_ID :\r
-        huart->TxFifoEmptyCallback = pCallback;\r
-        break;\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-      case HAL_UART_MSPINIT_CB_ID :\r
-        huart->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_MSPDEINIT_CB_ID :\r
-        huart->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
-\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (huart->gState == HAL_UART_STATE_RESET)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_UART_MSPINIT_CB_ID :\r
-        huart->MspInitCallback = pCallback;\r
-        break;\r
-\r
-      case HAL_UART_MSPDEINIT_CB_ID :\r
-        huart->MspDeInitCallback = pCallback;\r
-        break;\r
-\r
-      default :\r
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
-\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
-\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief  Unregister an UART Callback\r
-  *         UART callaback is redirected to the weak predefined callback\r
-  * @param  huart uart handle\r
-  * @param  CallbackID ID of the callback to be unregistered\r
-  *         This parameter can be one of the following values:\r
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
-  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID\r
-  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
-  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-\r
-  __HAL_LOCK(huart);\r
-\r
-  if (HAL_UART_STATE_READY == huart->gState)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
-        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */\r
-        break;\r
-\r
-      case HAL_UART_TX_COMPLETE_CB_ID :\r
-        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */\r
-        break;\r
-\r
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
-        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */\r
-        break;\r
-\r
-      case HAL_UART_RX_COMPLETE_CB_ID :\r
-        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */\r
-        break;\r
-\r
-      case HAL_UART_ERROR_CB_ID :\r
-        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */\r
-        break;\r
-\r
-      case HAL_UART_ABORT_COMPLETE_CB_ID :\r
-        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */\r
-        break;\r
-\r
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
-        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
-        break;\r
-\r
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
-        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */\r
-        break;\r
-\r
-      case HAL_UART_WAKEUP_CB_ID :\r
-        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback            */\r
-        break;\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-      case HAL_UART_RX_FIFO_FULL_CB_ID :\r
-        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */\r
-        break;\r
-\r
-      case HAL_UART_TX_FIFO_EMPTY_CB_ID :\r
-        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */\r
-        break;\r
-\r
-#endif /* USART_CR1_FIFOEN */\r
-      case HAL_UART_MSPINIT_CB_ID :\r
-        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */\r
-        break;\r
-\r
-      case HAL_UART_MSPDEINIT_CB_ID :\r
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */\r
-        break;\r
-\r
-      default :\r
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
-\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else if (HAL_UART_STATE_RESET == huart->gState)\r
-  {\r
-    switch (CallbackID)\r
-    {\r
-      case HAL_UART_MSPINIT_CB_ID :\r
-        huart->MspInitCallback = HAL_UART_MspInit;\r
-        break;\r
-\r
-      case HAL_UART_MSPDEINIT_CB_ID :\r
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
-        break;\r
-\r
-      default :\r
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
-\r
-        status =  HAL_ERROR;\r
-        break;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
-\r
-    status =  HAL_ERROR;\r
-  }\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return status;\r
-}\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions\r
-  * @brief UART Transmit/Receive functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### IO operation functions #####\r
- ===============================================================================\r
-    This subsection provides a set of functions allowing to manage the UART asynchronous\r
-    and Half duplex data transfers.\r
-\r
-    (#) There are two mode of transfer:\r
-       (+) Blocking mode: The communication is performed in polling mode.\r
-           The HAL status of all data processing is returned by the same function\r
-           after finishing transfer.\r
-       (+) Non-Blocking mode: The communication is performed using Interrupts\r
-           or DMA, These API's return the HAL status.\r
-           The end of the data processing will be indicated through the\r
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\r
-           using DMA mode.\r
-           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\r
-           will be executed respectively at the end of the transmit or Receive process\r
-           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected\r
-\r
-    (#) Blocking mode API's are :\r
-        (+) HAL_UART_Transmit()\r
-        (+) HAL_UART_Receive()\r
-\r
-    (#) Non-Blocking mode API's with Interrupt are :\r
-        (+) HAL_UART_Transmit_IT()\r
-        (+) HAL_UART_Receive_IT()\r
-        (+) HAL_UART_IRQHandler()\r
-\r
-    (#) Non-Blocking mode API's with DMA are :\r
-        (+) HAL_UART_Transmit_DMA()\r
-        (+) HAL_UART_Receive_DMA()\r
-        (+) HAL_UART_DMAPause()\r
-        (+) HAL_UART_DMAResume()\r
-        (+) HAL_UART_DMAStop()\r
-\r
-    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r
-        (+) HAL_UART_TxHalfCpltCallback()\r
-        (+) HAL_UART_TxCpltCallback()\r
-        (+) HAL_UART_RxHalfCpltCallback()\r
-        (+) HAL_UART_RxCpltCallback()\r
-        (+) HAL_UART_ErrorCallback()\r
-\r
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :\r
-        (+) HAL_UART_Abort()\r
-        (+) HAL_UART_AbortTransmit()\r
-        (+) HAL_UART_AbortReceive()\r
-        (+) HAL_UART_Abort_IT()\r
-        (+) HAL_UART_AbortTransmit_IT()\r
-        (+) HAL_UART_AbortReceive_IT()\r
-\r
-    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:\r
-        (+) HAL_UART_AbortCpltCallback()\r
-        (+) HAL_UART_AbortTransmitCpltCallback()\r
-        (+) HAL_UART_AbortReceiveCpltCallback()\r
-\r
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.\r
-        Errors are handled as follows :\r
-       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is\r
-           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .\r
-           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,\r
-           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.\r
-           If user wants to abort it, Abort services should be called by user.\r
-       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.\r
-           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.\r
-           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.\r
-\r
-    -@- In the Half duplex communication, it is forbidden to run the transmit\r
-        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Send an amount of data in blocking mode.\r
-  * @note When FIFO mode is enabled, writing a data in the TDR register adds one\r
-  *       data to the TXFIFO. Write operations to the TDR register are performed\r
-  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and\r
-  *       TXE are mapped on the same bit-field.\r
-  * @param huart   UART handle.\r
-  * @param pData   Pointer to data buffer.\r
-  * @param Size    Amount of data to be sent.\r
-  * @param Timeout Timeout duration.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint8_t  *pdata8bits;\r
-  uint16_t *pdata16bits;\r
-  uint32_t tickstart;\r
-\r
-  /* Check that a Tx process is not already ongoing */\r
-  if (huart->gState == HAL_UART_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    __HAL_LOCK(huart);\r
-\r
-    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-    huart->gState = HAL_UART_STATE_BUSY_TX;\r
-\r
-    /* Init tickstart for timeout managment*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    huart->TxXferSize  = Size;\r
-    huart->TxXferCount = Size;\r
-\r
-    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */\r
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-    {\r
-      pdata8bits  = NULL;\r
-      pdata16bits = (uint16_t *) pData;\r
-    }\r
-    else\r
-    {\r
-      pdata8bits  = pData;\r
-      pdata16bits = NULL;\r
-    }\r
-\r
-    while (huart->TxXferCount > 0U)\r
-    {\r
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
-      {\r
-        return HAL_TIMEOUT;\r
-      }\r
-      if (pdata8bits == NULL)\r
-      {\r
-        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);\r
-        pdata16bits++;\r
-      }\r
-      else\r
-      {\r
-        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);\r
-        pdata8bits++;\r
-      }\r
-      huart->TxXferCount--;\r
-    }\r
-\r
-    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-\r
-    /* At end of Tx process, restore huart->gState to Ready */\r
-    huart->gState = HAL_UART_STATE_READY;\r
-\r
-    __HAL_UNLOCK(huart);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Receive an amount of data in blocking mode.\r
-  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO\r
-  *       is not empty. Read operations from the RDR register are performed when\r
-  *       RXFNE flag is set. From hardware perspective, RXFNE flag and\r
-  *       RXNE are mapped on the same bit-field.\r
-  * @param huart   UART handle.\r
-  * @param pData   Pointer to data buffer.\r
-  * @param Size    Amount of data to be received.\r
-  * @param Timeout Timeout duration.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
-  uint8_t  *pdata8bits;\r
-  uint16_t *pdata16bits;\r
-  uint16_t uhMask;\r
-  uint32_t tickstart;\r
-\r
-  /* Check that a Rx process is not already ongoing */\r
-  if (huart->RxState == HAL_UART_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      return  HAL_ERROR;\r
-    }\r
-\r
-    __HAL_LOCK(huart);\r
-\r
-    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-    huart->RxState = HAL_UART_STATE_BUSY_RX;\r
-\r
-    /* Init tickstart for timeout managment*/\r
-    tickstart = HAL_GetTick();\r
-\r
-    huart->RxXferSize  = Size;\r
-    huart->RxXferCount = Size;\r
-\r
-    /* Computation of UART mask to apply to RDR register */\r
-    UART_MASK_COMPUTATION(huart);\r
-    uhMask = huart->Mask;\r
-\r
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */\r
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-    {\r
-      pdata8bits  = NULL;\r
-      pdata16bits = (uint16_t *) pData;\r
-    }\r
-    else\r
-    {\r
-      pdata8bits  = pData;\r
-      pdata16bits = NULL;\r
-    }\r
-\r
-    /* as long as data have to be received */\r
-    while (huart->RxXferCount > 0U)\r
-    {\r
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
-      {\r
-        return HAL_TIMEOUT;\r
-      }\r
-      if (pdata8bits == NULL)\r
-      {\r
-        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);\r
-        pdata16bits++;\r
-      }\r
-      else\r
-      {\r
-        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r
-        pdata8bits++;\r
-      }\r
-      huart->RxXferCount--;\r
-    }\r
-\r
-    /* At end of Rx process, restore huart->RxState to Ready */\r
-    huart->RxState = HAL_UART_STATE_READY;\r
-\r
-    __HAL_UNLOCK(huart);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Send an amount of data in interrupt mode.\r
-  * @param huart UART handle.\r
-  * @param pData Pointer to data buffer.\r
-  * @param Size  Amount of data to be sent.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
-{\r
-  /* Check that a Tx process is not already ongoing */\r
-  if (huart->gState == HAL_UART_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    __HAL_LOCK(huart);\r
-\r
-    huart->pTxBuffPtr  = pData;\r
-    huart->TxXferSize  = Size;\r
-    huart->TxXferCount = Size;\r
-    huart->TxISR       = NULL;\r
-\r
-    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-    huart->gState = HAL_UART_STATE_BUSY_TX;\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-    /* Configure Tx interrupt processing */\r
-    if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
-    {\r
-      /* Set the Tx ISR function pointer according to the data word length */\r
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-      {\r
-        huart->TxISR = UART_TxISR_16BIT_FIFOEN;\r
-      }\r
-      else\r
-      {\r
-        huart->TxISR = UART_TxISR_8BIT_FIFOEN;\r
-      }\r
-\r
-      __HAL_UNLOCK(huart);\r
-\r
-      /* Enable the TX FIFO threshold interrupt */\r
-      SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
-    }\r
-    else\r
-    {\r
-      /* Set the Tx ISR function pointer according to the data word length */\r
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-      {\r
-        huart->TxISR = UART_TxISR_16BIT;\r
-      }\r
-      else\r
-      {\r
-        huart->TxISR = UART_TxISR_8BIT;\r
-      }\r
-\r
-      __HAL_UNLOCK(huart);\r
-\r
-      /* Enable the Transmit Data Register Empty interrupt */\r
-      SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
-    }\r
-#else\r
-    /* Set the Tx ISR function pointer according to the data word length */\r
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-    {\r
-      huart->TxISR = UART_TxISR_16BIT;\r
-    }\r
-    else\r
-    {\r
-      huart->TxISR = UART_TxISR_8BIT;\r
-    }\r
-\r
-    __HAL_UNLOCK(huart);\r
-\r
-    /* Enable the Transmit Data Register Empty interrupt */\r
-    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Receive an amount of data in interrupt mode.\r
-  * @param huart UART handle.\r
-  * @param pData Pointer to data buffer.\r
-  * @param Size  Amount of data to be received.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
-{\r
-  /* Check that a Rx process is not already ongoing */\r
-  if (huart->RxState == HAL_UART_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    __HAL_LOCK(huart);\r
-\r
-    huart->pRxBuffPtr  = pData;\r
-    huart->RxXferSize  = Size;\r
-    huart->RxXferCount = Size;\r
-    huart->RxISR       = NULL;\r
-\r
-    /* Computation of UART mask to apply to RDR register */\r
-    UART_MASK_COMPUTATION(huart);\r
-\r
-    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-    huart->RxState = HAL_UART_STATE_BUSY_RX;\r
-\r
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-    /* Configure Rx interrupt processing*/\r
-    if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))\r
-    {\r
-      /* Set the Rx ISR function pointer according to the data word length */\r
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-      {\r
-        huart->RxISR = UART_RxISR_16BIT_FIFOEN;\r
-      }\r
-      else\r
-      {\r
-        huart->RxISR = UART_RxISR_8BIT_FIFOEN;\r
-      }\r
-\r
-      __HAL_UNLOCK(huart);\r
-\r
-      /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */\r
-      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
-      SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
-    }\r
-    else\r
-    {\r
-      /* Set the Rx ISR function pointer according to the data word length */\r
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-      {\r
-        huart->RxISR = UART_RxISR_16BIT;\r
-      }\r
-      else\r
-      {\r
-        huart->RxISR = UART_RxISR_8BIT;\r
-      }\r
-\r
-      __HAL_UNLOCK(huart);\r
-\r
-      /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */\r
-      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);\r
-    }\r
-#else\r
-    /* Set the Rx ISR function pointer according to the data word length */\r
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
-    {\r
-      huart->RxISR = UART_RxISR_16BIT;\r
-    }\r
-    else\r
-    {\r
-      huart->RxISR = UART_RxISR_8BIT;\r
-    }\r
-\r
-    __HAL_UNLOCK(huart);\r
-\r
-    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */\r
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Send an amount of data in DMA mode.\r
-  * @param huart UART handle.\r
-  * @param pData Pointer to data buffer.\r
-  * @param Size  Amount of data to be sent.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
-{\r
-  /* Check that a Tx process is not already ongoing */\r
-  if (huart->gState == HAL_UART_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    __HAL_LOCK(huart);\r
-\r
-    huart->pTxBuffPtr  = pData;\r
-    huart->TxXferSize  = Size;\r
-    huart->TxXferCount = Size;\r
-\r
-    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-    huart->gState = HAL_UART_STATE_BUSY_TX;\r
-\r
-    if (huart->hdmatx != NULL)\r
-    {\r
-      /* Set the UART DMA transfer complete callback */\r
-      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r
-\r
-      /* Set the UART DMA Half transfer complete callback */\r
-      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      huart->hdmatx->XferErrorCallback = UART_DMAError;\r
-\r
-      /* Set the DMA abort callback */\r
-      huart->hdmatx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the UART transmit DMA channel */\r
-      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)\r
-      {\r
-        /* Set error code to DMA */\r
-        huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-        __HAL_UNLOCK(huart);\r
-\r
-        /* Restore huart->gState to ready */\r
-        huart->gState = HAL_UART_STATE_READY;\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-    /* Clear the TC flag in the ICR register */\r
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);\r
-\r
-    __HAL_UNLOCK(huart);\r
-\r
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
-    in the UART CR3 register */\r
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Receive an amount of data in DMA mode.\r
-  * @note   When the UART parity is enabled (PCE = 1), the received data contain\r
-  *         the parity bit (MSB position).\r
-  * @param huart UART handle.\r
-  * @param pData Pointer to data buffer.\r
-  * @param Size  Amount of data to be received.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
-{\r
-  /* Check that a Rx process is not already ongoing */\r
-  if (huart->RxState == HAL_UART_STATE_READY)\r
-  {\r
-    if ((pData == NULL) || (Size == 0U))\r
-    {\r
-      return HAL_ERROR;\r
-    }\r
-\r
-    __HAL_LOCK(huart);\r
-\r
-    huart->pRxBuffPtr = pData;\r
-    huart->RxXferSize = Size;\r
-\r
-    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-    huart->RxState = HAL_UART_STATE_BUSY_RX;\r
-\r
-    if (huart->hdmarx != NULL)\r
-    {\r
-      /* Set the UART DMA transfer complete callback */\r
-      huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r
-\r
-      /* Set the UART DMA Half transfer complete callback */\r
-      huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r
-\r
-      /* Set the DMA error callback */\r
-      huart->hdmarx->XferErrorCallback = UART_DMAError;\r
-\r
-      /* Set the DMA abort callback */\r
-      huart->hdmarx->XferAbortCallback = NULL;\r
-\r
-      /* Enable the DMA channel */\r
-      if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)\r
-      {\r
-        /* Set error code to DMA */\r
-        huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-        __HAL_UNLOCK(huart);\r
-\r
-        /* Restore huart->gState to ready */\r
-        huart->gState = HAL_UART_STATE_READY;\r
-\r
-        return HAL_ERROR;\r
-      }\r
-    }\r
-    __HAL_UNLOCK(huart);\r
-\r
-    /* Enable the UART Parity Error Interrupt */\r
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
-\r
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
-    in the UART CR3 register */\r
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-    return HAL_OK;\r
-  }\r
-  else\r
-  {\r
-    return HAL_BUSY;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Pause the DMA Transfer.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r
-{\r
-  const HAL_UART_StateTypeDef gstate = huart->gState;\r
-  const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
-\r
-  __HAL_LOCK(huart);\r
-\r
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
-      (gstate == HAL_UART_STATE_BUSY_TX))\r
-  {\r
-    /* Disable the UART DMA Tx request */\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-  }\r
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
-      (rxstate == HAL_UART_STATE_BUSY_RX))\r
-  {\r
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-    /* Disable the UART DMA Rx request */\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-  }\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Resume the DMA Transfer.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r
-{\r
-  __HAL_LOCK(huart);\r
-\r
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
-  {\r
-    /* Enable the UART DMA Tx request */\r
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-  }\r
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
-  {\r
-    /* Clear the Overrun flag before resuming the Rx transfer */\r
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);\r
-\r
-    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-    /* Enable the UART DMA Rx request */\r
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-  }\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Stop the DMA Transfer.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r
-{\r
-  /* The Lock is not implemented on this API to allow the user application\r
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /\r
-     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:\r
-     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r
-     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r
-     the stream and the corresponding call back is executed. */\r
-\r
-  const HAL_UART_StateTypeDef gstate = huart->gState;\r
-  const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
-\r
-  /* Stop UART DMA Tx request if ongoing */\r
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
-      (gstate == HAL_UART_STATE_BUSY_TX))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-\r
-    /* Abort the UART DMA Tx channel */\r
-    if (huart->hdmatx != NULL)\r
-    {\r
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
-      {\r
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
-        {\r
-          /* Set error code to DMA */\r
-          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-\r
-    UART_EndTxTransfer(huart);\r
-  }\r
-\r
-  /* Stop UART DMA Rx request if ongoing */\r
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
-      (rxstate == HAL_UART_STATE_BUSY_RX))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-    /* Abort the UART DMA Rx channel */\r
-    if (huart->hdmarx != NULL)\r
-    {\r
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
-      {\r
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
-        {\r
-          /* Set error code to DMA */\r
-          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-\r
-    UART_EndRxTransfer(huart);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing transfers (blocking mode).\r
-  * @param  huart UART handle.\r
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable UART Interrupts (Tx and Rx)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)\r
-{\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);\r
-#else\r
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Disable the UART DMA Tx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-\r
-    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
-    if (huart->hdmatx != NULL)\r
-    {\r
-      /* Set the UART DMA Abort callback to Null.\r
-         No call back execution at end of DMA abort procedure */\r
-      huart->hdmatx->XferAbortCallback = NULL;\r
-\r
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
-      {\r
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
-        {\r
-          /* Set error code to DMA */\r
-          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Disable the UART DMA Rx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
-    if (huart->hdmarx != NULL)\r
-    {\r
-      /* Set the UART DMA Abort callback to Null.\r
-         No call back execution at end of DMA abort procedure */\r
-      huart->hdmarx->XferAbortCallback = NULL;\r
-\r
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
-      {\r
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
-        {\r
-          /* Set error code to DMA */\r
-          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Reset Tx and Rx transfer counters */\r
-  huart->TxXferCount = 0U;\r
-  huart->RxXferCount = 0U;\r
-\r
-  /* Clear the Error flags in the ICR register */\r
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Flush the whole TX FIFO (if needed) */\r
-  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
-  {\r
-    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
-  }\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Discard the received data */\r
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-\r
-  /* Restore huart->gState and huart->RxState to Ready */\r
-  huart->gState  = HAL_UART_STATE_READY;\r
-  huart->RxState = HAL_UART_STATE_READY;\r
-\r
-  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing Transmit transfer (blocking mode).\r
-  * @param  huart UART handle.\r
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable UART Interrupts (Tx)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)\r
-{\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Disable TCIE, TXEIE and TXFTIE interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
-#else\r
-  /* Disable TXEIE and TCIE interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Disable the UART DMA Tx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-\r
-    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
-    if (huart->hdmatx != NULL)\r
-    {\r
-      /* Set the UART DMA Abort callback to Null.\r
-         No call back execution at end of DMA abort procedure */\r
-      huart->hdmatx->XferAbortCallback = NULL;\r
-\r
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
-      {\r
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
-        {\r
-          /* Set error code to DMA */\r
-          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Reset Tx transfer counter */\r
-  huart->TxXferCount = 0U;\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Flush the whole TX FIFO (if needed) */\r
-  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
-  {\r
-    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
-  }\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Restore huart->gState to Ready */\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing Receive transfer (blocking mode).\r
-  * @param  huart UART handle.\r
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable UART Interrupts (Rx)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)\r
-{\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);\r
-#else\r
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Disable the UART DMA Rx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
-    if (huart->hdmarx != NULL)\r
-    {\r
-      /* Set the UART DMA Abort callback to Null.\r
-         No call back execution at end of DMA abort procedure */\r
-      huart->hdmarx->XferAbortCallback = NULL;\r
-\r
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
-      {\r
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
-        {\r
-          /* Set error code to DMA */\r
-          huart->ErrorCode = HAL_UART_ERROR_DMA;\r
-\r
-          return HAL_TIMEOUT;\r
-        }\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Reset Rx transfer counter */\r
-  huart->RxXferCount = 0U;\r
-\r
-  /* Clear the Error flags in the ICR register */\r
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-  /* Discard the received data */\r
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-\r
-  /* Restore huart->RxState to Ready */\r
-  huart->RxState = HAL_UART_STATE_READY;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing transfers (Interrupt mode).\r
-  * @param  huart UART handle.\r
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable UART Interrupts (Tx and Rx)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  *           - At abort completion, call user abort complete callback\r
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)\r
-{\r
-  uint32_t abortcplt = 1U;\r
-\r
-  /* Disable interrupts */\r
-#if defined(USART_CR1_FIFOEN)\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));\r
-#else\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised\r
-     before any call to DMA Abort functions */\r
-  /* DMA Tx Handle is valid */\r
-  if (huart->hdmatx != NULL)\r
-  {\r
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r
-       Otherwise, set it to NULL */\r
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
-    {\r
-      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;\r
-    }\r
-    else\r
-    {\r
-      huart->hdmatx->XferAbortCallback = NULL;\r
-    }\r
-  }\r
-  /* DMA Rx Handle is valid */\r
-  if (huart->hdmarx != NULL)\r
-  {\r
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r
-       Otherwise, set it to NULL */\r
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
-    {\r
-      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;\r
-    }\r
-    else\r
-    {\r
-      huart->hdmarx->XferAbortCallback = NULL;\r
-    }\r
-  }\r
-\r
-  /* Disable the UART DMA Tx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
-  {\r
-    /* Disable DMA Tx at UART level */\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-\r
-    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
-    if (huart->hdmatx != NULL)\r
-    {\r
-      /* UART Tx DMA Abort callback has already been initialised :\r
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
-\r
-      /* Abort DMA TX */\r
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
-      {\r
-        huart->hdmatx->XferAbortCallback = NULL;\r
-      }\r
-      else\r
-      {\r
-        abortcplt = 0U;\r
-      }\r
-    }\r
-  }\r
-\r
-  /* Disable the UART DMA Rx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
-    if (huart->hdmarx != NULL)\r
-    {\r
-      /* UART Rx DMA Abort callback has already been initialised :\r
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
-\r
-      /* Abort DMA RX */\r
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
-      {\r
-        huart->hdmarx->XferAbortCallback = NULL;\r
-        abortcplt = 1U;\r
-      }\r
-      else\r
-      {\r
-        abortcplt = 0U;\r
-      }\r
-    }\r
-  }\r
-\r
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */\r
-  if (abortcplt == 1U)\r
-  {\r
-    /* Reset Tx and Rx transfer counters */\r
-    huart->TxXferCount = 0U;\r
-    huart->RxXferCount = 0U;\r
-\r
-    /* Clear ISR function pointers */\r
-    huart->RxISR = NULL;\r
-    huart->TxISR = NULL;\r
-\r
-    /* Reset errorCode */\r
-    huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-\r
-    /* Clear the Error flags in the ICR register */\r
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-    /* Flush the whole TX FIFO (if needed) */\r
-    if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
-    {\r
-      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
-    }\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-    /* Discard the received data */\r
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-\r
-    /* Restore huart->gState and huart->RxState to Ready */\r
-    huart->gState  = HAL_UART_STATE_READY;\r
-    huart->RxState = HAL_UART_STATE_READY;\r
-\r
-    /* As no DMA to be aborted, call directly user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    /* Call registered Abort complete callback */\r
-    huart->AbortCpltCallback(huart);\r
-#else\r
-    /* Call legacy weak Abort complete callback */\r
-    HAL_UART_AbortCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).\r
-  * @param  huart UART handle.\r
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable UART Interrupts (Tx)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  *           - At abort completion, call user abort complete callback\r
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)\r
-{\r
-  /* Disable interrupts */\r
-#if defined(USART_CR1_FIFOEN)\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
-#else\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Disable the UART DMA Tx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-\r
-    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
-    if (huart->hdmatx != NULL)\r
-    {\r
-      /* Set the UART DMA Abort callback :\r
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
-      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;\r
-\r
-      /* Abort DMA TX */\r
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
-      {\r
-        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */\r
-        huart->hdmatx->XferAbortCallback(huart->hdmatx);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Reset Tx transfer counter */\r
-      huart->TxXferCount = 0U;\r
-\r
-      /* Clear TxISR function pointers */\r
-      huart->TxISR = NULL;\r
-\r
-      /* Restore huart->gState to Ready */\r
-      huart->gState = HAL_UART_STATE_READY;\r
-\r
-      /* As no DMA to be aborted, call directly user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-      /* Call registered Abort Transmit Complete Callback */\r
-      huart->AbortTransmitCpltCallback(huart);\r
-#else\r
-      /* Call legacy weak Abort Transmit Complete Callback */\r
-      HAL_UART_AbortTransmitCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Reset Tx transfer counter */\r
-    huart->TxXferCount = 0U;\r
-\r
-    /* Clear TxISR function pointers */\r
-    huart->TxISR = NULL;\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-    /* Flush the whole TX FIFO (if needed) */\r
-    if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
-    {\r
-      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
-    }\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-    /* Restore huart->gState to Ready */\r
-    huart->gState = HAL_UART_STATE_READY;\r
-\r
-    /* As no DMA to be aborted, call directly user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    /* Call registered Abort Transmit Complete Callback */\r
-    huart->AbortTransmitCpltCallback(huart);\r
-#else\r
-    /* Call legacy weak Abort Transmit Complete Callback */\r
-    HAL_UART_AbortTransmitCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).\r
-  * @param  huart UART handle.\r
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
-  *         This procedure performs following operations :\r
-  *           - Disable UART Interrupts (Rx)\r
-  *           - Disable the DMA transfer in the peripheral register (if enabled)\r
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
-  *           - Set handle State to READY\r
-  *           - At abort completion, call user abort complete callback\r
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)\r
-{\r
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
-#if defined(USART_CR1_FIFOEN)\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
-#else\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Disable the UART DMA Rx request if enabled */\r
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
-  {\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
-    if (huart->hdmarx != NULL)\r
-    {\r
-      /* Set the UART DMA Abort callback :\r
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
-      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;\r
-\r
-      /* Abort DMA RX */\r
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
-      {\r
-        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
-        huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /* Reset Rx transfer counter */\r
-      huart->RxXferCount = 0U;\r
-\r
-      /* Clear RxISR function pointer */\r
-      huart->pRxBuffPtr = NULL;\r
-\r
-      /* Clear the Error flags in the ICR register */\r
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-      /* Discard the received data */\r
-      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-\r
-      /* Restore huart->RxState to Ready */\r
-      huart->RxState = HAL_UART_STATE_READY;\r
-\r
-      /* As no DMA to be aborted, call directly user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-      /* Call registered Abort Receive Complete Callback */\r
-      huart->AbortReceiveCpltCallback(huart);\r
-#else\r
-      /* Call legacy weak Abort Receive Complete Callback */\r
-      HAL_UART_AbortReceiveCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Reset Rx transfer counter */\r
-    huart->RxXferCount = 0U;\r
-\r
-    /* Clear RxISR function pointer */\r
-    huart->pRxBuffPtr = NULL;\r
-\r
-    /* Clear the Error flags in the ICR register */\r
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-    /* Restore huart->RxState to Ready */\r
-    huart->RxState = HAL_UART_STATE_READY;\r
-\r
-    /* As no DMA to be aborted, call directly user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    /* Call registered Abort Receive Complete Callback */\r
-    huart->AbortReceiveCpltCallback(huart);\r
-#else\r
-    /* Call legacy weak Abort Receive Complete Callback */\r
-    HAL_UART_AbortReceiveCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Handle UART interrupt request.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r
-{\r
-  uint32_t isrflags   = READ_REG(huart->Instance->ISR);\r
-  uint32_t cr1its     = READ_REG(huart->Instance->CR1);\r
-  uint32_t cr3its     = READ_REG(huart->Instance->CR3);\r
-\r
-  uint32_t errorflags;\r
-  uint32_t errorcode;\r
-\r
-  /* If no error occurs */\r
-  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r
-  if (errorflags == 0U)\r
-  {\r
-    /* UART in mode Receiver ---------------------------------------------------*/\r
-#if defined(USART_CR1_FIFOEN)\r
-    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
-        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
-            || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
-#else\r
-    if (((isrflags & USART_ISR_RXNE) != 0U)\r
-        && ((cr1its & USART_CR1_RXNEIE) != 0U))\r
-#endif /* USART_CR1_FIFOEN */\r
-    {\r
-      if (huart->RxISR != NULL)\r
-      {\r
-        huart->RxISR(huart);\r
-      }\r
-      return;\r
-    }\r
-  }\r
-\r
-  /* If some errors occur */\r
-#if defined(USART_CR1_FIFOEN)\r
-  if ((errorflags != 0U)\r
-      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)\r
-           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))\r
-#else\r
-  if ((errorflags != 0U)\r
-      && (((cr3its & USART_CR3_EIE) != 0U)\r
-          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))\r
-#endif /* USART_CR1_FIFOEN */\r
-  {\r
-    /* UART parity error interrupt occurred -------------------------------------*/\r
-    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))\r
-    {\r
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);\r
-\r
-      huart->ErrorCode |= HAL_UART_ERROR_PE;\r
-    }\r
-\r
-    /* UART frame error interrupt occurred --------------------------------------*/\r
-    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
-    {\r
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);\r
-\r
-      huart->ErrorCode |= HAL_UART_ERROR_FE;\r
-    }\r
-\r
-    /* UART noise error interrupt occurred --------------------------------------*/\r
-    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
-    {\r
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);\r
-\r
-      huart->ErrorCode |= HAL_UART_ERROR_NE;\r
-    }\r
-\r
-    /* UART Over-Run interrupt occurred -----------------------------------------*/\r
-#if defined(USART_CR1_FIFOEN)\r
-    if (((isrflags & USART_ISR_ORE) != 0U)\r
-        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||\r
-            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))\r
-#else\r
-    if (((isrflags & USART_ISR_ORE) != 0U)\r
-        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||\r
-            ((cr3its & USART_CR3_EIE) != 0U)))\r
-#endif /* USART_CR1_FIFOEN */\r
-    {\r
-      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);\r
-\r
-      huart->ErrorCode |= HAL_UART_ERROR_ORE;\r
-    }\r
-\r
-    /* Call UART Error Call back function if need be --------------------------*/\r
-    if (huart->ErrorCode != HAL_UART_ERROR_NONE)\r
-    {\r
-      /* UART in mode Receiver ---------------------------------------------------*/\r
-#if defined(USART_CR1_FIFOEN)\r
-      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
-          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
-              || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
-#else\r
-      if (((isrflags & USART_ISR_RXNE) != 0U)\r
-          && ((cr1its & USART_CR1_RXNEIE) != 0U))\r
-#endif /* USART_CR1_FIFOEN */\r
-      {\r
-        if (huart->RxISR != NULL)\r
-        {\r
-          huart->RxISR(huart);\r
-        }\r
-      }\r
-\r
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
-         consider error as blocking */\r
-      errorcode = huart->ErrorCode;\r
-      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||\r
-          ((errorcode & HAL_UART_ERROR_ORE) != 0U))\r
-      {\r
-        /* Blocking error : transfer is aborted\r
-           Set the UART state ready to be able to start again the process,\r
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
-        UART_EndRxTransfer(huart);\r
-\r
-        /* Disable the UART DMA Rx request if enabled */\r
-        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
-        {\r
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-          /* Abort the UART DMA Rx channel */\r
-          if (huart->hdmarx != NULL)\r
-          {\r
-            /* Set the UART DMA Abort callback :\r
-               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\r
-            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\r
-\r
-            /* Abort DMA RX */\r
-            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
-            {\r
-              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
-              huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
-            }\r
-          }\r
-          else\r
-          {\r
-            /* Call user error callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-            /*Call registered error callback*/\r
-            huart->ErrorCallback(huart);\r
-#else\r
-            /*Call legacy weak error callback*/\r
-            HAL_UART_ErrorCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-\r
-          }\r
-        }\r
-        else\r
-        {\r
-          /* Call user error callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-          /*Call registered error callback*/\r
-          huart->ErrorCallback(huart);\r
-#else\r
-          /*Call legacy weak error callback*/\r
-          HAL_UART_ErrorCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-        }\r
-      }\r
-      else\r
-      {\r
-        /* Non Blocking error : transfer could go on.\r
-           Error is notified to user through user error callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-        /*Call registered error callback*/\r
-        huart->ErrorCallback(huart);\r
-#else\r
-        /*Call legacy weak error callback*/\r
-        HAL_UART_ErrorCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-        huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-      }\r
-    }\r
-    return;\r
-\r
-  } /* End if some error occurs */\r
-\r
-  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/\r
-  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))\r
-  {\r
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);\r
-\r
-    /* UART Rx state is not reset as a reception process might be ongoing.\r
-       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    /* Call registered Wakeup Callback */\r
-    huart->WakeupCallback(huart);\r
-#else\r
-    /* Call legacy weak Wakeup Callback */\r
-    HAL_UARTEx_WakeupCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-    return;\r
-  }\r
-\r
-  /* UART in mode Transmitter ------------------------------------------------*/\r
-#if defined(USART_CR1_FIFOEN)\r
-  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)\r
-      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)\r
-          || ((cr3its & USART_CR3_TXFTIE) != 0U)))\r
-#else\r
-  if (((isrflags & USART_ISR_TXE) != 0U)\r
-      && ((cr1its & USART_CR1_TXEIE) != 0U))\r
-#endif /* USART_CR1_FIFOEN */\r
-  {\r
-    if (huart->TxISR != NULL)\r
-    {\r
-      huart->TxISR(huart);\r
-    }\r
-    return;\r
-  }\r
-\r
-  /* UART in mode Transmitter (transmission end) -----------------------------*/\r
-  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))\r
-  {\r
-    UART_EndTransmit_IT(huart);\r
-    return;\r
-  }\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* UART TX Fifo Empty occurred ----------------------------------------------*/\r
-  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))\r
-  {\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    /* Call registered Tx Fifo Empty Callback */\r
-    huart->TxFifoEmptyCallback(huart);\r
-#else\r
-    /* Call legacy weak Tx Fifo Empty Callback */\r
-    HAL_UARTEx_TxFifoEmptyCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-    return;\r
-  }\r
-\r
-  /* UART RX Fifo Full occurred ----------------------------------------------*/\r
-  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))\r
-  {\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    /* Call registered Rx Fifo Full Callback */\r
-    huart->RxFifoFullCallback(huart);\r
-#else\r
-    /* Call legacy weak Rx Fifo Full Callback */\r
-    HAL_UARTEx_RxFifoFullCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-    return;\r
-  }\r
-#endif /* USART_CR1_FIFOEN */\r
-}\r
-\r
-/**\r
-  * @brief Tx Transfer completed callback.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_TxCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Tx Half Transfer completed callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Rx Transfer completed callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_RxCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Rx Half Transfer completed callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE: This function should not be modified, when the callback is needed,\r
-           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  UART error callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_ErrorCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  UART Abort Complete callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_AbortCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  UART Abort Complete callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  UART Abort Receive Complete callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\r
-  *  @brief   UART control functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Peripheral Control functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to control the UART.\r
-     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r
-     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode\r
-     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode\r
-     (+) UART_SetConfig() API configures the UART peripheral\r
-     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features\r
-     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization\r
-     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter\r
-     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver\r
-     (+) HAL_LIN_SendBreak() API transmits the break characters\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;\r
-  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).\r
-  * @param  huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)\r
-{\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Enable USART mute mode by setting the MME bit in the CR1 register */\r
-  SET_BIT(huart->Instance->CR1, USART_CR1_MME);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-/**\r
-  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode\r
-  *         as it may not have been in mute mode at this very moment).\r
-  * @param  huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)\r
-{\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Disable USART mute mode by clearing the MME bit in the CR1 register */\r
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-/**\r
-  * @brief Enter UART mute mode (means UART actually enters mute mode).\r
-  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r
-{\r
-  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);\r
-}\r
-\r
-/**\r
-  * @brief  Enable the UART transmitter and disable the UART receiver.\r
-  * @param  huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r
-{\r
-  __HAL_LOCK(huart);\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Clear TE and RE bits */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
-\r
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r
-  SET_BIT(huart->Instance->CR1, USART_CR1_TE);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Enable the UART receiver and disable the UART transmitter.\r
-  * @param  huart UART handle.\r
-  * @retval HAL status.\r
-  */\r
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r
-{\r
-  __HAL_LOCK(huart);\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Clear TE and RE bits */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
-\r
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r
-  SET_BIT(huart->Instance->CR1, USART_CR1_RE);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Transmit break characters.\r
-  * @param  huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r
-{\r
-  /* Check the parameters */\r
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\r
-\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Send break characters */\r
-  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
-  *  @brief   UART Peripheral State functions\r
-  *\r
-@verbatim\r
-  ==============================================================================\r
-            ##### Peripheral State and Error functions #####\r
-  ==============================================================================\r
-    [..]\r
-    This subsection provides functions allowing to :\r
-      (+) Return the UART handle state.\r
-      (+) Return the UART handle error code\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Return the UART handle state.\r
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified UART.\r
-  * @retval HAL state\r
-  */\r
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r
-{\r
-  uint32_t temp1;\r
-  uint32_t temp2;\r
-  temp1 = huart->gState;\r
-  temp2 = huart->RxState;\r
-\r
-  return (HAL_UART_StateTypeDef)(temp1 | temp2);\r
-}\r
-\r
-/**\r
-  * @brief  Return the UART handle error code.\r
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\r
-  *               the configuration information for the specified UART.\r
-  * @retval UART Error Code\r
-  */\r
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r
-{\r
-  return huart->ErrorCode;\r
-}\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UART_Private_Functions UART Private Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initialize the callbacks to their default values.\r
-  * @param  huart UART handle.\r
-  * @retval none\r
-  */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)\r
-{\r
-  /* Init the UART Callback settings */\r
-  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */\r
-  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */\r
-  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */\r
-  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */\r
-  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */\r
-  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */\r
-  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
-  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */\r
-  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */\r
-#if defined(USART_CR1_FIFOEN)\r
-  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */\r
-  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-}\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-\r
-/**\r
-  * @brief Configure the UART peripheral.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)\r
-{\r
-  uint32_t tmpreg;\r
-  uint16_t brrtemp;\r
-  UART_ClockSourceTypeDef clocksource;\r
-  uint32_t usartdiv                   = 0x00000000U;\r
-  HAL_StatusTypeDef ret               = HAL_OK;\r
-  uint32_t lpuart_ker_ck_pres         = 0x00000000U;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\r
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
-  if (UART_INSTANCE_LOWPOWER(huart))\r
-  {\r
-    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));\r
-  }\r
-  else\r
-  {\r
-    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r
-    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));\r
-  }\r
-\r
-  assert_param(IS_UART_PARITY(huart->Init.Parity));\r
-  assert_param(IS_UART_MODE(huart->Init.Mode));\r
-  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\r
-#if defined(USART_PRESC_PRESCALER)\r
-  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));\r
-#endif /* USART_PRESC_PRESCALER */\r
-\r
-  /*-------------------------- USART CR1 Configuration -----------------------*/\r
-  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure\r
-  *  the UART Word Length, Parity, Mode and oversampling:\r
-  *  set the M bits according to huart->Init.WordLength value\r
-  *  set PCE and PS bits according to huart->Init.Parity value\r
-  *  set TE and RE bits according to huart->Init.Mode value\r
-  *  set OVER8 bit according to huart->Init.OverSampling value */\r
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;\r
-#if defined(USART_CR1_FIFOEN)\r
-  tmpreg |= (uint32_t)huart->FifoMode;\r
-#endif /* USART_CR1_FIFOEN */\r
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
-\r
-  /*-------------------------- USART CR2 Configuration -----------------------*/\r
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according\r
-  * to huart->Init.StopBits value */\r
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r
-\r
-  /*-------------------------- USART CR3 Configuration -----------------------*/\r
-  /* Configure\r
-  * - UART HardWare Flow Control: set CTSE and RTSE bits according\r
-  *   to huart->Init.HwFlowCtl value\r
-  * - one-bit sampling method versus three samples' majority rule according\r
-  *   to huart->Init.OneBitSampling (not applicable to LPUART) */\r
-  tmpreg = (uint32_t)huart->Init.HwFlowCtl;\r
-\r
-  if (!(UART_INSTANCE_LOWPOWER(huart)))\r
-  {\r
-    tmpreg |= huart->Init.OneBitSampling;\r
-  }\r
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);\r
-\r
-#if defined(USART_PRESC_PRESCALER)\r
-  /*-------------------------- USART PRESC Configuration -----------------------*/\r
-  /* Configure\r
-  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */\r
-  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);\r
-#endif /* USART_PRESC_PRESCALER */\r
-\r
-  /*-------------------------- USART BRR Configuration -----------------------*/\r
-  UART_GETCLOCKSOURCE(huart, clocksource);\r
-\r
-  /* Check LPUART instance */\r
-  if (UART_INSTANCE_LOWPOWER(huart))\r
-  {\r
-    /* Retrieve frequency clock */\r
-    switch (clocksource)\r
-    {\r
-      case UART_CLOCKSOURCE_PCLK1:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
-#else\r
-        lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq();\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_HSI:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
-#else\r
-        lpuart_ker_ck_pres = (uint32_t)HSI_VALUE;\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_SYSCLK:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
-#else\r
-        lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq();\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_LSE:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
-#else\r
-        lpuart_ker_ck_pres = (uint32_t)LSE_VALUE;\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_UNDEFINED:\r
-      default:\r
-        ret = HAL_ERROR;\r
-        break;\r
-    }\r
-\r
-    /* if proper clock source reported */\r
-    if (lpuart_ker_ck_pres != 0U)\r
-    {\r
-      /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */\r
-      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||\r
-          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))\r
-      {\r
-        ret = HAL_ERROR;\r
-      }\r
-      else\r
-      {\r
-        switch (clocksource)\r
-        {\r
-          case UART_CLOCKSOURCE_PCLK1:\r
-#if defined(USART_PRESC_PRESCALER)\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-            break;\r
-          case UART_CLOCKSOURCE_HSI:\r
-#if defined(USART_PRESC_PRESCALER)\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-            break;\r
-          case UART_CLOCKSOURCE_SYSCLK:\r
-#if defined(USART_PRESC_PRESCALER)\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-            break;\r
-          case UART_CLOCKSOURCE_LSE:\r
-#if defined(USART_PRESC_PRESCALER)\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-            usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-            break;\r
-          case UART_CLOCKSOURCE_UNDEFINED:\r
-          default:\r
-            ret = HAL_ERROR;\r
-            break;\r
-        }\r
-\r
-        /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */\r
-        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))\r
-        {\r
-          huart->Instance->BRR = usartdiv;\r
-        }\r
-        else\r
-        {\r
-          ret = HAL_ERROR;\r
-        }\r
-      } /*   if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */\r
-    } /* if (lpuart_ker_ck_pres != 0) */\r
-  }\r
-  /* Check UART Over Sampling to set Baud Rate Register */\r
-  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
-  {\r
-    switch (clocksource)\r
-    {\r
-      case UART_CLOCKSOURCE_PCLK1:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_PCLK2:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_HSI:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_SYSCLK:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_LSE:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_UNDEFINED:\r
-      default:\r
-        ret = HAL_ERROR;\r
-        break;\r
-    }\r
-\r
-    /* USARTDIV must be greater than or equal to 0d16 */\r
-    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))\r
-    {\r
-      brrtemp = (uint16_t)(usartdiv & 0xFFF0U);\r
-      brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r
-      huart->Instance->BRR = brrtemp;\r
-    }\r
-    else\r
-    {\r
-      ret = HAL_ERROR;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    switch (clocksource)\r
-    {\r
-      case UART_CLOCKSOURCE_PCLK1:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_PCLK2:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_HSI:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_SYSCLK:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_LSE:\r
-#if defined(USART_PRESC_PRESCALER)\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
-#else\r
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));\r
-#endif /* USART_PRESC_PRESCALER */\r
-        break;\r
-      case UART_CLOCKSOURCE_UNDEFINED:\r
-      default:\r
-        ret = HAL_ERROR;\r
-        break;\r
-    }\r
-\r
-    /* USARTDIV must be greater than or equal to 0d16 */\r
-    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))\r
-    {\r
-      huart->Instance->BRR = usartdiv;\r
-    }\r
-    else\r
-    {\r
-      ret = HAL_ERROR;\r
-    }\r
-  }\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Initialize the number of data to process during RX/TX ISR execution */\r
-  huart->NbTxDataToProcess = 1;\r
-  huart->NbRxDataToProcess = 1;\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Clear ISR function pointers */\r
-  huart->RxISR = NULL;\r
-  huart->TxISR = NULL;\r
-\r
-  return ret;\r
-}\r
-\r
-/**\r
-  * @brief Configure the UART peripheral advanced features.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)\r
-{\r
-  /* Check whether the set of advanced features to configure is properly set */\r
-  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));\r
-\r
-  /* if required, configure TX pin active level inversion */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))\r
-  {\r
-    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));\r
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);\r
-  }\r
-\r
-  /* if required, configure RX pin active level inversion */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))\r
-  {\r
-    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));\r
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);\r
-  }\r
-\r
-  /* if required, configure data inversion */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))\r
-  {\r
-    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));\r
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);\r
-  }\r
-\r
-  /* if required, configure RX/TX pins swap */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))\r
-  {\r
-    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));\r
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);\r
-  }\r
-\r
-  /* if required, configure RX overrun detection disabling */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r
-  {\r
-    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));\r
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);\r
-  }\r
-\r
-  /* if required, configure DMA disabling on reception error */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))\r
-  {\r
-    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));\r
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);\r
-  }\r
-\r
-  /* if required, configure auto Baud rate detection scheme */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))\r
-  {\r
-    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));\r
-    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));\r
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);\r
-    /* set auto Baudrate detection parameters if detection is enabled */\r
-    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)\r
-    {\r
-      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));\r
-      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);\r
-    }\r
-  }\r
-\r
-  /* if required, configure MSB first on communication line */\r
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))\r
-  {\r
-    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));\r
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Check the UART Idle State.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)\r
-{\r
-  uint32_t tickstart;\r
-\r
-  /* Initialize the UART ErrorCode */\r
-  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-\r
-  /* Init tickstart for timeout managment*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Check if the Transmitter is enabled */\r
-  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
-  {\r
-    /* Wait until TEACK flag is set */\r
-    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
-    {\r
-      /* Timeout occurred */\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-\r
-  /* Check if the Receiver is enabled */\r
-  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
-  {\r
-    /* Wait until REACK flag is set */\r
-    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
-    {\r
-      /* Timeout occurred */\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-\r
-  /* Initialize the UART State */\r
-  huart->gState = HAL_UART_STATE_READY;\r
-  huart->RxState = HAL_UART_STATE_READY;\r
-\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Handle UART Communication Timeout.\r
-  * @param huart     UART handle.\r
-  * @param Flag      Specifies the UART flag to check\r
-  * @param Status    Flag status (SET or RESET)\r
-  * @param Tickstart Tick start value\r
-  * @param Timeout   Timeout duration\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,\r
-                                              uint32_t Tickstart, uint32_t Timeout)\r
-{\r
-  /* Wait until flag is set */\r
-  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\r
-  {\r
-    /* Check for the Timeout */\r
-    if (Timeout != HAL_MAX_DELAY)\r
-    {\r
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
-      {\r
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
-#if defined(USART_CR1_FIFOEN)\r
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));\r
-#else\r
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r
-#endif /* USART_CR1_FIFOEN */\r
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-        huart->gState = HAL_UART_STATE_READY;\r
-        huart->RxState = HAL_UART_STATE_READY;\r
-\r
-        __HAL_UNLOCK(huart);\r
-\r
-        return HAL_TIMEOUT;\r
-      }\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)\r
-{\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Disable TXEIE, TCIE, TXFT interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));\r
-#else\r
-  /* Disable TXEIE and TCIE interrupts */\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* At end of Tx process, restore huart->gState to Ready */\r
-  huart->gState = HAL_UART_STATE_READY;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)\r
-{\r
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
-#if defined(USART_CR1_FIFOEN)\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
-#else\r
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* At end of Rx process, restore huart->RxState to Ready */\r
-  huart->RxState = HAL_UART_STATE_READY;\r
-\r
-  /* Reset RxIsr function pointer */\r
-  huart->RxISR = NULL;\r
-}\r
-\r
-\r
-/**\r
-  * @brief DMA UART transmit process complete callback.\r
-  * @param hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-  /* DMA Normal mode */\r
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))\r
-  {\r
-    huart->TxXferCount = 0U;\r
-\r
-    /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r
-       in the UART CR3 register */\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
-\r
-    /* Enable the UART Transmit Complete Interrupt */\r
-    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
-  }\r
-  /* DMA Circular mode */\r
-  else\r
-  {\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    /*Call registered Tx complete callback*/\r
-    huart->TxCpltCallback(huart);\r
-#else\r
-    /*Call legacy weak Tx complete callback*/\r
-    HAL_UART_TxCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief DMA UART transmit process half complete callback.\r
-  * @param hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /*Call registered Tx Half complete callback*/\r
-  huart->TxHalfCpltCallback(huart);\r
-#else\r
-  /*Call legacy weak Tx Half complete callback*/\r
-  HAL_UART_TxHalfCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief DMA UART receive process complete callback.\r
-  * @param hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-  /* DMA Normal mode */\r
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))\r
-  {\r
-    huart->RxXferCount = 0U;\r
-\r
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit\r
-       in the UART CR3 register */\r
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
-\r
-    /* At end of Rx process, restore huart->RxState to Ready */\r
-    huart->RxState = HAL_UART_STATE_READY;\r
-  }\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /*Call registered Rx complete callback*/\r
-  huart->RxCpltCallback(huart);\r
-#else\r
-  /*Call legacy weak Rx complete callback*/\r
-  HAL_UART_RxCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief DMA UART receive process half complete callback.\r
-  * @param hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /*Call registered Rx Half complete callback*/\r
-  huart->RxHalfCpltCallback(huart);\r
-#else\r
-  /*Call legacy weak Rx Half complete callback*/\r
-  HAL_UART_RxHalfCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief DMA UART communication error callback.\r
-  * @param hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-  const HAL_UART_StateTypeDef gstate = huart->gState;\r
-  const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
-\r
-  /* Stop UART DMA Tx request if ongoing */\r
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
-      (gstate == HAL_UART_STATE_BUSY_TX))\r
-  {\r
-    huart->TxXferCount = 0U;\r
-    UART_EndTxTransfer(huart);\r
-  }\r
-\r
-  /* Stop UART DMA Rx request if ongoing */\r
-  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
-      (rxstate == HAL_UART_STATE_BUSY_RX))\r
-  {\r
-    huart->RxXferCount = 0U;\r
-    UART_EndRxTransfer(huart);\r
-  }\r
-\r
-  huart->ErrorCode |= HAL_UART_ERROR_DMA;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /*Call registered error callback*/\r
-  huart->ErrorCallback(huart);\r
-#else\r
-  /*Call legacy weak error callback*/\r
-  HAL_UART_ErrorCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error\r
-  *         (To be called at end of DMA Abort procedure following error occurrence).\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-  huart->RxXferCount = 0U;\r
-  huart->TxXferCount = 0U;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /*Call registered error callback*/\r
-  huart->ErrorCallback(huart);\r
-#else\r
-  /*Call legacy weak error callback*/\r
-  HAL_UART_ErrorCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA UART Tx communication abort callback, when initiated by user\r
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).\r
-  * @note   When this callback is executed, User Abort complete call back is called only if no\r
-  *         Abort still ongoing for Rx DMA Handle.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-  huart->hdmatx->XferAbortCallback = NULL;\r
-\r
-  /* Check if an Abort process is still ongoing */\r
-  if (huart->hdmarx != NULL)\r
-  {\r
-    if (huart->hdmarx->XferAbortCallback != NULL)\r
-    {\r
-      return;\r
-    }\r
-  }\r
-\r
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
-  huart->TxXferCount = 0U;\r
-  huart->RxXferCount = 0U;\r
-\r
-  /* Reset errorCode */\r
-  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-\r
-  /* Clear the Error flags in the ICR register */\r
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Flush the whole TX FIFO (if needed) */\r
-  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
-  {\r
-    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
-  }\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Restore huart->gState and huart->RxState to Ready */\r
-  huart->gState  = HAL_UART_STATE_READY;\r
-  huart->RxState = HAL_UART_STATE_READY;\r
-\r
-  /* Call user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /* Call registered Abort complete callback */\r
-  huart->AbortCpltCallback(huart);\r
-#else\r
-  /* Call legacy weak Abort complete callback */\r
-  HAL_UART_AbortCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-\r
-/**\r
-  * @brief  DMA UART Rx communication abort callback, when initiated by user\r
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).\r
-  * @note   When this callback is executed, User Abort complete call back is called only if no\r
-  *         Abort still ongoing for Tx DMA Handle.\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-  huart->hdmarx->XferAbortCallback = NULL;\r
-\r
-  /* Check if an Abort process is still ongoing */\r
-  if (huart->hdmatx != NULL)\r
-  {\r
-    if (huart->hdmatx->XferAbortCallback != NULL)\r
-    {\r
-      return;\r
-    }\r
-  }\r
-\r
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
-  huart->TxXferCount = 0U;\r
-  huart->RxXferCount = 0U;\r
-\r
-  /* Reset errorCode */\r
-  huart->ErrorCode = HAL_UART_ERROR_NONE;\r
-\r
-  /* Clear the Error flags in the ICR register */\r
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-  /* Discard the received data */\r
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-\r
-  /* Restore huart->gState and huart->RxState to Ready */\r
-  huart->gState  = HAL_UART_STATE_READY;\r
-  huart->RxState = HAL_UART_STATE_READY;\r
-\r
-  /* Call user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /* Call registered Abort complete callback */\r
-  huart->AbortCpltCallback(huart);\r
-#else\r
-  /* Call legacy weak Abort complete callback */\r
-  HAL_UART_AbortCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-\r
-/**\r
-  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to\r
-  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)\r
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,\r
-  *         and leads to user Tx Abort Complete callback execution).\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
-\r
-  huart->TxXferCount = 0U;\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-  /* Flush the whole TX FIFO (if needed) */\r
-  if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
-  {\r
-    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
-  }\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-  /* Restore huart->gState to Ready */\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  /* Call user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /* Call registered Abort Transmit Complete Callback */\r
-  huart->AbortTransmitCpltCallback(huart);\r
-#else\r
-  /* Call legacy weak Abort Transmit Complete Callback */\r
-  HAL_UART_AbortTransmitCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to\r
-  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)\r
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,\r
-  *         and leads to user Rx Abort Complete callback execution).\r
-  * @param  hdma DMA handle.\r
-  * @retval None\r
-  */\r
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
-\r
-  huart->RxXferCount = 0U;\r
-\r
-  /* Clear the Error flags in the ICR register */\r
-  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
-\r
-  /* Discard the received data */\r
-  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-\r
-  /* Restore huart->RxState to Ready */\r
-  huart->RxState = HAL_UART_STATE_READY;\r
-\r
-  /* Call user Abort complete callback */\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /* Call registered Abort Receive Complete Callback */\r
-  huart->AbortReceiveCpltCallback(huart);\r
-#else\r
-  /* Call legacy weak Abort Receive Complete Callback */\r
-  HAL_UART_AbortReceiveCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief TX interrrupt handler for 7 or 8 bits data word length .\r
-  * @note   Function is called under interruption only, once\r
-  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)\r
-{\r
-  /* Check that a Tx process is ongoing */\r
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
-  {\r
-    if (huart->TxXferCount == 0U)\r
-    {\r
-      /* Disable the UART Transmit Data Register Empty Interrupt */\r
-#if defined(USART_CR1_FIFOEN)\r
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
-#else\r
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-      /* Enable the UART Transmit Complete Interrupt */\r
-      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
-    }\r
-    else\r
-    {\r
-      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);\r
-      huart->pTxBuffPtr++;\r
-      huart->TxXferCount--;\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief TX interrrupt handler for 9 bits data word length.\r
-  * @note   Function is called under interruption only, once\r
-  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)\r
-{\r
-  uint16_t *tmp;\r
-\r
-  /* Check that a Tx process is ongoing */\r
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
-  {\r
-    if (huart->TxXferCount == 0U)\r
-    {\r
-      /* Disable the UART Transmit Data Register Empty Interrupt */\r
-#if defined(USART_CR1_FIFOEN)\r
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
-#else\r
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-      /* Enable the UART Transmit Complete Interrupt */\r
-      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
-    }\r
-    else\r
-    {\r
-      tmp = (uint16_t *) huart->pTxBuffPtr;\r
-      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);\r
-      huart->pTxBuffPtr += 2U;\r
-      huart->TxXferCount--;\r
-    }\r
-  }\r
-}\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/**\r
-  * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.\r
-  * @note   Function is called under interruption only, once\r
-  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)\r
-{\r
-  uint16_t  nb_tx_data;\r
-\r
-  /* Check that a Tx process is ongoing */\r
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
-  {\r
-    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
-    {\r
-      if (huart->TxXferCount == 0U)\r
-      {\r
-        /* Disable the TX FIFO threshold interrupt */\r
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
-\r
-        /* Enable the UART Transmit Complete Interrupt */\r
-        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
-\r
-        break; /* force exit loop */\r
-      }\r
-      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)\r
-      {\r
-        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);\r
-        huart->pTxBuffPtr++;\r
-        huart->TxXferCount--;\r
-      }\r
-      else\r
-      {\r
-        /* Nothing to do */\r
-      }\r
-    }\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.\r
-  * @note   Function is called under interruption only, once\r
-  *         interruptions have been enabled by HAL_UART_Transmit_IT().\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)\r
-{\r
-  uint16_t *tmp;\r
-  uint16_t  nb_tx_data;\r
-\r
-  /* Check that a Tx process is ongoing */\r
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
-  {\r
-    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
-    {\r
-      if (huart->TxXferCount == 0U)\r
-      {\r
-        /* Disable the TX FIFO threshold interrupt */\r
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
-\r
-        /* Enable the UART Transmit Complete Interrupt */\r
-        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
-\r
-        break; /* force exit loop */\r
-      }\r
-      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)\r
-      {\r
-        tmp = (uint16_t *) huart->pTxBuffPtr;\r
-        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);\r
-        huart->pTxBuffPtr += 2U;\r
-        huart->TxXferCount--;\r
-      }\r
-      else\r
-      {\r
-        /* Nothing to do */\r
-      }\r
-    }\r
-  }\r
-}\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @brief  Wrap up transmission in non-blocking mode.\r
-  * @param  huart pointer to a UART_HandleTypeDef structure that contains\r
-  *                the configuration information for the specified UART module.\r
-  * @retval None\r
-  */\r
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r
-{\r
-  /* Disable the UART Transmit Complete Interrupt */\r
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
-\r
-  /* Tx process is ended, restore huart->gState to Ready */\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  /* Cleat TxISR function pointer */\r
-  huart->TxISR = NULL;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-  /*Call registered Tx complete callback*/\r
-  huart->TxCpltCallback(huart);\r
-#else\r
-  /*Call legacy weak Tx complete callback*/\r
-  HAL_UART_TxCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
-  * @brief RX interrrupt handler for 7 or 8 bits data word length .\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)\r
-{\r
-  uint16_t uhMask = huart->Mask;\r
-  uint16_t  uhdata;\r
-\r
-  /* Check that a Rx process is ongoing */\r
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
-  {\r
-    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
-    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);\r
-    huart->pRxBuffPtr++;\r
-    huart->RxXferCount--;\r
-\r
-    if (huart->RxXferCount == 0U)\r
-    {\r
-      /* Disable the UART Parity Error Interrupt and RXNE interrupts */\r
-#if defined(USART_CR1_FIFOEN)\r
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
-#else\r
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-      /* Rx process is completed, restore huart->RxState to Ready */\r
-      huart->RxState = HAL_UART_STATE_READY;\r
-\r
-      /* Clear RxISR function pointer */\r
-      huart->RxISR = NULL;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-      /*Call registered Rx complete callback*/\r
-      huart->RxCpltCallback(huart);\r
-#else\r
-      /*Call legacy weak Rx complete callback*/\r
-      HAL_UART_RxCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Clear RXNE interrupt flag */\r
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief RX interrrupt handler for 9 bits data word length .\r
-  * @note   Function is called under interruption only, once\r
-  *         interruptions have been enabled by HAL_UART_Receive_IT()\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)\r
-{\r
-  uint16_t *tmp;\r
-  uint16_t uhMask = huart->Mask;\r
-  uint16_t  uhdata;\r
-\r
-  /* Check that a Rx process is ongoing */\r
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
-  {\r
-    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
-    tmp = (uint16_t *) huart->pRxBuffPtr ;\r
-    *tmp = (uint16_t)(uhdata & uhMask);\r
-    huart->pRxBuffPtr += 2U;\r
-    huart->RxXferCount--;\r
-\r
-    if (huart->RxXferCount == 0U)\r
-    {\r
-      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/\r
-#if defined(USART_CR1_FIFOEN)\r
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
-#else\r
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
-\r
-      /* Rx process is completed, restore huart->RxState to Ready */\r
-      huart->RxState = HAL_UART_STATE_READY;\r
-\r
-      /* Clear RxISR function pointer */\r
-      huart->RxISR = NULL;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-      /*Call registered Rx complete callback*/\r
-      huart->RxCpltCallback(huart);\r
-#else\r
-      /*Call legacy weak Rx complete callback*/\r
-      HAL_UART_RxCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Clear RXNE interrupt flag */\r
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-  }\r
-}\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/**\r
-  * @brief RX interrrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.\r
-  * @note   Function is called under interruption only, once\r
-  *         interruptions have been enabled by HAL_UART_Receive_IT()\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)\r
-{\r
-  uint16_t  uhMask = huart->Mask;\r
-  uint16_t  uhdata;\r
-  uint16_t   nb_rx_data;\r
-  uint16_t  rxdatacount;\r
-\r
-  /* Check that a Rx process is ongoing */\r
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
-  {\r
-    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
-    {\r
-      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
-      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);\r
-      huart->pRxBuffPtr++;\r
-      huart->RxXferCount--;\r
-\r
-      if (huart->RxXferCount == 0U)\r
-      {\r
-        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/\r
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
-\r
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
-        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
-\r
-        /* Rx process is completed, restore huart->RxState to Ready */\r
-        huart->RxState = HAL_UART_STATE_READY;\r
-\r
-        /* Clear RxISR function pointer */\r
-        huart->RxISR = NULL;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-        /*Call registered Rx complete callback*/\r
-        huart->RxCpltCallback(huart);\r
-#else\r
-        /*Call legacy weak Rx complete callback*/\r
-        HAL_UART_RxCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-      }\r
-    }\r
-\r
-    /* When remaining number of bytes to receive is less than the RX FIFO\r
-    threshold, next incoming frames are processed as if FIFO mode was\r
-    disabled (i.e. one interrupt per received frame).\r
-    */\r
-    rxdatacount = huart->RxXferCount;\r
-    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))\r
-    {\r
-      /* Disable the UART RXFT interrupt*/\r
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
-\r
-      /* Update the RxISR function pointer */\r
-      huart->RxISR = UART_RxISR_8BIT;\r
-\r
-      /* Enable the UART Data Register Not Empty interrupt */\r
-      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Clear RXNE interrupt flag */\r
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.\r
-  * @note   Function is called under interruption only, once\r
-  *         interruptions have been enabled by HAL_UART_Receive_IT()\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)\r
-{\r
-  uint16_t *tmp;\r
-  uint16_t  uhMask = huart->Mask;\r
-  uint16_t  uhdata;\r
-  uint16_t   nb_rx_data;\r
-  uint16_t  rxdatacount;\r
-\r
-  /* Check that a Rx process is ongoing */\r
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
-  {\r
-    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
-    {\r
-      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
-      tmp = (uint16_t *) huart->pRxBuffPtr ;\r
-      *tmp = (uint16_t)(uhdata & uhMask);\r
-      huart->pRxBuffPtr += 2U;\r
-      huart->RxXferCount--;\r
-\r
-      if (huart->RxXferCount == 0U)\r
-      {\r
-        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/\r
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
-\r
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
-        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
-\r
-        /* Rx process is completed, restore huart->RxState to Ready */\r
-        huart->RxState = HAL_UART_STATE_READY;\r
-\r
-        /* Clear RxISR function pointer */\r
-        huart->RxISR = NULL;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-        /*Call registered Rx complete callback*/\r
-        huart->RxCpltCallback(huart);\r
-#else\r
-        /*Call legacy weak Rx complete callback*/\r
-        HAL_UART_RxCpltCallback(huart);\r
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
-      }\r
-    }\r
-\r
-    /* When remaining number of bytes to receive is less than the RX FIFO\r
-    threshold, next incoming frames are processed as if FIFO mode was\r
-    disabled (i.e. one interrupt per received frame).\r
-    */\r
-    rxdatacount = huart->RxXferCount;\r
-    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))\r
-    {\r
-      /* Disable the UART RXFT interrupt*/\r
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
-\r
-      /* Update the RxISR function pointer */\r
-      huart->RxISR = UART_RxISR_16BIT;\r
-\r
-      /* Enable the UART Data Register Not Empty interrupt */\r
-      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
-    }\r
-  }\r
-  else\r
-  {\r
-    /* Clear RXNE interrupt flag */\r
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
-  }\r
-}\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_UART_MODULE_ENABLED */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
deleted file mode 100644 (file)
index 98f6d33..0000000
+++ /dev/null
@@ -1,787 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_hal_uart_ex.c\r
-  * @author  MCD Application Team\r
-  * @brief   Extended UART HAL module driver.\r
-  *          This file provides firmware functions to manage the following extended\r
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\r
-  *           + Initialization and de-initialization functions\r
-  *           + Peripheral Control functions\r
-  *\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-               ##### UART peripheral extended features  #####\r
-  ==============================================================================\r
-\r
-    (#) Declare a UART_HandleTypeDef handle structure.\r
-\r
-    (#) For the UART RS485 Driver Enable mode, initialize the UART registers\r
-        by calling the HAL_RS485Ex_Init() API.\r
-\r
-    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.\r
-\r
-        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior\r
-            starting RX/TX transfers. Also RX/TX FIFO thresholds must be\r
-            configured prior starting RX/TX transfers.\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
-  * @{\r
-  */\r
-\r
-/** @defgroup UARTEx UARTEx\r
-  * @brief UART Extended HAL module driver\r
-  * @{\r
-  */\r
-\r
-#ifdef HAL_UART_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#if defined(USART_CR1_FIFOEN)\r
-/** @defgroup UARTEX_Private_Constants UARTEx Private Constants\r
-  * @{\r
-  */\r
-/* UART RX FIFO depth */\r
-#define RX_FIFO_DEPTH 8U\r
-\r
-/* UART TX FIFO depth */\r
-#define TX_FIFO_DEPTH 8U\r
-/**\r
-  * @}\r
-  */\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup UARTEx_Private_Functions UARTEx Private Functions\r
-  * @{\r
-  */\r
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);\r
-#if defined(USART_CR1_FIFOEN)\r
-static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);\r
-#endif /* USART_CR1_FIFOEN */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions\r
-  * @brief    Extended Initialization and Configuration Functions\r
-  *\r
-@verbatim\r
-===============================================================================\r
-            ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
-    [..]\r
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
-    in asynchronous mode.\r
-      (+) For the asynchronous mode the parameters below can be configured:\r
-        (++) Baud Rate\r
-        (++) Word Length\r
-        (++) Stop Bit\r
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
-             in the data register is transmitted but is changed by the parity bit.\r
-        (++) Hardware flow control\r
-        (++) Receiver/transmitter modes\r
-        (++) Over Sampling Method\r
-        (++) One-Bit Sampling Method\r
-      (+) For the asynchronous mode, the following advanced features can be configured as well:\r
-        (++) TX and/or RX pin level inversion\r
-        (++) data logical level inversion\r
-        (++) RX and TX pins swap\r
-        (++) RX overrun detection disabling\r
-        (++) DMA disabling on RX error\r
-        (++) MSB first on communication line\r
-        (++) auto Baud rate detection\r
-    [..]\r
-    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration\r
-     procedures (details for the procedures are available in reference manual).\r
-\r
-@endverbatim\r
-\r
-  Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
-  8-bit or 9-bit), the possible UART formats are listed in the\r
-  following table.\r
-\r
-    Table 1. UART frame format.\r
-    +-----------------------------------------------------------------------+\r
-    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |\r
-    |---------|---------|-----------|---------------------------------------|\r
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |\r
-    +-----------------------------------------------------------------------+\r
-\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Initialize the RS485 Driver enable feature according to the specified\r
-  *         parameters in the UART_InitTypeDef and creates the associated handle.\r
-  * @param huart            UART handle.\r
-  * @param Polarity         Select the driver enable polarity.\r
-  *          This parameter can be one of the following values:\r
-  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high\r
-  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low\r
-  * @param AssertionTime    Driver Enable assertion time:\r
-  *       5-bit value defining the time between the activation of the DE (Driver Enable)\r
-  *       signal and the beginning of the start bit. It is expressed in sample time\r
-  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)\r
-  * @param DeassertionTime  Driver Enable deassertion time:\r
-  *       5-bit value defining the time between the end of the last stop bit, in a\r
-  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.\r
-  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the\r
-  *       oversampling rate).\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,\r
-                                   uint32_t DeassertionTime)\r
-{\r
-  uint32_t temp;\r
-\r
-  /* Check the UART handle allocation */\r
-  if (huart == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-  /* Check the Driver Enable UART instance */\r
-  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));\r
-\r
-  /* Check the Driver Enable polarity */\r
-  assert_param(IS_UART_DE_POLARITY(Polarity));\r
-\r
-  /* Check the Driver Enable assertion time */\r
-  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));\r
-\r
-  /* Check the Driver Enable deassertion time */\r
-  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));\r
-\r
-  if (huart->gState == HAL_UART_STATE_RESET)\r
-  {\r
-    /* Allocate lock resource and initialize it */\r
-    huart->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
-    UART_InitCallbacksToDefault(huart);\r
-\r
-    if (huart->MspInitCallback == NULL)\r
-    {\r
-      huart->MspInitCallback = HAL_UART_MspInit;\r
-    }\r
-\r
-    /* Init the low level hardware */\r
-    huart->MspInitCallback(huart);\r
-#else\r
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
-    HAL_UART_MspInit(huart);\r
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
-  }\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Set the UART Communication parameters */\r
-  if (UART_SetConfig(huart) == HAL_ERROR)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
-  {\r
-    UART_AdvFeatureConfig(huart);\r
-  }\r
-\r
-  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */\r
-  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);\r
-\r
-  /* Set the Driver Enable polarity */\r
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);\r
-\r
-  /* Set the Driver Enable assertion and deassertion times */\r
-  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);\r
-  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);\r
-  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);\r
-\r
-  /* Enable the Peripheral */\r
-  __HAL_UART_ENABLE(huart);\r
-\r
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions\r
-  *  @brief Extended functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### IO operation functions #####\r
- ===============================================================================\r
-    This subsection provides a set of Wakeup and FIFO mode related callback functions.\r
-\r
-    (#) Wakeup from Stop mode Callback:\r
-        (+) HAL_UARTEx_WakeupCallback()\r
-\r
-    (#) TX/RX Fifos Callbacks:\r
-        (+) HAL_UARTEx_RxFifoFullCallback()\r
-        (+) HAL_UARTEx_TxFifoEmptyCallback()\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief UART wakeup from Stop mode callback.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UARTEx_WakeupCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/**\r
-  * @brief  UART RX Fifo full callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  UART TX Fifo empty callback.\r
-  * @param  huart UART handle.\r
-  * @retval None\r
-  */\r
-__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(huart);\r
-\r
-  /* NOTE : This function should not be modified, when the callback is needed,\r
-            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.\r
-   */\r
-}\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions\r
-  * @brief    Extended Peripheral Control functions\r
-  *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Peripheral Control functions #####\r
- ===============================================================================\r
-    [..] This section provides the following functions:\r
-     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode\r
-     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality\r
-     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address\r
-         detection length to more than 4 bits for multiprocessor address mark wake up.\r
-     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode\r
-         trigger: address match, Start Bit detection or RXNE bit status.\r
-     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode\r
-     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality\r
-     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode\r
-     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode\r
-     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold\r
-     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-\r
-\r
-#if defined(USART_CR3_UCESM)\r
-/**\r
-  * @brief  Keep UART Clock enabled when in Stop Mode.\r
-  * @note   When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled\r
-  *         this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.\r
-  * @note   When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source,\r
-  *         and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set.\r
-  * @param  huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart)\r
-{\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  /* Set UCESM bit */\r
-  SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Disable UART Clock when in Stop Mode.\r
-  * @param  huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart)\r
-{\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  /* Clear UCESM bit */\r
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-#endif /* USART_CR3_UCESM */\r
-\r
-/**\r
-  * @brief By default in multiprocessor mode, when the wake up method is set\r
-  *        to address mark, the UART handles only 4-bit long addresses detection;\r
-  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit\r
-  *        long).\r
-  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,\r
-  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.\r
-  * @param huart         UART handle.\r
-  * @param AddressLength This parameter can be one of the following values:\r
-  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address\r
-  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)\r
-{\r
-  /* Check the UART handle allocation */\r
-  if (huart == NULL)\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-\r
-  /* Check the address length parameter */\r
-  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Set the address length */\r
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);\r
-\r
-  /* Enable the Peripheral */\r
-  __HAL_UART_ENABLE(huart);\r
-\r
-  /* TEACK and/or REACK to check before moving huart->gState to Ready */\r
-  return (UART_CheckIdleState(huart));\r
-}\r
-\r
-/**\r
-  * @brief Set Wakeup from Stop mode interrupt flag selection.\r
-  * @note It is the application responsibility to enable the interrupt used as\r
-  *       usart_wkup interrupt source before entering low-power mode.\r
-  * @param huart           UART handle.\r
-  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.\r
-  *          This parameter can be one of the following values:\r
-  *          @arg @ref UART_WAKEUP_ON_ADDRESS\r
-  *          @arg @ref UART_WAKEUP_ON_STARTBIT\r
-  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)\r
-{\r
-  HAL_StatusTypeDef status = HAL_OK;\r
-  uint32_t tickstart;\r
-\r
-  /* check the wake-up from stop mode UART instance */\r
-  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));\r
-  /* check the wake-up selection parameter */\r
-  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Disable the Peripheral */\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Set the wake-up selection scheme */\r
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);\r
-\r
-  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)\r
-  {\r
-    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);\r
-  }\r
-\r
-  /* Enable the Peripheral */\r
-  __HAL_UART_ENABLE(huart);\r
-\r
-  /* Init tickstart for timeout managment*/\r
-  tickstart = HAL_GetTick();\r
-\r
-  /* Wait until REACK flag is set */\r
-  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
-  {\r
-    status = HAL_TIMEOUT;\r
-  }\r
-  else\r
-  {\r
-    /* Initialize the UART State */\r
-    huart->gState = HAL_UART_STATE_READY;\r
-  }\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return status;\r
-}\r
-\r
-/**\r
-  * @brief Enable UART Stop Mode.\r
-  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)\r
-{\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  /* Set UESM bit */\r
-  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Disable UART Stop Mode.\r
-  * @param huart UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)\r
-{\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  /* Clear UESM bit */\r
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/**\r
-  * @brief  Enable the FIFO mode.\r
-  * @param huart      UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)\r
-{\r
-  uint32_t tmpcr1;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Save actual UART configuration */\r
-  tmpcr1 = READ_REG(huart->Instance->CR1);\r
-\r
-  /* Disable UART */\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Enable FIFO mode */\r
-  SET_BIT(tmpcr1, USART_CR1_FIFOEN);\r
-  huart->FifoMode = UART_FIFOMODE_ENABLE;\r
-\r
-  /* Restore UART configuration */\r
-  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
-\r
-  /* Determine the number of data to process during RX/TX ISR execution */\r
-  UARTEx_SetNbDataToProcess(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Disable the FIFO mode.\r
-  * @param huart      UART handle.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)\r
-{\r
-  uint32_t tmpcr1;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Save actual UART configuration */\r
-  tmpcr1 = READ_REG(huart->Instance->CR1);\r
-\r
-  /* Disable UART */\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Enable FIFO mode */\r
-  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);\r
-  huart->FifoMode = UART_FIFOMODE_DISABLE;\r
-\r
-  /* Restore UART configuration */\r
-  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Set the TXFIFO threshold.\r
-  * @param huart      UART handle.\r
-  * @param Threshold  TX FIFO threshold value\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8\r
-  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4\r
-  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2\r
-  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4\r
-  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8\r
-  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)\r
-{\r
-  uint32_t tmpcr1;\r
-\r
-  /* Check parameters */\r
-  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
-  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Save actual UART configuration */\r
-  tmpcr1 = READ_REG(huart->Instance->CR1);\r
-\r
-  /* Disable UART */\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Update TX threshold configuration */\r
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);\r
-\r
-  /* Determine the number of data to process during RX/TX ISR execution */\r
-  UARTEx_SetNbDataToProcess(huart);\r
-\r
-  /* Restore UART configuration */\r
-  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Set the RXFIFO threshold.\r
-  * @param huart      UART handle.\r
-  * @param Threshold  RX FIFO threshold value\r
-  *          This parameter can be one of the following values:\r
-  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8\r
-  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4\r
-  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2\r
-  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4\r
-  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8\r
-  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)\r
-{\r
-  uint32_t tmpcr1;\r
-\r
-  /* Check the parameters */\r
-  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
-  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));\r
-\r
-  /* Process Locked */\r
-  __HAL_LOCK(huart);\r
-\r
-  huart->gState = HAL_UART_STATE_BUSY;\r
-\r
-  /* Save actual UART configuration */\r
-  tmpcr1 = READ_REG(huart->Instance->CR1);\r
-\r
-  /* Disable UART */\r
-  __HAL_UART_DISABLE(huart);\r
-\r
-  /* Update RX threshold configuration */\r
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);\r
-\r
-  /* Determine the number of data to process during RX/TX ISR execution */\r
-  UARTEx_SetNbDataToProcess(huart);\r
-\r
-  /* Restore UART configuration */\r
-  WRITE_REG(huart->Instance->CR1, tmpcr1);\r
-\r
-  huart->gState = HAL_UART_STATE_READY;\r
-\r
-  /* Process Unlocked */\r
-  __HAL_UNLOCK(huart);\r
-\r
-  return HAL_OK;\r
-}\r
-#endif /* USART_CR1_FIFOEN */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup UARTEx_Private_Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.\r
-  * @param huart           UART handle.\r
-  * @param WakeUpSelection UART wake up from stop mode parameters.\r
-  * @retval None\r
-  */\r
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)\r
-{\r
-  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));\r
-\r
-  /* Set the USART address length */\r
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);\r
-\r
-  /* Set the USART address node */\r
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));\r
-}\r
-\r
-#if defined(USART_CR1_FIFOEN)\r
-/**\r
-  * @brief Calculate the number of data to process in RX/TX ISR.\r
-  * @note The RX FIFO depth and the TX FIFO depth is extracted from\r
-  *       the UART configuration registers.\r
-  * @param huart UART handle.\r
-  * @retval None\r
-  */\r
-static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)\r
-{\r
-  uint8_t rx_fifo_depth;\r
-  uint8_t tx_fifo_depth;\r
-  uint8_t rx_fifo_threshold;\r
-  uint8_t tx_fifo_threshold;\r
-  uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};\r
-  uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};\r
-\r
-  if (huart->FifoMode == UART_FIFOMODE_DISABLE)\r
-  {\r
-    huart->NbTxDataToProcess = 1U;\r
-    huart->NbRxDataToProcess = 1U;\r
-  }\r
-  else\r
-  {\r
-    rx_fifo_depth = RX_FIFO_DEPTH;\r
-    tx_fifo_depth = TX_FIFO_DEPTH;\r
-    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);\r
-    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);\r
-    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];\r
-    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];\r
-  }\r
-}\r
-#endif /* USART_CR1_FIFOEN */\r
-/**\r
-  * @}\r
-  */\r
-\r
-#endif /* HAL_UART_MODULE_ENABLED */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/ST_Code/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
deleted file mode 100644 (file)
index 4533162..0000000
+++ /dev/null
@@ -1,2611 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32l4xx_ll_usb.c\r
-  * @author  MCD Application Team\r
-  * @brief   USB Low Layer HAL module driver.\r
-  *\r
-  *          This file provides firmware functions to manage the following\r
-  *          functionalities of the USB Peripheral Controller:\r
-  *           + Initialization/de-initialization functions\r
-  *           + I/O operation functions\r
-  *           + Peripheral Control functions\r
-  *           + Peripheral State functions\r
-  *\r
-  @verbatim\r
-  ==============================================================================\r
-                    ##### How to use this driver #####\r
-  ==============================================================================\r
-    [..]\r
-      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r
-\r
-      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r
-\r
-      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r
-\r
-  @endverbatim\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r
-  * All rights reserved.</center></h2>\r
-  *\r
-  * This software component is licensed by ST under BSD 3-Clause license,\r
-  * the "License"; You may not use this file except in compliance with the\r
-  * License. You may obtain a copy of the License at:\r
-  *                        opensource.org/licenses/BSD-3-Clause\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_LL_USB_DRIVER\r
-  * @{\r
-  */\r
-\r
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r
-#if defined (USB) || defined (USB_OTG_FS)\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-#if defined (USB_OTG_FS)\r
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions\r
-  * @{\r
-  */\r
-\r
-/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions\r
- *  @brief    Initialization and Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
-                      ##### Initialization/de-initialization functions #####\r
- ===============================================================================\r
-\r
-@endverbatim\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Initializes the USB Core\r
-  * @param  USBx USB Instance\r
-  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains\r
-  *         the configuration information for the specified USBx peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
-{\r
-  HAL_StatusTypeDef ret;\r
-\r
-  if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r
-  {\r
-    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
-\r
-    /* Init The ULPI Interface */\r
-    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r
-\r
-    /* Select vbus source */\r
-    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r
-    if (cfg.use_external_vbus == 1U)\r
-    {\r
-      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r
-    }\r
-    /* Reset after a PHY select  */\r
-    ret = USB_CoreReset(USBx);\r
-  }\r
-  else /* FS interface (embedded Phy) */\r
-  {\r
-    /* Select FS Embedded PHY */\r
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r
-\r
-    /* Reset after a PHY select and set Host mode */\r
-    ret = USB_CoreReset(USBx);\r
-\r
-    if (cfg.battery_charging_enable == 0U)\r
-    {\r
-      /* Activate the USB Transceiver */\r
-      USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\r
-    }\r
-    else\r
-    {\r
-      /* Deactivate the USB Transceiver */\r
-      USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
-    }\r
-  }\r
-\r
-  return ret;\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Set the USB turnaround time\r
-  * @param  USBx USB Instance\r
-  * @param  hclk: AHB clock frequency\r
-  * @retval USB turnaround time In PHY Clocks number\r
-  */\r
-HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,\r
-                                        uint32_t hclk, uint8_t speed)\r
-{\r
-  uint32_t UsbTrd;\r
-\r
-  /* The USBTRD is configured according to the tables below, depending on AHB frequency\r
-  used by application. In the low AHB frequency range it is used to stretch enough the USB response\r
-  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access\r
-  latency to the Data FIFO */\r
-  if (speed == USBD_FS_SPEED)\r
-  {\r
-    if ((hclk >= 14200000U) && (hclk < 15000000U))\r
-    {\r
-      /* hclk Clock Range between 14.2-15 MHz */\r
-      UsbTrd = 0xFU;\r
-    }\r
-    else if ((hclk >= 15000000U) && (hclk < 16000000U))\r
-    {\r
-      /* hclk Clock Range between 15-16 MHz */\r
-      UsbTrd = 0xEU;\r
-    }\r
-    else if ((hclk >= 16000000U) && (hclk < 17200000U))\r
-    {\r
-      /* hclk Clock Range between 16-17.2 MHz */\r
-      UsbTrd = 0xDU;\r
-    }\r
-    else if ((hclk >= 17200000U) && (hclk < 18500000U))\r
-    {\r
-      /* hclk Clock Range between 17.2-18.5 MHz */\r
-      UsbTrd = 0xCU;\r
-    }\r
-    else if ((hclk >= 18500000U) && (hclk < 20000000U))\r
-    {\r
-      /* hclk Clock Range between 18.5-20 MHz */\r
-      UsbTrd = 0xBU;\r
-    }\r
-    else if ((hclk >= 20000000U) && (hclk < 21800000U))\r
-    {\r
-      /* hclk Clock Range between 20-21.8 MHz */\r
-      UsbTrd = 0xAU;\r
-    }\r
-    else if ((hclk >= 21800000U) && (hclk < 24000000U))\r
-    {\r
-      /* hclk Clock Range between 21.8-24 MHz */\r
-      UsbTrd = 0x9U;\r
-    }\r
-    else if ((hclk >= 24000000U) && (hclk < 27700000U))\r
-    {\r
-      /* hclk Clock Range between 24-27.7 MHz */\r
-      UsbTrd = 0x8U;\r
-    }\r
-    else if ((hclk >= 27700000U) && (hclk < 32000000U))\r
-    {\r
-      /* hclk Clock Range between 27.7-32 MHz */\r
-      UsbTrd = 0x7U;\r
-    }\r
-    else /* if(hclk >= 32000000) */\r
-    {\r
-      /* hclk Clock Range between 32-200 MHz */\r
-      UsbTrd = 0x6U;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    UsbTrd = USBD_DEFAULT_TRDT_VALUE;\r
-  }\r
-\r
-  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\r
-  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_EnableGlobalInt\r
-  *         Enables the controller's Global Int in the AHB Config reg\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DisableGlobalInt\r
-  *         Disable the controller's Global Int in the AHB Config reg\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_SetCurrentMode : Set functional mode\r
-  * @param  USBx  Selected device\r
-  * @param  mode   current core mode\r
-  *          This parameter can be one of these values:\r
-  *            @arg USB_DEVICE_MODE: Peripheral mode\r
-  *            @arg USB_HOST_MODE: Host mode\r
-  *            @arg USB_DRD_MODE: Dual Role Device mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)\r
-{\r
-  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);\r
-\r
-  if (mode == USB_HOST_MODE)\r
-  {\r
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;\r
-  }\r
-  else if (mode == USB_DEVICE_MODE)\r
-  {\r
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;\r
-  }\r
-  else\r
-  {\r
-    return HAL_ERROR;\r
-  }\r
-  HAL_Delay(50U);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DevInit : Initializes the USB_OTG controller registers\r
-  *         for device mode\r
-  * @param  USBx  Selected device\r
-  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\r
-  *         the configuration information for the specified USBx peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
-{\r
-  HAL_StatusTypeDef ret = HAL_OK;\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t i;\r
-\r
-  for (i = 0U; i < 15U; i++)\r
-  {\r
-    USBx->DIEPTXF[i] = 0U;\r
-  }\r
-\r
-  /* VBUS Sensing setup */\r
-  if (cfg.vbus_sensing_enable == 0U)\r
-  {\r
-    /* Deactivate VBUS Sensing B */\r
-    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;\r
-\r
-    /* B-peripheral session valid override enable */\r
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r
-  }\r
-  else\r
-  {\r
-    /* Enable HW VBUS sensing */\r
-    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
-  }\r
-\r
-  /* Restart the Phy Clock */\r
-  USBx_PCGCCTL = 0U;\r
-\r
-  /* Device mode configuration */\r
-  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r
-\r
-  /* Set Core speed to Full speed mode */\r
-  (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);\r
-\r
-  /* Flush the FIFOs */\r
-  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */\r
-  {\r
-    ret = HAL_ERROR;\r
-  }\r
-\r
-  if (USB_FlushRxFifo(USBx) != HAL_OK)\r
-  {\r
-    ret = HAL_ERROR;\r
-  }\r
-\r
-  /* Clear all pending Device Interrupts */\r
-  USBx_DEVICE->DIEPMSK = 0U;\r
-  USBx_DEVICE->DOEPMSK = 0U;\r
-  USBx_DEVICE->DAINTMSK = 0U;\r
-\r
-  for (i = 0U; i < cfg.dev_endpoints; i++)\r
-  {\r
-    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r
-    {\r
-      if (i == 0U)\r
-      {\r
-        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;\r
-      }\r
-      else\r
-      {\r
-        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      USBx_INEP(i)->DIEPCTL = 0U;\r
-    }\r
-\r
-    USBx_INEP(i)->DIEPTSIZ = 0U;\r
-    USBx_INEP(i)->DIEPINT  = 0xFB7FU;\r
-  }\r
-\r
-  for (i = 0U; i < cfg.dev_endpoints; i++)\r
-  {\r
-    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
-    {\r
-      if (i == 0U)\r
-      {\r
-        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;\r
-      }\r
-      else\r
-      {\r
-        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;\r
-      }\r
-    }\r
-    else\r
-    {\r
-      USBx_OUTEP(i)->DOEPCTL = 0U;\r
-    }\r
-\r
-    USBx_OUTEP(i)->DOEPTSIZ = 0U;\r
-    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;\r
-  }\r
-\r
-  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r
-\r
-  /* Disable all interrupts. */\r
-  USBx->GINTMSK = 0U;\r
-\r
-  /* Clear any pending interrupts */\r
-  USBx->GINTSTS = 0xBFFFFFFFU;\r
-\r
-  /* Enable the common interrupts */\r
-  USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r
-\r
-  /* Enable interrupts matching to the Device mode ONLY */\r
-  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\r
-                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\r
-                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |\r
-                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;\r
-\r
-  if (cfg.Sof_enable != 0U)\r
-  {\r
-    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r
-  }\r
-\r
-  if (cfg.vbus_sensing_enable == 1U)\r
-  {\r
-    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);\r
-  }\r
-\r
-  return ret;\r
-}\r
-\r
-/**\r
-  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO\r
-  * @param  USBx  Selected device\r
-  * @param  num  FIFO number\r
-  *         This parameter can be a value from 1 to 15\r
-            15 means Flush all Tx FIFOs\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)\r
-{\r
-  uint32_t count = 0U;\r
-\r
-  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));\r
-\r
-  do\r
-  {\r
-    if (++count > 200000U)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_FlushRxFifo : Flush Rx FIFO\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t count = 0;\r
-\r
-  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r
-\r
-  do\r
-  {\r
-    if (++count > 200000U)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register\r
-  *         depending the PHY type and the enumeration speed of the device.\r
-  * @param  USBx  Selected device\r
-  * @param  speed  device speed\r
-  *          This parameter can be one of these values:\r
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r
-  * @retval  Hal status\r
-  */\r
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  USBx_DEVICE->DCFG |= speed;\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_GetDevSpeed  Return the Dev Speed\r
-  * @param  USBx  Selected device\r
-  * @retval speed  device speed\r
-  *          This parameter can be one of these values:\r
-  *            @arg PCD_SPEED_FULL: Full speed mode\r
-  */\r
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint8_t speed;\r
-  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;\r
-\r
-  if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||\r
-      (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))\r
-  {\r
-    speed = USBD_FS_SPEED;\r
-  }\r
-  else\r
-  {\r
-    speed = 0xFU;\r
-  }\r
-\r
-  return speed;\r
-}\r
-\r
-/**\r
-  * @brief  Activate and configure an endpoint\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-\r
-  if (ep->is_in == 1U)\r
-  {\r
-    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\r
-\r
-    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)\r
-    {\r
-      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r
-                                   ((uint32_t)ep->type << 18) | (epnum << 22) |\r
-                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
-                                   USB_OTG_DIEPCTL_USBAEP;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\r
-\r
-    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r
-    {\r
-      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r
-                                    ((uint32_t)ep->type << 18) |\r
-                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
-                                    USB_OTG_DOEPCTL_USBAEP;\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Activate and configure a dedicated endpoint\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-\r
-  /* Read DEPCTLn register */\r
-  if (ep->is_in == 1U)\r
-  {\r
-    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)\r
-    {\r
-      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r
-                                   ((uint32_t)ep->type << 18) | (epnum << 22) |\r
-                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
-                                   USB_OTG_DIEPCTL_USBAEP;\r
-    }\r
-\r
-    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\r
-  }\r
-  else\r
-  {\r
-    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r
-    {\r
-      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r
-                                    ((uint32_t)ep->type << 18) | (epnum << 22) |\r
-                                    USB_OTG_DOEPCTL_USBAEP;\r
-    }\r
-\r
-    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  De-activate and de-initialize an endpoint\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-\r
-  /* Read DEPCTLn register */\r
-  if (ep->is_in == 1U)\r
-  {\r
-    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
-    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
-    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |\r
-                                   USB_OTG_DIEPCTL_MPSIZ |\r
-                                   USB_OTG_DIEPCTL_TXFNUM |\r
-                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
-                                   USB_OTG_DIEPCTL_EPTYP);\r
-  }\r
-  else\r
-  {\r
-    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
-    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
-    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |\r
-                                    USB_OTG_DOEPCTL_MPSIZ |\r
-                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |\r
-                                    USB_OTG_DOEPCTL_EPTYP);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  De-activate and de-initialize a dedicated endpoint\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-\r
-  /* Read DEPCTLn register */\r
-  if (ep->is_in == 1U)\r
-  {\r
-    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r
-    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
-  }\r
-  else\r
-  {\r
-    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;\r
-    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-  uint16_t pktcnt;\r
-\r
-  /* IN endpoint */\r
-  if (ep->is_in == 1U)\r
-  {\r
-    /* Zero Length Packet? */\r
-    if (ep->xfer_len == 0U)\r
-    {\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
-    }\r
-    else\r
-    {\r
-      /* Program the transfer size and packet count\r
-      * as follows: xfersize = N * maxpacket +\r
-      * short_packet pktcnt = N + (short_packet\r
-      * exist ? 1 : 0)\r
-      */\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));\r
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r
-\r
-      if (ep->type == EP_TYPE_ISOC)\r
-      {\r
-        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);\r
-        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));\r
-      }\r
-    }\r
-    /* EP enable, IN data in FIFO */\r
-    USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
-\r
-    if (ep->type != EP_TYPE_ISOC)\r
-    {\r
-      /* Enable the Tx FIFO Empty Interrupt for this EP */\r
-      if (ep->xfer_len > 0U)\r
-      {\r
-        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r
-      {\r
-        USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r
-      }\r
-      else\r
-      {\r
-        USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r
-      }\r
-\r
-      (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len);\r
-    }\r
-  }\r
-  else /* OUT endpoint */\r
-  {\r
-    /* Program the transfer size and packet count as follows:\r
-    * pktcnt = N\r
-    * xfersize = N * maxpacket\r
-    */\r
-    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r
-    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r
-\r
-    if (ep->xfer_len == 0U)\r
-    {\r
-      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r
-      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
-    }\r
-    else\r
-    {\r
-      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);\r
-      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);\r
-      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);\r
-    }\r
-\r
-    if (ep->type == EP_TYPE_ISOC)\r
-    {\r
-      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r
-      {\r
-        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r
-      }\r
-      else\r
-      {\r
-        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r
-      }\r
-    }\r
-    /* EP enable */\r
-    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-\r
-  /* IN endpoint */\r
-  if (ep->is_in == 1U)\r
-  {\r
-    /* Zero Length Packet? */\r
-    if (ep->xfer_len == 0U)\r
-    {\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
-    }\r
-    else\r
-    {\r
-      /* Program the transfer size and packet count\r
-      * as follows: xfersize = N * maxpacket +\r
-      * short_packet pktcnt = N + (short_packet\r
-      * exist ? 1 : 0)\r
-      */\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
-\r
-      if (ep->xfer_len > ep->maxpacket)\r
-      {\r
-        ep->xfer_len = ep->maxpacket;\r
-      }\r
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r
-    }\r
-\r
-    /* EP enable, IN data in FIFO */\r
-    USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
-\r
-    /* Enable the Tx FIFO Empty Interrupt for this EP */\r
-    if (ep->xfer_len > 0U)\r
-    {\r
-      USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\r
-    }\r
-  }\r
-  else /* OUT endpoint */\r
-  {\r
-    /* Program the transfer size and packet count as follows:\r
-    * pktcnt = N\r
-    * xfersize = N * maxpacket\r
-    */\r
-    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r
-    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r
-\r
-    if (ep->xfer_len > 0U)\r
-    {\r
-      ep->xfer_len = ep->maxpacket;\r
-    }\r
-\r
-    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
-    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));\r
-\r
-    /* EP enable */\r
-    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated\r
-  *         with the EP/channel\r
-  * @param  USBx  Selected device\r
-  * @param  src   pointer to source buffer\r
-  * @param  ch_ep_num  endpoint or host channel number\r
-  * @param  len  Number of bytes to write\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t *pSrc = (uint32_t *)src;\r
-  uint32_t count32b, i;\r
-\r
-  count32b = ((uint32_t)len + 3U) / 4U;\r
-  for (i = 0U; i < count32b; i++)\r
-  {\r
-    USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);\r
-    pSrc++;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadPacket : read a packet from the RX FIFO\r
-  * @param  USBx  Selected device\r
-  * @param  dest  source pointer\r
-  * @param  len  Number of bytes to read\r
-  * @retval pointer to destination buffer\r
-  */\r
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t *pDest = (uint32_t *)dest;\r
-  uint32_t i;\r
-  uint32_t count32b = ((uint32_t)len + 3U) / 4U;\r
-\r
-  for (i = 0U; i < count32b; i++)\r
-  {\r
-    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));\r
-    pDest++;\r
-  }\r
-\r
-  return ((void *)pDest);\r
-}\r
-\r
-/**\r
-  * @brief  USB_EPSetStall : set a stall condition over an EP\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-\r
-  if (ep->is_in == 1U)\r
-  {\r
-    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))\r
-    {\r
-      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);\r
-    }\r
-    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r
-  }\r
-  else\r
-  {\r
-    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))\r
-    {\r
-      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);\r
-    }\r
-    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_EPClearStall : Clear a stall condition over an EP\r
-  * @param  USBx  Selected device\r
-  * @param  ep pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t epnum = (uint32_t)ep->num;\r
-\r
-  if (ep->is_in == 1U)\r
-  {\r
-    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
-    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r
-    {\r
-      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
-    }\r
-  }\r
-  else\r
-  {\r
-    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
-    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r
-    {\r
-      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
-    }\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_StopDevice : Stop the usb device mode\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  HAL_StatusTypeDef ret;\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t i;\r
-\r
-  /* Clear Pending interrupt */\r
-  for (i = 0U; i < 15U; i++)\r
-  {\r
-    USBx_INEP(i)->DIEPINT = 0xFB7FU;\r
-    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r
-  }\r
-\r
-  /* Clear interrupt masks */\r
-  USBx_DEVICE->DIEPMSK  = 0U;\r
-  USBx_DEVICE->DOEPMSK  = 0U;\r
-  USBx_DEVICE->DAINTMSK = 0U;\r
-\r
-  /* Flush the FIFO */\r
-  ret = USB_FlushRxFifo(USBx);\r
-  if (ret != HAL_OK)\r
-  {\r
-    return ret;\r
-  }\r
-\r
-  ret = USB_FlushTxFifo(USBx,  0x10U);\r
-  if (ret != HAL_OK)\r
-  {\r
-    return ret;\r
-  }\r
-\r
-  return ret;\r
-}\r
-\r
-/**\r
-  * @brief  USB_SetDevAddress : Stop the usb device mode\r
-  * @param  USBx  Selected device\r
-  * @param  address  new device address to be assigned\r
-  *          This parameter can be a value from 0 to 255\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);\r
-  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;\r
-  HAL_Delay(3U);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\r
-  HAL_Delay(3U);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadInterrupts: return the global USB interrupt status\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t tmpreg;\r
-\r
-  tmpreg = USBx->GINTSTS;\r
-  tmpreg &= USBx->GINTMSK;\r
-\r
-  return tmpreg;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t tmpreg;\r
-\r
-  tmpreg  = USBx_DEVICE->DAINT;\r
-  tmpreg &= USBx_DEVICE->DAINTMSK;\r
-\r
-  return ((tmpreg & 0xffff0000U) >> 16);\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t tmpreg;\r
-\r
-  tmpreg  = USBx_DEVICE->DAINT;\r
-  tmpreg &= USBx_DEVICE->DAINTMSK;\r
-\r
-  return ((tmpreg & 0xFFFFU));\r
-}\r
-\r
-/**\r
-  * @brief  Returns Device OUT EP Interrupt register\r
-  * @param  USBx  Selected device\r
-  * @param  epnum  endpoint number\r
-  *          This parameter can be a value from 0 to 15\r
-  * @retval Device OUT EP Interrupt register\r
-  */\r
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t tmpreg;\r
-\r
-  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;\r
-  tmpreg &= USBx_DEVICE->DOEPMSK;\r
-\r
-  return tmpreg;\r
-}\r
-\r
-/**\r
-  * @brief  Returns Device IN EP Interrupt register\r
-  * @param  USBx  Selected device\r
-  * @param  epnum  endpoint number\r
-  *          This parameter can be a value from 0 to 15\r
-  * @retval Device IN EP Interrupt register\r
-  */\r
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t tmpreg, msk, emp;\r
-\r
-  msk = USBx_DEVICE->DIEPMSK;\r
-  emp = USBx_DEVICE->DIEPEMPMSK;\r
-  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;\r
-  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;\r
-\r
-  return tmpreg;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ClearInterrupts: clear a USB interrupt\r
-  * @param  USBx  Selected device\r
-  * @param  interrupt  interrupt flag\r
-  * @retval None\r
-  */\r
-void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r
-{\r
-  USBx->GINTSTS |= interrupt;\r
-}\r
-\r
-/**\r
-  * @brief  Returns USB core mode\r
-  * @param  USBx  Selected device\r
-  * @retval return core mode : Host or Device\r
-  *          This parameter can be one of these values:\r
-  *           0 : Host\r
-  *           1 : Device\r
-  */\r
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  return ((USBx->GINTSTS) & 0x1U);\r
-}\r
-\r
-/**\r
-  * @brief  Activate EP0 for Setup transactions\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  /* Set the MPS of the IN EP based on the enumeration speed */\r
-  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r
-\r
-  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
-  {\r
-    USBx_INEP(0U)->DIEPCTL |= 3U;\r
-  }\r
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Prepare the EP0 to start the first control setup\r
-  * @param  USBx  Selected device\r
-  * @param  psetup  pointer to setup packet\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)\r
-{\r
-  UNUSED(psetup);\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\r
-\r
-  if (gSNPSiD > USB_OTG_CORE_ID_300A)\r
-  {\r
-    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
-    {\r
-      return HAL_OK;\r
-    }\r
-  }\r
-\r
-  USBx_OUTEP(0U)->DOEPTSIZ = 0U;\r
-  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
-  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);\r
-  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Reset the USB Core (needed after USB clock settings change)\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t count = 0U;\r
-\r
-  /* Wait for AHB master IDLE state. */\r
-  do\r
-  {\r
-    if (++count > 200000U)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);\r
-\r
-  /* Core Soft Reset */\r
-  count = 0U;\r
-  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r
-\r
-  do\r
-  {\r
-    if (++count > 200000U)\r
-    {\r
-      return HAL_TIMEOUT;\r
-    }\r
-  }\r
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_HostInit : Initializes the USB OTG controller registers\r
-  *         for Host mode\r
-  * @param  USBx  Selected device\r
-  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\r
-  *         the configuration information for the specified USBx peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t i;\r
-\r
-  /* Restart the Phy Clock */\r
-  USBx_PCGCCTL = 0U;\r
-\r
-  /* Disable VBUS sensing */\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);\r
-\r
-  /* Disable Battery chargin detector */\r
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);\r
-\r
-  /* Set default Max speed support */\r
-  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);\r
-\r
-  /* Make sure the FIFOs are flushed. */\r
-  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */\r
-  (void)USB_FlushRxFifo(USBx);\r
-\r
-  /* Clear all pending HC Interrupts */\r
-  for (i = 0U; i < cfg.Host_channels; i++)\r
-  {\r
-    USBx_HC(i)->HCINT = 0xFFFFFFFFU;\r
-    USBx_HC(i)->HCINTMSK = 0U;\r
-  }\r
-\r
-  /* Enable VBUS driving */\r
-  (void)USB_DriveVbus(USBx, 1U);\r
-\r
-  HAL_Delay(200U);\r
-\r
-  /* Disable all interrupts. */\r
-  USBx->GINTMSK = 0U;\r
-\r
-  /* Clear any pending interrupts */\r
-  USBx->GINTSTS = 0xFFFFFFFFU;\r
-\r
-  /* set Rx FIFO size */\r
-  USBx->GRXFSIZ  = 0x80U;\r
-  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);\r
-  USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);\r
-  /* Enable the common interrupts */\r
-  USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r
-\r
-  /* Enable interrupts matching to the Host mode ONLY */\r
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \\r
-                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \\r
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the\r
-  *         HCFG register on the PHY type and set the right frame interval\r
-  * @param  USBx  Selected device\r
-  * @param  freq  clock frequency\r
-  *          This parameter can be one of these values:\r
-  *           HCFG_48_MHZ : Full Speed 48 MHz Clock\r
-  *           HCFG_6_MHZ : Low Speed 6 MHz Clock\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r
-  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;\r
-\r
-  if (freq == HCFG_48_MHZ)\r
-  {\r
-    USBx_HOST->HFIR = 48000U;\r
-  }\r
-  else if (freq == HCFG_6_MHZ)\r
-  {\r
-    USBx_HOST->HFIR = 6000U;\r
-  }\r
-  else\r
-  {\r
-    /* ... */\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-* @brief  USB_OTG_ResetPort : Reset Host Port\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  * @note (1)The application must wait at least 10 ms\r
-  *   before clearing the reset bit.\r
-  */\r
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  __IO uint32_t hprt0 = 0U;\r
-\r
-  hprt0 = USBx_HPRT0;\r
-\r
-  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r
-             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r
-\r
-  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);\r
-  HAL_Delay(100U);                                 /* See Note #1 */\r
-  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);\r
-  HAL_Delay(10U);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DriveVbus : activate or de-activate vbus\r
-  * @param  state  VBUS state\r
-  *          This parameter can be one of these values:\r
-  *           0 : VBUS Active\r
-  *           1 : VBUS Inactive\r
-  * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  __IO uint32_t hprt0 = 0U;\r
-\r
-  hprt0 = USBx_HPRT0;\r
-\r
-  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r
-             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r
-\r
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))\r
-  {\r
-    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);\r
-  }\r
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))\r
-  {\r
-    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);\r
-  }\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Return Host Core speed\r
-  * @param  USBx  Selected device\r
-  * @retval speed : Host speed\r
-  *          This parameter can be one of these values:\r
-  *            @arg HCD_SPEED_FULL: Full speed mode\r
-  *            @arg HCD_SPEED_LOW: Low speed mode\r
-  */\r
-uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  __IO uint32_t hprt0 = 0U;\r
-\r
-  hprt0 = USBx_HPRT0;\r
-  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r
-}\r
-\r
-/**\r
-  * @brief  Return Host Current Frame number\r
-  * @param  USBx  Selected device\r
-  * @retval current frame number\r
-*/\r
-uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r
-}\r
-\r
-/**\r
-  * @brief  Initialize a host channel\r
-  * @param  USBx  Selected device\r
-  * @param  ch_num  Channel number\r
-  *         This parameter can be a value from 1 to 15\r
-  * @param  epnum  Endpoint number\r
-  *          This parameter can be a value from 1 to 15\r
-  * @param  dev_address  Current device address\r
-  *          This parameter can be a value from 0 to 255\r
-  * @param  speed  Current device speed\r
-  *          This parameter can be one of these values:\r
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r
-  * @param  ep_type  Endpoint Type\r
-  *          This parameter can be one of these values:\r
-  *            @arg EP_TYPE_CTRL: Control type\r
-  *            @arg EP_TYPE_ISOC: Isochronous type\r
-  *            @arg EP_TYPE_BULK: Bulk type\r
-  *            @arg EP_TYPE_INTR: Interrupt type\r
-  * @param  mps  Max Packet Size\r
-  *          This parameter can be a value from 0 to32K\r
-  * @retval HAL state\r
-  */\r
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,\r
-                              uint8_t ch_num,\r
-                              uint8_t epnum,\r
-                              uint8_t dev_address,\r
-                              uint8_t speed,\r
-                              uint8_t ep_type,\r
-                              uint16_t mps)\r
-{\r
-  HAL_StatusTypeDef ret = HAL_OK;\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t HCcharEpDir, HCcharLowSpeed;\r
-\r
-  /* Clear old interrupt conditions for this host channel. */\r
-  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;\r
-\r
-  /* Enable channel interrupts required for this transfer. */\r
-  switch (ep_type)\r
-  {\r
-    case EP_TYPE_CTRL:\r
-    case EP_TYPE_BULK:\r
-      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r
-                                            USB_OTG_HCINTMSK_STALLM |\r
-                                            USB_OTG_HCINTMSK_TXERRM |\r
-                                            USB_OTG_HCINTMSK_DTERRM |\r
-                                            USB_OTG_HCINTMSK_AHBERR |\r
-                                            USB_OTG_HCINTMSK_NAKM;\r
-\r
-      if ((epnum & 0x80U) == 0x80U)\r
-      {\r
-        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
-      }\r
-      break;\r
-\r
-    case EP_TYPE_INTR:\r
-      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r
-                                            USB_OTG_HCINTMSK_STALLM |\r
-                                            USB_OTG_HCINTMSK_TXERRM |\r
-                                            USB_OTG_HCINTMSK_DTERRM |\r
-                                            USB_OTG_HCINTMSK_NAKM   |\r
-                                            USB_OTG_HCINTMSK_AHBERR |\r
-                                            USB_OTG_HCINTMSK_FRMORM;\r
-\r
-      if ((epnum & 0x80U) == 0x80U)\r
-      {\r
-        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
-      }\r
-\r
-      break;\r
-\r
-    case EP_TYPE_ISOC:\r
-      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r
-                                            USB_OTG_HCINTMSK_ACKM   |\r
-                                            USB_OTG_HCINTMSK_AHBERR |\r
-                                            USB_OTG_HCINTMSK_FRMORM;\r
-\r
-      if ((epnum & 0x80U) == 0x80U)\r
-      {\r
-        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);\r
-      }\r
-      break;\r
-\r
-    default:\r
-      ret = HAL_ERROR;\r
-      break;\r
-  }\r
-\r
-  /* Enable the top level host channel interrupt. */\r
-  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);\r
-\r
-  /* Make sure host channel interrupts are enabled. */\r
-  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r
-\r
-  /* Program the HCCHAR register */\r
-  if ((epnum & 0x80U) == 0x80U)\r
-  {\r
-    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;\r
-  }\r
-  else\r
-  {\r
-    HCcharEpDir = 0U;\r
-  }\r
-\r
-  if (speed == HPRT0_PRTSPD_LOW_SPEED)\r
-  {\r
-    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;\r
-  }\r
-  else\r
-  {\r
-    HCcharLowSpeed = 0U;\r
-  }\r
-\r
-  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |\r
-                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |\r
-                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |\r
-                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;\r
-\r
-  if (ep_type == EP_TYPE_INTR)\r
-  {\r
-    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r
-  }\r
-\r
-  return ret;\r
-}\r
-\r
-/**\r
-  * @brief  Start a transfer over a host channel\r
-  * @param  USBx  Selected device\r
-  * @param  hc  pointer to host channel structure\r
-  * @retval HAL state\r
-  */\r
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t ch_num = (uint32_t)hc->ch_num;\r
-  static __IO uint32_t tmpreg = 0U;\r
-  uint8_t  is_oddframe;\r
-  uint16_t len_words;\r
-  uint16_t num_packets;\r
-  uint16_t max_hc_pkt_count = 256U;\r
-\r
-  /* Compute the expected number of packets associated to the transfer */\r
-  if (hc->xfer_len > 0U)\r
-  {\r
-    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);\r
-\r
-    if (num_packets > max_hc_pkt_count)\r
-    {\r
-      num_packets = max_hc_pkt_count;\r
-      hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    num_packets = 1U;\r
-  }\r
-  if (hc->ep_is_in != 0U)\r
-  {\r
-    hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r
-  }\r
-\r
-  /* Initialize the HCTSIZn register */\r
-  USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |\r
-                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r
-                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);\r
-\r
-  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;\r
-  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r
-  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;\r
-\r
-  /* Set host channel enable */\r
-  tmpreg = USBx_HC(ch_num)->HCCHAR;\r
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
-\r
-  /* make sure to set the correct ep direction */\r
-  if (hc->ep_is_in != 0U)\r
-  {\r
-    tmpreg |= USB_OTG_HCCHAR_EPDIR;\r
-  }\r
-  else\r
-  {\r
-    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;\r
-  }\r
-  tmpreg |= USB_OTG_HCCHAR_CHENA;\r
-  USBx_HC(ch_num)->HCCHAR = tmpreg;\r
-\r
-    if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))\r
-    {\r
-      switch (hc->ep_type)\r
-      {\r
-        /* Non periodic transfer */\r
-        case EP_TYPE_CTRL:\r
-        case EP_TYPE_BULK:\r
-\r
-          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r
-\r
-          /* check if there is enough space in FIFO space */\r
-          if (len_words > (USBx->HNPTXSTS & 0xFFFFU))\r
-          {\r
-            /* need to process data in nptxfempty interrupt */\r
-            USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r
-          }\r
-          break;\r
-\r
-        /* Periodic transfer */\r
-        case EP_TYPE_INTR:\r
-        case EP_TYPE_ISOC:\r
-          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r
-          /* check if there is enough space in FIFO space */\r
-          if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */\r
-          {\r
-            /* need to process data in ptxfempty interrupt */\r
-            USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;\r
-          }\r
-          break;\r
-\r
-        default:\r
-          break;\r
-      }\r
-\r
-      /* Write packet into the Tx FIFO. */\r
-      (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len);\r
-    }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Read all host channel interrupts status\r
-  * @param  USBx  Selected device\r
-  * @retval HAL state\r
-  */\r
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  return ((USBx_HOST->HAINT) & 0xFFFFU);\r
-}\r
-\r
-/**\r
-  * @brief  Halt a host channel\r
-  * @param  USBx  Selected device\r
-  * @param  hc_num  Host Channel number\r
-  *         This parameter can be a value from 1 to 15\r
-  * @retval HAL state\r
-  */\r
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t hcnum = (uint32_t)hc_num;\r
-  uint32_t count = 0U;\r
-  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;\r
-\r
-  /* Check for space in the request queue to issue the halt. */\r
-  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))\r
-  {\r
-    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
-\r
-    if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)\r
-    {\r
-      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
-      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
-      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
-      do\r
-      {\r
-        if (++count > 1000U)\r
-        {\r
-          break;\r
-        }\r
-      }\r
-      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
-    }\r
-    else\r
-    {\r
-      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
-    }\r
-  }\r
-  else\r
-  {\r
-    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
-\r
-    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)\r
-    {\r
-      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
-      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
-      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
-      do\r
-      {\r
-        if (++count > 1000U)\r
-        {\r
-          break;\r
-        }\r
-      }\r
-      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
-    }\r
-    else\r
-    {\r
-      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
-    }\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Initiate Do Ping protocol\r
-  * @param  USBx  Selected device\r
-  * @param  hc_num  Host Channel number\r
-  *         This parameter can be a value from 1 to 15\r
-  * @retval HAL state\r
-  */\r
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t chnum = (uint32_t)ch_num;\r
-  uint32_t num_packets = 1U;\r
-  uint32_t tmpreg;\r
-\r
-  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r
-                           USB_OTG_HCTSIZ_DOPING;\r
-\r
-  /* Set host channel enable */\r
-  tmpreg = USBx_HC(chnum)->HCCHAR;\r
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
-  tmpreg |= USB_OTG_HCCHAR_CHENA;\r
-  USBx_HC(chnum)->HCCHAR = tmpreg;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Stop Host Core\r
-  * @param  USBx  Selected device\r
-  * @retval HAL state\r
-  */\r
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-  uint32_t count = 0U;\r
-  uint32_t value;\r
-  uint32_t i;\r
-\r
-\r
-  (void)USB_DisableGlobalInt(USBx);\r
-\r
-  /* Flush FIFO */\r
-  (void)USB_FlushTxFifo(USBx, 0x10U);\r
-  (void)USB_FlushRxFifo(USBx);\r
-\r
-  /* Flush out any leftover queued requests. */\r
-  for (i = 0U; i <= 15U; i++)\r
-  {\r
-    value = USBx_HC(i)->HCCHAR;\r
-    value |=  USB_OTG_HCCHAR_CHDIS;\r
-    value &= ~USB_OTG_HCCHAR_CHENA;\r
-    value &= ~USB_OTG_HCCHAR_EPDIR;\r
-    USBx_HC(i)->HCCHAR = value;\r
-  }\r
-\r
-  /* Halt all channels to put them into a known state. */\r
-  for (i = 0U; i <= 15U; i++)\r
-  {\r
-    value = USBx_HC(i)->HCCHAR;\r
-    value |= USB_OTG_HCCHAR_CHDIS;\r
-    value |= USB_OTG_HCCHAR_CHENA;\r
-    value &= ~USB_OTG_HCCHAR_EPDIR;\r
-    USBx_HC(i)->HCCHAR = value;\r
-\r
-    do\r
-    {\r
-      if (++count > 1000U)\r
-      {\r
-        break;\r
-      }\r
-    }\r
-    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
-  }\r
-\r
-  /* Clear any pending Host interrupts */\r
-  USBx_HOST->HAINT = 0xFFFFFFFFU;\r
-  USBx->GINTSTS = 0xFFFFFFFFU;\r
-  (void)USB_EnableGlobalInt(USBx);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling\r
-  * @param  USBx Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
-  {\r
-    /* active Remote wakeup signalling */\r
-    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling\r
-  * @param  USBx Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r
-{\r
-  uint32_t USBx_BASE = (uint32_t)USBx;\r
-\r
-  /* active Remote wakeup signalling */\r
-  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\r
-\r
-  return HAL_OK;\r
-}\r
-#endif /* defined (USB_OTG_FS) */\r
-\r
-#if defined (USB)\r
-/**\r
-  * @brief  Initializes the USB Core\r
-  * @param  USBx: USB Instance\r
-  * @param  cfg : pointer to a USB_CfgTypeDef structure that contains\r
-  *         the configuration information for the specified USBx peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(cfg);\r
-\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_EnableGlobalInt\r
-  *         Enables the controller's Global Int in the AHB Config reg\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)\r
-{\r
-  uint16_t winterruptmask;\r
-\r
-  /* Set winterruptmask variable */\r
-  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |\r
-                   USB_CNTR_SUSPM | USB_CNTR_ERRM |\r
-                   USB_CNTR_SOFM | USB_CNTR_ESOFM |\r
-                   USB_CNTR_RESETM | USB_CNTR_L1REQM;\r
-\r
-  /* Set interrupt mask */\r
-  USBx->CNTR |= winterruptmask;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DisableGlobalInt\r
-  *         Disable the controller's Global Int in the AHB Config reg\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)\r
-{\r
-  uint16_t winterruptmask;\r
-\r
-  /* Set winterruptmask variable */\r
-  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |\r
-                   USB_CNTR_SUSPM | USB_CNTR_ERRM |\r
-                   USB_CNTR_SOFM | USB_CNTR_ESOFM |\r
-                   USB_CNTR_RESETM | USB_CNTR_L1REQM;\r
-\r
-  /* Clear interrupt mask */\r
-  USBx->CNTR &= ~winterruptmask;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_SetCurrentMode : Set functional mode\r
-  * @param  USBx : Selected device\r
-  * @param  mode :  current core mode\r
-  *          This parameter can be one of the these values:\r
-  *            @arg USB_DEVICE_MODE: Peripheral mode mode\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(mode);\r
-\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DevInit : Initializes the USB controller registers\r
-  *         for device mode\r
-  * @param  USBx : Selected device\r
-  * @param  cfg  : pointer to a USB_CfgTypeDef structure that contains\r
-  *         the configuration information for the specified USBx peripheral.\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(cfg);\r
-\r
-  /* Init Device */\r
-  /*CNTR_FRES = 1*/\r
-  USBx->CNTR = USB_CNTR_FRES;\r
-\r
-  /*CNTR_FRES = 0*/\r
-  USBx->CNTR = 0;\r
-\r
-  /*Clear pending interrupts*/\r
-  USBx->ISTR = 0;\r
-\r
-  /*Set Btable Address*/\r
-  USBx->BTABLE = BTABLE_ADDRESS;\r
-\r
-  /* Enable USB Device Interrupt mask */\r
-  (void)USB_EnableGlobalInt(USBx);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_SetDevSpeed :Initializes the device speed\r
-  *         depending on the PHY type and the enumeration speed of the device.\r
-  * @param  USBx  Selected device\r
-  * @param  speed  device speed\r
-  * @retval  Hal status\r
-  */\r
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(speed);\r
-\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_FlushTxFifo : Flush a Tx FIFO\r
-  * @param  USBx : Selected device\r
-  * @param  num : FIFO number\r
-  *         This parameter can be a value from 1 to 15\r
-            15 means Flush all Tx FIFOs\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(num);\r
-\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_FlushRxFifo : Flush Rx FIFO\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  Activate and configure an endpoint\r
-  * @param  USBx : Selected device\r
-  * @param  ep: pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
-{\r
-  HAL_StatusTypeDef ret = HAL_OK;\r
-  uint16_t wEpRegVal;\r
-\r
-  wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;\r
-\r
-  /* initialize Endpoint */\r
-  switch (ep->type)\r
-  {\r
-    case EP_TYPE_CTRL:\r
-      wEpRegVal |= USB_EP_CONTROL;\r
-      break;\r
-\r
-    case EP_TYPE_BULK:\r
-      wEpRegVal |= USB_EP_BULK;\r
-      break;\r
-\r
-    case EP_TYPE_INTR:\r
-      wEpRegVal |= USB_EP_INTERRUPT;\r
-      break;\r
-\r
-    case EP_TYPE_ISOC:\r
-      wEpRegVal |= USB_EP_ISOCHRONOUS;\r
-      break;\r
-\r
-    default:\r
-      ret = HAL_ERROR;\r
-      break;\r
-  }\r
-\r
-  PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);\r
-\r
-  PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);\r
-\r
-  if (ep->doublebuffer == 0U)\r
-  {\r
-    if (ep->is_in != 0U)\r
-    {\r
-      /*Set the endpoint Transmit buffer address */\r
-      PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);\r
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
-\r
-      if (ep->type != EP_TYPE_ISOC)\r
-      {\r
-        /* Configure NAK status for the Endpoint */\r
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
-      }\r
-      else\r
-      {\r
-        /* Configure TX Endpoint to disabled state */\r
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      /*Set the endpoint Receive buffer address */\r
-      PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);\r
-      /*Set the endpoint Receive buffer counter*/\r
-      PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);\r
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
-      /* Configure VALID status for the Endpoint*/\r
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
-    }\r
-  }\r
-  /*Double Buffer*/\r
-  else\r
-  {\r
-    /* Set the endpoint as double buffered */\r
-    PCD_SET_EP_DBUF(USBx, ep->num);\r
-    /* Set buffer address for double buffered mode */\r
-    PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);\r
-\r
-    if (ep->is_in == 0U)\r
-    {\r
-      /* Clear the data toggle bits for the endpoint IN/OUT */\r
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
-\r
-      /* Reset value of the data toggle bits for the endpoint out */\r
-      PCD_TX_DTOG(USBx, ep->num);\r
-\r
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
-    }\r
-    else\r
-    {\r
-      /* Clear the data toggle bits for the endpoint IN/OUT */\r
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
-      PCD_RX_DTOG(USBx, ep->num);\r
-\r
-      if (ep->type != EP_TYPE_ISOC)\r
-      {\r
-        /* Configure NAK status for the Endpoint */\r
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
-      }\r
-      else\r
-      {\r
-        /* Configure TX Endpoint to disabled state */\r
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
-      }\r
-\r
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
-    }\r
-  }\r
-\r
-  return ret;\r
-}\r
-\r
-/**\r
-  * @brief  De-activate and de-initialize an endpoint\r
-  * @param  USBx : Selected device\r
-  * @param  ep: pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
-{\r
-  if (ep->doublebuffer == 0U)\r
-  {\r
-    if (ep->is_in != 0U)\r
-    {\r
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
-      /* Configure DISABLE status for the Endpoint*/\r
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
-    }\r
-    else\r
-    {\r
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
-      /* Configure DISABLE status for the Endpoint*/\r
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
-    }\r
-  }\r
-  /*Double Buffer*/\r
-  else\r
-  {\r
-    if (ep->is_in == 0U)\r
-    {\r
-      /* Clear the data toggle bits for the endpoint IN/OUT*/\r
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
-\r
-      /* Reset value of the data toggle bits for the endpoint out*/\r
-      PCD_TX_DTOG(USBx, ep->num);\r
-\r
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
-    }\r
-    else\r
-    {\r
-      /* Clear the data toggle bits for the endpoint IN/OUT*/\r
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
-      PCD_RX_DTOG(USBx, ep->num);\r
-      /* Configure DISABLE status for the Endpoint*/\r
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
-    }\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP\r
-  * @param  USBx : Selected device\r
-  * @param  ep: pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
-{\r
-  uint16_t pmabuffer;\r
-  uint32_t len;\r
-\r
-  /* IN endpoint */\r
-  if (ep->is_in == 1U)\r
-  {\r
-    /*Multi packet transfer*/\r
-    if (ep->xfer_len > ep->maxpacket)\r
-    {\r
-      len = ep->maxpacket;\r
-      ep->xfer_len -= len;\r
-    }\r
-    else\r
-    {\r
-      len = ep->xfer_len;\r
-      ep->xfer_len = 0U;\r
-    }\r
-\r
-    /* configure and validate Tx endpoint */\r
-    if (ep->doublebuffer == 0U)\r
-    {\r
-      USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);\r
-      PCD_SET_EP_TX_CNT(USBx, ep->num, len);\r
-    }\r
-    else\r
-    {\r
-      /* Write the data to the USB endpoint */\r
-      if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)\r
-      {\r
-        /* Set the Double buffer counter for pmabuffer1 */\r
-        PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);\r
-        pmabuffer = ep->pmaaddr1;\r
-      }\r
-      else\r
-      {\r
-        /* Set the Double buffer counter for pmabuffer0 */\r
-        PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);\r
-        pmabuffer = ep->pmaaddr0;\r
-      }\r
-      USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);\r
-      PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);\r
-    }\r
-\r
-    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);\r
-  }\r
-  else /* OUT endpoint */\r
-  {\r
-    /* Multi packet transfer*/\r
-    if (ep->xfer_len > ep->maxpacket)\r
-    {\r
-      len = ep->maxpacket;\r
-      ep->xfer_len -= len;\r
-    }\r
-    else\r
-    {\r
-      len = ep->xfer_len;\r
-      ep->xfer_len = 0U;\r
-    }\r
-\r
-    /* configure and validate Rx endpoint */\r
-    if (ep->doublebuffer == 0U)\r
-    {\r
-      /*Set RX buffer count*/\r
-      PCD_SET_EP_RX_CNT(USBx, ep->num, len);\r
-    }\r
-    else\r
-    {\r
-      /*Set the Double buffer counter*/\r
-      PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);\r
-    }\r
-\r
-    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated\r
-  *         with the EP/channel\r
-  * @param  USBx : Selected device\r
-  * @param  src :  pointer to source buffer\r
-  * @param  ch_ep_num : endpoint or host channel number\r
-  * @param  len : Number of bytes to write\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(src);\r
-  UNUSED(ch_ep_num);\r
-  UNUSED(len);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated\r
-  *         with the EP/channel\r
-  * @param  USBx : Selected device\r
-  * @param  dest : destination pointer\r
-  * @param  len : Number of bytes to read\r
-  * @retval pointer to destination buffer\r
-  */\r
-void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(dest);\r
-  UNUSED(len);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return ((void *)NULL);\r
-}\r
-\r
-/**\r
-  * @brief  USB_EPSetStall : set a stall condition over an EP\r
-  * @param  USBx : Selected device\r
-  * @param  ep: pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
-{\r
-  if (ep->is_in != 0U)\r
-  {\r
-    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);\r
-  }\r
-  else\r
-  {\r
-    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_EPClearStall : Clear a stall condition over an EP\r
-  * @param  USBx : Selected device\r
-  * @param  ep: pointer to endpoint structure\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
-{\r
-  if (ep->doublebuffer == 0U)\r
-  {\r
-    if (ep->is_in != 0U)\r
-    {\r
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
-\r
-      if (ep->type != EP_TYPE_ISOC)\r
-      {\r
-        /* Configure NAK status for the Endpoint */\r
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
-      }\r
-    }\r
-    else\r
-    {\r
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
-\r
-      /* Configure VALID status for the Endpoint*/\r
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
-    }\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_StopDevice : Stop the usb device mode\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)\r
-{\r
-  /* disable all interrupts and force USB reset */\r
-  USBx->CNTR = USB_CNTR_FRES;\r
-\r
-  /* clear interrupt status register */\r
-  USBx->ISTR = 0;\r
-\r
-  /* switch-off device */\r
-  USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_SetDevAddress : Stop the usb device mode\r
-  * @param  USBx : Selected device\r
-  * @param  address : new device address to be assigned\r
-  *          This parameter can be a value from 0 to 255\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef  USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)\r
-{\r
-  if (address == 0U)\r
-  {\r
-    /* set device address and enable function */\r
-    USBx->DADDR = USB_DADDR_EF;\r
-  }\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef  USB_DevConnect(USB_TypeDef *USBx)\r
-{\r
-  /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */\r
-  USBx->BCDR |= USB_BCDR_DPPU;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef  USB_DevDisconnect(USB_TypeDef *USBx)\r
-{\r
-  /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */\r
-  USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadInterrupts: return the global USB interrupt status\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-uint32_t  USB_ReadInterrupts(USB_TypeDef *USBx)\r
-{\r
-  uint32_t tmpreg;\r
-\r
-  tmpreg = USBx->ISTR;\r
-  return tmpreg;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return (0);\r
-}\r
-\r
-/**\r
-  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
-  * @param  USBx : Selected device\r
-  * @retval HAL status\r
-  */\r
-uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return (0);\r
-}\r
-\r
-/**\r
-  * @brief  Returns Device OUT EP Interrupt register\r
-  * @param  USBx : Selected device\r
-  * @param  epnum : endpoint number\r
-  *          This parameter can be a value from 0 to 15\r
-  * @retval Device OUT EP Interrupt register\r
-  */\r
-uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(epnum);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return (0);\r
-}\r
-\r
-/**\r
-  * @brief  Returns Device IN EP Interrupt register\r
-  * @param  USBx : Selected device\r
-  * @param  epnum : endpoint number\r
-  *          This parameter can be a value from 0 to 15\r
-  * @retval Device IN EP Interrupt register\r
-  */\r
-uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(epnum);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return (0);\r
-}\r
-\r
-/**\r
-  * @brief  USB_ClearInterrupts: clear a USB interrupt\r
-  * @param  USBx  Selected device\r
-  * @param  interrupt  interrupt flag\r
-  * @retval None\r
-  */\r
-void  USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(interrupt);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-}\r
-\r
-/**\r
-  * @brief  Prepare the EP0 to start the first control setup\r
-  * @param  USBx  Selected device\r
-  * @param  psetup  pointer to setup packet\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)\r
-{\r
-  /* Prevent unused argument(s) compilation warning */\r
-  UNUSED(USBx);\r
-  UNUSED(psetup);\r
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
-              only by USB OTG FS peripheral.\r
-            - This function is added to ensure compatibility across platforms.\r
-   */\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)\r
-{\r
-  USBx->CNTR |= USB_CNTR_RESUME;\r
-\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief  USB_DeActivateRemoteWakeup : de-active remote wakeup signalling\r
-  * @param  USBx  Selected device\r
-  * @retval HAL status\r
-  */\r
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)\r
-{\r
-  USBx->CNTR &= ~(USB_CNTR_RESUME);\r
-  return HAL_OK;\r
-}\r
-\r
-/**\r
-  * @brief Copy a buffer from user memory area to packet memory area (PMA)\r
-  * @param   USBx USB peripheral instance register address.\r
-  * @param   pbUsrBuf pointer to user memory area.\r
-  * @param   wPMABufAddr address into PMA.\r
-  * @param   wNBytes: no. of bytes to be copied.\r
-  * @retval None\r
-  */\r
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)\r
-{\r
-  uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;\r
-  uint32_t BaseAddr = (uint32_t)USBx;\r
-  uint32_t i, temp1, temp2;\r
-  uint16_t *pdwVal;\r
-  uint8_t *pBuf = pbUsrBuf;\r
-\r
-  pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));\r
-\r
-  for (i = n; i != 0U; i--)\r
-  {\r
-    temp1 = (uint16_t) * pBuf;\r
-    pBuf++;\r
-    temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8));\r
-    *pdwVal = (uint16_t)temp2;\r
-    pdwVal++;\r
-\r
-#if PMA_ACCESS > 1U\r
-    pdwVal++;\r
-#endif\r
-\r
-    pBuf++;\r
-  }\r
-}\r
-\r
-/**\r
-  * @brief Copy a buffer from user memory area to packet memory area (PMA)\r
-  * @param   USBx: USB peripheral instance register address.\r
-  * @param   pbUsrBuf pointer to user memory area.\r
-  * @param   wPMABufAddr address into PMA.\r
-  * @param   wNBytes: no. of bytes to be copied.\r
-  * @retval None\r
-  */\r
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)\r
-{\r
-  uint32_t n = (uint32_t)wNBytes >> 1;\r
-  uint32_t BaseAddr = (uint32_t)USBx;\r
-  uint32_t i, temp;\r
-  uint16_t *pdwVal;\r
-  uint8_t *pBuf = pbUsrBuf;\r
-\r
-  pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));\r
-\r
-  for (i = n; i != 0U; i--)\r
-  {\r
-    temp = *pdwVal;\r
-    pdwVal++;\r
-    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);\r
-    pBuf++;\r
-    *pBuf = (uint8_t)((temp >> 8) & 0xFFU);\r
-    pBuf++;\r
-\r
-#if PMA_ACCESS > 1U\r
-    pdwVal++;\r
-#endif\r
-  }\r
-\r
-  if ((wNBytes % 2U) != 0U)\r
-  {\r
-    temp = *pdwVal;\r
-    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);\r
-  }\r
-}\r
-#endif /* defined (USB) */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-#endif /* defined (USB) || defined (USB_OTG_FS) */\r
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r